sh: Support IRQ balancing for SH-X3 proto cores, too.

This adds in hardware IRQ auto-distribution support for SH-X3 proto CPUs,
following the SH7786 support.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

diff --git a/arch/sh/kernel/cpu/sh4a/setup-shx3.c b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
index 9158bc5ea38beb9c8df4835563d89fac1a1430dd..04a487445aa6cb6a234fe71befb794e94f714b81 100644 (file)
--- a/arch/sh/kernel/cpu/sh4a/setup-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
@@ -1,7 +1,7 @@
 /*
  * SH-X3 Prototype Setup
  *
- *  Copyright (C) 2007 - 2009  Paul Mundt
+ *  Copyright (C) 2007 - 2010  Paul Mundt
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -354,6 +354,10 @@ static struct intc_group groups[] __initdata = {
                   DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11),
 };
 
+#define INT2DISTCR0    0xfe4108a0
+#define INT2DISTCR1    0xfe4108a4
+#define INT2DISTCR2    0xfe4108a8
+
 static struct intc_mask_reg mask_registers[] __initdata = {
        { 0xfe410030, 0xfe410050, 32, /* CnINTMSK0 / CnINTMSKCLR0 */
          { IRQ0, IRQ1, IRQ2, IRQ3 } },
@@ -363,20 +367,23 @@ static struct intc_mask_reg mask_registers[] __initdata = {
          { FE1, FE0, 0, ATAPI, VCORE0, VIN1, VIN0, IIC,
            DU, GPIO3, GPIO2, GPIO1, GPIO0, PAM, 0, 0,
            0, 0, 0, 0, 0, 0, 0, 0, /* HUDI bits ignored */
-           0, TMU5, TMU4, TMU3, TMU2, TMU1, TMU0, 0, } },
+           0, TMU5, TMU4, TMU3, TMU2, TMU1, TMU0, 0, },
+           INTC_SMP_BALANCING(INT2DISTCR0) },
        { 0xfe410830, 0xfe410860, 32, /* CnINT2MSK1 / CnINT2MSKCLR1 */
          { 0, 0, 0, 0, DTU3, DTU2, DTU1, DTU0, /* IRM bits ignored */
            PCII9, PCII8, PCII7, PCII6, PCII5, PCII4, PCII3, PCII2,
            PCII1, PCII0, DMAC1_DMAE, DMAC1_DMINT11,
            DMAC1_DMINT10, DMAC1_DMINT9, DMAC1_DMINT8, DMAC1_DMINT7,
            DMAC1_DMINT6, DMAC0_DMAE, DMAC0_DMINT5, DMAC0_DMINT4,
-           DMAC0_DMINT3, DMAC0_DMINT2, DMAC0_DMINT1, DMAC0_DMINT0 } },
+           DMAC0_DMINT3, DMAC0_DMINT2, DMAC0_DMINT1, DMAC0_DMINT0 },
+           INTC_SMP_BALANCING(INT2DISTCR1) },
        { 0xfe410840, 0xfe410870, 32, /* CnINT2MSK2 / CnINT2MSKCLR2 */
          { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
            SCIF3_TXI, SCIF3_BRI, SCIF3_RXI, SCIF3_ERI,
            SCIF2_TXI, SCIF2_BRI, SCIF2_RXI, SCIF2_ERI,
            SCIF1_TXI, SCIF1_BRI, SCIF1_RXI, SCIF1_ERI,
-           SCIF0_TXI, SCIF0_BRI, SCIF0_RXI, SCIF0_ERI } },
+           SCIF0_TXI, SCIF0_BRI, SCIF0_RXI, SCIF0_ERI },
+           INTC_SMP_BALANCING(INT2DISTCR2) },
 };
 
 static struct intc_prio_reg prio_registers[] __initdata = {

diff --git a/drivers/sh/Kconfig b/drivers/sh/Kconfig
index a54de0b9b3dfe3f40c56c983d2ca64ce75cc4335..1dc8b7ae35fb4c51e3564b931b274466ed86706f 100644 (file)
--- a/drivers/sh/Kconfig
+++ b/drivers/sh/Kconfig
@@ -14,7 +14,7 @@ config INTC_USERIMASK
 
 config INTC_BALANCING
        bool "Hardware IRQ balancing support"
-       depends on SMP && SUPERH && CPU_SUBTYPE_SH7786
+       depends on SMP && SUPERH && CPU_SHX3
        help
          This enables support for IRQ auto-distribution mode on SH-X3
          SMP parts. All of the balancing and CPU wakeup decisions are