]> bbs.cooldavid.org Git - net-next-2.6.git/commitdiff
sh: mach-sdk7786: Add support for the FPGA SRAM.
authorPaul Mundt <lethal@linux-sh.org>
Thu, 14 Oct 2010 17:13:04 +0000 (02:13 +0900)
committerPaul Mundt <lethal@linux-sh.org>
Thu, 14 Oct 2010 17:13:04 +0000 (02:13 +0900)
This ties in the 2KiB of FPGA SRAM in to the generic SRAM pool.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
arch/sh/boards/Kconfig
arch/sh/boards/mach-sdk7786/Makefile
arch/sh/boards/mach-sdk7786/sram.c [new file with mode: 0644]
arch/sh/include/asm/sizes.h
arch/sh/include/mach-sdk7786/mach/fpga.h

index bb2cb27074e9fd109f7fa2b084374d7a37f0e245..9c94711aa6caee785b152ba7be282b98a6b6d285 100644 (file)
@@ -156,6 +156,7 @@ config SH_SDK7786
        select SYS_SUPPORTS_PCI
        select NO_IOPORT if !PCI
        select ARCH_WANT_OPTIONAL_GPIOLIB
+       select HAVE_SRAM_POOL
        help
          Select SDK7786 if configuring for a Renesas Technology Europe
          SH7786-65nm board.
index d0f801bd8416b72852985f5b7ba1914dcfe214ab..23ff7d4ac491fc2e47cf334700e3133f01684b9c 100644 (file)
@@ -1,3 +1,4 @@
-obj-y  := setup.o fpga.o irq.o
+obj-y  := fpga.o irq.o setup.o
 
 obj-$(CONFIG_GENERIC_GPIO)     += gpio.o
+obj-$(CONFIG_HAVE_SRAM_POOL)   += sram.o
diff --git a/arch/sh/boards/mach-sdk7786/sram.c b/arch/sh/boards/mach-sdk7786/sram.c
new file mode 100644 (file)
index 0000000..c81c3ab
--- /dev/null
@@ -0,0 +1,72 @@
+/*
+ * SDK7786 FPGA SRAM Support.
+ *
+ * Copyright (C) 2010  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/io.h>
+#include <linux/string.h>
+#include <mach/fpga.h>
+#include <asm/sram.h>
+#include <asm/sizes.h>
+
+static int __init fpga_sram_init(void)
+{
+       unsigned long phys;
+       unsigned int area;
+       void __iomem *vaddr;
+       int ret;
+       u16 data;
+
+       /* Enable FPGA SRAM */
+       data = fpga_read_reg(LCLASR);
+       data |= LCLASR_FRAMEN;
+       fpga_write_reg(data, LCLASR);
+
+       /*
+        * FPGA_SEL determines the area mapping
+        */
+       area = (data & LCLASR_FPGA_SEL_MASK) >> LCLASR_FPGA_SEL_SHIFT;
+       if (unlikely(area == LCLASR_AREA_MASK)) {
+               pr_err("FPGA memory unmapped.\n");
+               return -ENXIO;
+       }
+
+       /*
+        * The memory itself occupies a 2KiB range at the top of the area
+        * immediately below the system registers.
+        */
+       phys = (area << 26) + SZ_64M - SZ_4K;
+
+       /*
+        * The FPGA SRAM resides in translatable physical space, so set
+        * up a mapping prior to inserting it in to the pool.
+        */
+       vaddr = ioremap(phys, SZ_2K);
+       if (unlikely(!vaddr)) {
+               pr_err("Failed remapping FPGA memory.\n");
+               return -ENXIO;
+       }
+
+       pr_info("Adding %dKiB of FPGA memory at 0x%08lx-0x%08lx "
+               "(area %d) to pool.\n",
+               SZ_2K >> 10, phys, phys + SZ_2K - 1, area);
+
+       ret = gen_pool_add(sram_pool, (unsigned long)vaddr, SZ_2K, -1);
+       if (unlikely(ret < 0)) {
+               pr_err("Failed adding memory\n");
+               iounmap(vaddr);
+               return ret;
+       }
+
+       return 0;
+}
+postcore_initcall(fpga_sram_init);
index 3a1fb97770f1f507b3f0d58cba278d2860b9bb7a..0b9fe2d5c36d9d4ac05621d50b8e6725ce6f3d13 100644 (file)
@@ -32,6 +32,7 @@
 #define SZ_512                         0x00000200
 
 #define SZ_1K                           0x00000400
+#define SZ_2K                           0x00000800
 #define SZ_4K                           0x00001000
 #define SZ_8K                           0x00002000
 #define SZ_16K                          0x00004000
index b7d93699b679dfc1ea7b90832e3ef523e95843f0..40f0c2d3690c5a3c6744f2bdff6c4eed8eb1c027 100644 (file)
 
 #define FAER           0x150
 #define USRGPIR                0x160
+
 /* 0x170 reserved */
-#define LCLASR         0x180
+
+#define LCLASR                 0x180
+#define  LCLASR_FRAMEN         BIT(15)
+
+#define  LCLASR_FPGA_SEL_SHIFT 12
+#define  LCLASR_NAND_SEL_SHIFT 8
+#define  LCLASR_NORB_SEL_SHIFT 4
+#define  LCLASR_NORA_SEL_SHIFT 0
+
+#define  LCLASR_AREA_MASK      0x7
+
+#define  LCLASR_FPGA_SEL_MASK  (LCLASR_AREA_MASK << LCLASR_FPGA_SEL_SHIFT)
+#define  LCLASR_NAND_SEL_MASK  (LCLASR_AREA_MASK << LCLASR_NAND_SEL_SHIFT)
+#define  LCLASR_NORB_SEL_MASK  (LCLASR_AREA_MASK << LCLASR_NORB_SEL_SHIFT)
+#define  LCLASR_NORA_SEL_MASK  (LCLASR_AREA_MASK << LCLASR_NORA_SEL_SHIFT)
 
 #define SBCR           0x190
 #define  SCBR_I2CMEN   BIT(0)  /* FPGA I2C master enable */