drm/i915: Add CLKCFG register definition

The CLKCFG register holds information about the GMCH plls and input clock
values.

Signed-off-by: Keith Packard <keithp@keithp.com>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f6237a0b1133c0429cc27a2a0c26282bd6051b8c..544d5677a2fa28aa2701e0b7621ab963bd0779f2 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -569,6 +569,19 @@
 #define C0DRB3                 0x10206
 #define C1DRB3                 0x10606
 
+/* Clocking configuration register */
+#define CLKCFG                 0x10c00
+#define CLKCFG_FSB_400                                 (0 << 0)        /* hrawclk 100 */
+#define CLKCFG_FSB_533                                 (1 << 0)        /* hrawclk 133 */
+#define CLKCFG_FSB_667                                 (3 << 0)        /* hrawclk 166 */
+#define CLKCFG_FSB_800                                 (2 << 0)        /* hrawclk 200 */
+#define CLKCFG_FSB_1067                                        (6 << 0)        /* hrawclk 266 */
+#define CLKCFG_FSB_1333                                        (7 << 0)        /* hrawclk 333 */
+/* this is a guess, could be 5 as well */
+#define CLKCFG_FSB_1600                                        (4 << 0)        /* hrawclk 400 */
+#define CLKCFG_FSB_1600_ALT                            (5 << 0)        /* hrawclk 400 */
+#define CLKCFG_FSB_MASK                                        (7 << 0)
+ 
 /** GM965 GM45 render standby register */
 #define MCHBAR_RENDER_STANDBY  0x111B8