ARM: 5995/1: ARM: Add L2x0 outer_sync() support (3/4)

The L2x0 cache controllers need to explicitly drain their write buffer
even for Normal Noncacheable memory accesses.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 88a24de55aaf5a6b840a68a469b24fd3d58c2a5e..55a2a00db77fec71f866172d68af19360dde0eaa 100644 (file)
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -763,6 +763,7 @@ config CACHE_L2X0
                   REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || ARCH_NOMADIK || ARCH_OMAP4
        default y
        select OUTER_CACHE
+       select OUTER_CACHE_SYNC
        help
          This option enables the L2x0 PrimeCell.
 

diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 07334632d3e2761293e1880b2486a2e85c3437e4..21ad68ba22bab8a3acd859cbba4df0fc36c93b72 100644 (file)
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -93,6 +93,15 @@ static inline void l2x0_flush_line(unsigned long addr)
 }
 #endif
 
+static void l2x0_cache_sync(void)
+{
+       unsigned long flags;
+
+       spin_lock_irqsave(&l2x0_lock, flags);
+       cache_sync();
+       spin_unlock_irqrestore(&l2x0_lock, flags);
+}
+
 static inline void l2x0_inv_all(void)
 {
        unsigned long flags;
@@ -225,6 +234,7 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
        outer_cache.inv_range = l2x0_inv_range;
        outer_cache.clean_range = l2x0_clean_range;
        outer_cache.flush_range = l2x0_flush_range;
+       outer_cache.sync = l2x0_cache_sync;
 
        printk(KERN_INFO "L2X0 cache controller enabled\n");
 }