drivers/video/sh_mobile_hdmi.c

   1 /*
   2  * SH-Mobile High-Definition Multimedia Interface (HDMI) driver
   3  * for SLISHDMI13T and SLIPHDMIT IP cores
   4  *
   5  * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/console.h>
  14 #include <linux/delay.h>
  15 #include <linux/err.h>
  16 #include <linux/init.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/slab.h>
  23 #include <linux/types.h>
  24 #include <linux/workqueue.h>
  25 #include <sound/soc-dapm.h>
  26 #include <sound/initval.h>
  27
  28 #include <video/sh_mobile_hdmi.h>
  29 #include <video/sh_mobile_lcdc.h>
  30
  31 #define HDMI_SYSTEM_CTRL                        0x00 /* System control */
  32 #define HDMI_L_R_DATA_SWAP_CTRL_RPKT            0x01 /* L/R data swap control,
  33                                                         bits 19..16 of 20-bit N for Audio Clock Regeneration packet */
  34 #define HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8       0x02 /* bits 15..8 of 20-bit N for Audio Clock Regeneration packet */
  35 #define HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0        0x03 /* bits 7..0 of 20-bit N for Audio Clock Regeneration packet */
  36 #define HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS          0x04 /* SPDIF audio sampling frequency,
  37                                                         bits 19..16 of Internal CTS */
  38 #define HDMI_INTERNAL_CTS_15_8                  0x05 /* bits 15..8 of Internal CTS */
  39 #define HDMI_INTERNAL_CTS_7_0                   0x06 /* bits 7..0 of Internal CTS */
  40 #define HDMI_EXTERNAL_CTS_19_16                 0x07 /* External CTS */
  41 #define HDMI_EXTERNAL_CTS_15_8                  0x08 /* External CTS */
  42 #define HDMI_EXTERNAL_CTS_7_0                   0x09 /* External CTS */
  43 #define HDMI_AUDIO_SETTING_1                    0x0A /* Audio setting.1 */
  44 #define HDMI_AUDIO_SETTING_2                    0x0B /* Audio setting.2 */
  45 #define HDMI_I2S_AUDIO_SET                      0x0C /* I2S audio setting */
  46 #define HDMI_DSD_AUDIO_SET                      0x0D /* DSD audio setting */
  47 #define HDMI_DEBUG_MONITOR_1                    0x0E /* Debug monitor.1 */
  48 #define HDMI_DEBUG_MONITOR_2                    0x0F /* Debug monitor.2 */
  49 #define HDMI_I2S_INPUT_PIN_SWAP                 0x10 /* I2S input pin swap */
  50 #define HDMI_AUDIO_STATUS_BITS_SETTING_1        0x11 /* Audio status bits setting.1 */
  51 #define HDMI_AUDIO_STATUS_BITS_SETTING_2        0x12 /* Audio status bits setting.2 */
  52 #define HDMI_CATEGORY_CODE                      0x13 /* Category code */
  53 #define HDMI_SOURCE_NUM_AUDIO_WORD_LEN          0x14 /* Source number/Audio word length */
  54 #define HDMI_AUDIO_VIDEO_SETTING_1              0x15 /* Audio/Video setting.1 */
  55 #define HDMI_VIDEO_SETTING_1                    0x16 /* Video setting.1 */
  56 #define HDMI_DEEP_COLOR_MODES                   0x17 /* Deep Color Modes */
  57
  58 /* 12 16- and 10-bit Color space conversion parameters: 0x18..0x2f */
  59 #define HDMI_COLOR_SPACE_CONVERSION_PARAMETERS  0x18
  60
  61 #define HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS      0x30 /* External video parameter settings */
  62 #define HDMI_EXTERNAL_H_TOTAL_7_0               0x31 /* External horizontal total (LSB) */
  63 #define HDMI_EXTERNAL_H_TOTAL_11_8              0x32 /* External horizontal total (MSB) */
  64 #define HDMI_EXTERNAL_H_BLANK_7_0               0x33 /* External horizontal blank (LSB) */
  65 #define HDMI_EXTERNAL_H_BLANK_9_8               0x34 /* External horizontal blank (MSB) */
  66 #define HDMI_EXTERNAL_H_DELAY_7_0               0x35 /* External horizontal delay (LSB) */
  67 #define HDMI_EXTERNAL_H_DELAY_9_8               0x36 /* External horizontal delay (MSB) */
  68 #define HDMI_EXTERNAL_H_DURATION_7_0            0x37 /* External horizontal duration (LSB) */
  69 #define HDMI_EXTERNAL_H_DURATION_9_8            0x38 /* External horizontal duration (MSB) */
  70 #define HDMI_EXTERNAL_V_TOTAL_7_0               0x39 /* External vertical total (LSB) */
  71 #define HDMI_EXTERNAL_V_TOTAL_9_8               0x3A /* External vertical total (MSB) */
  72 #define HDMI_AUDIO_VIDEO_SETTING_2              0x3B /* Audio/Video setting.2 */
  73 #define HDMI_EXTERNAL_V_BLANK                   0x3D /* External vertical blank */
  74 #define HDMI_EXTERNAL_V_DELAY                   0x3E /* External vertical delay */
  75 #define HDMI_EXTERNAL_V_DURATION                0x3F /* External vertical duration */
  76 #define HDMI_CTRL_PKT_MANUAL_SEND_CONTROL       0x40 /* Control packet manual send control */
  77 #define HDMI_CTRL_PKT_AUTO_SEND                 0x41 /* Control packet auto send with VSYNC control */
  78 #define HDMI_AUTO_CHECKSUM_OPTION               0x42 /* Auto checksum option */
  79 #define HDMI_VIDEO_SETTING_2                    0x45 /* Video setting.2 */
  80 #define HDMI_OUTPUT_OPTION                      0x46 /* Output option */
  81 #define HDMI_SLIPHDMIT_PARAM_OPTION             0x51 /* SLIPHDMIT parameter option */
  82 #define HDMI_HSYNC_PMENT_AT_EMB_7_0             0x52 /* HSYNC placement at embedded sync (LSB) */
  83 #define HDMI_HSYNC_PMENT_AT_EMB_15_8            0x53 /* HSYNC placement at embedded sync (MSB) */
  84 #define HDMI_VSYNC_PMENT_AT_EMB_7_0             0x54 /* VSYNC placement at embedded sync (LSB) */
  85 #define HDMI_VSYNC_PMENT_AT_EMB_14_8            0x55 /* VSYNC placement at embedded sync (MSB) */
  86 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_1         0x56 /* SLIPHDMIT parameter settings.1 */
  87 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_2         0x57 /* SLIPHDMIT parameter settings.2 */
  88 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_3         0x58 /* SLIPHDMIT parameter settings.3 */
  89 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_5         0x59 /* SLIPHDMIT parameter settings.5 */
  90 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_6         0x5A /* SLIPHDMIT parameter settings.6 */
  91 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_7         0x5B /* SLIPHDMIT parameter settings.7 */
  92 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_8         0x5C /* SLIPHDMIT parameter settings.8 */
  93 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_9         0x5D /* SLIPHDMIT parameter settings.9 */
  94 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_10        0x5E /* SLIPHDMIT parameter settings.10 */
  95 #define HDMI_CTRL_PKT_BUF_INDEX                 0x5F /* Control packet buffer index */
  96 #define HDMI_CTRL_PKT_BUF_ACCESS_HB0            0x60 /* Control packet data buffer access window - HB0 */
  97 #define HDMI_CTRL_PKT_BUF_ACCESS_HB1            0x61 /* Control packet data buffer access window - HB1 */
  98 #define HDMI_CTRL_PKT_BUF_ACCESS_HB2            0x62 /* Control packet data buffer access window - HB2 */
  99 #define HDMI_CTRL_PKT_BUF_ACCESS_PB0            0x63 /* Control packet data buffer access window - PB0 */
 100 #define HDMI_CTRL_PKT_BUF_ACCESS_PB1            0x64 /* Control packet data buffer access window - PB1 */
 101 #define HDMI_CTRL_PKT_BUF_ACCESS_PB2            0x65 /* Control packet data buffer access window - PB2 */
 102 #define HDMI_CTRL_PKT_BUF_ACCESS_PB3            0x66 /* Control packet data buffer access window - PB3 */
 103 #define HDMI_CTRL_PKT_BUF_ACCESS_PB4            0x67 /* Control packet data buffer access window - PB4 */
 104 #define HDMI_CTRL_PKT_BUF_ACCESS_PB5            0x68 /* Control packet data buffer access window - PB5 */
 105 #define HDMI_CTRL_PKT_BUF_ACCESS_PB6            0x69 /* Control packet data buffer access window - PB6 */
 106 #define HDMI_CTRL_PKT_BUF_ACCESS_PB7            0x6A /* Control packet data buffer access window - PB7 */
 107 #define HDMI_CTRL_PKT_BUF_ACCESS_PB8            0x6B /* Control packet data buffer access window - PB8 */
 108 #define HDMI_CTRL_PKT_BUF_ACCESS_PB9            0x6C /* Control packet data buffer access window - PB9 */
 109 #define HDMI_CTRL_PKT_BUF_ACCESS_PB10           0x6D /* Control packet data buffer access window - PB10 */
 110 #define HDMI_CTRL_PKT_BUF_ACCESS_PB11           0x6E /* Control packet data buffer access window - PB11 */
 111 #define HDMI_CTRL_PKT_BUF_ACCESS_PB12           0x6F /* Control packet data buffer access window - PB12 */
 112 #define HDMI_CTRL_PKT_BUF_ACCESS_PB13           0x70 /* Control packet data buffer access window - PB13 */
 113 #define HDMI_CTRL_PKT_BUF_ACCESS_PB14           0x71 /* Control packet data buffer access window - PB14 */
 114 #define HDMI_CTRL_PKT_BUF_ACCESS_PB15           0x72 /* Control packet data buffer access window - PB15 */
 115 #define HDMI_CTRL_PKT_BUF_ACCESS_PB16           0x73 /* Control packet data buffer access window - PB16 */
 116 #define HDMI_CTRL_PKT_BUF_ACCESS_PB17           0x74 /* Control packet data buffer access window - PB17 */
 117 #define HDMI_CTRL_PKT_BUF_ACCESS_PB18           0x75 /* Control packet data buffer access window - PB18 */
 118 #define HDMI_CTRL_PKT_BUF_ACCESS_PB19           0x76 /* Control packet data buffer access window - PB19 */
 119 #define HDMI_CTRL_PKT_BUF_ACCESS_PB20           0x77 /* Control packet data buffer access window - PB20 */
 120 #define HDMI_CTRL_PKT_BUF_ACCESS_PB21           0x78 /* Control packet data buffer access window - PB21 */
 121 #define HDMI_CTRL_PKT_BUF_ACCESS_PB22           0x79 /* Control packet data buffer access window - PB22 */
 122 #define HDMI_CTRL_PKT_BUF_ACCESS_PB23           0x7A /* Control packet data buffer access window - PB23 */
 123 #define HDMI_CTRL_PKT_BUF_ACCESS_PB24           0x7B /* Control packet data buffer access window - PB24 */
 124 #define HDMI_CTRL_PKT_BUF_ACCESS_PB25           0x7C /* Control packet data buffer access window - PB25 */
 125 #define HDMI_CTRL_PKT_BUF_ACCESS_PB26           0x7D /* Control packet data buffer access window - PB26 */
 126 #define HDMI_CTRL_PKT_BUF_ACCESS_PB27           0x7E /* Control packet data buffer access window - PB27 */
 127 #define HDMI_EDID_KSV_FIFO_ACCESS_WINDOW        0x80 /* EDID/KSV FIFO access window */
 128 #define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_7_0       0x81 /* DDC bus access frequency control (LSB) */
 129 #define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_15_8      0x82 /* DDC bus access frequency control (MSB) */
 130 #define HDMI_INTERRUPT_MASK_1                   0x92 /* Interrupt mask.1 */
 131 #define HDMI_INTERRUPT_MASK_2                   0x93 /* Interrupt mask.2 */
 132 #define HDMI_INTERRUPT_STATUS_1                 0x94 /* Interrupt status.1 */
 133 #define HDMI_INTERRUPT_STATUS_2                 0x95 /* Interrupt status.2 */
 134 #define HDMI_INTERRUPT_MASK_3                   0x96 /* Interrupt mask.3 */
 135 #define HDMI_INTERRUPT_MASK_4                   0x97 /* Interrupt mask.4 */
 136 #define HDMI_INTERRUPT_STATUS_3                 0x98 /* Interrupt status.3 */
 137 #define HDMI_INTERRUPT_STATUS_4                 0x99 /* Interrupt status.4 */
 138 #define HDMI_SOFTWARE_HDCP_CONTROL_1            0x9A /* Software HDCP control.1 */
 139 #define HDMI_FRAME_COUNTER                      0x9C /* Frame counter */
 140 #define HDMI_FRAME_COUNTER_FOR_RI_CHECK         0x9D /* Frame counter for Ri check */
 141 #define HDMI_HDCP_CONTROL                       0xAF /* HDCP control */
 142 #define HDMI_RI_FRAME_COUNT_REGISTER            0xB2 /* Ri frame count register */
 143 #define HDMI_DDC_BUS_CONTROL                    0xB7 /* DDC bus control */
 144 #define HDMI_HDCP_STATUS                        0xB8 /* HDCP status */
 145 #define HDMI_SHA0                               0xB9 /* sha0 */
 146 #define HDMI_SHA1                               0xBA /* sha1 */
 147 #define HDMI_SHA2                               0xBB /* sha2 */
 148 #define HDMI_SHA3                               0xBC /* sha3 */
 149 #define HDMI_SHA4                               0xBD /* sha4 */
 150 #define HDMI_BCAPS_READ                         0xBE /* BCAPS read / debug */
 151 #define HDMI_AKSV_BKSV_7_0_MONITOR              0xBF /* AKSV/BKSV[7:0] monitor */
 152 #define HDMI_AKSV_BKSV_15_8_MONITOR             0xC0 /* AKSV/BKSV[15:8] monitor */
 153 #define HDMI_AKSV_BKSV_23_16_MONITOR            0xC1 /* AKSV/BKSV[23:16] monitor */
 154 #define HDMI_AKSV_BKSV_31_24_MONITOR            0xC2 /* AKSV/BKSV[31:24] monitor */
 155 #define HDMI_AKSV_BKSV_39_32_MONITOR            0xC3 /* AKSV/BKSV[39:32] monitor */
 156 #define HDMI_EDID_SEGMENT_POINTER               0xC4 /* EDID segment pointer */
 157 #define HDMI_EDID_WORD_ADDRESS                  0xC5 /* EDID word address */
 158 #define HDMI_EDID_DATA_FIFO_ADDRESS             0xC6 /* EDID data FIFO address */
 159 #define HDMI_NUM_OF_HDMI_DEVICES                0xC7 /* Number of HDMI devices */
 160 #define HDMI_HDCP_ERROR_CODE                    0xC8 /* HDCP error code */
 161 #define HDMI_100MS_TIMER_SET                    0xC9 /* 100ms timer setting */
 162 #define HDMI_5SEC_TIMER_SET                     0xCA /* 5sec timer setting */
 163 #define HDMI_RI_READ_COUNT                      0xCB /* Ri read count */
 164 #define HDMI_AN_SEED                            0xCC /* An seed */
 165 #define HDMI_MAX_NUM_OF_RCIVRS_ALLOWED          0xCD /* Maximum number of receivers allowed */
 166 #define HDMI_HDCP_MEMORY_ACCESS_CONTROL_1       0xCE /* HDCP memory access control.1 */
 167 #define HDMI_HDCP_MEMORY_ACCESS_CONTROL_2       0xCF /* HDCP memory access control.2 */
 168 #define HDMI_HDCP_CONTROL_2                     0xD0 /* HDCP Control 2 */
 169 #define HDMI_HDCP_KEY_MEMORY_CONTROL            0xD2 /* HDCP Key Memory Control */
 170 #define HDMI_COLOR_SPACE_CONV_CONFIG_1          0xD3 /* Color space conversion configuration.1 */
 171 #define HDMI_VIDEO_SETTING_3                    0xD4 /* Video setting.3 */
 172 #define HDMI_RI_7_0                             0xD5 /* Ri[7:0] */
 173 #define HDMI_RI_15_8                            0xD6 /* Ri[15:8] */
 174 #define HDMI_PJ                                 0xD7 /* Pj */
 175 #define HDMI_SHA_RD                             0xD8 /* sha_rd */
 176 #define HDMI_RI_7_0_SAVED                       0xD9 /* Ri[7:0] saved */
 177 #define HDMI_RI_15_8_SAVED                      0xDA /* Ri[15:8] saved */
 178 #define HDMI_PJ_SAVED                           0xDB /* Pj saved */
 179 #define HDMI_NUM_OF_DEVICES                     0xDC /* Number of devices */
 180 #define HDMI_HOT_PLUG_MSENS_STATUS              0xDF /* Hot plug/MSENS status */
 181 #define HDMI_BCAPS_WRITE                        0xE0 /* bcaps */
 182 #define HDMI_BSTAT_7_0                          0xE1 /* bstat[7:0] */
 183 #define HDMI_BSTAT_15_8                         0xE2 /* bstat[15:8] */
 184 #define HDMI_BKSV_7_0                           0xE3 /* bksv[7:0] */
 185 #define HDMI_BKSV_15_8                          0xE4 /* bksv[15:8] */
 186 #define HDMI_BKSV_23_16                         0xE5 /* bksv[23:16] */
 187 #define HDMI_BKSV_31_24                         0xE6 /* bksv[31:24] */
 188 #define HDMI_BKSV_39_32                         0xE7 /* bksv[39:32] */
 189 #define HDMI_AN_7_0                             0xE8 /* An[7:0] */
 190 #define HDMI_AN_15_8                            0xE9 /* An [15:8] */
 191 #define HDMI_AN_23_16                           0xEA /* An [23:16] */
 192 #define HDMI_AN_31_24                           0xEB /* An [31:24] */
 193 #define HDMI_AN_39_32                           0xEC /* An [39:32] */
 194 #define HDMI_AN_47_40                           0xED /* An [47:40] */
 195 #define HDMI_AN_55_48                           0xEE /* An [55:48] */
 196 #define HDMI_AN_63_56                           0xEF /* An [63:56] */
 197 #define HDMI_PRODUCT_ID                         0xF0 /* Product ID */
 198 #define HDMI_REVISION_ID                        0xF1 /* Revision ID */
 199 #define HDMI_TEST_MODE                          0xFE /* Test mode */
 200
 201 enum hotplug_state {
 202         HDMI_HOTPLUG_DISCONNECTED,
 203         HDMI_HOTPLUG_CONNECTED,
 204         HDMI_HOTPLUG_EDID_DONE,
 205 };
 206
 207 struct sh_hdmi {
 208         void __iomem *base;
 209         enum hotplug_state hp_state;
 210         struct clk *hdmi_clk;
 211         struct device *dev;
 212         struct fb_info *info;
 213         struct delayed_work edid_work;
 214         struct fb_var_screeninfo var;
 215 };
 216
 217 static void hdmi_write(struct sh_hdmi *hdmi, u8 data, u8 reg)
 218 {
 219         iowrite8(data, hdmi->base + reg);
 220 }
 221
 222 static u8 hdmi_read(struct sh_hdmi *hdmi, u8 reg)
 223 {
 224         return ioread8(hdmi->base + reg);
 225 }
 226
 227 /*
 228  *      HDMI sound
 229  */
 230 static unsigned int sh_hdmi_snd_read(struct snd_soc_codec *codec,
 231                                      unsigned int reg)
 232 {
 233         struct sh_hdmi *hdmi = snd_soc_codec_get_drvdata(codec);
 234
 235         return hdmi_read(hdmi, reg);
 236 }
 237
 238 static int sh_hdmi_snd_write(struct snd_soc_codec *codec,
 239                              unsigned int reg,
 240                              unsigned int value)
 241 {
 242         struct sh_hdmi *hdmi = snd_soc_codec_get_drvdata(codec);
 243
 244         hdmi_write(hdmi, value, reg);
 245         return 0;
 246 }
 247
 248 static struct snd_soc_dai_driver sh_hdmi_dai = {
 249         .name = "sh_mobile_hdmi-hifi",
 250         .playback = {
 251                 .stream_name = "Playback",
 252                 .channels_min = 2,
 253                 .channels_max = 8,
 254                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100  |
 255                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200  |
 256                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
 257                          SNDRV_PCM_RATE_192000,
 258                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 259         },
 260 };
 261
 262 static int sh_hdmi_snd_probe(struct snd_soc_codec *codec)
 263 {
 264         dev_info(codec->dev, "SH Mobile HDMI Audio Codec");
 265
 266         return 0;
 267 }
 268
 269 static struct snd_soc_codec_driver soc_codec_dev_sh_hdmi = {
 270         .probe          = sh_hdmi_snd_probe,
 271         .read           = sh_hdmi_snd_read,
 272         .write          = sh_hdmi_snd_write,
 273 };
 274
 275 /*
 276  *      HDMI video
 277  */
 278
 279 /* External video parameter settings */
 280 static void hdmi_external_video_param(struct sh_hdmi *hdmi)
 281 {
 282         struct fb_var_screeninfo *var = &hdmi->var;
 283         u16 htotal, hblank, hdelay, vtotal, vblank, vdelay, voffset;
 284         u8 sync = 0;
 285
 286         htotal = var->xres + var->right_margin + var->left_margin + var->hsync_len;
 287
 288         hdelay = var->hsync_len + var->left_margin;
 289         hblank = var->right_margin + hdelay;
 290
 291         /*
 292          * Vertical timing looks a bit different in Figure 18,
 293          * but let's try the same first by setting offset = 0
 294          */
 295         vtotal = var->yres + var->upper_margin + var->lower_margin + var->vsync_len;
 296
 297         vdelay = var->vsync_len + var->upper_margin;
 298         vblank = var->lower_margin + vdelay;
 299         voffset = min(var->upper_margin / 2, 6U);
 300
 301         /*
 302          * [3]: VSYNC polarity: Positive
 303          * [2]: HSYNC polarity: Positive
 304          * [1]: Interlace/Progressive: Progressive
 305          * [0]: External video settings enable: used.
 306          */
 307         if (var->sync & FB_SYNC_HOR_HIGH_ACT)
 308                 sync |= 4;
 309         if (var->sync & FB_SYNC_VERT_HIGH_ACT)
 310                 sync |= 8;
 311
 312         pr_debug("H: %u, %u, %u, %u; V: %u, %u, %u, %u; sync 0x%x\n",
 313                  htotal, hblank, hdelay, var->hsync_len,
 314                  vtotal, vblank, vdelay, var->vsync_len, sync);
 315
 316         hdmi_write(hdmi, sync | (voffset << 4), HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
 317
 318         hdmi_write(hdmi, htotal, HDMI_EXTERNAL_H_TOTAL_7_0);
 319         hdmi_write(hdmi, htotal >> 8, HDMI_EXTERNAL_H_TOTAL_11_8);
 320
 321         hdmi_write(hdmi, hblank, HDMI_EXTERNAL_H_BLANK_7_0);
 322         hdmi_write(hdmi, hblank >> 8, HDMI_EXTERNAL_H_BLANK_9_8);
 323
 324         hdmi_write(hdmi, hdelay, HDMI_EXTERNAL_H_DELAY_7_0);
 325         hdmi_write(hdmi, hdelay >> 8, HDMI_EXTERNAL_H_DELAY_9_8);
 326
 327         hdmi_write(hdmi, var->hsync_len, HDMI_EXTERNAL_H_DURATION_7_0);
 328         hdmi_write(hdmi, var->hsync_len >> 8, HDMI_EXTERNAL_H_DURATION_9_8);
 329
 330         hdmi_write(hdmi, vtotal, HDMI_EXTERNAL_V_TOTAL_7_0);
 331         hdmi_write(hdmi, vtotal >> 8, HDMI_EXTERNAL_V_TOTAL_9_8);
 332
 333         hdmi_write(hdmi, vblank, HDMI_EXTERNAL_V_BLANK);
 334
 335         hdmi_write(hdmi, vdelay, HDMI_EXTERNAL_V_DELAY);
 336
 337         hdmi_write(hdmi, var->vsync_len, HDMI_EXTERNAL_V_DURATION);
 338
 339         /* Set bit 0 of HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS here for manual mode */
 340 }
 341
 342 /**
 343  * sh_hdmi_video_config()
 344  */
 345 static void sh_hdmi_video_config(struct sh_hdmi *hdmi)
 346 {
 347         /*
 348          * [7:4]: Audio sampling frequency: 48kHz
 349          * [3:1]: Input video format: RGB and YCbCr 4:4:4 (Y on Green)
 350          * [0]: Internal/External DE select: internal
 351          */
 352         hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
 353
 354         /*
 355          * [7:6]: Video output format: RGB 4:4:4
 356          * [5:4]: Input video data width: 8 bit
 357          * [3:1]: EAV/SAV location: channel 1
 358          * [0]: Video input color space: RGB
 359          */
 360         hdmi_write(hdmi, 0x34, HDMI_VIDEO_SETTING_1);
 361
 362         /*
 363          * [7:6]: Together with bit [6] of HDMI_AUDIO_VIDEO_SETTING_2, which is
 364          * left at 0 by default, this configures 24bpp and sets the Color Depth
 365          * (CD) field in the General Control Packet
 366          */
 367         hdmi_write(hdmi, 0x20, HDMI_DEEP_COLOR_MODES);
 368 }
 369
 370 /**
 371  * sh_hdmi_audio_config()
 372  */
 373 static void sh_hdmi_audio_config(struct sh_hdmi *hdmi)
 374 {
 375         u8 data;
 376         struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
 377
 378         /*
 379          * [7:4] L/R data swap control
 380          * [3:0] appropriate N[19:16]
 381          */
 382         hdmi_write(hdmi, 0x00, HDMI_L_R_DATA_SWAP_CTRL_RPKT);
 383         /* appropriate N[15:8] */
 384         hdmi_write(hdmi, 0x18, HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8);
 385         /* appropriate N[7:0] */
 386         hdmi_write(hdmi, 0x00, HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0);
 387
 388         /* [7:4] 48 kHz SPDIF not used */
 389         hdmi_write(hdmi, 0x20, HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS);
 390
 391         /*
 392          * [6:5] set required down sampling rate if required
 393          * [4:3] set required audio source
 394          */
 395         switch (pdata->flags & HDMI_SND_SRC_MASK) {
 396         default:
 397                 /* fall through */
 398         case HDMI_SND_SRC_I2S:
 399                 data = 0x0 << 3;
 400                 break;
 401         case HDMI_SND_SRC_SPDIF:
 402                 data = 0x1 << 3;
 403                 break;
 404         case HDMI_SND_SRC_DSD:
 405                 data = 0x2 << 3;
 406                 break;
 407         case HDMI_SND_SRC_HBR:
 408                 data = 0x3 << 3;
 409                 break;
 410         }
 411         hdmi_write(hdmi, data, HDMI_AUDIO_SETTING_1);
 412
 413         /* [3:0] set sending channel number for channel status */
 414         hdmi_write(hdmi, 0x40, HDMI_AUDIO_SETTING_2);
 415
 416         /*
 417          * [5:2] set valid I2S source input pin
 418          * [1:0] set input I2S source mode
 419          */
 420         hdmi_write(hdmi, 0x04, HDMI_I2S_AUDIO_SET);
 421
 422         /* [7:4] set valid DSD source input pin */
 423         hdmi_write(hdmi, 0x00, HDMI_DSD_AUDIO_SET);
 424
 425         /* [7:0] set appropriate I2S input pin swap settings if required */
 426         hdmi_write(hdmi, 0x00, HDMI_I2S_INPUT_PIN_SWAP);
 427
 428         /*
 429          * [7] set validity bit for channel status
 430          * [3:0] set original sample frequency for channel status
 431          */
 432         hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_1);
 433
 434         /*
 435          * [7] set value for channel status
 436          * [6] set value for channel status
 437          * [5] set copyright bit for channel status
 438          * [4:2] set additional information for channel status
 439          * [1:0] set clock accuracy for channel status
 440          */
 441         hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_2);
 442
 443         /* [7:0] set category code for channel status */
 444         hdmi_write(hdmi, 0x00, HDMI_CATEGORY_CODE);
 445
 446         /*
 447          * [7:4] set source number for channel status
 448          * [3:0] set word length for channel status
 449          */
 450         hdmi_write(hdmi, 0x00, HDMI_SOURCE_NUM_AUDIO_WORD_LEN);
 451
 452         /* [7:4] set sample frequency for channel status */
 453         hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
 454 }
 455
 456 /**
 457  * sh_hdmi_phy_config()
 458  */
 459 static void sh_hdmi_phy_config(struct sh_hdmi *hdmi)
 460 {
 461         /* 720p, 8bit, 74.25MHz. Might need to be adjusted for other formats */
 462         hdmi_write(hdmi, 0x19, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
 463         hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
 464         hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
 465         /* PLLA_CONFIG[7:0]: VCO gain, VCO offset, LPF resistance[0] */
 466         hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
 467         hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
 468         hdmi_write(hdmi, 0x4A, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
 469         hdmi_write(hdmi, 0x0E, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
 470         hdmi_write(hdmi, 0x25, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
 471         hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
 472 }
 473
 474 /**
 475  * sh_hdmi_avi_infoframe_setup() - Auxiliary Video Information InfoFrame CONTROL PACKET
 476  */
 477 static void sh_hdmi_avi_infoframe_setup(struct sh_hdmi *hdmi)
 478 {
 479         /* AVI InfoFrame */
 480         hdmi_write(hdmi, 0x06, HDMI_CTRL_PKT_BUF_INDEX);
 481
 482         /* Packet Type = 0x82 */
 483         hdmi_write(hdmi, 0x82, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
 484
 485         /* Version = 0x02 */
 486         hdmi_write(hdmi, 0x02, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
 487
 488         /* Length = 13 (0x0D) */
 489         hdmi_write(hdmi, 0x0D, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
 490
 491         /* N. A. Checksum */
 492         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
 493
 494         /*
 495          * Y = RGB
 496          * A0 = No Data
 497          * B = Bar Data not valid
 498          * S = No Data
 499          */
 500         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
 501
 502         /*
 503          * C = No Data
 504          * M = 16:9 Picture Aspect Ratio
 505          * R = Same as picture aspect ratio
 506          */
 507         hdmi_write(hdmi, 0x28, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
 508
 509         /*
 510          * ITC = No Data
 511          * EC = xvYCC601
 512          * Q = Default (depends on video format)
 513          * SC = No Known non_uniform Scaling
 514          */
 515         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
 516
 517         /*
 518          * VIC = 1280 x 720p: ignored if external config is used
 519          * Send 2 for 720 x 480p, 16 for 1080p
 520          */
 521         hdmi_write(hdmi, 4, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
 522
 523         /* PR = No Repetition */
 524         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
 525
 526         /* Line Number of End of Top Bar (lower 8 bits) */
 527         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
 528
 529         /* Line Number of End of Top Bar (upper 8 bits) */
 530         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
 531
 532         /* Line Number of Start of Bottom Bar (lower 8 bits) */
 533         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
 534
 535         /* Line Number of Start of Bottom Bar (upper 8 bits) */
 536         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
 537
 538         /* Pixel Number of End of Left Bar (lower 8 bits) */
 539         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
 540
 541         /* Pixel Number of End of Left Bar (upper 8 bits) */
 542         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB11);
 543
 544         /* Pixel Number of Start of Right Bar (lower 8 bits) */
 545         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB12);
 546
 547         /* Pixel Number of Start of Right Bar (upper 8 bits) */
 548         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB13);
 549 }
 550
 551 /**
 552  * sh_hdmi_audio_infoframe_setup() - Audio InfoFrame of CONTROL PACKET
 553  */
 554 static void sh_hdmi_audio_infoframe_setup(struct sh_hdmi *hdmi)
 555 {
 556         /* Audio InfoFrame */
 557         hdmi_write(hdmi, 0x08, HDMI_CTRL_PKT_BUF_INDEX);
 558
 559         /* Packet Type = 0x84 */
 560         hdmi_write(hdmi, 0x84, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
 561
 562         /* Version Number = 0x01 */
 563         hdmi_write(hdmi, 0x01, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
 564
 565         /* 0 Length = 10 (0x0A) */
 566         hdmi_write(hdmi, 0x0A, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
 567
 568         /* n. a. Checksum */
 569         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
 570
 571         /* Audio Channel Count = Refer to Stream Header */
 572         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
 573
 574         /* Refer to Stream Header */
 575         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
 576
 577         /* Format depends on coding type (i.e. CT0...CT3) */
 578         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
 579
 580         /* Speaker Channel Allocation = Front Right + Front Left */
 581         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
 582
 583         /* Level Shift Value = 0 dB, Down - mix is permitted or no information */
 584         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
 585
 586         /* Reserved (0) */
 587         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
 588         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
 589         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
 590         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
 591         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
 592 }
 593
 594 /**
 595  * sh_hdmi_gamut_metadata_setup() - Gamut Metadata Packet of CONTROL PACKET
 596  */
 597 static void sh_hdmi_gamut_metadata_setup(struct sh_hdmi *hdmi)
 598 {
 599         int i;
 600
 601         /* Gamut Metadata Packet */
 602         hdmi_write(hdmi, 0x04, HDMI_CTRL_PKT_BUF_INDEX);
 603
 604         /* Packet Type = 0x0A */
 605         hdmi_write(hdmi, 0x0A, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
 606         /* Gamut Packet is not used, so default value */
 607         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
 608         /* Gamut Packet is not used, so default value */
 609         hdmi_write(hdmi, 0x10, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
 610
 611         /* GBD bytes 0 through 27 */
 612         for (i = 0; i <= 27; i++)
 613                 /* HDMI_CTRL_PKT_BUF_ACCESS_PB0_63H - PB27_7EH */
 614                 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0 + i);
 615 }
 616
 617 /**
 618  * sh_hdmi_acp_setup() - Audio Content Protection Packet (ACP)
 619  */
 620 static void sh_hdmi_acp_setup(struct sh_hdmi *hdmi)
 621 {
 622         int i;
 623
 624         /* Audio Content Protection Packet (ACP) */
 625         hdmi_write(hdmi, 0x01, HDMI_CTRL_PKT_BUF_INDEX);
 626
 627         /* Packet Type = 0x04 */
 628         hdmi_write(hdmi, 0x04, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
 629         /* ACP_Type */
 630         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
 631         /* Reserved (0) */
 632         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
 633
 634         /* GBD bytes 0 through 27 */
 635         for (i = 0; i <= 27; i++)
 636                 /* HDMI_CTRL_PKT_BUF_ACCESS_PB0 - PB27 */
 637                 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0 + i);
 638 }
 639
 640 /**
 641  * sh_hdmi_isrc1_setup() - ISRC1 Packet
 642  */
 643 static void sh_hdmi_isrc1_setup(struct sh_hdmi *hdmi)
 644 {
 645         int i;
 646
 647         /* ISRC1 Packet */
 648         hdmi_write(hdmi, 0x02, HDMI_CTRL_PKT_BUF_INDEX);
 649
 650         /* Packet Type = 0x05 */
 651         hdmi_write(hdmi, 0x05, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
 652         /* ISRC_Cont, ISRC_Valid, Reserved (0), ISRC_Status */
 653         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
 654         /* Reserved (0) */
 655         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
 656
 657         /* PB0 UPC_EAN_ISRC_0-15 */
 658         /* Bytes PB16-PB27 shall be set to a value of 0. */
 659         for (i = 0; i <= 27; i++)
 660                 /* HDMI_CTRL_PKT_BUF_ACCESS_PB0 - PB27 */
 661                 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0 + i);
 662 }
 663
 664 /**
 665  * sh_hdmi_isrc2_setup() - ISRC2 Packet
 666  */
 667 static void sh_hdmi_isrc2_setup(struct sh_hdmi *hdmi)
 668 {
 669         int i;
 670
 671         /* ISRC2 Packet */
 672         hdmi_write(hdmi, 0x03, HDMI_CTRL_PKT_BUF_INDEX);
 673
 674         /* HB0 Packet Type = 0x06 */
 675         hdmi_write(hdmi, 0x06, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
 676         /* Reserved (0) */
 677         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
 678         /* Reserved (0) */
 679         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
 680
 681         /* PB0 UPC_EAN_ISRC_16-31 */
 682         /* Bytes PB16-PB27 shall be set to a value of 0. */
 683         for (i = 0; i <= 27; i++)
 684                 /* HDMI_CTRL_PKT_BUF_ACCESS_PB0 - PB27 */
 685                 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0 + i);
 686 }
 687
 688 /**
 689  * sh_hdmi_configure() - Initialise HDMI for output
 690  */
 691 static void sh_hdmi_configure(struct sh_hdmi *hdmi)
 692 {
 693         /* Configure video format */
 694         sh_hdmi_video_config(hdmi);
 695
 696         /* Configure audio format */
 697         sh_hdmi_audio_config(hdmi);
 698
 699         /* Configure PHY */
 700         sh_hdmi_phy_config(hdmi);
 701
 702         /* Auxiliary Video Information (AVI) InfoFrame */
 703         sh_hdmi_avi_infoframe_setup(hdmi);
 704
 705         /* Audio InfoFrame */
 706         sh_hdmi_audio_infoframe_setup(hdmi);
 707
 708         /* Gamut Metadata packet */
 709         sh_hdmi_gamut_metadata_setup(hdmi);
 710
 711         /* Audio Content Protection (ACP) Packet */
 712         sh_hdmi_acp_setup(hdmi);
 713
 714         /* ISRC1 Packet */
 715         sh_hdmi_isrc1_setup(hdmi);
 716
 717         /* ISRC2 Packet */
 718         sh_hdmi_isrc2_setup(hdmi);
 719
 720         /*
 721          * Control packet auto send with VSYNC control: auto send
 722          * General control, Gamut metadata, ISRC, and ACP packets
 723          */
 724         hdmi_write(hdmi, 0x8E, HDMI_CTRL_PKT_AUTO_SEND);
 725
 726         /* FIXME */
 727         msleep(10);
 728
 729         /* PS mode b->d, reset PLLA and PLLB */
 730         hdmi_write(hdmi, 0x4C, HDMI_SYSTEM_CTRL);
 731
 732         udelay(10);
 733
 734         hdmi_write(hdmi, 0x40, HDMI_SYSTEM_CTRL);
 735 }
 736
 737 static void sh_hdmi_read_edid(struct sh_hdmi *hdmi)
 738 {
 739         struct fb_var_screeninfo *var = &hdmi->var;
 740         struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
 741         struct fb_videomode *lcd_cfg = &pdata->lcd_chan->lcd_cfg;
 742         unsigned long height = var->height, width = var->width;
 743         int i;
 744         u8 edid[128];
 745
 746         /* Read EDID */
 747         pr_debug("Read back EDID code:");
 748         for (i = 0; i < 128; i++) {
 749                 edid[i] = hdmi_read(hdmi, HDMI_EDID_KSV_FIFO_ACCESS_WINDOW);
 750 #ifdef DEBUG
 751                 if ((i % 16) == 0) {
 752                         printk(KERN_CONT "\n");
 753                         printk(KERN_DEBUG "%02X | %02X", i, edid[i]);
 754                 } else {
 755                         printk(KERN_CONT " %02X", edid[i]);
 756                 }
 757 #endif
 758         }
 759 #ifdef DEBUG
 760         printk(KERN_CONT "\n");
 761 #endif
 762         fb_parse_edid(edid, var);
 763         pr_debug("%u-%u-%u-%u x %u-%u-%u-%u @ %lu kHz monitor detected\n",
 764                  var->left_margin, var->xres, var->right_margin, var->hsync_len,
 765                  var->upper_margin, var->yres, var->lower_margin, var->vsync_len,
 766                  PICOS2KHZ(var->pixclock));
 767
 768         /* FIXME: Use user-provided configuration instead of EDID */
 769         var->width              = width;
 770         var->xres               = lcd_cfg->xres;
 771         var->xres_virtual       = lcd_cfg->xres;
 772         var->left_margin        = lcd_cfg->left_margin;
 773         var->right_margin       = lcd_cfg->right_margin;
 774         var->hsync_len          = lcd_cfg->hsync_len;
 775         var->height             = height;
 776         var->yres               = lcd_cfg->yres;
 777         var->yres_virtual       = lcd_cfg->yres * 2;
 778         var->upper_margin       = lcd_cfg->upper_margin;
 779         var->lower_margin       = lcd_cfg->lower_margin;
 780         var->vsync_len          = lcd_cfg->vsync_len;
 781         var->sync               = lcd_cfg->sync;
 782         var->pixclock           = lcd_cfg->pixclock;
 783
 784         hdmi_external_video_param(hdmi);
 785 }
 786
 787 static irqreturn_t sh_hdmi_hotplug(int irq, void *dev_id)
 788 {
 789         struct sh_hdmi *hdmi = dev_id;
 790         u8 status1, status2, mask1, mask2;
 791
 792         /* mode_b and PLLA and PLLB reset */
 793         hdmi_write(hdmi, 0x2C, HDMI_SYSTEM_CTRL);
 794
 795         /* How long shall reset be held? */
 796         udelay(10);
 797
 798         /* mode_b and PLLA and PLLB reset release */
 799         hdmi_write(hdmi, 0x20, HDMI_SYSTEM_CTRL);
 800
 801         status1 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_1);
 802         status2 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_2);
 803
 804         mask1 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_1);
 805         mask2 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_2);
 806
 807         /* Correct would be to ack only set bits, but the datasheet requires 0xff */
 808         hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_1);
 809         hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_2);
 810
 811         if (printk_ratelimit())
 812                 pr_debug("IRQ #%d: Status #1: 0x%x & 0x%x, #2: 0x%x & 0x%x\n",
 813                          irq, status1, mask1, status2, mask2);
 814
 815         if (!((status1 & mask1) | (status2 & mask2))) {
 816                 return IRQ_NONE;
 817         } else if (status1 & 0xc0) {
 818                 u8 msens;
 819
 820                 /* Datasheet specifies 10ms... */
 821                 udelay(500);
 822
 823                 msens = hdmi_read(hdmi, HDMI_HOT_PLUG_MSENS_STATUS);
 824                 pr_debug("MSENS 0x%x\n", msens);
 825                 /* Check, if hot plug & MSENS pin status are both high */
 826                 if ((msens & 0xC0) == 0xC0) {
 827                         /* Display plug in */
 828                         hdmi->hp_state = HDMI_HOTPLUG_CONNECTED;
 829
 830                         /* Set EDID word address  */
 831                         hdmi_write(hdmi, 0x00, HDMI_EDID_WORD_ADDRESS);
 832                         /* Set EDID segment pointer */
 833                         hdmi_write(hdmi, 0x00, HDMI_EDID_SEGMENT_POINTER);
 834                         /* Enable EDID interrupt */
 835                         hdmi_write(hdmi, 0xC6, HDMI_INTERRUPT_MASK_1);
 836                 } else if (!(status1 & 0x80)) {
 837                         /* Display unplug, beware multiple interrupts */
 838                         if (hdmi->hp_state != HDMI_HOTPLUG_DISCONNECTED)
 839                                 schedule_delayed_work(&hdmi->edid_work, 0);
 840
 841                         hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
 842                         /* display_off will switch back to mode_a */
 843                 }
 844         } else if (status1 & 2) {
 845                 /* EDID error interrupt: retry */
 846                 /* Set EDID word address  */
 847                 hdmi_write(hdmi, 0x00, HDMI_EDID_WORD_ADDRESS);
 848                 /* Set EDID segment pointer */
 849                 hdmi_write(hdmi, 0x00, HDMI_EDID_SEGMENT_POINTER);
 850         } else if (status1 & 4) {
 851                 /* Disable EDID interrupt */
 852                 hdmi_write(hdmi, 0xC0, HDMI_INTERRUPT_MASK_1);
 853                 hdmi->hp_state = HDMI_HOTPLUG_EDID_DONE;
 854                 schedule_delayed_work(&hdmi->edid_work, msecs_to_jiffies(10));
 855         }
 856
 857         return IRQ_HANDLED;
 858 }
 859
 860 static void hdmi_display_on(void *arg, struct fb_info *info)
 861 {
 862         struct sh_hdmi *hdmi = arg;
 863         struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
 864
 865         if (info->var.xres != 1280 || info->var.yres != 720) {
 866                 dev_warn(info->device, "Unsupported framebuffer geometry %ux%u\n",
 867                          info->var.xres, info->var.yres);
 868                 return;
 869         }
 870
 871         pr_debug("%s(%p): state %x\n", __func__, pdata->lcd_dev, info->state);
 872         /*
 873          * FIXME: not a good place to store fb_info. And we cannot nullify it
 874          * even on monitor disconnect. What should the lifecycle be?
 875          */
 876         hdmi->info = info;
 877         switch (hdmi->hp_state) {
 878         case HDMI_HOTPLUG_EDID_DONE:
 879                 /* PS mode d->e. All functions are active */
 880                 hdmi_write(hdmi, 0x80, HDMI_SYSTEM_CTRL);
 881                 pr_debug("HDMI running\n");
 882                 break;
 883         case HDMI_HOTPLUG_DISCONNECTED:
 884                 info->state = FBINFO_STATE_SUSPENDED;
 885         default:
 886                 hdmi->var = info->var;
 887         }
 888 }
 889
 890 static void hdmi_display_off(void *arg)
 891 {
 892         struct sh_hdmi *hdmi = arg;
 893         struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
 894
 895         pr_debug("%s(%p)\n", __func__, pdata->lcd_dev);
 896         /* PS mode e->a */
 897         hdmi_write(hdmi, 0x10, HDMI_SYSTEM_CTRL);
 898 }
 899
 900 /* Hotplug interrupt occurred, read EDID */
 901 static void edid_work_fn(struct work_struct *work)
 902 {
 903         struct sh_hdmi *hdmi = container_of(work, struct sh_hdmi, edid_work.work);
 904         struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
 905
 906         pr_debug("%s(%p): begin, hotplug status %d\n", __func__,
 907                  pdata->lcd_dev, hdmi->hp_state);
 908
 909         if (!pdata->lcd_dev)
 910                 return;
 911
 912         if (hdmi->hp_state == HDMI_HOTPLUG_EDID_DONE) {
 913                 pm_runtime_get_sync(hdmi->dev);
 914                 /* A device has been plugged in */
 915                 sh_hdmi_read_edid(hdmi);
 916                 msleep(10);
 917                 sh_hdmi_configure(hdmi);
 918                 /* Switched to another (d) power-save mode */
 919                 msleep(10);
 920
 921                 if (!hdmi->info)
 922                         return;
 923
 924                 acquire_console_sem();
 925
 926                 /* HDMI plug in */
 927                 hdmi->info->var = hdmi->var;
 928                 if (hdmi->info->state != FBINFO_STATE_RUNNING)
 929                         fb_set_suspend(hdmi->info, 0);
 930                 else
 931                         hdmi_display_on(hdmi, hdmi->info);
 932
 933                 release_console_sem();
 934         } else {
 935                 if (!hdmi->info)
 936                         return;
 937
 938                 acquire_console_sem();
 939
 940                 /* HDMI disconnect */
 941                 fb_set_suspend(hdmi->info, 1);
 942
 943                 release_console_sem();
 944                 pm_runtime_put(hdmi->dev);
 945         }
 946
 947         pr_debug("%s(%p): end\n", __func__, pdata->lcd_dev);
 948 }
 949
 950 static int __init sh_hdmi_probe(struct platform_device *pdev)
 951 {
 952         struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data;
 953         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 954         int irq = platform_get_irq(pdev, 0), ret;
 955         struct sh_hdmi *hdmi;
 956         long rate;
 957
 958         if (!res || !pdata || irq < 0)
 959                 return -ENODEV;
 960
 961         hdmi = kzalloc(sizeof(*hdmi), GFP_KERNEL);
 962         if (!hdmi) {
 963                 dev_err(&pdev->dev, "Cannot allocate device data\n");
 964                 return -ENOMEM;
 965         }
 966
 967         ret =  snd_soc_register_codec(&pdev->dev,
 968                         &soc_codec_dev_sh_hdmi, &sh_hdmi_dai, 1);
 969         if (ret < 0)
 970                 goto esndreg;
 971
 972         hdmi->dev = &pdev->dev;
 973
 974         hdmi->hdmi_clk = clk_get(&pdev->dev, "ick");
 975         if (IS_ERR(hdmi->hdmi_clk)) {
 976                 ret = PTR_ERR(hdmi->hdmi_clk);
 977                 dev_err(&pdev->dev, "Unable to get clock: %d\n", ret);
 978                 goto egetclk;
 979         }
 980
 981         rate = PICOS2KHZ(pdata->lcd_chan->lcd_cfg.pixclock) * 1000;
 982
 983         rate = clk_round_rate(hdmi->hdmi_clk, rate);
 984         if (rate < 0) {
 985                 ret = rate;
 986                 dev_err(&pdev->dev, "Cannot get suitable rate: %ld\n", rate);
 987                 goto erate;
 988         }
 989
 990         ret = clk_set_rate(hdmi->hdmi_clk, rate);
 991         if (ret < 0) {
 992                 dev_err(&pdev->dev, "Cannot set rate %ld: %d\n", rate, ret);
 993                 goto erate;
 994         }
 995
 996         pr_debug("HDMI set frequency %lu\n", rate);
 997
 998         ret = clk_enable(hdmi->hdmi_clk);
 999         if (ret < 0) {
1000                 dev_err(&pdev->dev, "Cannot enable clock: %d\n", ret);
1001                 goto eclkenable;
1002         }
1003
1004         dev_info(&pdev->dev, "Enabled HDMI clock at %luHz\n", rate);
1005
1006         if (!request_mem_region(res->start, resource_size(res), dev_name(&pdev->dev))) {
1007                 dev_err(&pdev->dev, "HDMI register region already claimed\n");
1008                 ret = -EBUSY;
1009                 goto ereqreg;
1010         }
1011
1012         hdmi->base = ioremap(res->start, resource_size(res));
1013         if (!hdmi->base) {
1014                 dev_err(&pdev->dev, "HDMI register region already claimed\n");
1015                 ret = -ENOMEM;
1016                 goto emap;
1017         }
1018
1019         platform_set_drvdata(pdev, hdmi);
1020
1021 #if 1
1022         /* Product and revision IDs are 0 in sh-mobile version */
1023         dev_info(&pdev->dev, "Detected HDMI controller 0x%x:0x%x\n",
1024                  hdmi_read(hdmi, HDMI_PRODUCT_ID), hdmi_read(hdmi, HDMI_REVISION_ID));
1025 #endif
1026
1027         /* Set up LCDC callbacks */
1028         pdata->lcd_chan->board_cfg.board_data = hdmi;
1029         pdata->lcd_chan->board_cfg.display_on = hdmi_display_on;
1030         pdata->lcd_chan->board_cfg.display_off = hdmi_display_off;
1031
1032         INIT_DELAYED_WORK(&hdmi->edid_work, edid_work_fn);
1033
1034         pm_runtime_enable(&pdev->dev);
1035         pm_runtime_resume(&pdev->dev);
1036
1037         ret = request_irq(irq, sh_hdmi_hotplug, 0,
1038                           dev_name(&pdev->dev), hdmi);
1039         if (ret < 0) {
1040                 dev_err(&pdev->dev, "Unable to request irq: %d\n", ret);
1041                 goto ereqirq;
1042         }
1043
1044         return 0;
1045
1046 ereqirq:
1047         pm_runtime_disable(&pdev->dev);
1048         iounmap(hdmi->base);
1049 emap:
1050         release_mem_region(res->start, resource_size(res));
1051 ereqreg:
1052         clk_disable(hdmi->hdmi_clk);
1053 eclkenable:
1054 erate:
1055         clk_put(hdmi->hdmi_clk);
1056 egetclk:
1057         snd_soc_unregister_codec(&pdev->dev);
1058 esndreg:
1059         kfree(hdmi);
1060
1061         return ret;
1062 }
1063
1064 static int __exit sh_hdmi_remove(struct platform_device *pdev)
1065 {
1066         struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data;
1067         struct sh_hdmi *hdmi = platform_get_drvdata(pdev);
1068         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1069         int irq = platform_get_irq(pdev, 0);
1070
1071         snd_soc_unregister_codec(&pdev->dev);
1072
1073         pdata->lcd_chan->board_cfg.display_on = NULL;
1074         pdata->lcd_chan->board_cfg.display_off = NULL;
1075         pdata->lcd_chan->board_cfg.board_data = NULL;
1076
1077         free_irq(irq, hdmi);
1078         pm_runtime_disable(&pdev->dev);
1079         cancel_delayed_work_sync(&hdmi->edid_work);
1080         clk_disable(hdmi->hdmi_clk);
1081         clk_put(hdmi->hdmi_clk);
1082         iounmap(hdmi->base);
1083         release_mem_region(res->start, resource_size(res));
1084         kfree(hdmi);
1085
1086         return 0;
1087 }
1088
1089 static struct platform_driver sh_hdmi_driver = {
1090         .remove         = __exit_p(sh_hdmi_remove),
1091         .driver = {
1092                 .name   = "sh-mobile-hdmi",
1093         },
1094 };
1095
1096 static int __init sh_hdmi_init(void)
1097 {
1098         return platform_driver_probe(&sh_hdmi_driver, sh_hdmi_probe);
1099 }
1100 module_init(sh_hdmi_init);
1101
1102 static void __exit sh_hdmi_exit(void)
1103 {
1104         platform_driver_unregister(&sh_hdmi_driver);
1105 }
1106 module_exit(sh_hdmi_exit);
1107
1108 MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
1109 MODULE_DESCRIPTION("SuperH / ARM-shmobile HDMI driver");
1110 MODULE_LICENSE("GPL v2");