drivers/staging/lirc/lirc_sir.c

   1 /*
   2  * LIRC SIR driver, (C) 2000 Milan Pikula <www@fornax.sk>
   3  *
   4  * lirc_sir - Device driver for use with SIR (serial infra red)
   5  * mode of IrDA on many notebooks.
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License as published by
   9  *  the Free Software Foundation; either version 2 of the License, or
  10  *  (at your option) any later version.
  11  *
  12  *  This program is distributed in the hope that it will be useful,
  13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *  GNU General Public License for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License
  18  *  along with this program; if not, write to the Free Software
  19  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  *
  21  *
  22  * 2000/09/16 Frank Przybylski <mail@frankprzybylski.de> :
  23  *  added timeout and relaxed pulse detection, removed gap bug
  24  *
  25  * 2000/12/15 Christoph Bartelmus <lirc@bartelmus.de> :
  26  *   added support for Tekram Irmate 210 (sending does not work yet,
  27  *   kind of disappointing that nobody was able to implement that
  28  *   before),
  29  *   major clean-up
  30  *
  31  * 2001/02/27 Christoph Bartelmus <lirc@bartelmus.de> :
  32  *   added support for StrongARM SA1100 embedded microprocessor
  33  *   parts cut'n'pasted from sa1100_ir.c (C) 2000 Russell King
  34  */
  35
  36 #include <linux/module.h>
  37 #include <linux/sched.h>
  38 #include <linux/errno.h>
  39 #include <linux/signal.h>
  40 #include <linux/fs.h>
  41 #include <linux/interrupt.h>
  42 #include <linux/ioport.h>
  43 #include <linux/kernel.h>
  44 #include <linux/serial_reg.h>
  45 #include <linux/time.h>
  46 #include <linux/string.h>
  47 #include <linux/types.h>
  48 #include <linux/wait.h>
  49 #include <linux/mm.h>
  50 #include <linux/delay.h>
  51 #include <linux/poll.h>
  52 #include <asm/system.h>
  53 #include <linux/io.h>
  54 #include <asm/irq.h>
  55 #include <linux/fcntl.h>
  56 #ifdef LIRC_ON_SA1100
  57 #include <asm/hardware.h>
  58 #ifdef CONFIG_SA1100_COLLIE
  59 #include <asm/arch/tc35143.h>
  60 #include <asm/ucb1200.h>
  61 #endif
  62 #endif
  63
  64 #include <linux/timer.h>
  65
  66 #include <media/lirc.h>
  67 #include <media/lirc_dev.h>
  68
  69 /* SECTION: Definitions */
  70
  71 /*** Tekram dongle ***/
  72 #ifdef LIRC_SIR_TEKRAM
  73 /* stolen from kernel source */
  74 /* definitions for Tekram dongle */
  75 #define TEKRAM_115200 0x00
  76 #define TEKRAM_57600  0x01
  77 #define TEKRAM_38400  0x02
  78 #define TEKRAM_19200  0x03
  79 #define TEKRAM_9600   0x04
  80 #define TEKRAM_2400   0x08
  81
  82 #define TEKRAM_PW 0x10 /* Pulse select bit */
  83
  84 /* 10bit * 1s/115200bit in milliseconds = 87ms*/
  85 #define TIME_CONST (10000000ul/115200ul)
  86
  87 #endif
  88
  89 #ifdef LIRC_SIR_ACTISYS_ACT200L
  90 static void init_act200(void);
  91 #elif defined(LIRC_SIR_ACTISYS_ACT220L)
  92 static void init_act220(void);
  93 #endif
  94
  95 /*** SA1100 ***/
  96 #ifdef LIRC_ON_SA1100
  97 struct sa1100_ser2_registers {
  98         /* HSSP control register */
  99         unsigned char hscr0;
 100         /* UART registers */
 101         unsigned char utcr0;
 102         unsigned char utcr1;
 103         unsigned char utcr2;
 104         unsigned char utcr3;
 105         unsigned char utcr4;
 106         unsigned char utdr;
 107         unsigned char utsr0;
 108         unsigned char utsr1;
 109 } sr;
 110
 111 static int irq = IRQ_Ser2ICP;
 112
 113 #define LIRC_ON_SA1100_TRANSMITTER_LATENCY 0
 114
 115 /* pulse/space ratio of 50/50 */
 116 static unsigned long pulse_width = (13-LIRC_ON_SA1100_TRANSMITTER_LATENCY);
 117 /* 1000000/freq-pulse_width */
 118 static unsigned long space_width = (13-LIRC_ON_SA1100_TRANSMITTER_LATENCY);
 119 static unsigned int freq = 38000;      /* modulation frequency */
 120 static unsigned int duty_cycle = 50;   /* duty cycle of 50% */
 121
 122 #endif
 123
 124 #define RBUF_LEN 1024
 125 #define WBUF_LEN 1024
 126
 127 #define LIRC_DRIVER_NAME "lirc_sir"
 128
 129 #define PULSE '['
 130
 131 #ifndef LIRC_SIR_TEKRAM
 132 /* 9bit * 1s/115200bit in milli seconds = 78.125ms*/
 133 #define TIME_CONST (9000000ul/115200ul)
 134 #endif
 135
 136
 137 /* timeout for sequences in jiffies (=5/100s), must be longer than TIME_CONST */
 138 #define SIR_TIMEOUT     (HZ*5/100)
 139
 140 #ifndef LIRC_ON_SA1100
 141 #ifndef LIRC_IRQ
 142 #define LIRC_IRQ 4
 143 #endif
 144 #ifndef LIRC_PORT
 145 /* for external dongles, default to com1 */
 146 #if defined(LIRC_SIR_ACTISYS_ACT200L) || \
 147     defined(LIRC_SIR_ACTISYS_ACT220L) || \
 148     defined(LIRC_SIR_TEKRAM)
 149 #define LIRC_PORT 0x3f8
 150 #else
 151 /* onboard sir ports are typically com3 */
 152 #define LIRC_PORT 0x3e8
 153 #endif
 154 #endif
 155
 156 static int io = LIRC_PORT;
 157 static int irq = LIRC_IRQ;
 158 static int threshold = 3;
 159 #endif
 160
 161 static DEFINE_SPINLOCK(timer_lock);
 162 static struct timer_list timerlist;
 163 /* time of last signal change detected */
 164 static struct timeval last_tv = {0, 0};
 165 /* time of last UART data ready interrupt */
 166 static struct timeval last_intr_tv = {0, 0};
 167 static int last_value;
 168
 169 static DECLARE_WAIT_QUEUE_HEAD(lirc_read_queue);
 170
 171 static DEFINE_SPINLOCK(hardware_lock);
 172
 173 static int rx_buf[RBUF_LEN];
 174 static unsigned int rx_tail, rx_head;
 175
 176 static int debug;
 177 #define dprintk(fmt, args...)                                           \
 178         do {                                                            \
 179                 if (debug)                                              \
 180                         printk(KERN_DEBUG LIRC_DRIVER_NAME ": "         \
 181                                 fmt, ## args);                          \
 182         } while (0)
 183
 184 /* SECTION: Prototypes */
 185
 186 /* Communication with user-space */
 187 static unsigned int lirc_poll(struct file *file, poll_table *wait);
 188 static ssize_t lirc_read(struct file *file, char *buf, size_t count,
 189                 loff_t *ppos);
 190 static ssize_t lirc_write(struct file *file, const char *buf, size_t n,
 191                 loff_t *pos);
 192 static long lirc_ioctl(struct file *filep, unsigned int cmd, unsigned long arg);
 193 static void add_read_queue(int flag, unsigned long val);
 194 static int init_chrdev(void);
 195 static void drop_chrdev(void);
 196 /* Hardware */
 197 static irqreturn_t sir_interrupt(int irq, void *dev_id);
 198 static void send_space(unsigned long len);
 199 static void send_pulse(unsigned long len);
 200 static int init_hardware(void);
 201 static void drop_hardware(void);
 202 /* Initialisation */
 203 static int init_port(void);
 204 static void drop_port(void);
 205
 206 #ifdef LIRC_ON_SA1100
 207 static void on(void)
 208 {
 209         PPSR |= PPC_TXD2;
 210 }
 211
 212 static void off(void)
 213 {
 214         PPSR &= ~PPC_TXD2;
 215 }
 216 #else
 217 static inline unsigned int sinp(int offset)
 218 {
 219         return inb(io + offset);
 220 }
 221
 222 static inline void soutp(int offset, int value)
 223 {
 224         outb(value, io + offset);
 225 }
 226 #endif
 227
 228 #ifndef MAX_UDELAY_MS
 229 #define MAX_UDELAY_US 5000
 230 #else
 231 #define MAX_UDELAY_US (MAX_UDELAY_MS*1000)
 232 #endif
 233
 234 static void safe_udelay(unsigned long usecs)
 235 {
 236         while (usecs > MAX_UDELAY_US) {
 237                 udelay(MAX_UDELAY_US);
 238                 usecs -= MAX_UDELAY_US;
 239         }
 240         udelay(usecs);
 241 }
 242
 243 /* SECTION: Communication with user-space */
 244
 245 static unsigned int lirc_poll(struct file *file, poll_table *wait)
 246 {
 247         poll_wait(file, &lirc_read_queue, wait);
 248         if (rx_head != rx_tail)
 249                 return POLLIN | POLLRDNORM;
 250         return 0;
 251 }
 252
 253 static ssize_t lirc_read(struct file *file, char *buf, size_t count,
 254                 loff_t *ppos)
 255 {
 256         int n = 0;
 257         int retval = 0;
 258         DECLARE_WAITQUEUE(wait, current);
 259
 260         if (count % sizeof(int))
 261                 return -EINVAL;
 262
 263         add_wait_queue(&lirc_read_queue, &wait);
 264         set_current_state(TASK_INTERRUPTIBLE);
 265         while (n < count) {
 266                 if (rx_head != rx_tail) {
 267                         if (copy_to_user((void *) buf + n,
 268                                         (void *) (rx_buf + rx_head),
 269                                         sizeof(int))) {
 270                                 retval = -EFAULT;
 271                                 break;
 272                         }
 273                         rx_head = (rx_head + 1) & (RBUF_LEN - 1);
 274                         n += sizeof(int);
 275                 } else {
 276                         if (file->f_flags & O_NONBLOCK) {
 277                                 retval = -EAGAIN;
 278                                 break;
 279                         }
 280                         if (signal_pending(current)) {
 281                                 retval = -ERESTARTSYS;
 282                                 break;
 283                         }
 284                         schedule();
 285                         set_current_state(TASK_INTERRUPTIBLE);
 286                 }
 287         }
 288         remove_wait_queue(&lirc_read_queue, &wait);
 289         set_current_state(TASK_RUNNING);
 290         return n ? n : retval;
 291 }
 292 static ssize_t lirc_write(struct file *file, const char *buf, size_t n,
 293                                 loff_t *pos)
 294 {
 295         unsigned long flags;
 296         int i, count;
 297         int *tx_buf;
 298
 299         count = n / sizeof(int);
 300         if (n % sizeof(int) || count % 2 == 0)
 301                 return -EINVAL;
 302         tx_buf = memdup_user(buf, n);
 303         if (IS_ERR(tx_buf))
 304                 return PTR_ERR(tx_buf);
 305         i = 0;
 306 #ifdef LIRC_ON_SA1100
 307         /* disable receiver */
 308         Ser2UTCR3 = 0;
 309 #endif
 310         local_irq_save(flags);
 311         while (1) {
 312                 if (i >= count)
 313                         break;
 314                 if (tx_buf[i])
 315                         send_pulse(tx_buf[i]);
 316                 i++;
 317                 if (i >= count)
 318                         break;
 319                 if (tx_buf[i])
 320                         send_space(tx_buf[i]);
 321                 i++;
 322         }
 323         local_irq_restore(flags);
 324 #ifdef LIRC_ON_SA1100
 325         off();
 326         udelay(1000); /* wait 1ms for IR diode to recover */
 327         Ser2UTCR3 = 0;
 328         /* clear status register to prevent unwanted interrupts */
 329         Ser2UTSR0 &= (UTSR0_RID | UTSR0_RBB | UTSR0_REB);
 330         /* enable receiver */
 331         Ser2UTCR3 = UTCR3_RXE|UTCR3_RIE;
 332 #endif
 333         return count;
 334 }
 335
 336 static long lirc_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
 337 {
 338         int retval = 0;
 339         __u32 value = 0;
 340 #ifdef LIRC_ON_SA1100
 341
 342         if (cmd == LIRC_GET_FEATURES)
 343                 value = LIRC_CAN_SEND_PULSE |
 344                         LIRC_CAN_SET_SEND_DUTY_CYCLE |
 345                         LIRC_CAN_SET_SEND_CARRIER |
 346                         LIRC_CAN_REC_MODE2;
 347         else if (cmd == LIRC_GET_SEND_MODE)
 348                 value = LIRC_MODE_PULSE;
 349         else if (cmd == LIRC_GET_REC_MODE)
 350                 value = LIRC_MODE_MODE2;
 351 #else
 352         if (cmd == LIRC_GET_FEATURES)
 353                 value = LIRC_CAN_SEND_PULSE | LIRC_CAN_REC_MODE2;
 354         else if (cmd == LIRC_GET_SEND_MODE)
 355                 value = LIRC_MODE_PULSE;
 356         else if (cmd == LIRC_GET_REC_MODE)
 357                 value = LIRC_MODE_MODE2;
 358 #endif
 359
 360         switch (cmd) {
 361         case LIRC_GET_FEATURES:
 362         case LIRC_GET_SEND_MODE:
 363         case LIRC_GET_REC_MODE:
 364                 retval = put_user(value, (__u32 *) arg);
 365                 break;
 366
 367         case LIRC_SET_SEND_MODE:
 368         case LIRC_SET_REC_MODE:
 369                 retval = get_user(value, (__u32 *) arg);
 370                 break;
 371 #ifdef LIRC_ON_SA1100
 372         case LIRC_SET_SEND_DUTY_CYCLE:
 373                 retval = get_user(value, (__u32 *) arg);
 374                 if (retval)
 375                         return retval;
 376                 if (value <= 0 || value > 100)
 377                         return -EINVAL;
 378                 /* (value/100)*(1000000/freq) */
 379                 duty_cycle = value;
 380                 pulse_width = (unsigned long) duty_cycle*10000/freq;
 381                 space_width = (unsigned long) 1000000L/freq-pulse_width;
 382                 if (pulse_width >= LIRC_ON_SA1100_TRANSMITTER_LATENCY)
 383                         pulse_width -= LIRC_ON_SA1100_TRANSMITTER_LATENCY;
 384                 if (space_width >= LIRC_ON_SA1100_TRANSMITTER_LATENCY)
 385                         space_width -= LIRC_ON_SA1100_TRANSMITTER_LATENCY;
 386                 break;
 387         case LIRC_SET_SEND_CARRIER:
 388                 retval = get_user(value, (__u32 *) arg);
 389                 if (retval)
 390                         return retval;
 391                 if (value > 500000 || value < 20000)
 392                         return -EINVAL;
 393                 freq = value;
 394                 pulse_width = (unsigned long) duty_cycle*10000/freq;
 395                 space_width = (unsigned long) 1000000L/freq-pulse_width;
 396                 if (pulse_width >= LIRC_ON_SA1100_TRANSMITTER_LATENCY)
 397                         pulse_width -= LIRC_ON_SA1100_TRANSMITTER_LATENCY;
 398                 if (space_width >= LIRC_ON_SA1100_TRANSMITTER_LATENCY)
 399                         space_width -= LIRC_ON_SA1100_TRANSMITTER_LATENCY;
 400                 break;
 401 #endif
 402         default:
 403                 retval = -ENOIOCTLCMD;
 404
 405         }
 406
 407         if (retval)
 408                 return retval;
 409         if (cmd == LIRC_SET_REC_MODE) {
 410                 if (value != LIRC_MODE_MODE2)
 411                         retval = -ENOSYS;
 412         } else if (cmd == LIRC_SET_SEND_MODE) {
 413                 if (value != LIRC_MODE_PULSE)
 414                         retval = -ENOSYS;
 415         }
 416
 417         return retval;
 418 }
 419
 420 static void add_read_queue(int flag, unsigned long val)
 421 {
 422         unsigned int new_rx_tail;
 423         int newval;
 424
 425         dprintk("add flag %d with val %lu\n", flag, val);
 426
 427         newval = val & PULSE_MASK;
 428
 429         /*
 430          * statistically, pulses are ~TIME_CONST/2 too long. we could
 431          * maybe make this more exact, but this is good enough
 432          */
 433         if (flag) {
 434                 /* pulse */
 435                 if (newval > TIME_CONST/2)
 436                         newval -= TIME_CONST/2;
 437                 else /* should not ever happen */
 438                         newval = 1;
 439                 newval |= PULSE_BIT;
 440         } else {
 441                 newval += TIME_CONST/2;
 442         }
 443         new_rx_tail = (rx_tail + 1) & (RBUF_LEN - 1);
 444         if (new_rx_tail == rx_head) {
 445                 dprintk("Buffer overrun.\n");
 446                 return;
 447         }
 448         rx_buf[rx_tail] = newval;
 449         rx_tail = new_rx_tail;
 450         wake_up_interruptible(&lirc_read_queue);
 451 }
 452
 453 static const struct file_operations lirc_fops = {
 454         .owner          = THIS_MODULE,
 455         .read           = lirc_read,
 456         .write          = lirc_write,
 457         .poll           = lirc_poll,
 458         .unlocked_ioctl = lirc_ioctl,
 459 #ifdef CONFIG_COMPAT
 460         .compat_ioctl   = lirc_ioctl,
 461 #endif
 462         .open           = lirc_dev_fop_open,
 463         .release        = lirc_dev_fop_close,
 464 };
 465
 466 static int set_use_inc(void *data)
 467 {
 468        return 0;
 469 }
 470
 471 static void set_use_dec(void *data)
 472 {
 473 }
 474
 475 static struct lirc_driver driver = {
 476        .name            = LIRC_DRIVER_NAME,
 477        .minor           = -1,
 478        .code_length     = 1,
 479        .sample_rate     = 0,
 480        .data            = NULL,
 481        .add_to_buf      = NULL,
 482        .set_use_inc     = set_use_inc,
 483        .set_use_dec     = set_use_dec,
 484        .fops            = &lirc_fops,
 485        .dev             = NULL,
 486        .owner           = THIS_MODULE,
 487 };
 488
 489
 490 static int init_chrdev(void)
 491 {
 492         driver.minor = lirc_register_driver(&driver);
 493         if (driver.minor < 0) {
 494                 printk(KERN_ERR LIRC_DRIVER_NAME ": init_chrdev() failed.\n");
 495                 return -EIO;
 496         }
 497         return 0;
 498 }
 499
 500 static void drop_chrdev(void)
 501 {
 502         lirc_unregister_driver(driver.minor);
 503 }
 504
 505 /* SECTION: Hardware */
 506 static long delta(struct timeval *tv1, struct timeval *tv2)
 507 {
 508         unsigned long deltv;
 509
 510         deltv = tv2->tv_sec - tv1->tv_sec;
 511         if (deltv > 15)
 512                 deltv = 0xFFFFFF;
 513         else
 514                 deltv = deltv*1000000 +
 515                         tv2->tv_usec -
 516                         tv1->tv_usec;
 517         return deltv;
 518 }
 519
 520 static void sir_timeout(unsigned long data)
 521 {
 522         /*
 523          * if last received signal was a pulse, but receiving stopped
 524          * within the 9 bit frame, we need to finish this pulse and
 525          * simulate a signal change to from pulse to space. Otherwise
 526          * upper layers will receive two sequences next time.
 527          */
 528
 529         unsigned long flags;
 530         unsigned long pulse_end;
 531
 532         /* avoid interference with interrupt */
 533         spin_lock_irqsave(&timer_lock, flags);
 534         if (last_value) {
 535 #ifndef LIRC_ON_SA1100
 536                 /* clear unread bits in UART and restart */
 537                 outb(UART_FCR_CLEAR_RCVR, io + UART_FCR);
 538 #endif
 539                 /* determine 'virtual' pulse end: */
 540                 pulse_end = delta(&last_tv, &last_intr_tv);
 541                 dprintk("timeout add %d for %lu usec\n", last_value, pulse_end);
 542                 add_read_queue(last_value, pulse_end);
 543                 last_value = 0;
 544                 last_tv = last_intr_tv;
 545         }
 546         spin_unlock_irqrestore(&timer_lock, flags);
 547 }
 548
 549 static irqreturn_t sir_interrupt(int irq, void *dev_id)
 550 {
 551         unsigned char data;
 552         struct timeval curr_tv;
 553         static unsigned long deltv;
 554 #ifdef LIRC_ON_SA1100
 555         int status;
 556         static int n;
 557
 558         status = Ser2UTSR0;
 559         /*
 560          * Deal with any receive errors first.  The bytes in error may be
 561          * the only bytes in the receive FIFO, so we do this first.
 562          */
 563         while (status & UTSR0_EIF) {
 564                 int bstat;
 565
 566                 if (debug) {
 567                         dprintk("EIF\n");
 568                         bstat = Ser2UTSR1;
 569
 570                         if (bstat & UTSR1_FRE)
 571                                 dprintk("frame error\n");
 572                         if (bstat & UTSR1_ROR)
 573                                 dprintk("receive fifo overrun\n");
 574                         if (bstat & UTSR1_PRE)
 575                                 dprintk("parity error\n");
 576                 }
 577
 578                 bstat = Ser2UTDR;
 579                 n++;
 580                 status = Ser2UTSR0;
 581         }
 582
 583         if (status & (UTSR0_RFS | UTSR0_RID)) {
 584                 do_gettimeofday(&curr_tv);
 585                 deltv = delta(&last_tv, &curr_tv);
 586                 do {
 587                         data = Ser2UTDR;
 588                         dprintk("%d data: %u\n", n, (unsigned int) data);
 589                         n++;
 590                 } while (status & UTSR0_RID && /* do not empty fifo in order to
 591                                                 * get UTSR0_RID in any case */
 592                       Ser2UTSR1 & UTSR1_RNE); /* data ready */
 593
 594                 if (status&UTSR0_RID) {
 595                         add_read_queue(0 , deltv - n * TIME_CONST); /*space*/
 596                         add_read_queue(1, n * TIME_CONST); /*pulse*/
 597                         n = 0;
 598                         last_tv = curr_tv;
 599                 }
 600         }
 601
 602         if (status & UTSR0_TFS)
 603                 printk(KERN_ERR "transmit fifo not full, shouldn't happen\n");
 604
 605         /* We must clear certain bits. */
 606         status &= (UTSR0_RID | UTSR0_RBB | UTSR0_REB);
 607         if (status)
 608                 Ser2UTSR0 = status;
 609 #else
 610         unsigned long deltintrtv;
 611         unsigned long flags;
 612         int iir, lsr;
 613
 614         while ((iir = inb(io + UART_IIR) & UART_IIR_ID)) {
 615                 switch (iir&UART_IIR_ID) { /* FIXME toto treba preriedit */
 616                 case UART_IIR_MSI:
 617                         (void) inb(io + UART_MSR);
 618                         break;
 619                 case UART_IIR_RLSI:
 620                         (void) inb(io + UART_LSR);
 621                         break;
 622                 case UART_IIR_THRI:
 623 #if 0
 624                         if (lsr & UART_LSR_THRE) /* FIFO is empty */
 625                                 outb(data, io + UART_TX)
 626 #endif
 627                         break;
 628                 case UART_IIR_RDI:
 629                         /* avoid interference with timer */
 630                         spin_lock_irqsave(&timer_lock, flags);
 631                         do {
 632                                 del_timer(&timerlist);
 633                                 data = inb(io + UART_RX);
 634                                 do_gettimeofday(&curr_tv);
 635                                 deltv = delta(&last_tv, &curr_tv);
 636                                 deltintrtv = delta(&last_intr_tv, &curr_tv);
 637                                 dprintk("t %lu, d %d\n", deltintrtv, (int)data);
 638                                 /*
 639                                  * if nothing came in last X cycles,
 640                                  * it was gap
 641                                  */
 642                                 if (deltintrtv > TIME_CONST * threshold) {
 643                                         if (last_value) {
 644                                                 dprintk("GAP\n");
 645                                                 /* simulate signal change */
 646                                                 add_read_queue(last_value,
 647                                                                deltv -
 648                                                                deltintrtv);
 649                                                 last_value = 0;
 650                                                 last_tv.tv_sec =
 651                                                         last_intr_tv.tv_sec;
 652                                                 last_tv.tv_usec =
 653                                                         last_intr_tv.tv_usec;
 654                                                 deltv = deltintrtv;
 655                                         }
 656                                 }
 657                                 data = 1;
 658                                 if (data ^ last_value) {
 659                                         /*
 660                                          * deltintrtv > 2*TIME_CONST, remember?
 661                                          * the other case is timeout
 662                                          */
 663                                         add_read_queue(last_value,
 664                                                        deltv-TIME_CONST);
 665                                         last_value = data;
 666                                         last_tv = curr_tv;
 667                                         if (last_tv.tv_usec >= TIME_CONST) {
 668                                                 last_tv.tv_usec -= TIME_CONST;
 669                                         } else {
 670                                                 last_tv.tv_sec--;
 671                                                 last_tv.tv_usec += 1000000 -
 672                                                         TIME_CONST;
 673                                         }
 674                                 }
 675                                 last_intr_tv = curr_tv;
 676                                 if (data) {
 677                                         /*
 678                                          * start timer for end of
 679                                          * sequence detection
 680                                          */
 681                                         timerlist.expires = jiffies +
 682                                                                 SIR_TIMEOUT;
 683                                         add_timer(&timerlist);
 684                                 }
 685
 686                                 lsr = inb(io + UART_LSR);
 687                         } while (lsr & UART_LSR_DR); /* data ready */
 688                         spin_unlock_irqrestore(&timer_lock, flags);
 689                         break;
 690                 default:
 691                         break;
 692                 }
 693         }
 694 #endif
 695         return IRQ_RETVAL(IRQ_HANDLED);
 696 }
 697
 698 #ifdef LIRC_ON_SA1100
 699 static void send_pulse(unsigned long length)
 700 {
 701         unsigned long k, delay;
 702         int flag;
 703
 704         if (length == 0)
 705                 return;
 706         /*
 707          * this won't give us the carrier frequency we really want
 708          * due to integer arithmetic, but we can accept this inaccuracy
 709          */
 710
 711         for (k = flag = 0; k < length; k += delay, flag = !flag) {
 712                 if (flag) {
 713                         off();
 714                         delay = space_width;
 715                 } else {
 716                         on();
 717                         delay = pulse_width;
 718                 }
 719                 safe_udelay(delay);
 720         }
 721         off();
 722 }
 723
 724 static void send_space(unsigned long length)
 725 {
 726         if (length == 0)
 727                 return;
 728         off();
 729         safe_udelay(length);
 730 }
 731 #else
 732 static void send_space(unsigned long len)
 733 {
 734         safe_udelay(len);
 735 }
 736
 737 static void send_pulse(unsigned long len)
 738 {
 739         long bytes_out = len / TIME_CONST;
 740         long time_left;
 741
 742         time_left = (long)len - (long)bytes_out * (long)TIME_CONST;
 743         if (bytes_out == 0) {
 744                 bytes_out++;
 745                 time_left = 0;
 746         }
 747         while (bytes_out--) {
 748                 outb(PULSE, io + UART_TX);
 749                 /* FIXME treba seriozne cakanie z char/serial.c */
 750                 while (!(inb(io + UART_LSR) & UART_LSR_THRE))
 751                         ;
 752         }
 753 #if 0
 754         if (time_left > 0)
 755                 safe_udelay(time_left);
 756 #endif
 757 }
 758 #endif
 759
 760 #ifdef CONFIG_SA1100_COLLIE
 761 static int sa1100_irda_set_power_collie(int state)
 762 {
 763         if (state) {
 764                 /*
 765                  *  0 - off
 766                  *  1 - short range, lowest power
 767                  *  2 - medium range, medium power
 768                  *  3 - maximum range, high power
 769                  */
 770                 ucb1200_set_io_direction(TC35143_GPIO_IR_ON,
 771                                          TC35143_IODIR_OUTPUT);
 772                 ucb1200_set_io(TC35143_GPIO_IR_ON, TC35143_IODAT_LOW);
 773                 udelay(100);
 774         } else {
 775                 /* OFF */
 776                 ucb1200_set_io_direction(TC35143_GPIO_IR_ON,
 777                                          TC35143_IODIR_OUTPUT);
 778                 ucb1200_set_io(TC35143_GPIO_IR_ON, TC35143_IODAT_HIGH);
 779         }
 780         return 0;
 781 }
 782 #endif
 783
 784 static int init_hardware(void)
 785 {
 786         unsigned long flags;
 787
 788         spin_lock_irqsave(&hardware_lock, flags);
 789         /* reset UART */
 790 #ifdef LIRC_ON_SA1100
 791 #ifdef CONFIG_SA1100_BITSY
 792         if (machine_is_bitsy()) {
 793                 printk(KERN_INFO "Power on IR module\n");
 794                 set_bitsy_egpio(EGPIO_BITSY_IR_ON);
 795         }
 796 #endif
 797 #ifdef CONFIG_SA1100_COLLIE
 798         sa1100_irda_set_power_collie(3);        /* power on */
 799 #endif
 800         sr.hscr0 = Ser2HSCR0;
 801
 802         sr.utcr0 = Ser2UTCR0;
 803         sr.utcr1 = Ser2UTCR1;
 804         sr.utcr2 = Ser2UTCR2;
 805         sr.utcr3 = Ser2UTCR3;
 806         sr.utcr4 = Ser2UTCR4;
 807
 808         sr.utdr = Ser2UTDR;
 809         sr.utsr0 = Ser2UTSR0;
 810         sr.utsr1 = Ser2UTSR1;
 811
 812         /* configure GPIO */
 813         /* output */
 814         PPDR |= PPC_TXD2;
 815         PSDR |= PPC_TXD2;
 816         /* set output to 0 */
 817         off();
 818
 819         /* Enable HP-SIR modulation, and ensure that the port is disabled. */
 820         Ser2UTCR3 = 0;
 821         Ser2HSCR0 = sr.hscr0 & (~HSCR0_HSSP);
 822
 823         /* clear status register to prevent unwanted interrupts */
 824         Ser2UTSR0 &= (UTSR0_RID | UTSR0_RBB | UTSR0_REB);
 825
 826         /* 7N1 */
 827         Ser2UTCR0 = UTCR0_1StpBit|UTCR0_7BitData;
 828         /* 115200 */
 829         Ser2UTCR1 = 0;
 830         Ser2UTCR2 = 1;
 831         /* use HPSIR, 1.6 usec pulses */
 832         Ser2UTCR4 = UTCR4_HPSIR|UTCR4_Z1_6us;
 833
 834         /* enable receiver, receive fifo interrupt */
 835         Ser2UTCR3 = UTCR3_RXE|UTCR3_RIE;
 836
 837         /* clear status register to prevent unwanted interrupts */
 838         Ser2UTSR0 &= (UTSR0_RID | UTSR0_RBB | UTSR0_REB);
 839
 840 #elif defined(LIRC_SIR_TEKRAM)
 841         /* disable FIFO */
 842         soutp(UART_FCR,
 843               UART_FCR_CLEAR_RCVR|
 844               UART_FCR_CLEAR_XMIT|
 845               UART_FCR_TRIGGER_1);
 846
 847         /* Set DLAB 0. */
 848         soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB));
 849
 850         /* First of all, disable all interrupts */
 851         soutp(UART_IER, sinp(UART_IER) &
 852               (~(UART_IER_MSI|UART_IER_RLSI|UART_IER_THRI|UART_IER_RDI)));
 853
 854         /* Set DLAB 1. */
 855         soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB);
 856
 857         /* Set divisor to 12 => 9600 Baud */
 858         soutp(UART_DLM, 0);
 859         soutp(UART_DLL, 12);
 860
 861         /* Set DLAB 0. */
 862         soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB));
 863
 864         /* power supply */
 865         soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
 866         safe_udelay(50*1000);
 867
 868         /* -DTR low -> reset PIC */
 869         soutp(UART_MCR, UART_MCR_RTS|UART_MCR_OUT2);
 870         udelay(1*1000);
 871
 872         soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
 873         udelay(100);
 874
 875
 876         /* -RTS low -> send control byte */
 877         soutp(UART_MCR, UART_MCR_DTR|UART_MCR_OUT2);
 878         udelay(7);
 879         soutp(UART_TX, TEKRAM_115200|TEKRAM_PW);
 880
 881         /* one byte takes ~1042 usec to transmit at 9600,8N1 */
 882         udelay(1500);
 883
 884         /* back to normal operation */
 885         soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
 886         udelay(50);
 887
 888         udelay(1500);
 889
 890         /* read previous control byte */
 891         printk(KERN_INFO LIRC_DRIVER_NAME
 892                ": 0x%02x\n", sinp(UART_RX));
 893
 894         /* Set DLAB 1. */
 895         soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB);
 896
 897         /* Set divisor to 1 => 115200 Baud */
 898         soutp(UART_DLM, 0);
 899         soutp(UART_DLL, 1);
 900
 901         /* Set DLAB 0, 8 Bit */
 902         soutp(UART_LCR, UART_LCR_WLEN8);
 903         /* enable interrupts */
 904         soutp(UART_IER, sinp(UART_IER)|UART_IER_RDI);
 905 #else
 906         outb(0, io + UART_MCR);
 907         outb(0, io + UART_IER);
 908         /* init UART */
 909         /* set DLAB, speed = 115200 */
 910         outb(UART_LCR_DLAB | UART_LCR_WLEN7, io + UART_LCR);
 911         outb(1, io + UART_DLL); outb(0, io + UART_DLM);
 912         /* 7N1+start = 9 bits at 115200 ~ 3 bits at 44000 */
 913         outb(UART_LCR_WLEN7, io + UART_LCR);
 914         /* FIFO operation */
 915         outb(UART_FCR_ENABLE_FIFO, io + UART_FCR);
 916         /* interrupts */
 917         /* outb(UART_IER_RLSI|UART_IER_RDI|UART_IER_THRI, io + UART_IER); */
 918         outb(UART_IER_RDI, io + UART_IER);
 919         /* turn on UART */
 920         outb(UART_MCR_DTR|UART_MCR_RTS|UART_MCR_OUT2, io + UART_MCR);
 921 #ifdef LIRC_SIR_ACTISYS_ACT200L
 922         init_act200();
 923 #elif defined(LIRC_SIR_ACTISYS_ACT220L)
 924         init_act220();
 925 #endif
 926 #endif
 927         spin_unlock_irqrestore(&hardware_lock, flags);
 928         return 0;
 929 }
 930
 931 static void drop_hardware(void)
 932 {
 933         unsigned long flags;
 934
 935         spin_lock_irqsave(&hardware_lock, flags);
 936
 937 #ifdef LIRC_ON_SA1100
 938         Ser2UTCR3 = 0;
 939
 940         Ser2UTCR0 = sr.utcr0;
 941         Ser2UTCR1 = sr.utcr1;
 942         Ser2UTCR2 = sr.utcr2;
 943         Ser2UTCR4 = sr.utcr4;
 944         Ser2UTCR3 = sr.utcr3;
 945
 946         Ser2HSCR0 = sr.hscr0;
 947 #ifdef CONFIG_SA1100_BITSY
 948         if (machine_is_bitsy())
 949                 clr_bitsy_egpio(EGPIO_BITSY_IR_ON);
 950 #endif
 951 #ifdef CONFIG_SA1100_COLLIE
 952         sa1100_irda_set_power_collie(0);        /* power off */
 953 #endif
 954 #else
 955         /* turn off interrupts */
 956         outb(0, io + UART_IER);
 957 #endif
 958         spin_unlock_irqrestore(&hardware_lock, flags);
 959 }
 960
 961 /* SECTION: Initialisation */
 962
 963 static int init_port(void)
 964 {
 965         int retval;
 966
 967         /* get I/O port access and IRQ line */
 968 #ifndef LIRC_ON_SA1100
 969         if (request_region(io, 8, LIRC_DRIVER_NAME) == NULL) {
 970                 printk(KERN_ERR LIRC_DRIVER_NAME
 971                        ": i/o port 0x%.4x already in use.\n", io);
 972                 return -EBUSY;
 973         }
 974 #endif
 975         retval = request_irq(irq, sir_interrupt, IRQF_DISABLED,
 976                              LIRC_DRIVER_NAME, NULL);
 977         if (retval < 0) {
 978 #               ifndef LIRC_ON_SA1100
 979                 release_region(io, 8);
 980 #               endif
 981                 printk(KERN_ERR LIRC_DRIVER_NAME
 982                         ": IRQ %d already in use.\n",
 983                         irq);
 984                 return retval;
 985         }
 986 #ifndef LIRC_ON_SA1100
 987         printk(KERN_INFO LIRC_DRIVER_NAME
 988                 ": I/O port 0x%.4x, IRQ %d.\n",
 989                 io, irq);
 990 #endif
 991
 992         init_timer(&timerlist);
 993         timerlist.function = sir_timeout;
 994         timerlist.data = 0xabadcafe;
 995
 996         return 0;
 997 }
 998
 999 static void drop_port(void)
1000 {
1001         free_irq(irq, NULL);
1002         del_timer_sync(&timerlist);
1003 #ifndef LIRC_ON_SA1100
1004         release_region(io, 8);
1005 #endif
1006 }
1007
1008 #ifdef LIRC_SIR_ACTISYS_ACT200L
1009 /* Crystal/Cirrus CS8130 IR transceiver, used in Actisys Act200L dongle */
1010 /* some code borrowed from Linux IRDA driver */
1011
1012 /* Register 0: Control register #1 */
1013 #define ACT200L_REG0    0x00
1014 #define ACT200L_TXEN    0x01 /* Enable transmitter */
1015 #define ACT200L_RXEN    0x02 /* Enable receiver */
1016 #define ACT200L_ECHO    0x08 /* Echo control chars */
1017
1018 /* Register 1: Control register #2 */
1019 #define ACT200L_REG1    0x10
1020 #define ACT200L_LODB    0x01 /* Load new baud rate count value */
1021 #define ACT200L_WIDE    0x04 /* Expand the maximum allowable pulse */
1022
1023 /* Register 3: Transmit mode register #2 */
1024 #define ACT200L_REG3    0x30
1025 #define ACT200L_B0      0x01 /* DataBits, 0=6, 1=7, 2=8, 3=9(8P)  */
1026 #define ACT200L_B1      0x02 /* DataBits, 0=6, 1=7, 2=8, 3=9(8P)  */
1027 #define ACT200L_CHSY    0x04 /* StartBit Synced 0=bittime, 1=startbit */
1028
1029 /* Register 4: Output Power register */
1030 #define ACT200L_REG4    0x40
1031 #define ACT200L_OP0     0x01 /* Enable LED1C output */
1032 #define ACT200L_OP1     0x02 /* Enable LED2C output */
1033 #define ACT200L_BLKR    0x04
1034
1035 /* Register 5: Receive Mode register */
1036 #define ACT200L_REG5    0x50
1037 #define ACT200L_RWIDL   0x01 /* fixed 1.6us pulse mode */
1038     /*.. other various IRDA bit modes, and TV remote modes..*/
1039
1040 /* Register 6: Receive Sensitivity register #1 */
1041 #define ACT200L_REG6    0x60
1042 #define ACT200L_RS0     0x01 /* receive threshold bit 0 */
1043 #define ACT200L_RS1     0x02 /* receive threshold bit 1 */
1044
1045 /* Register 7: Receive Sensitivity register #2 */
1046 #define ACT200L_REG7    0x70
1047 #define ACT200L_ENPOS   0x04 /* Ignore the falling edge */
1048
1049 /* Register 8,9: Baud Rate Divider register #1,#2 */
1050 #define ACT200L_REG8    0x80
1051 #define ACT200L_REG9    0x90
1052
1053 #define ACT200L_2400    0x5f
1054 #define ACT200L_9600    0x17
1055 #define ACT200L_19200   0x0b
1056 #define ACT200L_38400   0x05
1057 #define ACT200L_57600   0x03
1058 #define ACT200L_115200  0x01
1059
1060 /* Register 13: Control register #3 */
1061 #define ACT200L_REG13   0xd0
1062 #define ACT200L_SHDW    0x01 /* Enable access to shadow registers */
1063
1064 /* Register 15: Status register */
1065 #define ACT200L_REG15   0xf0
1066
1067 /* Register 21: Control register #4 */
1068 #define ACT200L_REG21   0x50
1069 #define ACT200L_EXCK    0x02 /* Disable clock output driver */
1070 #define ACT200L_OSCL    0x04 /* oscillator in low power, medium accuracy mode */
1071
1072 static void init_act200(void)
1073 {
1074         int i;
1075         __u8 control[] = {
1076                 ACT200L_REG15,
1077                 ACT200L_REG13 | ACT200L_SHDW,
1078                 ACT200L_REG21 | ACT200L_EXCK | ACT200L_OSCL,
1079                 ACT200L_REG13,
1080                 ACT200L_REG7  | ACT200L_ENPOS,
1081                 ACT200L_REG6  | ACT200L_RS0  | ACT200L_RS1,
1082                 ACT200L_REG5  | ACT200L_RWIDL,
1083                 ACT200L_REG4  | ACT200L_OP0  | ACT200L_OP1 | ACT200L_BLKR,
1084                 ACT200L_REG3  | ACT200L_B0,
1085                 ACT200L_REG0  | ACT200L_TXEN | ACT200L_RXEN,
1086                 ACT200L_REG8 |  (ACT200L_115200       & 0x0f),
1087                 ACT200L_REG9 | ((ACT200L_115200 >> 4) & 0x0f),
1088                 ACT200L_REG1 | ACT200L_LODB | ACT200L_WIDE
1089         };
1090
1091         /* Set DLAB 1. */
1092         soutp(UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN8);
1093
1094         /* Set divisor to 12 => 9600 Baud */
1095         soutp(UART_DLM, 0);
1096         soutp(UART_DLL, 12);
1097
1098         /* Set DLAB 0. */
1099         soutp(UART_LCR, UART_LCR_WLEN8);
1100         /* Set divisor to 12 => 9600 Baud */
1101
1102         /* power supply */
1103         soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
1104         for (i = 0; i < 50; i++)
1105                 safe_udelay(1000);
1106
1107                 /* Reset the dongle : set RTS low for 25 ms */
1108         soutp(UART_MCR, UART_MCR_DTR|UART_MCR_OUT2);
1109         for (i = 0; i < 25; i++)
1110                 udelay(1000);
1111
1112         soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
1113         udelay(100);
1114
1115         /* Clear DTR and set RTS to enter command mode */
1116         soutp(UART_MCR, UART_MCR_RTS|UART_MCR_OUT2);
1117         udelay(7);
1118
1119         /* send out the control register settings for 115K 7N1 SIR operation */
1120         for (i = 0; i < sizeof(control); i++) {
1121                 soutp(UART_TX, control[i]);
1122                 /* one byte takes ~1042 usec to transmit at 9600,8N1 */
1123                 udelay(1500);
1124         }
1125
1126         /* back to normal operation */
1127         soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
1128         udelay(50);
1129
1130         udelay(1500);
1131         soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB);
1132
1133         /* Set DLAB 1. */
1134         soutp(UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN7);
1135
1136         /* Set divisor to 1 => 115200 Baud */
1137         soutp(UART_DLM, 0);
1138         soutp(UART_DLL, 1);
1139
1140         /* Set DLAB 0. */
1141         soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB));
1142
1143         /* Set DLAB 0, 7 Bit */
1144         soutp(UART_LCR, UART_LCR_WLEN7);
1145
1146         /* enable interrupts */
1147         soutp(UART_IER, sinp(UART_IER)|UART_IER_RDI);
1148 }
1149 #endif
1150
1151 #ifdef LIRC_SIR_ACTISYS_ACT220L
1152 /*
1153  * Derived from linux IrDA driver (net/irda/actisys.c)
1154  * Drop me a mail for any kind of comment: maxx@spaceboyz.net
1155  */
1156
1157 void init_act220(void)
1158 {
1159         int i;
1160
1161         /* DLAB 1 */
1162         soutp(UART_LCR, UART_LCR_DLAB|UART_LCR_WLEN7);
1163
1164         /* 9600 baud */
1165         soutp(UART_DLM, 0);
1166         soutp(UART_DLL, 12);
1167
1168         /* DLAB 0 */
1169         soutp(UART_LCR, UART_LCR_WLEN7);
1170
1171         /* reset the dongle, set DTR low for 10us */
1172         soutp(UART_MCR, UART_MCR_RTS|UART_MCR_OUT2);
1173         udelay(10);
1174
1175         /* back to normal (still 9600) */
1176         soutp(UART_MCR, UART_MCR_DTR|UART_MCR_RTS|UART_MCR_OUT2);
1177
1178         /*
1179          * send RTS pulses until we reach 115200
1180          * i hope this is really the same for act220l/act220l+
1181          */
1182         for (i = 0; i < 3; i++) {
1183                 udelay(10);
1184                 /* set RTS low for 10 us */
1185                 soutp(UART_MCR, UART_MCR_DTR|UART_MCR_OUT2);
1186                 udelay(10);
1187                 /* set RTS high for 10 us */
1188                 soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2);
1189         }
1190
1191         /* back to normal operation */
1192         udelay(1500); /* better safe than sorry ;) */
1193
1194         /* Set DLAB 1. */
1195         soutp(UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN7);
1196
1197         /* Set divisor to 1 => 115200 Baud */
1198         soutp(UART_DLM, 0);
1199         soutp(UART_DLL, 1);
1200
1201         /* Set DLAB 0, 7 Bit */
1202         /* The dongle doesn't seem to have any problems with operation at 7N1 */
1203         soutp(UART_LCR, UART_LCR_WLEN7);
1204
1205         /* enable interrupts */
1206         soutp(UART_IER, UART_IER_RDI);
1207 }
1208 #endif
1209
1210 static int init_lirc_sir(void)
1211 {
1212         int retval;
1213
1214         init_waitqueue_head(&lirc_read_queue);
1215         retval = init_port();
1216         if (retval < 0)
1217                 return retval;
1218         init_hardware();
1219         printk(KERN_INFO LIRC_DRIVER_NAME
1220                 ": Installed.\n");
1221         return 0;
1222 }
1223
1224
1225 static int __init lirc_sir_init(void)
1226 {
1227         int retval;
1228
1229         retval = init_chrdev();
1230         if (retval < 0)
1231                 return retval;
1232         retval = init_lirc_sir();
1233         if (retval) {
1234                 drop_chrdev();
1235                 return retval;
1236         }
1237         return 0;
1238 }
1239
1240 static void __exit lirc_sir_exit(void)
1241 {
1242         drop_hardware();
1243         drop_chrdev();
1244         drop_port();
1245         printk(KERN_INFO LIRC_DRIVER_NAME ": Uninstalled.\n");
1246 }
1247
1248 module_init(lirc_sir_init);
1249 module_exit(lirc_sir_exit);
1250
1251 #ifdef LIRC_SIR_TEKRAM
1252 MODULE_DESCRIPTION("Infrared receiver driver for Tekram Irmate 210");
1253 MODULE_AUTHOR("Christoph Bartelmus");
1254 #elif defined(LIRC_ON_SA1100)
1255 MODULE_DESCRIPTION("LIRC driver for StrongARM SA1100 embedded microprocessor");
1256 MODULE_AUTHOR("Christoph Bartelmus");
1257 #elif defined(LIRC_SIR_ACTISYS_ACT200L)
1258 MODULE_DESCRIPTION("LIRC driver for Actisys Act200L");
1259 MODULE_AUTHOR("Karl Bongers");
1260 #elif defined(LIRC_SIR_ACTISYS_ACT220L)
1261 MODULE_DESCRIPTION("LIRC driver for Actisys Act220L(+)");
1262 MODULE_AUTHOR("Jan Roemisch");
1263 #else
1264 MODULE_DESCRIPTION("Infrared receiver driver for SIR type serial ports");
1265 MODULE_AUTHOR("Milan Pikula");
1266 #endif
1267 MODULE_LICENSE("GPL");
1268
1269 #ifdef LIRC_ON_SA1100
1270 module_param(irq, int, S_IRUGO);
1271 MODULE_PARM_DESC(irq, "Interrupt (16)");
1272 #else
1273 module_param(io, int, S_IRUGO);
1274 MODULE_PARM_DESC(io, "I/O address base (0x3f8 or 0x2f8)");
1275
1276 module_param(irq, int, S_IRUGO);
1277 MODULE_PARM_DESC(irq, "Interrupt (4 or 3)");
1278
1279 module_param(threshold, int, S_IRUGO);
1280 MODULE_PARM_DESC(threshold, "space detection threshold (3)");
1281 #endif
1282
1283 module_param(debug, bool, S_IRUGO | S_IWUSR);
1284 MODULE_PARM_DESC(debug, "Enable debugging messages");