drivers/scsi/qla2xxx/qla_sup.c

   1 /*
   2  * QLogic Fibre Channel HBA Driver
   3  * Copyright (c)  2003-2008 QLogic Corporation
   4  *
   5  * See LICENSE.qla2xxx for copyright and licensing details.
   6  */
   7 #include "qla_def.h"
   8
   9 #include <linux/delay.h>
  10 #include <linux/vmalloc.h>
  11 #include <asm/uaccess.h>
  12
  13 /*
  14  * NVRAM support routines
  15  */
  16
  17 /**
  18  * qla2x00_lock_nvram_access() -
  19  * @ha: HA context
  20  */
  21 static void
  22 qla2x00_lock_nvram_access(struct qla_hw_data *ha)
  23 {
  24         uint16_t data;
  25         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  26
  27         if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
  28                 data = RD_REG_WORD(&reg->nvram);
  29                 while (data & NVR_BUSY) {
  30                         udelay(100);
  31                         data = RD_REG_WORD(&reg->nvram);
  32                 }
  33
  34                 /* Lock resource */
  35                 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
  36                 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  37                 udelay(5);
  38                 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  39                 while ((data & BIT_0) == 0) {
  40                         /* Lock failed */
  41                         udelay(100);
  42                         WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
  43                         RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  44                         udelay(5);
  45                         data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  46                 }
  47         }
  48 }
  49
  50 /**
  51  * qla2x00_unlock_nvram_access() -
  52  * @ha: HA context
  53  */
  54 static void
  55 qla2x00_unlock_nvram_access(struct qla_hw_data *ha)
  56 {
  57         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  58
  59         if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
  60                 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0);
  61                 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  62         }
  63 }
  64
  65 /**
  66  * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
  67  * @ha: HA context
  68  * @data: Serial interface selector
  69  */
  70 static void
  71 qla2x00_nv_write(struct qla_hw_data *ha, uint16_t data)
  72 {
  73         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  74
  75         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
  76         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
  77         NVRAM_DELAY();
  78         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_CLOCK |
  79             NVR_WRT_ENABLE);
  80         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
  81         NVRAM_DELAY();
  82         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
  83         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
  84         NVRAM_DELAY();
  85 }
  86
  87 /**
  88  * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
  89  *      NVRAM.
  90  * @ha: HA context
  91  * @nv_cmd: NVRAM command
  92  *
  93  * Bit definitions for NVRAM command:
  94  *
  95  *      Bit 26     = start bit
  96  *      Bit 25, 24 = opcode
  97  *      Bit 23-16  = address
  98  *      Bit 15-0   = write data
  99  *
 100  * Returns the word read from nvram @addr.
 101  */
 102 static uint16_t
 103 qla2x00_nvram_request(struct qla_hw_data *ha, uint32_t nv_cmd)
 104 {
 105         uint8_t         cnt;
 106         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 107         uint16_t        data = 0;
 108         uint16_t        reg_data;
 109
 110         /* Send command to NVRAM. */
 111         nv_cmd <<= 5;
 112         for (cnt = 0; cnt < 11; cnt++) {
 113                 if (nv_cmd & BIT_31)
 114                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 115                 else
 116                         qla2x00_nv_write(ha, 0);
 117                 nv_cmd <<= 1;
 118         }
 119
 120         /* Read data from NVRAM. */
 121         for (cnt = 0; cnt < 16; cnt++) {
 122                 WRT_REG_WORD(&reg->nvram, NVR_SELECT | NVR_CLOCK);
 123                 RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
 124                 NVRAM_DELAY();
 125                 data <<= 1;
 126                 reg_data = RD_REG_WORD(&reg->nvram);
 127                 if (reg_data & NVR_DATA_IN)
 128                         data |= BIT_0;
 129                 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 130                 RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
 131                 NVRAM_DELAY();
 132         }
 133
 134         /* Deselect chip. */
 135         WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
 136         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 137         NVRAM_DELAY();
 138
 139         return data;
 140 }
 141
 142
 143 /**
 144  * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
 145  *      request routine to get the word from NVRAM.
 146  * @ha: HA context
 147  * @addr: Address in NVRAM to read
 148  *
 149  * Returns the word read from nvram @addr.
 150  */
 151 static uint16_t
 152 qla2x00_get_nvram_word(struct qla_hw_data *ha, uint32_t addr)
 153 {
 154         uint16_t        data;
 155         uint32_t        nv_cmd;
 156
 157         nv_cmd = addr << 16;
 158         nv_cmd |= NV_READ_OP;
 159         data = qla2x00_nvram_request(ha, nv_cmd);
 160
 161         return (data);
 162 }
 163
 164 /**
 165  * qla2x00_nv_deselect() - Deselect NVRAM operations.
 166  * @ha: HA context
 167  */
 168 static void
 169 qla2x00_nv_deselect(struct qla_hw_data *ha)
 170 {
 171         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 172
 173         WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
 174         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 175         NVRAM_DELAY();
 176 }
 177
 178 /**
 179  * qla2x00_write_nvram_word() - Write NVRAM data.
 180  * @ha: HA context
 181  * @addr: Address in NVRAM to write
 182  * @data: word to program
 183  */
 184 static void
 185 qla2x00_write_nvram_word(struct qla_hw_data *ha, uint32_t addr, uint16_t data)
 186 {
 187         int count;
 188         uint16_t word;
 189         uint32_t nv_cmd, wait_cnt;
 190         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 191
 192         qla2x00_nv_write(ha, NVR_DATA_OUT);
 193         qla2x00_nv_write(ha, 0);
 194         qla2x00_nv_write(ha, 0);
 195
 196         for (word = 0; word < 8; word++)
 197                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 198
 199         qla2x00_nv_deselect(ha);
 200
 201         /* Write data */
 202         nv_cmd = (addr << 16) | NV_WRITE_OP;
 203         nv_cmd |= data;
 204         nv_cmd <<= 5;
 205         for (count = 0; count < 27; count++) {
 206                 if (nv_cmd & BIT_31)
 207                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 208                 else
 209                         qla2x00_nv_write(ha, 0);
 210
 211                 nv_cmd <<= 1;
 212         }
 213
 214         qla2x00_nv_deselect(ha);
 215
 216         /* Wait for NVRAM to become ready */
 217         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 218         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 219         wait_cnt = NVR_WAIT_CNT;
 220         do {
 221                 if (!--wait_cnt) {
 222                         DEBUG9_10(qla_printk(KERN_WARNING, ha,
 223                             "NVRAM didn't go ready...\n"));
 224                         break;
 225                 }
 226                 NVRAM_DELAY();
 227                 word = RD_REG_WORD(&reg->nvram);
 228         } while ((word & NVR_DATA_IN) == 0);
 229
 230         qla2x00_nv_deselect(ha);
 231
 232         /* Disable writes */
 233         qla2x00_nv_write(ha, NVR_DATA_OUT);
 234         for (count = 0; count < 10; count++)
 235                 qla2x00_nv_write(ha, 0);
 236
 237         qla2x00_nv_deselect(ha);
 238 }
 239
 240 static int
 241 qla2x00_write_nvram_word_tmo(struct qla_hw_data *ha, uint32_t addr,
 242         uint16_t data, uint32_t tmo)
 243 {
 244         int ret, count;
 245         uint16_t word;
 246         uint32_t nv_cmd;
 247         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 248
 249         ret = QLA_SUCCESS;
 250
 251         qla2x00_nv_write(ha, NVR_DATA_OUT);
 252         qla2x00_nv_write(ha, 0);
 253         qla2x00_nv_write(ha, 0);
 254
 255         for (word = 0; word < 8; word++)
 256                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 257
 258         qla2x00_nv_deselect(ha);
 259
 260         /* Write data */
 261         nv_cmd = (addr << 16) | NV_WRITE_OP;
 262         nv_cmd |= data;
 263         nv_cmd <<= 5;
 264         for (count = 0; count < 27; count++) {
 265                 if (nv_cmd & BIT_31)
 266                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 267                 else
 268                         qla2x00_nv_write(ha, 0);
 269
 270                 nv_cmd <<= 1;
 271         }
 272
 273         qla2x00_nv_deselect(ha);
 274
 275         /* Wait for NVRAM to become ready */
 276         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 277         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 278         do {
 279                 NVRAM_DELAY();
 280                 word = RD_REG_WORD(&reg->nvram);
 281                 if (!--tmo) {
 282                         ret = QLA_FUNCTION_FAILED;
 283                         break;
 284                 }
 285         } while ((word & NVR_DATA_IN) == 0);
 286
 287         qla2x00_nv_deselect(ha);
 288
 289         /* Disable writes */
 290         qla2x00_nv_write(ha, NVR_DATA_OUT);
 291         for (count = 0; count < 10; count++)
 292                 qla2x00_nv_write(ha, 0);
 293
 294         qla2x00_nv_deselect(ha);
 295
 296         return ret;
 297 }
 298
 299 /**
 300  * qla2x00_clear_nvram_protection() -
 301  * @ha: HA context
 302  */
 303 static int
 304 qla2x00_clear_nvram_protection(struct qla_hw_data *ha)
 305 {
 306         int ret, stat;
 307         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 308         uint32_t word, wait_cnt;
 309         uint16_t wprot, wprot_old;
 310
 311         /* Clear NVRAM write protection. */
 312         ret = QLA_FUNCTION_FAILED;
 313
 314         wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
 315         stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base,
 316             __constant_cpu_to_le16(0x1234), 100000);
 317         wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
 318         if (stat != QLA_SUCCESS || wprot != 0x1234) {
 319                 /* Write enable. */
 320                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 321                 qla2x00_nv_write(ha, 0);
 322                 qla2x00_nv_write(ha, 0);
 323                 for (word = 0; word < 8; word++)
 324                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 325
 326                 qla2x00_nv_deselect(ha);
 327
 328                 /* Enable protection register. */
 329                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 330                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
 331                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
 332                 for (word = 0; word < 8; word++)
 333                         qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
 334
 335                 qla2x00_nv_deselect(ha);
 336
 337                 /* Clear protection register (ffff is cleared). */
 338                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 339                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 340                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 341                 for (word = 0; word < 8; word++)
 342                         qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
 343
 344                 qla2x00_nv_deselect(ha);
 345
 346                 /* Wait for NVRAM to become ready. */
 347                 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 348                 RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
 349                 wait_cnt = NVR_WAIT_CNT;
 350                 do {
 351                         if (!--wait_cnt) {
 352                                 DEBUG9_10(qla_printk(KERN_WARNING, ha,
 353                                     "NVRAM didn't go ready...\n"));
 354                                 break;
 355                         }
 356                         NVRAM_DELAY();
 357                         word = RD_REG_WORD(&reg->nvram);
 358                 } while ((word & NVR_DATA_IN) == 0);
 359
 360                 if (wait_cnt)
 361                         ret = QLA_SUCCESS;
 362         } else
 363                 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old);
 364
 365         return ret;
 366 }
 367
 368 static void
 369 qla2x00_set_nvram_protection(struct qla_hw_data *ha, int stat)
 370 {
 371         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 372         uint32_t word, wait_cnt;
 373
 374         if (stat != QLA_SUCCESS)
 375                 return;
 376
 377         /* Set NVRAM write protection. */
 378         /* Write enable. */
 379         qla2x00_nv_write(ha, NVR_DATA_OUT);
 380         qla2x00_nv_write(ha, 0);
 381         qla2x00_nv_write(ha, 0);
 382         for (word = 0; word < 8; word++)
 383                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 384
 385         qla2x00_nv_deselect(ha);
 386
 387         /* Enable protection register. */
 388         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 389         qla2x00_nv_write(ha, NVR_PR_ENABLE);
 390         qla2x00_nv_write(ha, NVR_PR_ENABLE);
 391         for (word = 0; word < 8; word++)
 392                 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
 393
 394         qla2x00_nv_deselect(ha);
 395
 396         /* Enable protection register. */
 397         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 398         qla2x00_nv_write(ha, NVR_PR_ENABLE);
 399         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 400         for (word = 0; word < 8; word++)
 401                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
 402
 403         qla2x00_nv_deselect(ha);
 404
 405         /* Wait for NVRAM to become ready. */
 406         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 407         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 408         wait_cnt = NVR_WAIT_CNT;
 409         do {
 410                 if (!--wait_cnt) {
 411                         DEBUG9_10(qla_printk(KERN_WARNING, ha,
 412                             "NVRAM didn't go ready...\n"));
 413                         break;
 414                 }
 415                 NVRAM_DELAY();
 416                 word = RD_REG_WORD(&reg->nvram);
 417         } while ((word & NVR_DATA_IN) == 0);
 418 }
 419
 420
 421 /*****************************************************************************/
 422 /* Flash Manipulation Routines                                               */
 423 /*****************************************************************************/
 424
 425 #define OPTROM_BURST_SIZE       0x1000
 426 #define OPTROM_BURST_DWORDS     (OPTROM_BURST_SIZE / 4)
 427
 428 static inline uint32_t
 429 flash_conf_addr(struct qla_hw_data *ha, uint32_t faddr)
 430 {
 431         return ha->flash_conf_off | faddr;
 432 }
 433
 434 static inline uint32_t
 435 flash_data_addr(struct qla_hw_data *ha, uint32_t faddr)
 436 {
 437         return ha->flash_data_off | faddr;
 438 }
 439
 440 static inline uint32_t
 441 nvram_conf_addr(struct qla_hw_data *ha, uint32_t naddr)
 442 {
 443         return ha->nvram_conf_off | naddr;
 444 }
 445
 446 static inline uint32_t
 447 nvram_data_addr(struct qla_hw_data *ha, uint32_t naddr)
 448 {
 449         return ha->nvram_data_off | naddr;
 450 }
 451
 452 static uint32_t
 453 qla24xx_read_flash_dword(struct qla_hw_data *ha, uint32_t addr)
 454 {
 455         int rval;
 456         uint32_t cnt, data;
 457         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 458
 459         WRT_REG_DWORD(&reg->flash_addr, addr & ~FARX_DATA_FLAG);
 460         /* Wait for READ cycle to complete. */
 461         rval = QLA_SUCCESS;
 462         for (cnt = 3000;
 463             (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) == 0 &&
 464             rval == QLA_SUCCESS; cnt--) {
 465                 if (cnt)
 466                         udelay(10);
 467                 else
 468                         rval = QLA_FUNCTION_TIMEOUT;
 469                 cond_resched();
 470         }
 471
 472         /* TODO: What happens if we time out? */
 473         data = 0xDEADDEAD;
 474         if (rval == QLA_SUCCESS)
 475                 data = RD_REG_DWORD(&reg->flash_data);
 476
 477         return data;
 478 }
 479
 480 uint32_t *
 481 qla24xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
 482     uint32_t dwords)
 483 {
 484         uint32_t i;
 485         struct qla_hw_data *ha = vha->hw;
 486
 487         /* Dword reads to flash. */
 488         for (i = 0; i < dwords; i++, faddr++)
 489                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
 490                     flash_data_addr(ha, faddr)));
 491
 492         return dwptr;
 493 }
 494
 495 static int
 496 qla24xx_write_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t data)
 497 {
 498         int rval;
 499         uint32_t cnt;
 500         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 501
 502         WRT_REG_DWORD(&reg->flash_data, data);
 503         RD_REG_DWORD(&reg->flash_data);         /* PCI Posting. */
 504         WRT_REG_DWORD(&reg->flash_addr, addr | FARX_DATA_FLAG);
 505         /* Wait for Write cycle to complete. */
 506         rval = QLA_SUCCESS;
 507         for (cnt = 500000; (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) &&
 508             rval == QLA_SUCCESS; cnt--) {
 509                 if (cnt)
 510                         udelay(10);
 511                 else
 512                         rval = QLA_FUNCTION_TIMEOUT;
 513                 cond_resched();
 514         }
 515         return rval;
 516 }
 517
 518 static void
 519 qla24xx_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
 520     uint8_t *flash_id)
 521 {
 522         uint32_t ids;
 523
 524         ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x03ab));
 525         *man_id = LSB(ids);
 526         *flash_id = MSB(ids);
 527
 528         /* Check if man_id and flash_id are valid. */
 529         if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) {
 530                 /* Read information using 0x9f opcode
 531                  * Device ID, Mfg ID would be read in the format:
 532                  *   <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID>
 533                  * Example: ATMEL 0x00 01 45 1F
 534                  * Extract MFG and Dev ID from last two bytes.
 535                  */
 536                 ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x009f));
 537                 *man_id = LSB(ids);
 538                 *flash_id = MSB(ids);
 539         }
 540 }
 541
 542 static int
 543 qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start)
 544 {
 545         const char *loc, *locations[] = { "DEF", "PCI" };
 546         uint32_t pcihdr, pcids;
 547         uint32_t *dcode;
 548         uint8_t *buf, *bcode, last_image;
 549         uint16_t cnt, chksum, *wptr;
 550         struct qla_flt_location *fltl;
 551         struct qla_hw_data *ha = vha->hw;
 552         struct req_que *req = ha->req_q_map[0];
 553
 554         /*
 555          * FLT-location structure resides after the last PCI region.
 556          */
 557
 558         /* Begin with sane defaults. */
 559         loc = locations[0];
 560         *start = 0;
 561         if (IS_QLA24XX_TYPE(ha))
 562                 *start = FA_FLASH_LAYOUT_ADDR_24;
 563         else if (IS_QLA25XX(ha))
 564                 *start = FA_FLASH_LAYOUT_ADDR;
 565         else if (IS_QLA81XX(ha))
 566                 *start = FA_FLASH_LAYOUT_ADDR_81;
 567         /* Begin with first PCI expansion ROM header. */
 568         buf = (uint8_t *)req->ring;
 569         dcode = (uint32_t *)req->ring;
 570         pcihdr = 0;
 571         last_image = 1;
 572         do {
 573                 /* Verify PCI expansion ROM header. */
 574                 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
 575                 bcode = buf + (pcihdr % 4);
 576                 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa)
 577                         goto end;
 578
 579                 /* Locate PCI data structure. */
 580                 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
 581                 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
 582                 bcode = buf + (pcihdr % 4);
 583
 584                 /* Validate signature of PCI data structure. */
 585                 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
 586                     bcode[0x2] != 'I' || bcode[0x3] != 'R')
 587                         goto end;
 588
 589                 last_image = bcode[0x15] & BIT_7;
 590
 591                 /* Locate next PCI expansion ROM. */
 592                 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
 593         } while (!last_image);
 594
 595         /* Now verify FLT-location structure. */
 596         fltl = (struct qla_flt_location *)req->ring;
 597         qla24xx_read_flash_data(vha, dcode, pcihdr >> 2,
 598             sizeof(struct qla_flt_location) >> 2);
 599         if (fltl->sig[0] != 'Q' || fltl->sig[1] != 'F' ||
 600             fltl->sig[2] != 'L' || fltl->sig[3] != 'T')
 601                 goto end;
 602
 603         wptr = (uint16_t *)req->ring;
 604         cnt = sizeof(struct qla_flt_location) >> 1;
 605         for (chksum = 0; cnt; cnt--)
 606                 chksum += le16_to_cpu(*wptr++);
 607         if (chksum) {
 608                 qla_printk(KERN_ERR, ha,
 609                     "Inconsistent FLTL detected: checksum=0x%x.\n", chksum);
 610                 qla2x00_dump_buffer(buf, sizeof(struct qla_flt_location));
 611                 return QLA_FUNCTION_FAILED;
 612         }
 613
 614         /* Good data.  Use specified location. */
 615         loc = locations[1];
 616         *start = (le16_to_cpu(fltl->start_hi) << 16 |
 617             le16_to_cpu(fltl->start_lo)) >> 2;
 618 end:
 619         DEBUG2(qla_printk(KERN_DEBUG, ha, "FLTL[%s] = 0x%x.\n", loc, *start));
 620         return QLA_SUCCESS;
 621 }
 622
 623 static void
 624 qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr)
 625 {
 626         const char *loc, *locations[] = { "DEF", "FLT" };
 627         const uint32_t def_fw[] =
 628                 { FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR_81 };
 629         const uint32_t def_boot[] =
 630                 { FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR_81 };
 631         const uint32_t def_vpd_nvram[] =
 632                 { FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR_81 };
 633         const uint32_t def_vpd0[] =
 634                 { 0, 0, FA_VPD0_ADDR_81 };
 635         const uint32_t def_vpd1[] =
 636                 { 0, 0, FA_VPD1_ADDR_81 };
 637         const uint32_t def_nvram0[] =
 638                 { 0, 0, FA_NVRAM0_ADDR_81 };
 639         const uint32_t def_nvram1[] =
 640                 { 0, 0, FA_NVRAM1_ADDR_81 };
 641         const uint32_t def_fdt[] =
 642                 { FA_FLASH_DESCR_ADDR_24, FA_FLASH_DESCR_ADDR,
 643                         FA_FLASH_DESCR_ADDR_81 };
 644         const uint32_t def_npiv_conf0[] =
 645                 { FA_NPIV_CONF0_ADDR_24, FA_NPIV_CONF0_ADDR,
 646                         FA_NPIV_CONF0_ADDR_81 };
 647         const uint32_t def_npiv_conf1[] =
 648                 { FA_NPIV_CONF1_ADDR_24, FA_NPIV_CONF1_ADDR,
 649                         FA_NPIV_CONF1_ADDR_81 };
 650         uint32_t def;
 651         uint16_t *wptr;
 652         uint16_t cnt, chksum;
 653         uint32_t start;
 654         struct qla_flt_header *flt;
 655         struct qla_flt_region *region;
 656         struct qla_hw_data *ha = vha->hw;
 657         struct req_que *req = ha->req_q_map[0];
 658
 659         ha->flt_region_flt = flt_addr;
 660         wptr = (uint16_t *)req->ring;
 661         flt = (struct qla_flt_header *)req->ring;
 662         region = (struct qla_flt_region *)&flt[1];
 663         ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
 664             flt_addr << 2, OPTROM_BURST_SIZE);
 665         if (*wptr == __constant_cpu_to_le16(0xffff))
 666                 goto no_flash_data;
 667         if (flt->version != __constant_cpu_to_le16(1)) {
 668                 DEBUG2(qla_printk(KERN_INFO, ha, "Unsupported FLT detected: "
 669                     "version=0x%x length=0x%x checksum=0x%x.\n",
 670                     le16_to_cpu(flt->version), le16_to_cpu(flt->length),
 671                     le16_to_cpu(flt->checksum)));
 672                 goto no_flash_data;
 673         }
 674
 675         cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
 676         for (chksum = 0; cnt; cnt--)
 677                 chksum += le16_to_cpu(*wptr++);
 678         if (chksum) {
 679                 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FLT detected: "
 680                     "version=0x%x length=0x%x checksum=0x%x.\n",
 681                     le16_to_cpu(flt->version), le16_to_cpu(flt->length),
 682                     chksum));
 683                 goto no_flash_data;
 684         }
 685
 686         loc = locations[1];
 687         cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
 688         for ( ; cnt; cnt--, region++) {
 689                 /* Store addresses as DWORD offsets. */
 690                 start = le32_to_cpu(region->start) >> 2;
 691
 692                 DEBUG3(qla_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x "
 693                     "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start,
 694                     le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size)));
 695
 696                 switch (le32_to_cpu(region->code) & 0xff) {
 697                 case FLT_REG_FW:
 698                         ha->flt_region_fw = start;
 699                         break;
 700                 case FLT_REG_BOOT_CODE:
 701                         ha->flt_region_boot = start;
 702                         break;
 703                 case FLT_REG_VPD_0:
 704                         ha->flt_region_vpd_nvram = start;
 705                         if (!(PCI_FUNC(ha->pdev->devfn) & 1))
 706                                 ha->flt_region_vpd = start;
 707                         break;
 708                 case FLT_REG_VPD_1:
 709                         if (PCI_FUNC(ha->pdev->devfn) & 1)
 710                                 ha->flt_region_vpd = start;
 711                         break;
 712                 case FLT_REG_NVRAM_0:
 713                         if (!(PCI_FUNC(ha->pdev->devfn) & 1))
 714                                 ha->flt_region_nvram = start;
 715                         break;
 716                 case FLT_REG_NVRAM_1:
 717                         if (PCI_FUNC(ha->pdev->devfn) & 1)
 718                                 ha->flt_region_nvram = start;
 719                         break;
 720                 case FLT_REG_FDT:
 721                         ha->flt_region_fdt = start;
 722                         break;
 723                 case FLT_REG_NPIV_CONF_0:
 724                         if (!(PCI_FUNC(ha->pdev->devfn) & 1))
 725                                 ha->flt_region_npiv_conf = start;
 726                         break;
 727                 case FLT_REG_NPIV_CONF_1:
 728                         if (PCI_FUNC(ha->pdev->devfn) & 1)
 729                                 ha->flt_region_npiv_conf = start;
 730                         break;
 731                 }
 732         }
 733         goto done;
 734
 735 no_flash_data:
 736         /* Use hardcoded defaults. */
 737         loc = locations[0];
 738         def = 0;
 739         if (IS_QLA24XX_TYPE(ha))
 740                 def = 0;
 741         else if (IS_QLA25XX(ha))
 742                 def = 1;
 743         else if (IS_QLA81XX(ha))
 744                 def = 2;
 745         ha->flt_region_fw = def_fw[def];
 746         ha->flt_region_boot = def_boot[def];
 747         ha->flt_region_vpd_nvram = def_vpd_nvram[def];
 748         ha->flt_region_vpd = !(PCI_FUNC(ha->pdev->devfn) & 1) ?
 749             def_vpd0[def]: def_vpd1[def];
 750         ha->flt_region_nvram = !(PCI_FUNC(ha->pdev->devfn) & 1) ?
 751             def_nvram0[def]: def_nvram1[def];
 752         ha->flt_region_fdt = def_fdt[def];
 753         ha->flt_region_npiv_conf = !(PCI_FUNC(ha->pdev->devfn) & 1) ?
 754             def_npiv_conf0[def]: def_npiv_conf1[def];
 755 done:
 756         DEBUG2(qla_printk(KERN_DEBUG, ha, "FLT[%s]: boot=0x%x fw=0x%x "
 757             "vpd_nvram=0x%x vpd=0x%x nvram=0x%x fdt=0x%x flt=0x%x "
 758             "npiv=0x%x.\n", loc, ha->flt_region_boot, ha->flt_region_fw,
 759             ha->flt_region_vpd_nvram, ha->flt_region_vpd, ha->flt_region_nvram,
 760             ha->flt_region_fdt, ha->flt_region_flt, ha->flt_region_npiv_conf));
 761 }
 762
 763 static void
 764 qla2xxx_get_fdt_info(scsi_qla_host_t *vha)
 765 {
 766 #define FLASH_BLK_SIZE_4K       0x1000
 767 #define FLASH_BLK_SIZE_32K      0x8000
 768 #define FLASH_BLK_SIZE_64K      0x10000
 769         const char *loc, *locations[] = { "MID", "FDT" };
 770         uint16_t cnt, chksum;
 771         uint16_t *wptr;
 772         struct qla_fdt_layout *fdt;
 773         uint8_t man_id, flash_id;
 774         uint16_t mid, fid;
 775         struct qla_hw_data *ha = vha->hw;
 776         struct req_que *req = ha->req_q_map[0];
 777
 778         wptr = (uint16_t *)req->ring;
 779         fdt = (struct qla_fdt_layout *)req->ring;
 780         ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
 781             ha->flt_region_fdt << 2, OPTROM_BURST_SIZE);
 782         if (*wptr == __constant_cpu_to_le16(0xffff))
 783                 goto no_flash_data;
 784         if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
 785             fdt->sig[3] != 'D')
 786                 goto no_flash_data;
 787
 788         for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
 789             cnt++)
 790                 chksum += le16_to_cpu(*wptr++);
 791         if (chksum) {
 792                 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FDT detected: "
 793                     "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0],
 794                     le16_to_cpu(fdt->version)));
 795                 DEBUG9(qla2x00_dump_buffer((uint8_t *)fdt, sizeof(*fdt)));
 796                 goto no_flash_data;
 797         }
 798
 799         loc = locations[1];
 800         mid = le16_to_cpu(fdt->man_id);
 801         fid = le16_to_cpu(fdt->id);
 802         ha->fdt_wrt_disable = fdt->wrt_disable_bits;
 803         ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0300 | fdt->erase_cmd);
 804         ha->fdt_block_size = le32_to_cpu(fdt->block_size);
 805         if (fdt->unprotect_sec_cmd) {
 806                 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0300 |
 807                     fdt->unprotect_sec_cmd);
 808                 ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
 809                     flash_conf_addr(ha, 0x0300 | fdt->protect_sec_cmd):
 810                     flash_conf_addr(ha, 0x0336);
 811         }
 812         goto done;
 813 no_flash_data:
 814         loc = locations[0];
 815         qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
 816         mid = man_id;
 817         fid = flash_id;
 818         ha->fdt_wrt_disable = 0x9c;
 819         ha->fdt_erase_cmd = flash_conf_addr(ha, 0x03d8);
 820         switch (man_id) {
 821         case 0xbf: /* STT flash. */
 822                 if (flash_id == 0x8e)
 823                         ha->fdt_block_size = FLASH_BLK_SIZE_64K;
 824                 else
 825                         ha->fdt_block_size = FLASH_BLK_SIZE_32K;
 826
 827                 if (flash_id == 0x80)
 828                         ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0352);
 829                 break;
 830         case 0x13: /* ST M25P80. */
 831                 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
 832                 break;
 833         case 0x1f: /* Atmel 26DF081A. */
 834                 ha->fdt_block_size = FLASH_BLK_SIZE_4K;
 835                 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0320);
 836                 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0339);
 837                 ha->fdt_protect_sec_cmd = flash_conf_addr(ha, 0x0336);
 838                 break;
 839         default:
 840                 /* Default to 64 kb sector size. */
 841                 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
 842                 break;
 843         }
 844 done:
 845         DEBUG2(qla_printk(KERN_DEBUG, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x "
 846             "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid,
 847             ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd,
 848             ha->fdt_unprotect_sec_cmd, ha->fdt_wrt_disable,
 849             ha->fdt_block_size));
 850 }
 851
 852 int
 853 qla2xxx_get_flash_info(scsi_qla_host_t *vha)
 854 {
 855         int ret;
 856         uint32_t flt_addr;
 857         struct qla_hw_data *ha = vha->hw;
 858
 859         if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && !IS_QLA81XX(ha))
 860                 return QLA_SUCCESS;
 861
 862         ret = qla2xxx_find_flt_start(vha, &flt_addr);
 863         if (ret != QLA_SUCCESS)
 864                 return ret;
 865
 866         qla2xxx_get_flt_info(vha, flt_addr);
 867         qla2xxx_get_fdt_info(vha);
 868
 869         return QLA_SUCCESS;
 870 }
 871
 872 void
 873 qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha)
 874 {
 875 #define NPIV_CONFIG_SIZE        (16*1024)
 876         void *data;
 877         uint16_t *wptr;
 878         uint16_t cnt, chksum;
 879         int i;
 880         struct qla_npiv_header hdr;
 881         struct qla_npiv_entry *entry;
 882         struct qla_hw_data *ha = vha->hw;
 883
 884         if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && !IS_QLA81XX(ha))
 885                 return;
 886
 887         ha->isp_ops->read_optrom(vha, (uint8_t *)&hdr,
 888             ha->flt_region_npiv_conf << 2, sizeof(struct qla_npiv_header));
 889         if (hdr.version == __constant_cpu_to_le16(0xffff))
 890                 return;
 891         if (hdr.version != __constant_cpu_to_le16(1)) {
 892                 DEBUG2(qla_printk(KERN_INFO, ha, "Unsupported NPIV-Config "
 893                     "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
 894                     le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
 895                     le16_to_cpu(hdr.checksum)));
 896                 return;
 897         }
 898
 899         data = kmalloc(NPIV_CONFIG_SIZE, GFP_KERNEL);
 900         if (!data) {
 901                 DEBUG2(qla_printk(KERN_INFO, ha, "NPIV-Config: Unable to "
 902                     "allocate memory.\n"));
 903                 return;
 904         }
 905
 906         ha->isp_ops->read_optrom(vha, (uint8_t *)data,
 907             ha->flt_region_npiv_conf << 2, NPIV_CONFIG_SIZE);
 908
 909         cnt = (sizeof(struct qla_npiv_header) + le16_to_cpu(hdr.entries) *
 910             sizeof(struct qla_npiv_entry)) >> 1;
 911         for (wptr = data, chksum = 0; cnt; cnt--)
 912                 chksum += le16_to_cpu(*wptr++);
 913         if (chksum) {
 914                 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent NPIV-Config "
 915                     "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
 916                     le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
 917                     chksum));
 918                 goto done;
 919         }
 920
 921         entry = data + sizeof(struct qla_npiv_header);
 922         cnt = le16_to_cpu(hdr.entries);
 923         for (i = 0; cnt; cnt--, entry++, i++) {
 924                 uint16_t flags;
 925                 struct fc_vport_identifiers vid;
 926                 struct fc_vport *vport;
 927
 928                 flags = le16_to_cpu(entry->flags);
 929                 if (flags == 0xffff)
 930                         continue;
 931                 if ((flags & BIT_0) == 0)
 932                         continue;
 933
 934                 memset(&vid, 0, sizeof(vid));
 935                 vid.roles = FC_PORT_ROLE_FCP_INITIATOR;
 936                 vid.vport_type = FC_PORTTYPE_NPIV;
 937                 vid.disable = false;
 938                 vid.port_name = wwn_to_u64(entry->port_name);
 939                 vid.node_name = wwn_to_u64(entry->node_name);
 940
 941                 memcpy(&ha->npiv_info[i], entry, sizeof(struct qla_npiv_entry));
 942
 943                 DEBUG2(qla_printk(KERN_DEBUG, ha, "NPIV[%02x]: wwpn=%llx "
 944                         "wwnn=%llx vf_id=0x%x Q_qos=0x%x F_qos=0x%x.\n", cnt,
 945                         vid.port_name, vid.node_name, le16_to_cpu(entry->vf_id),
 946                         entry->q_qos, entry->f_qos));
 947
 948                 if (i < QLA_PRECONFIG_VPORTS) {
 949                         vport = fc_vport_create(vha->host, 0, &vid);
 950                         if (!vport)
 951                                 qla_printk(KERN_INFO, ha,
 952                                 "NPIV-Config: Failed to create vport [%02x]: "
 953                                 "wwpn=%llx wwnn=%llx.\n", cnt,
 954                                 vid.port_name, vid.node_name);
 955                 }
 956         }
 957 done:
 958         kfree(data);
 959         ha->npiv_info = NULL;
 960 }
 961
 962 static int
 963 qla24xx_unprotect_flash(scsi_qla_host_t *vha)
 964 {
 965         struct qla_hw_data *ha = vha->hw;
 966         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 967
 968         if (ha->flags.fac_supported)
 969                 return qla81xx_fac_do_write_enable(vha, 1);
 970
 971         /* Enable flash write. */
 972         WRT_REG_DWORD(&reg->ctrl_status,
 973             RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
 974         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
 975
 976         if (!ha->fdt_wrt_disable)
 977                 goto done;
 978
 979         /* Disable flash write-protection, first clear SR protection bit */
 980         qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
 981         /* Then write zero again to clear remaining SR bits.*/
 982         qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
 983 done:
 984         return QLA_SUCCESS;
 985 }
 986
 987 static int
 988 qla24xx_protect_flash(scsi_qla_host_t *vha)
 989 {
 990         uint32_t cnt;
 991         struct qla_hw_data *ha = vha->hw;
 992         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 993
 994         if (ha->flags.fac_supported)
 995                 return qla81xx_fac_do_write_enable(vha, 0);
 996
 997         if (!ha->fdt_wrt_disable)
 998                 goto skip_wrt_protect;
 999
1000         /* Enable flash write-protection and wait for completion. */
1001         qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101),
1002             ha->fdt_wrt_disable);
1003         for (cnt = 300; cnt &&
1004             qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x005)) & BIT_0;
1005             cnt--) {
1006                 udelay(10);
1007         }
1008
1009 skip_wrt_protect:
1010         /* Disable flash write. */
1011         WRT_REG_DWORD(&reg->ctrl_status,
1012             RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
1013         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
1014
1015         return QLA_SUCCESS;
1016 }
1017
1018 static int
1019 qla24xx_erase_sector(scsi_qla_host_t *vha, uint32_t fdata)
1020 {
1021         struct qla_hw_data *ha = vha->hw;
1022         uint32_t start, finish;
1023
1024         if (ha->flags.fac_supported) {
1025                 start = fdata >> 2;
1026                 finish = start + (ha->fdt_block_size >> 2) - 1;
1027                 return qla81xx_fac_erase_sector(vha, flash_data_addr(ha,
1028                     start), flash_data_addr(ha, finish));
1029         }
1030
1031         return qla24xx_write_flash_dword(ha, ha->fdt_erase_cmd,
1032             (fdata & 0xff00) | ((fdata << 16) & 0xff0000) |
1033             ((fdata >> 16) & 0xff));
1034 }
1035
1036 static int
1037 qla24xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
1038     uint32_t dwords)
1039 {
1040         int ret;
1041         uint32_t liter;
1042         uint32_t sec_mask, rest_addr;
1043         uint32_t fdata;
1044         dma_addr_t optrom_dma;
1045         void *optrom = NULL;
1046         struct qla_hw_data *ha = vha->hw;
1047
1048         /* Prepare burst-capable write on supported ISPs. */
1049         if ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && !(faddr & 0xfff) &&
1050             dwords > OPTROM_BURST_DWORDS) {
1051                 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
1052                     &optrom_dma, GFP_KERNEL);
1053                 if (!optrom) {
1054                         qla_printk(KERN_DEBUG, ha,
1055                             "Unable to allocate memory for optrom burst write "
1056                             "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
1057                 }
1058         }
1059
1060         rest_addr = (ha->fdt_block_size >> 2) - 1;
1061         sec_mask = ~rest_addr;
1062
1063         ret = qla24xx_unprotect_flash(vha);
1064         if (ret != QLA_SUCCESS) {
1065                 qla_printk(KERN_WARNING, ha,
1066                     "Unable to unprotect flash for update.\n");
1067                 goto done;
1068         }
1069
1070         for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
1071                 fdata = (faddr & sec_mask) << 2;
1072
1073                 /* Are we at the beginning of a sector? */
1074                 if ((faddr & rest_addr) == 0) {
1075                         /* Do sector unprotect. */
1076                         if (ha->fdt_unprotect_sec_cmd)
1077                                 qla24xx_write_flash_dword(ha,
1078                                     ha->fdt_unprotect_sec_cmd,
1079                                     (fdata & 0xff00) | ((fdata << 16) &
1080                                     0xff0000) | ((fdata >> 16) & 0xff));
1081                         ret = qla24xx_erase_sector(vha, fdata);
1082                         if (ret != QLA_SUCCESS) {
1083                                 DEBUG9(qla_printk(KERN_WARNING, ha,
1084                                     "Unable to erase sector: address=%x.\n",
1085                                     faddr));
1086                                 break;
1087                         }
1088                 }
1089
1090                 /* Go with burst-write. */
1091                 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
1092                         /* Copy data to DMA'ble buffer. */
1093                         memcpy(optrom, dwptr, OPTROM_BURST_SIZE);
1094
1095                         ret = qla2x00_load_ram(vha, optrom_dma,
1096                             flash_data_addr(ha, faddr),
1097                             OPTROM_BURST_DWORDS);
1098                         if (ret != QLA_SUCCESS) {
1099                                 qla_printk(KERN_WARNING, ha,
1100                                     "Unable to burst-write optrom segment "
1101                                     "(%x/%x/%llx).\n", ret,
1102                                     flash_data_addr(ha, faddr),
1103                                     (unsigned long long)optrom_dma);
1104                                 qla_printk(KERN_WARNING, ha,
1105                                     "Reverting to slow-write.\n");
1106
1107                                 dma_free_coherent(&ha->pdev->dev,
1108                                     OPTROM_BURST_SIZE, optrom, optrom_dma);
1109                                 optrom = NULL;
1110                         } else {
1111                                 liter += OPTROM_BURST_DWORDS - 1;
1112                                 faddr += OPTROM_BURST_DWORDS - 1;
1113                                 dwptr += OPTROM_BURST_DWORDS - 1;
1114                                 continue;
1115                         }
1116                 }
1117
1118                 ret = qla24xx_write_flash_dword(ha,
1119                     flash_data_addr(ha, faddr), cpu_to_le32(*dwptr));
1120                 if (ret != QLA_SUCCESS) {
1121                         DEBUG9(printk("%s(%ld) Unable to program flash "
1122                             "address=%x data=%x.\n", __func__,
1123                             vha->host_no, faddr, *dwptr));
1124                         break;
1125                 }
1126
1127                 /* Do sector protect. */
1128                 if (ha->fdt_unprotect_sec_cmd &&
1129                     ((faddr & rest_addr) == rest_addr))
1130                         qla24xx_write_flash_dword(ha,
1131                             ha->fdt_protect_sec_cmd,
1132                             (fdata & 0xff00) | ((fdata << 16) &
1133                             0xff0000) | ((fdata >> 16) & 0xff));
1134         }
1135
1136         ret = qla24xx_protect_flash(vha);
1137         if (ret != QLA_SUCCESS)
1138                 qla_printk(KERN_WARNING, ha,
1139                     "Unable to protect flash after update.\n");
1140 done:
1141         if (optrom)
1142                 dma_free_coherent(&ha->pdev->dev,
1143                     OPTROM_BURST_SIZE, optrom, optrom_dma);
1144
1145         return ret;
1146 }
1147
1148 uint8_t *
1149 qla2x00_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1150     uint32_t bytes)
1151 {
1152         uint32_t i;
1153         uint16_t *wptr;
1154         struct qla_hw_data *ha = vha->hw;
1155
1156         /* Word reads to NVRAM via registers. */
1157         wptr = (uint16_t *)buf;
1158         qla2x00_lock_nvram_access(ha);
1159         for (i = 0; i < bytes >> 1; i++, naddr++)
1160                 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
1161                     naddr));
1162         qla2x00_unlock_nvram_access(ha);
1163
1164         return buf;
1165 }
1166
1167 uint8_t *
1168 qla24xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1169     uint32_t bytes)
1170 {
1171         uint32_t i;
1172         uint32_t *dwptr;
1173         struct qla_hw_data *ha = vha->hw;
1174
1175         /* Dword reads to flash. */
1176         dwptr = (uint32_t *)buf;
1177         for (i = 0; i < bytes >> 2; i++, naddr++)
1178                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1179                     nvram_data_addr(ha, naddr)));
1180
1181         return buf;
1182 }
1183
1184 int
1185 qla2x00_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1186     uint32_t bytes)
1187 {
1188         int ret, stat;
1189         uint32_t i;
1190         uint16_t *wptr;
1191         unsigned long flags;
1192         struct qla_hw_data *ha = vha->hw;
1193
1194         ret = QLA_SUCCESS;
1195
1196         spin_lock_irqsave(&ha->hardware_lock, flags);
1197         qla2x00_lock_nvram_access(ha);
1198
1199         /* Disable NVRAM write-protection. */
1200         stat = qla2x00_clear_nvram_protection(ha);
1201
1202         wptr = (uint16_t *)buf;
1203         for (i = 0; i < bytes >> 1; i++, naddr++) {
1204                 qla2x00_write_nvram_word(ha, naddr,
1205                     cpu_to_le16(*wptr));
1206                 wptr++;
1207         }
1208
1209         /* Enable NVRAM write-protection. */
1210         qla2x00_set_nvram_protection(ha, stat);
1211
1212         qla2x00_unlock_nvram_access(ha);
1213         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1214
1215         return ret;
1216 }
1217
1218 int
1219 qla24xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1220     uint32_t bytes)
1221 {
1222         int ret;
1223         uint32_t i;
1224         uint32_t *dwptr;
1225         struct qla_hw_data *ha = vha->hw;
1226         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1227
1228         ret = QLA_SUCCESS;
1229
1230         /* Enable flash write. */
1231         WRT_REG_DWORD(&reg->ctrl_status,
1232             RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
1233         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
1234
1235         /* Disable NVRAM write-protection. */
1236         qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1237         qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1238
1239         /* Dword writes to flash. */
1240         dwptr = (uint32_t *)buf;
1241         for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
1242                 ret = qla24xx_write_flash_dword(ha,
1243                     nvram_data_addr(ha, naddr), cpu_to_le32(*dwptr));
1244                 if (ret != QLA_SUCCESS) {
1245                         DEBUG9(qla_printk(KERN_WARNING, ha,
1246                             "Unable to program nvram address=%x data=%x.\n",
1247                             naddr, *dwptr));
1248                         break;
1249                 }
1250         }
1251
1252         /* Enable NVRAM write-protection. */
1253         qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0x8c);
1254
1255         /* Disable flash write. */
1256         WRT_REG_DWORD(&reg->ctrl_status,
1257             RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
1258         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
1259
1260         return ret;
1261 }
1262
1263 uint8_t *
1264 qla25xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1265     uint32_t bytes)
1266 {
1267         uint32_t i;
1268         uint32_t *dwptr;
1269         struct qla_hw_data *ha = vha->hw;
1270
1271         /* Dword reads to flash. */
1272         dwptr = (uint32_t *)buf;
1273         for (i = 0; i < bytes >> 2; i++, naddr++)
1274                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1275                     flash_data_addr(ha, ha->flt_region_vpd_nvram | naddr)));
1276
1277         return buf;
1278 }
1279
1280 int
1281 qla25xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1282     uint32_t bytes)
1283 {
1284         struct qla_hw_data *ha = vha->hw;
1285 #define RMW_BUFFER_SIZE (64 * 1024)
1286         uint8_t *dbuf;
1287
1288         dbuf = vmalloc(RMW_BUFFER_SIZE);
1289         if (!dbuf)
1290                 return QLA_MEMORY_ALLOC_FAILED;
1291         ha->isp_ops->read_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
1292             RMW_BUFFER_SIZE);
1293         memcpy(dbuf + (naddr << 2), buf, bytes);
1294         ha->isp_ops->write_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
1295             RMW_BUFFER_SIZE);
1296         vfree(dbuf);
1297
1298         return QLA_SUCCESS;
1299 }
1300
1301 static inline void
1302 qla2x00_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
1303 {
1304         if (IS_QLA2322(ha)) {
1305                 /* Flip all colors. */
1306                 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1307                         /* Turn off. */
1308                         ha->beacon_color_state = 0;
1309                         *pflags = GPIO_LED_ALL_OFF;
1310                 } else {
1311                         /* Turn on. */
1312                         ha->beacon_color_state = QLA_LED_ALL_ON;
1313                         *pflags = GPIO_LED_RGA_ON;
1314                 }
1315         } else {
1316                 /* Flip green led only. */
1317                 if (ha->beacon_color_state == QLA_LED_GRN_ON) {
1318                         /* Turn off. */
1319                         ha->beacon_color_state = 0;
1320                         *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF;
1321                 } else {
1322                         /* Turn on. */
1323                         ha->beacon_color_state = QLA_LED_GRN_ON;
1324                         *pflags = GPIO_LED_GREEN_ON_AMBER_OFF;
1325                 }
1326         }
1327 }
1328
1329 #define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r))
1330
1331 void
1332 qla2x00_beacon_blink(struct scsi_qla_host *vha)
1333 {
1334         uint16_t gpio_enable;
1335         uint16_t gpio_data;
1336         uint16_t led_color = 0;
1337         unsigned long flags;
1338         struct qla_hw_data *ha = vha->hw;
1339         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1340
1341         spin_lock_irqsave(&ha->hardware_lock, flags);
1342
1343         /* Save the Original GPIOE. */
1344         if (ha->pio_address) {
1345                 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1346                 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1347         } else {
1348                 gpio_enable = RD_REG_WORD(&reg->gpioe);
1349                 gpio_data = RD_REG_WORD(&reg->gpiod);
1350         }
1351
1352         /* Set the modified gpio_enable values */
1353         gpio_enable |= GPIO_LED_MASK;
1354
1355         if (ha->pio_address) {
1356                 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1357         } else {
1358                 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1359                 RD_REG_WORD(&reg->gpioe);
1360         }
1361
1362         qla2x00_flip_colors(ha, &led_color);
1363
1364         /* Clear out any previously set LED color. */
1365         gpio_data &= ~GPIO_LED_MASK;
1366
1367         /* Set the new input LED color to GPIOD. */
1368         gpio_data |= led_color;
1369
1370         /* Set the modified gpio_data values */
1371         if (ha->pio_address) {
1372                 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1373         } else {
1374                 WRT_REG_WORD(&reg->gpiod, gpio_data);
1375                 RD_REG_WORD(&reg->gpiod);
1376         }
1377
1378         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1379 }
1380
1381 int
1382 qla2x00_beacon_on(struct scsi_qla_host *vha)
1383 {
1384         uint16_t gpio_enable;
1385         uint16_t gpio_data;
1386         unsigned long flags;
1387         struct qla_hw_data *ha = vha->hw;
1388         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1389
1390         ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1391         ha->fw_options[1] |= FO1_DISABLE_GPIO6_7;
1392
1393         if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1394                 qla_printk(KERN_WARNING, ha,
1395                     "Unable to update fw options (beacon on).\n");
1396                 return QLA_FUNCTION_FAILED;
1397         }
1398
1399         /* Turn off LEDs. */
1400         spin_lock_irqsave(&ha->hardware_lock, flags);
1401         if (ha->pio_address) {
1402                 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1403                 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1404         } else {
1405                 gpio_enable = RD_REG_WORD(&reg->gpioe);
1406                 gpio_data = RD_REG_WORD(&reg->gpiod);
1407         }
1408         gpio_enable |= GPIO_LED_MASK;
1409
1410         /* Set the modified gpio_enable values. */
1411         if (ha->pio_address) {
1412                 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1413         } else {
1414                 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1415                 RD_REG_WORD(&reg->gpioe);
1416         }
1417
1418         /* Clear out previously set LED colour. */
1419         gpio_data &= ~GPIO_LED_MASK;
1420         if (ha->pio_address) {
1421                 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1422         } else {
1423                 WRT_REG_WORD(&reg->gpiod, gpio_data);
1424                 RD_REG_WORD(&reg->gpiod);
1425         }
1426         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1427
1428         /*
1429          * Let the per HBA timer kick off the blinking process based on
1430          * the following flags. No need to do anything else now.
1431          */
1432         ha->beacon_blink_led = 1;
1433         ha->beacon_color_state = 0;
1434
1435         return QLA_SUCCESS;
1436 }
1437
1438 int
1439 qla2x00_beacon_off(struct scsi_qla_host *vha)
1440 {
1441         int rval = QLA_SUCCESS;
1442         struct qla_hw_data *ha = vha->hw;
1443
1444         ha->beacon_blink_led = 0;
1445
1446         /* Set the on flag so when it gets flipped it will be off. */
1447         if (IS_QLA2322(ha))
1448                 ha->beacon_color_state = QLA_LED_ALL_ON;
1449         else
1450                 ha->beacon_color_state = QLA_LED_GRN_ON;
1451
1452         ha->isp_ops->beacon_blink(vha); /* This turns green LED off */
1453
1454         ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1455         ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7;
1456
1457         rval = qla2x00_set_fw_options(vha, ha->fw_options);
1458         if (rval != QLA_SUCCESS)
1459                 qla_printk(KERN_WARNING, ha,
1460                     "Unable to update fw options (beacon off).\n");
1461         return rval;
1462 }
1463
1464
1465 static inline void
1466 qla24xx_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
1467 {
1468         /* Flip all colors. */
1469         if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1470                 /* Turn off. */
1471                 ha->beacon_color_state = 0;
1472                 *pflags = 0;
1473         } else {
1474                 /* Turn on. */
1475                 ha->beacon_color_state = QLA_LED_ALL_ON;
1476                 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON;
1477         }
1478 }
1479
1480 void
1481 qla24xx_beacon_blink(struct scsi_qla_host *vha)
1482 {
1483         uint16_t led_color = 0;
1484         uint32_t gpio_data;
1485         unsigned long flags;
1486         struct qla_hw_data *ha = vha->hw;
1487         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1488
1489         /* Save the Original GPIOD. */
1490         spin_lock_irqsave(&ha->hardware_lock, flags);
1491         gpio_data = RD_REG_DWORD(&reg->gpiod);
1492
1493         /* Enable the gpio_data reg for update. */
1494         gpio_data |= GPDX_LED_UPDATE_MASK;
1495
1496         WRT_REG_DWORD(&reg->gpiod, gpio_data);
1497         gpio_data = RD_REG_DWORD(&reg->gpiod);
1498
1499         /* Set the color bits. */
1500         qla24xx_flip_colors(ha, &led_color);
1501
1502         /* Clear out any previously set LED color. */
1503         gpio_data &= ~GPDX_LED_COLOR_MASK;
1504
1505         /* Set the new input LED color to GPIOD. */
1506         gpio_data |= led_color;
1507
1508         /* Set the modified gpio_data values. */
1509         WRT_REG_DWORD(&reg->gpiod, gpio_data);
1510         gpio_data = RD_REG_DWORD(&reg->gpiod);
1511         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1512 }
1513
1514 int
1515 qla24xx_beacon_on(struct scsi_qla_host *vha)
1516 {
1517         uint32_t gpio_data;
1518         unsigned long flags;
1519         struct qla_hw_data *ha = vha->hw;
1520         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1521
1522         if (ha->beacon_blink_led == 0) {
1523                 /* Enable firmware for update */
1524                 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL;
1525
1526                 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS)
1527                         return QLA_FUNCTION_FAILED;
1528
1529                 if (qla2x00_get_fw_options(vha, ha->fw_options) !=
1530                     QLA_SUCCESS) {
1531                         qla_printk(KERN_WARNING, ha,
1532                             "Unable to update fw options (beacon on).\n");
1533                         return QLA_FUNCTION_FAILED;
1534                 }
1535
1536                 spin_lock_irqsave(&ha->hardware_lock, flags);
1537                 gpio_data = RD_REG_DWORD(&reg->gpiod);
1538
1539                 /* Enable the gpio_data reg for update. */
1540                 gpio_data |= GPDX_LED_UPDATE_MASK;
1541                 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1542                 RD_REG_DWORD(&reg->gpiod);
1543
1544                 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1545         }
1546
1547         /* So all colors blink together. */
1548         ha->beacon_color_state = 0;
1549
1550         /* Let the per HBA timer kick off the blinking process. */
1551         ha->beacon_blink_led = 1;
1552
1553         return QLA_SUCCESS;
1554 }
1555
1556 int
1557 qla24xx_beacon_off(struct scsi_qla_host *vha)
1558 {
1559         uint32_t gpio_data;
1560         unsigned long flags;
1561         struct qla_hw_data *ha = vha->hw;
1562         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1563
1564         ha->beacon_blink_led = 0;
1565         ha->beacon_color_state = QLA_LED_ALL_ON;
1566
1567         ha->isp_ops->beacon_blink(vha); /* Will flip to all off. */
1568
1569         /* Give control back to firmware. */
1570         spin_lock_irqsave(&ha->hardware_lock, flags);
1571         gpio_data = RD_REG_DWORD(&reg->gpiod);
1572
1573         /* Disable the gpio_data reg for update. */
1574         gpio_data &= ~GPDX_LED_UPDATE_MASK;
1575         WRT_REG_DWORD(&reg->gpiod, gpio_data);
1576         RD_REG_DWORD(&reg->gpiod);
1577         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1578
1579         ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL;
1580
1581         if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1582                 qla_printk(KERN_WARNING, ha,
1583                     "Unable to update fw options (beacon off).\n");
1584                 return QLA_FUNCTION_FAILED;
1585         }
1586
1587         if (qla2x00_get_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1588                 qla_printk(KERN_WARNING, ha,
1589                     "Unable to get fw options (beacon off).\n");
1590                 return QLA_FUNCTION_FAILED;
1591         }
1592
1593         return QLA_SUCCESS;
1594 }
1595
1596
1597 /*
1598  * Flash support routines
1599  */
1600
1601 /**
1602  * qla2x00_flash_enable() - Setup flash for reading and writing.
1603  * @ha: HA context
1604  */
1605 static void
1606 qla2x00_flash_enable(struct qla_hw_data *ha)
1607 {
1608         uint16_t data;
1609         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1610
1611         data = RD_REG_WORD(&reg->ctrl_status);
1612         data |= CSR_FLASH_ENABLE;
1613         WRT_REG_WORD(&reg->ctrl_status, data);
1614         RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1615 }
1616
1617 /**
1618  * qla2x00_flash_disable() - Disable flash and allow RISC to run.
1619  * @ha: HA context
1620  */
1621 static void
1622 qla2x00_flash_disable(struct qla_hw_data *ha)
1623 {
1624         uint16_t data;
1625         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1626
1627         data = RD_REG_WORD(&reg->ctrl_status);
1628         data &= ~(CSR_FLASH_ENABLE);
1629         WRT_REG_WORD(&reg->ctrl_status, data);
1630         RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1631 }
1632
1633 /**
1634  * qla2x00_read_flash_byte() - Reads a byte from flash
1635  * @ha: HA context
1636  * @addr: Address in flash to read
1637  *
1638  * A word is read from the chip, but, only the lower byte is valid.
1639  *
1640  * Returns the byte read from flash @addr.
1641  */
1642 static uint8_t
1643 qla2x00_read_flash_byte(struct qla_hw_data *ha, uint32_t addr)
1644 {
1645         uint16_t data;
1646         uint16_t bank_select;
1647         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1648
1649         bank_select = RD_REG_WORD(&reg->ctrl_status);
1650
1651         if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1652                 /* Specify 64K address range: */
1653                 /*  clear out Module Select and Flash Address bits [19:16]. */
1654                 bank_select &= ~0xf8;
1655                 bank_select |= addr >> 12 & 0xf0;
1656                 bank_select |= CSR_FLASH_64K_BANK;
1657                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1658                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1659
1660                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1661                 data = RD_REG_WORD(&reg->flash_data);
1662
1663                 return (uint8_t)data;
1664         }
1665
1666         /* Setup bit 16 of flash address. */
1667         if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1668                 bank_select |= CSR_FLASH_64K_BANK;
1669                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1670                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1671         } else if (((addr & BIT_16) == 0) &&
1672             (bank_select & CSR_FLASH_64K_BANK)) {
1673                 bank_select &= ~(CSR_FLASH_64K_BANK);
1674                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1675                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1676         }
1677
1678         /* Always perform IO mapped accesses to the FLASH registers. */
1679         if (ha->pio_address) {
1680                 uint16_t data2;
1681
1682                 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1683                 do {
1684                         data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1685                         barrier();
1686                         cpu_relax();
1687                         data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1688                 } while (data != data2);
1689         } else {
1690                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1691                 data = qla2x00_debounce_register(&reg->flash_data);
1692         }
1693
1694         return (uint8_t)data;
1695 }
1696
1697 /**
1698  * qla2x00_write_flash_byte() - Write a byte to flash
1699  * @ha: HA context
1700  * @addr: Address in flash to write
1701  * @data: Data to write
1702  */
1703 static void
1704 qla2x00_write_flash_byte(struct qla_hw_data *ha, uint32_t addr, uint8_t data)
1705 {
1706         uint16_t bank_select;
1707         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1708
1709         bank_select = RD_REG_WORD(&reg->ctrl_status);
1710         if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1711                 /* Specify 64K address range: */
1712                 /*  clear out Module Select and Flash Address bits [19:16]. */
1713                 bank_select &= ~0xf8;
1714                 bank_select |= addr >> 12 & 0xf0;
1715                 bank_select |= CSR_FLASH_64K_BANK;
1716                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1717                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1718
1719                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1720                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1721                 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1722                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1723
1724                 return;
1725         }
1726
1727         /* Setup bit 16 of flash address. */
1728         if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1729                 bank_select |= CSR_FLASH_64K_BANK;
1730                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1731                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1732         } else if (((addr & BIT_16) == 0) &&
1733             (bank_select & CSR_FLASH_64K_BANK)) {
1734                 bank_select &= ~(CSR_FLASH_64K_BANK);
1735                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1736                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1737         }
1738
1739         /* Always perform IO mapped accesses to the FLASH registers. */
1740         if (ha->pio_address) {
1741                 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1742                 WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data);
1743         } else {
1744                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1745                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1746                 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1747                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1748         }
1749 }
1750
1751 /**
1752  * qla2x00_poll_flash() - Polls flash for completion.
1753  * @ha: HA context
1754  * @addr: Address in flash to poll
1755  * @poll_data: Data to be polled
1756  * @man_id: Flash manufacturer ID
1757  * @flash_id: Flash ID
1758  *
1759  * This function polls the device until bit 7 of what is read matches data
1760  * bit 7 or until data bit 5 becomes a 1.  If that hapens, the flash ROM timed
1761  * out (a fatal error).  The flash book recommeds reading bit 7 again after
1762  * reading bit 5 as a 1.
1763  *
1764  * Returns 0 on success, else non-zero.
1765  */
1766 static int
1767 qla2x00_poll_flash(struct qla_hw_data *ha, uint32_t addr, uint8_t poll_data,
1768     uint8_t man_id, uint8_t flash_id)
1769 {
1770         int status;
1771         uint8_t flash_data;
1772         uint32_t cnt;
1773
1774         status = 1;
1775
1776         /* Wait for 30 seconds for command to finish. */
1777         poll_data &= BIT_7;
1778         for (cnt = 3000000; cnt; cnt--) {
1779                 flash_data = qla2x00_read_flash_byte(ha, addr);
1780                 if ((flash_data & BIT_7) == poll_data) {
1781                         status = 0;
1782                         break;
1783                 }
1784
1785                 if (man_id != 0x40 && man_id != 0xda) {
1786                         if ((flash_data & BIT_5) && cnt > 2)
1787                                 cnt = 2;
1788                 }
1789                 udelay(10);
1790                 barrier();
1791                 cond_resched();
1792         }
1793         return status;
1794 }
1795
1796 /**
1797  * qla2x00_program_flash_address() - Programs a flash address
1798  * @ha: HA context
1799  * @addr: Address in flash to program
1800  * @data: Data to be written in flash
1801  * @man_id: Flash manufacturer ID
1802  * @flash_id: Flash ID
1803  *
1804  * Returns 0 on success, else non-zero.
1805  */
1806 static int
1807 qla2x00_program_flash_address(struct qla_hw_data *ha, uint32_t addr,
1808     uint8_t data, uint8_t man_id, uint8_t flash_id)
1809 {
1810         /* Write Program Command Sequence. */
1811         if (IS_OEM_001(ha)) {
1812                 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1813                 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1814                 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0);
1815                 qla2x00_write_flash_byte(ha, addr, data);
1816         } else {
1817                 if (man_id == 0xda && flash_id == 0xc1) {
1818                         qla2x00_write_flash_byte(ha, addr, data);
1819                         if (addr & 0x7e)
1820                                 return 0;
1821                 } else {
1822                         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1823                         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1824                         qla2x00_write_flash_byte(ha, 0x5555, 0xa0);
1825                         qla2x00_write_flash_byte(ha, addr, data);
1826                 }
1827         }
1828
1829         udelay(150);
1830
1831         /* Wait for write to complete. */
1832         return qla2x00_poll_flash(ha, addr, data, man_id, flash_id);
1833 }
1834
1835 /**
1836  * qla2x00_erase_flash() - Erase the flash.
1837  * @ha: HA context
1838  * @man_id: Flash manufacturer ID
1839  * @flash_id: Flash ID
1840  *
1841  * Returns 0 on success, else non-zero.
1842  */
1843 static int
1844 qla2x00_erase_flash(struct qla_hw_data *ha, uint8_t man_id, uint8_t flash_id)
1845 {
1846         /* Individual Sector Erase Command Sequence */
1847         if (IS_OEM_001(ha)) {
1848                 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1849                 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1850                 qla2x00_write_flash_byte(ha, 0xaaa, 0x80);
1851                 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1852                 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1853                 qla2x00_write_flash_byte(ha, 0xaaa, 0x10);
1854         } else {
1855                 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1856                 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1857                 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1858                 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1859                 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1860                 qla2x00_write_flash_byte(ha, 0x5555, 0x10);
1861         }
1862
1863         udelay(150);
1864
1865         /* Wait for erase to complete. */
1866         return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id);
1867 }
1868
1869 /**
1870  * qla2x00_erase_flash_sector() - Erase a flash sector.
1871  * @ha: HA context
1872  * @addr: Flash sector to erase
1873  * @sec_mask: Sector address mask
1874  * @man_id: Flash manufacturer ID
1875  * @flash_id: Flash ID
1876  *
1877  * Returns 0 on success, else non-zero.
1878  */
1879 static int
1880 qla2x00_erase_flash_sector(struct qla_hw_data *ha, uint32_t addr,
1881     uint32_t sec_mask, uint8_t man_id, uint8_t flash_id)
1882 {
1883         /* Individual Sector Erase Command Sequence */
1884         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1885         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1886         qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1887         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1888         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1889         if (man_id == 0x1f && flash_id == 0x13)
1890                 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10);
1891         else
1892                 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30);
1893
1894         udelay(150);
1895
1896         /* Wait for erase to complete. */
1897         return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id);
1898 }
1899
1900 /**
1901  * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
1902  * @man_id: Flash manufacturer ID
1903  * @flash_id: Flash ID
1904  */
1905 static void
1906 qla2x00_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
1907     uint8_t *flash_id)
1908 {
1909         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1910         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1911         qla2x00_write_flash_byte(ha, 0x5555, 0x90);
1912         *man_id = qla2x00_read_flash_byte(ha, 0x0000);
1913         *flash_id = qla2x00_read_flash_byte(ha, 0x0001);
1914         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1915         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1916         qla2x00_write_flash_byte(ha, 0x5555, 0xf0);
1917 }
1918
1919 static void
1920 qla2x00_read_flash_data(struct qla_hw_data *ha, uint8_t *tmp_buf,
1921         uint32_t saddr, uint32_t length)
1922 {
1923         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1924         uint32_t midpoint, ilength;
1925         uint8_t data;
1926
1927         midpoint = length / 2;
1928
1929         WRT_REG_WORD(&reg->nvram, 0);
1930         RD_REG_WORD(&reg->nvram);
1931         for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) {
1932                 if (ilength == midpoint) {
1933                         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1934                         RD_REG_WORD(&reg->nvram);
1935                 }
1936                 data = qla2x00_read_flash_byte(ha, saddr);
1937                 if (saddr % 100)
1938                         udelay(10);
1939                 *tmp_buf = data;
1940                 cond_resched();
1941         }
1942 }
1943
1944 static inline void
1945 qla2x00_suspend_hba(struct scsi_qla_host *vha)
1946 {
1947         int cnt;
1948         unsigned long flags;
1949         struct qla_hw_data *ha = vha->hw;
1950         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1951
1952         /* Suspend HBA. */
1953         scsi_block_requests(vha->host);
1954         ha->isp_ops->disable_intrs(ha);
1955         set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1956
1957         /* Pause RISC. */
1958         spin_lock_irqsave(&ha->hardware_lock, flags);
1959         WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1960         RD_REG_WORD(&reg->hccr);
1961         if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1962                 for (cnt = 0; cnt < 30000; cnt++) {
1963                         if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
1964                                 break;
1965                         udelay(100);
1966                 }
1967         } else {
1968                 udelay(10);
1969         }
1970         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1971 }
1972
1973 static inline void
1974 qla2x00_resume_hba(struct scsi_qla_host *vha)
1975 {
1976         struct qla_hw_data *ha = vha->hw;
1977
1978         /* Resume HBA. */
1979         clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1980         set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1981         qla2xxx_wake_dpc(vha);
1982         qla2x00_wait_for_chip_reset(vha);
1983         scsi_unblock_requests(vha->host);
1984 }
1985
1986 uint8_t *
1987 qla2x00_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
1988     uint32_t offset, uint32_t length)
1989 {
1990         uint32_t addr, midpoint;
1991         uint8_t *data;
1992         struct qla_hw_data *ha = vha->hw;
1993         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1994
1995         /* Suspend HBA. */
1996         qla2x00_suspend_hba(vha);
1997
1998         /* Go with read. */
1999         midpoint = ha->optrom_size / 2;
2000
2001         qla2x00_flash_enable(ha);
2002         WRT_REG_WORD(&reg->nvram, 0);
2003         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
2004         for (addr = offset, data = buf; addr < length; addr++, data++) {
2005                 if (addr == midpoint) {
2006                         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2007                         RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
2008                 }
2009
2010                 *data = qla2x00_read_flash_byte(ha, addr);
2011         }
2012         qla2x00_flash_disable(ha);
2013
2014         /* Resume HBA. */
2015         qla2x00_resume_hba(vha);
2016
2017         return buf;
2018 }
2019
2020 int
2021 qla2x00_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2022     uint32_t offset, uint32_t length)
2023 {
2024
2025         int rval;
2026         uint8_t man_id, flash_id, sec_number, data;
2027         uint16_t wd;
2028         uint32_t addr, liter, sec_mask, rest_addr;
2029         struct qla_hw_data *ha = vha->hw;
2030         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2031
2032         /* Suspend HBA. */
2033         qla2x00_suspend_hba(vha);
2034
2035         rval = QLA_SUCCESS;
2036         sec_number = 0;
2037
2038         /* Reset ISP chip. */
2039         WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
2040         pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
2041
2042         /* Go with write. */
2043         qla2x00_flash_enable(ha);
2044         do {    /* Loop once to provide quick error exit */
2045                 /* Structure of flash memory based on manufacturer */
2046                 if (IS_OEM_001(ha)) {
2047                         /* OEM variant with special flash part. */
2048                         man_id = flash_id = 0;
2049                         rest_addr = 0xffff;
2050                         sec_mask   = 0x10000;
2051                         goto update_flash;
2052                 }
2053                 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id);
2054                 switch (man_id) {
2055                 case 0x20: /* ST flash. */
2056                         if (flash_id == 0xd2 || flash_id == 0xe3) {
2057                                 /*
2058                                  * ST m29w008at part - 64kb sector size with
2059                                  * 32kb,8kb,8kb,16kb sectors at memory address
2060                                  * 0xf0000.
2061                                  */
2062                                 rest_addr = 0xffff;
2063                                 sec_mask = 0x10000;
2064                                 break;
2065                         }
2066                         /*
2067                          * ST m29w010b part - 16kb sector size
2068                          * Default to 16kb sectors
2069                          */
2070                         rest_addr = 0x3fff;
2071                         sec_mask = 0x1c000;
2072                         break;
2073                 case 0x40: /* Mostel flash. */
2074                         /* Mostel v29c51001 part - 512 byte sector size. */
2075                         rest_addr = 0x1ff;
2076                         sec_mask = 0x1fe00;
2077                         break;
2078                 case 0xbf: /* SST flash. */
2079                         /* SST39sf10 part - 4kb sector size. */
2080                         rest_addr = 0xfff;
2081                         sec_mask = 0x1f000;
2082                         break;
2083                 case 0xda: /* Winbond flash. */
2084                         /* Winbond W29EE011 part - 256 byte sector size. */
2085                         rest_addr = 0x7f;
2086                         sec_mask = 0x1ff80;
2087                         break;
2088                 case 0xc2: /* Macronix flash. */
2089                         /* 64k sector size. */
2090                         if (flash_id == 0x38 || flash_id == 0x4f) {
2091                                 rest_addr = 0xffff;
2092                                 sec_mask = 0x10000;
2093                                 break;
2094                         }
2095                         /* Fall through... */
2096
2097                 case 0x1f: /* Atmel flash. */
2098                         /* 512k sector size. */
2099                         if (flash_id == 0x13) {
2100                                 rest_addr = 0x7fffffff;
2101                                 sec_mask =   0x80000000;
2102                                 break;
2103                         }
2104                         /* Fall through... */
2105
2106                 case 0x01: /* AMD flash. */
2107                         if (flash_id == 0x38 || flash_id == 0x40 ||
2108                             flash_id == 0x4f) {
2109                                 /* Am29LV081 part - 64kb sector size. */
2110                                 /* Am29LV002BT part - 64kb sector size. */
2111                                 rest_addr = 0xffff;
2112                                 sec_mask = 0x10000;
2113                                 break;
2114                         } else if (flash_id == 0x3e) {
2115                                 /*
2116                                  * Am29LV008b part - 64kb sector size with
2117                                  * 32kb,8kb,8kb,16kb sector at memory address
2118                                  * h0xf0000.
2119                                  */
2120                                 rest_addr = 0xffff;
2121                                 sec_mask = 0x10000;
2122                                 break;
2123                         } else if (flash_id == 0x20 || flash_id == 0x6e) {
2124                                 /*
2125                                  * Am29LV010 part or AM29f010 - 16kb sector
2126                                  * size.
2127                                  */
2128                                 rest_addr = 0x3fff;
2129                                 sec_mask = 0x1c000;
2130                                 break;
2131                         } else if (flash_id == 0x6d) {
2132                                 /* Am29LV001 part - 8kb sector size. */
2133                                 rest_addr = 0x1fff;
2134                                 sec_mask = 0x1e000;
2135                                 break;
2136                         }
2137                 default:
2138                         /* Default to 16 kb sector size. */
2139                         rest_addr = 0x3fff;
2140                         sec_mask = 0x1c000;
2141                         break;
2142                 }
2143
2144 update_flash:
2145                 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2146                         if (qla2x00_erase_flash(ha, man_id, flash_id)) {
2147                                 rval = QLA_FUNCTION_FAILED;
2148                                 break;
2149                         }
2150                 }
2151
2152                 for (addr = offset, liter = 0; liter < length; liter++,
2153                     addr++) {
2154                         data = buf[liter];
2155                         /* Are we at the beginning of a sector? */
2156                         if ((addr & rest_addr) == 0) {
2157                                 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2158                                         if (addr >= 0x10000UL) {
2159                                                 if (((addr >> 12) & 0xf0) &&
2160                                                     ((man_id == 0x01 &&
2161                                                         flash_id == 0x3e) ||
2162                                                      (man_id == 0x20 &&
2163                                                          flash_id == 0xd2))) {
2164                                                         sec_number++;
2165                                                         if (sec_number == 1) {
2166                                                                 rest_addr =
2167                                                                     0x7fff;
2168                                                                 sec_mask =
2169                                                                     0x18000;
2170                                                         } else if (
2171                                                             sec_number == 2 ||
2172                                                             sec_number == 3) {
2173                                                                 rest_addr =
2174                                                                     0x1fff;
2175                                                                 sec_mask =
2176                                                                     0x1e000;
2177                                                         } else if (
2178                                                             sec_number == 4) {
2179                                                                 rest_addr =
2180                                                                     0x3fff;
2181                                                                 sec_mask =
2182                                                                     0x1c000;
2183                                                         }
2184                                                 }
2185                                         }
2186                                 } else if (addr == ha->optrom_size / 2) {
2187                                         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2188                                         RD_REG_WORD(&reg->nvram);
2189                                 }
2190
2191                                 if (flash_id == 0xda && man_id == 0xc1) {
2192                                         qla2x00_write_flash_byte(ha, 0x5555,
2193                                             0xaa);
2194                                         qla2x00_write_flash_byte(ha, 0x2aaa,
2195                                             0x55);
2196                                         qla2x00_write_flash_byte(ha, 0x5555,
2197                                             0xa0);
2198                                 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) {
2199                                         /* Then erase it */
2200                                         if (qla2x00_erase_flash_sector(ha,
2201                                             addr, sec_mask, man_id,
2202                                             flash_id)) {
2203                                                 rval = QLA_FUNCTION_FAILED;
2204                                                 break;
2205                                         }
2206                                         if (man_id == 0x01 && flash_id == 0x6d)
2207                                                 sec_number++;
2208                                 }
2209                         }
2210
2211                         if (man_id == 0x01 && flash_id == 0x6d) {
2212                                 if (sec_number == 1 &&
2213                                     addr == (rest_addr - 1)) {
2214                                         rest_addr = 0x0fff;
2215                                         sec_mask   = 0x1f000;
2216                                 } else if (sec_number == 3 && (addr & 0x7ffe)) {
2217                                         rest_addr = 0x3fff;
2218                                         sec_mask   = 0x1c000;
2219                                 }
2220                         }
2221
2222                         if (qla2x00_program_flash_address(ha, addr, data,
2223                             man_id, flash_id)) {
2224                                 rval = QLA_FUNCTION_FAILED;
2225                                 break;
2226                         }
2227                         cond_resched();
2228                 }
2229         } while (0);
2230         qla2x00_flash_disable(ha);
2231
2232         /* Resume HBA. */
2233         qla2x00_resume_hba(vha);
2234
2235         return rval;
2236 }
2237
2238 uint8_t *
2239 qla24xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2240     uint32_t offset, uint32_t length)
2241 {
2242         struct qla_hw_data *ha = vha->hw;
2243
2244         /* Suspend HBA. */
2245         scsi_block_requests(vha->host);
2246         set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2247
2248         /* Go with read. */
2249         qla24xx_read_flash_data(vha, (uint32_t *)buf, offset >> 2, length >> 2);
2250
2251         /* Resume HBA. */
2252         clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2253         scsi_unblock_requests(vha->host);
2254
2255         return buf;
2256 }
2257
2258 int
2259 qla24xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2260     uint32_t offset, uint32_t length)
2261 {
2262         int rval;
2263         struct qla_hw_data *ha = vha->hw;
2264
2265         /* Suspend HBA. */
2266         scsi_block_requests(vha->host);
2267         set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2268
2269         /* Go with write. */
2270         rval = qla24xx_write_flash_data(vha, (uint32_t *)buf, offset >> 2,
2271             length >> 2);
2272
2273         clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2274         scsi_unblock_requests(vha->host);
2275
2276         return rval;
2277 }
2278
2279 uint8_t *
2280 qla25xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2281     uint32_t offset, uint32_t length)
2282 {
2283         int rval;
2284         dma_addr_t optrom_dma;
2285         void *optrom;
2286         uint8_t *pbuf;
2287         uint32_t faddr, left, burst;
2288         struct qla_hw_data *ha = vha->hw;
2289
2290         if (offset & 0xfff)
2291                 goto slow_read;
2292         if (length < OPTROM_BURST_SIZE)
2293                 goto slow_read;
2294
2295         optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2296             &optrom_dma, GFP_KERNEL);
2297         if (!optrom) {
2298                 qla_printk(KERN_DEBUG, ha,
2299                     "Unable to allocate memory for optrom burst read "
2300                     "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
2301
2302                 goto slow_read;
2303         }
2304
2305         pbuf = buf;
2306         faddr = offset >> 2;
2307         left = length >> 2;
2308         burst = OPTROM_BURST_DWORDS;
2309         while (left != 0) {
2310                 if (burst > left)
2311                         burst = left;
2312
2313                 rval = qla2x00_dump_ram(vha, optrom_dma,
2314                     flash_data_addr(ha, faddr), burst);
2315                 if (rval) {
2316                         qla_printk(KERN_WARNING, ha,
2317                             "Unable to burst-read optrom segment "
2318                             "(%x/%x/%llx).\n", rval,
2319                             flash_data_addr(ha, faddr),
2320                             (unsigned long long)optrom_dma);
2321                         qla_printk(KERN_WARNING, ha,
2322                             "Reverting to slow-read.\n");
2323
2324                         dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2325                             optrom, optrom_dma);
2326                         goto slow_read;
2327                 }
2328
2329                 memcpy(pbuf, optrom, burst * 4);
2330
2331                 left -= burst;
2332                 faddr += burst;
2333                 pbuf += burst * 4;
2334         }
2335
2336         dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom,
2337             optrom_dma);
2338
2339         return buf;
2340
2341 slow_read:
2342     return qla24xx_read_optrom_data(vha, buf, offset, length);
2343 }
2344
2345 /**
2346  * qla2x00_get_fcode_version() - Determine an FCODE image's version.
2347  * @ha: HA context
2348  * @pcids: Pointer to the FCODE PCI data structure
2349  *
2350  * The process of retrieving the FCODE version information is at best
2351  * described as interesting.
2352  *
2353  * Within the first 100h bytes of the image an ASCII string is present
2354  * which contains several pieces of information including the FCODE
2355  * version.  Unfortunately it seems the only reliable way to retrieve
2356  * the version is by scanning for another sentinel within the string,
2357  * the FCODE build date:
2358  *
2359  *      ... 2.00.02 10/17/02 ...
2360  *
2361  * Returns QLA_SUCCESS on successful retrieval of version.
2362  */
2363 static void
2364 qla2x00_get_fcode_version(struct qla_hw_data *ha, uint32_t pcids)
2365 {
2366         int ret = QLA_FUNCTION_FAILED;
2367         uint32_t istart, iend, iter, vend;
2368         uint8_t do_next, rbyte, *vbyte;
2369
2370         memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2371
2372         /* Skip the PCI data structure. */
2373         istart = pcids +
2374             ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) |
2375                 qla2x00_read_flash_byte(ha, pcids + 0x0A));
2376         iend = istart + 0x100;
2377         do {
2378                 /* Scan for the sentinel date string...eeewww. */
2379                 do_next = 0;
2380                 iter = istart;
2381                 while ((iter < iend) && !do_next) {
2382                         iter++;
2383                         if (qla2x00_read_flash_byte(ha, iter) == '/') {
2384                                 if (qla2x00_read_flash_byte(ha, iter + 2) ==
2385                                     '/')
2386                                         do_next++;
2387                                 else if (qla2x00_read_flash_byte(ha,
2388                                     iter + 3) == '/')
2389                                         do_next++;
2390                         }
2391                 }
2392                 if (!do_next)
2393                         break;
2394
2395                 /* Backtrack to previous ' ' (space). */
2396                 do_next = 0;
2397                 while ((iter > istart) && !do_next) {
2398                         iter--;
2399                         if (qla2x00_read_flash_byte(ha, iter) == ' ')
2400                                 do_next++;
2401                 }
2402                 if (!do_next)
2403                         break;
2404
2405                 /*
2406                  * Mark end of version tag, and find previous ' ' (space) or
2407                  * string length (recent FCODE images -- major hack ahead!!!).
2408                  */
2409                 vend = iter - 1;
2410                 do_next = 0;
2411                 while ((iter > istart) && !do_next) {
2412                         iter--;
2413                         rbyte = qla2x00_read_flash_byte(ha, iter);
2414                         if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10)
2415                                 do_next++;
2416                 }
2417                 if (!do_next)
2418                         break;
2419
2420                 /* Mark beginning of version tag, and copy data. */
2421                 iter++;
2422                 if ((vend - iter) &&
2423                     ((vend - iter) < sizeof(ha->fcode_revision))) {
2424                         vbyte = ha->fcode_revision;
2425                         while (iter <= vend) {
2426                                 *vbyte++ = qla2x00_read_flash_byte(ha, iter);
2427                                 iter++;
2428                         }
2429                         ret = QLA_SUCCESS;
2430                 }
2431         } while (0);
2432
2433         if (ret != QLA_SUCCESS)
2434                 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2435 }
2436
2437 int
2438 qla2x00_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
2439 {
2440         int ret = QLA_SUCCESS;
2441         uint8_t code_type, last_image;
2442         uint32_t pcihdr, pcids;
2443         uint8_t *dbyte;
2444         uint16_t *dcode;
2445         struct qla_hw_data *ha = vha->hw;
2446
2447         if (!ha->pio_address || !mbuf)
2448                 return QLA_FUNCTION_FAILED;
2449
2450         memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2451         memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2452         memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2453         memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2454
2455         qla2x00_flash_enable(ha);
2456
2457         /* Begin with first PCI expansion ROM header. */
2458         pcihdr = 0;
2459         last_image = 1;
2460         do {
2461                 /* Verify PCI expansion ROM header. */
2462                 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 ||
2463                     qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) {
2464                         /* No signature */
2465                         DEBUG2(qla_printk(KERN_DEBUG, ha, "No matching ROM "
2466                             "signature.\n"));
2467                         ret = QLA_FUNCTION_FAILED;
2468                         break;
2469                 }
2470
2471                 /* Locate PCI data structure. */
2472                 pcids = pcihdr +
2473                     ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) |
2474                         qla2x00_read_flash_byte(ha, pcihdr + 0x18));
2475
2476                 /* Validate signature of PCI data structure. */
2477                 if (qla2x00_read_flash_byte(ha, pcids) != 'P' ||
2478                     qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' ||
2479                     qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' ||
2480                     qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') {
2481                         /* Incorrect header. */
2482                         DEBUG2(qla_printk(KERN_INFO, ha, "PCI data struct not "
2483                             "found pcir_adr=%x.\n", pcids));
2484                         ret = QLA_FUNCTION_FAILED;
2485                         break;
2486                 }
2487
2488                 /* Read version */
2489                 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14);
2490                 switch (code_type) {
2491                 case ROM_CODE_TYPE_BIOS:
2492                         /* Intel x86, PC-AT compatible. */
2493                         ha->bios_revision[0] =
2494                             qla2x00_read_flash_byte(ha, pcids + 0x12);
2495                         ha->bios_revision[1] =
2496                             qla2x00_read_flash_byte(ha, pcids + 0x13);
2497                         DEBUG3(qla_printk(KERN_DEBUG, ha, "read BIOS %d.%d.\n",
2498                             ha->bios_revision[1], ha->bios_revision[0]));
2499                         break;
2500                 case ROM_CODE_TYPE_FCODE:
2501                         /* Open Firmware standard for PCI (FCode). */
2502                         /* Eeeewww... */
2503                         qla2x00_get_fcode_version(ha, pcids);
2504                         break;
2505                 case ROM_CODE_TYPE_EFI:
2506                         /* Extensible Firmware Interface (EFI). */
2507                         ha->efi_revision[0] =
2508                             qla2x00_read_flash_byte(ha, pcids + 0x12);
2509                         ha->efi_revision[1] =
2510                             qla2x00_read_flash_byte(ha, pcids + 0x13);
2511                         DEBUG3(qla_printk(KERN_DEBUG, ha, "read EFI %d.%d.\n",
2512                             ha->efi_revision[1], ha->efi_revision[0]));
2513                         break;
2514                 default:
2515                         DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized code "
2516                             "type %x at pcids %x.\n", code_type, pcids));
2517                         break;
2518                 }
2519
2520                 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7;
2521
2522                 /* Locate next PCI expansion ROM. */
2523                 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) |
2524                     qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512;
2525         } while (!last_image);
2526
2527         if (IS_QLA2322(ha)) {
2528                 /* Read firmware image information. */
2529                 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2530                 dbyte = mbuf;
2531                 memset(dbyte, 0, 8);
2532                 dcode = (uint16_t *)dbyte;
2533
2534                 qla2x00_read_flash_data(ha, dbyte, ha->flt_region_fw * 4 + 10,
2535                     8);
2536                 DEBUG3(qla_printk(KERN_DEBUG, ha, "dumping fw ver from "
2537                     "flash:\n"));
2538                 DEBUG3(qla2x00_dump_buffer((uint8_t *)dbyte, 8));
2539
2540                 if ((dcode[0] == 0xffff && dcode[1] == 0xffff &&
2541                     dcode[2] == 0xffff && dcode[3] == 0xffff) ||
2542                     (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2543                     dcode[3] == 0)) {
2544                         DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized fw "
2545                             "revision at %x.\n", ha->flt_region_fw * 4));
2546                 } else {
2547                         /* values are in big endian */
2548                         ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1];
2549                         ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3];
2550                         ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5];
2551                 }
2552         }
2553
2554         qla2x00_flash_disable(ha);
2555
2556         return ret;
2557 }
2558
2559 int
2560 qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
2561 {
2562         int ret = QLA_SUCCESS;
2563         uint32_t pcihdr, pcids;
2564         uint32_t *dcode;
2565         uint8_t *bcode;
2566         uint8_t code_type, last_image;
2567         int i;
2568         struct qla_hw_data *ha = vha->hw;
2569
2570         if (!mbuf)
2571                 return QLA_FUNCTION_FAILED;
2572
2573         memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2574         memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2575         memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2576         memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2577
2578         dcode = mbuf;
2579
2580         /* Begin with first PCI expansion ROM header. */
2581         pcihdr = ha->flt_region_boot << 2;
2582         last_image = 1;
2583         do {
2584                 /* Verify PCI expansion ROM header. */
2585                 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
2586                 bcode = mbuf + (pcihdr % 4);
2587                 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) {
2588                         /* No signature */
2589                         DEBUG2(qla_printk(KERN_DEBUG, ha, "No matching ROM "
2590                             "signature.\n"));
2591                         ret = QLA_FUNCTION_FAILED;
2592                         break;
2593                 }
2594
2595                 /* Locate PCI data structure. */
2596                 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
2597
2598                 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
2599                 bcode = mbuf + (pcihdr % 4);
2600
2601                 /* Validate signature of PCI data structure. */
2602                 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
2603                     bcode[0x2] != 'I' || bcode[0x3] != 'R') {
2604                         /* Incorrect header. */
2605                         DEBUG2(qla_printk(KERN_INFO, ha, "PCI data struct not "
2606                             "found pcir_adr=%x.\n", pcids));
2607                         ret = QLA_FUNCTION_FAILED;
2608                         break;
2609                 }
2610
2611                 /* Read version */
2612                 code_type = bcode[0x14];
2613                 switch (code_type) {
2614                 case ROM_CODE_TYPE_BIOS:
2615                         /* Intel x86, PC-AT compatible. */
2616                         ha->bios_revision[0] = bcode[0x12];
2617                         ha->bios_revision[1] = bcode[0x13];
2618                         DEBUG3(qla_printk(KERN_DEBUG, ha, "read BIOS %d.%d.\n",
2619                             ha->bios_revision[1], ha->bios_revision[0]));
2620                         break;
2621                 case ROM_CODE_TYPE_FCODE:
2622                         /* Open Firmware standard for PCI (FCode). */
2623                         ha->fcode_revision[0] = bcode[0x12];
2624                         ha->fcode_revision[1] = bcode[0x13];
2625                         DEBUG3(qla_printk(KERN_DEBUG, ha, "read FCODE %d.%d.\n",
2626                             ha->fcode_revision[1], ha->fcode_revision[0]));
2627                         break;
2628                 case ROM_CODE_TYPE_EFI:
2629                         /* Extensible Firmware Interface (EFI). */
2630                         ha->efi_revision[0] = bcode[0x12];
2631                         ha->efi_revision[1] = bcode[0x13];
2632                         DEBUG3(qla_printk(KERN_DEBUG, ha, "read EFI %d.%d.\n",
2633                             ha->efi_revision[1], ha->efi_revision[0]));
2634                         break;
2635                 default:
2636                         DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized code "
2637                             "type %x at pcids %x.\n", code_type, pcids));
2638                         break;
2639                 }
2640
2641                 last_image = bcode[0x15] & BIT_7;
2642
2643                 /* Locate next PCI expansion ROM. */
2644                 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
2645         } while (!last_image);
2646
2647         /* Read firmware image information. */
2648         memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2649         dcode = mbuf;
2650
2651         qla24xx_read_flash_data(vha, dcode, ha->flt_region_fw + 4, 4);
2652         for (i = 0; i < 4; i++)
2653                 dcode[i] = be32_to_cpu(dcode[i]);
2654
2655         if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
2656             dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
2657             (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2658             dcode[3] == 0)) {
2659                 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized fw "
2660                     "revision at %x.\n", ha->flt_region_fw * 4));
2661         } else {
2662                 ha->fw_revision[0] = dcode[0];
2663                 ha->fw_revision[1] = dcode[1];
2664                 ha->fw_revision[2] = dcode[2];
2665                 ha->fw_revision[3] = dcode[3];
2666         }
2667
2668         return ret;
2669 }
2670
2671 static int
2672 qla2xxx_is_vpd_valid(uint8_t *pos, uint8_t *end)
2673 {
2674         if (pos >= end || *pos != 0x82)
2675                 return 0;
2676
2677         pos += 3 + pos[1];
2678         if (pos >= end || *pos != 0x90)
2679                 return 0;
2680
2681         pos += 3 + pos[1];
2682         if (pos >= end || *pos != 0x78)
2683                 return 0;
2684
2685         return 1;
2686 }
2687
2688 int
2689 qla2xxx_get_vpd_field(scsi_qla_host_t *vha, char *key, char *str, size_t size)
2690 {
2691         struct qla_hw_data *ha = vha->hw;
2692         uint8_t *pos = ha->vpd;
2693         uint8_t *end = pos + ha->vpd_size;
2694         int len = 0;
2695
2696         if (!IS_FWI2_CAPABLE(ha) || !qla2xxx_is_vpd_valid(pos, end))
2697                 return 0;
2698
2699         while (pos < end && *pos != 0x78) {
2700                 len = (*pos == 0x82) ? pos[1] : pos[2];
2701
2702                 if (!strncmp(pos, key, strlen(key)))
2703                         break;
2704
2705                 if (*pos != 0x90 && *pos != 0x91)
2706                         pos += len;
2707
2708                 pos += 3;
2709         }
2710
2711         if (pos < end - len && *pos != 0x78)
2712                 return snprintf(str, size, "%.*s", len, pos + 3);
2713
2714         return 0;
2715 }