drivers/net/wireless/rt2x00/rt2800pci.c

   1 /*
   2         Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com>
   3         Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   4         Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   5         Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
   6         Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
   7         Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
   8         Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
   9         Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
  10         <http://rt2x00.serialmonkey.com>
  11
  12         This program is free software; you can redistribute it and/or modify
  13         it under the terms of the GNU General Public License as published by
  14         the Free Software Foundation; either version 2 of the License, or
  15         (at your option) any later version.
  16
  17         This program is distributed in the hope that it will be useful,
  18         but WITHOUT ANY WARRANTY; without even the implied warranty of
  19         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20         GNU General Public License for more details.
  21
  22         You should have received a copy of the GNU General Public License
  23         along with this program; if not, write to the
  24         Free Software Foundation, Inc.,
  25         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  26  */
  27
  28 /*
  29         Module: rt2800pci
  30         Abstract: rt2800pci device specific routines.
  31         Supported chipsets: RT2800E & RT2800ED.
  32  */
  33
  34 #include <linux/crc-ccitt.h>
  35 #include <linux/delay.h>
  36 #include <linux/etherdevice.h>
  37 #include <linux/init.h>
  38 #include <linux/kernel.h>
  39 #include <linux/module.h>
  40 #include <linux/pci.h>
  41 #include <linux/platform_device.h>
  42 #include <linux/eeprom_93cx6.h>
  43
  44 #include "rt2x00.h"
  45 #include "rt2x00pci.h"
  46 #include "rt2x00soc.h"
  47 #include "rt2800lib.h"
  48 #include "rt2800.h"
  49 #include "rt2800pci.h"
  50
  51 /*
  52  * Allow hardware encryption to be disabled.
  53  */
  54 static int modparam_nohwcrypt = 1;
  55 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  56 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  57
  58 static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
  59 {
  60         unsigned int i;
  61         u32 reg;
  62
  63         for (i = 0; i < 200; i++) {
  64                 rt2800_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
  65
  66                 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
  67                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
  68                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
  69                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
  70                         break;
  71
  72                 udelay(REGISTER_BUSY_DELAY);
  73         }
  74
  75         if (i == 200)
  76                 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
  77
  78         rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
  79         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
  80 }
  81
  82 #ifdef CONFIG_RT2800PCI_SOC
  83 static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
  84 {
  85         u32 *base_addr = (u32 *) KSEG1ADDR(0x1F040000); /* XXX for RT3052 */
  86
  87         memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
  88 }
  89 #else
  90 static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
  91 {
  92 }
  93 #endif /* CONFIG_RT2800PCI_SOC */
  94
  95 #ifdef CONFIG_RT2800PCI_PCI
  96 static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
  97 {
  98         struct rt2x00_dev *rt2x00dev = eeprom->data;
  99         u32 reg;
 100
 101         rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
 102
 103         eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
 104         eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
 105         eeprom->reg_data_clock =
 106             !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
 107         eeprom->reg_chip_select =
 108             !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
 109 }
 110
 111 static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 112 {
 113         struct rt2x00_dev *rt2x00dev = eeprom->data;
 114         u32 reg = 0;
 115
 116         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
 117         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
 118         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
 119                            !!eeprom->reg_data_clock);
 120         rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
 121                            !!eeprom->reg_chip_select);
 122
 123         rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
 124 }
 125
 126 static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
 127 {
 128         struct eeprom_93cx6 eeprom;
 129         u32 reg;
 130
 131         rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
 132
 133         eeprom.data = rt2x00dev;
 134         eeprom.register_read = rt2800pci_eepromregister_read;
 135         eeprom.register_write = rt2800pci_eepromregister_write;
 136         eeprom.width = !rt2x00_get_field32(reg, E2PROM_CSR_TYPE) ?
 137             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
 138         eeprom.reg_data_in = 0;
 139         eeprom.reg_data_out = 0;
 140         eeprom.reg_data_clock = 0;
 141         eeprom.reg_chip_select = 0;
 142
 143         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
 144                                EEPROM_SIZE / sizeof(u16));
 145 }
 146
 147 static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
 148 {
 149         return rt2800_efuse_detect(rt2x00dev);
 150 }
 151
 152 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
 153 {
 154         rt2800_read_eeprom_efuse(rt2x00dev);
 155 }
 156 #else
 157 static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
 158 {
 159 }
 160
 161 static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
 162 {
 163         return 0;
 164 }
 165
 166 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
 167 {
 168 }
 169 #endif /* CONFIG_RT2800PCI_PCI */
 170
 171 /*
 172  * Firmware functions
 173  */
 174 static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
 175 {
 176         return FIRMWARE_RT2860;
 177 }
 178
 179 static int rt2800pci_check_firmware(struct rt2x00_dev *rt2x00dev,
 180                                     const u8 *data, const size_t len)
 181 {
 182         u16 fw_crc;
 183         u16 crc;
 184
 185         /*
 186          * Only support 8kb firmware files.
 187          */
 188         if (len != 8192)
 189                 return FW_BAD_LENGTH;
 190
 191         /*
 192          * The last 2 bytes in the firmware array are the crc checksum itself,
 193          * this means that we should never pass those 2 bytes to the crc
 194          * algorithm.
 195          */
 196         fw_crc = (data[len - 2] << 8 | data[len - 1]);
 197
 198         /*
 199          * Use the crc ccitt algorithm.
 200          * This will return the same value as the legacy driver which
 201          * used bit ordering reversion on the both the firmware bytes
 202          * before input input as well as on the final output.
 203          * Obviously using crc ccitt directly is much more efficient.
 204          */
 205         crc = crc_ccitt(~0, data, len - 2);
 206
 207         /*
 208          * There is a small difference between the crc-itu-t + bitrev and
 209          * the crc-ccitt crc calculation. In the latter method the 2 bytes
 210          * will be swapped, use swab16 to convert the crc to the correct
 211          * value.
 212          */
 213         crc = swab16(crc);
 214
 215         return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
 216 }
 217
 218 static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
 219                                    const u8 *data, const size_t len)
 220 {
 221         unsigned int i;
 222         u32 reg;
 223
 224         /*
 225          * Wait for stable hardware.
 226          */
 227         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 228                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
 229                 if (reg && reg != ~0)
 230                         break;
 231                 msleep(1);
 232         }
 233
 234         if (i == REGISTER_BUSY_COUNT) {
 235                 ERROR(rt2x00dev, "Unstable hardware.\n");
 236                 return -EBUSY;
 237         }
 238
 239         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
 240         rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
 241
 242         /*
 243          * Disable DMA, will be reenabled later when enabling
 244          * the radio.
 245          */
 246         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 247         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 248         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
 249         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 250         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
 251         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 252         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 253
 254         /*
 255          * enable Host program ram write selection
 256          */
 257         reg = 0;
 258         rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
 259         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
 260
 261         /*
 262          * Write firmware to device.
 263          */
 264         rt2800_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
 265                                       data, len);
 266
 267         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
 268         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
 269
 270         /*
 271          * Wait for device to stabilize.
 272          */
 273         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 274                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
 275                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
 276                         break;
 277                 msleep(1);
 278         }
 279
 280         if (i == REGISTER_BUSY_COUNT) {
 281                 ERROR(rt2x00dev, "PBF system register not ready.\n");
 282                 return -EBUSY;
 283         }
 284
 285         /*
 286          * Disable interrupts
 287          */
 288         rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_RADIO_IRQ_OFF);
 289
 290         /*
 291          * Initialize BBP R/W access agent
 292          */
 293         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
 294         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 295
 296         return 0;
 297 }
 298
 299 /*
 300  * Initialization functions.
 301  */
 302 static bool rt2800pci_get_entry_state(struct queue_entry *entry)
 303 {
 304         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 305         u32 word;
 306
 307         if (entry->queue->qid == QID_RX) {
 308                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 309
 310                 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
 311         } else {
 312                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 313
 314                 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
 315         }
 316 }
 317
 318 static void rt2800pci_clear_entry(struct queue_entry *entry)
 319 {
 320         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 321         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 322         u32 word;
 323
 324         if (entry->queue->qid == QID_RX) {
 325                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 326                 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
 327                 rt2x00_desc_write(entry_priv->desc, 0, word);
 328
 329                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 330                 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
 331                 rt2x00_desc_write(entry_priv->desc, 1, word);
 332         } else {
 333                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 334                 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
 335                 rt2x00_desc_write(entry_priv->desc, 1, word);
 336         }
 337 }
 338
 339 static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
 340 {
 341         struct queue_entry_priv_pci *entry_priv;
 342         u32 reg;
 343
 344         rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
 345         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
 346         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
 347         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
 348         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
 349         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
 350         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
 351         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
 352         rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
 353
 354         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
 355         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
 356
 357         /*
 358          * Initialize registers.
 359          */
 360         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
 361         rt2800_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
 362         rt2800_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
 363         rt2800_register_write(rt2x00dev, TX_CTX_IDX0, 0);
 364         rt2800_register_write(rt2x00dev, TX_DTX_IDX0, 0);
 365
 366         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
 367         rt2800_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
 368         rt2800_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
 369         rt2800_register_write(rt2x00dev, TX_CTX_IDX1, 0);
 370         rt2800_register_write(rt2x00dev, TX_DTX_IDX1, 0);
 371
 372         entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
 373         rt2800_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
 374         rt2800_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
 375         rt2800_register_write(rt2x00dev, TX_CTX_IDX2, 0);
 376         rt2800_register_write(rt2x00dev, TX_DTX_IDX2, 0);
 377
 378         entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
 379         rt2800_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
 380         rt2800_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
 381         rt2800_register_write(rt2x00dev, TX_CTX_IDX3, 0);
 382         rt2800_register_write(rt2x00dev, TX_DTX_IDX3, 0);
 383
 384         entry_priv = rt2x00dev->rx->entries[0].priv_data;
 385         rt2800_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
 386         rt2800_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
 387         rt2800_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1);
 388         rt2800_register_write(rt2x00dev, RX_DRX_IDX, 0);
 389
 390         /*
 391          * Enable global DMA configuration
 392          */
 393         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 394         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 395         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 396         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 397         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 398
 399         rt2800_register_write(rt2x00dev, DELAY_INT_CFG, 0);
 400
 401         return 0;
 402 }
 403
 404 /*
 405  * Device state switch handlers.
 406  */
 407 static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
 408                                 enum dev_state state)
 409 {
 410         u32 reg;
 411
 412         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
 413         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
 414                            (state == STATE_RADIO_RX_ON) ||
 415                            (state == STATE_RADIO_RX_ON_LINK));
 416         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
 417 }
 418
 419 static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
 420                                  enum dev_state state)
 421 {
 422         int mask = (state == STATE_RADIO_IRQ_ON);
 423         u32 reg;
 424
 425         /*
 426          * When interrupts are being enabled, the interrupt registers
 427          * should clear the register to assure a clean state.
 428          */
 429         if (state == STATE_RADIO_IRQ_ON) {
 430                 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
 431                 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
 432         }
 433
 434         rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
 435         rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, mask);
 436         rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, mask);
 437         rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
 438         rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, mask);
 439         rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, mask);
 440         rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, mask);
 441         rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, mask);
 442         rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, mask);
 443         rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, mask);
 444         rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, mask);
 445         rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, mask);
 446         rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
 447         rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
 448         rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
 449         rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
 450         rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, mask);
 451         rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, mask);
 452         rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, mask);
 453         rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
 454 }
 455
 456 static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
 457 {
 458         u32 reg;
 459         u16 word;
 460
 461         /*
 462          * Initialize all registers.
 463          */
 464         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
 465                      rt2800pci_init_queues(rt2x00dev) ||
 466                      rt2800_init_registers(rt2x00dev) ||
 467                      rt2800_wait_wpdma_ready(rt2x00dev) ||
 468                      rt2800_init_bbp(rt2x00dev) ||
 469                      rt2800_init_rfcsr(rt2x00dev)))
 470                 return -EIO;
 471
 472         /*
 473          * Send signal to firmware during boot time.
 474          */
 475         rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
 476
 477         /*
 478          * Enable RX.
 479          */
 480         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
 481         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
 482         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
 483         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
 484
 485         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 486         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
 487         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
 488         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
 489         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 490         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 491
 492         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
 493         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
 494         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
 495         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
 496
 497         /*
 498          * Initialize LED control
 499          */
 500         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
 501         rt2800_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
 502                               word & 0xff, (word >> 8) & 0xff);
 503
 504         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
 505         rt2800_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
 506                               word & 0xff, (word >> 8) & 0xff);
 507
 508         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
 509         rt2800_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
 510                               word & 0xff, (word >> 8) & 0xff);
 511
 512         return 0;
 513 }
 514
 515 static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
 516 {
 517         u32 reg;
 518
 519         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 520         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 521         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
 522         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 523         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
 524         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 525         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 526
 527         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
 528         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
 529         rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
 530
 531         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
 532
 533         rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
 534         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
 535         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
 536         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
 537         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
 538         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
 539         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
 540         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
 541         rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
 542
 543         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
 544         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
 545
 546         /* Wait for DMA, ignore error */
 547         rt2800_wait_wpdma_ready(rt2x00dev);
 548 }
 549
 550 static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
 551                                enum dev_state state)
 552 {
 553         /*
 554          * Always put the device to sleep (even when we intend to wakeup!)
 555          * if the device is booting and wasn't asleep it will return
 556          * failure when attempting to wakeup.
 557          */
 558         rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
 559
 560         if (state == STATE_AWAKE) {
 561                 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0);
 562                 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
 563         }
 564
 565         return 0;
 566 }
 567
 568 static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
 569                                       enum dev_state state)
 570 {
 571         int retval = 0;
 572
 573         switch (state) {
 574         case STATE_RADIO_ON:
 575                 /*
 576                  * Before the radio can be enabled, the device first has
 577                  * to be woken up. After that it needs a bit of time
 578                  * to be fully awake and then the radio can be enabled.
 579                  */
 580                 rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
 581                 msleep(1);
 582                 retval = rt2800pci_enable_radio(rt2x00dev);
 583                 break;
 584         case STATE_RADIO_OFF:
 585                 /*
 586                  * After the radio has been disabled, the device should
 587                  * be put to sleep for powersaving.
 588                  */
 589                 rt2800pci_disable_radio(rt2x00dev);
 590                 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
 591                 break;
 592         case STATE_RADIO_RX_ON:
 593         case STATE_RADIO_RX_ON_LINK:
 594         case STATE_RADIO_RX_OFF:
 595         case STATE_RADIO_RX_OFF_LINK:
 596                 rt2800pci_toggle_rx(rt2x00dev, state);
 597                 break;
 598         case STATE_RADIO_IRQ_ON:
 599         case STATE_RADIO_IRQ_OFF:
 600                 rt2800pci_toggle_irq(rt2x00dev, state);
 601                 break;
 602         case STATE_DEEP_SLEEP:
 603         case STATE_SLEEP:
 604         case STATE_STANDBY:
 605         case STATE_AWAKE:
 606                 retval = rt2800pci_set_state(rt2x00dev, state);
 607                 break;
 608         default:
 609                 retval = -ENOTSUPP;
 610                 break;
 611         }
 612
 613         if (unlikely(retval))
 614                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
 615                       state, retval);
 616
 617         return retval;
 618 }
 619
 620 /*
 621  * TX descriptor initialization
 622  */
 623 static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
 624                                     struct sk_buff *skb,
 625                                     struct txentry_desc *txdesc)
 626 {
 627         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
 628         __le32 *txd = skbdesc->desc;
 629         __le32 *txwi = (__le32 *)(skb->data - rt2x00dev->ops->extra_tx_headroom);
 630         u32 word;
 631
 632         /*
 633          * Initialize TX Info descriptor
 634          */
 635         rt2x00_desc_read(txwi, 0, &word);
 636         rt2x00_set_field32(&word, TXWI_W0_FRAG,
 637                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 638         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
 639         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
 640         rt2x00_set_field32(&word, TXWI_W0_TS,
 641                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
 642         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
 643                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
 644         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
 645         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
 646         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
 647         rt2x00_set_field32(&word, TXWI_W0_BW,
 648                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
 649         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
 650                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
 651         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
 652         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
 653         rt2x00_desc_write(txwi, 0, word);
 654
 655         rt2x00_desc_read(txwi, 1, &word);
 656         rt2x00_set_field32(&word, TXWI_W1_ACK,
 657                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
 658         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
 659                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
 660         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
 661         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
 662                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
 663                            txdesc->key_idx : 0xff);
 664         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
 665                            skb->len - txdesc->l2pad);
 666         rt2x00_set_field32(&word, TXWI_W1_PACKETID,
 667                            skbdesc->entry->queue->qid + 1);
 668         rt2x00_desc_write(txwi, 1, word);
 669
 670         /*
 671          * Always write 0 to IV/EIV fields, hardware will insert the IV
 672          * from the IVEIV register when TXD_W3_WIV is set to 0.
 673          * When TXD_W3_WIV is set to 1 it will use the IV data
 674          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
 675          * crypto entry in the registers should be used to encrypt the frame.
 676          */
 677         _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
 678         _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
 679
 680         /*
 681          * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
 682          * must contains a TXWI structure + 802.11 header + padding + 802.11
 683          * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
 684          * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
 685          * data. It means that LAST_SEC0 is always 0.
 686          */
 687
 688         /*
 689          * Initialize TX descriptor
 690          */
 691         rt2x00_desc_read(txd, 0, &word);
 692         rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
 693         rt2x00_desc_write(txd, 0, word);
 694
 695         rt2x00_desc_read(txd, 1, &word);
 696         rt2x00_set_field32(&word, TXD_W1_SD_LEN1, skb->len);
 697         rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
 698                            !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 699         rt2x00_set_field32(&word, TXD_W1_BURST,
 700                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
 701         rt2x00_set_field32(&word, TXD_W1_SD_LEN0,
 702                            rt2x00dev->ops->extra_tx_headroom);
 703         rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
 704         rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
 705         rt2x00_desc_write(txd, 1, word);
 706
 707         rt2x00_desc_read(txd, 2, &word);
 708         rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
 709                            skbdesc->skb_dma + rt2x00dev->ops->extra_tx_headroom);
 710         rt2x00_desc_write(txd, 2, word);
 711
 712         rt2x00_desc_read(txd, 3, &word);
 713         rt2x00_set_field32(&word, TXD_W3_WIV,
 714                            !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
 715         rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
 716         rt2x00_desc_write(txd, 3, word);
 717 }
 718
 719 /*
 720  * TX data initialization
 721  */
 722 static void rt2800pci_write_beacon(struct queue_entry *entry)
 723 {
 724         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 725         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 726         unsigned int beacon_base;
 727         u32 reg;
 728
 729         /*
 730          * Disable beaconing while we are reloading the beacon data,
 731          * otherwise we might be sending out invalid data.
 732          */
 733         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 734         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 735         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 736
 737         /*
 738          * Write entire beacon with descriptor to register.
 739          */
 740         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
 741         rt2800_register_multiwrite(rt2x00dev,
 742                                       beacon_base,
 743                                       skbdesc->desc, skbdesc->desc_len);
 744         rt2800_register_multiwrite(rt2x00dev,
 745                                       beacon_base + skbdesc->desc_len,
 746                                       entry->skb->data, entry->skb->len);
 747
 748         /*
 749          * Clean up beacon skb.
 750          */
 751         dev_kfree_skb_any(entry->skb);
 752         entry->skb = NULL;
 753 }
 754
 755 static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
 756                                     const enum data_queue_qid queue_idx)
 757 {
 758         struct data_queue *queue;
 759         unsigned int idx, qidx = 0;
 760         u32 reg;
 761
 762         if (queue_idx == QID_BEACON) {
 763                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 764                 if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
 765                         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
 766                         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
 767                         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
 768                         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 769                 }
 770                 return;
 771         }
 772
 773         if (queue_idx > QID_HCCA && queue_idx != QID_MGMT)
 774                 return;
 775
 776         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
 777         idx = queue->index[Q_INDEX];
 778
 779         if (queue_idx == QID_MGMT)
 780                 qidx = 5;
 781         else
 782                 qidx = queue_idx;
 783
 784         rt2800_register_write(rt2x00dev, TX_CTX_IDX(qidx), idx);
 785 }
 786
 787 static void rt2800pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
 788                                     const enum data_queue_qid qid)
 789 {
 790         u32 reg;
 791
 792         if (qid == QID_BEACON) {
 793                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, 0);
 794                 return;
 795         }
 796
 797         rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
 798         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, (qid == QID_AC_BE));
 799         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, (qid == QID_AC_BK));
 800         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, (qid == QID_AC_VI));
 801         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, (qid == QID_AC_VO));
 802         rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
 803 }
 804
 805 /*
 806  * RX control handlers
 807  */
 808 static void rt2800pci_fill_rxdone(struct queue_entry *entry,
 809                                   struct rxdone_entry_desc *rxdesc)
 810 {
 811         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 812         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 813         __le32 *rxd = entry_priv->desc;
 814         __le32 *rxwi = (__le32 *)entry->skb->data;
 815         u32 rxd3;
 816         u32 rxwi0;
 817         u32 rxwi1;
 818         u32 rxwi2;
 819         u32 rxwi3;
 820
 821         rt2x00_desc_read(rxd, 3, &rxd3);
 822         rt2x00_desc_read(rxwi, 0, &rxwi0);
 823         rt2x00_desc_read(rxwi, 1, &rxwi1);
 824         rt2x00_desc_read(rxwi, 2, &rxwi2);
 825         rt2x00_desc_read(rxwi, 3, &rxwi3);
 826
 827         if (rt2x00_get_field32(rxd3, RXD_W3_CRC_ERROR))
 828                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
 829
 830         if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
 831                 /*
 832                  * Unfortunately we don't know the cipher type used during
 833                  * decryption. This prevents us from correct providing
 834                  * correct statistics through debugfs.
 835                  */
 836                 rxdesc->cipher = rt2x00_get_field32(rxwi0, RXWI_W0_UDF);
 837                 rxdesc->cipher_status =
 838                     rt2x00_get_field32(rxd3, RXD_W3_CIPHER_ERROR);
 839         }
 840
 841         if (rt2x00_get_field32(rxd3, RXD_W3_DECRYPTED)) {
 842                 /*
 843                  * Hardware has stripped IV/EIV data from 802.11 frame during
 844                  * decryption. Unfortunately the descriptor doesn't contain
 845                  * any fields with the EIV/IV data either, so they can't
 846                  * be restored by rt2x00lib.
 847                  */
 848                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
 849
 850                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
 851                         rxdesc->flags |= RX_FLAG_DECRYPTED;
 852                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
 853                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
 854         }
 855
 856         if (rt2x00_get_field32(rxd3, RXD_W3_MY_BSS))
 857                 rxdesc->dev_flags |= RXDONE_MY_BSS;
 858
 859         if (rt2x00_get_field32(rxd3, RXD_W3_L2PAD))
 860                 rxdesc->dev_flags |= RXDONE_L2PAD;
 861
 862         if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
 863                 rxdesc->flags |= RX_FLAG_SHORT_GI;
 864
 865         if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
 866                 rxdesc->flags |= RX_FLAG_40MHZ;
 867
 868         /*
 869          * Detect RX rate, always use MCS as signal type.
 870          */
 871         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
 872         rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
 873         rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
 874
 875         /*
 876          * Mask of 0x8 bit to remove the short preamble flag.
 877          */
 878         if (rxdesc->rate_mode == RATE_MODE_CCK)
 879                 rxdesc->signal &= ~0x8;
 880
 881         rxdesc->rssi =
 882             (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
 883              rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1)) / 2;
 884
 885         rxdesc->noise =
 886             (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
 887              rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
 888
 889         rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
 890
 891         /*
 892          * Set RX IDX in register to inform hardware that we have handled
 893          * this entry and it is available for reuse again.
 894          */
 895         rt2800_register_write(rt2x00dev, RX_CRX_IDX, entry->entry_idx);
 896
 897         /*
 898          * Remove TXWI descriptor from start of buffer.
 899          */
 900         skb_pull(entry->skb, RXWI_DESC_SIZE);
 901 }
 902
 903 /*
 904  * Interrupt functions.
 905  */
 906 static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
 907 {
 908         struct data_queue *queue;
 909         struct queue_entry *entry;
 910         struct queue_entry *entry_done;
 911         struct queue_entry_priv_pci *entry_priv;
 912         struct txdone_entry_desc txdesc;
 913         u32 word;
 914         u32 reg;
 915         u32 old_reg;
 916         unsigned int type;
 917         unsigned int index;
 918         u16 mcs, real_mcs;
 919
 920         /*
 921          * During each loop we will compare the freshly read
 922          * TX_STA_FIFO register value with the value read from
 923          * the previous loop. If the 2 values are equal then
 924          * we should stop processing because the chance it
 925          * quite big that the device has been unplugged and
 926          * we risk going into an endless loop.
 927          */
 928         old_reg = 0;
 929
 930         while (1) {
 931                 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
 932                 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
 933                         break;
 934
 935                 if (old_reg == reg)
 936                         break;
 937                 old_reg = reg;
 938
 939                 /*
 940                  * Skip this entry when it contains an invalid
 941                  * queue identication number.
 942                  */
 943                 type = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE) - 1;
 944                 if (type >= QID_RX)
 945                         continue;
 946
 947                 queue = rt2x00queue_get_queue(rt2x00dev, type);
 948                 if (unlikely(!queue))
 949                         continue;
 950
 951                 /*
 952                  * Skip this entry when it contains an invalid
 953                  * index number.
 954                  */
 955                 index = rt2x00_get_field32(reg, TX_STA_FIFO_WCID) - 1;
 956                 if (unlikely(index >= queue->limit))
 957                         continue;
 958
 959                 entry = &queue->entries[index];
 960                 entry_priv = entry->priv_data;
 961                 rt2x00_desc_read((__le32 *)entry->skb->data, 0, &word);
 962
 963                 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
 964                 while (entry != entry_done) {
 965                         /*
 966                          * Catch up.
 967                          * Just report any entries we missed as failed.
 968                          */
 969                         WARNING(rt2x00dev,
 970                                 "TX status report missed for entry %d\n",
 971                                 entry_done->entry_idx);
 972
 973                         txdesc.flags = 0;
 974                         __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
 975                         txdesc.retry = 0;
 976
 977                         rt2x00lib_txdone(entry_done, &txdesc);
 978                         entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
 979                 }
 980
 981                 /*
 982                  * Obtain the status about this packet.
 983                  */
 984                 txdesc.flags = 0;
 985                 if (rt2x00_get_field32(reg, TX_STA_FIFO_TX_SUCCESS))
 986                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
 987                 else
 988                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
 989
 990                 /*
 991                  * Ralink has a retry mechanism using a global fallback
 992                  * table. We setup this fallback table to try immediate
 993                  * lower rate for all rates. In the TX_STA_FIFO,
 994                  * the MCS field contains the MCS used for the successfull
 995                  * transmission. If the first transmission succeed,
 996                  * we have mcs == tx_mcs. On the second transmission,
 997                  * we have mcs = tx_mcs - 1. So the number of
 998                  * retry is (tx_mcs - mcs).
 999                  */
1000                 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
1001                 real_mcs = rt2x00_get_field32(reg, TX_STA_FIFO_MCS);
1002                 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
1003                 txdesc.retry = mcs - min(mcs, real_mcs);
1004
1005                 rt2x00lib_txdone(entry, &txdesc);
1006         }
1007 }
1008
1009 static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
1010 {
1011         struct rt2x00_dev *rt2x00dev = dev_instance;
1012         u32 reg;
1013
1014         /* Read status and ACK all interrupts */
1015         rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1016         rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1017
1018         if (!reg)
1019                 return IRQ_NONE;
1020
1021         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1022                 return IRQ_HANDLED;
1023
1024         /*
1025          * 1 - Rx ring done interrupt.
1026          */
1027         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
1028                 rt2x00pci_rxdone(rt2x00dev);
1029
1030         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS))
1031                 rt2800pci_txdone(rt2x00dev);
1032
1033         return IRQ_HANDLED;
1034 }
1035
1036 /*
1037  * Device probe functions.
1038  */
1039 static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1040 {
1041         /*
1042          * Read EEPROM into buffer
1043          */
1044         if (rt2x00_is_soc(rt2x00dev))
1045                 rt2800pci_read_eeprom_soc(rt2x00dev);
1046         else if (rt2800pci_efuse_detect(rt2x00dev))
1047                 rt2800pci_read_eeprom_efuse(rt2x00dev);
1048         else
1049                 rt2800pci_read_eeprom_pci(rt2x00dev);
1050
1051         return rt2800_validate_eeprom(rt2x00dev);
1052 }
1053
1054 static const struct rt2800_ops rt2800pci_rt2800_ops = {
1055         .register_read          = rt2x00pci_register_read,
1056         .register_read_lock     = rt2x00pci_register_read, /* same for PCI */
1057         .register_write         = rt2x00pci_register_write,
1058         .register_write_lock    = rt2x00pci_register_write, /* same for PCI */
1059
1060         .register_multiread     = rt2x00pci_register_multiread,
1061         .register_multiwrite    = rt2x00pci_register_multiwrite,
1062
1063         .regbusy_read           = rt2x00pci_regbusy_read,
1064 };
1065
1066 static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1067 {
1068         int retval;
1069
1070         rt2x00dev->priv = (void *)&rt2800pci_rt2800_ops;
1071
1072         /*
1073          * Allocate eeprom data.
1074          */
1075         retval = rt2800pci_validate_eeprom(rt2x00dev);
1076         if (retval)
1077                 return retval;
1078
1079         retval = rt2800_init_eeprom(rt2x00dev);
1080         if (retval)
1081                 return retval;
1082
1083         /*
1084          * Initialize hw specifications.
1085          */
1086         retval = rt2800_probe_hw_mode(rt2x00dev);
1087         if (retval)
1088                 return retval;
1089
1090         /*
1091          * This device has multiple filters for control frames
1092          * and has a separate filter for PS Poll frames.
1093          */
1094         __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
1095         __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags);
1096
1097         /*
1098          * This device requires firmware.
1099          */
1100         if (!rt2x00_is_soc(rt2x00dev))
1101                 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
1102         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1103         __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
1104         if (!modparam_nohwcrypt)
1105                 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
1106
1107         /*
1108          * Set the rssi offset.
1109          */
1110         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1111
1112         return 0;
1113 }
1114
1115 static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
1116         .irq_handler            = rt2800pci_interrupt,
1117         .probe_hw               = rt2800pci_probe_hw,
1118         .get_firmware_name      = rt2800pci_get_firmware_name,
1119         .check_firmware         = rt2800pci_check_firmware,
1120         .load_firmware          = rt2800pci_load_firmware,
1121         .initialize             = rt2x00pci_initialize,
1122         .uninitialize           = rt2x00pci_uninitialize,
1123         .get_entry_state        = rt2800pci_get_entry_state,
1124         .clear_entry            = rt2800pci_clear_entry,
1125         .set_device_state       = rt2800pci_set_device_state,
1126         .rfkill_poll            = rt2800_rfkill_poll,
1127         .link_stats             = rt2800_link_stats,
1128         .reset_tuner            = rt2800_reset_tuner,
1129         .link_tuner             = rt2800_link_tuner,
1130         .write_tx_desc          = rt2800pci_write_tx_desc,
1131         .write_tx_data          = rt2x00pci_write_tx_data,
1132         .write_beacon           = rt2800pci_write_beacon,
1133         .kick_tx_queue          = rt2800pci_kick_tx_queue,
1134         .kill_tx_queue          = rt2800pci_kill_tx_queue,
1135         .fill_rxdone            = rt2800pci_fill_rxdone,
1136         .config_shared_key      = rt2800_config_shared_key,
1137         .config_pairwise_key    = rt2800_config_pairwise_key,
1138         .config_filter          = rt2800_config_filter,
1139         .config_intf            = rt2800_config_intf,
1140         .config_erp             = rt2800_config_erp,
1141         .config_ant             = rt2800_config_ant,
1142         .config                 = rt2800_config,
1143 };
1144
1145 static const struct data_queue_desc rt2800pci_queue_rx = {
1146         .entry_num              = RX_ENTRIES,
1147         .data_size              = AGGREGATION_SIZE,
1148         .desc_size              = RXD_DESC_SIZE,
1149         .priv_size              = sizeof(struct queue_entry_priv_pci),
1150 };
1151
1152 static const struct data_queue_desc rt2800pci_queue_tx = {
1153         .entry_num              = TX_ENTRIES,
1154         .data_size              = AGGREGATION_SIZE,
1155         .desc_size              = TXD_DESC_SIZE,
1156         .priv_size              = sizeof(struct queue_entry_priv_pci),
1157 };
1158
1159 static const struct data_queue_desc rt2800pci_queue_bcn = {
1160         .entry_num              = 8 * BEACON_ENTRIES,
1161         .data_size              = 0, /* No DMA required for beacons */
1162         .desc_size              = TXWI_DESC_SIZE,
1163         .priv_size              = sizeof(struct queue_entry_priv_pci),
1164 };
1165
1166 static const struct rt2x00_ops rt2800pci_ops = {
1167         .name                   = KBUILD_MODNAME,
1168         .max_sta_intf           = 1,
1169         .max_ap_intf            = 8,
1170         .eeprom_size            = EEPROM_SIZE,
1171         .rf_size                = RF_SIZE,
1172         .tx_queues              = NUM_TX_QUEUES,
1173         .extra_tx_headroom      = TXWI_DESC_SIZE,
1174         .rx                     = &rt2800pci_queue_rx,
1175         .tx                     = &rt2800pci_queue_tx,
1176         .bcn                    = &rt2800pci_queue_bcn,
1177         .lib                    = &rt2800pci_rt2x00_ops,
1178         .hw                     = &rt2800_mac80211_ops,
1179 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1180         .debugfs                = &rt2800_rt2x00debug,
1181 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1182 };
1183
1184 /*
1185  * RT2800pci module information.
1186  */
1187 static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
1188         { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
1189         { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
1190         { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
1191         { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
1192         { PCI_DEVICE(0x1432, 0x7708), PCI_DEVICE_DATA(&rt2800pci_ops) },
1193         { PCI_DEVICE(0x1432, 0x7727), PCI_DEVICE_DATA(&rt2800pci_ops) },
1194         { PCI_DEVICE(0x1432, 0x7728), PCI_DEVICE_DATA(&rt2800pci_ops) },
1195         { PCI_DEVICE(0x1432, 0x7738), PCI_DEVICE_DATA(&rt2800pci_ops) },
1196         { PCI_DEVICE(0x1432, 0x7748), PCI_DEVICE_DATA(&rt2800pci_ops) },
1197         { PCI_DEVICE(0x1432, 0x7758), PCI_DEVICE_DATA(&rt2800pci_ops) },
1198         { PCI_DEVICE(0x1432, 0x7768), PCI_DEVICE_DATA(&rt2800pci_ops) },
1199         { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
1200 #ifdef CONFIG_RT2800PCI_RT30XX
1201         { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) },
1202         { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) },
1203         { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) },
1204         { PCI_DEVICE(0x1462, 0x891a), PCI_DEVICE_DATA(&rt2800pci_ops) },
1205 #endif
1206 #ifdef CONFIG_RT2800PCI_RT35XX
1207         { PCI_DEVICE(0x1814, 0x3060), PCI_DEVICE_DATA(&rt2800pci_ops) },
1208         { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) },
1209         { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) },
1210         { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) },
1211 #endif
1212         { 0, }
1213 };
1214
1215 MODULE_AUTHOR(DRV_PROJECT);
1216 MODULE_VERSION(DRV_VERSION);
1217 MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1218 MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
1219 #ifdef CONFIG_RT2800PCI_PCI
1220 MODULE_FIRMWARE(FIRMWARE_RT2860);
1221 MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
1222 #endif /* CONFIG_RT2800PCI_PCI */
1223 MODULE_LICENSE("GPL");
1224
1225 #ifdef CONFIG_RT2800PCI_SOC
1226 static int rt2800soc_probe(struct platform_device *pdev)
1227 {
1228         return rt2x00soc_probe(pdev, rt2800pci_ops);
1229 }
1230
1231 static struct platform_driver rt2800soc_driver = {
1232         .driver         = {
1233                 .name           = "rt2800_wmac",
1234                 .owner          = THIS_MODULE,
1235                 .mod_name       = KBUILD_MODNAME,
1236         },
1237         .probe          = rt2800soc_probe,
1238         .remove         = __devexit_p(rt2x00soc_remove),
1239         .suspend        = rt2x00soc_suspend,
1240         .resume         = rt2x00soc_resume,
1241 };
1242 #endif /* CONFIG_RT2800PCI_SOC */
1243
1244 #ifdef CONFIG_RT2800PCI_PCI
1245 static struct pci_driver rt2800pci_driver = {
1246         .name           = KBUILD_MODNAME,
1247         .id_table       = rt2800pci_device_table,
1248         .probe          = rt2x00pci_probe,
1249         .remove         = __devexit_p(rt2x00pci_remove),
1250         .suspend        = rt2x00pci_suspend,
1251         .resume         = rt2x00pci_resume,
1252 };
1253 #endif /* CONFIG_RT2800PCI_PCI */
1254
1255 static int __init rt2800pci_init(void)
1256 {
1257         int ret = 0;
1258
1259 #ifdef CONFIG_RT2800PCI_SOC
1260         ret = platform_driver_register(&rt2800soc_driver);
1261         if (ret)
1262                 return ret;
1263 #endif
1264 #ifdef CONFIG_RT2800PCI_PCI
1265         ret = pci_register_driver(&rt2800pci_driver);
1266         if (ret) {
1267 #ifdef CONFIG_RT2800PCI_SOC
1268                 platform_driver_unregister(&rt2800soc_driver);
1269 #endif
1270                 return ret;
1271         }
1272 #endif
1273
1274         return ret;
1275 }
1276
1277 static void __exit rt2800pci_exit(void)
1278 {
1279 #ifdef CONFIG_RT2800PCI_PCI
1280         pci_unregister_driver(&rt2800pci_driver);
1281 #endif
1282 #ifdef CONFIG_RT2800PCI_SOC
1283         platform_driver_unregister(&rt2800soc_driver);
1284 #endif
1285 }
1286
1287 module_init(rt2800pci_init);
1288 module_exit(rt2800pci_exit);