drivers/net/wireless/rt2x00/rt2800lib.c

   1 /*
   2         Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
   3         Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
   4
   5         Based on the original rt2800pci.c and rt2800usb.c.
   6           Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com>
   7           Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   8           Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   9           Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
  10           Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  11           Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  12           Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  13           <http://rt2x00.serialmonkey.com>
  14
  15         This program is free software; you can redistribute it and/or modify
  16         it under the terms of the GNU General Public License as published by
  17         the Free Software Foundation; either version 2 of the License, or
  18         (at your option) any later version.
  19
  20         This program is distributed in the hope that it will be useful,
  21         but WITHOUT ANY WARRANTY; without even the implied warranty of
  22         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23         GNU General Public License for more details.
  24
  25         You should have received a copy of the GNU General Public License
  26         along with this program; if not, write to the
  27         Free Software Foundation, Inc.,
  28         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  29  */
  30
  31 /*
  32         Module: rt2800lib
  33         Abstract: rt2800 generic device routines.
  34  */
  35
  36 #include <linux/kernel.h>
  37 #include <linux/module.h>
  38 #include <linux/slab.h>
  39
  40 #include "rt2x00.h"
  41 #if defined(CONFIG_RT2X00_LIB_USB) || defined(CONFIG_RT2X00_LIB_USB_MODULE)
  42 #include "rt2x00usb.h"
  43 #endif
  44 #if defined(CONFIG_RT2X00_LIB_PCI) || defined(CONFIG_RT2X00_LIB_PCI_MODULE)
  45 #include "rt2x00pci.h"
  46 #endif
  47 #include "rt2800lib.h"
  48 #include "rt2800.h"
  49 #include "rt2800usb.h"
  50
  51 MODULE_AUTHOR("Bartlomiej Zolnierkiewicz");
  52 MODULE_DESCRIPTION("rt2800 library");
  53 MODULE_LICENSE("GPL");
  54
  55 /*
  56  * Register access.
  57  * All access to the CSR registers will go through the methods
  58  * rt2800_register_read and rt2800_register_write.
  59  * BBP and RF register require indirect register access,
  60  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  61  * These indirect registers work with busy bits,
  62  * and we will try maximal REGISTER_BUSY_COUNT times to access
  63  * the register while taking a REGISTER_BUSY_DELAY us delay
  64  * between each attampt. When the busy bit is still set at that time,
  65  * the access attempt is considered to have failed,
  66  * and we will print an error.
  67  * The _lock versions must be used if you already hold the csr_mutex
  68  */
  69 #define WAIT_FOR_BBP(__dev, __reg) \
  70         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  71 #define WAIT_FOR_RFCSR(__dev, __reg) \
  72         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  73 #define WAIT_FOR_RF(__dev, __reg) \
  74         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  75 #define WAIT_FOR_MCU(__dev, __reg) \
  76         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  77                             H2M_MAILBOX_CSR_OWNER, (__reg))
  78
  79 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
  80                              const unsigned int word, const u8 value)
  81 {
  82         u32 reg;
  83
  84         mutex_lock(&rt2x00dev->csr_mutex);
  85
  86         /*
  87          * Wait until the BBP becomes available, afterwards we
  88          * can safely write the new data into the register.
  89          */
  90         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  91                 reg = 0;
  92                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
  93                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
  94                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
  95                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
  96                 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
  97                         rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
  98
  99                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 100         }
 101
 102         mutex_unlock(&rt2x00dev->csr_mutex);
 103 }
 104
 105 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
 106                             const unsigned int word, u8 *value)
 107 {
 108         u32 reg;
 109
 110         mutex_lock(&rt2x00dev->csr_mutex);
 111
 112         /*
 113          * Wait until the BBP becomes available, afterwards we
 114          * can safely write the read request into the register.
 115          * After the data has been written, we wait until hardware
 116          * returns the correct value, if at any time the register
 117          * doesn't become available in time, reg will be 0xffffffff
 118          * which means we return 0xff to the caller.
 119          */
 120         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 121                 reg = 0;
 122                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 123                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 124                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 125                 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
 126                         rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 127
 128                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 129
 130                 WAIT_FOR_BBP(rt2x00dev, &reg);
 131         }
 132
 133         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 134
 135         mutex_unlock(&rt2x00dev->csr_mutex);
 136 }
 137
 138 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 139                                const unsigned int word, const u8 value)
 140 {
 141         u32 reg;
 142
 143         mutex_lock(&rt2x00dev->csr_mutex);
 144
 145         /*
 146          * Wait until the RFCSR becomes available, afterwards we
 147          * can safely write the new data into the register.
 148          */
 149         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 150                 reg = 0;
 151                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 152                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 153                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 154                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 155
 156                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 157         }
 158
 159         mutex_unlock(&rt2x00dev->csr_mutex);
 160 }
 161
 162 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 163                               const unsigned int word, u8 *value)
 164 {
 165         u32 reg;
 166
 167         mutex_lock(&rt2x00dev->csr_mutex);
 168
 169         /*
 170          * Wait until the RFCSR becomes available, afterwards we
 171          * can safely write the read request into the register.
 172          * After the data has been written, we wait until hardware
 173          * returns the correct value, if at any time the register
 174          * doesn't become available in time, reg will be 0xffffffff
 175          * which means we return 0xff to the caller.
 176          */
 177         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 178                 reg = 0;
 179                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 180                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 181                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 182
 183                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 184
 185                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
 186         }
 187
 188         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 189
 190         mutex_unlock(&rt2x00dev->csr_mutex);
 191 }
 192
 193 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
 194                             const unsigned int word, const u32 value)
 195 {
 196         u32 reg;
 197
 198         mutex_lock(&rt2x00dev->csr_mutex);
 199
 200         /*
 201          * Wait until the RF becomes available, afterwards we
 202          * can safely write the new data into the register.
 203          */
 204         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 205                 reg = 0;
 206                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 207                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 208                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 209                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 210
 211                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 212                 rt2x00_rf_write(rt2x00dev, word, value);
 213         }
 214
 215         mutex_unlock(&rt2x00dev->csr_mutex);
 216 }
 217
 218 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
 219                         const u8 command, const u8 token,
 220                         const u8 arg0, const u8 arg1)
 221 {
 222         u32 reg;
 223
 224         /*
 225          * SOC devices don't support MCU requests.
 226          */
 227         if (rt2x00_is_soc(rt2x00dev))
 228                 return;
 229
 230         mutex_lock(&rt2x00dev->csr_mutex);
 231
 232         /*
 233          * Wait until the MCU becomes available, afterwards we
 234          * can safely write the new data into the register.
 235          */
 236         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 237                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 238                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 239                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 240                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 241                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 242
 243                 reg = 0;
 244                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 245                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 246         }
 247
 248         mutex_unlock(&rt2x00dev->csr_mutex);
 249 }
 250 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
 251
 252 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
 253 {
 254         unsigned int i;
 255         u32 reg;
 256
 257         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 258                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 259                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
 260                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
 261                         return 0;
 262
 263                 msleep(1);
 264         }
 265
 266         ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
 267         return -EACCES;
 268 }
 269 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
 270
 271 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 272 const struct rt2x00debug rt2800_rt2x00debug = {
 273         .owner  = THIS_MODULE,
 274         .csr    = {
 275                 .read           = rt2800_register_read,
 276                 .write          = rt2800_register_write,
 277                 .flags          = RT2X00DEBUGFS_OFFSET,
 278                 .word_base      = CSR_REG_BASE,
 279                 .word_size      = sizeof(u32),
 280                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 281         },
 282         .eeprom = {
 283                 .read           = rt2x00_eeprom_read,
 284                 .write          = rt2x00_eeprom_write,
 285                 .word_base      = EEPROM_BASE,
 286                 .word_size      = sizeof(u16),
 287                 .word_count     = EEPROM_SIZE / sizeof(u16),
 288         },
 289         .bbp    = {
 290                 .read           = rt2800_bbp_read,
 291                 .write          = rt2800_bbp_write,
 292                 .word_base      = BBP_BASE,
 293                 .word_size      = sizeof(u8),
 294                 .word_count     = BBP_SIZE / sizeof(u8),
 295         },
 296         .rf     = {
 297                 .read           = rt2x00_rf_read,
 298                 .write          = rt2800_rf_write,
 299                 .word_base      = RF_BASE,
 300                 .word_size      = sizeof(u32),
 301                 .word_count     = RF_SIZE / sizeof(u32),
 302         },
 303 };
 304 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
 305 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 306
 307 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 308 {
 309         u32 reg;
 310
 311         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
 312         return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
 313 }
 314 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
 315
 316 #ifdef CONFIG_RT2X00_LIB_LEDS
 317 static void rt2800_brightness_set(struct led_classdev *led_cdev,
 318                                   enum led_brightness brightness)
 319 {
 320         struct rt2x00_led *led =
 321             container_of(led_cdev, struct rt2x00_led, led_dev);
 322         unsigned int enabled = brightness != LED_OFF;
 323         unsigned int bg_mode =
 324             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 325         unsigned int polarity =
 326                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 327                                    EEPROM_FREQ_LED_POLARITY);
 328         unsigned int ledmode =
 329                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 330                                    EEPROM_FREQ_LED_MODE);
 331
 332         if (led->type == LED_TYPE_RADIO) {
 333                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 334                                       enabled ? 0x20 : 0);
 335         } else if (led->type == LED_TYPE_ASSOC) {
 336                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 337                                       enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
 338         } else if (led->type == LED_TYPE_QUALITY) {
 339                 /*
 340                  * The brightness is divided into 6 levels (0 - 5),
 341                  * The specs tell us the following levels:
 342                  *      0, 1 ,3, 7, 15, 31
 343                  * to determine the level in a simple way we can simply
 344                  * work with bitshifting:
 345                  *      (1 << level) - 1
 346                  */
 347                 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 348                                       (1 << brightness / (LED_FULL / 6)) - 1,
 349                                       polarity);
 350         }
 351 }
 352
 353 static int rt2800_blink_set(struct led_classdev *led_cdev,
 354                             unsigned long *delay_on, unsigned long *delay_off)
 355 {
 356         struct rt2x00_led *led =
 357             container_of(led_cdev, struct rt2x00_led, led_dev);
 358         u32 reg;
 359
 360         rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
 361         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
 362         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
 363         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
 364         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
 365         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
 366         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
 367         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
 368         rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
 369
 370         return 0;
 371 }
 372
 373 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
 374                      struct rt2x00_led *led, enum led_type type)
 375 {
 376         led->rt2x00dev = rt2x00dev;
 377         led->type = type;
 378         led->led_dev.brightness_set = rt2800_brightness_set;
 379         led->led_dev.blink_set = rt2800_blink_set;
 380         led->flags = LED_INITIALIZED;
 381 }
 382 #endif /* CONFIG_RT2X00_LIB_LEDS */
 383
 384 /*
 385  * Configuration handlers.
 386  */
 387 static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
 388                                     struct rt2x00lib_crypto *crypto,
 389                                     struct ieee80211_key_conf *key)
 390 {
 391         struct mac_wcid_entry wcid_entry;
 392         struct mac_iveiv_entry iveiv_entry;
 393         u32 offset;
 394         u32 reg;
 395
 396         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
 397
 398         rt2800_register_read(rt2x00dev, offset, &reg);
 399         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
 400                            !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
 401         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
 402                            (crypto->cmd == SET_KEY) * crypto->cipher);
 403         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
 404                            (crypto->cmd == SET_KEY) * crypto->bssidx);
 405         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
 406         rt2800_register_write(rt2x00dev, offset, reg);
 407
 408         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
 409
 410         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
 411         if ((crypto->cipher == CIPHER_TKIP) ||
 412             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
 413             (crypto->cipher == CIPHER_AES))
 414                 iveiv_entry.iv[3] |= 0x20;
 415         iveiv_entry.iv[3] |= key->keyidx << 6;
 416         rt2800_register_multiwrite(rt2x00dev, offset,
 417                                       &iveiv_entry, sizeof(iveiv_entry));
 418
 419         offset = MAC_WCID_ENTRY(key->hw_key_idx);
 420
 421         memset(&wcid_entry, 0, sizeof(wcid_entry));
 422         if (crypto->cmd == SET_KEY)
 423                 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
 424         rt2800_register_multiwrite(rt2x00dev, offset,
 425                                       &wcid_entry, sizeof(wcid_entry));
 426 }
 427
 428 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
 429                              struct rt2x00lib_crypto *crypto,
 430                              struct ieee80211_key_conf *key)
 431 {
 432         struct hw_key_entry key_entry;
 433         struct rt2x00_field32 field;
 434         u32 offset;
 435         u32 reg;
 436
 437         if (crypto->cmd == SET_KEY) {
 438                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
 439
 440                 memcpy(key_entry.key, crypto->key,
 441                        sizeof(key_entry.key));
 442                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 443                        sizeof(key_entry.tx_mic));
 444                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 445                        sizeof(key_entry.rx_mic));
 446
 447                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
 448                 rt2800_register_multiwrite(rt2x00dev, offset,
 449                                               &key_entry, sizeof(key_entry));
 450         }
 451
 452         /*
 453          * The cipher types are stored over multiple registers
 454          * starting with SHARED_KEY_MODE_BASE each word will have
 455          * 32 bits and contains the cipher types for 2 bssidx each.
 456          * Using the correct defines correctly will cause overhead,
 457          * so just calculate the correct offset.
 458          */
 459         field.bit_offset = 4 * (key->hw_key_idx % 8);
 460         field.bit_mask = 0x7 << field.bit_offset;
 461
 462         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
 463
 464         rt2800_register_read(rt2x00dev, offset, &reg);
 465         rt2x00_set_field32(&reg, field,
 466                            (crypto->cmd == SET_KEY) * crypto->cipher);
 467         rt2800_register_write(rt2x00dev, offset, reg);
 468
 469         /*
 470          * Update WCID information
 471          */
 472         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
 473
 474         return 0;
 475 }
 476 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
 477
 478 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
 479                                struct rt2x00lib_crypto *crypto,
 480                                struct ieee80211_key_conf *key)
 481 {
 482         struct hw_key_entry key_entry;
 483         u32 offset;
 484
 485         if (crypto->cmd == SET_KEY) {
 486                 /*
 487                  * 1 pairwise key is possible per AID, this means that the AID
 488                  * equals our hw_key_idx. Make sure the WCID starts _after_ the
 489                  * last possible shared key entry.
 490                  */
 491                 if (crypto->aid > (256 - 32))
 492                         return -ENOSPC;
 493
 494                 key->hw_key_idx = 32 + crypto->aid;
 495
 496                 memcpy(key_entry.key, crypto->key,
 497                        sizeof(key_entry.key));
 498                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 499                        sizeof(key_entry.tx_mic));
 500                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 501                        sizeof(key_entry.rx_mic));
 502
 503                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
 504                 rt2800_register_multiwrite(rt2x00dev, offset,
 505                                               &key_entry, sizeof(key_entry));
 506         }
 507
 508         /*
 509          * Update WCID information
 510          */
 511         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
 512
 513         return 0;
 514 }
 515 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
 516
 517 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
 518                           const unsigned int filter_flags)
 519 {
 520         u32 reg;
 521
 522         /*
 523          * Start configuration steps.
 524          * Note that the version error will always be dropped
 525          * and broadcast frames will always be accepted since
 526          * there is no filter for it at this time.
 527          */
 528         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
 529         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
 530                            !(filter_flags & FIF_FCSFAIL));
 531         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
 532                            !(filter_flags & FIF_PLCPFAIL));
 533         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
 534                            !(filter_flags & FIF_PROMISC_IN_BSS));
 535         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
 536         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
 537         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
 538                            !(filter_flags & FIF_ALLMULTI));
 539         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
 540         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
 541         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
 542                            !(filter_flags & FIF_CONTROL));
 543         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
 544                            !(filter_flags & FIF_CONTROL));
 545         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
 546                            !(filter_flags & FIF_CONTROL));
 547         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
 548                            !(filter_flags & FIF_CONTROL));
 549         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
 550                            !(filter_flags & FIF_CONTROL));
 551         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
 552                            !(filter_flags & FIF_PSPOLL));
 553         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
 554         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
 555         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
 556                            !(filter_flags & FIF_CONTROL));
 557         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
 558 }
 559 EXPORT_SYMBOL_GPL(rt2800_config_filter);
 560
 561 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
 562                         struct rt2x00intf_conf *conf, const unsigned int flags)
 563 {
 564         unsigned int beacon_base;
 565         u32 reg;
 566
 567         if (flags & CONFIG_UPDATE_TYPE) {
 568                 /*
 569                  * Clear current synchronisation setup.
 570                  * For the Beacon base registers we only need to clear
 571                  * the first byte since that byte contains the VALID and OWNER
 572                  * bits which (when set to 0) will invalidate the entire beacon.
 573                  */
 574                 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
 575                 rt2800_register_write(rt2x00dev, beacon_base, 0);
 576
 577                 /*
 578                  * Enable synchronisation.
 579                  */
 580                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 581                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
 582                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
 583                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE,
 584                                    (conf->sync == TSF_SYNC_BEACON));
 585                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 586         }
 587
 588         if (flags & CONFIG_UPDATE_MAC) {
 589                 reg = le32_to_cpu(conf->mac[1]);
 590                 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
 591                 conf->mac[1] = cpu_to_le32(reg);
 592
 593                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
 594                                               conf->mac, sizeof(conf->mac));
 595         }
 596
 597         if (flags & CONFIG_UPDATE_BSSID) {
 598                 reg = le32_to_cpu(conf->bssid[1]);
 599                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
 600                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
 601                 conf->bssid[1] = cpu_to_le32(reg);
 602
 603                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
 604                                               conf->bssid, sizeof(conf->bssid));
 605         }
 606 }
 607 EXPORT_SYMBOL_GPL(rt2800_config_intf);
 608
 609 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp)
 610 {
 611         u32 reg;
 612
 613         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
 614         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 0x20);
 615         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
 616
 617         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
 618         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
 619                            !!erp->short_preamble);
 620         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
 621                            !!erp->short_preamble);
 622         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
 623
 624         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
 625         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
 626                            erp->cts_protection ? 2 : 0);
 627         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
 628
 629         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
 630                                  erp->basic_rates);
 631         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
 632
 633         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
 634         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
 635         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
 636         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
 637
 638         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
 639         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
 640         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
 641         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
 642         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
 643         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
 644         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
 645
 646         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 647         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
 648                            erp->beacon_int * 16);
 649         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 650 }
 651 EXPORT_SYMBOL_GPL(rt2800_config_erp);
 652
 653 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
 654 {
 655         u8 r1;
 656         u8 r3;
 657
 658         rt2800_bbp_read(rt2x00dev, 1, &r1);
 659         rt2800_bbp_read(rt2x00dev, 3, &r3);
 660
 661         /*
 662          * Configure the TX antenna.
 663          */
 664         switch ((int)ant->tx) {
 665         case 1:
 666                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
 667                 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
 668                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
 669                 break;
 670         case 2:
 671                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
 672                 break;
 673         case 3:
 674                 /* Do nothing */
 675                 break;
 676         }
 677
 678         /*
 679          * Configure the RX antenna.
 680          */
 681         switch ((int)ant->rx) {
 682         case 1:
 683                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
 684                 break;
 685         case 2:
 686                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
 687                 break;
 688         case 3:
 689                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
 690                 break;
 691         }
 692
 693         rt2800_bbp_write(rt2x00dev, 3, r3);
 694         rt2800_bbp_write(rt2x00dev, 1, r1);
 695 }
 696 EXPORT_SYMBOL_GPL(rt2800_config_ant);
 697
 698 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
 699                                    struct rt2x00lib_conf *libconf)
 700 {
 701         u16 eeprom;
 702         short lna_gain;
 703
 704         if (libconf->rf.channel <= 14) {
 705                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 706                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
 707         } else if (libconf->rf.channel <= 64) {
 708                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 709                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
 710         } else if (libconf->rf.channel <= 128) {
 711                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 712                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
 713         } else {
 714                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 715                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
 716         }
 717
 718         rt2x00dev->lna_gain = lna_gain;
 719 }
 720
 721 static void rt2800_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
 722                                        struct ieee80211_conf *conf,
 723                                        struct rf_channel *rf,
 724                                        struct channel_info *info)
 725 {
 726         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 727
 728         if (rt2x00dev->default_ant.tx == 1)
 729                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
 730
 731         if (rt2x00dev->default_ant.rx == 1) {
 732                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
 733                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 734         } else if (rt2x00dev->default_ant.rx == 2)
 735                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 736
 737         if (rf->channel > 14) {
 738                 /*
 739                  * When TX power is below 0, we should increase it by 7 to
 740                  * make it a positive value (Minumum value is -7).
 741                  * However this means that values between 0 and 7 have
 742                  * double meaning, and we should set a 7DBm boost flag.
 743                  */
 744                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
 745                                    (info->tx_power1 >= 0));
 746
 747                 if (info->tx_power1 < 0)
 748                         info->tx_power1 += 7;
 749
 750                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
 751                                    TXPOWER_A_TO_DEV(info->tx_power1));
 752
 753                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
 754                                    (info->tx_power2 >= 0));
 755
 756                 if (info->tx_power2 < 0)
 757                         info->tx_power2 += 7;
 758
 759                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
 760                                    TXPOWER_A_TO_DEV(info->tx_power2));
 761         } else {
 762                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
 763                                    TXPOWER_G_TO_DEV(info->tx_power1));
 764                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
 765                                    TXPOWER_G_TO_DEV(info->tx_power2));
 766         }
 767
 768         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
 769
 770         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
 771         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
 772         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 773         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
 774
 775         udelay(200);
 776
 777         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
 778         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
 779         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 780         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
 781
 782         udelay(200);
 783
 784         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
 785         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
 786         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 787         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
 788 }
 789
 790 static void rt2800_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
 791                                        struct ieee80211_conf *conf,
 792                                        struct rf_channel *rf,
 793                                        struct channel_info *info)
 794 {
 795         u8 rfcsr;
 796
 797         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
 798         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
 799
 800         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
 801         rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2);
 802         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
 803
 804         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
 805         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
 806                           TXPOWER_G_TO_DEV(info->tx_power1));
 807         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
 808
 809         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
 810         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
 811         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
 812
 813         rt2800_rfcsr_write(rt2x00dev, 24,
 814                               rt2x00dev->calibration[conf_is_ht40(conf)]);
 815
 816         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
 817         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
 818         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
 819 }
 820
 821 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
 822                                   struct ieee80211_conf *conf,
 823                                   struct rf_channel *rf,
 824                                   struct channel_info *info)
 825 {
 826         u32 reg;
 827         unsigned int tx_pin;
 828         u8 bbp;
 829
 830         if ((rt2x00_rt(rt2x00dev, RT3070) ||
 831              rt2x00_rt(rt2x00dev, RT3090)) &&
 832             (rt2x00_rf(rt2x00dev, RF2020) ||
 833              rt2x00_rf(rt2x00dev, RF3020) ||
 834              rt2x00_rf(rt2x00dev, RF3021) ||
 835              rt2x00_rf(rt2x00dev, RF3022)))
 836                 rt2800_config_channel_rt3x(rt2x00dev, conf, rf, info);
 837         else
 838                 rt2800_config_channel_rt2x(rt2x00dev, conf, rf, info);
 839
 840         /*
 841          * Change BBP settings
 842          */
 843         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
 844         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
 845         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
 846         rt2800_bbp_write(rt2x00dev, 86, 0);
 847
 848         if (rf->channel <= 14) {
 849                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
 850                         rt2800_bbp_write(rt2x00dev, 82, 0x62);
 851                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
 852                 } else {
 853                         rt2800_bbp_write(rt2x00dev, 82, 0x84);
 854                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
 855                 }
 856         } else {
 857                 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
 858
 859                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
 860                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
 861                 else
 862                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
 863         }
 864
 865         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
 866         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
 867         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
 868         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
 869         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
 870
 871         tx_pin = 0;
 872
 873         /* Turn on unused PA or LNA when not using 1T or 1R */
 874         if (rt2x00dev->default_ant.tx != 1) {
 875                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
 876                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
 877         }
 878
 879         /* Turn on unused PA or LNA when not using 1T or 1R */
 880         if (rt2x00dev->default_ant.rx != 1) {
 881                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
 882                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
 883         }
 884
 885         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
 886         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
 887         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
 888         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
 889         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
 890         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
 891
 892         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
 893
 894         rt2800_bbp_read(rt2x00dev, 4, &bbp);
 895         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
 896         rt2800_bbp_write(rt2x00dev, 4, bbp);
 897
 898         rt2800_bbp_read(rt2x00dev, 3, &bbp);
 899         rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
 900         rt2800_bbp_write(rt2x00dev, 3, bbp);
 901
 902         if (rt2x00_rt(rt2x00dev, RT2860) &&
 903             (rt2x00_rev(rt2x00dev) == RT2860C_VERSION)) {
 904                 if (conf_is_ht40(conf)) {
 905                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
 906                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
 907                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
 908                 } else {
 909                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
 910                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
 911                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
 912                 }
 913         }
 914
 915         msleep(1);
 916 }
 917
 918 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
 919                                   const int txpower)
 920 {
 921         u32 reg;
 922         u32 value = TXPOWER_G_TO_DEV(txpower);
 923         u8 r1;
 924
 925         rt2800_bbp_read(rt2x00dev, 1, &r1);
 926         rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
 927         rt2800_bbp_write(rt2x00dev, 1, r1);
 928
 929         rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
 930         rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
 931         rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
 932         rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
 933         rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
 934         rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
 935         rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
 936         rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
 937         rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
 938         rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
 939
 940         rt2800_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
 941         rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
 942         rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
 943         rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
 944         rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
 945         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
 946         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
 947         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
 948         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
 949         rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
 950
 951         rt2800_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
 952         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
 953         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
 954         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
 955         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
 956         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
 957         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
 958         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
 959         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
 960         rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
 961
 962         rt2800_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
 963         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
 964         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
 965         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
 966         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
 967         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
 968         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
 969         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
 970         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
 971         rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
 972
 973         rt2800_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
 974         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
 975         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
 976         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
 977         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
 978         rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
 979 }
 980
 981 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 982                                       struct rt2x00lib_conf *libconf)
 983 {
 984         u32 reg;
 985
 986         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
 987         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
 988                            libconf->conf->short_frame_max_tx_count);
 989         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
 990                            libconf->conf->long_frame_max_tx_count);
 991         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
 992         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
 993         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
 994         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
 995         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
 996 }
 997
 998 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
 999                              struct rt2x00lib_conf *libconf)
1000 {
1001         enum dev_state state =
1002             (libconf->conf->flags & IEEE80211_CONF_PS) ?
1003                 STATE_SLEEP : STATE_AWAKE;
1004         u32 reg;
1005
1006         if (state == STATE_SLEEP) {
1007                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1008
1009                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1010                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1011                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1012                                    libconf->conf->listen_interval - 1);
1013                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1014                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1015
1016                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1017         } else {
1018                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1019
1020                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1021                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1022                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1023                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1024                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1025         }
1026 }
1027
1028 void rt2800_config(struct rt2x00_dev *rt2x00dev,
1029                    struct rt2x00lib_conf *libconf,
1030                    const unsigned int flags)
1031 {
1032         /* Always recalculate LNA gain before changing configuration */
1033         rt2800_config_lna_gain(rt2x00dev, libconf);
1034
1035         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1036                 rt2800_config_channel(rt2x00dev, libconf->conf,
1037                                       &libconf->rf, &libconf->channel);
1038         if (flags & IEEE80211_CONF_CHANGE_POWER)
1039                 rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
1040         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1041                 rt2800_config_retry_limit(rt2x00dev, libconf);
1042         if (flags & IEEE80211_CONF_CHANGE_PS)
1043                 rt2800_config_ps(rt2x00dev, libconf);
1044 }
1045 EXPORT_SYMBOL_GPL(rt2800_config);
1046
1047 /*
1048  * Link tuning
1049  */
1050 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1051 {
1052         u32 reg;
1053
1054         /*
1055          * Update FCS error count from register.
1056          */
1057         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1058         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1059 }
1060 EXPORT_SYMBOL_GPL(rt2800_link_stats);
1061
1062 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1063 {
1064         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1065                 if (rt2x00_is_usb(rt2x00dev) &&
1066                     rt2x00_rt(rt2x00dev, RT3070) &&
1067                     (rt2x00_rev(rt2x00dev) == RT3070_VERSION))
1068                         return 0x1c + (2 * rt2x00dev->lna_gain);
1069                 else
1070                         return 0x2e + rt2x00dev->lna_gain;
1071         }
1072
1073         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1074                 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1075         else
1076                 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1077 }
1078
1079 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
1080                                   struct link_qual *qual, u8 vgc_level)
1081 {
1082         if (qual->vgc_level != vgc_level) {
1083                 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1084                 qual->vgc_level = vgc_level;
1085                 qual->vgc_level_reg = vgc_level;
1086         }
1087 }
1088
1089 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1090 {
1091         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
1092 }
1093 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
1094
1095 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
1096                        const u32 count)
1097 {
1098         if (rt2x00_rt(rt2x00dev, RT2860) &&
1099             (rt2x00_rev(rt2x00dev) == RT2860C_VERSION))
1100                 return;
1101
1102         /*
1103          * When RSSI is better then -80 increase VGC level with 0x10
1104          */
1105         rt2800_set_vgc(rt2x00dev, qual,
1106                        rt2800_get_default_vgc(rt2x00dev) +
1107                        ((qual->rssi > -80) * 0x10));
1108 }
1109 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
1110
1111 /*
1112  * Initialization functions.
1113  */
1114 int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1115 {
1116         u32 reg;
1117         unsigned int i;
1118
1119         if (rt2x00_is_usb(rt2x00dev)) {
1120                 /*
1121                  * Wait until BBP and RF are ready.
1122                  */
1123                 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1124                         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1125                         if (reg && reg != ~0)
1126                                 break;
1127                         msleep(1);
1128                 }
1129
1130                 if (i == REGISTER_BUSY_COUNT) {
1131                         ERROR(rt2x00dev, "Unstable hardware.\n");
1132                         return -EBUSY;
1133                 }
1134
1135                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1136                 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL,
1137                                       reg & ~0x00002000);
1138         } else if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
1139                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1140
1141         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1142         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1143         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1144         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1145
1146         if (rt2x00_is_usb(rt2x00dev)) {
1147                 rt2800_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
1148 #if defined(CONFIG_RT2X00_LIB_USB) || defined(CONFIG_RT2X00_LIB_USB_MODULE)
1149                 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
1150                                             USB_MODE_RESET, REGISTER_TIMEOUT);
1151 #endif
1152         }
1153
1154         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1155
1156         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1157         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1158         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1159         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1160         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1161         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1162
1163         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1164         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1165         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1166         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1167         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1168         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1169
1170         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1171         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1172
1173         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1174
1175         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1176         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1177         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1178         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1179         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1180         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1181         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1182         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1183
1184         if (rt2x00_is_usb(rt2x00dev) &&
1185             rt2x00_rt(rt2x00dev, RT3070) &&
1186             (rt2x00_rev(rt2x00dev) == RT3070_VERSION)) {
1187                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1188                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1189                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1190         } else {
1191                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1192                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1193         }
1194
1195         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1196         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1197         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1198         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1199         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1200         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1201         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1202         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1203         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1204         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1205
1206         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1207         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1208         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1209         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1210
1211         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1212         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1213         if ((rt2x00_rt(rt2x00dev, RT2872) &&
1214              (rt2x00_rev(rt2x00dev) >= RT2880E_VERSION)) ||
1215             rt2x00_rt(rt2x00dev, RT2880) ||
1216             rt2x00_rt(rt2x00dev, RT2883) ||
1217             rt2x00_rt(rt2x00dev, RT2890) ||
1218             rt2x00_rt(rt2x00dev, RT3052) ||
1219             (rt2x00_rt(rt2x00dev, RT3070) &&
1220              (rt2x00_rev(rt2x00dev) < RT3070_VERSION)))
1221                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1222         else
1223                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1224         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1225         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1226         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1227
1228         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1229
1230         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1231         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1232         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1233         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1234         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1235         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1236         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1237
1238         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1239         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
1240         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1241         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1242         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1243         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1244         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1245         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1246         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1247         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1248         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1249
1250         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1251         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
1252         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1253         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1254         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1255         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1256         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1257         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1258         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1259         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1260         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1261
1262         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1263         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1264         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1265         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1266         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1267         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1268         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1269         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1270         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1271         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1272         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1273
1274         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1275         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1276         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1277         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1278         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1279         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1280         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1281         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1282         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1283         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1284         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1285
1286         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1287         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1288         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1289         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1290         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1291         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1292         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1293         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1294         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1295         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1296         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1297
1298         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1299         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1300         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1301         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1302         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1303         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1304         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1305         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1306         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1307         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1308         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1309
1310         if (rt2x00_is_usb(rt2x00dev)) {
1311                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1312
1313                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1314                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1315                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1316                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1317                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1318                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1319                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1320                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1321                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1322                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1323                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1324         }
1325
1326         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1327         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1328
1329         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1330         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1331         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1332                            IEEE80211_MAX_RTS_THRESHOLD);
1333         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1334         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1335
1336         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1337         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1338
1339         /*
1340          * ASIC will keep garbage value after boot, clear encryption keys.
1341          */
1342         for (i = 0; i < 4; i++)
1343                 rt2800_register_write(rt2x00dev,
1344                                          SHARED_KEY_MODE_ENTRY(i), 0);
1345
1346         for (i = 0; i < 256; i++) {
1347                 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1348                 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1349                                               wcid, sizeof(wcid));
1350
1351                 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1352                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1353         }
1354
1355         /*
1356          * Clear all beacons
1357          * For the Beacon base registers we only need to clear
1358          * the first byte since that byte contains the VALID and OWNER
1359          * bits which (when set to 0) will invalidate the entire beacon.
1360          */
1361         rt2800_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1362         rt2800_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1363         rt2800_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1364         rt2800_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1365         rt2800_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1366         rt2800_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1367         rt2800_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1368         rt2800_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1369
1370         if (rt2x00_is_usb(rt2x00dev)) {
1371                 rt2800_register_read(rt2x00dev, USB_CYC_CFG, &reg);
1372                 rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
1373                 rt2800_register_write(rt2x00dev, USB_CYC_CFG, reg);
1374         }
1375
1376         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1377         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1378         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1379         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1380         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1381         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1382         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1383         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1384         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1385         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1386
1387         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1388         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1389         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1390         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1391         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1392         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1393         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1394         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1395         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1396         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1397
1398         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1399         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1400         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1401         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
1402         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1403         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1404         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1405         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1406         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1407         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1408
1409         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1410         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1411         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1412         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1413         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1414         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1415
1416         /*
1417          * We must clear the error counters.
1418          * These registers are cleared on read,
1419          * so we may pass a useless variable to store the value.
1420          */
1421         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1422         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1423         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1424         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1425         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1426         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1427
1428         return 0;
1429 }
1430 EXPORT_SYMBOL_GPL(rt2800_init_registers);
1431
1432 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1433 {
1434         unsigned int i;
1435         u32 reg;
1436
1437         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1438                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1439                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1440                         return 0;
1441
1442                 udelay(REGISTER_BUSY_DELAY);
1443         }
1444
1445         ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1446         return -EACCES;
1447 }
1448
1449 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1450 {
1451         unsigned int i;
1452         u8 value;
1453
1454         /*
1455          * BBP was enabled after firmware was loaded,
1456          * but we need to reactivate it now.
1457          */
1458         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1459         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1460         msleep(1);
1461
1462         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1463                 rt2800_bbp_read(rt2x00dev, 0, &value);
1464                 if ((value != 0xff) && (value != 0x00))
1465                         return 0;
1466                 udelay(REGISTER_BUSY_DELAY);
1467         }
1468
1469         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1470         return -EACCES;
1471 }
1472
1473 int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
1474 {
1475         unsigned int i;
1476         u16 eeprom;
1477         u8 reg_id;
1478         u8 value;
1479
1480         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
1481                      rt2800_wait_bbp_ready(rt2x00dev)))
1482                 return -EACCES;
1483
1484         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
1485         rt2800_bbp_write(rt2x00dev, 66, 0x38);
1486         rt2800_bbp_write(rt2x00dev, 69, 0x12);
1487         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1488         rt2800_bbp_write(rt2x00dev, 73, 0x10);
1489         rt2800_bbp_write(rt2x00dev, 81, 0x37);
1490         rt2800_bbp_write(rt2x00dev, 82, 0x62);
1491         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
1492         rt2800_bbp_write(rt2x00dev, 84, 0x99);
1493         rt2800_bbp_write(rt2x00dev, 86, 0x00);
1494         rt2800_bbp_write(rt2x00dev, 91, 0x04);
1495         rt2800_bbp_write(rt2x00dev, 92, 0x00);
1496         rt2800_bbp_write(rt2x00dev, 103, 0x00);
1497         rt2800_bbp_write(rt2x00dev, 105, 0x05);
1498
1499         if (rt2x00_rt(rt2x00dev, RT2860) &&
1500             (rt2x00_rev(rt2x00dev) == RT2860C_VERSION)) {
1501                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1502                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
1503         }
1504
1505         if (rt2x00_rt(rt2x00dev, RT2860) &&
1506             (rt2x00_rev(rt2x00dev) > RT2860D_VERSION))
1507                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
1508
1509         if (rt2x00_is_usb(rt2x00dev) &&
1510             rt2x00_rt(rt2x00dev, RT3070) &&
1511             (rt2x00_rev(rt2x00dev) == RT3070_VERSION)) {
1512                 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1513                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
1514                 rt2800_bbp_write(rt2x00dev, 105, 0x05);
1515         }
1516
1517         if (rt2x00_rt(rt2x00dev, RT3052)) {
1518                 rt2800_bbp_write(rt2x00dev, 31, 0x08);
1519                 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
1520                 rt2800_bbp_write(rt2x00dev, 80, 0x08);
1521         }
1522
1523         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1524                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1525
1526                 if (eeprom != 0xffff && eeprom != 0x0000) {
1527                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1528                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1529                         rt2800_bbp_write(rt2x00dev, reg_id, value);
1530                 }
1531         }
1532
1533         return 0;
1534 }
1535 EXPORT_SYMBOL_GPL(rt2800_init_bbp);
1536
1537 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1538                                 bool bw40, u8 rfcsr24, u8 filter_target)
1539 {
1540         unsigned int i;
1541         u8 bbp;
1542         u8 rfcsr;
1543         u8 passband;
1544         u8 stopband;
1545         u8 overtuned = 0;
1546
1547         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1548
1549         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1550         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1551         rt2800_bbp_write(rt2x00dev, 4, bbp);
1552
1553         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1554         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1555         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1556
1557         /*
1558          * Set power & frequency of passband test tone
1559          */
1560         rt2800_bbp_write(rt2x00dev, 24, 0);
1561
1562         for (i = 0; i < 100; i++) {
1563                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1564                 msleep(1);
1565
1566                 rt2800_bbp_read(rt2x00dev, 55, &passband);
1567                 if (passband)
1568                         break;
1569         }
1570
1571         /*
1572          * Set power & frequency of stopband test tone
1573          */
1574         rt2800_bbp_write(rt2x00dev, 24, 0x06);
1575
1576         for (i = 0; i < 100; i++) {
1577                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1578                 msleep(1);
1579
1580                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
1581
1582                 if ((passband - stopband) <= filter_target) {
1583                         rfcsr24++;
1584                         overtuned += ((passband - stopband) == filter_target);
1585                 } else
1586                         break;
1587
1588                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1589         }
1590
1591         rfcsr24 -= !!overtuned;
1592
1593         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1594         return rfcsr24;
1595 }
1596
1597 int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1598 {
1599         u8 rfcsr;
1600         u8 bbp;
1601
1602         if (rt2x00_is_usb(rt2x00dev) &&
1603             rt2x00_rt(rt2x00dev, RT3070) &&
1604             (rt2x00_rev(rt2x00dev) != RT3070_VERSION))
1605                 return 0;
1606
1607         if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev)) {
1608                 if (!rt2x00_rf(rt2x00dev, RF3020) &&
1609                     !rt2x00_rf(rt2x00dev, RF3021) &&
1610                     !rt2x00_rf(rt2x00dev, RF3022))
1611                         return 0;
1612         }
1613
1614         /*
1615          * Init RF calibration.
1616          */
1617         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1618         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1619         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1620         msleep(1);
1621         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1622         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1623
1624         if (rt2x00_is_usb(rt2x00dev)) {
1625                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1626                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1627                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1628                 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
1629                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1630                 rt2800_rfcsr_write(rt2x00dev, 10, 0x71);
1631                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1632                 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
1633                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1634                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1635                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1636                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1637                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1638                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1639                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1640                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1641                 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
1642                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1643                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
1644                 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
1645         } else if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev)) {
1646                 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
1647                 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
1648                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
1649                 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
1650                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1651                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1652                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1653                 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
1654                 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
1655                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1656                 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
1657                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1658                 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
1659                 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
1660                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1661                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1662                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1663                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1664                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1665                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1666                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1667                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1668                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
1669                 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
1670                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
1671                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1672                 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
1673                 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
1674                 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
1675                 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
1676         }
1677
1678         /*
1679          * Set RX Filter calibration for 20MHz and 40MHz
1680          */
1681         rt2x00dev->calibration[0] =
1682             rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1683         rt2x00dev->calibration[1] =
1684             rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1685
1686         /*
1687          * Set back to initial state
1688          */
1689         rt2800_bbp_write(rt2x00dev, 24, 0);
1690
1691         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1692         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1693         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1694
1695         /*
1696          * set BBP back to BW20
1697          */
1698         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1699         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1700         rt2800_bbp_write(rt2x00dev, 4, bbp);
1701
1702         return 0;
1703 }
1704 EXPORT_SYMBOL_GPL(rt2800_init_rfcsr);
1705
1706 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
1707 {
1708         u32 reg;
1709
1710         rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
1711
1712         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
1713 }
1714 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
1715
1716 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
1717 {
1718         u32 reg;
1719
1720         mutex_lock(&rt2x00dev->csr_mutex);
1721
1722         rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
1723         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
1724         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
1725         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
1726         rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
1727
1728         /* Wait until the EEPROM has been loaded */
1729         rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
1730
1731         /* Apparently the data is read from end to start */
1732         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
1733                                         (u32 *)&rt2x00dev->eeprom[i]);
1734         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
1735                                         (u32 *)&rt2x00dev->eeprom[i + 2]);
1736         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
1737                                         (u32 *)&rt2x00dev->eeprom[i + 4]);
1738         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
1739                                         (u32 *)&rt2x00dev->eeprom[i + 6]);
1740
1741         mutex_unlock(&rt2x00dev->csr_mutex);
1742 }
1743
1744 void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
1745 {
1746         unsigned int i;
1747
1748         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
1749                 rt2800_efuse_read(rt2x00dev, i);
1750 }
1751 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
1752
1753 int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1754 {
1755         u16 word;
1756         u8 *mac;
1757         u8 default_lna_gain;
1758
1759         /*
1760          * Start validation of the data that has been read.
1761          */
1762         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1763         if (!is_valid_ether_addr(mac)) {
1764                 random_ether_addr(mac);
1765                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1766         }
1767
1768         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1769         if (word == 0xffff) {
1770                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
1771                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
1772                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
1773                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1774                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1775         } else if (rt2x00_rt(rt2x00dev, RT2860) ||
1776                    rt2x00_rt(rt2x00dev, RT2870) ||
1777                    rt2x00_rt(rt2x00dev, RT2872) ||
1778                    rt2x00_rt(rt2x00dev, RT2880) ||
1779                    (rt2x00_rt(rt2x00dev, RT2883) &&
1780                     (rt2x00_rev(rt2x00dev) < RT2883_VERSION))) {
1781                 /*
1782                  * There is a max of 2 RX streams for RT28x0 series
1783                  */
1784                 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
1785                         rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
1786                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1787         }
1788
1789         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1790         if (word == 0xffff) {
1791                 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
1792                 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
1793                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
1794                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
1795                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1796                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
1797                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
1798                 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
1799                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
1800                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
1801                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1802                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1803         }
1804
1805         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1806         if ((word & 0x00ff) == 0x00ff) {
1807                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1808                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
1809                                    LED_MODE_TXRX_ACTIVITY);
1810                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
1811                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1812                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
1813                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
1814                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
1815                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1816         }
1817
1818         /*
1819          * During the LNA validation we are going to use
1820          * lna0 as correct value. Note that EEPROM_LNA
1821          * is never validated.
1822          */
1823         rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
1824         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
1825
1826         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
1827         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
1828                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
1829         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
1830                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
1831         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
1832
1833         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
1834         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
1835                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
1836         if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
1837             rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
1838                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
1839                                    default_lna_gain);
1840         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
1841
1842         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
1843         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
1844                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
1845         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
1846                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
1847         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
1848
1849         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
1850         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
1851                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
1852         if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
1853             rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
1854                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
1855                                    default_lna_gain);
1856         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
1857
1858         return 0;
1859 }
1860 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
1861
1862 int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
1863 {
1864         u32 reg;
1865         u16 value;
1866         u16 eeprom;
1867
1868         /*
1869          * Read EEPROM word for configuration.
1870          */
1871         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1872
1873         /*
1874          * Identify RF chipset.
1875          */
1876         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1877         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1878
1879         rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
1880                         value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
1881
1882         if (!rt2x00_rt(rt2x00dev, RT2860) &&
1883             !rt2x00_rt(rt2x00dev, RT2870) &&
1884             !rt2x00_rt(rt2x00dev, RT2872) &&
1885             !rt2x00_rt(rt2x00dev, RT2880) &&
1886             !rt2x00_rt(rt2x00dev, RT2883) &&
1887             !rt2x00_rt(rt2x00dev, RT2890) &&
1888             !rt2x00_rt(rt2x00dev, RT3052) &&
1889             !rt2x00_rt(rt2x00dev, RT3070) &&
1890             !rt2x00_rt(rt2x00dev, RT3071) &&
1891             !rt2x00_rt(rt2x00dev, RT3090) &&
1892             !rt2x00_rt(rt2x00dev, RT3390) &&
1893             !rt2x00_rt(rt2x00dev, RT3572)) {
1894                 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1895                 return -ENODEV;
1896         }
1897
1898         if (!rt2x00_rf(rt2x00dev, RF2820) &&
1899             !rt2x00_rf(rt2x00dev, RF2850) &&
1900             !rt2x00_rf(rt2x00dev, RF2720) &&
1901             !rt2x00_rf(rt2x00dev, RF2750) &&
1902             !rt2x00_rf(rt2x00dev, RF3020) &&
1903             !rt2x00_rf(rt2x00dev, RF2020) &&
1904             !rt2x00_rf(rt2x00dev, RF3021) &&
1905             !rt2x00_rf(rt2x00dev, RF3022) &&
1906             !rt2x00_rf(rt2x00dev, RF3052)) {
1907                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1908                 return -ENODEV;
1909         }
1910
1911         /*
1912          * Identify default antenna configuration.
1913          */
1914         rt2x00dev->default_ant.tx =
1915             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
1916         rt2x00dev->default_ant.rx =
1917             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
1918
1919         /*
1920          * Read frequency offset and RF programming sequence.
1921          */
1922         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1923         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1924
1925         /*
1926          * Read external LNA informations.
1927          */
1928         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1929
1930         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
1931                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1932         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
1933                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1934
1935         /*
1936          * Detect if this device has an hardware controlled radio.
1937          */
1938         if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
1939                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1940
1941         /*
1942          * Store led settings, for correct led behaviour.
1943          */
1944 #ifdef CONFIG_RT2X00_LIB_LEDS
1945         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1946         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
1947         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
1948
1949         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
1950 #endif /* CONFIG_RT2X00_LIB_LEDS */
1951
1952         return 0;
1953 }
1954 EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
1955
1956 /*
1957  * RF value list for rt28x0
1958  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
1959  */
1960 static const struct rf_channel rf_vals[] = {
1961         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
1962         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
1963         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
1964         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
1965         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
1966         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
1967         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
1968         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
1969         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
1970         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
1971         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
1972         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
1973         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
1974         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
1975
1976         /* 802.11 UNI / HyperLan 2 */
1977         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
1978         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
1979         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
1980         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
1981         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
1982         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
1983         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
1984         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
1985         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
1986         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
1987         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
1988         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
1989
1990         /* 802.11 HyperLan 2 */
1991         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
1992         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
1993         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
1994         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
1995         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
1996         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
1997         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
1998         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
1999         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2000         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2001         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2002         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2003         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2004         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2005         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2006         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2007
2008         /* 802.11 UNII */
2009         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2010         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2011         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2012         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2013         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2014         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2015         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2016         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
2017         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
2018         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
2019         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
2020
2021         /* 802.11 Japan */
2022         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2023         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2024         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2025         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2026         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2027         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2028         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2029 };
2030
2031 /*
2032  * RF value list for rt3070
2033  * Supports: 2.4 GHz
2034  */
2035 static const struct rf_channel rf_vals_302x[] = {
2036         {1,  241, 2, 2 },
2037         {2,  241, 2, 7 },
2038         {3,  242, 2, 2 },
2039         {4,  242, 2, 7 },
2040         {5,  243, 2, 2 },
2041         {6,  243, 2, 7 },
2042         {7,  244, 2, 2 },
2043         {8,  244, 2, 7 },
2044         {9,  245, 2, 2 },
2045         {10, 245, 2, 7 },
2046         {11, 246, 2, 2 },
2047         {12, 246, 2, 7 },
2048         {13, 247, 2, 2 },
2049         {14, 248, 2, 4 },
2050 };
2051
2052 int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2053 {
2054         struct hw_mode_spec *spec = &rt2x00dev->spec;
2055         struct channel_info *info;
2056         char *tx_power1;
2057         char *tx_power2;
2058         unsigned int i;
2059         u16 eeprom;
2060
2061         /*
2062          * Disable powersaving as default on PCI devices.
2063          */
2064         if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
2065                 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2066
2067         /*
2068          * Initialize all hw fields.
2069          */
2070         rt2x00dev->hw->flags =
2071             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2072             IEEE80211_HW_SIGNAL_DBM |
2073             IEEE80211_HW_SUPPORTS_PS |
2074             IEEE80211_HW_PS_NULLFUNC_STACK;
2075
2076         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2077         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2078                                 rt2x00_eeprom_addr(rt2x00dev,
2079                                                    EEPROM_MAC_ADDR_0));
2080
2081         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2082
2083         /*
2084          * Initialize hw_mode information.
2085          */
2086         spec->supported_bands = SUPPORT_BAND_2GHZ;
2087         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2088
2089         if (rt2x00_rf(rt2x00dev, RF2820) ||
2090             rt2x00_rf(rt2x00dev, RF2720) ||
2091             rt2x00_rf(rt2x00dev, RF3052)) {
2092                 spec->num_channels = 14;
2093                 spec->channels = rf_vals;
2094         } else if (rt2x00_rf(rt2x00dev, RF2850) || rt2x00_rf(rt2x00dev, RF2750)) {
2095                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2096                 spec->num_channels = ARRAY_SIZE(rf_vals);
2097                 spec->channels = rf_vals;
2098         } else if (rt2x00_rf(rt2x00dev, RF3020) ||
2099                    rt2x00_rf(rt2x00dev, RF2020) ||
2100                    rt2x00_rf(rt2x00dev, RF3021) ||
2101                    rt2x00_rf(rt2x00dev, RF3022)) {
2102                 spec->num_channels = ARRAY_SIZE(rf_vals_302x);
2103                 spec->channels = rf_vals_302x;
2104         }
2105
2106         /*
2107          * Initialize HT information.
2108          */
2109         if (!rt2x00_rf(rt2x00dev, RF2020))
2110                 spec->ht.ht_supported = true;
2111         else
2112                 spec->ht.ht_supported = false;
2113
2114         spec->ht.cap =
2115             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2116             IEEE80211_HT_CAP_GRN_FLD |
2117             IEEE80211_HT_CAP_SGI_20 |
2118             IEEE80211_HT_CAP_SGI_40 |
2119             IEEE80211_HT_CAP_TX_STBC |
2120             IEEE80211_HT_CAP_RX_STBC;
2121         spec->ht.ampdu_factor = 3;
2122         spec->ht.ampdu_density = 4;
2123         spec->ht.mcs.tx_params =
2124             IEEE80211_HT_MCS_TX_DEFINED |
2125             IEEE80211_HT_MCS_TX_RX_DIFF |
2126             ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2127                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2128
2129         switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2130         case 3:
2131                 spec->ht.mcs.rx_mask[2] = 0xff;
2132         case 2:
2133                 spec->ht.mcs.rx_mask[1] = 0xff;
2134         case 1:
2135                 spec->ht.mcs.rx_mask[0] = 0xff;
2136                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2137                 break;
2138         }
2139
2140         /*
2141          * Create channel information array
2142          */
2143         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2144         if (!info)
2145                 return -ENOMEM;
2146
2147         spec->channels_info = info;
2148
2149         tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2150         tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2151
2152         for (i = 0; i < 14; i++) {
2153                 info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2154                 info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2155         }
2156
2157         if (spec->num_channels > 14) {
2158                 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2159                 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2160
2161                 for (i = 14; i < spec->num_channels; i++) {
2162                         info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2163                         info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2164                 }
2165         }
2166
2167         return 0;
2168 }
2169 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
2170
2171 /*
2172  * IEEE80211 stack callback functions.
2173  */
2174 static void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
2175                                 u32 *iv32, u16 *iv16)
2176 {
2177         struct rt2x00_dev *rt2x00dev = hw->priv;
2178         struct mac_iveiv_entry iveiv_entry;
2179         u32 offset;
2180
2181         offset = MAC_IVEIV_ENTRY(hw_key_idx);
2182         rt2800_register_multiread(rt2x00dev, offset,
2183                                       &iveiv_entry, sizeof(iveiv_entry));
2184
2185         memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
2186         memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2187 }
2188
2189 static int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2190 {
2191         struct rt2x00_dev *rt2x00dev = hw->priv;
2192         u32 reg;
2193         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2194
2195         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2196         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2197         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2198
2199         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2200         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2201         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2202
2203         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2204         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2205         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2206
2207         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2208         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2209         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2210
2211         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2212         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2213         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2214
2215         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2216         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
2217         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2218
2219         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2220         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
2221         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2222
2223         return 0;
2224 }
2225
2226 static int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2227                           const struct ieee80211_tx_queue_params *params)
2228 {
2229         struct rt2x00_dev *rt2x00dev = hw->priv;
2230         struct data_queue *queue;
2231         struct rt2x00_field32 field;
2232         int retval;
2233         u32 reg;
2234         u32 offset;
2235
2236         /*
2237          * First pass the configuration through rt2x00lib, that will
2238          * update the queue settings and validate the input. After that
2239          * we are free to update the registers based on the value
2240          * in the queue parameter.
2241          */
2242         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2243         if (retval)
2244                 return retval;
2245
2246         /*
2247          * We only need to perform additional register initialization
2248          * for WMM queues/
2249          */
2250         if (queue_idx >= 4)
2251                 return 0;
2252
2253         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2254
2255         /* Update WMM TXOP register */
2256         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
2257         field.bit_offset = (queue_idx & 1) * 16;
2258         field.bit_mask = 0xffff << field.bit_offset;
2259
2260         rt2800_register_read(rt2x00dev, offset, &reg);
2261         rt2x00_set_field32(&reg, field, queue->txop);
2262         rt2800_register_write(rt2x00dev, offset, reg);
2263
2264         /* Update WMM registers */
2265         field.bit_offset = queue_idx * 4;
2266         field.bit_mask = 0xf << field.bit_offset;
2267
2268         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2269         rt2x00_set_field32(&reg, field, queue->aifs);
2270         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2271
2272         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2273         rt2x00_set_field32(&reg, field, queue->cw_min);
2274         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2275
2276         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2277         rt2x00_set_field32(&reg, field, queue->cw_max);
2278         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2279
2280         /* Update EDCA registers */
2281         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2282
2283         rt2800_register_read(rt2x00dev, offset, &reg);
2284         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
2285         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2286         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2287         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2288         rt2800_register_write(rt2x00dev, offset, reg);
2289
2290         return 0;
2291 }
2292
2293 static u64 rt2800_get_tsf(struct ieee80211_hw *hw)
2294 {
2295         struct rt2x00_dev *rt2x00dev = hw->priv;
2296         u64 tsf;
2297         u32 reg;
2298
2299         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2300         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2301         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2302         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2303
2304         return tsf;
2305 }
2306
2307 const struct ieee80211_ops rt2800_mac80211_ops = {
2308         .tx                     = rt2x00mac_tx,
2309         .start                  = rt2x00mac_start,
2310         .stop                   = rt2x00mac_stop,
2311         .add_interface          = rt2x00mac_add_interface,
2312         .remove_interface       = rt2x00mac_remove_interface,
2313         .config                 = rt2x00mac_config,
2314         .configure_filter       = rt2x00mac_configure_filter,
2315         .set_tim                = rt2x00mac_set_tim,
2316         .set_key                = rt2x00mac_set_key,
2317         .get_stats              = rt2x00mac_get_stats,
2318         .get_tkip_seq           = rt2800_get_tkip_seq,
2319         .set_rts_threshold      = rt2800_set_rts_threshold,
2320         .bss_info_changed       = rt2x00mac_bss_info_changed,
2321         .conf_tx                = rt2800_conf_tx,
2322         .get_tsf                = rt2800_get_tsf,
2323         .rfkill_poll            = rt2x00mac_rfkill_poll,
2324 };
2325 EXPORT_SYMBOL_GPL(rt2800_mac80211_ops);