drivers/net/wireless/ath/ath9k/eeprom_4k.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "hw.h"
  18 #include "ar9002_phy.h"
  19
  20 static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah)
  21 {
  22         return ((ah->eeprom.map4k.baseEepHeader.version >> 12) & 0xF);
  23 }
  24
  25 static int ath9k_hw_4k_get_eeprom_rev(struct ath_hw *ah)
  26 {
  27         return ((ah->eeprom.map4k.baseEepHeader.version) & 0xFFF);
  28 }
  29
  30 static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
  31 {
  32 #define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
  33         struct ath_common *common = ath9k_hw_common(ah);
  34         u16 *eep_data = (u16 *)&ah->eeprom.map4k;
  35         int addr, eep_start_loc = 0;
  36
  37         eep_start_loc = 64;
  38
  39         if (!ath9k_hw_use_flash(ah)) {
  40                 ath_print(common, ATH_DBG_EEPROM,
  41                           "Reading from EEPROM, not flash\n");
  42         }
  43
  44         for (addr = 0; addr < SIZE_EEPROM_4K; addr++) {
  45                 if (!ath9k_hw_nvram_read(common, addr + eep_start_loc, eep_data)) {
  46                         ath_print(common, ATH_DBG_EEPROM,
  47                                   "Unable to read eeprom region\n");
  48                         return false;
  49                 }
  50                 eep_data++;
  51         }
  52
  53         return true;
  54 #undef SIZE_EEPROM_4K
  55 }
  56
  57 static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
  58 {
  59 #define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
  60         struct ath_common *common = ath9k_hw_common(ah);
  61         struct ar5416_eeprom_4k *eep =
  62                 (struct ar5416_eeprom_4k *) &ah->eeprom.map4k;
  63         u16 *eepdata, temp, magic, magic2;
  64         u32 sum = 0, el;
  65         bool need_swap = false;
  66         int i, addr;
  67
  68
  69         if (!ath9k_hw_use_flash(ah)) {
  70                 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET,
  71                                          &magic)) {
  72                         ath_print(common, ATH_DBG_FATAL,
  73                                   "Reading Magic # failed\n");
  74                         return false;
  75                 }
  76
  77                 ath_print(common, ATH_DBG_EEPROM,
  78                           "Read Magic = 0x%04X\n", magic);
  79
  80                 if (magic != AR5416_EEPROM_MAGIC) {
  81                         magic2 = swab16(magic);
  82
  83                         if (magic2 == AR5416_EEPROM_MAGIC) {
  84                                 need_swap = true;
  85                                 eepdata = (u16 *) (&ah->eeprom);
  86
  87                                 for (addr = 0; addr < EEPROM_4K_SIZE; addr++) {
  88                                         temp = swab16(*eepdata);
  89                                         *eepdata = temp;
  90                                         eepdata++;
  91                                 }
  92                         } else {
  93                                 ath_print(common, ATH_DBG_FATAL,
  94                                           "Invalid EEPROM Magic. "
  95                                           "endianness mismatch.\n");
  96                                 return -EINVAL;
  97                         }
  98                 }
  99         }
 100
 101         ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
 102                   need_swap ? "True" : "False");
 103
 104         if (need_swap)
 105                 el = swab16(ah->eeprom.map4k.baseEepHeader.length);
 106         else
 107                 el = ah->eeprom.map4k.baseEepHeader.length;
 108
 109         if (el > sizeof(struct ar5416_eeprom_4k))
 110                 el = sizeof(struct ar5416_eeprom_4k) / sizeof(u16);
 111         else
 112                 el = el / sizeof(u16);
 113
 114         eepdata = (u16 *)(&ah->eeprom);
 115
 116         for (i = 0; i < el; i++)
 117                 sum ^= *eepdata++;
 118
 119         if (need_swap) {
 120                 u32 integer;
 121                 u16 word;
 122
 123                 ath_print(common, ATH_DBG_EEPROM,
 124                           "EEPROM Endianness is not native.. Changing\n");
 125
 126                 word = swab16(eep->baseEepHeader.length);
 127                 eep->baseEepHeader.length = word;
 128
 129                 word = swab16(eep->baseEepHeader.checksum);
 130                 eep->baseEepHeader.checksum = word;
 131
 132                 word = swab16(eep->baseEepHeader.version);
 133                 eep->baseEepHeader.version = word;
 134
 135                 word = swab16(eep->baseEepHeader.regDmn[0]);
 136                 eep->baseEepHeader.regDmn[0] = word;
 137
 138                 word = swab16(eep->baseEepHeader.regDmn[1]);
 139                 eep->baseEepHeader.regDmn[1] = word;
 140
 141                 word = swab16(eep->baseEepHeader.rfSilent);
 142                 eep->baseEepHeader.rfSilent = word;
 143
 144                 word = swab16(eep->baseEepHeader.blueToothOptions);
 145                 eep->baseEepHeader.blueToothOptions = word;
 146
 147                 word = swab16(eep->baseEepHeader.deviceCap);
 148                 eep->baseEepHeader.deviceCap = word;
 149
 150                 integer = swab32(eep->modalHeader.antCtrlCommon);
 151                 eep->modalHeader.antCtrlCommon = integer;
 152
 153                 for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) {
 154                         integer = swab32(eep->modalHeader.antCtrlChain[i]);
 155                         eep->modalHeader.antCtrlChain[i] = integer;
 156                 }
 157
 158                 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
 159                         word = swab16(eep->modalHeader.spurChans[i].spurChan);
 160                         eep->modalHeader.spurChans[i].spurChan = word;
 161                 }
 162         }
 163
 164         if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
 165             ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
 166                 ath_print(common, ATH_DBG_FATAL,
 167                           "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
 168                           sum, ah->eep_ops->get_eeprom_ver(ah));
 169                 return -EINVAL;
 170         }
 171
 172         return 0;
 173 #undef EEPROM_4K_SIZE
 174 }
 175
 176 static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
 177                                   enum eeprom_param param)
 178 {
 179         struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
 180         struct modal_eep_4k_header *pModal = &eep->modalHeader;
 181         struct base_eep_header_4k *pBase = &eep->baseEepHeader;
 182
 183         switch (param) {
 184         case EEP_NFTHRESH_2:
 185                 return pModal->noiseFloorThreshCh[0];
 186         case EEP_MAC_LSW:
 187                 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
 188         case EEP_MAC_MID:
 189                 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
 190         case EEP_MAC_MSW:
 191                 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
 192         case EEP_REG_0:
 193                 return pBase->regDmn[0];
 194         case EEP_REG_1:
 195                 return pBase->regDmn[1];
 196         case EEP_OP_CAP:
 197                 return pBase->deviceCap;
 198         case EEP_OP_MODE:
 199                 return pBase->opCapFlags;
 200         case EEP_RF_SILENT:
 201                 return pBase->rfSilent;
 202         case EEP_OB_2:
 203                 return pModal->ob_0;
 204         case EEP_DB_2:
 205                 return pModal->db1_1;
 206         case EEP_MINOR_REV:
 207                 return pBase->version & AR5416_EEP_VER_MINOR_MASK;
 208         case EEP_TX_MASK:
 209                 return pBase->txMask;
 210         case EEP_RX_MASK:
 211                 return pBase->rxMask;
 212         case EEP_FRAC_N_5G:
 213                 return 0;
 214         case EEP_PWR_TABLE_OFFSET:
 215                 return AR5416_PWR_TABLE_OFFSET_DB;
 216         case EEP_MODAL_VER:
 217                 return pModal->version;
 218         case EEP_ANT_DIV_CTL1:
 219                 return pModal->antdiv_ctl1;
 220         default:
 221                 return 0;
 222         }
 223 }
 224
 225 static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hw *ah,
 226                                 struct ath9k_channel *chan,
 227                                 struct cal_data_per_freq_4k *pRawDataSet,
 228                                 u8 *bChans, u16 availPiers,
 229                                 u16 tPdGainOverlap,
 230                                 u16 *pPdGainBoundaries, u8 *pPDADCValues,
 231                                 u16 numXpdGains)
 232 {
 233 #define TMP_VAL_VPD_TABLE \
 234         ((vpdTableI[i][sizeCurrVpdTable - 1] + (ss - maxIndex + 1) * vpdStep));
 235         int i, j, k;
 236         int16_t ss;
 237         u16 idxL = 0, idxR = 0, numPiers;
 238         static u8 vpdTableL[AR5416_EEP4K_NUM_PD_GAINS]
 239                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
 240         static u8 vpdTableR[AR5416_EEP4K_NUM_PD_GAINS]
 241                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
 242         static u8 vpdTableI[AR5416_EEP4K_NUM_PD_GAINS]
 243                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
 244
 245         u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
 246         u8 minPwrT4[AR5416_EEP4K_NUM_PD_GAINS];
 247         u8 maxPwrT4[AR5416_EEP4K_NUM_PD_GAINS];
 248         int16_t vpdStep;
 249         int16_t tmpVal;
 250         u16 sizeCurrVpdTable, maxIndex, tgtIndex;
 251         bool match;
 252         int16_t minDelta = 0;
 253         struct chan_centers centers;
 254 #define PD_GAIN_BOUNDARY_DEFAULT 58;
 255
 256         memset(&minPwrT4, 0, AR9287_NUM_PD_GAINS);
 257         ath9k_hw_get_channel_centers(ah, chan, &centers);
 258
 259         for (numPiers = 0; numPiers < availPiers; numPiers++) {
 260                 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
 261                         break;
 262         }
 263
 264         match = ath9k_hw_get_lower_upper_index(
 265                                         (u8)FREQ2FBIN(centers.synth_center,
 266                                         IS_CHAN_2GHZ(chan)), bChans, numPiers,
 267                                         &idxL, &idxR);
 268
 269         if (match) {
 270                 for (i = 0; i < numXpdGains; i++) {
 271                         minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
 272                         maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
 273                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
 274                                         pRawDataSet[idxL].pwrPdg[i],
 275                                         pRawDataSet[idxL].vpdPdg[i],
 276                                         AR5416_EEP4K_PD_GAIN_ICEPTS,
 277                                         vpdTableI[i]);
 278                 }
 279         } else {
 280                 for (i = 0; i < numXpdGains; i++) {
 281                         pVpdL = pRawDataSet[idxL].vpdPdg[i];
 282                         pPwrL = pRawDataSet[idxL].pwrPdg[i];
 283                         pVpdR = pRawDataSet[idxR].vpdPdg[i];
 284                         pPwrR = pRawDataSet[idxR].pwrPdg[i];
 285
 286                         minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
 287
 288                         maxPwrT4[i] =
 289                                 min(pPwrL[AR5416_EEP4K_PD_GAIN_ICEPTS - 1],
 290                                     pPwrR[AR5416_EEP4K_PD_GAIN_ICEPTS - 1]);
 291
 292
 293                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
 294                                                 pPwrL, pVpdL,
 295                                                 AR5416_EEP4K_PD_GAIN_ICEPTS,
 296                                                 vpdTableL[i]);
 297                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
 298                                                 pPwrR, pVpdR,
 299                                                 AR5416_EEP4K_PD_GAIN_ICEPTS,
 300                                                 vpdTableR[i]);
 301
 302                         for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
 303                                 vpdTableI[i][j] =
 304                                         (u8)(ath9k_hw_interpolate((u16)
 305                                              FREQ2FBIN(centers.
 306                                                        synth_center,
 307                                                        IS_CHAN_2GHZ
 308                                                        (chan)),
 309                                              bChans[idxL], bChans[idxR],
 310                                              vpdTableL[i][j], vpdTableR[i][j]));
 311                         }
 312                 }
 313         }
 314
 315         k = 0;
 316
 317         for (i = 0; i < numXpdGains; i++) {
 318                 if (i == (numXpdGains - 1))
 319                         pPdGainBoundaries[i] =
 320                                 (u16)(maxPwrT4[i] / 2);
 321                 else
 322                         pPdGainBoundaries[i] =
 323                                 (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
 324
 325                 pPdGainBoundaries[i] =
 326                         min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
 327
 328                 if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
 329                         minDelta = pPdGainBoundaries[0] - 23;
 330                         pPdGainBoundaries[0] = 23;
 331                 } else {
 332                         minDelta = 0;
 333                 }
 334
 335                 if (i == 0) {
 336                         if (AR_SREV_9280_10_OR_LATER(ah))
 337                                 ss = (int16_t)(0 - (minPwrT4[i] / 2));
 338                         else
 339                                 ss = 0;
 340                 } else {
 341                         ss = (int16_t)((pPdGainBoundaries[i - 1] -
 342                                         (minPwrT4[i] / 2)) -
 343                                        tPdGainOverlap + 1 + minDelta);
 344                 }
 345                 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
 346                 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
 347
 348                 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
 349                         tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
 350                         pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
 351                         ss++;
 352                 }
 353
 354                 sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
 355                 tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
 356                                 (minPwrT4[i] / 2));
 357                 maxIndex = (tgtIndex < sizeCurrVpdTable) ?
 358                         tgtIndex : sizeCurrVpdTable;
 359
 360                 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1)))
 361                         pPDADCValues[k++] = vpdTableI[i][ss++];
 362
 363                 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
 364                                     vpdTableI[i][sizeCurrVpdTable - 2]);
 365                 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
 366
 367                 if (tgtIndex >= maxIndex) {
 368                         while ((ss <= tgtIndex) &&
 369                                (k < (AR5416_NUM_PDADC_VALUES - 1))) {
 370                                 tmpVal = (int16_t) TMP_VAL_VPD_TABLE;
 371                                 pPDADCValues[k++] = (u8)((tmpVal > 255) ?
 372                                                          255 : tmpVal);
 373                                 ss++;
 374                         }
 375                 }
 376         }
 377
 378         while (i < AR5416_EEP4K_PD_GAINS_IN_MASK) {
 379                 pPdGainBoundaries[i] = PD_GAIN_BOUNDARY_DEFAULT;
 380                 i++;
 381         }
 382
 383         while (k < AR5416_NUM_PDADC_VALUES) {
 384                 pPDADCValues[k] = pPDADCValues[k - 1];
 385                 k++;
 386         }
 387
 388         return;
 389 #undef TMP_VAL_VPD_TABLE
 390 }
 391
 392 static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
 393                                   struct ath9k_channel *chan,
 394                                   int16_t *pTxPowerIndexOffset)
 395 {
 396         struct ath_common *common = ath9k_hw_common(ah);
 397         struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
 398         struct cal_data_per_freq_4k *pRawDataset;
 399         u8 *pCalBChans = NULL;
 400         u16 pdGainOverlap_t2;
 401         static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
 402         u16 gainBoundaries[AR5416_EEP4K_PD_GAINS_IN_MASK];
 403         u16 numPiers, i, j;
 404         u16 numXpdGain, xpdMask;
 405         u16 xpdGainValues[AR5416_EEP4K_NUM_PD_GAINS] = { 0, 0 };
 406         u32 reg32, regOffset, regChainOffset;
 407
 408         xpdMask = pEepData->modalHeader.xpdGain;
 409
 410         if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
 411             AR5416_EEP_MINOR_VER_2) {
 412                 pdGainOverlap_t2 =
 413                         pEepData->modalHeader.pdGainOverlap;
 414         } else {
 415                 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
 416                                             AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
 417         }
 418
 419         pCalBChans = pEepData->calFreqPier2G;
 420         numPiers = AR5416_EEP4K_NUM_2G_CAL_PIERS;
 421
 422         numXpdGain = 0;
 423
 424         for (i = 1; i <= AR5416_EEP4K_PD_GAINS_IN_MASK; i++) {
 425                 if ((xpdMask >> (AR5416_EEP4K_PD_GAINS_IN_MASK - i)) & 1) {
 426                         if (numXpdGain >= AR5416_EEP4K_NUM_PD_GAINS)
 427                                 break;
 428                         xpdGainValues[numXpdGain] =
 429                                 (u16)(AR5416_EEP4K_PD_GAINS_IN_MASK - i);
 430                         numXpdGain++;
 431                 }
 432         }
 433
 434         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
 435                       (numXpdGain - 1) & 0x3);
 436         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
 437                       xpdGainValues[0]);
 438         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
 439                       xpdGainValues[1]);
 440         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, 0);
 441
 442         for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) {
 443                 if (AR_SREV_5416_20_OR_LATER(ah) &&
 444                     (ah->rxchainmask == 5 || ah->txchainmask == 5) &&
 445                     (i != 0)) {
 446                         regChainOffset = (i == 1) ? 0x2000 : 0x1000;
 447                 } else
 448                         regChainOffset = i * 0x1000;
 449
 450                 if (pEepData->baseEepHeader.txMask & (1 << i)) {
 451                         pRawDataset = pEepData->calPierData2G[i];
 452
 453                         ath9k_hw_get_4k_gain_boundaries_pdadcs(ah, chan,
 454                                             pRawDataset, pCalBChans,
 455                                             numPiers, pdGainOverlap_t2,
 456                                             gainBoundaries,
 457                                             pdadcValues, numXpdGain);
 458
 459                         ENABLE_REGWRITE_BUFFER(ah);
 460
 461                         if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
 462                                 REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,
 463                                           SM(pdGainOverlap_t2,
 464                                              AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
 465                                           | SM(gainBoundaries[0],
 466                                                AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
 467                                           | SM(gainBoundaries[1],
 468                                                AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
 469                                           | SM(gainBoundaries[2],
 470                                                AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
 471                                           | SM(gainBoundaries[3],
 472                                        AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
 473                         }
 474
 475                         regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
 476                         for (j = 0; j < 32; j++) {
 477                                 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) |
 478                                         ((pdadcValues[4 * j + 1] & 0xFF) << 8) |
 479                                         ((pdadcValues[4 * j + 2] & 0xFF) << 16)|
 480                                         ((pdadcValues[4 * j + 3] & 0xFF) << 24);
 481                                 REG_WRITE(ah, regOffset, reg32);
 482
 483                                 ath_print(common, ATH_DBG_EEPROM,
 484                                           "PDADC (%d,%4x): %4.4x %8.8x\n",
 485                                           i, regChainOffset, regOffset,
 486                                           reg32);
 487                                 ath_print(common, ATH_DBG_EEPROM,
 488                                           "PDADC: Chain %d | "
 489                                           "PDADC %3d Value %3d | "
 490                                           "PDADC %3d Value %3d | "
 491                                           "PDADC %3d Value %3d | "
 492                                           "PDADC %3d Value %3d |\n",
 493                                           i, 4 * j, pdadcValues[4 * j],
 494                                           4 * j + 1, pdadcValues[4 * j + 1],
 495                                           4 * j + 2, pdadcValues[4 * j + 2],
 496                                           4 * j + 3,
 497                                           pdadcValues[4 * j + 3]);
 498
 499                                 regOffset += 4;
 500                         }
 501
 502                         REGWRITE_BUFFER_FLUSH(ah);
 503                         DISABLE_REGWRITE_BUFFER(ah);
 504                 }
 505         }
 506
 507         *pTxPowerIndexOffset = 0;
 508 }
 509
 510 static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
 511                                                  struct ath9k_channel *chan,
 512                                                  int16_t *ratesArray,
 513                                                  u16 cfgCtl,
 514                                                  u16 AntennaReduction,
 515                                                  u16 twiceMaxRegulatoryPower,
 516                                                  u16 powerLimit)
 517 {
 518 #define CMP_TEST_GRP \
 519         (((cfgCtl & ~CTL_MODE_M)| (pCtlMode[ctlMode] & CTL_MODE_M)) ==  \
 520          pEepData->ctlIndex[i])                                         \
 521         || (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \
 522             ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))
 523
 524         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
 525         int i;
 526         int16_t twiceLargestAntenna;
 527         u16 twiceMinEdgePower;
 528         u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
 529         u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
 530         u16 numCtlModes, *pCtlMode, ctlMode, freq;
 531         struct chan_centers centers;
 532         struct cal_ctl_data_4k *rep;
 533         struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
 534         static const u16 tpScaleReductionTable[5] =
 535                 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
 536         struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
 537                 0, { 0, 0, 0, 0}
 538         };
 539         struct cal_target_power_leg targetPowerOfdmExt = {
 540                 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
 541                 0, { 0, 0, 0, 0 }
 542         };
 543         struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
 544                 0, {0, 0, 0, 0}
 545         };
 546         u16 ctlModesFor11g[] =
 547                 { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
 548                   CTL_2GHT40
 549                 };
 550
 551         ath9k_hw_get_channel_centers(ah, chan, &centers);
 552
 553         twiceLargestAntenna = pEepData->modalHeader.antennaGainCh[0];
 554         twiceLargestAntenna = (int16_t)min(AntennaReduction -
 555                                            twiceLargestAntenna, 0);
 556
 557         maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
 558         if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
 559                 maxRegAllowedPower -=
 560                         (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
 561         }
 562
 563         scaledPower = min(powerLimit, maxRegAllowedPower);
 564         scaledPower = max((u16)0, scaledPower);
 565
 566         numCtlModes = ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40;
 567         pCtlMode = ctlModesFor11g;
 568
 569         ath9k_hw_get_legacy_target_powers(ah, chan,
 570                         pEepData->calTargetPowerCck,
 571                         AR5416_NUM_2G_CCK_TARGET_POWERS,
 572                         &targetPowerCck, 4, false);
 573         ath9k_hw_get_legacy_target_powers(ah, chan,
 574                         pEepData->calTargetPower2G,
 575                         AR5416_NUM_2G_20_TARGET_POWERS,
 576                         &targetPowerOfdm, 4, false);
 577         ath9k_hw_get_target_powers(ah, chan,
 578                         pEepData->calTargetPower2GHT20,
 579                         AR5416_NUM_2G_20_TARGET_POWERS,
 580                         &targetPowerHt20, 8, false);
 581
 582         if (IS_CHAN_HT40(chan)) {
 583                 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
 584                 ath9k_hw_get_target_powers(ah, chan,
 585                                 pEepData->calTargetPower2GHT40,
 586                                 AR5416_NUM_2G_40_TARGET_POWERS,
 587                                 &targetPowerHt40, 8, true);
 588                 ath9k_hw_get_legacy_target_powers(ah, chan,
 589                                 pEepData->calTargetPowerCck,
 590                                 AR5416_NUM_2G_CCK_TARGET_POWERS,
 591                                 &targetPowerCckExt, 4, true);
 592                 ath9k_hw_get_legacy_target_powers(ah, chan,
 593                                 pEepData->calTargetPower2G,
 594                                 AR5416_NUM_2G_20_TARGET_POWERS,
 595                                 &targetPowerOfdmExt, 4, true);
 596         }
 597
 598         for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
 599                 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
 600                         (pCtlMode[ctlMode] == CTL_2GHT40);
 601
 602                 if (isHt40CtlMode)
 603                         freq = centers.synth_center;
 604                 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
 605                         freq = centers.ext_center;
 606                 else
 607                         freq = centers.ctl_center;
 608
 609                 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
 610                     ah->eep_ops->get_eeprom_rev(ah) <= 2)
 611                         twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
 612
 613                 for (i = 0; (i < AR5416_EEP4K_NUM_CTLS) &&
 614                              pEepData->ctlIndex[i]; i++) {
 615
 616                         if (CMP_TEST_GRP) {
 617                                 rep = &(pEepData->ctlData[i]);
 618
 619                                 twiceMinEdgePower = ath9k_hw_get_max_edge_power(
 620                                         freq,
 621                                         rep->ctlEdges[
 622                                         ar5416_get_ntxchains(ah->txchainmask) - 1],
 623                                         IS_CHAN_2GHZ(chan),
 624                                         AR5416_EEP4K_NUM_BAND_EDGES);
 625
 626                                 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
 627                                         twiceMaxEdgePower =
 628                                                 min(twiceMaxEdgePower,
 629                                                     twiceMinEdgePower);
 630                                 } else {
 631                                         twiceMaxEdgePower = twiceMinEdgePower;
 632                                         break;
 633                                 }
 634                         }
 635                 }
 636
 637                 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
 638
 639                 switch (pCtlMode[ctlMode]) {
 640                 case CTL_11B:
 641                         for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
 642                                 targetPowerCck.tPow2x[i] =
 643                                         min((u16)targetPowerCck.tPow2x[i],
 644                                             minCtlPower);
 645                         }
 646                         break;
 647                 case CTL_11G:
 648                         for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
 649                                 targetPowerOfdm.tPow2x[i] =
 650                                         min((u16)targetPowerOfdm.tPow2x[i],
 651                                             minCtlPower);
 652                         }
 653                         break;
 654                 case CTL_2GHT20:
 655                         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
 656                                 targetPowerHt20.tPow2x[i] =
 657                                         min((u16)targetPowerHt20.tPow2x[i],
 658                                             minCtlPower);
 659                         }
 660                         break;
 661                 case CTL_11B_EXT:
 662                         targetPowerCckExt.tPow2x[0] =
 663                                 min((u16)targetPowerCckExt.tPow2x[0],
 664                                     minCtlPower);
 665                         break;
 666                 case CTL_11G_EXT:
 667                         targetPowerOfdmExt.tPow2x[0] =
 668                                 min((u16)targetPowerOfdmExt.tPow2x[0],
 669                                     minCtlPower);
 670                         break;
 671                 case CTL_2GHT40:
 672                         for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
 673                                 targetPowerHt40.tPow2x[i] =
 674                                         min((u16)targetPowerHt40.tPow2x[i],
 675                                             minCtlPower);
 676                         }
 677                         break;
 678                 default:
 679                         break;
 680                 }
 681         }
 682
 683         ratesArray[rate6mb] =
 684         ratesArray[rate9mb] =
 685         ratesArray[rate12mb] =
 686         ratesArray[rate18mb] =
 687         ratesArray[rate24mb] =
 688         targetPowerOfdm.tPow2x[0];
 689
 690         ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
 691         ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
 692         ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
 693         ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
 694
 695         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
 696                 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
 697
 698         ratesArray[rate1l] = targetPowerCck.tPow2x[0];
 699         ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1];
 700         ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2];
 701         ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3];
 702
 703         if (IS_CHAN_HT40(chan)) {
 704                 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
 705                         ratesArray[rateHt40_0 + i] =
 706                                 targetPowerHt40.tPow2x[i];
 707                 }
 708                 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
 709                 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
 710                 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
 711                 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
 712         }
 713
 714 #undef CMP_TEST_GRP
 715 }
 716
 717 static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
 718                                     struct ath9k_channel *chan,
 719                                     u16 cfgCtl,
 720                                     u8 twiceAntennaReduction,
 721                                     u8 twiceMaxRegulatoryPower,
 722                                     u8 powerLimit)
 723 {
 724         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
 725         struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
 726         struct modal_eep_4k_header *pModal = &pEepData->modalHeader;
 727         int16_t ratesArray[Ar5416RateSize];
 728         int16_t txPowerIndexOffset = 0;
 729         u8 ht40PowerIncForPdadc = 2;
 730         int i;
 731
 732         memset(ratesArray, 0, sizeof(ratesArray));
 733
 734         if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
 735             AR5416_EEP_MINOR_VER_2) {
 736                 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
 737         }
 738
 739         ath9k_hw_set_4k_power_per_rate_table(ah, chan,
 740                                              &ratesArray[0], cfgCtl,
 741                                              twiceAntennaReduction,
 742                                              twiceMaxRegulatoryPower,
 743                                              powerLimit);
 744
 745         ath9k_hw_set_4k_power_cal_table(ah, chan, &txPowerIndexOffset);
 746
 747         for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
 748                 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
 749                 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
 750                         ratesArray[i] = AR5416_MAX_RATE_POWER;
 751         }
 752
 753
 754         /* Update regulatory */
 755
 756         i = rate6mb;
 757         if (IS_CHAN_HT40(chan))
 758                 i = rateHt40_0;
 759         else if (IS_CHAN_HT20(chan))
 760                 i = rateHt20_0;
 761
 762         regulatory->max_power_level = ratesArray[i];
 763
 764         if (AR_SREV_9280_10_OR_LATER(ah)) {
 765                 for (i = 0; i < Ar5416RateSize; i++)
 766                         ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2;
 767         }
 768
 769         ENABLE_REGWRITE_BUFFER(ah);
 770
 771         /* OFDM power per rate */
 772         REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
 773                   ATH9K_POW_SM(ratesArray[rate18mb], 24)
 774                   | ATH9K_POW_SM(ratesArray[rate12mb], 16)
 775                   | ATH9K_POW_SM(ratesArray[rate9mb], 8)
 776                   | ATH9K_POW_SM(ratesArray[rate6mb], 0));
 777         REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
 778                   ATH9K_POW_SM(ratesArray[rate54mb], 24)
 779                   | ATH9K_POW_SM(ratesArray[rate48mb], 16)
 780                   | ATH9K_POW_SM(ratesArray[rate36mb], 8)
 781                   | ATH9K_POW_SM(ratesArray[rate24mb], 0));
 782
 783         /* CCK power per rate */
 784         REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
 785                   ATH9K_POW_SM(ratesArray[rate2s], 24)
 786                   | ATH9K_POW_SM(ratesArray[rate2l], 16)
 787                   | ATH9K_POW_SM(ratesArray[rateXr], 8)
 788                   | ATH9K_POW_SM(ratesArray[rate1l], 0));
 789         REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
 790                   ATH9K_POW_SM(ratesArray[rate11s], 24)
 791                   | ATH9K_POW_SM(ratesArray[rate11l], 16)
 792                   | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
 793                   | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
 794
 795         /* HT20 power per rate */
 796         REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
 797                   ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
 798                   | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
 799                   | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
 800                   | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
 801         REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
 802                   ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
 803                   | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
 804                   | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
 805                   | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
 806
 807         /* HT40 power per rate */
 808         if (IS_CHAN_HT40(chan)) {
 809                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
 810                           ATH9K_POW_SM(ratesArray[rateHt40_3] +
 811                                        ht40PowerIncForPdadc, 24)
 812                           | ATH9K_POW_SM(ratesArray[rateHt40_2] +
 813                                          ht40PowerIncForPdadc, 16)
 814                           | ATH9K_POW_SM(ratesArray[rateHt40_1] +
 815                                          ht40PowerIncForPdadc, 8)
 816                           | ATH9K_POW_SM(ratesArray[rateHt40_0] +
 817                                          ht40PowerIncForPdadc, 0));
 818                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
 819                           ATH9K_POW_SM(ratesArray[rateHt40_7] +
 820                                        ht40PowerIncForPdadc, 24)
 821                           | ATH9K_POW_SM(ratesArray[rateHt40_6] +
 822                                          ht40PowerIncForPdadc, 16)
 823                           | ATH9K_POW_SM(ratesArray[rateHt40_5] +
 824                                          ht40PowerIncForPdadc, 8)
 825                           | ATH9K_POW_SM(ratesArray[rateHt40_4] +
 826                                          ht40PowerIncForPdadc, 0));
 827                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
 828                           ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
 829                           | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
 830                           | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
 831                           | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
 832         }
 833
 834         REGWRITE_BUFFER_FLUSH(ah);
 835         DISABLE_REGWRITE_BUFFER(ah);
 836 }
 837
 838 static void ath9k_hw_4k_set_addac(struct ath_hw *ah,
 839                                   struct ath9k_channel *chan)
 840 {
 841         struct modal_eep_4k_header *pModal;
 842         struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
 843         u8 biaslevel;
 844
 845         if (ah->hw_version.macVersion != AR_SREV_VERSION_9160)
 846                 return;
 847
 848         if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7)
 849                 return;
 850
 851         pModal = &eep->modalHeader;
 852
 853         if (pModal->xpaBiasLvl != 0xff) {
 854                 biaslevel = pModal->xpaBiasLvl;
 855                 INI_RA(&ah->iniAddac, 7, 1) =
 856                   (INI_RA(&ah->iniAddac, 7, 1) & (~0x18)) | biaslevel << 3;
 857         }
 858 }
 859
 860 static void ath9k_hw_4k_set_gain(struct ath_hw *ah,
 861                                  struct modal_eep_4k_header *pModal,
 862                                  struct ar5416_eeprom_4k *eep,
 863                                  u8 txRxAttenLocal)
 864 {
 865         REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0,
 866                   pModal->antCtrlChain[0]);
 867
 868         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0),
 869                   (REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) &
 870                    ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
 871                      AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
 872                   SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
 873                   SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
 874
 875         if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
 876             AR5416_EEP_MINOR_VER_3) {
 877                 txRxAttenLocal = pModal->txRxAttenCh[0];
 878
 879                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
 880                               AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]);
 881                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
 882                               AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
 883                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
 884                               AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
 885                               pModal->xatten2Margin[0]);
 886                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
 887                               AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]);
 888
 889                 /* Set the block 1 value to block 0 value */
 890                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
 891                               AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
 892                               pModal->bswMargin[0]);
 893                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
 894                               AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
 895                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
 896                               AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
 897                               pModal->xatten2Margin[0]);
 898                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
 899                               AR_PHY_GAIN_2GHZ_XATTEN2_DB,
 900                               pModal->xatten2Db[0]);
 901         }
 902
 903         REG_RMW_FIELD(ah, AR_PHY_RXGAIN,
 904                       AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
 905         REG_RMW_FIELD(ah, AR_PHY_RXGAIN,
 906                       AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
 907
 908         REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,
 909                       AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
 910         REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,
 911                       AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
 912
 913         if (AR_SREV_9285_11(ah))
 914                 REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
 915 }
 916
 917 /*
 918  * Read EEPROM header info and program the device for correct operation
 919  * given the channel value.
 920  */
 921 static void ath9k_hw_4k_set_board_values(struct ath_hw *ah,
 922                                          struct ath9k_channel *chan)
 923 {
 924         struct modal_eep_4k_header *pModal;
 925         struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
 926         u8 txRxAttenLocal;
 927         u8 ob[5], db1[5], db2[5];
 928         u8 ant_div_control1, ant_div_control2;
 929         u32 regVal;
 930
 931         pModal = &eep->modalHeader;
 932         txRxAttenLocal = 23;
 933
 934         REG_WRITE(ah, AR_PHY_SWITCH_COM,
 935                   ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
 936
 937         /* Single chain for 4K EEPROM*/
 938         ath9k_hw_4k_set_gain(ah, pModal, eep, txRxAttenLocal);
 939
 940         /* Initialize Ant Diversity settings from EEPROM */
 941         if (pModal->version >= 3) {
 942                 ant_div_control1 = pModal->antdiv_ctl1;
 943                 ant_div_control2 = pModal->antdiv_ctl2;
 944
 945                 regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
 946                 regVal &= (~(AR_PHY_9285_ANT_DIV_CTL_ALL));
 947
 948                 regVal |= SM(ant_div_control1,
 949                              AR_PHY_9285_ANT_DIV_CTL);
 950                 regVal |= SM(ant_div_control2,
 951                              AR_PHY_9285_ANT_DIV_ALT_LNACONF);
 952                 regVal |= SM((ant_div_control2 >> 2),
 953                              AR_PHY_9285_ANT_DIV_MAIN_LNACONF);
 954                 regVal |= SM((ant_div_control1 >> 1),
 955                              AR_PHY_9285_ANT_DIV_ALT_GAINTB);
 956                 regVal |= SM((ant_div_control1 >> 2),
 957                              AR_PHY_9285_ANT_DIV_MAIN_GAINTB);
 958
 959
 960                 REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal);
 961                 regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
 962                 regVal = REG_READ(ah, AR_PHY_CCK_DETECT);
 963                 regVal &= (~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
 964                 regVal |= SM((ant_div_control1 >> 3),
 965                              AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
 966
 967                 REG_WRITE(ah, AR_PHY_CCK_DETECT, regVal);
 968                 regVal = REG_READ(ah, AR_PHY_CCK_DETECT);
 969         }
 970
 971         if (pModal->version >= 2) {
 972                 ob[0] = pModal->ob_0;
 973                 ob[1] = pModal->ob_1;
 974                 ob[2] = pModal->ob_2;
 975                 ob[3] = pModal->ob_3;
 976                 ob[4] = pModal->ob_4;
 977
 978                 db1[0] = pModal->db1_0;
 979                 db1[1] = pModal->db1_1;
 980                 db1[2] = pModal->db1_2;
 981                 db1[3] = pModal->db1_3;
 982                 db1[4] = pModal->db1_4;
 983
 984                 db2[0] = pModal->db2_0;
 985                 db2[1] = pModal->db2_1;
 986                 db2[2] = pModal->db2_2;
 987                 db2[3] = pModal->db2_3;
 988                 db2[4] = pModal->db2_4;
 989         } else if (pModal->version == 1) {
 990                 ob[0] = pModal->ob_0;
 991                 ob[1] = ob[2] = ob[3] = ob[4] = pModal->ob_1;
 992                 db1[0] = pModal->db1_0;
 993                 db1[1] = db1[2] = db1[3] = db1[4] = pModal->db1_1;
 994                 db2[0] = pModal->db2_0;
 995                 db2[1] = db2[2] = db2[3] = db2[4] = pModal->db2_1;
 996         } else {
 997                 int i;
 998
 999                 for (i = 0; i < 5; i++) {
1000                         ob[i] = pModal->ob_0;
1001                         db1[i] = pModal->db1_0;
1002                         db2[i] = pModal->db1_0;
1003                 }
1004         }
1005
1006         if (AR_SREV_9271(ah)) {
1007                 ath9k_hw_analog_shift_rmw(ah,
1008                                           AR9285_AN_RF2G3,
1009                                           AR9271_AN_RF2G3_OB_cck,
1010                                           AR9271_AN_RF2G3_OB_cck_S,
1011                                           ob[0]);
1012                 ath9k_hw_analog_shift_rmw(ah,
1013                                           AR9285_AN_RF2G3,
1014                                           AR9271_AN_RF2G3_OB_psk,
1015                                           AR9271_AN_RF2G3_OB_psk_S,
1016                                           ob[1]);
1017                 ath9k_hw_analog_shift_rmw(ah,
1018                                           AR9285_AN_RF2G3,
1019                                           AR9271_AN_RF2G3_OB_qam,
1020                                           AR9271_AN_RF2G3_OB_qam_S,
1021                                           ob[2]);
1022                 ath9k_hw_analog_shift_rmw(ah,
1023                                           AR9285_AN_RF2G3,
1024                                           AR9271_AN_RF2G3_DB_1,
1025                                           AR9271_AN_RF2G3_DB_1_S,
1026                                           db1[0]);
1027                 ath9k_hw_analog_shift_rmw(ah,
1028                                           AR9285_AN_RF2G4,
1029                                           AR9271_AN_RF2G4_DB_2,
1030                                           AR9271_AN_RF2G4_DB_2_S,
1031                                           db2[0]);
1032         } else {
1033                 ath9k_hw_analog_shift_rmw(ah,
1034                                           AR9285_AN_RF2G3,
1035                                           AR9285_AN_RF2G3_OB_0,
1036                                           AR9285_AN_RF2G3_OB_0_S,
1037                                           ob[0]);
1038                 ath9k_hw_analog_shift_rmw(ah,
1039                                           AR9285_AN_RF2G3,
1040                                           AR9285_AN_RF2G3_OB_1,
1041                                           AR9285_AN_RF2G3_OB_1_S,
1042                                           ob[1]);
1043                 ath9k_hw_analog_shift_rmw(ah,
1044                                           AR9285_AN_RF2G3,
1045                                           AR9285_AN_RF2G3_OB_2,
1046                                           AR9285_AN_RF2G3_OB_2_S,
1047                                           ob[2]);
1048                 ath9k_hw_analog_shift_rmw(ah,
1049                                           AR9285_AN_RF2G3,
1050                                           AR9285_AN_RF2G3_OB_3,
1051                                           AR9285_AN_RF2G3_OB_3_S,
1052                                           ob[3]);
1053                 ath9k_hw_analog_shift_rmw(ah,
1054                                           AR9285_AN_RF2G3,
1055                                           AR9285_AN_RF2G3_OB_4,
1056                                           AR9285_AN_RF2G3_OB_4_S,
1057                                           ob[4]);
1058
1059                 ath9k_hw_analog_shift_rmw(ah,
1060                                           AR9285_AN_RF2G3,
1061                                           AR9285_AN_RF2G3_DB1_0,
1062                                           AR9285_AN_RF2G3_DB1_0_S,
1063                                           db1[0]);
1064                 ath9k_hw_analog_shift_rmw(ah,
1065                                           AR9285_AN_RF2G3,
1066                                           AR9285_AN_RF2G3_DB1_1,
1067                                           AR9285_AN_RF2G3_DB1_1_S,
1068                                           db1[1]);
1069                 ath9k_hw_analog_shift_rmw(ah,
1070                                           AR9285_AN_RF2G3,
1071                                           AR9285_AN_RF2G3_DB1_2,
1072                                           AR9285_AN_RF2G3_DB1_2_S,
1073                                           db1[2]);
1074                 ath9k_hw_analog_shift_rmw(ah,
1075                                           AR9285_AN_RF2G4,
1076                                           AR9285_AN_RF2G4_DB1_3,
1077                                           AR9285_AN_RF2G4_DB1_3_S,
1078                                           db1[3]);
1079                 ath9k_hw_analog_shift_rmw(ah,
1080                                           AR9285_AN_RF2G4,
1081                                           AR9285_AN_RF2G4_DB1_4,
1082                                           AR9285_AN_RF2G4_DB1_4_S, db1[4]);
1083
1084                 ath9k_hw_analog_shift_rmw(ah,
1085                                           AR9285_AN_RF2G4,
1086                                           AR9285_AN_RF2G4_DB2_0,
1087                                           AR9285_AN_RF2G4_DB2_0_S,
1088                                           db2[0]);
1089                 ath9k_hw_analog_shift_rmw(ah,
1090                                           AR9285_AN_RF2G4,
1091                                           AR9285_AN_RF2G4_DB2_1,
1092                                           AR9285_AN_RF2G4_DB2_1_S,
1093                                           db2[1]);
1094                 ath9k_hw_analog_shift_rmw(ah,
1095                                           AR9285_AN_RF2G4,
1096                                           AR9285_AN_RF2G4_DB2_2,
1097                                           AR9285_AN_RF2G4_DB2_2_S,
1098                                           db2[2]);
1099                 ath9k_hw_analog_shift_rmw(ah,
1100                                           AR9285_AN_RF2G4,
1101                                           AR9285_AN_RF2G4_DB2_3,
1102                                           AR9285_AN_RF2G4_DB2_3_S,
1103                                           db2[3]);
1104                 ath9k_hw_analog_shift_rmw(ah,
1105                                           AR9285_AN_RF2G4,
1106                                           AR9285_AN_RF2G4_DB2_4,
1107                                           AR9285_AN_RF2G4_DB2_4_S,
1108                                           db2[4]);
1109         }
1110
1111
1112         if (AR_SREV_9285_11(ah))
1113                 REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);
1114
1115         REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
1116                       pModal->switchSettling);
1117         REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
1118                       pModal->adcDesiredSize);
1119
1120         REG_WRITE(ah, AR_PHY_RF_CTL4,
1121                   SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) |
1122                   SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) |
1123                   SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON)  |
1124                   SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
1125
1126         REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
1127                       pModal->txEndToRxOn);
1128
1129         if (AR_SREV_9271_10(ah))
1130                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
1131                               pModal->txEndToRxOn);
1132         REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
1133                       pModal->thresh62);
1134         REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,
1135                       pModal->thresh62);
1136
1137         if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1138                                                 AR5416_EEP_MINOR_VER_2) {
1139                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_DATA_START,
1140                               pModal->txFrameToDataStart);
1141                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
1142                               pModal->txFrameToPaOn);
1143         }
1144
1145         if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1146                                                 AR5416_EEP_MINOR_VER_3) {
1147                 if (IS_CHAN_HT40(chan))
1148                         REG_RMW_FIELD(ah, AR_PHY_SETTLING,
1149                                       AR_PHY_SETTLING_SWITCH,
1150                                       pModal->swSettleHt40);
1151         }
1152 }
1153
1154 static u32 ath9k_hw_4k_get_eeprom_antenna_cfg(struct ath_hw *ah,
1155                                               struct ath9k_channel *chan)
1156 {
1157         struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
1158         struct modal_eep_4k_header *pModal = &eep->modalHeader;
1159
1160         return pModal->antCtrlCommon;
1161 }
1162
1163 static u8 ath9k_hw_4k_get_num_ant_config(struct ath_hw *ah,
1164                                          enum ieee80211_band freq_band)
1165 {
1166         return 1;
1167 }
1168
1169 static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1170 {
1171 #define EEP_MAP4K_SPURCHAN \
1172         (ah->eeprom.map4k.modalHeader.spurChans[i].spurChan)
1173         struct ath_common *common = ath9k_hw_common(ah);
1174
1175         u16 spur_val = AR_NO_SPUR;
1176
1177         ath_print(common, ATH_DBG_ANI,
1178                   "Getting spur idx %d is2Ghz. %d val %x\n",
1179                   i, is2GHz, ah->config.spurchans[i][is2GHz]);
1180
1181         switch (ah->config.spurmode) {
1182         case SPUR_DISABLE:
1183                 break;
1184         case SPUR_ENABLE_IOCTL:
1185                 spur_val = ah->config.spurchans[i][is2GHz];
1186                 ath_print(common, ATH_DBG_ANI,
1187                           "Getting spur val from new loc. %d\n", spur_val);
1188                 break;
1189         case SPUR_ENABLE_EEPROM:
1190                 spur_val = EEP_MAP4K_SPURCHAN;
1191                 break;
1192         }
1193
1194         return spur_val;
1195
1196 #undef EEP_MAP4K_SPURCHAN
1197 }
1198
1199 const struct eeprom_ops eep_4k_ops = {
1200         .check_eeprom           = ath9k_hw_4k_check_eeprom,
1201         .get_eeprom             = ath9k_hw_4k_get_eeprom,
1202         .fill_eeprom            = ath9k_hw_4k_fill_eeprom,
1203         .get_eeprom_ver         = ath9k_hw_4k_get_eeprom_ver,
1204         .get_eeprom_rev         = ath9k_hw_4k_get_eeprom_rev,
1205         .get_num_ant_config     = ath9k_hw_4k_get_num_ant_config,
1206         .get_eeprom_antenna_cfg = ath9k_hw_4k_get_eeprom_antenna_cfg,
1207         .set_board_values       = ath9k_hw_4k_set_board_values,
1208         .set_addac              = ath9k_hw_4k_set_addac,
1209         .set_txpower            = ath9k_hw_4k_set_txpower,
1210         .get_spur_channel       = ath9k_hw_4k_get_spur_channel
1211 };