drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2010 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/stringify.h>
  22 #include <linux/kernel.h>
  23 #include <linux/types.h>
  24 #include <linux/compiler.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/in.h>
  28 #include <linux/init.h>
  29 #include <linux/ioport.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/ethtool.h>
  35 #include <linux/mii.h>
  36 #include <linux/phy.h>
  37 #include <linux/brcmphy.h>
  38 #include <linux/if_vlan.h>
  39 #include <linux/ip.h>
  40 #include <linux/tcp.h>
  41 #include <linux/workqueue.h>
  42 #include <linux/prefetch.h>
  43 #include <linux/dma-mapping.h>
  44 #include <linux/firmware.h>
  45
  46 #include <net/checksum.h>
  47 #include <net/ip.h>
  48
  49 #include <asm/system.h>
  50 #include <asm/io.h>
  51 #include <asm/byteorder.h>
  52 #include <asm/uaccess.h>
  53
  54 #ifdef CONFIG_SPARC
  55 #include <asm/idprom.h>
  56 #include <asm/prom.h>
  57 #endif
  58
  59 #define BAR_0   0
  60 #define BAR_2   2
  61
  62 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  63 #define TG3_VLAN_TAG_USED 1
  64 #else
  65 #define TG3_VLAN_TAG_USED 0
  66 #endif
  67
  68 #include "tg3.h"
  69
  70 #define DRV_MODULE_NAME         "tg3"
  71 #define TG3_MAJ_NUM                     3
  72 #define TG3_MIN_NUM                     113
  73 #define DRV_MODULE_VERSION      \
  74         __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
  75 #define DRV_MODULE_RELDATE      "August 2, 2010"
  76
  77 #define TG3_DEF_MAC_MODE        0
  78 #define TG3_DEF_RX_MODE         0
  79 #define TG3_DEF_TX_MODE         0
  80 #define TG3_DEF_MSG_ENABLE        \
  81         (NETIF_MSG_DRV          | \
  82          NETIF_MSG_PROBE        | \
  83          NETIF_MSG_LINK         | \
  84          NETIF_MSG_TIMER        | \
  85          NETIF_MSG_IFDOWN       | \
  86          NETIF_MSG_IFUP         | \
  87          NETIF_MSG_RX_ERR       | \
  88          NETIF_MSG_TX_ERR)
  89
  90 /* length of time before we decide the hardware is borked,
  91  * and dev->tx_timeout() should be called to fix the problem
  92  */
  93 #define TG3_TX_TIMEOUT                  (5 * HZ)
  94
  95 /* hardware minimum and maximum for a single frame's data payload */
  96 #define TG3_MIN_MTU                     60
  97 #define TG3_MAX_MTU(tp) \
  98         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  99
 100 /* These numbers seem to be hard coded in the NIC firmware somehow.
 101  * You can't change the ring sizes, but you can change where you place
 102  * them in the NIC onboard memory.
 103  */
 104 #define TG3_RX_RING_SIZE                512
 105 #define TG3_DEF_RX_RING_PENDING         200
 106 #define TG3_RX_JUMBO_RING_SIZE          256
 107 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 108 #define TG3_RSS_INDIR_TBL_SIZE          128
 109
 110 /* Do not place this n-ring entries value into the tp struct itself,
 111  * we really want to expose these constants to GCC so that modulo et
 112  * al.  operations are done with shifts and masks instead of with
 113  * hw multiply/modulo instructions.  Another solution would be to
 114  * replace things like '% foo' with '& (foo - 1)'.
 115  */
 116 #define TG3_RX_RCB_RING_SIZE(tp)        \
 117         (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
 118           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
 119
 120 #define TG3_TX_RING_SIZE                512
 121 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 122
 123 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 124                                  TG3_RX_RING_SIZE)
 125 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
 126                                  TG3_RX_JUMBO_RING_SIZE)
 127 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 128                                  TG3_RX_RCB_RING_SIZE(tp))
 129 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 130                                  TG3_TX_RING_SIZE)
 131 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 132
 133 #define TG3_RX_DMA_ALIGN                16
 134 #define TG3_RX_HEADROOM                 ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
 135
 136 #define TG3_DMA_BYTE_ENAB               64
 137
 138 #define TG3_RX_STD_DMA_SZ               1536
 139 #define TG3_RX_JMB_DMA_SZ               9046
 140
 141 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 142
 143 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 144 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 145
 146 #define TG3_RX_STD_BUFF_RING_SIZE \
 147         (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
 148
 149 #define TG3_RX_JMB_BUFF_RING_SIZE \
 150         (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
 151
 152 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
 153  * that are at least dword aligned when used in PCIX mode.  The driver
 154  * works around this bug by double copying the packet.  This workaround
 155  * is built into the normal double copy length check for efficiency.
 156  *
 157  * However, the double copy is only necessary on those architectures
 158  * where unaligned memory accesses are inefficient.  For those architectures
 159  * where unaligned memory accesses incur little penalty, we can reintegrate
 160  * the 5701 in the normal rx path.  Doing so saves a device structure
 161  * dereference by hardcoding the double copy threshold in place.
 162  */
 163 #define TG3_RX_COPY_THRESHOLD           256
 164 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
 165         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
 166 #else
 167         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
 168 #endif
 169
 170 /* minimum number of free TX descriptors required to wake up TX process */
 171 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 172
 173 #define TG3_RAW_IP_ALIGN 2
 174
 175 /* number of ETHTOOL_GSTATS u64's */
 176 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 177
 178 #define TG3_NUM_TEST            6
 179
 180 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
 181
 182 #define FIRMWARE_TG3            "tigon/tg3.bin"
 183 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 184 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 185
 186 static char version[] __devinitdata =
 187         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
 188
 189 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 190 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 191 MODULE_LICENSE("GPL");
 192 MODULE_VERSION(DRV_MODULE_VERSION);
 193 MODULE_FIRMWARE(FIRMWARE_TG3);
 194 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 195 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 196
 197 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 198 module_param(tg3_debug, int, 0);
 199 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 200
 201 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 255         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 256         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 257         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 258         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 259         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 260         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 261         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 262         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 263         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 264         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 265         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
 266         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
 267         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
 268         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
 269         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
 270         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
 271         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
 272         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
 273         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
 274         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
 275         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 276         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 277         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 278         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 279         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 280         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 281         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 282         {}
 283 };
 284
 285 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 286
 287 static const struct {
 288         const char string[ETH_GSTRING_LEN];
 289 } ethtool_stats_keys[TG3_NUM_STATS] = {
 290         { "rx_octets" },
 291         { "rx_fragments" },
 292         { "rx_ucast_packets" },
 293         { "rx_mcast_packets" },
 294         { "rx_bcast_packets" },
 295         { "rx_fcs_errors" },
 296         { "rx_align_errors" },
 297         { "rx_xon_pause_rcvd" },
 298         { "rx_xoff_pause_rcvd" },
 299         { "rx_mac_ctrl_rcvd" },
 300         { "rx_xoff_entered" },
 301         { "rx_frame_too_long_errors" },
 302         { "rx_jabbers" },
 303         { "rx_undersize_packets" },
 304         { "rx_in_length_errors" },
 305         { "rx_out_length_errors" },
 306         { "rx_64_or_less_octet_packets" },
 307         { "rx_65_to_127_octet_packets" },
 308         { "rx_128_to_255_octet_packets" },
 309         { "rx_256_to_511_octet_packets" },
 310         { "rx_512_to_1023_octet_packets" },
 311         { "rx_1024_to_1522_octet_packets" },
 312         { "rx_1523_to_2047_octet_packets" },
 313         { "rx_2048_to_4095_octet_packets" },
 314         { "rx_4096_to_8191_octet_packets" },
 315         { "rx_8192_to_9022_octet_packets" },
 316
 317         { "tx_octets" },
 318         { "tx_collisions" },
 319
 320         { "tx_xon_sent" },
 321         { "tx_xoff_sent" },
 322         { "tx_flow_control" },
 323         { "tx_mac_errors" },
 324         { "tx_single_collisions" },
 325         { "tx_mult_collisions" },
 326         { "tx_deferred" },
 327         { "tx_excessive_collisions" },
 328         { "tx_late_collisions" },
 329         { "tx_collide_2times" },
 330         { "tx_collide_3times" },
 331         { "tx_collide_4times" },
 332         { "tx_collide_5times" },
 333         { "tx_collide_6times" },
 334         { "tx_collide_7times" },
 335         { "tx_collide_8times" },
 336         { "tx_collide_9times" },
 337         { "tx_collide_10times" },
 338         { "tx_collide_11times" },
 339         { "tx_collide_12times" },
 340         { "tx_collide_13times" },
 341         { "tx_collide_14times" },
 342         { "tx_collide_15times" },
 343         { "tx_ucast_packets" },
 344         { "tx_mcast_packets" },
 345         { "tx_bcast_packets" },
 346         { "tx_carrier_sense_errors" },
 347         { "tx_discards" },
 348         { "tx_errors" },
 349
 350         { "dma_writeq_full" },
 351         { "dma_write_prioq_full" },
 352         { "rxbds_empty" },
 353         { "rx_discards" },
 354         { "rx_errors" },
 355         { "rx_threshold_hit" },
 356
 357         { "dma_readq_full" },
 358         { "dma_read_prioq_full" },
 359         { "tx_comp_queue_full" },
 360
 361         { "ring_set_send_prod_index" },
 362         { "ring_status_update" },
 363         { "nic_irqs" },
 364         { "nic_avoided_irqs" },
 365         { "nic_tx_threshold_hit" }
 366 };
 367
 368 static const struct {
 369         const char string[ETH_GSTRING_LEN];
 370 } ethtool_test_keys[TG3_NUM_TEST] = {
 371         { "nvram test     (online) " },
 372         { "link test      (online) " },
 373         { "register test  (offline)" },
 374         { "memory test    (offline)" },
 375         { "loopback test  (offline)" },
 376         { "interrupt test (offline)" },
 377 };
 378
 379 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 380 {
 381         writel(val, tp->regs + off);
 382 }
 383
 384 static u32 tg3_read32(struct tg3 *tp, u32 off)
 385 {
 386         return readl(tp->regs + off);
 387 }
 388
 389 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 390 {
 391         writel(val, tp->aperegs + off);
 392 }
 393
 394 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 395 {
 396         return readl(tp->aperegs + off);
 397 }
 398
 399 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 400 {
 401         unsigned long flags;
 402
 403         spin_lock_irqsave(&tp->indirect_lock, flags);
 404         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 405         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 406         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 407 }
 408
 409 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 410 {
 411         writel(val, tp->regs + off);
 412         readl(tp->regs + off);
 413 }
 414
 415 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 416 {
 417         unsigned long flags;
 418         u32 val;
 419
 420         spin_lock_irqsave(&tp->indirect_lock, flags);
 421         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 422         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 423         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 424         return val;
 425 }
 426
 427 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 428 {
 429         unsigned long flags;
 430
 431         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 432                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 433                                        TG3_64BIT_REG_LOW, val);
 434                 return;
 435         }
 436         if (off == TG3_RX_STD_PROD_IDX_REG) {
 437                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 438                                        TG3_64BIT_REG_LOW, val);
 439                 return;
 440         }
 441
 442         spin_lock_irqsave(&tp->indirect_lock, flags);
 443         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 444         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 445         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 446
 447         /* In indirect mode when disabling interrupts, we also need
 448          * to clear the interrupt bit in the GRC local ctrl register.
 449          */
 450         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 451             (val == 0x1)) {
 452                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 453                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 454         }
 455 }
 456
 457 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 458 {
 459         unsigned long flags;
 460         u32 val;
 461
 462         spin_lock_irqsave(&tp->indirect_lock, flags);
 463         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 464         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 465         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 466         return val;
 467 }
 468
 469 /* usec_wait specifies the wait time in usec when writing to certain registers
 470  * where it is unsafe to read back the register without some delay.
 471  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 472  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 473  */
 474 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 475 {
 476         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 477             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 478                 /* Non-posted methods */
 479                 tp->write32(tp, off, val);
 480         else {
 481                 /* Posted method */
 482                 tg3_write32(tp, off, val);
 483                 if (usec_wait)
 484                         udelay(usec_wait);
 485                 tp->read32(tp, off);
 486         }
 487         /* Wait again after the read for the posted method to guarantee that
 488          * the wait time is met.
 489          */
 490         if (usec_wait)
 491                 udelay(usec_wait);
 492 }
 493
 494 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 495 {
 496         tp->write32_mbox(tp, off, val);
 497         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 498             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 499                 tp->read32_mbox(tp, off);
 500 }
 501
 502 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 503 {
 504         void __iomem *mbox = tp->regs + off;
 505         writel(val, mbox);
 506         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 507                 writel(val, mbox);
 508         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 509                 readl(mbox);
 510 }
 511
 512 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 513 {
 514         return readl(tp->regs + off + GRCMBOX_BASE);
 515 }
 516
 517 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 518 {
 519         writel(val, tp->regs + off + GRCMBOX_BASE);
 520 }
 521
 522 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
 523 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 524 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
 525 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
 526 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
 527
 528 #define tw32(reg, val)                  tp->write32(tp, reg, val)
 529 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
 530 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
 531 #define tr32(reg)                       tp->read32(tp, reg)
 532
 533 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 534 {
 535         unsigned long flags;
 536
 537         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 538             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 539                 return;
 540
 541         spin_lock_irqsave(&tp->indirect_lock, flags);
 542         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 543                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 544                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 545
 546                 /* Always leave this as zero. */
 547                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 548         } else {
 549                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 550                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 551
 552                 /* Always leave this as zero. */
 553                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 554         }
 555         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 556 }
 557
 558 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 559 {
 560         unsigned long flags;
 561
 562         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 563             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 564                 *val = 0;
 565                 return;
 566         }
 567
 568         spin_lock_irqsave(&tp->indirect_lock, flags);
 569         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 570                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 571                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 572
 573                 /* Always leave this as zero. */
 574                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 575         } else {
 576                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 577                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 578
 579                 /* Always leave this as zero. */
 580                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 581         }
 582         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 583 }
 584
 585 static void tg3_ape_lock_init(struct tg3 *tp)
 586 {
 587         int i;
 588         u32 regbase;
 589
 590         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 591                 regbase = TG3_APE_LOCK_GRANT;
 592         else
 593                 regbase = TG3_APE_PER_LOCK_GRANT;
 594
 595         /* Make sure the driver hasn't any stale locks. */
 596         for (i = 0; i < 8; i++)
 597                 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
 598 }
 599
 600 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 601 {
 602         int i, off;
 603         int ret = 0;
 604         u32 status, req, gnt;
 605
 606         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 607                 return 0;
 608
 609         switch (locknum) {
 610         case TG3_APE_LOCK_GRC:
 611         case TG3_APE_LOCK_MEM:
 612                 break;
 613         default:
 614                 return -EINVAL;
 615         }
 616
 617         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
 618                 req = TG3_APE_LOCK_REQ;
 619                 gnt = TG3_APE_LOCK_GRANT;
 620         } else {
 621                 req = TG3_APE_PER_LOCK_REQ;
 622                 gnt = TG3_APE_PER_LOCK_GRANT;
 623         }
 624
 625         off = 4 * locknum;
 626
 627         tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
 628
 629         /* Wait for up to 1 millisecond to acquire lock. */
 630         for (i = 0; i < 100; i++) {
 631                 status = tg3_ape_read32(tp, gnt + off);
 632                 if (status == APE_LOCK_GRANT_DRIVER)
 633                         break;
 634                 udelay(10);
 635         }
 636
 637         if (status != APE_LOCK_GRANT_DRIVER) {
 638                 /* Revoke the lock request. */
 639                 tg3_ape_write32(tp, gnt + off,
 640                                 APE_LOCK_GRANT_DRIVER);
 641
 642                 ret = -EBUSY;
 643         }
 644
 645         return ret;
 646 }
 647
 648 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 649 {
 650         u32 gnt;
 651
 652         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 653                 return;
 654
 655         switch (locknum) {
 656         case TG3_APE_LOCK_GRC:
 657         case TG3_APE_LOCK_MEM:
 658                 break;
 659         default:
 660                 return;
 661         }
 662
 663         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 664                 gnt = TG3_APE_LOCK_GRANT;
 665         else
 666                 gnt = TG3_APE_PER_LOCK_GRANT;
 667
 668         tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
 669 }
 670
 671 static void tg3_disable_ints(struct tg3 *tp)
 672 {
 673         int i;
 674
 675         tw32(TG3PCI_MISC_HOST_CTRL,
 676              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 677         for (i = 0; i < tp->irq_max; i++)
 678                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 679 }
 680
 681 static void tg3_enable_ints(struct tg3 *tp)
 682 {
 683         int i;
 684
 685         tp->irq_sync = 0;
 686         wmb();
 687
 688         tw32(TG3PCI_MISC_HOST_CTRL,
 689              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 690
 691         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
 692         for (i = 0; i < tp->irq_cnt; i++) {
 693                 struct tg3_napi *tnapi = &tp->napi[i];
 694
 695                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 696                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 697                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 698
 699                 tp->coal_now |= tnapi->coal_now;
 700         }
 701
 702         /* Force an initial interrupt */
 703         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 704             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 705                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 706         else
 707                 tw32(HOSTCC_MODE, tp->coal_now);
 708
 709         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
 710 }
 711
 712 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 713 {
 714         struct tg3 *tp = tnapi->tp;
 715         struct tg3_hw_status *sblk = tnapi->hw_status;
 716         unsigned int work_exists = 0;
 717
 718         /* check for phy events */
 719         if (!(tp->tg3_flags &
 720               (TG3_FLAG_USE_LINKCHG_REG |
 721                TG3_FLAG_POLL_SERDES))) {
 722                 if (sblk->status & SD_STATUS_LINK_CHG)
 723                         work_exists = 1;
 724         }
 725         /* check for RX/TX work to do */
 726         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 727             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
 728                 work_exists = 1;
 729
 730         return work_exists;
 731 }
 732
 733 /* tg3_int_reenable
 734  *  similar to tg3_enable_ints, but it accurately determines whether there
 735  *  is new work pending and can return without flushing the PIO write
 736  *  which reenables interrupts
 737  */
 738 static void tg3_int_reenable(struct tg3_napi *tnapi)
 739 {
 740         struct tg3 *tp = tnapi->tp;
 741
 742         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 743         mmiowb();
 744
 745         /* When doing tagged status, this work check is unnecessary.
 746          * The last_tag we write above tells the chip which piece of
 747          * work we've completed.
 748          */
 749         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 750             tg3_has_work(tnapi))
 751                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 752                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 753 }
 754
 755 static void tg3_napi_disable(struct tg3 *tp)
 756 {
 757         int i;
 758
 759         for (i = tp->irq_cnt - 1; i >= 0; i--)
 760                 napi_disable(&tp->napi[i].napi);
 761 }
 762
 763 static void tg3_napi_enable(struct tg3 *tp)
 764 {
 765         int i;
 766
 767         for (i = 0; i < tp->irq_cnt; i++)
 768                 napi_enable(&tp->napi[i].napi);
 769 }
 770
 771 static inline void tg3_netif_stop(struct tg3 *tp)
 772 {
 773         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 774         tg3_napi_disable(tp);
 775         netif_tx_disable(tp->dev);
 776 }
 777
 778 static inline void tg3_netif_start(struct tg3 *tp)
 779 {
 780         /* NOTE: unconditional netif_tx_wake_all_queues is only
 781          * appropriate so long as all callers are assured to
 782          * have free tx slots (such as after tg3_init_hw)
 783          */
 784         netif_tx_wake_all_queues(tp->dev);
 785
 786         tg3_napi_enable(tp);
 787         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
 788         tg3_enable_ints(tp);
 789 }
 790
 791 static void tg3_switch_clocks(struct tg3 *tp)
 792 {
 793         u32 clock_ctrl;
 794         u32 orig_clock_ctrl;
 795
 796         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 797             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 798                 return;
 799
 800         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 801
 802         orig_clock_ctrl = clock_ctrl;
 803         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 804                        CLOCK_CTRL_CLKRUN_OENABLE |
 805                        0x1f);
 806         tp->pci_clock_ctrl = clock_ctrl;
 807
 808         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 809                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 810                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 811                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 812                 }
 813         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 814                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 815                             clock_ctrl |
 816                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 817                             40);
 818                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 819                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 820                             40);
 821         }
 822         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 823 }
 824
 825 #define PHY_BUSY_LOOPS  5000
 826
 827 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 828 {
 829         u32 frame_val;
 830         unsigned int loops;
 831         int ret;
 832
 833         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 834                 tw32_f(MAC_MI_MODE,
 835                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 836                 udelay(80);
 837         }
 838
 839         *val = 0x0;
 840
 841         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 842                       MI_COM_PHY_ADDR_MASK);
 843         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 844                       MI_COM_REG_ADDR_MASK);
 845         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 846
 847         tw32_f(MAC_MI_COM, frame_val);
 848
 849         loops = PHY_BUSY_LOOPS;
 850         while (loops != 0) {
 851                 udelay(10);
 852                 frame_val = tr32(MAC_MI_COM);
 853
 854                 if ((frame_val & MI_COM_BUSY) == 0) {
 855                         udelay(5);
 856                         frame_val = tr32(MAC_MI_COM);
 857                         break;
 858                 }
 859                 loops -= 1;
 860         }
 861
 862         ret = -EBUSY;
 863         if (loops != 0) {
 864                 *val = frame_val & MI_COM_DATA_MASK;
 865                 ret = 0;
 866         }
 867
 868         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 869                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 870                 udelay(80);
 871         }
 872
 873         return ret;
 874 }
 875
 876 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 877 {
 878         u32 frame_val;
 879         unsigned int loops;
 880         int ret;
 881
 882         if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
 883             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 884                 return 0;
 885
 886         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 887                 tw32_f(MAC_MI_MODE,
 888                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 889                 udelay(80);
 890         }
 891
 892         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 893                       MI_COM_PHY_ADDR_MASK);
 894         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 895                       MI_COM_REG_ADDR_MASK);
 896         frame_val |= (val & MI_COM_DATA_MASK);
 897         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 898
 899         tw32_f(MAC_MI_COM, frame_val);
 900
 901         loops = PHY_BUSY_LOOPS;
 902         while (loops != 0) {
 903                 udelay(10);
 904                 frame_val = tr32(MAC_MI_COM);
 905                 if ((frame_val & MI_COM_BUSY) == 0) {
 906                         udelay(5);
 907                         frame_val = tr32(MAC_MI_COM);
 908                         break;
 909                 }
 910                 loops -= 1;
 911         }
 912
 913         ret = -EBUSY;
 914         if (loops != 0)
 915                 ret = 0;
 916
 917         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 918                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 919                 udelay(80);
 920         }
 921
 922         return ret;
 923 }
 924
 925 static int tg3_bmcr_reset(struct tg3 *tp)
 926 {
 927         u32 phy_control;
 928         int limit, err;
 929
 930         /* OK, reset it, and poll the BMCR_RESET bit until it
 931          * clears or we time out.
 932          */
 933         phy_control = BMCR_RESET;
 934         err = tg3_writephy(tp, MII_BMCR, phy_control);
 935         if (err != 0)
 936                 return -EBUSY;
 937
 938         limit = 5000;
 939         while (limit--) {
 940                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 941                 if (err != 0)
 942                         return -EBUSY;
 943
 944                 if ((phy_control & BMCR_RESET) == 0) {
 945                         udelay(40);
 946                         break;
 947                 }
 948                 udelay(10);
 949         }
 950         if (limit < 0)
 951                 return -EBUSY;
 952
 953         return 0;
 954 }
 955
 956 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 957 {
 958         struct tg3 *tp = bp->priv;
 959         u32 val;
 960
 961         spin_lock_bh(&tp->lock);
 962
 963         if (tg3_readphy(tp, reg, &val))
 964                 val = -EIO;
 965
 966         spin_unlock_bh(&tp->lock);
 967
 968         return val;
 969 }
 970
 971 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 972 {
 973         struct tg3 *tp = bp->priv;
 974         u32 ret = 0;
 975
 976         spin_lock_bh(&tp->lock);
 977
 978         if (tg3_writephy(tp, reg, val))
 979                 ret = -EIO;
 980
 981         spin_unlock_bh(&tp->lock);
 982
 983         return ret;
 984 }
 985
 986 static int tg3_mdio_reset(struct mii_bus *bp)
 987 {
 988         return 0;
 989 }
 990
 991 static void tg3_mdio_config_5785(struct tg3 *tp)
 992 {
 993         u32 val;
 994         struct phy_device *phydev;
 995
 996         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
 997         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 998         case PHY_ID_BCM50610:
 999         case PHY_ID_BCM50610M:
1000                 val = MAC_PHYCFG2_50610_LED_MODES;
1001                 break;
1002         case PHY_ID_BCMAC131:
1003                 val = MAC_PHYCFG2_AC131_LED_MODES;
1004                 break;
1005         case PHY_ID_RTL8211C:
1006                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1007                 break;
1008         case PHY_ID_RTL8201E:
1009                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1010                 break;
1011         default:
1012                 return;
1013         }
1014
1015         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1016                 tw32(MAC_PHYCFG2, val);
1017
1018                 val = tr32(MAC_PHYCFG1);
1019                 val &= ~(MAC_PHYCFG1_RGMII_INT |
1020                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1021                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1022                 tw32(MAC_PHYCFG1, val);
1023
1024                 return;
1025         }
1026
1027         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
1028                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1029                        MAC_PHYCFG2_FMODE_MASK_MASK |
1030                        MAC_PHYCFG2_GMODE_MASK_MASK |
1031                        MAC_PHYCFG2_ACT_MASK_MASK   |
1032                        MAC_PHYCFG2_QUAL_MASK_MASK |
1033                        MAC_PHYCFG2_INBAND_ENABLE;
1034
1035         tw32(MAC_PHYCFG2, val);
1036
1037         val = tr32(MAC_PHYCFG1);
1038         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1039                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1040         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1041                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1042                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1043                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1044                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1045         }
1046         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1047                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1048         tw32(MAC_PHYCFG1, val);
1049
1050         val = tr32(MAC_EXT_RGMII_MODE);
1051         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1052                  MAC_RGMII_MODE_RX_QUALITY |
1053                  MAC_RGMII_MODE_RX_ACTIVITY |
1054                  MAC_RGMII_MODE_RX_ENG_DET |
1055                  MAC_RGMII_MODE_TX_ENABLE |
1056                  MAC_RGMII_MODE_TX_LOWPWR |
1057                  MAC_RGMII_MODE_TX_RESET);
1058         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1059                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1060                         val |= MAC_RGMII_MODE_RX_INT_B |
1061                                MAC_RGMII_MODE_RX_QUALITY |
1062                                MAC_RGMII_MODE_RX_ACTIVITY |
1063                                MAC_RGMII_MODE_RX_ENG_DET;
1064                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1065                         val |= MAC_RGMII_MODE_TX_ENABLE |
1066                                MAC_RGMII_MODE_TX_LOWPWR |
1067                                MAC_RGMII_MODE_TX_RESET;
1068         }
1069         tw32(MAC_EXT_RGMII_MODE, val);
1070 }
1071
1072 static void tg3_mdio_start(struct tg3 *tp)
1073 {
1074         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1075         tw32_f(MAC_MI_MODE, tp->mi_mode);
1076         udelay(80);
1077
1078         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1079             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1080                 tg3_mdio_config_5785(tp);
1081 }
1082
1083 static int tg3_mdio_init(struct tg3 *tp)
1084 {
1085         int i;
1086         u32 reg;
1087         struct phy_device *phydev;
1088
1089         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1090             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
1091                 u32 is_serdes;
1092
1093                 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1094
1095                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1096                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1097                 else
1098                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1099                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1100                 if (is_serdes)
1101                         tp->phy_addr += 7;
1102         } else
1103                 tp->phy_addr = TG3_PHY_MII_ADDR;
1104
1105         tg3_mdio_start(tp);
1106
1107         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1108             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1109                 return 0;
1110
1111         tp->mdio_bus = mdiobus_alloc();
1112         if (tp->mdio_bus == NULL)
1113                 return -ENOMEM;
1114
1115         tp->mdio_bus->name     = "tg3 mdio bus";
1116         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1117                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1118         tp->mdio_bus->priv     = tp;
1119         tp->mdio_bus->parent   = &tp->pdev->dev;
1120         tp->mdio_bus->read     = &tg3_mdio_read;
1121         tp->mdio_bus->write    = &tg3_mdio_write;
1122         tp->mdio_bus->reset    = &tg3_mdio_reset;
1123         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1124         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1125
1126         for (i = 0; i < PHY_MAX_ADDR; i++)
1127                 tp->mdio_bus->irq[i] = PHY_POLL;
1128
1129         /* The bus registration will look for all the PHYs on the mdio bus.
1130          * Unfortunately, it does not ensure the PHY is powered up before
1131          * accessing the PHY ID registers.  A chip reset is the
1132          * quickest way to bring the device back to an operational state..
1133          */
1134         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1135                 tg3_bmcr_reset(tp);
1136
1137         i = mdiobus_register(tp->mdio_bus);
1138         if (i) {
1139                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1140                 mdiobus_free(tp->mdio_bus);
1141                 return i;
1142         }
1143
1144         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1145
1146         if (!phydev || !phydev->drv) {
1147                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1148                 mdiobus_unregister(tp->mdio_bus);
1149                 mdiobus_free(tp->mdio_bus);
1150                 return -ENODEV;
1151         }
1152
1153         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1154         case PHY_ID_BCM57780:
1155                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1156                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1157                 break;
1158         case PHY_ID_BCM50610:
1159         case PHY_ID_BCM50610M:
1160                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1161                                      PHY_BRCM_RX_REFCLK_UNUSED |
1162                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1163                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1164                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1165                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1166                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1167                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1168                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1169                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1170                 /* fallthru */
1171         case PHY_ID_RTL8211C:
1172                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1173                 break;
1174         case PHY_ID_RTL8201E:
1175         case PHY_ID_BCMAC131:
1176                 phydev->interface = PHY_INTERFACE_MODE_MII;
1177                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1178                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1179                 break;
1180         }
1181
1182         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1183
1184         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1185                 tg3_mdio_config_5785(tp);
1186
1187         return 0;
1188 }
1189
1190 static void tg3_mdio_fini(struct tg3 *tp)
1191 {
1192         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1193                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1194                 mdiobus_unregister(tp->mdio_bus);
1195                 mdiobus_free(tp->mdio_bus);
1196         }
1197 }
1198
1199 /* tp->lock is held. */
1200 static inline void tg3_generate_fw_event(struct tg3 *tp)
1201 {
1202         u32 val;
1203
1204         val = tr32(GRC_RX_CPU_EVENT);
1205         val |= GRC_RX_CPU_DRIVER_EVENT;
1206         tw32_f(GRC_RX_CPU_EVENT, val);
1207
1208         tp->last_event_jiffies = jiffies;
1209 }
1210
1211 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1212
1213 /* tp->lock is held. */
1214 static void tg3_wait_for_event_ack(struct tg3 *tp)
1215 {
1216         int i;
1217         unsigned int delay_cnt;
1218         long time_remain;
1219
1220         /* If enough time has passed, no wait is necessary. */
1221         time_remain = (long)(tp->last_event_jiffies + 1 +
1222                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1223                       (long)jiffies;
1224         if (time_remain < 0)
1225                 return;
1226
1227         /* Check if we can shorten the wait time. */
1228         delay_cnt = jiffies_to_usecs(time_remain);
1229         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1230                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1231         delay_cnt = (delay_cnt >> 3) + 1;
1232
1233         for (i = 0; i < delay_cnt; i++) {
1234                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1235                         break;
1236                 udelay(8);
1237         }
1238 }
1239
1240 /* tp->lock is held. */
1241 static void tg3_ump_link_report(struct tg3 *tp)
1242 {
1243         u32 reg;
1244         u32 val;
1245
1246         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1247             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1248                 return;
1249
1250         tg3_wait_for_event_ack(tp);
1251
1252         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1253
1254         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1255
1256         val = 0;
1257         if (!tg3_readphy(tp, MII_BMCR, &reg))
1258                 val = reg << 16;
1259         if (!tg3_readphy(tp, MII_BMSR, &reg))
1260                 val |= (reg & 0xffff);
1261         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1262
1263         val = 0;
1264         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1265                 val = reg << 16;
1266         if (!tg3_readphy(tp, MII_LPA, &reg))
1267                 val |= (reg & 0xffff);
1268         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1269
1270         val = 0;
1271         if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1272                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1273                         val = reg << 16;
1274                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1275                         val |= (reg & 0xffff);
1276         }
1277         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1278
1279         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1280                 val = reg << 16;
1281         else
1282                 val = 0;
1283         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1284
1285         tg3_generate_fw_event(tp);
1286 }
1287
1288 static void tg3_link_report(struct tg3 *tp)
1289 {
1290         if (!netif_carrier_ok(tp->dev)) {
1291                 netif_info(tp, link, tp->dev, "Link is down\n");
1292                 tg3_ump_link_report(tp);
1293         } else if (netif_msg_link(tp)) {
1294                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1295                             (tp->link_config.active_speed == SPEED_1000 ?
1296                              1000 :
1297                              (tp->link_config.active_speed == SPEED_100 ?
1298                               100 : 10)),
1299                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1300                              "full" : "half"));
1301
1302                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1303                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1304                             "on" : "off",
1305                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1306                             "on" : "off");
1307                 tg3_ump_link_report(tp);
1308         }
1309 }
1310
1311 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1312 {
1313         u16 miireg;
1314
1315         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1316                 miireg = ADVERTISE_PAUSE_CAP;
1317         else if (flow_ctrl & FLOW_CTRL_TX)
1318                 miireg = ADVERTISE_PAUSE_ASYM;
1319         else if (flow_ctrl & FLOW_CTRL_RX)
1320                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1321         else
1322                 miireg = 0;
1323
1324         return miireg;
1325 }
1326
1327 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1328 {
1329         u16 miireg;
1330
1331         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1332                 miireg = ADVERTISE_1000XPAUSE;
1333         else if (flow_ctrl & FLOW_CTRL_TX)
1334                 miireg = ADVERTISE_1000XPSE_ASYM;
1335         else if (flow_ctrl & FLOW_CTRL_RX)
1336                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1337         else
1338                 miireg = 0;
1339
1340         return miireg;
1341 }
1342
1343 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1344 {
1345         u8 cap = 0;
1346
1347         if (lcladv & ADVERTISE_1000XPAUSE) {
1348                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1349                         if (rmtadv & LPA_1000XPAUSE)
1350                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1351                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1352                                 cap = FLOW_CTRL_RX;
1353                 } else {
1354                         if (rmtadv & LPA_1000XPAUSE)
1355                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1356                 }
1357         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1358                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1359                         cap = FLOW_CTRL_TX;
1360         }
1361
1362         return cap;
1363 }
1364
1365 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1366 {
1367         u8 autoneg;
1368         u8 flowctrl = 0;
1369         u32 old_rx_mode = tp->rx_mode;
1370         u32 old_tx_mode = tp->tx_mode;
1371
1372         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1373                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1374         else
1375                 autoneg = tp->link_config.autoneg;
1376
1377         if (autoneg == AUTONEG_ENABLE &&
1378             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1379                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1380                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1381                 else
1382                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1383         } else
1384                 flowctrl = tp->link_config.flowctrl;
1385
1386         tp->link_config.active_flowctrl = flowctrl;
1387
1388         if (flowctrl & FLOW_CTRL_RX)
1389                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1390         else
1391                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1392
1393         if (old_rx_mode != tp->rx_mode)
1394                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1395
1396         if (flowctrl & FLOW_CTRL_TX)
1397                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1398         else
1399                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1400
1401         if (old_tx_mode != tp->tx_mode)
1402                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1403 }
1404
1405 static void tg3_adjust_link(struct net_device *dev)
1406 {
1407         u8 oldflowctrl, linkmesg = 0;
1408         u32 mac_mode, lcl_adv, rmt_adv;
1409         struct tg3 *tp = netdev_priv(dev);
1410         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1411
1412         spin_lock_bh(&tp->lock);
1413
1414         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1415                                     MAC_MODE_HALF_DUPLEX);
1416
1417         oldflowctrl = tp->link_config.active_flowctrl;
1418
1419         if (phydev->link) {
1420                 lcl_adv = 0;
1421                 rmt_adv = 0;
1422
1423                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1424                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1425                 else if (phydev->speed == SPEED_1000 ||
1426                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1427                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1428                 else
1429                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1430
1431                 if (phydev->duplex == DUPLEX_HALF)
1432                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1433                 else {
1434                         lcl_adv = tg3_advert_flowctrl_1000T(
1435                                   tp->link_config.flowctrl);
1436
1437                         if (phydev->pause)
1438                                 rmt_adv = LPA_PAUSE_CAP;
1439                         if (phydev->asym_pause)
1440                                 rmt_adv |= LPA_PAUSE_ASYM;
1441                 }
1442
1443                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1444         } else
1445                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1446
1447         if (mac_mode != tp->mac_mode) {
1448                 tp->mac_mode = mac_mode;
1449                 tw32_f(MAC_MODE, tp->mac_mode);
1450                 udelay(40);
1451         }
1452
1453         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1454                 if (phydev->speed == SPEED_10)
1455                         tw32(MAC_MI_STAT,
1456                              MAC_MI_STAT_10MBPS_MODE |
1457                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1458                 else
1459                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1460         }
1461
1462         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1463                 tw32(MAC_TX_LENGTHS,
1464                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1465                       (6 << TX_LENGTHS_IPG_SHIFT) |
1466                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1467         else
1468                 tw32(MAC_TX_LENGTHS,
1469                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1470                       (6 << TX_LENGTHS_IPG_SHIFT) |
1471                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1472
1473         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1474             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1475             phydev->speed != tp->link_config.active_speed ||
1476             phydev->duplex != tp->link_config.active_duplex ||
1477             oldflowctrl != tp->link_config.active_flowctrl)
1478                 linkmesg = 1;
1479
1480         tp->link_config.active_speed = phydev->speed;
1481         tp->link_config.active_duplex = phydev->duplex;
1482
1483         spin_unlock_bh(&tp->lock);
1484
1485         if (linkmesg)
1486                 tg3_link_report(tp);
1487 }
1488
1489 static int tg3_phy_init(struct tg3 *tp)
1490 {
1491         struct phy_device *phydev;
1492
1493         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1494                 return 0;
1495
1496         /* Bring the PHY back to a known state. */
1497         tg3_bmcr_reset(tp);
1498
1499         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1500
1501         /* Attach the MAC to the PHY. */
1502         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1503                              phydev->dev_flags, phydev->interface);
1504         if (IS_ERR(phydev)) {
1505                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1506                 return PTR_ERR(phydev);
1507         }
1508
1509         /* Mask with MAC supported features. */
1510         switch (phydev->interface) {
1511         case PHY_INTERFACE_MODE_GMII:
1512         case PHY_INTERFACE_MODE_RGMII:
1513                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1514                         phydev->supported &= (PHY_GBIT_FEATURES |
1515                                               SUPPORTED_Pause |
1516                                               SUPPORTED_Asym_Pause);
1517                         break;
1518                 }
1519                 /* fallthru */
1520         case PHY_INTERFACE_MODE_MII:
1521                 phydev->supported &= (PHY_BASIC_FEATURES |
1522                                       SUPPORTED_Pause |
1523                                       SUPPORTED_Asym_Pause);
1524                 break;
1525         default:
1526                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1527                 return -EINVAL;
1528         }
1529
1530         tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1531
1532         phydev->advertising = phydev->supported;
1533
1534         return 0;
1535 }
1536
1537 static void tg3_phy_start(struct tg3 *tp)
1538 {
1539         struct phy_device *phydev;
1540
1541         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1542                 return;
1543
1544         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1545
1546         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1547                 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1548                 phydev->speed = tp->link_config.orig_speed;
1549                 phydev->duplex = tp->link_config.orig_duplex;
1550                 phydev->autoneg = tp->link_config.orig_autoneg;
1551                 phydev->advertising = tp->link_config.orig_advertising;
1552         }
1553
1554         phy_start(phydev);
1555
1556         phy_start_aneg(phydev);
1557 }
1558
1559 static void tg3_phy_stop(struct tg3 *tp)
1560 {
1561         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1562                 return;
1563
1564         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1565 }
1566
1567 static void tg3_phy_fini(struct tg3 *tp)
1568 {
1569         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1570                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1571                 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1572         }
1573 }
1574
1575 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1576 {
1577         int err;
1578
1579         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1580         if (!err)
1581                 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1582
1583         return err;
1584 }
1585
1586 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1587 {
1588         u32 phytest;
1589
1590         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1591                 u32 phy;
1592
1593                 tg3_writephy(tp, MII_TG3_FET_TEST,
1594                              phytest | MII_TG3_FET_SHADOW_EN);
1595                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1596                         if (enable)
1597                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1598                         else
1599                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1600                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1601                 }
1602                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1603         }
1604 }
1605
1606 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1607 {
1608         u32 reg;
1609
1610         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1611             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1612               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1613              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1614                 return;
1615
1616         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1617                 tg3_phy_fet_toggle_apd(tp, enable);
1618                 return;
1619         }
1620
1621         reg = MII_TG3_MISC_SHDW_WREN |
1622               MII_TG3_MISC_SHDW_SCR5_SEL |
1623               MII_TG3_MISC_SHDW_SCR5_LPED |
1624               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1625               MII_TG3_MISC_SHDW_SCR5_SDTL |
1626               MII_TG3_MISC_SHDW_SCR5_C125OE;
1627         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1628                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1629
1630         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1631
1632
1633         reg = MII_TG3_MISC_SHDW_WREN |
1634               MII_TG3_MISC_SHDW_APD_SEL |
1635               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1636         if (enable)
1637                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1638
1639         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1640 }
1641
1642 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1643 {
1644         u32 phy;
1645
1646         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1647             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
1648                 return;
1649
1650         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1651                 u32 ephy;
1652
1653                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1654                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1655
1656                         tg3_writephy(tp, MII_TG3_FET_TEST,
1657                                      ephy | MII_TG3_FET_SHADOW_EN);
1658                         if (!tg3_readphy(tp, reg, &phy)) {
1659                                 if (enable)
1660                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1661                                 else
1662                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1663                                 tg3_writephy(tp, reg, phy);
1664                         }
1665                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1666                 }
1667         } else {
1668                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1669                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1670                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1671                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1672                         if (enable)
1673                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1674                         else
1675                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1676                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1677                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1678                 }
1679         }
1680 }
1681
1682 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1683 {
1684         u32 val;
1685
1686         if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1687                 return;
1688
1689         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1690             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1691                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1692                              (val | (1 << 15) | (1 << 4)));
1693 }
1694
1695 static void tg3_phy_apply_otp(struct tg3 *tp)
1696 {
1697         u32 otp, phy;
1698
1699         if (!tp->phy_otp)
1700                 return;
1701
1702         otp = tp->phy_otp;
1703
1704         /* Enable SM_DSP clock and tx 6dB coding. */
1705         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1706               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1707               MII_TG3_AUXCTL_ACTL_TX_6DB;
1708         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1709
1710         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1711         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1712         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1713
1714         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1715               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1716         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1717
1718         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1719         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1720         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1721
1722         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1723         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1724
1725         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1726         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1727
1728         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1729               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1730         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1731
1732         /* Turn off SM_DSP clock. */
1733         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1734               MII_TG3_AUXCTL_ACTL_TX_6DB;
1735         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1736 }
1737
1738 static int tg3_wait_macro_done(struct tg3 *tp)
1739 {
1740         int limit = 100;
1741
1742         while (limit--) {
1743                 u32 tmp32;
1744
1745                 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1746                         if ((tmp32 & 0x1000) == 0)
1747                                 break;
1748                 }
1749         }
1750         if (limit < 0)
1751                 return -EBUSY;
1752
1753         return 0;
1754 }
1755
1756 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1757 {
1758         static const u32 test_pat[4][6] = {
1759         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1760         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1761         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1762         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1763         };
1764         int chan;
1765
1766         for (chan = 0; chan < 4; chan++) {
1767                 int i;
1768
1769                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1770                              (chan * 0x2000) | 0x0200);
1771                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1772
1773                 for (i = 0; i < 6; i++)
1774                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1775                                      test_pat[chan][i]);
1776
1777                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1778                 if (tg3_wait_macro_done(tp)) {
1779                         *resetp = 1;
1780                         return -EBUSY;
1781                 }
1782
1783                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1784                              (chan * 0x2000) | 0x0200);
1785                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1786                 if (tg3_wait_macro_done(tp)) {
1787                         *resetp = 1;
1788                         return -EBUSY;
1789                 }
1790
1791                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1792                 if (tg3_wait_macro_done(tp)) {
1793                         *resetp = 1;
1794                         return -EBUSY;
1795                 }
1796
1797                 for (i = 0; i < 6; i += 2) {
1798                         u32 low, high;
1799
1800                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1801                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1802                             tg3_wait_macro_done(tp)) {
1803                                 *resetp = 1;
1804                                 return -EBUSY;
1805                         }
1806                         low &= 0x7fff;
1807                         high &= 0x000f;
1808                         if (low != test_pat[chan][i] ||
1809                             high != test_pat[chan][i+1]) {
1810                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1811                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1812                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1813
1814                                 return -EBUSY;
1815                         }
1816                 }
1817         }
1818
1819         return 0;
1820 }
1821
1822 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1823 {
1824         int chan;
1825
1826         for (chan = 0; chan < 4; chan++) {
1827                 int i;
1828
1829                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1830                              (chan * 0x2000) | 0x0200);
1831                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1832                 for (i = 0; i < 6; i++)
1833                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1834                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1835                 if (tg3_wait_macro_done(tp))
1836                         return -EBUSY;
1837         }
1838
1839         return 0;
1840 }
1841
1842 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1843 {
1844         u32 reg32, phy9_orig;
1845         int retries, do_phy_reset, err;
1846
1847         retries = 10;
1848         do_phy_reset = 1;
1849         do {
1850                 if (do_phy_reset) {
1851                         err = tg3_bmcr_reset(tp);
1852                         if (err)
1853                                 return err;
1854                         do_phy_reset = 0;
1855                 }
1856
1857                 /* Disable transmitter and interrupt.  */
1858                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1859                         continue;
1860
1861                 reg32 |= 0x3000;
1862                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1863
1864                 /* Set full-duplex, 1000 mbps.  */
1865                 tg3_writephy(tp, MII_BMCR,
1866                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1867
1868                 /* Set to master mode.  */
1869                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1870                         continue;
1871
1872                 tg3_writephy(tp, MII_TG3_CTRL,
1873                              (MII_TG3_CTRL_AS_MASTER |
1874                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1875
1876                 /* Enable SM_DSP_CLOCK and 6dB.  */
1877                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1878
1879                 /* Block the PHY control access.  */
1880                 tg3_phydsp_write(tp, 0x8005, 0x0800);
1881
1882                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1883                 if (!err)
1884                         break;
1885         } while (--retries);
1886
1887         err = tg3_phy_reset_chanpat(tp);
1888         if (err)
1889                 return err;
1890
1891         tg3_phydsp_write(tp, 0x8005, 0x0000);
1892
1893         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1894         tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1895
1896         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1897             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1898                 /* Set Extended packet length bit for jumbo frames */
1899                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1900         } else {
1901                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1902         }
1903
1904         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1905
1906         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1907                 reg32 &= ~0x3000;
1908                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1909         } else if (!err)
1910                 err = -EBUSY;
1911
1912         return err;
1913 }
1914
1915 /* This will reset the tigon3 PHY if there is no valid
1916  * link unless the FORCE argument is non-zero.
1917  */
1918 static int tg3_phy_reset(struct tg3 *tp)
1919 {
1920         u32 val, cpmuctrl;
1921         int err;
1922
1923         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1924                 val = tr32(GRC_MISC_CFG);
1925                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1926                 udelay(40);
1927         }
1928         err  = tg3_readphy(tp, MII_BMSR, &val);
1929         err |= tg3_readphy(tp, MII_BMSR, &val);
1930         if (err != 0)
1931                 return -EBUSY;
1932
1933         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1934                 netif_carrier_off(tp->dev);
1935                 tg3_link_report(tp);
1936         }
1937
1938         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1939             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1940             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1941                 err = tg3_phy_reset_5703_4_5(tp);
1942                 if (err)
1943                         return err;
1944                 goto out;
1945         }
1946
1947         cpmuctrl = 0;
1948         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1949             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1950                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1951                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1952                         tw32(TG3_CPMU_CTRL,
1953                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1954         }
1955
1956         err = tg3_bmcr_reset(tp);
1957         if (err)
1958                 return err;
1959
1960         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1961                 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1962                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
1963
1964                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1965         }
1966
1967         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1968             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1969                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1970                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1971                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1972                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1973                         udelay(40);
1974                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1975                 }
1976         }
1977
1978         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1979              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1980             (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
1981                 return 0;
1982
1983         tg3_phy_apply_otp(tp);
1984
1985         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
1986                 tg3_phy_toggle_apd(tp, true);
1987         else
1988                 tg3_phy_toggle_apd(tp, false);
1989
1990 out:
1991         if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) {
1992                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1993                 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
1994                 tg3_phydsp_write(tp, 0x000a, 0x0323);
1995                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1996         }
1997         if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
1998                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
1999                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2000         }
2001         if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2002                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2003                 tg3_phydsp_write(tp, 0x000a, 0x310b);
2004                 tg3_phydsp_write(tp, 0x201f, 0x9506);
2005                 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2006                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2007         } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2008                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2009                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2010                 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2011                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2012                         tg3_writephy(tp, MII_TG3_TEST1,
2013                                      MII_TG3_TEST1_TRIM_EN | 0x4);
2014                 } else
2015                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2016                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2017         }
2018         /* Set Extended packet length bit (bit 14) on all chips that */
2019         /* support jumbo frames */
2020         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2021                 /* Cannot do read-modify-write on 5401 */
2022                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2023         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2024                 /* Set bit 14 with read-modify-write to preserve other bits */
2025                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2026                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
2027                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val | 0x4000);
2028         }
2029
2030         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2031          * jumbo frames transmission.
2032          */
2033         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2034                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2035                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2036                                      val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2037         }
2038
2039         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2040                 /* adjust output voltage */
2041                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2042         }
2043
2044         tg3_phy_toggle_automdix(tp, 1);
2045         tg3_phy_set_wirespeed(tp);
2046         return 0;
2047 }
2048
2049 static void tg3_frob_aux_power(struct tg3 *tp)
2050 {
2051         struct tg3 *tp_peer = tp;
2052
2053         /* The GPIOs do something completely different on 57765. */
2054         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2055             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2056             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2057                 return;
2058
2059         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2060             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2061             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2062                 struct net_device *dev_peer;
2063
2064                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2065                 /* remove_one() may have been run on the peer. */
2066                 if (!dev_peer)
2067                         tp_peer = tp;
2068                 else
2069                         tp_peer = netdev_priv(dev_peer);
2070         }
2071
2072         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2073             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2074             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2075             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2076                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2077                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2078                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2079                                     (GRC_LCLCTRL_GPIO_OE0 |
2080                                      GRC_LCLCTRL_GPIO_OE1 |
2081                                      GRC_LCLCTRL_GPIO_OE2 |
2082                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2083                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2084                                     100);
2085                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2086                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2087                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2088                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2089                                              GRC_LCLCTRL_GPIO_OE1 |
2090                                              GRC_LCLCTRL_GPIO_OE2 |
2091                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2092                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2093                                              tp->grc_local_ctrl;
2094                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2095
2096                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2097                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2098
2099                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2100                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2101                 } else {
2102                         u32 no_gpio2;
2103                         u32 grc_local_ctrl = 0;
2104
2105                         if (tp_peer != tp &&
2106                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2107                                 return;
2108
2109                         /* Workaround to prevent overdrawing Amps. */
2110                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2111                             ASIC_REV_5714) {
2112                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2113                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2114                                             grc_local_ctrl, 100);
2115                         }
2116
2117                         /* On 5753 and variants, GPIO2 cannot be used. */
2118                         no_gpio2 = tp->nic_sram_data_cfg &
2119                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2120
2121                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2122                                          GRC_LCLCTRL_GPIO_OE1 |
2123                                          GRC_LCLCTRL_GPIO_OE2 |
2124                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2125                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2126                         if (no_gpio2) {
2127                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2128                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2129                         }
2130                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2131                                                     grc_local_ctrl, 100);
2132
2133                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2134
2135                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2136                                                     grc_local_ctrl, 100);
2137
2138                         if (!no_gpio2) {
2139                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2140                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2141                                             grc_local_ctrl, 100);
2142                         }
2143                 }
2144         } else {
2145                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2146                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2147                         if (tp_peer != tp &&
2148                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2149                                 return;
2150
2151                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2152                                     (GRC_LCLCTRL_GPIO_OE1 |
2153                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2154
2155                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2156                                     GRC_LCLCTRL_GPIO_OE1, 100);
2157
2158                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2159                                     (GRC_LCLCTRL_GPIO_OE1 |
2160                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2161                 }
2162         }
2163 }
2164
2165 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2166 {
2167         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2168                 return 1;
2169         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2170                 if (speed != SPEED_10)
2171                         return 1;
2172         } else if (speed == SPEED_10)
2173                 return 1;
2174
2175         return 0;
2176 }
2177
2178 static int tg3_setup_phy(struct tg3 *, int);
2179
2180 #define RESET_KIND_SHUTDOWN     0
2181 #define RESET_KIND_INIT         1
2182 #define RESET_KIND_SUSPEND      2
2183
2184 static void tg3_write_sig_post_reset(struct tg3 *, int);
2185 static int tg3_halt_cpu(struct tg3 *, u32);
2186
2187 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2188 {
2189         u32 val;
2190
2191         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2192                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2193                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2194                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2195
2196                         sg_dig_ctrl |=
2197                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2198                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2199                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2200                 }
2201                 return;
2202         }
2203
2204         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2205                 tg3_bmcr_reset(tp);
2206                 val = tr32(GRC_MISC_CFG);
2207                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2208                 udelay(40);
2209                 return;
2210         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2211                 u32 phytest;
2212                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2213                         u32 phy;
2214
2215                         tg3_writephy(tp, MII_ADVERTISE, 0);
2216                         tg3_writephy(tp, MII_BMCR,
2217                                      BMCR_ANENABLE | BMCR_ANRESTART);
2218
2219                         tg3_writephy(tp, MII_TG3_FET_TEST,
2220                                      phytest | MII_TG3_FET_SHADOW_EN);
2221                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2222                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2223                                 tg3_writephy(tp,
2224                                              MII_TG3_FET_SHDW_AUXMODE4,
2225                                              phy);
2226                         }
2227                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2228                 }
2229                 return;
2230         } else if (do_low_power) {
2231                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2232                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2233
2234                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2235                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2236                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2237                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2238                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2239         }
2240
2241         /* The PHY should not be powered down on some chips because
2242          * of bugs.
2243          */
2244         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2245             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2246             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2247              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2248                 return;
2249
2250         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2251             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2252                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2253                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2254                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2255                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2256         }
2257
2258         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2259 }
2260
2261 /* tp->lock is held. */
2262 static int tg3_nvram_lock(struct tg3 *tp)
2263 {
2264         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2265                 int i;
2266
2267                 if (tp->nvram_lock_cnt == 0) {
2268                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2269                         for (i = 0; i < 8000; i++) {
2270                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2271                                         break;
2272                                 udelay(20);
2273                         }
2274                         if (i == 8000) {
2275                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2276                                 return -ENODEV;
2277                         }
2278                 }
2279                 tp->nvram_lock_cnt++;
2280         }
2281         return 0;
2282 }
2283
2284 /* tp->lock is held. */
2285 static void tg3_nvram_unlock(struct tg3 *tp)
2286 {
2287         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2288                 if (tp->nvram_lock_cnt > 0)
2289                         tp->nvram_lock_cnt--;
2290                 if (tp->nvram_lock_cnt == 0)
2291                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2292         }
2293 }
2294
2295 /* tp->lock is held. */
2296 static void tg3_enable_nvram_access(struct tg3 *tp)
2297 {
2298         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2299             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2300                 u32 nvaccess = tr32(NVRAM_ACCESS);
2301
2302                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2303         }
2304 }
2305
2306 /* tp->lock is held. */
2307 static void tg3_disable_nvram_access(struct tg3 *tp)
2308 {
2309         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2310             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2311                 u32 nvaccess = tr32(NVRAM_ACCESS);
2312
2313                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2314         }
2315 }
2316
2317 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2318                                         u32 offset, u32 *val)
2319 {
2320         u32 tmp;
2321         int i;
2322
2323         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2324                 return -EINVAL;
2325
2326         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2327                                         EEPROM_ADDR_DEVID_MASK |
2328                                         EEPROM_ADDR_READ);
2329         tw32(GRC_EEPROM_ADDR,
2330              tmp |
2331              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2332              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2333               EEPROM_ADDR_ADDR_MASK) |
2334              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2335
2336         for (i = 0; i < 1000; i++) {
2337                 tmp = tr32(GRC_EEPROM_ADDR);
2338
2339                 if (tmp & EEPROM_ADDR_COMPLETE)
2340                         break;
2341                 msleep(1);
2342         }
2343         if (!(tmp & EEPROM_ADDR_COMPLETE))
2344                 return -EBUSY;
2345
2346         tmp = tr32(GRC_EEPROM_DATA);
2347
2348         /*
2349          * The data will always be opposite the native endian
2350          * format.  Perform a blind byteswap to compensate.
2351          */
2352         *val = swab32(tmp);
2353
2354         return 0;
2355 }
2356
2357 #define NVRAM_CMD_TIMEOUT 10000
2358
2359 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2360 {
2361         int i;
2362
2363         tw32(NVRAM_CMD, nvram_cmd);
2364         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2365                 udelay(10);
2366                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2367                         udelay(10);
2368                         break;
2369                 }
2370         }
2371
2372         if (i == NVRAM_CMD_TIMEOUT)
2373                 return -EBUSY;
2374
2375         return 0;
2376 }
2377
2378 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2379 {
2380         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2381             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2382             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2383            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2384             (tp->nvram_jedecnum == JEDEC_ATMEL))
2385
2386                 addr = ((addr / tp->nvram_pagesize) <<
2387                         ATMEL_AT45DB0X1B_PAGE_POS) +
2388                        (addr % tp->nvram_pagesize);
2389
2390         return addr;
2391 }
2392
2393 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2394 {
2395         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2396             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2397             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2398            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2399             (tp->nvram_jedecnum == JEDEC_ATMEL))
2400
2401                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2402                         tp->nvram_pagesize) +
2403                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2404
2405         return addr;
2406 }
2407
2408 /* NOTE: Data read in from NVRAM is byteswapped according to
2409  * the byteswapping settings for all other register accesses.
2410  * tg3 devices are BE devices, so on a BE machine, the data
2411  * returned will be exactly as it is seen in NVRAM.  On a LE
2412  * machine, the 32-bit value will be byteswapped.
2413  */
2414 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2415 {
2416         int ret;
2417
2418         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2419                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2420
2421         offset = tg3_nvram_phys_addr(tp, offset);
2422
2423         if (offset > NVRAM_ADDR_MSK)
2424                 return -EINVAL;
2425
2426         ret = tg3_nvram_lock(tp);
2427         if (ret)
2428                 return ret;
2429
2430         tg3_enable_nvram_access(tp);
2431
2432         tw32(NVRAM_ADDR, offset);
2433         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2434                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2435
2436         if (ret == 0)
2437                 *val = tr32(NVRAM_RDDATA);
2438
2439         tg3_disable_nvram_access(tp);
2440
2441         tg3_nvram_unlock(tp);
2442
2443         return ret;
2444 }
2445
2446 /* Ensures NVRAM data is in bytestream format. */
2447 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2448 {
2449         u32 v;
2450         int res = tg3_nvram_read(tp, offset, &v);
2451         if (!res)
2452                 *val = cpu_to_be32(v);
2453         return res;
2454 }
2455
2456 /* tp->lock is held. */
2457 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2458 {
2459         u32 addr_high, addr_low;
2460         int i;
2461
2462         addr_high = ((tp->dev->dev_addr[0] << 8) |
2463                      tp->dev->dev_addr[1]);
2464         addr_low = ((tp->dev->dev_addr[2] << 24) |
2465                     (tp->dev->dev_addr[3] << 16) |
2466                     (tp->dev->dev_addr[4] <<  8) |
2467                     (tp->dev->dev_addr[5] <<  0));
2468         for (i = 0; i < 4; i++) {
2469                 if (i == 1 && skip_mac_1)
2470                         continue;
2471                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2472                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2473         }
2474
2475         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2476             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2477                 for (i = 0; i < 12; i++) {
2478                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2479                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2480                 }
2481         }
2482
2483         addr_high = (tp->dev->dev_addr[0] +
2484                      tp->dev->dev_addr[1] +
2485                      tp->dev->dev_addr[2] +
2486                      tp->dev->dev_addr[3] +
2487                      tp->dev->dev_addr[4] +
2488                      tp->dev->dev_addr[5]) &
2489                 TX_BACKOFF_SEED_MASK;
2490         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2491 }
2492
2493 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2494 {
2495         u32 misc_host_ctrl;
2496         bool device_should_wake, do_low_power;
2497
2498         /* Make sure register accesses (indirect or otherwise)
2499          * will function correctly.
2500          */
2501         pci_write_config_dword(tp->pdev,
2502                                TG3PCI_MISC_HOST_CTRL,
2503                                tp->misc_host_ctrl);
2504
2505         switch (state) {
2506         case PCI_D0:
2507                 pci_enable_wake(tp->pdev, state, false);
2508                 pci_set_power_state(tp->pdev, PCI_D0);
2509
2510                 /* Switch out of Vaux if it is a NIC */
2511                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2512                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2513
2514                 return 0;
2515
2516         case PCI_D1:
2517         case PCI_D2:
2518         case PCI_D3hot:
2519                 break;
2520
2521         default:
2522                 netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
2523                            state);
2524                 return -EINVAL;
2525         }
2526
2527         /* Restore the CLKREQ setting. */
2528         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2529                 u16 lnkctl;
2530
2531                 pci_read_config_word(tp->pdev,
2532                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2533                                      &lnkctl);
2534                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2535                 pci_write_config_word(tp->pdev,
2536                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2537                                       lnkctl);
2538         }
2539
2540         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2541         tw32(TG3PCI_MISC_HOST_CTRL,
2542              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2543
2544         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2545                              device_may_wakeup(&tp->pdev->dev) &&
2546                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2547
2548         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2549                 do_low_power = false;
2550                 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
2551                     !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2552                         struct phy_device *phydev;
2553                         u32 phyid, advertising;
2554
2555                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2556
2557                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2558
2559                         tp->link_config.orig_speed = phydev->speed;
2560                         tp->link_config.orig_duplex = phydev->duplex;
2561                         tp->link_config.orig_autoneg = phydev->autoneg;
2562                         tp->link_config.orig_advertising = phydev->advertising;
2563
2564                         advertising = ADVERTISED_TP |
2565                                       ADVERTISED_Pause |
2566                                       ADVERTISED_Autoneg |
2567                                       ADVERTISED_10baseT_Half;
2568
2569                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2570                             device_should_wake) {
2571                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2572                                         advertising |=
2573                                                 ADVERTISED_100baseT_Half |
2574                                                 ADVERTISED_100baseT_Full |
2575                                                 ADVERTISED_10baseT_Full;
2576                                 else
2577                                         advertising |= ADVERTISED_10baseT_Full;
2578                         }
2579
2580                         phydev->advertising = advertising;
2581
2582                         phy_start_aneg(phydev);
2583
2584                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2585                         if (phyid != PHY_ID_BCMAC131) {
2586                                 phyid &= PHY_BCM_OUI_MASK;
2587                                 if (phyid == PHY_BCM_OUI_1 ||
2588                                     phyid == PHY_BCM_OUI_2 ||
2589                                     phyid == PHY_BCM_OUI_3)
2590                                         do_low_power = true;
2591                         }
2592                 }
2593         } else {
2594                 do_low_power = true;
2595
2596                 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2597                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2598                         tp->link_config.orig_speed = tp->link_config.speed;
2599                         tp->link_config.orig_duplex = tp->link_config.duplex;
2600                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2601                 }
2602
2603                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
2604                         tp->link_config.speed = SPEED_10;
2605                         tp->link_config.duplex = DUPLEX_HALF;
2606                         tp->link_config.autoneg = AUTONEG_ENABLE;
2607                         tg3_setup_phy(tp, 0);
2608                 }
2609         }
2610
2611         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2612                 u32 val;
2613
2614                 val = tr32(GRC_VCPU_EXT_CTRL);
2615                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2616         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2617                 int i;
2618                 u32 val;
2619
2620                 for (i = 0; i < 200; i++) {
2621                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2622                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2623                                 break;
2624                         msleep(1);
2625                 }
2626         }
2627         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2628                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2629                                                      WOL_DRV_STATE_SHUTDOWN |
2630                                                      WOL_DRV_WOL |
2631                                                      WOL_SET_MAGIC_PKT);
2632
2633         if (device_should_wake) {
2634                 u32 mac_mode;
2635
2636                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
2637                         if (do_low_power) {
2638                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2639                                 udelay(40);
2640                         }
2641
2642                         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
2643                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2644                         else
2645                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2646
2647                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2648                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2649                             ASIC_REV_5700) {
2650                                 u32 speed = (tp->tg3_flags &
2651                                              TG3_FLAG_WOL_SPEED_100MB) ?
2652                                              SPEED_100 : SPEED_10;
2653                                 if (tg3_5700_link_polarity(tp, speed))
2654                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2655                                 else
2656                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2657                         }
2658                 } else {
2659                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2660                 }
2661
2662                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2663                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2664
2665                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2666                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2667                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2668                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2669                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2670                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2671
2672                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2673                         mac_mode |= tp->mac_mode &
2674                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2675                         if (mac_mode & MAC_MODE_APE_TX_EN)
2676                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2677                 }
2678
2679                 tw32_f(MAC_MODE, mac_mode);
2680                 udelay(100);
2681
2682                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2683                 udelay(10);
2684         }
2685
2686         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2687             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2688              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2689                 u32 base_val;
2690
2691                 base_val = tp->pci_clock_ctrl;
2692                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2693                              CLOCK_CTRL_TXCLK_DISABLE);
2694
2695                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2696                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2697         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2698                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2699                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2700                 /* do nothing */
2701         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2702                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2703                 u32 newbits1, newbits2;
2704
2705                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2706                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2707                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2708                                     CLOCK_CTRL_TXCLK_DISABLE |
2709                                     CLOCK_CTRL_ALTCLK);
2710                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2711                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2712                         newbits1 = CLOCK_CTRL_625_CORE;
2713                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2714                 } else {
2715                         newbits1 = CLOCK_CTRL_ALTCLK;
2716                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2717                 }
2718
2719                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2720                             40);
2721
2722                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2723                             40);
2724
2725                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2726                         u32 newbits3;
2727
2728                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2729                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2730                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2731                                             CLOCK_CTRL_TXCLK_DISABLE |
2732                                             CLOCK_CTRL_44MHZ_CORE);
2733                         } else {
2734                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2735                         }
2736
2737                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2738                                     tp->pci_clock_ctrl | newbits3, 40);
2739                 }
2740         }
2741
2742         if (!(device_should_wake) &&
2743             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2744                 tg3_power_down_phy(tp, do_low_power);
2745
2746         tg3_frob_aux_power(tp);
2747
2748         /* Workaround for unstable PLL clock */
2749         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2750             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2751                 u32 val = tr32(0x7d00);
2752
2753                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2754                 tw32(0x7d00, val);
2755                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2756                         int err;
2757
2758                         err = tg3_nvram_lock(tp);
2759                         tg3_halt_cpu(tp, RX_CPU_BASE);
2760                         if (!err)
2761                                 tg3_nvram_unlock(tp);
2762                 }
2763         }
2764
2765         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2766
2767         if (device_should_wake)
2768                 pci_enable_wake(tp->pdev, state, true);
2769
2770         /* Finally, set the new power state. */
2771         pci_set_power_state(tp->pdev, state);
2772
2773         return 0;
2774 }
2775
2776 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2777 {
2778         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2779         case MII_TG3_AUX_STAT_10HALF:
2780                 *speed = SPEED_10;
2781                 *duplex = DUPLEX_HALF;
2782                 break;
2783
2784         case MII_TG3_AUX_STAT_10FULL:
2785                 *speed = SPEED_10;
2786                 *duplex = DUPLEX_FULL;
2787                 break;
2788
2789         case MII_TG3_AUX_STAT_100HALF:
2790                 *speed = SPEED_100;
2791                 *duplex = DUPLEX_HALF;
2792                 break;
2793
2794         case MII_TG3_AUX_STAT_100FULL:
2795                 *speed = SPEED_100;
2796                 *duplex = DUPLEX_FULL;
2797                 break;
2798
2799         case MII_TG3_AUX_STAT_1000HALF:
2800                 *speed = SPEED_1000;
2801                 *duplex = DUPLEX_HALF;
2802                 break;
2803
2804         case MII_TG3_AUX_STAT_1000FULL:
2805                 *speed = SPEED_1000;
2806                 *duplex = DUPLEX_FULL;
2807                 break;
2808
2809         default:
2810                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2811                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2812                                  SPEED_10;
2813                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2814                                   DUPLEX_HALF;
2815                         break;
2816                 }
2817                 *speed = SPEED_INVALID;
2818                 *duplex = DUPLEX_INVALID;
2819                 break;
2820         }
2821 }
2822
2823 static void tg3_phy_copper_begin(struct tg3 *tp)
2824 {
2825         u32 new_adv;
2826         int i;
2827
2828         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2829                 /* Entering low power mode.  Disable gigabit and
2830                  * 100baseT advertisements.
2831                  */
2832                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2833
2834                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2835                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2836                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2837                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2838
2839                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2840         } else if (tp->link_config.speed == SPEED_INVALID) {
2841                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
2842                         tp->link_config.advertising &=
2843                                 ~(ADVERTISED_1000baseT_Half |
2844                                   ADVERTISED_1000baseT_Full);
2845
2846                 new_adv = ADVERTISE_CSMA;
2847                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2848                         new_adv |= ADVERTISE_10HALF;
2849                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2850                         new_adv |= ADVERTISE_10FULL;
2851                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2852                         new_adv |= ADVERTISE_100HALF;
2853                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2854                         new_adv |= ADVERTISE_100FULL;
2855
2856                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2857
2858                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2859
2860                 if (tp->link_config.advertising &
2861                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2862                         new_adv = 0;
2863                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2864                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2865                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2866                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2867                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) &&
2868                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2869                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2870                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2871                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2872                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2873                 } else {
2874                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2875                 }
2876         } else {
2877                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2878                 new_adv |= ADVERTISE_CSMA;
2879
2880                 /* Asking for a specific link mode. */
2881                 if (tp->link_config.speed == SPEED_1000) {
2882                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2883
2884                         if (tp->link_config.duplex == DUPLEX_FULL)
2885                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2886                         else
2887                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2888                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2889                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2890                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2891                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2892                 } else {
2893                         if (tp->link_config.speed == SPEED_100) {
2894                                 if (tp->link_config.duplex == DUPLEX_FULL)
2895                                         new_adv |= ADVERTISE_100FULL;
2896                                 else
2897                                         new_adv |= ADVERTISE_100HALF;
2898                         } else {
2899                                 if (tp->link_config.duplex == DUPLEX_FULL)
2900                                         new_adv |= ADVERTISE_10FULL;
2901                                 else
2902                                         new_adv |= ADVERTISE_10HALF;
2903                         }
2904                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2905
2906                         new_adv = 0;
2907                 }
2908
2909                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2910         }
2911
2912         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2913             tp->link_config.speed != SPEED_INVALID) {
2914                 u32 bmcr, orig_bmcr;
2915
2916                 tp->link_config.active_speed = tp->link_config.speed;
2917                 tp->link_config.active_duplex = tp->link_config.duplex;
2918
2919                 bmcr = 0;
2920                 switch (tp->link_config.speed) {
2921                 default:
2922                 case SPEED_10:
2923                         break;
2924
2925                 case SPEED_100:
2926                         bmcr |= BMCR_SPEED100;
2927                         break;
2928
2929                 case SPEED_1000:
2930                         bmcr |= TG3_BMCR_SPEED1000;
2931                         break;
2932                 }
2933
2934                 if (tp->link_config.duplex == DUPLEX_FULL)
2935                         bmcr |= BMCR_FULLDPLX;
2936
2937                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2938                     (bmcr != orig_bmcr)) {
2939                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2940                         for (i = 0; i < 1500; i++) {
2941                                 u32 tmp;
2942
2943                                 udelay(10);
2944                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2945                                     tg3_readphy(tp, MII_BMSR, &tmp))
2946                                         continue;
2947                                 if (!(tmp & BMSR_LSTATUS)) {
2948                                         udelay(40);
2949                                         break;
2950                                 }
2951                         }
2952                         tg3_writephy(tp, MII_BMCR, bmcr);
2953                         udelay(40);
2954                 }
2955         } else {
2956                 tg3_writephy(tp, MII_BMCR,
2957                              BMCR_ANENABLE | BMCR_ANRESTART);
2958         }
2959 }
2960
2961 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2962 {
2963         int err;
2964
2965         /* Turn off tap power management. */
2966         /* Set Extended packet length bit */
2967         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2968
2969         err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
2970         err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
2971         err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
2972         err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
2973         err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
2974
2975         udelay(40);
2976
2977         return err;
2978 }
2979
2980 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2981 {
2982         u32 adv_reg, all_mask = 0;
2983
2984         if (mask & ADVERTISED_10baseT_Half)
2985                 all_mask |= ADVERTISE_10HALF;
2986         if (mask & ADVERTISED_10baseT_Full)
2987                 all_mask |= ADVERTISE_10FULL;
2988         if (mask & ADVERTISED_100baseT_Half)
2989                 all_mask |= ADVERTISE_100HALF;
2990         if (mask & ADVERTISED_100baseT_Full)
2991                 all_mask |= ADVERTISE_100FULL;
2992
2993         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2994                 return 0;
2995
2996         if ((adv_reg & all_mask) != all_mask)
2997                 return 0;
2998         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
2999                 u32 tg3_ctrl;
3000
3001                 all_mask = 0;
3002                 if (mask & ADVERTISED_1000baseT_Half)
3003                         all_mask |= ADVERTISE_1000HALF;
3004                 if (mask & ADVERTISED_1000baseT_Full)
3005                         all_mask |= ADVERTISE_1000FULL;
3006
3007                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3008                         return 0;
3009
3010                 if ((tg3_ctrl & all_mask) != all_mask)
3011                         return 0;
3012         }
3013         return 1;
3014 }
3015
3016 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3017 {
3018         u32 curadv, reqadv;
3019
3020         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3021                 return 1;
3022
3023         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3024         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3025
3026         if (tp->link_config.active_duplex == DUPLEX_FULL) {
3027                 if (curadv != reqadv)
3028                         return 0;
3029
3030                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3031                         tg3_readphy(tp, MII_LPA, rmtadv);
3032         } else {
3033                 /* Reprogram the advertisement register, even if it
3034                  * does not affect the current link.  If the link
3035                  * gets renegotiated in the future, we can save an
3036                  * additional renegotiation cycle by advertising
3037                  * it correctly in the first place.
3038                  */
3039                 if (curadv != reqadv) {
3040                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3041                                      ADVERTISE_PAUSE_ASYM);
3042                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3043                 }
3044         }
3045
3046         return 1;
3047 }
3048
3049 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3050 {
3051         int current_link_up;
3052         u32 bmsr, val;
3053         u32 lcl_adv, rmt_adv;
3054         u16 current_speed;
3055         u8 current_duplex;
3056         int i, err;
3057
3058         tw32(MAC_EVENT, 0);
3059
3060         tw32_f(MAC_STATUS,
3061              (MAC_STATUS_SYNC_CHANGED |
3062               MAC_STATUS_CFG_CHANGED |
3063               MAC_STATUS_MI_COMPLETION |
3064               MAC_STATUS_LNKSTATE_CHANGED));
3065         udelay(40);
3066
3067         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3068                 tw32_f(MAC_MI_MODE,
3069                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3070                 udelay(80);
3071         }
3072
3073         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3074
3075         /* Some third-party PHYs need to be reset on link going
3076          * down.
3077          */
3078         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3079              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3080              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3081             netif_carrier_ok(tp->dev)) {
3082                 tg3_readphy(tp, MII_BMSR, &bmsr);
3083                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3084                     !(bmsr & BMSR_LSTATUS))
3085                         force_reset = 1;
3086         }
3087         if (force_reset)
3088                 tg3_phy_reset(tp);
3089
3090         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3091                 tg3_readphy(tp, MII_BMSR, &bmsr);
3092                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3093                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3094                         bmsr = 0;
3095
3096                 if (!(bmsr & BMSR_LSTATUS)) {
3097                         err = tg3_init_5401phy_dsp(tp);
3098                         if (err)
3099                                 return err;
3100
3101                         tg3_readphy(tp, MII_BMSR, &bmsr);
3102                         for (i = 0; i < 1000; i++) {
3103                                 udelay(10);
3104                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3105                                     (bmsr & BMSR_LSTATUS)) {
3106                                         udelay(40);
3107                                         break;
3108                                 }
3109                         }
3110
3111                         if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3112                             TG3_PHY_REV_BCM5401_B0 &&
3113                             !(bmsr & BMSR_LSTATUS) &&
3114                             tp->link_config.active_speed == SPEED_1000) {
3115                                 err = tg3_phy_reset(tp);
3116                                 if (!err)
3117                                         err = tg3_init_5401phy_dsp(tp);
3118                                 if (err)
3119                                         return err;
3120                         }
3121                 }
3122         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3123                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3124                 /* 5701 {A0,B0} CRC bug workaround */
3125                 tg3_writephy(tp, 0x15, 0x0a75);
3126                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3127                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3128                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3129         }
3130
3131         /* Clear pending interrupts... */
3132         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3133         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3134
3135         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3136                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3137         else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3138                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3139
3140         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3141             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3142                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3143                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3144                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3145                 else
3146                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3147         }
3148
3149         current_link_up = 0;
3150         current_speed = SPEED_INVALID;
3151         current_duplex = DUPLEX_INVALID;
3152
3153         if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3154                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3155                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3156                 if (!(val & (1 << 10))) {
3157                         val |= (1 << 10);
3158                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3159                         goto relink;
3160                 }
3161         }
3162
3163         bmsr = 0;
3164         for (i = 0; i < 100; i++) {
3165                 tg3_readphy(tp, MII_BMSR, &bmsr);
3166                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3167                     (bmsr & BMSR_LSTATUS))
3168                         break;
3169                 udelay(40);
3170         }
3171
3172         if (bmsr & BMSR_LSTATUS) {
3173                 u32 aux_stat, bmcr;
3174
3175                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3176                 for (i = 0; i < 2000; i++) {
3177                         udelay(10);
3178                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3179                             aux_stat)
3180                                 break;
3181                 }
3182
3183                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3184                                              &current_speed,
3185                                              &current_duplex);
3186
3187                 bmcr = 0;
3188                 for (i = 0; i < 200; i++) {
3189                         tg3_readphy(tp, MII_BMCR, &bmcr);
3190                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3191                                 continue;
3192                         if (bmcr && bmcr != 0x7fff)
3193                                 break;
3194                         udelay(10);
3195                 }
3196
3197                 lcl_adv = 0;
3198                 rmt_adv = 0;
3199
3200                 tp->link_config.active_speed = current_speed;
3201                 tp->link_config.active_duplex = current_duplex;
3202
3203                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3204                         if ((bmcr & BMCR_ANENABLE) &&
3205                             tg3_copper_is_advertising_all(tp,
3206                                                 tp->link_config.advertising)) {
3207                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3208                                                                   &rmt_adv))
3209                                         current_link_up = 1;
3210                         }
3211                 } else {
3212                         if (!(bmcr & BMCR_ANENABLE) &&
3213                             tp->link_config.speed == current_speed &&
3214                             tp->link_config.duplex == current_duplex &&
3215                             tp->link_config.flowctrl ==
3216                             tp->link_config.active_flowctrl) {
3217                                 current_link_up = 1;
3218                         }
3219                 }
3220
3221                 if (current_link_up == 1 &&
3222                     tp->link_config.active_duplex == DUPLEX_FULL)
3223                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3224         }
3225
3226 relink:
3227         if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3228                 tg3_phy_copper_begin(tp);
3229
3230                 tg3_readphy(tp, MII_BMSR, &bmsr);
3231                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3232                     (bmsr & BMSR_LSTATUS))
3233                         current_link_up = 1;
3234         }
3235
3236         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3237         if (current_link_up == 1) {
3238                 if (tp->link_config.active_speed == SPEED_100 ||
3239                     tp->link_config.active_speed == SPEED_10)
3240                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3241                 else
3242                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3243         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
3244                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3245         else
3246                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3247
3248         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3249         if (tp->link_config.active_duplex == DUPLEX_HALF)
3250                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3251
3252         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3253                 if (current_link_up == 1 &&
3254                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3255                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3256                 else
3257                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3258         }
3259
3260         /* ??? Without this setting Netgear GA302T PHY does not
3261          * ??? send/receive packets...
3262          */
3263         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3264             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3265                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3266                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3267                 udelay(80);
3268         }
3269
3270         tw32_f(MAC_MODE, tp->mac_mode);
3271         udelay(40);
3272
3273         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3274                 /* Polled via timer. */
3275                 tw32_f(MAC_EVENT, 0);
3276         } else {
3277                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3278         }
3279         udelay(40);
3280
3281         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3282             current_link_up == 1 &&
3283             tp->link_config.active_speed == SPEED_1000 &&
3284             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3285              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3286                 udelay(120);
3287                 tw32_f(MAC_STATUS,
3288                      (MAC_STATUS_SYNC_CHANGED |
3289                       MAC_STATUS_CFG_CHANGED));
3290                 udelay(40);
3291                 tg3_write_mem(tp,
3292                               NIC_SRAM_FIRMWARE_MBOX,
3293                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3294         }
3295
3296         /* Prevent send BD corruption. */
3297         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3298                 u16 oldlnkctl, newlnkctl;
3299
3300                 pci_read_config_word(tp->pdev,
3301                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3302                                      &oldlnkctl);
3303                 if (tp->link_config.active_speed == SPEED_100 ||
3304                     tp->link_config.active_speed == SPEED_10)
3305                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3306                 else
3307                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3308                 if (newlnkctl != oldlnkctl)
3309                         pci_write_config_word(tp->pdev,
3310                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3311                                               newlnkctl);
3312         }
3313
3314         if (current_link_up != netif_carrier_ok(tp->dev)) {
3315                 if (current_link_up)
3316                         netif_carrier_on(tp->dev);
3317                 else
3318                         netif_carrier_off(tp->dev);
3319                 tg3_link_report(tp);
3320         }
3321
3322         return 0;
3323 }
3324
3325 struct tg3_fiber_aneginfo {
3326         int state;
3327 #define ANEG_STATE_UNKNOWN              0
3328 #define ANEG_STATE_AN_ENABLE            1
3329 #define ANEG_STATE_RESTART_INIT         2
3330 #define ANEG_STATE_RESTART              3
3331 #define ANEG_STATE_DISABLE_LINK_OK      4
3332 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3333 #define ANEG_STATE_ABILITY_DETECT       6
3334 #define ANEG_STATE_ACK_DETECT_INIT      7
3335 #define ANEG_STATE_ACK_DETECT           8
3336 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3337 #define ANEG_STATE_COMPLETE_ACK         10
3338 #define ANEG_STATE_IDLE_DETECT_INIT     11
3339 #define ANEG_STATE_IDLE_DETECT          12
3340 #define ANEG_STATE_LINK_OK              13
3341 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3342 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3343
3344         u32 flags;
3345 #define MR_AN_ENABLE            0x00000001
3346 #define MR_RESTART_AN           0x00000002
3347 #define MR_AN_COMPLETE          0x00000004
3348 #define MR_PAGE_RX              0x00000008
3349 #define MR_NP_LOADED            0x00000010
3350 #define MR_TOGGLE_TX            0x00000020
3351 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3352 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3353 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3354 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3355 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3356 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3357 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3358 #define MR_TOGGLE_RX            0x00002000
3359 #define MR_NP_RX                0x00004000
3360
3361 #define MR_LINK_OK              0x80000000
3362
3363         unsigned long link_time, cur_time;
3364
3365         u32 ability_match_cfg;
3366         int ability_match_count;
3367
3368         char ability_match, idle_match, ack_match;
3369
3370         u32 txconfig, rxconfig;
3371 #define ANEG_CFG_NP             0x00000080
3372 #define ANEG_CFG_ACK            0x00000040
3373 #define ANEG_CFG_RF2            0x00000020
3374 #define ANEG_CFG_RF1            0x00000010
3375 #define ANEG_CFG_PS2            0x00000001
3376 #define ANEG_CFG_PS1            0x00008000
3377 #define ANEG_CFG_HD             0x00004000
3378 #define ANEG_CFG_FD             0x00002000
3379 #define ANEG_CFG_INVAL          0x00001f06
3380
3381 };
3382 #define ANEG_OK         0
3383 #define ANEG_DONE       1
3384 #define ANEG_TIMER_ENAB 2
3385 #define ANEG_FAILED     -1
3386
3387 #define ANEG_STATE_SETTLE_TIME  10000
3388
3389 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3390                                    struct tg3_fiber_aneginfo *ap)
3391 {
3392         u16 flowctrl;
3393         unsigned long delta;
3394         u32 rx_cfg_reg;
3395         int ret;
3396
3397         if (ap->state == ANEG_STATE_UNKNOWN) {
3398                 ap->rxconfig = 0;
3399                 ap->link_time = 0;
3400                 ap->cur_time = 0;
3401                 ap->ability_match_cfg = 0;
3402                 ap->ability_match_count = 0;
3403                 ap->ability_match = 0;
3404                 ap->idle_match = 0;
3405                 ap->ack_match = 0;
3406         }
3407         ap->cur_time++;
3408
3409         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3410                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3411
3412                 if (rx_cfg_reg != ap->ability_match_cfg) {
3413                         ap->ability_match_cfg = rx_cfg_reg;
3414                         ap->ability_match = 0;
3415                         ap->ability_match_count = 0;
3416                 } else {
3417                         if (++ap->ability_match_count > 1) {
3418                                 ap->ability_match = 1;
3419                                 ap->ability_match_cfg = rx_cfg_reg;
3420                         }
3421                 }
3422                 if (rx_cfg_reg & ANEG_CFG_ACK)
3423                         ap->ack_match = 1;
3424                 else
3425                         ap->ack_match = 0;
3426
3427                 ap->idle_match = 0;
3428         } else {
3429                 ap->idle_match = 1;
3430                 ap->ability_match_cfg = 0;
3431                 ap->ability_match_count = 0;
3432                 ap->ability_match = 0;
3433                 ap->ack_match = 0;
3434
3435                 rx_cfg_reg = 0;
3436         }
3437
3438         ap->rxconfig = rx_cfg_reg;
3439         ret = ANEG_OK;
3440
3441         switch (ap->state) {
3442         case ANEG_STATE_UNKNOWN:
3443                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3444                         ap->state = ANEG_STATE_AN_ENABLE;
3445
3446                 /* fallthru */
3447         case ANEG_STATE_AN_ENABLE:
3448                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3449                 if (ap->flags & MR_AN_ENABLE) {
3450                         ap->link_time = 0;
3451                         ap->cur_time = 0;
3452                         ap->ability_match_cfg = 0;
3453                         ap->ability_match_count = 0;
3454                         ap->ability_match = 0;
3455                         ap->idle_match = 0;
3456                         ap->ack_match = 0;
3457
3458                         ap->state = ANEG_STATE_RESTART_INIT;
3459                 } else {
3460                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3461                 }
3462                 break;
3463
3464         case ANEG_STATE_RESTART_INIT:
3465                 ap->link_time = ap->cur_time;
3466                 ap->flags &= ~(MR_NP_LOADED);
3467                 ap->txconfig = 0;
3468                 tw32(MAC_TX_AUTO_NEG, 0);
3469                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3470                 tw32_f(MAC_MODE, tp->mac_mode);
3471                 udelay(40);
3472
3473                 ret = ANEG_TIMER_ENAB;
3474                 ap->state = ANEG_STATE_RESTART;
3475
3476                 /* fallthru */
3477         case ANEG_STATE_RESTART:
3478                 delta = ap->cur_time - ap->link_time;
3479                 if (delta > ANEG_STATE_SETTLE_TIME)
3480                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3481                 else
3482                         ret = ANEG_TIMER_ENAB;
3483                 break;
3484
3485         case ANEG_STATE_DISABLE_LINK_OK:
3486                 ret = ANEG_DONE;
3487                 break;
3488
3489         case ANEG_STATE_ABILITY_DETECT_INIT:
3490                 ap->flags &= ~(MR_TOGGLE_TX);
3491                 ap->txconfig = ANEG_CFG_FD;
3492                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3493                 if (flowctrl & ADVERTISE_1000XPAUSE)
3494                         ap->txconfig |= ANEG_CFG_PS1;
3495                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3496                         ap->txconfig |= ANEG_CFG_PS2;
3497                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3498                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3499                 tw32_f(MAC_MODE, tp->mac_mode);
3500                 udelay(40);
3501
3502                 ap->state = ANEG_STATE_ABILITY_DETECT;
3503                 break;
3504
3505         case ANEG_STATE_ABILITY_DETECT:
3506                 if (ap->ability_match != 0 && ap->rxconfig != 0)
3507                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3508                 break;
3509
3510         case ANEG_STATE_ACK_DETECT_INIT:
3511                 ap->txconfig |= ANEG_CFG_ACK;
3512                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3513                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3514                 tw32_f(MAC_MODE, tp->mac_mode);
3515                 udelay(40);
3516
3517                 ap->state = ANEG_STATE_ACK_DETECT;
3518
3519                 /* fallthru */
3520         case ANEG_STATE_ACK_DETECT:
3521                 if (ap->ack_match != 0) {
3522                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3523                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3524                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3525                         } else {
3526                                 ap->state = ANEG_STATE_AN_ENABLE;
3527                         }
3528                 } else if (ap->ability_match != 0 &&
3529                            ap->rxconfig == 0) {
3530                         ap->state = ANEG_STATE_AN_ENABLE;
3531                 }
3532                 break;
3533
3534         case ANEG_STATE_COMPLETE_ACK_INIT:
3535                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3536                         ret = ANEG_FAILED;
3537                         break;
3538                 }
3539                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3540                                MR_LP_ADV_HALF_DUPLEX |
3541                                MR_LP_ADV_SYM_PAUSE |
3542                                MR_LP_ADV_ASYM_PAUSE |
3543                                MR_LP_ADV_REMOTE_FAULT1 |
3544                                MR_LP_ADV_REMOTE_FAULT2 |
3545                                MR_LP_ADV_NEXT_PAGE |
3546                                MR_TOGGLE_RX |
3547                                MR_NP_RX);
3548                 if (ap->rxconfig & ANEG_CFG_FD)
3549                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3550                 if (ap->rxconfig & ANEG_CFG_HD)
3551                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3552                 if (ap->rxconfig & ANEG_CFG_PS1)
3553                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3554                 if (ap->rxconfig & ANEG_CFG_PS2)
3555                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3556                 if (ap->rxconfig & ANEG_CFG_RF1)
3557                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3558                 if (ap->rxconfig & ANEG_CFG_RF2)
3559                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3560                 if (ap->rxconfig & ANEG_CFG_NP)
3561                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3562
3563                 ap->link_time = ap->cur_time;
3564
3565                 ap->flags ^= (MR_TOGGLE_TX);
3566                 if (ap->rxconfig & 0x0008)
3567                         ap->flags |= MR_TOGGLE_RX;
3568                 if (ap->rxconfig & ANEG_CFG_NP)
3569                         ap->flags |= MR_NP_RX;
3570                 ap->flags |= MR_PAGE_RX;
3571
3572                 ap->state = ANEG_STATE_COMPLETE_ACK;
3573                 ret = ANEG_TIMER_ENAB;
3574                 break;
3575
3576         case ANEG_STATE_COMPLETE_ACK:
3577                 if (ap->ability_match != 0 &&
3578                     ap->rxconfig == 0) {
3579                         ap->state = ANEG_STATE_AN_ENABLE;
3580                         break;
3581                 }
3582                 delta = ap->cur_time - ap->link_time;
3583                 if (delta > ANEG_STATE_SETTLE_TIME) {
3584                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3585                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3586                         } else {
3587                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3588                                     !(ap->flags & MR_NP_RX)) {
3589                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3590                                 } else {
3591                                         ret = ANEG_FAILED;
3592                                 }
3593                         }
3594                 }
3595                 break;
3596
3597         case ANEG_STATE_IDLE_DETECT_INIT:
3598                 ap->link_time = ap->cur_time;
3599                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3600                 tw32_f(MAC_MODE, tp->mac_mode);
3601                 udelay(40);
3602
3603                 ap->state = ANEG_STATE_IDLE_DETECT;
3604                 ret = ANEG_TIMER_ENAB;
3605                 break;
3606
3607         case ANEG_STATE_IDLE_DETECT:
3608                 if (ap->ability_match != 0 &&
3609                     ap->rxconfig == 0) {
3610                         ap->state = ANEG_STATE_AN_ENABLE;
3611                         break;
3612                 }
3613                 delta = ap->cur_time - ap->link_time;
3614                 if (delta > ANEG_STATE_SETTLE_TIME) {
3615                         /* XXX another gem from the Broadcom driver :( */
3616                         ap->state = ANEG_STATE_LINK_OK;
3617                 }
3618                 break;
3619
3620         case ANEG_STATE_LINK_OK:
3621                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3622                 ret = ANEG_DONE;
3623                 break;
3624
3625         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3626                 /* ??? unimplemented */
3627                 break;
3628
3629         case ANEG_STATE_NEXT_PAGE_WAIT:
3630                 /* ??? unimplemented */
3631                 break;
3632
3633         default:
3634                 ret = ANEG_FAILED;
3635                 break;
3636         }
3637
3638         return ret;
3639 }
3640
3641 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3642 {
3643         int res = 0;
3644         struct tg3_fiber_aneginfo aninfo;
3645         int status = ANEG_FAILED;
3646         unsigned int tick;
3647         u32 tmp;
3648
3649         tw32_f(MAC_TX_AUTO_NEG, 0);
3650
3651         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3652         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3653         udelay(40);
3654
3655         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3656         udelay(40);
3657
3658         memset(&aninfo, 0, sizeof(aninfo));
3659         aninfo.flags |= MR_AN_ENABLE;
3660         aninfo.state = ANEG_STATE_UNKNOWN;
3661         aninfo.cur_time = 0;
3662         tick = 0;
3663         while (++tick < 195000) {
3664                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3665                 if (status == ANEG_DONE || status == ANEG_FAILED)
3666                         break;
3667
3668                 udelay(1);
3669         }
3670
3671         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3672         tw32_f(MAC_MODE, tp->mac_mode);
3673         udelay(40);
3674
3675         *txflags = aninfo.txconfig;
3676         *rxflags = aninfo.flags;
3677
3678         if (status == ANEG_DONE &&
3679             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3680                              MR_LP_ADV_FULL_DUPLEX)))
3681                 res = 1;
3682
3683         return res;
3684 }
3685
3686 static void tg3_init_bcm8002(struct tg3 *tp)
3687 {
3688         u32 mac_status = tr32(MAC_STATUS);
3689         int i;
3690
3691         /* Reset when initting first time or we have a link. */
3692         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3693             !(mac_status & MAC_STATUS_PCS_SYNCED))
3694                 return;
3695
3696         /* Set PLL lock range. */
3697         tg3_writephy(tp, 0x16, 0x8007);
3698
3699         /* SW reset */
3700         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3701
3702         /* Wait for reset to complete. */
3703         /* XXX schedule_timeout() ... */
3704         for (i = 0; i < 500; i++)
3705                 udelay(10);
3706
3707         /* Config mode; select PMA/Ch 1 regs. */
3708         tg3_writephy(tp, 0x10, 0x8411);
3709
3710         /* Enable auto-lock and comdet, select txclk for tx. */
3711         tg3_writephy(tp, 0x11, 0x0a10);
3712
3713         tg3_writephy(tp, 0x18, 0x00a0);
3714         tg3_writephy(tp, 0x16, 0x41ff);
3715
3716         /* Assert and deassert POR. */
3717         tg3_writephy(tp, 0x13, 0x0400);
3718         udelay(40);
3719         tg3_writephy(tp, 0x13, 0x0000);
3720
3721         tg3_writephy(tp, 0x11, 0x0a50);
3722         udelay(40);
3723         tg3_writephy(tp, 0x11, 0x0a10);
3724
3725         /* Wait for signal to stabilize */
3726         /* XXX schedule_timeout() ... */
3727         for (i = 0; i < 15000; i++)
3728                 udelay(10);
3729
3730         /* Deselect the channel register so we can read the PHYID
3731          * later.
3732          */
3733         tg3_writephy(tp, 0x10, 0x8011);
3734 }
3735
3736 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3737 {
3738         u16 flowctrl;
3739         u32 sg_dig_ctrl, sg_dig_status;
3740         u32 serdes_cfg, expected_sg_dig_ctrl;
3741         int workaround, port_a;
3742         int current_link_up;
3743
3744         serdes_cfg = 0;
3745         expected_sg_dig_ctrl = 0;
3746         workaround = 0;
3747         port_a = 1;
3748         current_link_up = 0;
3749
3750         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3751             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3752                 workaround = 1;
3753                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3754                         port_a = 0;
3755
3756                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3757                 /* preserve bits 20-23 for voltage regulator */
3758                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3759         }
3760
3761         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3762
3763         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3764                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3765                         if (workaround) {
3766                                 u32 val = serdes_cfg;
3767
3768                                 if (port_a)
3769                                         val |= 0xc010000;
3770                                 else
3771                                         val |= 0x4010000;
3772                                 tw32_f(MAC_SERDES_CFG, val);
3773                         }
3774
3775                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3776                 }
3777                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3778                         tg3_setup_flow_control(tp, 0, 0);
3779                         current_link_up = 1;
3780                 }
3781                 goto out;
3782         }
3783
3784         /* Want auto-negotiation.  */
3785         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3786
3787         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3788         if (flowctrl & ADVERTISE_1000XPAUSE)
3789                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3790         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3791                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3792
3793         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3794                 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3795                     tp->serdes_counter &&
3796                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3797                                     MAC_STATUS_RCVD_CFG)) ==
3798                      MAC_STATUS_PCS_SYNCED)) {
3799                         tp->serdes_counter--;
3800                         current_link_up = 1;
3801                         goto out;
3802                 }
3803 restart_autoneg:
3804                 if (workaround)
3805                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3806                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3807                 udelay(5);
3808                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3809
3810                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3811                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3812         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3813                                  MAC_STATUS_SIGNAL_DET)) {
3814                 sg_dig_status = tr32(SG_DIG_STATUS);
3815                 mac_status = tr32(MAC_STATUS);
3816
3817                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3818                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3819                         u32 local_adv = 0, remote_adv = 0;
3820
3821                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3822                                 local_adv |= ADVERTISE_1000XPAUSE;
3823                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3824                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3825
3826                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3827                                 remote_adv |= LPA_1000XPAUSE;
3828                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3829                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3830
3831                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3832                         current_link_up = 1;
3833                         tp->serdes_counter = 0;
3834                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3835                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3836                         if (tp->serdes_counter)
3837                                 tp->serdes_counter--;
3838                         else {
3839                                 if (workaround) {
3840                                         u32 val = serdes_cfg;
3841
3842                                         if (port_a)
3843                                                 val |= 0xc010000;
3844                                         else
3845                                                 val |= 0x4010000;
3846
3847                                         tw32_f(MAC_SERDES_CFG, val);
3848                                 }
3849
3850                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3851                                 udelay(40);
3852
3853                                 /* Link parallel detection - link is up */
3854                                 /* only if we have PCS_SYNC and not */
3855                                 /* receiving config code words */
3856                                 mac_status = tr32(MAC_STATUS);
3857                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3858                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3859                                         tg3_setup_flow_control(tp, 0, 0);
3860                                         current_link_up = 1;
3861                                         tp->phy_flags |=
3862                                                 TG3_PHYFLG_PARALLEL_DETECT;
3863                                         tp->serdes_counter =
3864                                                 SERDES_PARALLEL_DET_TIMEOUT;
3865                                 } else
3866                                         goto restart_autoneg;
3867                         }
3868                 }
3869         } else {
3870                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3871                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3872         }
3873
3874 out:
3875         return current_link_up;
3876 }
3877
3878 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3879 {
3880         int current_link_up = 0;
3881
3882         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3883                 goto out;
3884
3885         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3886                 u32 txflags, rxflags;
3887                 int i;
3888
3889                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3890                         u32 local_adv = 0, remote_adv = 0;
3891
3892                         if (txflags & ANEG_CFG_PS1)
3893                                 local_adv |= ADVERTISE_1000XPAUSE;
3894                         if (txflags & ANEG_CFG_PS2)
3895                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3896
3897                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3898                                 remote_adv |= LPA_1000XPAUSE;
3899                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3900                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3901
3902                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3903
3904                         current_link_up = 1;
3905                 }
3906                 for (i = 0; i < 30; i++) {
3907                         udelay(20);
3908                         tw32_f(MAC_STATUS,
3909                                (MAC_STATUS_SYNC_CHANGED |
3910                                 MAC_STATUS_CFG_CHANGED));
3911                         udelay(40);
3912                         if ((tr32(MAC_STATUS) &
3913                              (MAC_STATUS_SYNC_CHANGED |
3914                               MAC_STATUS_CFG_CHANGED)) == 0)
3915                                 break;
3916                 }
3917
3918                 mac_status = tr32(MAC_STATUS);
3919                 if (current_link_up == 0 &&
3920                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3921                     !(mac_status & MAC_STATUS_RCVD_CFG))
3922                         current_link_up = 1;
3923         } else {
3924                 tg3_setup_flow_control(tp, 0, 0);
3925
3926                 /* Forcing 1000FD link up. */
3927                 current_link_up = 1;
3928
3929                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3930                 udelay(40);
3931
3932                 tw32_f(MAC_MODE, tp->mac_mode);
3933                 udelay(40);
3934         }
3935
3936 out:
3937         return current_link_up;
3938 }
3939
3940 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3941 {
3942         u32 orig_pause_cfg;
3943         u16 orig_active_speed;
3944         u8 orig_active_duplex;
3945         u32 mac_status;
3946         int current_link_up;
3947         int i;
3948
3949         orig_pause_cfg = tp->link_config.active_flowctrl;
3950         orig_active_speed = tp->link_config.active_speed;
3951         orig_active_duplex = tp->link_config.active_duplex;
3952
3953         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3954             netif_carrier_ok(tp->dev) &&
3955             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3956                 mac_status = tr32(MAC_STATUS);
3957                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3958                                MAC_STATUS_SIGNAL_DET |
3959                                MAC_STATUS_CFG_CHANGED |
3960                                MAC_STATUS_RCVD_CFG);
3961                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3962                                    MAC_STATUS_SIGNAL_DET)) {
3963                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3964                                             MAC_STATUS_CFG_CHANGED));
3965                         return 0;
3966                 }
3967         }
3968
3969         tw32_f(MAC_TX_AUTO_NEG, 0);
3970
3971         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3972         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3973         tw32_f(MAC_MODE, tp->mac_mode);
3974         udelay(40);
3975
3976         if (tp->phy_id == TG3_PHY_ID_BCM8002)
3977                 tg3_init_bcm8002(tp);
3978
3979         /* Enable link change event even when serdes polling.  */
3980         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3981         udelay(40);
3982
3983         current_link_up = 0;
3984         mac_status = tr32(MAC_STATUS);
3985
3986         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3987                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3988         else
3989                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3990
3991         tp->napi[0].hw_status->status =
3992                 (SD_STATUS_UPDATED |
3993                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3994
3995         for (i = 0; i < 100; i++) {
3996                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3997                                     MAC_STATUS_CFG_CHANGED));
3998                 udelay(5);
3999                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4000                                          MAC_STATUS_CFG_CHANGED |
4001                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4002                         break;
4003         }
4004
4005         mac_status = tr32(MAC_STATUS);
4006         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4007                 current_link_up = 0;
4008                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4009                     tp->serdes_counter == 0) {
4010                         tw32_f(MAC_MODE, (tp->mac_mode |
4011                                           MAC_MODE_SEND_CONFIGS));
4012                         udelay(1);
4013                         tw32_f(MAC_MODE, tp->mac_mode);
4014                 }
4015         }
4016
4017         if (current_link_up == 1) {
4018                 tp->link_config.active_speed = SPEED_1000;
4019                 tp->link_config.active_duplex = DUPLEX_FULL;
4020                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4021                                     LED_CTRL_LNKLED_OVERRIDE |
4022                                     LED_CTRL_1000MBPS_ON));
4023         } else {
4024                 tp->link_config.active_speed = SPEED_INVALID;
4025                 tp->link_config.active_duplex = DUPLEX_INVALID;
4026                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4027                                     LED_CTRL_LNKLED_OVERRIDE |
4028                                     LED_CTRL_TRAFFIC_OVERRIDE));
4029         }
4030
4031         if (current_link_up != netif_carrier_ok(tp->dev)) {
4032                 if (current_link_up)
4033                         netif_carrier_on(tp->dev);
4034                 else
4035                         netif_carrier_off(tp->dev);
4036                 tg3_link_report(tp);
4037         } else {
4038                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4039                 if (orig_pause_cfg != now_pause_cfg ||
4040                     orig_active_speed != tp->link_config.active_speed ||
4041                     orig_active_duplex != tp->link_config.active_duplex)
4042                         tg3_link_report(tp);
4043         }
4044
4045         return 0;
4046 }
4047
4048 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4049 {
4050         int current_link_up, err = 0;
4051         u32 bmsr, bmcr;
4052         u16 current_speed;
4053         u8 current_duplex;
4054         u32 local_adv, remote_adv;
4055
4056         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4057         tw32_f(MAC_MODE, tp->mac_mode);
4058         udelay(40);
4059
4060         tw32(MAC_EVENT, 0);
4061
4062         tw32_f(MAC_STATUS,
4063              (MAC_STATUS_SYNC_CHANGED |
4064               MAC_STATUS_CFG_CHANGED |
4065               MAC_STATUS_MI_COMPLETION |
4066               MAC_STATUS_LNKSTATE_CHANGED));
4067         udelay(40);
4068
4069         if (force_reset)
4070                 tg3_phy_reset(tp);
4071
4072         current_link_up = 0;
4073         current_speed = SPEED_INVALID;
4074         current_duplex = DUPLEX_INVALID;
4075
4076         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4077         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4078         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4079                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4080                         bmsr |= BMSR_LSTATUS;
4081                 else
4082                         bmsr &= ~BMSR_LSTATUS;
4083         }
4084
4085         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4086
4087         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4088             (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4089                 /* do nothing, just check for link up at the end */
4090         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4091                 u32 adv, new_adv;
4092
4093                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4094                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4095                                   ADVERTISE_1000XPAUSE |
4096                                   ADVERTISE_1000XPSE_ASYM |
4097                                   ADVERTISE_SLCT);
4098
4099                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4100
4101                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4102                         new_adv |= ADVERTISE_1000XHALF;
4103                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4104                         new_adv |= ADVERTISE_1000XFULL;
4105
4106                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4107                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4108                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4109                         tg3_writephy(tp, MII_BMCR, bmcr);
4110
4111                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4112                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4113                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4114
4115                         return err;
4116                 }
4117         } else {
4118                 u32 new_bmcr;
4119
4120                 bmcr &= ~BMCR_SPEED1000;
4121                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4122
4123                 if (tp->link_config.duplex == DUPLEX_FULL)
4124                         new_bmcr |= BMCR_FULLDPLX;
4125
4126                 if (new_bmcr != bmcr) {
4127                         /* BMCR_SPEED1000 is a reserved bit that needs
4128                          * to be set on write.
4129                          */
4130                         new_bmcr |= BMCR_SPEED1000;
4131
4132                         /* Force a linkdown */
4133                         if (netif_carrier_ok(tp->dev)) {
4134                                 u32 adv;
4135
4136                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4137                                 adv &= ~(ADVERTISE_1000XFULL |
4138                                          ADVERTISE_1000XHALF |
4139                                          ADVERTISE_SLCT);
4140                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4141                                 tg3_writephy(tp, MII_BMCR, bmcr |
4142                                                            BMCR_ANRESTART |
4143                                                            BMCR_ANENABLE);
4144                                 udelay(10);
4145                                 netif_carrier_off(tp->dev);
4146                         }
4147                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4148                         bmcr = new_bmcr;
4149                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4150                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4151                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4152                             ASIC_REV_5714) {
4153                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4154                                         bmsr |= BMSR_LSTATUS;
4155                                 else
4156                                         bmsr &= ~BMSR_LSTATUS;
4157                         }
4158                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4159                 }
4160         }
4161
4162         if (bmsr & BMSR_LSTATUS) {
4163                 current_speed = SPEED_1000;
4164                 current_link_up = 1;
4165                 if (bmcr & BMCR_FULLDPLX)
4166                         current_duplex = DUPLEX_FULL;
4167                 else
4168                         current_duplex = DUPLEX_HALF;
4169
4170                 local_adv = 0;
4171                 remote_adv = 0;
4172
4173                 if (bmcr & BMCR_ANENABLE) {
4174                         u32 common;
4175
4176                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4177                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4178                         common = local_adv & remote_adv;
4179                         if (common & (ADVERTISE_1000XHALF |
4180                                       ADVERTISE_1000XFULL)) {
4181                                 if (common & ADVERTISE_1000XFULL)
4182                                         current_duplex = DUPLEX_FULL;
4183                                 else
4184                                         current_duplex = DUPLEX_HALF;
4185                         } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4186                                 /* Link is up via parallel detect */
4187                         } else {
4188                                 current_link_up = 0;
4189                         }
4190                 }
4191         }
4192
4193         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4194                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4195
4196         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4197         if (tp->link_config.active_duplex == DUPLEX_HALF)
4198                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4199
4200         tw32_f(MAC_MODE, tp->mac_mode);
4201         udelay(40);
4202
4203         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4204
4205         tp->link_config.active_speed = current_speed;
4206         tp->link_config.active_duplex = current_duplex;
4207
4208         if (current_link_up != netif_carrier_ok(tp->dev)) {
4209                 if (current_link_up)
4210                         netif_carrier_on(tp->dev);
4211                 else {
4212                         netif_carrier_off(tp->dev);
4213                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4214                 }
4215                 tg3_link_report(tp);
4216         }
4217         return err;
4218 }
4219
4220 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4221 {
4222         if (tp->serdes_counter) {
4223                 /* Give autoneg time to complete. */
4224                 tp->serdes_counter--;
4225                 return;
4226         }
4227
4228         if (!netif_carrier_ok(tp->dev) &&
4229             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4230                 u32 bmcr;
4231
4232                 tg3_readphy(tp, MII_BMCR, &bmcr);
4233                 if (bmcr & BMCR_ANENABLE) {
4234                         u32 phy1, phy2;
4235
4236                         /* Select shadow register 0x1f */
4237                         tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
4238                         tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
4239
4240                         /* Select expansion interrupt status register */
4241                         tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4242                                          MII_TG3_DSP_EXP1_INT_STAT);
4243                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4244                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4245
4246                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4247                                 /* We have signal detect and not receiving
4248                                  * config code words, link is up by parallel
4249                                  * detection.
4250                                  */
4251
4252                                 bmcr &= ~BMCR_ANENABLE;
4253                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4254                                 tg3_writephy(tp, MII_BMCR, bmcr);
4255                                 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
4256                         }
4257                 }
4258         } else if (netif_carrier_ok(tp->dev) &&
4259                    (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4260                    (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4261                 u32 phy2;
4262
4263                 /* Select expansion interrupt status register */
4264                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4265                                  MII_TG3_DSP_EXP1_INT_STAT);
4266                 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4267                 if (phy2 & 0x20) {
4268                         u32 bmcr;
4269
4270                         /* Config code words received, turn on autoneg. */
4271                         tg3_readphy(tp, MII_BMCR, &bmcr);
4272                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4273
4274                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4275
4276                 }
4277         }
4278 }
4279
4280 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4281 {
4282         int err;
4283
4284         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
4285                 err = tg3_setup_fiber_phy(tp, force_reset);
4286         else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4287                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4288         else
4289                 err = tg3_setup_copper_phy(tp, force_reset);
4290
4291         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4292                 u32 val, scale;
4293
4294                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4295                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4296                         scale = 65;
4297                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4298                         scale = 6;
4299                 else
4300                         scale = 12;
4301
4302                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4303                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4304                 tw32(GRC_MISC_CFG, val);
4305         }
4306
4307         if (tp->link_config.active_speed == SPEED_1000 &&
4308             tp->link_config.active_duplex == DUPLEX_HALF)
4309                 tw32(MAC_TX_LENGTHS,
4310                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4311                       (6 << TX_LENGTHS_IPG_SHIFT) |
4312                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4313         else
4314                 tw32(MAC_TX_LENGTHS,
4315                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4316                       (6 << TX_LENGTHS_IPG_SHIFT) |
4317                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4318
4319         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4320                 if (netif_carrier_ok(tp->dev)) {
4321                         tw32(HOSTCC_STAT_COAL_TICKS,
4322                              tp->coal.stats_block_coalesce_usecs);
4323                 } else {
4324                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4325                 }
4326         }
4327
4328         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4329                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4330                 if (!netif_carrier_ok(tp->dev))
4331                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4332                               tp->pwrmgmt_thresh;
4333                 else
4334                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4335                 tw32(PCIE_PWR_MGMT_THRESH, val);
4336         }
4337
4338         return err;
4339 }
4340
4341 /* This is called whenever we suspect that the system chipset is re-
4342  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4343  * is bogus tx completions. We try to recover by setting the
4344  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4345  * in the workqueue.
4346  */
4347 static void tg3_tx_recover(struct tg3 *tp)
4348 {
4349         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4350                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4351
4352         netdev_warn(tp->dev,
4353                     "The system may be re-ordering memory-mapped I/O "
4354                     "cycles to the network device, attempting to recover. "
4355                     "Please report the problem to the driver maintainer "
4356                     "and include system chipset information.\n");
4357
4358         spin_lock(&tp->lock);
4359         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4360         spin_unlock(&tp->lock);
4361 }
4362
4363 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4364 {
4365         /* Tell compiler to fetch tx indices from memory. */
4366         barrier();
4367         return tnapi->tx_pending -
4368                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4369 }
4370
4371 /* Tigon3 never reports partial packet sends.  So we do not
4372  * need special logic to handle SKBs that have not had all
4373  * of their frags sent yet, like SunGEM does.
4374  */
4375 static void tg3_tx(struct tg3_napi *tnapi)
4376 {
4377         struct tg3 *tp = tnapi->tp;
4378         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4379         u32 sw_idx = tnapi->tx_cons;
4380         struct netdev_queue *txq;
4381         int index = tnapi - tp->napi;
4382
4383         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4384                 index--;
4385
4386         txq = netdev_get_tx_queue(tp->dev, index);
4387
4388         while (sw_idx != hw_idx) {
4389                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4390                 struct sk_buff *skb = ri->skb;
4391                 int i, tx_bug = 0;
4392
4393                 if (unlikely(skb == NULL)) {
4394                         tg3_tx_recover(tp);
4395                         return;
4396                 }
4397
4398                 pci_unmap_single(tp->pdev,
4399                                  dma_unmap_addr(ri, mapping),
4400                                  skb_headlen(skb),
4401                                  PCI_DMA_TODEVICE);
4402
4403                 ri->skb = NULL;
4404
4405                 sw_idx = NEXT_TX(sw_idx);
4406
4407                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4408                         ri = &tnapi->tx_buffers[sw_idx];
4409                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4410                                 tx_bug = 1;
4411
4412                         pci_unmap_page(tp->pdev,
4413                                        dma_unmap_addr(ri, mapping),
4414                                        skb_shinfo(skb)->frags[i].size,
4415                                        PCI_DMA_TODEVICE);
4416                         sw_idx = NEXT_TX(sw_idx);
4417                 }
4418
4419                 dev_kfree_skb(skb);
4420
4421                 if (unlikely(tx_bug)) {
4422                         tg3_tx_recover(tp);
4423                         return;
4424                 }
4425         }
4426
4427         tnapi->tx_cons = sw_idx;
4428
4429         /* Need to make the tx_cons update visible to tg3_start_xmit()
4430          * before checking for netif_queue_stopped().  Without the
4431          * memory barrier, there is a small possibility that tg3_start_xmit()
4432          * will miss it and cause the queue to be stopped forever.
4433          */
4434         smp_mb();
4435
4436         if (unlikely(netif_tx_queue_stopped(txq) &&
4437                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4438                 __netif_tx_lock(txq, smp_processor_id());
4439                 if (netif_tx_queue_stopped(txq) &&
4440                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4441                         netif_tx_wake_queue(txq);
4442                 __netif_tx_unlock(txq);
4443         }
4444 }
4445
4446 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4447 {
4448         if (!ri->skb)
4449                 return;
4450
4451         pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4452                          map_sz, PCI_DMA_FROMDEVICE);
4453         dev_kfree_skb_any(ri->skb);
4454         ri->skb = NULL;
4455 }
4456
4457 /* Returns size of skb allocated or < 0 on error.
4458  *
4459  * We only need to fill in the address because the other members
4460  * of the RX descriptor are invariant, see tg3_init_rings.
4461  *
4462  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4463  * posting buffers we only dirty the first cache line of the RX
4464  * descriptor (containing the address).  Whereas for the RX status
4465  * buffers the cpu only reads the last cacheline of the RX descriptor
4466  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4467  */
4468 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4469                             u32 opaque_key, u32 dest_idx_unmasked)
4470 {
4471         struct tg3_rx_buffer_desc *desc;
4472         struct ring_info *map, *src_map;
4473         struct sk_buff *skb;
4474         dma_addr_t mapping;
4475         int skb_size, dest_idx;
4476
4477         src_map = NULL;
4478         switch (opaque_key) {
4479         case RXD_OPAQUE_RING_STD:
4480                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4481                 desc = &tpr->rx_std[dest_idx];
4482                 map = &tpr->rx_std_buffers[dest_idx];
4483                 skb_size = tp->rx_pkt_map_sz;
4484                 break;
4485
4486         case RXD_OPAQUE_RING_JUMBO:
4487                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4488                 desc = &tpr->rx_jmb[dest_idx].std;
4489                 map = &tpr->rx_jmb_buffers[dest_idx];
4490                 skb_size = TG3_RX_JMB_MAP_SZ;
4491                 break;
4492
4493         default:
4494                 return -EINVAL;
4495         }
4496
4497         /* Do not overwrite any of the map or rp information
4498          * until we are sure we can commit to a new buffer.
4499          *
4500          * Callers depend upon this behavior and assume that
4501          * we leave everything unchanged if we fail.
4502          */
4503         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4504         if (skb == NULL)
4505                 return -ENOMEM;
4506
4507         skb_reserve(skb, tp->rx_offset);
4508
4509         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4510                                  PCI_DMA_FROMDEVICE);
4511         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4512                 dev_kfree_skb(skb);
4513                 return -EIO;
4514         }
4515
4516         map->skb = skb;
4517         dma_unmap_addr_set(map, mapping, mapping);
4518
4519         desc->addr_hi = ((u64)mapping >> 32);
4520         desc->addr_lo = ((u64)mapping & 0xffffffff);
4521
4522         return skb_size;
4523 }
4524
4525 /* We only need to move over in the address because the other
4526  * members of the RX descriptor are invariant.  See notes above
4527  * tg3_alloc_rx_skb for full details.
4528  */
4529 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4530                            struct tg3_rx_prodring_set *dpr,
4531                            u32 opaque_key, int src_idx,
4532                            u32 dest_idx_unmasked)
4533 {
4534         struct tg3 *tp = tnapi->tp;
4535         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4536         struct ring_info *src_map, *dest_map;
4537         struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
4538         int dest_idx;
4539
4540         switch (opaque_key) {
4541         case RXD_OPAQUE_RING_STD:
4542                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4543                 dest_desc = &dpr->rx_std[dest_idx];
4544                 dest_map = &dpr->rx_std_buffers[dest_idx];
4545                 src_desc = &spr->rx_std[src_idx];
4546                 src_map = &spr->rx_std_buffers[src_idx];
4547                 break;
4548
4549         case RXD_OPAQUE_RING_JUMBO:
4550                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4551                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4552                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4553                 src_desc = &spr->rx_jmb[src_idx].std;
4554                 src_map = &spr->rx_jmb_buffers[src_idx];
4555                 break;
4556
4557         default:
4558                 return;
4559         }
4560
4561         dest_map->skb = src_map->skb;
4562         dma_unmap_addr_set(dest_map, mapping,
4563                            dma_unmap_addr(src_map, mapping));
4564         dest_desc->addr_hi = src_desc->addr_hi;
4565         dest_desc->addr_lo = src_desc->addr_lo;
4566
4567         /* Ensure that the update to the skb happens after the physical
4568          * addresses have been transferred to the new BD location.
4569          */
4570         smp_wmb();
4571
4572         src_map->skb = NULL;
4573 }
4574
4575 /* The RX ring scheme is composed of multiple rings which post fresh
4576  * buffers to the chip, and one special ring the chip uses to report
4577  * status back to the host.
4578  *
4579  * The special ring reports the status of received packets to the
4580  * host.  The chip does not write into the original descriptor the
4581  * RX buffer was obtained from.  The chip simply takes the original
4582  * descriptor as provided by the host, updates the status and length
4583  * field, then writes this into the next status ring entry.
4584  *
4585  * Each ring the host uses to post buffers to the chip is described
4586  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4587  * it is first placed into the on-chip ram.  When the packet's length
4588  * is known, it walks down the TG3_BDINFO entries to select the ring.
4589  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4590  * which is within the range of the new packet's length is chosen.
4591  *
4592  * The "separate ring for rx status" scheme may sound queer, but it makes
4593  * sense from a cache coherency perspective.  If only the host writes
4594  * to the buffer post rings, and only the chip writes to the rx status
4595  * rings, then cache lines never move beyond shared-modified state.
4596  * If both the host and chip were to write into the same ring, cache line
4597  * eviction could occur since both entities want it in an exclusive state.
4598  */
4599 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4600 {
4601         struct tg3 *tp = tnapi->tp;
4602         u32 work_mask, rx_std_posted = 0;
4603         u32 std_prod_idx, jmb_prod_idx;
4604         u32 sw_idx = tnapi->rx_rcb_ptr;
4605         u16 hw_idx;
4606         int received;
4607         struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
4608
4609         hw_idx = *(tnapi->rx_rcb_prod_idx);
4610         /*
4611          * We need to order the read of hw_idx and the read of
4612          * the opaque cookie.
4613          */
4614         rmb();
4615         work_mask = 0;
4616         received = 0;
4617         std_prod_idx = tpr->rx_std_prod_idx;
4618         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4619         while (sw_idx != hw_idx && budget > 0) {
4620                 struct ring_info *ri;
4621                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4622                 unsigned int len;
4623                 struct sk_buff *skb;
4624                 dma_addr_t dma_addr;
4625                 u32 opaque_key, desc_idx, *post_ptr;
4626                 bool hw_vlan __maybe_unused = false;
4627                 u16 vtag __maybe_unused = 0;
4628
4629                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4630                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4631                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4632                         ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4633                         dma_addr = dma_unmap_addr(ri, mapping);
4634                         skb = ri->skb;
4635                         post_ptr = &std_prod_idx;
4636                         rx_std_posted++;
4637                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4638                         ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4639                         dma_addr = dma_unmap_addr(ri, mapping);
4640                         skb = ri->skb;
4641                         post_ptr = &jmb_prod_idx;
4642                 } else
4643                         goto next_pkt_nopost;
4644
4645                 work_mask |= opaque_key;
4646
4647                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4648                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4649                 drop_it:
4650                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4651                                        desc_idx, *post_ptr);
4652                 drop_it_no_recycle:
4653                         /* Other statistics kept track of by card. */
4654                         tp->net_stats.rx_dropped++;
4655                         goto next_pkt;
4656                 }
4657
4658                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4659                       ETH_FCS_LEN;
4660
4661                 if (len > TG3_RX_COPY_THRESH(tp)) {
4662                         int skb_size;
4663
4664                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4665                                                     *post_ptr);
4666                         if (skb_size < 0)
4667                                 goto drop_it;
4668
4669                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4670                                          PCI_DMA_FROMDEVICE);
4671
4672                         /* Ensure that the update to the skb happens
4673                          * after the usage of the old DMA mapping.
4674                          */
4675                         smp_wmb();
4676
4677                         ri->skb = NULL;
4678
4679                         skb_put(skb, len);
4680                 } else {
4681                         struct sk_buff *copy_skb;
4682
4683                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4684                                        desc_idx, *post_ptr);
4685
4686                         copy_skb = netdev_alloc_skb(tp->dev, len + VLAN_HLEN +
4687                                                     TG3_RAW_IP_ALIGN);
4688                         if (copy_skb == NULL)
4689                                 goto drop_it_no_recycle;
4690
4691                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN + VLAN_HLEN);
4692                         skb_put(copy_skb, len);
4693                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4694                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4695                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4696
4697                         /* We'll reuse the original ring buffer. */
4698                         skb = copy_skb;
4699                 }
4700
4701                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4702                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4703                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4704                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4705                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4706                 else
4707                         skb_checksum_none_assert(skb);
4708
4709                 skb->protocol = eth_type_trans(skb, tp->dev);
4710
4711                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4712                     skb->protocol != htons(ETH_P_8021Q)) {
4713                         dev_kfree_skb(skb);
4714                         goto next_pkt;
4715                 }
4716
4717                 if (desc->type_flags & RXD_FLAG_VLAN &&
4718                     !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) {
4719                         vtag = desc->err_vlan & RXD_VLAN_MASK;
4720 #if TG3_VLAN_TAG_USED
4721                         if (tp->vlgrp)
4722                                 hw_vlan = true;
4723                         else
4724 #endif
4725                         {
4726                                 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
4727                                                     __skb_push(skb, VLAN_HLEN);
4728
4729                                 memmove(ve, skb->data + VLAN_HLEN,
4730                                         ETH_ALEN * 2);
4731                                 ve->h_vlan_proto = htons(ETH_P_8021Q);
4732                                 ve->h_vlan_TCI = htons(vtag);
4733                         }
4734                 }
4735
4736 #if TG3_VLAN_TAG_USED
4737                 if (hw_vlan)
4738                         vlan_gro_receive(&tnapi->napi, tp->vlgrp, vtag, skb);
4739                 else
4740 #endif
4741                         napi_gro_receive(&tnapi->napi, skb);
4742
4743                 received++;
4744                 budget--;
4745
4746 next_pkt:
4747                 (*post_ptr)++;
4748
4749                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4750                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4751                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4752                                      tpr->rx_std_prod_idx);
4753                         work_mask &= ~RXD_OPAQUE_RING_STD;
4754                         rx_std_posted = 0;
4755                 }
4756 next_pkt_nopost:
4757                 sw_idx++;
4758                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4759
4760                 /* Refresh hw_idx to see if there is new work */
4761                 if (sw_idx == hw_idx) {
4762                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4763                         rmb();
4764                 }
4765         }
4766
4767         /* ACK the status ring. */
4768         tnapi->rx_rcb_ptr = sw_idx;
4769         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4770
4771         /* Refill RX ring(s). */
4772         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4773                 if (work_mask & RXD_OPAQUE_RING_STD) {
4774                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4775                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4776                                      tpr->rx_std_prod_idx);
4777                 }
4778                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4779                         tpr->rx_jmb_prod_idx = jmb_prod_idx %
4780                                                TG3_RX_JUMBO_RING_SIZE;
4781                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4782                                      tpr->rx_jmb_prod_idx);
4783                 }
4784                 mmiowb();
4785         } else if (work_mask) {
4786                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4787                  * updated before the producer indices can be updated.
4788                  */
4789                 smp_wmb();
4790
4791                 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4792                 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
4793
4794                 if (tnapi != &tp->napi[1])
4795                         napi_schedule(&tp->napi[1].napi);
4796         }
4797
4798         return received;
4799 }
4800
4801 static void tg3_poll_link(struct tg3 *tp)
4802 {
4803         /* handle link change and other phy events */
4804         if (!(tp->tg3_flags &
4805               (TG3_FLAG_USE_LINKCHG_REG |
4806                TG3_FLAG_POLL_SERDES))) {
4807                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4808
4809                 if (sblk->status & SD_STATUS_LINK_CHG) {
4810                         sblk->status = SD_STATUS_UPDATED |
4811                                        (sblk->status & ~SD_STATUS_LINK_CHG);
4812                         spin_lock(&tp->lock);
4813                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4814                                 tw32_f(MAC_STATUS,
4815                                      (MAC_STATUS_SYNC_CHANGED |
4816                                       MAC_STATUS_CFG_CHANGED |
4817                                       MAC_STATUS_MI_COMPLETION |
4818                                       MAC_STATUS_LNKSTATE_CHANGED));
4819                                 udelay(40);
4820                         } else
4821                                 tg3_setup_phy(tp, 0);
4822                         spin_unlock(&tp->lock);
4823                 }
4824         }
4825 }
4826
4827 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4828                                 struct tg3_rx_prodring_set *dpr,
4829                                 struct tg3_rx_prodring_set *spr)
4830 {
4831         u32 si, di, cpycnt, src_prod_idx;
4832         int i, err = 0;
4833
4834         while (1) {
4835                 src_prod_idx = spr->rx_std_prod_idx;
4836
4837                 /* Make sure updates to the rx_std_buffers[] entries and the
4838                  * standard producer index are seen in the correct order.
4839                  */
4840                 smp_rmb();
4841
4842                 if (spr->rx_std_cons_idx == src_prod_idx)
4843                         break;
4844
4845                 if (spr->rx_std_cons_idx < src_prod_idx)
4846                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4847                 else
4848                         cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4849
4850                 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4851
4852                 si = spr->rx_std_cons_idx;
4853                 di = dpr->rx_std_prod_idx;
4854
4855                 for (i = di; i < di + cpycnt; i++) {
4856                         if (dpr->rx_std_buffers[i].skb) {
4857                                 cpycnt = i - di;
4858                                 err = -ENOSPC;
4859                                 break;
4860                         }
4861                 }
4862
4863                 if (!cpycnt)
4864                         break;
4865
4866                 /* Ensure that updates to the rx_std_buffers ring and the
4867                  * shadowed hardware producer ring from tg3_recycle_skb() are
4868                  * ordered correctly WRT the skb check above.
4869                  */
4870                 smp_rmb();
4871
4872                 memcpy(&dpr->rx_std_buffers[di],
4873                        &spr->rx_std_buffers[si],
4874                        cpycnt * sizeof(struct ring_info));
4875
4876                 for (i = 0; i < cpycnt; i++, di++, si++) {
4877                         struct tg3_rx_buffer_desc *sbd, *dbd;
4878                         sbd = &spr->rx_std[si];
4879                         dbd = &dpr->rx_std[di];
4880                         dbd->addr_hi = sbd->addr_hi;
4881                         dbd->addr_lo = sbd->addr_lo;
4882                 }
4883
4884                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4885                                        TG3_RX_RING_SIZE;
4886                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4887                                        TG3_RX_RING_SIZE;
4888         }
4889
4890         while (1) {
4891                 src_prod_idx = spr->rx_jmb_prod_idx;
4892
4893                 /* Make sure updates to the rx_jmb_buffers[] entries and
4894                  * the jumbo producer index are seen in the correct order.
4895                  */
4896                 smp_rmb();
4897
4898                 if (spr->rx_jmb_cons_idx == src_prod_idx)
4899                         break;
4900
4901                 if (spr->rx_jmb_cons_idx < src_prod_idx)
4902                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4903                 else
4904                         cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4905
4906                 cpycnt = min(cpycnt,
4907                              TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4908
4909                 si = spr->rx_jmb_cons_idx;
4910                 di = dpr->rx_jmb_prod_idx;
4911
4912                 for (i = di; i < di + cpycnt; i++) {
4913                         if (dpr->rx_jmb_buffers[i].skb) {
4914                                 cpycnt = i - di;
4915                                 err = -ENOSPC;
4916                                 break;
4917                         }
4918                 }
4919
4920                 if (!cpycnt)
4921                         break;
4922
4923                 /* Ensure that updates to the rx_jmb_buffers ring and the
4924                  * shadowed hardware producer ring from tg3_recycle_skb() are
4925                  * ordered correctly WRT the skb check above.
4926                  */
4927                 smp_rmb();
4928
4929                 memcpy(&dpr->rx_jmb_buffers[di],
4930                        &spr->rx_jmb_buffers[si],
4931                        cpycnt * sizeof(struct ring_info));
4932
4933                 for (i = 0; i < cpycnt; i++, di++, si++) {
4934                         struct tg3_rx_buffer_desc *sbd, *dbd;
4935                         sbd = &spr->rx_jmb[si].std;
4936                         dbd = &dpr->rx_jmb[di].std;
4937                         dbd->addr_hi = sbd->addr_hi;
4938                         dbd->addr_lo = sbd->addr_lo;
4939                 }
4940
4941                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4942                                        TG3_RX_JUMBO_RING_SIZE;
4943                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4944                                        TG3_RX_JUMBO_RING_SIZE;
4945         }
4946
4947         return err;
4948 }
4949
4950 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4951 {
4952         struct tg3 *tp = tnapi->tp;
4953
4954         /* run TX completion thread */
4955         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4956                 tg3_tx(tnapi);
4957                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4958                         return work_done;
4959         }
4960
4961         /* run RX thread, within the bounds set by NAPI.
4962          * All RX "locking" is done by ensuring outside
4963          * code synchronizes with tg3->napi.poll()
4964          */
4965         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4966                 work_done += tg3_rx(tnapi, budget - work_done);
4967
4968         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4969                 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
4970                 int i, err = 0;
4971                 u32 std_prod_idx = dpr->rx_std_prod_idx;
4972                 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
4973
4974                 for (i = 1; i < tp->irq_cnt; i++)
4975                         err |= tg3_rx_prodring_xfer(tp, dpr,
4976                                                     &tp->napi[i].prodring);
4977
4978                 wmb();
4979
4980                 if (std_prod_idx != dpr->rx_std_prod_idx)
4981                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4982                                      dpr->rx_std_prod_idx);
4983
4984                 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
4985                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4986                                      dpr->rx_jmb_prod_idx);
4987
4988                 mmiowb();
4989
4990                 if (err)
4991                         tw32_f(HOSTCC_MODE, tp->coal_now);
4992         }
4993
4994         return work_done;
4995 }
4996
4997 static int tg3_poll_msix(struct napi_struct *napi, int budget)
4998 {
4999         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5000         struct tg3 *tp = tnapi->tp;
5001         int work_done = 0;
5002         struct tg3_hw_status *sblk = tnapi->hw_status;
5003
5004         while (1) {
5005                 work_done = tg3_poll_work(tnapi, work_done, budget);
5006
5007                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5008                         goto tx_recovery;
5009
5010                 if (unlikely(work_done >= budget))
5011                         break;
5012
5013                 /* tp->last_tag is used in tg3_int_reenable() below
5014                  * to tell the hw how much work has been processed,
5015                  * so we must read it before checking for more work.
5016                  */
5017                 tnapi->last_tag = sblk->status_tag;
5018                 tnapi->last_irq_tag = tnapi->last_tag;
5019                 rmb();
5020
5021                 /* check for RX/TX work to do */
5022                 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5023                            *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5024                         napi_complete(napi);
5025                         /* Reenable interrupts. */
5026                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5027                         mmiowb();
5028                         break;
5029                 }
5030         }
5031
5032         return work_done;
5033
5034 tx_recovery:
5035         /* work_done is guaranteed to be less than budget. */
5036         napi_complete(napi);
5037         schedule_work(&tp->reset_task);
5038         return work_done;
5039 }
5040
5041 static int tg3_poll(struct napi_struct *napi, int budget)
5042 {
5043         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5044         struct tg3 *tp = tnapi->tp;
5045         int work_done = 0;
5046         struct tg3_hw_status *sblk = tnapi->hw_status;
5047
5048         while (1) {
5049                 tg3_poll_link(tp);
5050
5051                 work_done = tg3_poll_work(tnapi, work_done, budget);
5052
5053                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5054                         goto tx_recovery;
5055
5056                 if (unlikely(work_done >= budget))
5057                         break;
5058
5059                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5060                         /* tp->last_tag is used in tg3_int_reenable() below
5061                          * to tell the hw how much work has been processed,
5062                          * so we must read it before checking for more work.
5063                          */
5064                         tnapi->last_tag = sblk->status_tag;
5065                         tnapi->last_irq_tag = tnapi->last_tag;
5066                         rmb();
5067                 } else
5068                         sblk->status &= ~SD_STATUS_UPDATED;
5069
5070                 if (likely(!tg3_has_work(tnapi))) {
5071                         napi_complete(napi);
5072                         tg3_int_reenable(tnapi);
5073                         break;
5074                 }
5075         }
5076
5077         return work_done;
5078
5079 tx_recovery:
5080         /* work_done is guaranteed to be less than budget. */
5081         napi_complete(napi);
5082         schedule_work(&tp->reset_task);
5083         return work_done;
5084 }
5085
5086 static void tg3_irq_quiesce(struct tg3 *tp)
5087 {
5088         int i;
5089
5090         BUG_ON(tp->irq_sync);
5091
5092         tp->irq_sync = 1;
5093         smp_mb();
5094
5095         for (i = 0; i < tp->irq_cnt; i++)
5096                 synchronize_irq(tp->napi[i].irq_vec);
5097 }
5098
5099 static inline int tg3_irq_sync(struct tg3 *tp)
5100 {
5101         return tp->irq_sync;
5102 }
5103
5104 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5105  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5106  * with as well.  Most of the time, this is not necessary except when
5107  * shutting down the device.
5108  */
5109 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5110 {
5111         spin_lock_bh(&tp->lock);
5112         if (irq_sync)
5113                 tg3_irq_quiesce(tp);
5114 }
5115
5116 static inline void tg3_full_unlock(struct tg3 *tp)
5117 {
5118         spin_unlock_bh(&tp->lock);
5119 }
5120
5121 /* One-shot MSI handler - Chip automatically disables interrupt
5122  * after sending MSI so driver doesn't have to do it.
5123  */
5124 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5125 {
5126         struct tg3_napi *tnapi = dev_id;
5127         struct tg3 *tp = tnapi->tp;
5128
5129         prefetch(tnapi->hw_status);
5130         if (tnapi->rx_rcb)
5131                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5132
5133         if (likely(!tg3_irq_sync(tp)))
5134                 napi_schedule(&tnapi->napi);
5135
5136         return IRQ_HANDLED;
5137 }
5138
5139 /* MSI ISR - No need to check for interrupt sharing and no need to
5140  * flush status block and interrupt mailbox. PCI ordering rules
5141  * guarantee that MSI will arrive after the status block.
5142  */
5143 static irqreturn_t tg3_msi(int irq, void *dev_id)
5144 {
5145         struct tg3_napi *tnapi = dev_id;
5146         struct tg3 *tp = tnapi->tp;
5147
5148         prefetch(tnapi->hw_status);
5149         if (tnapi->rx_rcb)
5150                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5151         /*
5152          * Writing any value to intr-mbox-0 clears PCI INTA# and
5153          * chip-internal interrupt pending events.
5154          * Writing non-zero to intr-mbox-0 additional tells the
5155          * NIC to stop sending us irqs, engaging "in-intr-handler"
5156          * event coalescing.
5157          */
5158         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5159         if (likely(!tg3_irq_sync(tp)))
5160                 napi_schedule(&tnapi->napi);
5161
5162         return IRQ_RETVAL(1);
5163 }
5164
5165 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5166 {
5167         struct tg3_napi *tnapi = dev_id;
5168         struct tg3 *tp = tnapi->tp;
5169         struct tg3_hw_status *sblk = tnapi->hw_status;
5170         unsigned int handled = 1;
5171
5172         /* In INTx mode, it is possible for the interrupt to arrive at
5173          * the CPU before the status block posted prior to the interrupt.
5174          * Reading the PCI State register will confirm whether the
5175          * interrupt is ours and will flush the status block.
5176          */
5177         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5178                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5179                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5180                         handled = 0;
5181                         goto out;
5182                 }
5183         }
5184
5185         /*
5186          * Writing any value to intr-mbox-0 clears PCI INTA# and
5187          * chip-internal interrupt pending events.
5188          * Writing non-zero to intr-mbox-0 additional tells the
5189          * NIC to stop sending us irqs, engaging "in-intr-handler"
5190          * event coalescing.
5191          *
5192          * Flush the mailbox to de-assert the IRQ immediately to prevent
5193          * spurious interrupts.  The flush impacts performance but
5194          * excessive spurious interrupts can be worse in some cases.
5195          */
5196         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5197         if (tg3_irq_sync(tp))
5198                 goto out;
5199         sblk->status &= ~SD_STATUS_UPDATED;
5200         if (likely(tg3_has_work(tnapi))) {
5201                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5202                 napi_schedule(&tnapi->napi);
5203         } else {
5204                 /* No work, shared interrupt perhaps?  re-enable
5205                  * interrupts, and flush that PCI write
5206                  */
5207                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5208                                0x00000000);
5209         }
5210 out:
5211         return IRQ_RETVAL(handled);
5212 }
5213
5214 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5215 {
5216         struct tg3_napi *tnapi = dev_id;
5217         struct tg3 *tp = tnapi->tp;
5218         struct tg3_hw_status *sblk = tnapi->hw_status;
5219         unsigned int handled = 1;
5220
5221         /* In INTx mode, it is possible for the interrupt to arrive at
5222          * the CPU before the status block posted prior to the interrupt.
5223          * Reading the PCI State register will confirm whether the
5224          * interrupt is ours and will flush the status block.
5225          */
5226         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5227                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5228                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5229                         handled = 0;
5230                         goto out;
5231                 }
5232         }
5233
5234         /*
5235          * writing any value to intr-mbox-0 clears PCI INTA# and
5236          * chip-internal interrupt pending events.
5237          * writing non-zero to intr-mbox-0 additional tells the
5238          * NIC to stop sending us irqs, engaging "in-intr-handler"
5239          * event coalescing.
5240          *
5241          * Flush the mailbox to de-assert the IRQ immediately to prevent
5242          * spurious interrupts.  The flush impacts performance but
5243          * excessive spurious interrupts can be worse in some cases.
5244          */
5245         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5246
5247         /*
5248          * In a shared interrupt configuration, sometimes other devices'
5249          * interrupts will scream.  We record the current status tag here
5250          * so that the above check can report that the screaming interrupts
5251          * are unhandled.  Eventually they will be silenced.
5252          */
5253         tnapi->last_irq_tag = sblk->status_tag;
5254
5255         if (tg3_irq_sync(tp))
5256                 goto out;
5257
5258         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5259
5260         napi_schedule(&tnapi->napi);
5261
5262 out:
5263         return IRQ_RETVAL(handled);
5264 }
5265
5266 /* ISR for interrupt test */
5267 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5268 {
5269         struct tg3_napi *tnapi = dev_id;
5270         struct tg3 *tp = tnapi->tp;
5271         struct tg3_hw_status *sblk = tnapi->hw_status;
5272
5273         if ((sblk->status & SD_STATUS_UPDATED) ||
5274             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5275                 tg3_disable_ints(tp);
5276                 return IRQ_RETVAL(1);
5277         }
5278         return IRQ_RETVAL(0);
5279 }
5280
5281 static int tg3_init_hw(struct tg3 *, int);
5282 static int tg3_halt(struct tg3 *, int, int);
5283
5284 /* Restart hardware after configuration changes, self-test, etc.
5285  * Invoked with tp->lock held.
5286  */
5287 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5288         __releases(tp->lock)
5289         __acquires(tp->lock)
5290 {
5291         int err;
5292
5293         err = tg3_init_hw(tp, reset_phy);
5294         if (err) {
5295                 netdev_err(tp->dev,
5296                            "Failed to re-initialize device, aborting\n");
5297                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5298                 tg3_full_unlock(tp);
5299                 del_timer_sync(&tp->timer);
5300                 tp->irq_sync = 0;
5301                 tg3_napi_enable(tp);
5302                 dev_close(tp->dev);
5303                 tg3_full_lock(tp, 0);
5304         }
5305         return err;
5306 }
5307
5308 #ifdef CONFIG_NET_POLL_CONTROLLER
5309 static void tg3_poll_controller(struct net_device *dev)
5310 {
5311         int i;
5312         struct tg3 *tp = netdev_priv(dev);
5313
5314         for (i = 0; i < tp->irq_cnt; i++)
5315                 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5316 }
5317 #endif
5318
5319 static void tg3_reset_task(struct work_struct *work)
5320 {
5321         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5322         int err;
5323         unsigned int restart_timer;
5324
5325         tg3_full_lock(tp, 0);
5326
5327         if (!netif_running(tp->dev)) {
5328                 tg3_full_unlock(tp);
5329                 return;
5330         }
5331
5332         tg3_full_unlock(tp);
5333
5334         tg3_phy_stop(tp);
5335
5336         tg3_netif_stop(tp);
5337
5338         tg3_full_lock(tp, 1);
5339
5340         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5341         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5342
5343         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5344                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5345                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5346                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5347                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5348         }
5349
5350         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5351         err = tg3_init_hw(tp, 1);
5352         if (err)
5353                 goto out;
5354
5355         tg3_netif_start(tp);
5356
5357         if (restart_timer)
5358                 mod_timer(&tp->timer, jiffies + 1);
5359
5360 out:
5361         tg3_full_unlock(tp);
5362
5363         if (!err)
5364                 tg3_phy_start(tp);
5365 }
5366
5367 static void tg3_dump_short_state(struct tg3 *tp)
5368 {
5369         netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5370                    tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5371         netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5372                    tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5373 }
5374
5375 static void tg3_tx_timeout(struct net_device *dev)
5376 {
5377         struct tg3 *tp = netdev_priv(dev);
5378
5379         if (netif_msg_tx_err(tp)) {
5380                 netdev_err(dev, "transmit timed out, resetting\n");
5381                 tg3_dump_short_state(tp);
5382         }
5383
5384         schedule_work(&tp->reset_task);
5385 }
5386
5387 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5388 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5389 {
5390         u32 base = (u32) mapping & 0xffffffff;
5391
5392         return ((base > 0xffffdcc0) &&
5393                 (base + len + 8 < base));
5394 }
5395
5396 /* Test for DMA addresses > 40-bit */
5397 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5398                                           int len)
5399 {
5400 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5401         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5402                 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5403         return 0;
5404 #else
5405         return 0;
5406 #endif
5407 }
5408
5409 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5410
5411 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5412 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5413                                        struct sk_buff *skb, u32 last_plus_one,
5414                                        u32 *start, u32 base_flags, u32 mss)
5415 {
5416         struct tg3 *tp = tnapi->tp;
5417         struct sk_buff *new_skb;
5418         dma_addr_t new_addr = 0;
5419         u32 entry = *start;
5420         int i, ret = 0;
5421
5422         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5423                 new_skb = skb_copy(skb, GFP_ATOMIC);
5424         else {
5425                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5426
5427                 new_skb = skb_copy_expand(skb,
5428                                           skb_headroom(skb) + more_headroom,
5429                                           skb_tailroom(skb), GFP_ATOMIC);
5430         }
5431
5432         if (!new_skb) {
5433                 ret = -1;
5434         } else {
5435                 /* New SKB is guaranteed to be linear. */
5436                 entry = *start;
5437                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5438                                           PCI_DMA_TODEVICE);
5439                 /* Make sure the mapping succeeded */
5440                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5441                         ret = -1;
5442                         dev_kfree_skb(new_skb);
5443                         new_skb = NULL;
5444
5445                 /* Make sure new skb does not cross any 4G boundaries.
5446                  * Drop the packet if it does.
5447                  */
5448                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5449                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5450                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5451                                          PCI_DMA_TODEVICE);
5452                         ret = -1;
5453                         dev_kfree_skb(new_skb);
5454                         new_skb = NULL;
5455                 } else {
5456                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5457                                     base_flags, 1 | (mss << 1));
5458                         *start = NEXT_TX(entry);
5459                 }
5460         }
5461
5462         /* Now clean up the sw ring entries. */
5463         i = 0;
5464         while (entry != last_plus_one) {
5465                 int len;
5466
5467                 if (i == 0)
5468                         len = skb_headlen(skb);
5469                 else
5470                         len = skb_shinfo(skb)->frags[i-1].size;
5471
5472                 pci_unmap_single(tp->pdev,
5473                                  dma_unmap_addr(&tnapi->tx_buffers[entry],
5474                                                 mapping),
5475                                  len, PCI_DMA_TODEVICE);
5476                 if (i == 0) {
5477                         tnapi->tx_buffers[entry].skb = new_skb;
5478                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5479                                            new_addr);
5480                 } else {
5481                         tnapi->tx_buffers[entry].skb = NULL;
5482                 }
5483                 entry = NEXT_TX(entry);
5484                 i++;
5485         }
5486
5487         dev_kfree_skb(skb);
5488
5489         return ret;
5490 }
5491
5492 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5493                         dma_addr_t mapping, int len, u32 flags,
5494                         u32 mss_and_is_end)
5495 {
5496         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5497         int is_end = (mss_and_is_end & 0x1);
5498         u32 mss = (mss_and_is_end >> 1);
5499         u32 vlan_tag = 0;
5500
5501         if (is_end)
5502                 flags |= TXD_FLAG_END;
5503         if (flags & TXD_FLAG_VLAN) {
5504                 vlan_tag = flags >> 16;
5505                 flags &= 0xffff;
5506         }
5507         vlan_tag |= (mss << TXD_MSS_SHIFT);
5508
5509         txd->addr_hi = ((u64) mapping >> 32);
5510         txd->addr_lo = ((u64) mapping & 0xffffffff);
5511         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5512         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5513 }
5514
5515 /* hard_start_xmit for devices that don't have any bugs and
5516  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5517  */
5518 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5519                                   struct net_device *dev)
5520 {
5521         struct tg3 *tp = netdev_priv(dev);
5522         u32 len, entry, base_flags, mss;
5523         dma_addr_t mapping;
5524         struct tg3_napi *tnapi;
5525         struct netdev_queue *txq;
5526         unsigned int i, last;
5527
5528         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5529         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5530         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5531                 tnapi++;
5532
5533         /* We are running in BH disabled context with netif_tx_lock
5534          * and TX reclaim runs via tp->napi.poll inside of a software
5535          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5536          * no IRQ context deadlocks to worry about either.  Rejoice!
5537          */
5538         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5539                 if (!netif_tx_queue_stopped(txq)) {
5540                         netif_tx_stop_queue(txq);
5541
5542                         /* This is a hard error, log it. */
5543                         netdev_err(dev,
5544                                    "BUG! Tx Ring full when queue awake!\n");
5545                 }
5546                 return NETDEV_TX_BUSY;
5547         }
5548
5549         entry = tnapi->tx_prod;
5550         base_flags = 0;
5551         mss = skb_shinfo(skb)->gso_size;
5552         if (mss) {
5553                 int tcp_opt_len, ip_tcp_len;
5554                 u32 hdrlen;
5555
5556                 if (skb_header_cloned(skb) &&
5557                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5558                         dev_kfree_skb(skb);
5559                         goto out_unlock;
5560                 }
5561
5562                 if (skb_is_gso_v6(skb)) {
5563                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5564                 } else {
5565                         struct iphdr *iph = ip_hdr(skb);
5566
5567                         tcp_opt_len = tcp_optlen(skb);
5568                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5569
5570                         iph->check = 0;
5571                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5572                         hdrlen = ip_tcp_len + tcp_opt_len;
5573                 }
5574
5575                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5576                         mss |= (hdrlen & 0xc) << 12;
5577                         if (hdrlen & 0x10)
5578                                 base_flags |= 0x00000010;
5579                         base_flags |= (hdrlen & 0x3e0) << 5;
5580                 } else
5581                         mss |= hdrlen << 9;
5582
5583                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5584                                TXD_FLAG_CPU_POST_DMA);
5585
5586                 tcp_hdr(skb)->check = 0;
5587
5588         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5589                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5590         }
5591
5592 #if TG3_VLAN_TAG_USED
5593         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5594                 base_flags |= (TXD_FLAG_VLAN |
5595                                (vlan_tx_tag_get(skb) << 16));
5596 #endif
5597
5598         len = skb_headlen(skb);
5599
5600         /* Queue skb data, a.k.a. the main skb fragment. */
5601         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5602         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5603                 dev_kfree_skb(skb);
5604                 goto out_unlock;
5605         }
5606
5607         tnapi->tx_buffers[entry].skb = skb;
5608         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5609
5610         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5611             !mss && skb->len > ETH_DATA_LEN)
5612                 base_flags |= TXD_FLAG_JMB_PKT;
5613
5614         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5615                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5616
5617         entry = NEXT_TX(entry);
5618
5619         /* Now loop through additional data fragments, and queue them. */
5620         if (skb_shinfo(skb)->nr_frags > 0) {
5621                 last = skb_shinfo(skb)->nr_frags - 1;
5622                 for (i = 0; i <= last; i++) {
5623                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5624
5625                         len = frag->size;
5626                         mapping = pci_map_page(tp->pdev,
5627                                                frag->page,
5628                                                frag->page_offset,
5629                                                len, PCI_DMA_TODEVICE);
5630                         if (pci_dma_mapping_error(tp->pdev, mapping))
5631                                 goto dma_error;
5632
5633                         tnapi->tx_buffers[entry].skb = NULL;
5634                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5635                                            mapping);
5636
5637                         tg3_set_txd(tnapi, entry, mapping, len,
5638                                     base_flags, (i == last) | (mss << 1));
5639
5640                         entry = NEXT_TX(entry);
5641                 }
5642         }
5643
5644         /* Packets are ready, update Tx producer idx local and on card. */
5645         tw32_tx_mbox(tnapi->prodmbox, entry);
5646
5647         tnapi->tx_prod = entry;
5648         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5649                 netif_tx_stop_queue(txq);
5650
5651                 /* netif_tx_stop_queue() must be done before checking
5652                  * checking tx index in tg3_tx_avail() below, because in
5653                  * tg3_tx(), we update tx index before checking for
5654                  * netif_tx_queue_stopped().
5655                  */
5656                 smp_mb();
5657                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5658                         netif_tx_wake_queue(txq);
5659         }
5660
5661 out_unlock:
5662         mmiowb();
5663
5664         return NETDEV_TX_OK;
5665
5666 dma_error:
5667         last = i;
5668         entry = tnapi->tx_prod;
5669         tnapi->tx_buffers[entry].skb = NULL;
5670         pci_unmap_single(tp->pdev,
5671                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5672                          skb_headlen(skb),
5673                          PCI_DMA_TODEVICE);
5674         for (i = 0; i <= last; i++) {
5675                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5676                 entry = NEXT_TX(entry);
5677
5678                 pci_unmap_page(tp->pdev,
5679                                dma_unmap_addr(&tnapi->tx_buffers[entry],
5680                                               mapping),
5681                                frag->size, PCI_DMA_TODEVICE);
5682         }
5683
5684         dev_kfree_skb(skb);
5685         return NETDEV_TX_OK;
5686 }
5687
5688 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5689                                           struct net_device *);
5690
5691 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5692  * TSO header is greater than 80 bytes.
5693  */
5694 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5695 {
5696         struct sk_buff *segs, *nskb;
5697         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5698
5699         /* Estimate the number of fragments in the worst case */
5700         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5701                 netif_stop_queue(tp->dev);
5702
5703                 /* netif_tx_stop_queue() must be done before checking
5704                  * checking tx index in tg3_tx_avail() below, because in
5705                  * tg3_tx(), we update tx index before checking for
5706                  * netif_tx_queue_stopped().
5707                  */
5708                 smp_mb();
5709                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5710                         return NETDEV_TX_BUSY;
5711
5712                 netif_wake_queue(tp->dev);
5713         }
5714
5715         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5716         if (IS_ERR(segs))
5717                 goto tg3_tso_bug_end;
5718
5719         do {
5720                 nskb = segs;
5721                 segs = segs->next;
5722                 nskb->next = NULL;
5723                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5724         } while (segs);
5725
5726 tg3_tso_bug_end:
5727         dev_kfree_skb(skb);
5728
5729         return NETDEV_TX_OK;
5730 }
5731
5732 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5733  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5734  */
5735 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5736                                           struct net_device *dev)
5737 {
5738         struct tg3 *tp = netdev_priv(dev);
5739         u32 len, entry, base_flags, mss;
5740         int would_hit_hwbug;
5741         dma_addr_t mapping;
5742         struct tg3_napi *tnapi;
5743         struct netdev_queue *txq;
5744         unsigned int i, last;
5745
5746         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5747         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5748         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5749                 tnapi++;
5750
5751         /* We are running in BH disabled context with netif_tx_lock
5752          * and TX reclaim runs via tp->napi.poll inside of a software
5753          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5754          * no IRQ context deadlocks to worry about either.  Rejoice!
5755          */
5756         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5757                 if (!netif_tx_queue_stopped(txq)) {
5758                         netif_tx_stop_queue(txq);
5759
5760                         /* This is a hard error, log it. */
5761                         netdev_err(dev,
5762                                    "BUG! Tx Ring full when queue awake!\n");
5763                 }
5764                 return NETDEV_TX_BUSY;
5765         }
5766
5767         entry = tnapi->tx_prod;
5768         base_flags = 0;
5769         if (skb->ip_summed == CHECKSUM_PARTIAL)
5770                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5771
5772         mss = skb_shinfo(skb)->gso_size;
5773         if (mss) {
5774                 struct iphdr *iph;
5775                 u32 tcp_opt_len, hdr_len;
5776
5777                 if (skb_header_cloned(skb) &&
5778                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5779                         dev_kfree_skb(skb);
5780                         goto out_unlock;
5781                 }
5782
5783                 iph = ip_hdr(skb);
5784                 tcp_opt_len = tcp_optlen(skb);
5785
5786                 if (skb_is_gso_v6(skb)) {
5787                         hdr_len = skb_headlen(skb) - ETH_HLEN;
5788                 } else {
5789                         u32 ip_tcp_len;
5790
5791                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5792                         hdr_len = ip_tcp_len + tcp_opt_len;
5793
5794                         iph->check = 0;
5795                         iph->tot_len = htons(mss + hdr_len);
5796                 }
5797
5798                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5799                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5800                         return tg3_tso_bug(tp, skb);
5801
5802                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5803                                TXD_FLAG_CPU_POST_DMA);
5804
5805                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5806                         tcp_hdr(skb)->check = 0;
5807                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5808                 } else
5809                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5810                                                                  iph->daddr, 0,
5811                                                                  IPPROTO_TCP,
5812                                                                  0);
5813
5814                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5815                         mss |= (hdr_len & 0xc) << 12;
5816                         if (hdr_len & 0x10)
5817                                 base_flags |= 0x00000010;
5818                         base_flags |= (hdr_len & 0x3e0) << 5;
5819                 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5820                         mss |= hdr_len << 9;
5821                 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5822                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5823                         if (tcp_opt_len || iph->ihl > 5) {
5824                                 int tsflags;
5825
5826                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5827                                 mss |= (tsflags << 11);
5828                         }
5829                 } else {
5830                         if (tcp_opt_len || iph->ihl > 5) {
5831                                 int tsflags;
5832
5833                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5834                                 base_flags |= tsflags << 12;
5835                         }
5836                 }
5837         }
5838 #if TG3_VLAN_TAG_USED
5839         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5840                 base_flags |= (TXD_FLAG_VLAN |
5841                                (vlan_tx_tag_get(skb) << 16));
5842 #endif
5843
5844         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5845             !mss && skb->len > ETH_DATA_LEN)
5846                 base_flags |= TXD_FLAG_JMB_PKT;
5847
5848         len = skb_headlen(skb);
5849
5850         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5851         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5852                 dev_kfree_skb(skb);
5853                 goto out_unlock;
5854         }
5855
5856         tnapi->tx_buffers[entry].skb = skb;
5857         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5858
5859         would_hit_hwbug = 0;
5860
5861         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5862                 would_hit_hwbug = 1;
5863
5864         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5865             tg3_4g_overflow_test(mapping, len))
5866                 would_hit_hwbug = 1;
5867
5868         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5869             tg3_40bit_overflow_test(tp, mapping, len))
5870                 would_hit_hwbug = 1;
5871
5872         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5873                 would_hit_hwbug = 1;
5874
5875         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5876                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5877
5878         entry = NEXT_TX(entry);
5879
5880         /* Now loop through additional data fragments, and queue them. */
5881         if (skb_shinfo(skb)->nr_frags > 0) {
5882                 last = skb_shinfo(skb)->nr_frags - 1;
5883                 for (i = 0; i <= last; i++) {
5884                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5885
5886                         len = frag->size;
5887                         mapping = pci_map_page(tp->pdev,
5888                                                frag->page,
5889                                                frag->page_offset,
5890                                                len, PCI_DMA_TODEVICE);
5891
5892                         tnapi->tx_buffers[entry].skb = NULL;
5893                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5894                                            mapping);
5895                         if (pci_dma_mapping_error(tp->pdev, mapping))
5896                                 goto dma_error;
5897
5898                         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5899                             len <= 8)
5900                                 would_hit_hwbug = 1;
5901
5902                         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5903                             tg3_4g_overflow_test(mapping, len))
5904                                 would_hit_hwbug = 1;
5905
5906                         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5907                             tg3_40bit_overflow_test(tp, mapping, len))
5908                                 would_hit_hwbug = 1;
5909
5910                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5911                                 tg3_set_txd(tnapi, entry, mapping, len,
5912                                             base_flags, (i == last)|(mss << 1));
5913                         else
5914                                 tg3_set_txd(tnapi, entry, mapping, len,
5915                                             base_flags, (i == last));
5916
5917                         entry = NEXT_TX(entry);
5918                 }
5919         }
5920
5921         if (would_hit_hwbug) {
5922                 u32 last_plus_one = entry;
5923                 u32 start;
5924
5925                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5926                 start &= (TG3_TX_RING_SIZE - 1);
5927
5928                 /* If the workaround fails due to memory/mapping
5929                  * failure, silently drop this packet.
5930                  */
5931                 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
5932                                                 &start, base_flags, mss))
5933                         goto out_unlock;
5934
5935                 entry = start;
5936         }
5937
5938         /* Packets are ready, update Tx producer idx local and on card. */
5939         tw32_tx_mbox(tnapi->prodmbox, entry);
5940
5941         tnapi->tx_prod = entry;
5942         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5943                 netif_tx_stop_queue(txq);
5944
5945                 /* netif_tx_stop_queue() must be done before checking
5946                  * checking tx index in tg3_tx_avail() below, because in
5947                  * tg3_tx(), we update tx index before checking for
5948                  * netif_tx_queue_stopped().
5949                  */
5950                 smp_mb();
5951                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5952                         netif_tx_wake_queue(txq);
5953         }
5954
5955 out_unlock:
5956         mmiowb();
5957
5958         return NETDEV_TX_OK;
5959
5960 dma_error:
5961         last = i;
5962         entry = tnapi->tx_prod;
5963         tnapi->tx_buffers[entry].skb = NULL;
5964         pci_unmap_single(tp->pdev,
5965                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5966                          skb_headlen(skb),
5967                          PCI_DMA_TODEVICE);
5968         for (i = 0; i <= last; i++) {
5969                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5970                 entry = NEXT_TX(entry);
5971
5972                 pci_unmap_page(tp->pdev,
5973                                dma_unmap_addr(&tnapi->tx_buffers[entry],
5974                                               mapping),
5975                                frag->size, PCI_DMA_TODEVICE);
5976         }
5977
5978         dev_kfree_skb(skb);
5979         return NETDEV_TX_OK;
5980 }
5981
5982 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5983                                int new_mtu)
5984 {
5985         dev->mtu = new_mtu;
5986
5987         if (new_mtu > ETH_DATA_LEN) {
5988                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5989                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5990                         ethtool_op_set_tso(dev, 0);
5991                 } else {
5992                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5993                 }
5994         } else {
5995                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5996                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5997                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5998         }
5999 }
6000
6001 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
6002 {
6003         struct tg3 *tp = netdev_priv(dev);
6004         int err;
6005
6006         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
6007                 return -EINVAL;
6008
6009         if (!netif_running(dev)) {
6010                 /* We'll just catch it later when the
6011                  * device is up'd.
6012                  */
6013                 tg3_set_mtu(dev, tp, new_mtu);
6014                 return 0;
6015         }
6016
6017         tg3_phy_stop(tp);
6018
6019         tg3_netif_stop(tp);
6020
6021         tg3_full_lock(tp, 1);
6022
6023         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6024
6025         tg3_set_mtu(dev, tp, new_mtu);
6026
6027         err = tg3_restart_hw(tp, 0);
6028
6029         if (!err)
6030                 tg3_netif_start(tp);
6031
6032         tg3_full_unlock(tp);
6033
6034         if (!err)
6035                 tg3_phy_start(tp);
6036
6037         return err;
6038 }
6039
6040 static void tg3_rx_prodring_free(struct tg3 *tp,
6041                                  struct tg3_rx_prodring_set *tpr)
6042 {
6043         int i;
6044
6045         if (tpr != &tp->napi[0].prodring) {
6046                 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
6047                      i = (i + 1) % TG3_RX_RING_SIZE)
6048                         tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6049                                         tp->rx_pkt_map_sz);
6050
6051                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6052                         for (i = tpr->rx_jmb_cons_idx;
6053                              i != tpr->rx_jmb_prod_idx;
6054                              i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
6055                                 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6056                                                 TG3_RX_JMB_MAP_SZ);
6057                         }
6058                 }
6059
6060                 return;
6061         }
6062
6063         for (i = 0; i < TG3_RX_RING_SIZE; i++)
6064                 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6065                                 tp->rx_pkt_map_sz);
6066
6067         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6068                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
6069                         tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6070                                         TG3_RX_JMB_MAP_SZ);
6071         }
6072 }
6073
6074 /* Initialize rx rings for packet processing.
6075  *
6076  * The chip has been shut down and the driver detached from
6077  * the networking, so no interrupts or new tx packets will
6078  * end up in the driver.  tp->{tx,}lock are held and thus
6079  * we may not sleep.
6080  */
6081 static int tg3_rx_prodring_alloc(struct tg3 *tp,
6082                                  struct tg3_rx_prodring_set *tpr)
6083 {
6084         u32 i, rx_pkt_dma_sz;
6085
6086         tpr->rx_std_cons_idx = 0;
6087         tpr->rx_std_prod_idx = 0;
6088         tpr->rx_jmb_cons_idx = 0;
6089         tpr->rx_jmb_prod_idx = 0;
6090
6091         if (tpr != &tp->napi[0].prodring) {
6092                 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
6093                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
6094                         memset(&tpr->rx_jmb_buffers[0], 0,
6095                                TG3_RX_JMB_BUFF_RING_SIZE);
6096                 goto done;
6097         }
6098
6099         /* Zero out all descriptors. */
6100         memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
6101
6102         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6103         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
6104             tp->dev->mtu > ETH_DATA_LEN)
6105                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6106         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6107
6108         /* Initialize invariants of the rings, we only set this
6109          * stuff once.  This works because the card does not
6110          * write into the rx buffer posting rings.
6111          */
6112         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
6113                 struct tg3_rx_buffer_desc *rxd;
6114
6115                 rxd = &tpr->rx_std[i];
6116                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6117                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6118                 rxd->opaque = (RXD_OPAQUE_RING_STD |
6119                                (i << RXD_OPAQUE_INDEX_SHIFT));
6120         }
6121
6122         /* Now allocate fresh SKBs for each rx ring. */
6123         for (i = 0; i < tp->rx_pending; i++) {
6124                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6125                         netdev_warn(tp->dev,
6126                                     "Using a smaller RX standard ring. Only "
6127                                     "%d out of %d buffers were allocated "
6128                                     "successfully\n", i, tp->rx_pending);
6129                         if (i == 0)
6130                                 goto initfail;
6131                         tp->rx_pending = i;
6132                         break;
6133                 }
6134         }
6135
6136         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6137                 goto done;
6138
6139         memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
6140
6141         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
6142                 goto done;
6143
6144         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
6145                 struct tg3_rx_buffer_desc *rxd;
6146
6147                 rxd = &tpr->rx_jmb[i].std;
6148                 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6149                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6150                                   RXD_FLAG_JUMBO;
6151                 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6152                        (i << RXD_OPAQUE_INDEX_SHIFT));
6153         }
6154
6155         for (i = 0; i < tp->rx_jumbo_pending; i++) {
6156                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
6157                         netdev_warn(tp->dev,
6158                                     "Using a smaller RX jumbo ring. Only %d "
6159                                     "out of %d buffers were allocated "
6160                                     "successfully\n", i, tp->rx_jumbo_pending);
6161                         if (i == 0)
6162                                 goto initfail;
6163                         tp->rx_jumbo_pending = i;
6164                         break;
6165                 }
6166         }
6167
6168 done:
6169         return 0;
6170
6171 initfail:
6172         tg3_rx_prodring_free(tp, tpr);
6173         return -ENOMEM;
6174 }
6175
6176 static void tg3_rx_prodring_fini(struct tg3 *tp,
6177                                  struct tg3_rx_prodring_set *tpr)
6178 {
6179         kfree(tpr->rx_std_buffers);
6180         tpr->rx_std_buffers = NULL;
6181         kfree(tpr->rx_jmb_buffers);
6182         tpr->rx_jmb_buffers = NULL;
6183         if (tpr->rx_std) {
6184                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
6185                                     tpr->rx_std, tpr->rx_std_mapping);
6186                 tpr->rx_std = NULL;
6187         }
6188         if (tpr->rx_jmb) {
6189                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
6190                                     tpr->rx_jmb, tpr->rx_jmb_mapping);
6191                 tpr->rx_jmb = NULL;
6192         }
6193 }
6194
6195 static int tg3_rx_prodring_init(struct tg3 *tp,
6196                                 struct tg3_rx_prodring_set *tpr)
6197 {
6198         tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
6199         if (!tpr->rx_std_buffers)
6200                 return -ENOMEM;
6201
6202         tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6203                                            &tpr->rx_std_mapping);
6204         if (!tpr->rx_std)
6205                 goto err_out;
6206
6207         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6208                 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
6209                                               GFP_KERNEL);
6210                 if (!tpr->rx_jmb_buffers)
6211                         goto err_out;
6212
6213                 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6214                                                    TG3_RX_JUMBO_RING_BYTES,
6215                                                    &tpr->rx_jmb_mapping);
6216                 if (!tpr->rx_jmb)
6217                         goto err_out;
6218         }
6219
6220         return 0;
6221
6222 err_out:
6223         tg3_rx_prodring_fini(tp, tpr);
6224         return -ENOMEM;
6225 }
6226
6227 /* Free up pending packets in all rx/tx rings.
6228  *
6229  * The chip has been shut down and the driver detached from
6230  * the networking, so no interrupts or new tx packets will
6231  * end up in the driver.  tp->{tx,}lock is not held and we are not
6232  * in an interrupt context and thus may sleep.
6233  */
6234 static void tg3_free_rings(struct tg3 *tp)
6235 {
6236         int i, j;
6237
6238         for (j = 0; j < tp->irq_cnt; j++) {
6239                 struct tg3_napi *tnapi = &tp->napi[j];
6240
6241                 tg3_rx_prodring_free(tp, &tnapi->prodring);
6242
6243                 if (!tnapi->tx_buffers)
6244                         continue;
6245
6246                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6247                         struct ring_info *txp;
6248                         struct sk_buff *skb;
6249                         unsigned int k;
6250
6251                         txp = &tnapi->tx_buffers[i];
6252                         skb = txp->skb;
6253
6254                         if (skb == NULL) {
6255                                 i++;
6256                                 continue;
6257                         }
6258
6259                         pci_unmap_single(tp->pdev,
6260                                          dma_unmap_addr(txp, mapping),
6261                                          skb_headlen(skb),
6262                                          PCI_DMA_TODEVICE);
6263                         txp->skb = NULL;
6264
6265                         i++;
6266
6267                         for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6268                                 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6269                                 pci_unmap_page(tp->pdev,
6270                                                dma_unmap_addr(txp, mapping),
6271                                                skb_shinfo(skb)->frags[k].size,
6272                                                PCI_DMA_TODEVICE);
6273                                 i++;
6274                         }
6275
6276                         dev_kfree_skb_any(skb);
6277                 }
6278         }
6279 }
6280
6281 /* Initialize tx/rx rings for packet processing.
6282  *
6283  * The chip has been shut down and the driver detached from
6284  * the networking, so no interrupts or new tx packets will
6285  * end up in the driver.  tp->{tx,}lock are held and thus
6286  * we may not sleep.
6287  */
6288 static int tg3_init_rings(struct tg3 *tp)
6289 {
6290         int i;
6291
6292         /* Free up all the SKBs. */
6293         tg3_free_rings(tp);
6294
6295         for (i = 0; i < tp->irq_cnt; i++) {
6296                 struct tg3_napi *tnapi = &tp->napi[i];
6297
6298                 tnapi->last_tag = 0;
6299                 tnapi->last_irq_tag = 0;
6300                 tnapi->hw_status->status = 0;
6301                 tnapi->hw_status->status_tag = 0;
6302                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6303
6304                 tnapi->tx_prod = 0;
6305                 tnapi->tx_cons = 0;
6306                 if (tnapi->tx_ring)
6307                         memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6308
6309                 tnapi->rx_rcb_ptr = 0;
6310                 if (tnapi->rx_rcb)
6311                         memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6312
6313                 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
6314                         tg3_free_rings(tp);
6315                         return -ENOMEM;
6316                 }
6317         }
6318
6319         return 0;
6320 }
6321
6322 /*
6323  * Must not be invoked with interrupt sources disabled and
6324  * the hardware shutdown down.
6325  */
6326 static void tg3_free_consistent(struct tg3 *tp)
6327 {
6328         int i;
6329
6330         for (i = 0; i < tp->irq_cnt; i++) {
6331                 struct tg3_napi *tnapi = &tp->napi[i];
6332
6333                 if (tnapi->tx_ring) {
6334                         pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6335                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
6336                         tnapi->tx_ring = NULL;
6337                 }
6338
6339                 kfree(tnapi->tx_buffers);
6340                 tnapi->tx_buffers = NULL;
6341
6342                 if (tnapi->rx_rcb) {
6343                         pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6344                                             tnapi->rx_rcb,
6345                                             tnapi->rx_rcb_mapping);
6346                         tnapi->rx_rcb = NULL;
6347                 }
6348
6349                 tg3_rx_prodring_fini(tp, &tnapi->prodring);
6350
6351                 if (tnapi->hw_status) {
6352                         pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6353                                             tnapi->hw_status,
6354                                             tnapi->status_mapping);
6355                         tnapi->hw_status = NULL;
6356                 }
6357         }
6358
6359         if (tp->hw_stats) {
6360                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6361                                     tp->hw_stats, tp->stats_mapping);
6362                 tp->hw_stats = NULL;
6363         }
6364 }
6365
6366 /*
6367  * Must not be invoked with interrupt sources disabled and
6368  * the hardware shutdown down.  Can sleep.
6369  */
6370 static int tg3_alloc_consistent(struct tg3 *tp)
6371 {
6372         int i;
6373
6374         tp->hw_stats = pci_alloc_consistent(tp->pdev,
6375                                             sizeof(struct tg3_hw_stats),
6376                                             &tp->stats_mapping);
6377         if (!tp->hw_stats)
6378                 goto err_out;
6379
6380         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6381
6382         for (i = 0; i < tp->irq_cnt; i++) {
6383                 struct tg3_napi *tnapi = &tp->napi[i];
6384                 struct tg3_hw_status *sblk;
6385
6386                 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6387                                                         TG3_HW_STATUS_SIZE,
6388                                                         &tnapi->status_mapping);
6389                 if (!tnapi->hw_status)
6390                         goto err_out;
6391
6392                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6393                 sblk = tnapi->hw_status;
6394
6395                 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
6396                         goto err_out;
6397
6398                 /* If multivector TSS is enabled, vector 0 does not handle
6399                  * tx interrupts.  Don't allocate any resources for it.
6400                  */
6401                 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6402                     (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6403                         tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6404                                                     TG3_TX_RING_SIZE,
6405                                                     GFP_KERNEL);
6406                         if (!tnapi->tx_buffers)
6407                                 goto err_out;
6408
6409                         tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6410                                                               TG3_TX_RING_BYTES,
6411                                                        &tnapi->tx_desc_mapping);
6412                         if (!tnapi->tx_ring)
6413                                 goto err_out;
6414                 }
6415
6416                 /*
6417                  * When RSS is enabled, the status block format changes
6418                  * slightly.  The "rx_jumbo_consumer", "reserved",
6419                  * and "rx_mini_consumer" members get mapped to the
6420                  * other three rx return ring producer indexes.
6421                  */
6422                 switch (i) {
6423                 default:
6424                         tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6425                         break;
6426                 case 2:
6427                         tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6428                         break;
6429                 case 3:
6430                         tnapi->rx_rcb_prod_idx = &sblk->reserved;
6431                         break;
6432                 case 4:
6433                         tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6434                         break;
6435                 }
6436
6437                 /*
6438                  * If multivector RSS is enabled, vector 0 does not handle
6439                  * rx or tx interrupts.  Don't allocate any resources for it.
6440                  */
6441                 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6442                         continue;
6443
6444                 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6445                                                      TG3_RX_RCB_RING_BYTES(tp),
6446                                                      &tnapi->rx_rcb_mapping);
6447                 if (!tnapi->rx_rcb)
6448                         goto err_out;
6449
6450                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6451         }
6452
6453         return 0;
6454
6455 err_out:
6456         tg3_free_consistent(tp);
6457         return -ENOMEM;
6458 }
6459
6460 #define MAX_WAIT_CNT 1000
6461
6462 /* To stop a block, clear the enable bit and poll till it
6463  * clears.  tp->lock is held.
6464  */
6465 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6466 {
6467         unsigned int i;
6468         u32 val;
6469
6470         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6471                 switch (ofs) {
6472                 case RCVLSC_MODE:
6473                 case DMAC_MODE:
6474                 case MBFREE_MODE:
6475                 case BUFMGR_MODE:
6476                 case MEMARB_MODE:
6477                         /* We can't enable/disable these bits of the
6478                          * 5705/5750, just say success.
6479                          */
6480                         return 0;
6481
6482                 default:
6483                         break;
6484                 }
6485         }
6486
6487         val = tr32(ofs);
6488         val &= ~enable_bit;
6489         tw32_f(ofs, val);
6490
6491         for (i = 0; i < MAX_WAIT_CNT; i++) {
6492                 udelay(100);
6493                 val = tr32(ofs);
6494                 if ((val & enable_bit) == 0)
6495                         break;
6496         }
6497
6498         if (i == MAX_WAIT_CNT && !silent) {
6499                 dev_err(&tp->pdev->dev,
6500                         "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6501                         ofs, enable_bit);
6502                 return -ENODEV;
6503         }
6504
6505         return 0;
6506 }
6507
6508 /* tp->lock is held. */
6509 static int tg3_abort_hw(struct tg3 *tp, int silent)
6510 {
6511         int i, err;
6512
6513         tg3_disable_ints(tp);
6514
6515         tp->rx_mode &= ~RX_MODE_ENABLE;
6516         tw32_f(MAC_RX_MODE, tp->rx_mode);
6517         udelay(10);
6518
6519         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6520         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6521         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6522         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6523         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6524         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6525
6526         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6527         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6528         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6529         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6530         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6531         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6532         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6533
6534         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6535         tw32_f(MAC_MODE, tp->mac_mode);
6536         udelay(40);
6537
6538         tp->tx_mode &= ~TX_MODE_ENABLE;
6539         tw32_f(MAC_TX_MODE, tp->tx_mode);
6540
6541         for (i = 0; i < MAX_WAIT_CNT; i++) {
6542                 udelay(100);
6543                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6544                         break;
6545         }
6546         if (i >= MAX_WAIT_CNT) {
6547                 dev_err(&tp->pdev->dev,
6548                         "%s timed out, TX_MODE_ENABLE will not clear "
6549                         "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
6550                 err |= -ENODEV;
6551         }
6552
6553         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6554         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6555         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6556
6557         tw32(FTQ_RESET, 0xffffffff);
6558         tw32(FTQ_RESET, 0x00000000);
6559
6560         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6561         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6562
6563         for (i = 0; i < tp->irq_cnt; i++) {
6564                 struct tg3_napi *tnapi = &tp->napi[i];
6565                 if (tnapi->hw_status)
6566                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6567         }
6568         if (tp->hw_stats)
6569                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6570
6571         return err;
6572 }
6573
6574 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6575 {
6576         int i;
6577         u32 apedata;
6578
6579         /* NCSI does not support APE events */
6580         if (tp->tg3_flags3 & TG3_FLG3_APE_HAS_NCSI)
6581                 return;
6582
6583         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6584         if (apedata != APE_SEG_SIG_MAGIC)
6585                 return;
6586
6587         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6588         if (!(apedata & APE_FW_STATUS_READY))
6589                 return;
6590
6591         /* Wait for up to 1 millisecond for APE to service previous event. */
6592         for (i = 0; i < 10; i++) {
6593                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6594                         return;
6595
6596                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6597
6598                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6599                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6600                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6601
6602                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6603
6604                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6605                         break;
6606
6607                 udelay(100);
6608         }
6609
6610         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6611                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6612 }
6613
6614 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6615 {
6616         u32 event;
6617         u32 apedata;
6618
6619         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6620                 return;
6621
6622         switch (kind) {
6623         case RESET_KIND_INIT:
6624                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6625                                 APE_HOST_SEG_SIG_MAGIC);
6626                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6627                                 APE_HOST_SEG_LEN_MAGIC);
6628                 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6629                 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6630                 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6631                         APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
6632                 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6633                                 APE_HOST_BEHAV_NO_PHYLOCK);
6634                 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
6635                                     TG3_APE_HOST_DRVR_STATE_START);
6636
6637                 event = APE_EVENT_STATUS_STATE_START;
6638                 break;
6639         case RESET_KIND_SHUTDOWN:
6640                 /* With the interface we are currently using,
6641                  * APE does not track driver state.  Wiping
6642                  * out the HOST SEGMENT SIGNATURE forces
6643                  * the APE to assume OS absent status.
6644                  */
6645                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6646
6647                 if (device_may_wakeup(&tp->pdev->dev) &&
6648                     (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) {
6649                         tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
6650                                             TG3_APE_HOST_WOL_SPEED_AUTO);
6651                         apedata = TG3_APE_HOST_DRVR_STATE_WOL;
6652                 } else
6653                         apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
6654
6655                 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
6656
6657                 event = APE_EVENT_STATUS_STATE_UNLOAD;
6658                 break;
6659         case RESET_KIND_SUSPEND:
6660                 event = APE_EVENT_STATUS_STATE_SUSPEND;
6661                 break;
6662         default:
6663                 return;
6664         }
6665
6666         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6667
6668         tg3_ape_send_event(tp, event);
6669 }
6670
6671 /* tp->lock is held. */
6672 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6673 {
6674         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6675                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6676
6677         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6678                 switch (kind) {
6679                 case RESET_KIND_INIT:
6680                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6681                                       DRV_STATE_START);
6682                         break;
6683
6684                 case RESET_KIND_SHUTDOWN:
6685                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6686                                       DRV_STATE_UNLOAD);
6687                         break;
6688
6689                 case RESET_KIND_SUSPEND:
6690                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6691                                       DRV_STATE_SUSPEND);
6692                         break;
6693
6694                 default:
6695                         break;
6696                 }
6697         }
6698
6699         if (kind == RESET_KIND_INIT ||
6700             kind == RESET_KIND_SUSPEND)
6701                 tg3_ape_driver_state_change(tp, kind);
6702 }
6703
6704 /* tp->lock is held. */
6705 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6706 {
6707         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6708                 switch (kind) {
6709                 case RESET_KIND_INIT:
6710                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6711                                       DRV_STATE_START_DONE);
6712                         break;
6713
6714                 case RESET_KIND_SHUTDOWN:
6715                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6716                                       DRV_STATE_UNLOAD_DONE);
6717                         break;
6718
6719                 default:
6720                         break;
6721                 }
6722         }
6723
6724         if (kind == RESET_KIND_SHUTDOWN)
6725                 tg3_ape_driver_state_change(tp, kind);
6726 }
6727
6728 /* tp->lock is held. */
6729 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6730 {
6731         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6732                 switch (kind) {
6733                 case RESET_KIND_INIT:
6734                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6735                                       DRV_STATE_START);
6736                         break;
6737
6738                 case RESET_KIND_SHUTDOWN:
6739                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6740                                       DRV_STATE_UNLOAD);
6741                         break;
6742
6743                 case RESET_KIND_SUSPEND:
6744                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6745                                       DRV_STATE_SUSPEND);
6746                         break;
6747
6748                 default:
6749                         break;
6750                 }
6751         }
6752 }
6753
6754 static int tg3_poll_fw(struct tg3 *tp)
6755 {
6756         int i;
6757         u32 val;
6758
6759         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6760                 /* Wait up to 20ms for init done. */
6761                 for (i = 0; i < 200; i++) {
6762                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6763                                 return 0;
6764                         udelay(100);
6765                 }
6766                 return -ENODEV;
6767         }
6768
6769         /* Wait for firmware initialization to complete. */
6770         for (i = 0; i < 100000; i++) {
6771                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6772                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6773                         break;
6774                 udelay(10);
6775         }
6776
6777         /* Chip might not be fitted with firmware.  Some Sun onboard
6778          * parts are configured like that.  So don't signal the timeout
6779          * of the above loop as an error, but do report the lack of
6780          * running firmware once.
6781          */
6782         if (i >= 100000 &&
6783             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6784                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6785
6786                 netdev_info(tp->dev, "No firmware running\n");
6787         }
6788
6789         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6790                 /* The 57765 A0 needs a little more
6791                  * time to do some important work.
6792                  */
6793                 mdelay(10);
6794         }
6795
6796         return 0;
6797 }
6798
6799 /* Save PCI command register before chip reset */
6800 static void tg3_save_pci_state(struct tg3 *tp)
6801 {
6802         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6803 }
6804
6805 /* Restore PCI state after chip reset */
6806 static void tg3_restore_pci_state(struct tg3 *tp)
6807 {
6808         u32 val;
6809
6810         /* Re-enable indirect register accesses. */
6811         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6812                                tp->misc_host_ctrl);
6813
6814         /* Set MAX PCI retry to zero. */
6815         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6816         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6817             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6818                 val |= PCISTATE_RETRY_SAME_DMA;
6819         /* Allow reads and writes to the APE register and memory space. */
6820         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6821                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6822                        PCISTATE_ALLOW_APE_SHMEM_WR |
6823                        PCISTATE_ALLOW_APE_PSPACE_WR;
6824         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6825
6826         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6827
6828         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6829                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6830                         pcie_set_readrq(tp->pdev, 4096);
6831                 else {
6832                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6833                                               tp->pci_cacheline_sz);
6834                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6835                                               tp->pci_lat_timer);
6836                 }
6837         }
6838
6839         /* Make sure PCI-X relaxed ordering bit is clear. */
6840         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6841                 u16 pcix_cmd;
6842
6843                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6844                                      &pcix_cmd);
6845                 pcix_cmd &= ~PCI_X_CMD_ERO;
6846                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6847                                       pcix_cmd);
6848         }
6849
6850         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6851
6852                 /* Chip reset on 5780 will reset MSI enable bit,
6853                  * so need to restore it.
6854                  */
6855                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6856                         u16 ctrl;
6857
6858                         pci_read_config_word(tp->pdev,
6859                                              tp->msi_cap + PCI_MSI_FLAGS,
6860                                              &ctrl);
6861                         pci_write_config_word(tp->pdev,
6862                                               tp->msi_cap + PCI_MSI_FLAGS,
6863                                               ctrl | PCI_MSI_FLAGS_ENABLE);
6864                         val = tr32(MSGINT_MODE);
6865                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6866                 }
6867         }
6868 }
6869
6870 static void tg3_stop_fw(struct tg3 *);
6871
6872 /* tp->lock is held. */
6873 static int tg3_chip_reset(struct tg3 *tp)
6874 {
6875         u32 val;
6876         void (*write_op)(struct tg3 *, u32, u32);
6877         int i, err;
6878
6879         tg3_nvram_lock(tp);
6880
6881         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6882
6883         /* No matching tg3_nvram_unlock() after this because
6884          * chip reset below will undo the nvram lock.
6885          */
6886         tp->nvram_lock_cnt = 0;
6887
6888         /* GRC_MISC_CFG core clock reset will clear the memory
6889          * enable bit in PCI register 4 and the MSI enable bit
6890          * on some chips, so we save relevant registers here.
6891          */
6892         tg3_save_pci_state(tp);
6893
6894         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6895             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6896                 tw32(GRC_FASTBOOT_PC, 0);
6897
6898         /*
6899          * We must avoid the readl() that normally takes place.
6900          * It locks machines, causes machine checks, and other
6901          * fun things.  So, temporarily disable the 5701
6902          * hardware workaround, while we do the reset.
6903          */
6904         write_op = tp->write32;
6905         if (write_op == tg3_write_flush_reg32)
6906                 tp->write32 = tg3_write32;
6907
6908         /* Prevent the irq handler from reading or writing PCI registers
6909          * during chip reset when the memory enable bit in the PCI command
6910          * register may be cleared.  The chip does not generate interrupt
6911          * at this time, but the irq handler may still be called due to irq
6912          * sharing or irqpoll.
6913          */
6914         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6915         for (i = 0; i < tp->irq_cnt; i++) {
6916                 struct tg3_napi *tnapi = &tp->napi[i];
6917                 if (tnapi->hw_status) {
6918                         tnapi->hw_status->status = 0;
6919                         tnapi->hw_status->status_tag = 0;
6920                 }
6921                 tnapi->last_tag = 0;
6922                 tnapi->last_irq_tag = 0;
6923         }
6924         smp_mb();
6925
6926         for (i = 0; i < tp->irq_cnt; i++)
6927                 synchronize_irq(tp->napi[i].irq_vec);
6928
6929         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6930                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6931                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6932         }
6933
6934         /* do the reset */
6935         val = GRC_MISC_CFG_CORECLK_RESET;
6936
6937         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6938                 /* Force PCIe 1.0a mode */
6939                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
6940                     !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
6941                     tr32(TG3_PCIE_PHY_TSTCTL) ==
6942                     (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
6943                         tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
6944
6945                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6946                         tw32(GRC_MISC_CFG, (1 << 29));
6947                         val |= (1 << 29);
6948                 }
6949         }
6950
6951         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6952                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6953                 tw32(GRC_VCPU_EXT_CTRL,
6954                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6955         }
6956
6957         /* Manage gphy power for all CPMU absent PCIe devices. */
6958         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6959             !(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
6960                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6961
6962         tw32(GRC_MISC_CFG, val);
6963
6964         /* restore 5701 hardware bug workaround write method */
6965         tp->write32 = write_op;
6966
6967         /* Unfortunately, we have to delay before the PCI read back.
6968          * Some 575X chips even will not respond to a PCI cfg access
6969          * when the reset command is given to the chip.
6970          *
6971          * How do these hardware designers expect things to work
6972          * properly if the PCI write is posted for a long period
6973          * of time?  It is always necessary to have some method by
6974          * which a register read back can occur to push the write
6975          * out which does the reset.
6976          *
6977          * For most tg3 variants the trick below was working.
6978          * Ho hum...
6979          */
6980         udelay(120);
6981
6982         /* Flush PCI posted writes.  The normal MMIO registers
6983          * are inaccessible at this time so this is the only
6984          * way to make this reliably (actually, this is no longer
6985          * the case, see above).  I tried to use indirect
6986          * register read/write but this upset some 5701 variants.
6987          */
6988         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6989
6990         udelay(120);
6991
6992         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6993                 u16 val16;
6994
6995                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6996                         int i;
6997                         u32 cfg_val;
6998
6999                         /* Wait for link training to complete.  */
7000                         for (i = 0; i < 5000; i++)
7001                                 udelay(100);
7002
7003                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
7004                         pci_write_config_dword(tp->pdev, 0xc4,
7005                                                cfg_val | (1 << 15));
7006                 }
7007
7008                 /* Clear the "no snoop" and "relaxed ordering" bits. */
7009                 pci_read_config_word(tp->pdev,
7010                                      tp->pcie_cap + PCI_EXP_DEVCTL,
7011                                      &val16);
7012                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
7013                            PCI_EXP_DEVCTL_NOSNOOP_EN);
7014                 /*
7015                  * Older PCIe devices only support the 128 byte
7016                  * MPS setting.  Enforce the restriction.
7017                  */
7018                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7019                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
7020                 pci_write_config_word(tp->pdev,
7021                                       tp->pcie_cap + PCI_EXP_DEVCTL,
7022                                       val16);
7023
7024                 pcie_set_readrq(tp->pdev, 4096);
7025
7026                 /* Clear error status */
7027                 pci_write_config_word(tp->pdev,
7028                                       tp->pcie_cap + PCI_EXP_DEVSTA,
7029                                       PCI_EXP_DEVSTA_CED |
7030                                       PCI_EXP_DEVSTA_NFED |
7031                                       PCI_EXP_DEVSTA_FED |
7032                                       PCI_EXP_DEVSTA_URD);
7033         }
7034
7035         tg3_restore_pci_state(tp);
7036
7037         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
7038
7039         val = 0;
7040         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
7041                 val = tr32(MEMARB_MODE);
7042         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7043
7044         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7045                 tg3_stop_fw(tp);
7046                 tw32(0x5000, 0x400);
7047         }
7048
7049         tw32(GRC_MODE, tp->grc_mode);
7050
7051         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
7052                 val = tr32(0xc4);
7053
7054                 tw32(0xc4, val | (1 << 15));
7055         }
7056
7057         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7058             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7059                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7060                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7061                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7062                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7063         }
7064
7065         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
7066                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
7067                 tw32_f(MAC_MODE, tp->mac_mode);
7068         } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
7069                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
7070                 tw32_f(MAC_MODE, tp->mac_mode);
7071         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7072                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
7073                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
7074                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
7075                 tw32_f(MAC_MODE, tp->mac_mode);
7076         } else
7077                 tw32_f(MAC_MODE, 0);
7078         udelay(40);
7079
7080         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7081
7082         err = tg3_poll_fw(tp);
7083         if (err)
7084                 return err;
7085
7086         tg3_mdio_start(tp);
7087
7088         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
7089             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7090             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7091             !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
7092                 val = tr32(0x7c00);
7093
7094                 tw32(0x7c00, val | (1 << 25));
7095         }
7096
7097         /* Reprobe ASF enable state.  */
7098         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7099         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7100         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7101         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7102                 u32 nic_cfg;
7103
7104                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7105                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7106                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7107                         tp->last_event_jiffies = jiffies;
7108                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7109                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7110                 }
7111         }
7112
7113         return 0;
7114 }
7115
7116 /* tp->lock is held. */
7117 static void tg3_stop_fw(struct tg3 *tp)
7118 {
7119         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7120            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7121                 /* Wait for RX cpu to ACK the previous event. */
7122                 tg3_wait_for_event_ack(tp);
7123
7124                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7125
7126                 tg3_generate_fw_event(tp);
7127
7128                 /* Wait for RX cpu to ACK this event. */
7129                 tg3_wait_for_event_ack(tp);
7130         }
7131 }
7132
7133 /* tp->lock is held. */
7134 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7135 {
7136         int err;
7137
7138         tg3_stop_fw(tp);
7139
7140         tg3_write_sig_pre_reset(tp, kind);
7141
7142         tg3_abort_hw(tp, silent);
7143         err = tg3_chip_reset(tp);
7144
7145         __tg3_set_mac_addr(tp, 0);
7146
7147         tg3_write_sig_legacy(tp, kind);
7148         tg3_write_sig_post_reset(tp, kind);
7149
7150         if (err)
7151                 return err;
7152
7153         return 0;
7154 }
7155
7156 #define RX_CPU_SCRATCH_BASE     0x30000
7157 #define RX_CPU_SCRATCH_SIZE     0x04000
7158 #define TX_CPU_SCRATCH_BASE     0x34000
7159 #define TX_CPU_SCRATCH_SIZE     0x04000
7160
7161 /* tp->lock is held. */
7162 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7163 {
7164         int i;
7165
7166         BUG_ON(offset == TX_CPU_BASE &&
7167             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7168
7169         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7170                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7171
7172                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7173                 return 0;
7174         }
7175         if (offset == RX_CPU_BASE) {
7176                 for (i = 0; i < 10000; i++) {
7177                         tw32(offset + CPU_STATE, 0xffffffff);
7178                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7179                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7180                                 break;
7181                 }
7182
7183                 tw32(offset + CPU_STATE, 0xffffffff);
7184                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
7185                 udelay(10);
7186         } else {
7187                 for (i = 0; i < 10000; i++) {
7188                         tw32(offset + CPU_STATE, 0xffffffff);
7189                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7190                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7191                                 break;
7192                 }
7193         }
7194
7195         if (i >= 10000) {
7196                 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7197                            __func__, offset == RX_CPU_BASE ? "RX" : "TX");
7198                 return -ENODEV;
7199         }
7200
7201         /* Clear firmware's nvram arbitration. */
7202         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7203                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7204         return 0;
7205 }
7206
7207 struct fw_info {
7208         unsigned int fw_base;
7209         unsigned int fw_len;
7210         const __be32 *fw_data;
7211 };
7212
7213 /* tp->lock is held. */
7214 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7215                                  int cpu_scratch_size, struct fw_info *info)
7216 {
7217         int err, lock_err, i;
7218         void (*write_op)(struct tg3 *, u32, u32);
7219
7220         if (cpu_base == TX_CPU_BASE &&
7221             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7222                 netdev_err(tp->dev,
7223                            "%s: Trying to load TX cpu firmware which is 5705\n",
7224                            __func__);
7225                 return -EINVAL;
7226         }
7227
7228         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7229                 write_op = tg3_write_mem;
7230         else
7231                 write_op = tg3_write_indirect_reg32;
7232
7233         /* It is possible that bootcode is still loading at this point.
7234          * Get the nvram lock first before halting the cpu.
7235          */
7236         lock_err = tg3_nvram_lock(tp);
7237         err = tg3_halt_cpu(tp, cpu_base);
7238         if (!lock_err)
7239                 tg3_nvram_unlock(tp);
7240         if (err)
7241                 goto out;
7242
7243         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7244                 write_op(tp, cpu_scratch_base + i, 0);
7245         tw32(cpu_base + CPU_STATE, 0xffffffff);
7246         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7247         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7248                 write_op(tp, (cpu_scratch_base +
7249                               (info->fw_base & 0xffff) +
7250                               (i * sizeof(u32))),
7251                               be32_to_cpu(info->fw_data[i]));
7252
7253         err = 0;
7254
7255 out:
7256         return err;
7257 }
7258
7259 /* tp->lock is held. */
7260 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7261 {
7262         struct fw_info info;
7263         const __be32 *fw_data;
7264         int err, i;
7265
7266         fw_data = (void *)tp->fw->data;
7267
7268         /* Firmware blob starts with version numbers, followed by
7269            start address and length. We are setting complete length.
7270            length = end_address_of_bss - start_address_of_text.
7271            Remainder is the blob to be loaded contiguously
7272            from start address. */
7273
7274         info.fw_base = be32_to_cpu(fw_data[1]);
7275         info.fw_len = tp->fw->size - 12;
7276         info.fw_data = &fw_data[3];
7277
7278         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7279                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7280                                     &info);
7281         if (err)
7282                 return err;
7283
7284         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7285                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7286                                     &info);
7287         if (err)
7288                 return err;
7289
7290         /* Now startup only the RX cpu. */
7291         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7292         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7293
7294         for (i = 0; i < 5; i++) {
7295                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7296                         break;
7297                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7298                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
7299                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7300                 udelay(1000);
7301         }
7302         if (i >= 5) {
7303                 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7304                            "should be %08x\n", __func__,
7305                            tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
7306                 return -ENODEV;
7307         }
7308         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7309         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
7310
7311         return 0;
7312 }
7313
7314 /* 5705 needs a special version of the TSO firmware.  */
7315
7316 /* tp->lock is held. */
7317 static int tg3_load_tso_firmware(struct tg3 *tp)
7318 {
7319         struct fw_info info;
7320         const __be32 *fw_data;
7321         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7322         int err, i;
7323
7324         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7325                 return 0;
7326
7327         fw_data = (void *)tp->fw->data;
7328
7329         /* Firmware blob starts with version numbers, followed by
7330            start address and length. We are setting complete length.
7331            length = end_address_of_bss - start_address_of_text.
7332            Remainder is the blob to be loaded contiguously
7333            from start address. */
7334
7335         info.fw_base = be32_to_cpu(fw_data[1]);
7336         cpu_scratch_size = tp->fw_len;
7337         info.fw_len = tp->fw->size - 12;
7338         info.fw_data = &fw_data[3];
7339
7340         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7341                 cpu_base = RX_CPU_BASE;
7342                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7343         } else {
7344                 cpu_base = TX_CPU_BASE;
7345                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7346                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7347         }
7348
7349         err = tg3_load_firmware_cpu(tp, cpu_base,
7350                                     cpu_scratch_base, cpu_scratch_size,
7351                                     &info);
7352         if (err)
7353                 return err;
7354
7355         /* Now startup the cpu. */
7356         tw32(cpu_base + CPU_STATE, 0xffffffff);
7357         tw32_f(cpu_base + CPU_PC, info.fw_base);
7358
7359         for (i = 0; i < 5; i++) {
7360                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7361                         break;
7362                 tw32(cpu_base + CPU_STATE, 0xffffffff);
7363                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
7364                 tw32_f(cpu_base + CPU_PC, info.fw_base);
7365                 udelay(1000);
7366         }
7367         if (i >= 5) {
7368                 netdev_err(tp->dev,
7369                            "%s fails to set CPU PC, is %08x should be %08x\n",
7370                            __func__, tr32(cpu_base + CPU_PC), info.fw_base);
7371                 return -ENODEV;
7372         }
7373         tw32(cpu_base + CPU_STATE, 0xffffffff);
7374         tw32_f(cpu_base + CPU_MODE,  0x00000000);
7375         return 0;
7376 }
7377
7378
7379 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7380 {
7381         struct tg3 *tp = netdev_priv(dev);
7382         struct sockaddr *addr = p;
7383         int err = 0, skip_mac_1 = 0;
7384
7385         if (!is_valid_ether_addr(addr->sa_data))
7386                 return -EINVAL;
7387
7388         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7389
7390         if (!netif_running(dev))
7391                 return 0;
7392
7393         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7394                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7395
7396                 addr0_high = tr32(MAC_ADDR_0_HIGH);
7397                 addr0_low = tr32(MAC_ADDR_0_LOW);
7398                 addr1_high = tr32(MAC_ADDR_1_HIGH);
7399                 addr1_low = tr32(MAC_ADDR_1_LOW);
7400
7401                 /* Skip MAC addr 1 if ASF is using it. */
7402                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7403                     !(addr1_high == 0 && addr1_low == 0))
7404                         skip_mac_1 = 1;
7405         }
7406         spin_lock_bh(&tp->lock);
7407         __tg3_set_mac_addr(tp, skip_mac_1);
7408         spin_unlock_bh(&tp->lock);
7409
7410         return err;
7411 }
7412
7413 /* tp->lock is held. */
7414 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7415                            dma_addr_t mapping, u32 maxlen_flags,
7416                            u32 nic_addr)
7417 {
7418         tg3_write_mem(tp,
7419                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7420                       ((u64) mapping >> 32));
7421         tg3_write_mem(tp,
7422                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7423                       ((u64) mapping & 0xffffffff));
7424         tg3_write_mem(tp,
7425                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7426                        maxlen_flags);
7427
7428         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7429                 tg3_write_mem(tp,
7430                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7431                               nic_addr);
7432 }
7433
7434 static void __tg3_set_rx_mode(struct net_device *);
7435 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7436 {
7437         int i;
7438
7439         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7440                 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7441                 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7442                 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7443         } else {
7444                 tw32(HOSTCC_TXCOL_TICKS, 0);
7445                 tw32(HOSTCC_TXMAX_FRAMES, 0);
7446                 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7447         }
7448
7449         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
7450                 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7451                 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7452                 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7453         } else {
7454                 tw32(HOSTCC_RXCOL_TICKS, 0);
7455                 tw32(HOSTCC_RXMAX_FRAMES, 0);
7456                 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7457         }
7458
7459         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7460                 u32 val = ec->stats_block_coalesce_usecs;
7461
7462                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7463                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7464
7465                 if (!netif_carrier_ok(tp->dev))
7466                         val = 0;
7467
7468                 tw32(HOSTCC_STAT_COAL_TICKS, val);
7469         }
7470
7471         for (i = 0; i < tp->irq_cnt - 1; i++) {
7472                 u32 reg;
7473
7474                 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7475                 tw32(reg, ec->rx_coalesce_usecs);
7476                 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7477                 tw32(reg, ec->rx_max_coalesced_frames);
7478                 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7479                 tw32(reg, ec->rx_max_coalesced_frames_irq);
7480
7481                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7482                         reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7483                         tw32(reg, ec->tx_coalesce_usecs);
7484                         reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7485                         tw32(reg, ec->tx_max_coalesced_frames);
7486                         reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7487                         tw32(reg, ec->tx_max_coalesced_frames_irq);
7488                 }
7489         }
7490
7491         for (; i < tp->irq_max - 1; i++) {
7492                 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7493                 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7494                 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7495
7496                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7497                         tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7498                         tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7499                         tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7500                 }
7501         }
7502 }
7503
7504 /* tp->lock is held. */
7505 static void tg3_rings_reset(struct tg3 *tp)
7506 {
7507         int i;
7508         u32 stblk, txrcb, rxrcb, limit;
7509         struct tg3_napi *tnapi = &tp->napi[0];
7510
7511         /* Disable all transmit rings but the first. */
7512         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7513                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7514         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7515                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7516         else
7517                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7518
7519         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7520              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7521                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7522                               BDINFO_FLAGS_DISABLED);
7523
7524
7525         /* Disable all receive return rings but the first. */
7526         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7527             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7528                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7529         else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7530                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7531         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7532                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7533                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7534         else
7535                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7536
7537         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7538              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7539                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7540                               BDINFO_FLAGS_DISABLED);
7541
7542         /* Disable interrupts */
7543         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7544
7545         /* Zero mailbox registers. */
7546         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7547                 for (i = 1; i < tp->irq_max; i++) {
7548                         tp->napi[i].tx_prod = 0;
7549                         tp->napi[i].tx_cons = 0;
7550                         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7551                                 tw32_mailbox(tp->napi[i].prodmbox, 0);
7552                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
7553                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7554                 }
7555                 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7556                         tw32_mailbox(tp->napi[0].prodmbox, 0);
7557         } else {
7558                 tp->napi[0].tx_prod = 0;
7559                 tp->napi[0].tx_cons = 0;
7560                 tw32_mailbox(tp->napi[0].prodmbox, 0);
7561                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7562         }
7563
7564         /* Make sure the NIC-based send BD rings are disabled. */
7565         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7566                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7567                 for (i = 0; i < 16; i++)
7568                         tw32_tx_mbox(mbox + i * 8, 0);
7569         }
7570
7571         txrcb = NIC_SRAM_SEND_RCB;
7572         rxrcb = NIC_SRAM_RCV_RET_RCB;
7573
7574         /* Clear status block in ram. */
7575         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7576
7577         /* Set status block DMA address */
7578         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7579              ((u64) tnapi->status_mapping >> 32));
7580         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7581              ((u64) tnapi->status_mapping & 0xffffffff));
7582
7583         if (tnapi->tx_ring) {
7584                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7585                                (TG3_TX_RING_SIZE <<
7586                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7587                                NIC_SRAM_TX_BUFFER_DESC);
7588                 txrcb += TG3_BDINFO_SIZE;
7589         }
7590
7591         if (tnapi->rx_rcb) {
7592                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7593                                (TG3_RX_RCB_RING_SIZE(tp) <<
7594                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7595                 rxrcb += TG3_BDINFO_SIZE;
7596         }
7597
7598         stblk = HOSTCC_STATBLCK_RING1;
7599
7600         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7601                 u64 mapping = (u64)tnapi->status_mapping;
7602                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7603                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7604
7605                 /* Clear status block in ram. */
7606                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7607
7608                 if (tnapi->tx_ring) {
7609                         tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7610                                        (TG3_TX_RING_SIZE <<
7611                                         BDINFO_FLAGS_MAXLEN_SHIFT),
7612                                        NIC_SRAM_TX_BUFFER_DESC);
7613                         txrcb += TG3_BDINFO_SIZE;
7614                 }
7615
7616                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7617                                (TG3_RX_RCB_RING_SIZE(tp) <<
7618                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7619
7620                 stblk += 8;
7621                 rxrcb += TG3_BDINFO_SIZE;
7622         }
7623 }
7624
7625 /* tp->lock is held. */
7626 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7627 {
7628         u32 val, rdmac_mode;
7629         int i, err, limit;
7630         struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
7631
7632         tg3_disable_ints(tp);
7633
7634         tg3_stop_fw(tp);
7635
7636         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7637
7638         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
7639                 tg3_abort_hw(tp, 1);
7640
7641         if (reset_phy)
7642                 tg3_phy_reset(tp);
7643
7644         err = tg3_chip_reset(tp);
7645         if (err)
7646                 return err;
7647
7648         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7649
7650         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7651                 val = tr32(TG3_CPMU_CTRL);
7652                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7653                 tw32(TG3_CPMU_CTRL, val);
7654
7655                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7656                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7657                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7658                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7659
7660                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7661                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7662                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7663                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7664
7665                 val = tr32(TG3_CPMU_HST_ACC);
7666                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7667                 val |= CPMU_HST_ACC_MACCLK_6_25;
7668                 tw32(TG3_CPMU_HST_ACC, val);
7669         }
7670
7671         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7672                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7673                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7674                        PCIE_PWR_MGMT_L1_THRESH_4MS;
7675                 tw32(PCIE_PWR_MGMT_THRESH, val);
7676
7677                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7678                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7679
7680                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7681
7682                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7683                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7684         }
7685
7686         if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7687                 u32 grc_mode = tr32(GRC_MODE);
7688
7689                 /* Access the lower 1K of PL PCIE block registers. */
7690                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7691                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7692
7693                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7694                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7695                      val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7696
7697                 tw32(GRC_MODE, grc_mode);
7698         }
7699
7700         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
7701                 u32 grc_mode = tr32(GRC_MODE);
7702
7703                 /* Access the lower 1K of PL PCIE block registers. */
7704                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7705                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7706
7707                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5);
7708                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
7709                      val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
7710
7711                 tw32(GRC_MODE, grc_mode);
7712
7713                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7714                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7715                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7716                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7717         }
7718
7719         /* This works around an issue with Athlon chipsets on
7720          * B3 tigon3 silicon.  This bit has no effect on any
7721          * other revision.  But do not set this on PCI Express
7722          * chips and don't even touch the clocks if the CPMU is present.
7723          */
7724         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7725                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7726                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7727                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7728         }
7729
7730         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7731             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7732                 val = tr32(TG3PCI_PCISTATE);
7733                 val |= PCISTATE_RETRY_SAME_DMA;
7734                 tw32(TG3PCI_PCISTATE, val);
7735         }
7736
7737         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7738                 /* Allow reads and writes to the
7739                  * APE register and memory space.
7740                  */
7741                 val = tr32(TG3PCI_PCISTATE);
7742                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7743                        PCISTATE_ALLOW_APE_SHMEM_WR |
7744                        PCISTATE_ALLOW_APE_PSPACE_WR;
7745                 tw32(TG3PCI_PCISTATE, val);
7746         }
7747
7748         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7749                 /* Enable some hw fixes.  */
7750                 val = tr32(TG3PCI_MSI_DATA);
7751                 val |= (1 << 26) | (1 << 28) | (1 << 29);
7752                 tw32(TG3PCI_MSI_DATA, val);
7753         }
7754
7755         /* Descriptor ring init may make accesses to the
7756          * NIC SRAM area to setup the TX descriptors, so we
7757          * can only do this after the hardware has been
7758          * successfully reset.
7759          */
7760         err = tg3_init_rings(tp);
7761         if (err)
7762                 return err;
7763
7764         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
7765                 val = tr32(TG3PCI_DMA_RW_CTRL) &
7766                       ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7767                 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
7768                         val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
7769                 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7770         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7771                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7772                 /* This value is determined during the probe time DMA
7773                  * engine test, tg3_test_dma.
7774                  */
7775                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7776         }
7777
7778         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7779                           GRC_MODE_4X_NIC_SEND_RINGS |
7780                           GRC_MODE_NO_TX_PHDR_CSUM |
7781                           GRC_MODE_NO_RX_PHDR_CSUM);
7782         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7783
7784         /* Pseudo-header checksum is done by hardware logic and not
7785          * the offload processers, so make the chip do the pseudo-
7786          * header checksums on receive.  For transmit it is more
7787          * convenient to do the pseudo-header checksum in software
7788          * as Linux does that on transmit for us in all cases.
7789          */
7790         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7791
7792         tw32(GRC_MODE,
7793              tp->grc_mode |
7794              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7795
7796         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7797         val = tr32(GRC_MISC_CFG);
7798         val &= ~0xff;
7799         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7800         tw32(GRC_MISC_CFG, val);
7801
7802         /* Initialize MBUF/DESC pool. */
7803         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7804                 /* Do nothing.  */
7805         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7806                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7807                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7808                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7809                 else
7810                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7811                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7812                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7813         } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7814                 int fw_len;
7815
7816                 fw_len = tp->fw_len;
7817                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7818                 tw32(BUFMGR_MB_POOL_ADDR,
7819                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7820                 tw32(BUFMGR_MB_POOL_SIZE,
7821                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7822         }
7823
7824         if (tp->dev->mtu <= ETH_DATA_LEN) {
7825                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7826                      tp->bufmgr_config.mbuf_read_dma_low_water);
7827                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7828                      tp->bufmgr_config.mbuf_mac_rx_low_water);
7829                 tw32(BUFMGR_MB_HIGH_WATER,
7830                      tp->bufmgr_config.mbuf_high_water);
7831         } else {
7832                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7833                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7834                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7835                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7836                 tw32(BUFMGR_MB_HIGH_WATER,
7837                      tp->bufmgr_config.mbuf_high_water_jumbo);
7838         }
7839         tw32(BUFMGR_DMA_LOW_WATER,
7840              tp->bufmgr_config.dma_low_water);
7841         tw32(BUFMGR_DMA_HIGH_WATER,
7842              tp->bufmgr_config.dma_high_water);
7843
7844         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7845         for (i = 0; i < 2000; i++) {
7846                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7847                         break;
7848                 udelay(10);
7849         }
7850         if (i >= 2000) {
7851                 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
7852                 return -ENODEV;
7853         }
7854
7855         /* Setup replenish threshold. */
7856         val = tp->rx_pending / 8;
7857         if (val == 0)
7858                 val = 1;
7859         else if (val > tp->rx_std_max_post)
7860                 val = tp->rx_std_max_post;
7861         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7862                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7863                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7864
7865                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7866                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7867         }
7868
7869         tw32(RCVBDI_STD_THRESH, val);
7870
7871         /* Initialize TG3_BDINFO's at:
7872          *  RCVDBDI_STD_BD:     standard eth size rx ring
7873          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
7874          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
7875          *
7876          * like so:
7877          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
7878          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
7879          *                              ring attribute flags
7880          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
7881          *
7882          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7883          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7884          *
7885          * The size of each ring is fixed in the firmware, but the location is
7886          * configurable.
7887          */
7888         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7889              ((u64) tpr->rx_std_mapping >> 32));
7890         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7891              ((u64) tpr->rx_std_mapping & 0xffffffff));
7892         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
7893             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
7894                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7895                      NIC_SRAM_RX_BUFFER_DESC);
7896
7897         /* Disable the mini ring */
7898         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7899                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7900                      BDINFO_FLAGS_DISABLED);
7901
7902         /* Program the jumbo buffer descriptor ring control
7903          * blocks on those devices that have them.
7904          */
7905         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7906             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7907                 /* Setup replenish threshold. */
7908                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7909
7910                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7911                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7912                              ((u64) tpr->rx_jmb_mapping >> 32));
7913                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7914                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7915                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7916                              (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7917                              BDINFO_FLAGS_USE_EXT_RECV);
7918                         if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) ||
7919                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7920                                 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7921                                      NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7922                 } else {
7923                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7924                              BDINFO_FLAGS_DISABLED);
7925                 }
7926
7927                 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
7928                         val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7929                               (TG3_RX_STD_DMA_SZ << 2);
7930                 else
7931                         val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
7932         } else
7933                 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7934
7935         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7936
7937         tpr->rx_std_prod_idx = tp->rx_pending;
7938         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
7939
7940         tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7941                           tp->rx_jumbo_pending : 0;
7942         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
7943
7944         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
7945                 tw32(STD_REPLENISH_LWM, 32);
7946                 tw32(JMB_REPLENISH_LWM, 16);
7947         }
7948
7949         tg3_rings_reset(tp);
7950
7951         /* Initialize MAC address and backoff seed. */
7952         __tg3_set_mac_addr(tp, 0);
7953
7954         /* MTU + ethernet header + FCS + optional VLAN tag */
7955         tw32(MAC_RX_MTU_SIZE,
7956              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7957
7958         /* The slot time is changed by tg3_setup_phy if we
7959          * run at gigabit with half duplex.
7960          */
7961         tw32(MAC_TX_LENGTHS,
7962              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7963              (6 << TX_LENGTHS_IPG_SHIFT) |
7964              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7965
7966         /* Receive rules. */
7967         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7968         tw32(RCVLPC_CONFIG, 0x0181);
7969
7970         /* Calculate RDMAC_MODE setting early, we need it to determine
7971          * the RCVLPC_STATE_ENABLE mask.
7972          */
7973         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7974                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7975                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7976                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7977                       RDMAC_MODE_LNGREAD_ENAB);
7978
7979         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7980             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7981                 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
7982
7983         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7984             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7985             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7986                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7987                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7988                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7989
7990         /* If statement applies to 5705 and 5750 PCI devices only */
7991         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7992              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7993             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7994                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7995                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7996                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7997                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7998                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7999                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8000                 }
8001         }
8002
8003         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
8004                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8005
8006         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8007                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8008
8009         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
8010             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8011             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8012                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
8013
8014         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8015             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8016             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8017             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
8018             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
8019                 val = tr32(TG3_RDMA_RSRVCTRL_REG);
8020                 tw32(TG3_RDMA_RSRVCTRL_REG,
8021                      val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
8022         }
8023
8024         /* Receive/send statistics. */
8025         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
8026                 val = tr32(RCVLPC_STATS_ENABLE);
8027                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8028                 tw32(RCVLPC_STATS_ENABLE, val);
8029         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8030                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8031                 val = tr32(RCVLPC_STATS_ENABLE);
8032                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8033                 tw32(RCVLPC_STATS_ENABLE, val);
8034         } else {
8035                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8036         }
8037         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8038         tw32(SNDDATAI_STATSENAB, 0xffffff);
8039         tw32(SNDDATAI_STATSCTRL,
8040              (SNDDATAI_SCTRL_ENABLE |
8041               SNDDATAI_SCTRL_FASTUPD));
8042
8043         /* Setup host coalescing engine. */
8044         tw32(HOSTCC_MODE, 0);
8045         for (i = 0; i < 2000; i++) {
8046                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8047                         break;
8048                 udelay(10);
8049         }
8050
8051         __tg3_set_coalesce(tp, &tp->coal);
8052
8053         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8054                 /* Status/statistics block address.  See tg3_timer,
8055                  * the tg3_periodic_fetch_stats call there, and
8056                  * tg3_get_stats to see how this works for 5705/5750 chips.
8057                  */
8058                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8059                      ((u64) tp->stats_mapping >> 32));
8060                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8061                      ((u64) tp->stats_mapping & 0xffffffff));
8062                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8063
8064                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
8065
8066                 /* Clear statistics and status block memory areas */
8067                 for (i = NIC_SRAM_STATS_BLK;
8068                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8069                      i += sizeof(u32)) {
8070                         tg3_write_mem(tp, i, 0);
8071                         udelay(40);
8072                 }
8073         }
8074
8075         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8076
8077         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8078         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8079         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8080                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8081
8082         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
8083                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
8084                 /* reset to prevent losing 1st rx packet intermittently */
8085                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8086                 udelay(10);
8087         }
8088
8089         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8090                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8091         else
8092                 tp->mac_mode = 0;
8093         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8094                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
8095         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8096             !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8097             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8098                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8099         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8100         udelay(40);
8101
8102         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8103          * If TG3_FLG2_IS_NIC is zero, we should read the
8104          * register to preserve the GPIO settings for LOMs. The GPIOs,
8105          * whether used as inputs or outputs, are set by boot code after
8106          * reset.
8107          */
8108         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
8109                 u32 gpio_mask;
8110
8111                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8112                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8113                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8114
8115                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8116                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8117                                      GRC_LCLCTRL_GPIO_OUTPUT3;
8118
8119                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8120                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8121
8122                 tp->grc_local_ctrl &= ~gpio_mask;
8123                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8124
8125                 /* GPIO1 must be driven high for eeprom write protect */
8126                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8127                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8128                                                GRC_LCLCTRL_GPIO_OUTPUT1);
8129         }
8130         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8131         udelay(100);
8132
8133         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
8134                 val = tr32(MSGINT_MODE);
8135                 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8136                 tw32(MSGINT_MODE, val);
8137         }
8138
8139         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8140                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8141                 udelay(40);
8142         }
8143
8144         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8145                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8146                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8147                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8148                WDMAC_MODE_LNGREAD_ENAB);
8149
8150         /* If statement applies to 5705 and 5750 PCI devices only */
8151         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8152              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8153             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
8154                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8155                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8156                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8157                         /* nothing */
8158                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8159                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8160                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8161                         val |= WDMAC_MODE_RX_ACCEL;
8162                 }
8163         }
8164
8165         /* Enable host coalescing bug fix */
8166         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8167                 val |= WDMAC_MODE_STATUS_TAG_FIX;
8168
8169         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8170                 val |= WDMAC_MODE_BURST_ALL_DATA;
8171
8172         tw32_f(WDMAC_MODE, val);
8173         udelay(40);
8174
8175         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8176                 u16 pcix_cmd;
8177
8178                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8179                                      &pcix_cmd);
8180                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8181                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8182                         pcix_cmd |= PCI_X_CMD_READ_2K;
8183                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8184                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8185                         pcix_cmd |= PCI_X_CMD_READ_2K;
8186                 }
8187                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8188                                       pcix_cmd);
8189         }
8190
8191         tw32_f(RDMAC_MODE, rdmac_mode);
8192         udelay(40);
8193
8194         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8195         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8196                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8197
8198         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8199                 tw32(SNDDATAC_MODE,
8200                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8201         else
8202                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8203
8204         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8205         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8206         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8207         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8208         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8209                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8210         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8211         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8212                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8213         tw32(SNDBDI_MODE, val);
8214         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8215
8216         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8217                 err = tg3_load_5701_a0_firmware_fix(tp);
8218                 if (err)
8219                         return err;
8220         }
8221
8222         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8223                 err = tg3_load_tso_firmware(tp);
8224                 if (err)
8225                         return err;
8226         }
8227
8228         tp->tx_mode = TX_MODE_ENABLE;
8229         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
8230             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8231                 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
8232         tw32_f(MAC_TX_MODE, tp->tx_mode);
8233         udelay(100);
8234
8235         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8236                 u32 reg = MAC_RSS_INDIR_TBL_0;
8237                 u8 *ent = (u8 *)&val;
8238
8239                 /* Setup the indirection table */
8240                 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8241                         int idx = i % sizeof(val);
8242
8243                         ent[idx] = i % (tp->irq_cnt - 1);
8244                         if (idx == sizeof(val) - 1) {
8245                                 tw32(reg, val);
8246                                 reg += 4;
8247                         }
8248                 }
8249
8250                 /* Setup the "secret" hash key. */
8251                 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8252                 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8253                 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8254                 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8255                 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8256                 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8257                 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8258                 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8259                 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8260                 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8261         }
8262
8263         tp->rx_mode = RX_MODE_ENABLE;
8264         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8265                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8266
8267         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8268                 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8269                                RX_MODE_RSS_ITBL_HASH_BITS_7 |
8270                                RX_MODE_RSS_IPV6_HASH_EN |
8271                                RX_MODE_RSS_TCP_IPV6_HASH_EN |
8272                                RX_MODE_RSS_IPV4_HASH_EN |
8273                                RX_MODE_RSS_TCP_IPV4_HASH_EN;
8274
8275         tw32_f(MAC_RX_MODE, tp->rx_mode);
8276         udelay(10);
8277
8278         tw32(MAC_LED_CTRL, tp->led_ctrl);
8279
8280         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8281         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8282                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8283                 udelay(10);
8284         }
8285         tw32_f(MAC_RX_MODE, tp->rx_mode);
8286         udelay(10);
8287
8288         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8289                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8290                         !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
8291                         /* Set drive transmission level to 1.2V  */
8292                         /* only if the signal pre-emphasis bit is not set  */
8293                         val = tr32(MAC_SERDES_CFG);
8294                         val &= 0xfffff000;
8295                         val |= 0x880;
8296                         tw32(MAC_SERDES_CFG, val);
8297                 }
8298                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8299                         tw32(MAC_SERDES_CFG, 0x616000);
8300         }
8301
8302         /* Prevent chip from dropping frames when flow control
8303          * is enabled.
8304          */
8305         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8306                 val = 1;
8307         else
8308                 val = 2;
8309         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8310
8311         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8312             (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
8313                 /* Use hardware link auto-negotiation */
8314                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8315         }
8316
8317         if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8318             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8319                 u32 tmp;
8320
8321                 tmp = tr32(SERDES_RX_CTRL);
8322                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8323                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8324                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8325                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8326         }
8327
8328         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8329                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
8330                         tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
8331                         tp->link_config.speed = tp->link_config.orig_speed;
8332                         tp->link_config.duplex = tp->link_config.orig_duplex;
8333                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
8334                 }
8335
8336                 err = tg3_setup_phy(tp, 0);
8337                 if (err)
8338                         return err;
8339
8340                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8341                     !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8342                         u32 tmp;
8343
8344                         /* Clear CRC stats. */
8345                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8346                                 tg3_writephy(tp, MII_TG3_TEST1,
8347                                              tmp | MII_TG3_TEST1_CRC_EN);
8348                                 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
8349                         }
8350                 }
8351         }
8352
8353         __tg3_set_rx_mode(tp->dev);
8354
8355         /* Initialize receive rules. */
8356         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
8357         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8358         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
8359         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8360
8361         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8362             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8363                 limit = 8;
8364         else
8365                 limit = 16;
8366         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8367                 limit -= 4;
8368         switch (limit) {
8369         case 16:
8370                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
8371         case 15:
8372                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
8373         case 14:
8374                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
8375         case 13:
8376                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
8377         case 12:
8378                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
8379         case 11:
8380                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
8381         case 10:
8382                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
8383         case 9:
8384                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
8385         case 8:
8386                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
8387         case 7:
8388                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
8389         case 6:
8390                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
8391         case 5:
8392                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
8393         case 4:
8394                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
8395         case 3:
8396                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
8397         case 2:
8398         case 1:
8399
8400         default:
8401                 break;
8402         }
8403
8404         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8405                 /* Write our heartbeat update interval to APE. */
8406                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8407                                 APE_HOST_HEARTBEAT_INT_DISABLE);
8408
8409         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8410
8411         return 0;
8412 }
8413
8414 /* Called at device open time to get the chip ready for
8415  * packet processing.  Invoked with tp->lock held.
8416  */
8417 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8418 {
8419         tg3_switch_clocks(tp);
8420
8421         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8422
8423         return tg3_reset_hw(tp, reset_phy);
8424 }
8425
8426 #define TG3_STAT_ADD32(PSTAT, REG) \
8427 do {    u32 __val = tr32(REG); \
8428         (PSTAT)->low += __val; \
8429         if ((PSTAT)->low < __val) \
8430                 (PSTAT)->high += 1; \
8431 } while (0)
8432
8433 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8434 {
8435         struct tg3_hw_stats *sp = tp->hw_stats;
8436
8437         if (!netif_carrier_ok(tp->dev))
8438                 return;
8439
8440         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8441         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8442         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8443         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8444         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8445         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8446         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8447         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8448         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8449         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8450         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8451         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8452         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8453
8454         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8455         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8456         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8457         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8458         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8459         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8460         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8461         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8462         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8463         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8464         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8465         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8466         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8467         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8468
8469         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8470         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8471         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8472 }
8473
8474 static void tg3_timer(unsigned long __opaque)
8475 {
8476         struct tg3 *tp = (struct tg3 *) __opaque;
8477
8478         if (tp->irq_sync)
8479                 goto restart_timer;
8480
8481         spin_lock(&tp->lock);
8482
8483         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8484                 /* All of this garbage is because when using non-tagged
8485                  * IRQ status the mailbox/status_block protocol the chip
8486                  * uses with the cpu is race prone.
8487                  */
8488                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8489                         tw32(GRC_LOCAL_CTRL,
8490                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8491                 } else {
8492                         tw32(HOSTCC_MODE, tp->coalesce_mode |
8493                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8494                 }
8495
8496                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8497                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8498                         spin_unlock(&tp->lock);
8499                         schedule_work(&tp->reset_task);
8500                         return;
8501                 }
8502         }
8503
8504         /* This part only runs once per second. */
8505         if (!--tp->timer_counter) {
8506                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8507                         tg3_periodic_fetch_stats(tp);
8508
8509                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8510                         u32 mac_stat;
8511                         int phy_event;
8512
8513                         mac_stat = tr32(MAC_STATUS);
8514
8515                         phy_event = 0;
8516                         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
8517                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8518                                         phy_event = 1;
8519                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8520                                 phy_event = 1;
8521
8522                         if (phy_event)
8523                                 tg3_setup_phy(tp, 0);
8524                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8525                         u32 mac_stat = tr32(MAC_STATUS);
8526                         int need_setup = 0;
8527
8528                         if (netif_carrier_ok(tp->dev) &&
8529                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8530                                 need_setup = 1;
8531                         }
8532                         if (!netif_carrier_ok(tp->dev) &&
8533                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
8534                                          MAC_STATUS_SIGNAL_DET))) {
8535                                 need_setup = 1;
8536                         }
8537                         if (need_setup) {
8538                                 if (!tp->serdes_counter) {
8539                                         tw32_f(MAC_MODE,
8540                                              (tp->mac_mode &
8541                                               ~MAC_MODE_PORT_MODE_MASK));
8542                                         udelay(40);
8543                                         tw32_f(MAC_MODE, tp->mac_mode);
8544                                         udelay(40);
8545                                 }
8546                                 tg3_setup_phy(tp, 0);
8547                         }
8548                 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8549                            (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8550                         tg3_serdes_parallel_detect(tp);
8551                 }
8552
8553                 tp->timer_counter = tp->timer_multiplier;
8554         }
8555
8556         /* Heartbeat is only sent once every 2 seconds.
8557          *
8558          * The heartbeat is to tell the ASF firmware that the host
8559          * driver is still alive.  In the event that the OS crashes,
8560          * ASF needs to reset the hardware to free up the FIFO space
8561          * that may be filled with rx packets destined for the host.
8562          * If the FIFO is full, ASF will no longer function properly.
8563          *
8564          * Unintended resets have been reported on real time kernels
8565          * where the timer doesn't run on time.  Netpoll will also have
8566          * same problem.
8567          *
8568          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8569          * to check the ring condition when the heartbeat is expiring
8570          * before doing the reset.  This will prevent most unintended
8571          * resets.
8572          */
8573         if (!--tp->asf_counter) {
8574                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8575                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8576                         tg3_wait_for_event_ack(tp);
8577
8578                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8579                                       FWCMD_NICDRV_ALIVE3);
8580                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8581                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
8582                                       TG3_FW_UPDATE_TIMEOUT_SEC);
8583
8584                         tg3_generate_fw_event(tp);
8585                 }
8586                 tp->asf_counter = tp->asf_multiplier;
8587         }
8588
8589         spin_unlock(&tp->lock);
8590
8591 restart_timer:
8592         tp->timer.expires = jiffies + tp->timer_offset;
8593         add_timer(&tp->timer);
8594 }
8595
8596 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8597 {
8598         irq_handler_t fn;
8599         unsigned long flags;
8600         char *name;
8601         struct tg3_napi *tnapi = &tp->napi[irq_num];
8602
8603         if (tp->irq_cnt == 1)
8604                 name = tp->dev->name;
8605         else {
8606                 name = &tnapi->irq_lbl[0];
8607                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8608                 name[IFNAMSIZ-1] = 0;
8609         }
8610
8611         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8612                 fn = tg3_msi;
8613                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8614                         fn = tg3_msi_1shot;
8615                 flags = IRQF_SAMPLE_RANDOM;
8616         } else {
8617                 fn = tg3_interrupt;
8618                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8619                         fn = tg3_interrupt_tagged;
8620                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8621         }
8622
8623         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8624 }
8625
8626 static int tg3_test_interrupt(struct tg3 *tp)
8627 {
8628         struct tg3_napi *tnapi = &tp->napi[0];
8629         struct net_device *dev = tp->dev;
8630         int err, i, intr_ok = 0;
8631         u32 val;
8632
8633         if (!netif_running(dev))
8634                 return -ENODEV;
8635
8636         tg3_disable_ints(tp);
8637
8638         free_irq(tnapi->irq_vec, tnapi);
8639
8640         /*
8641          * Turn off MSI one shot mode.  Otherwise this test has no
8642          * observable way to know whether the interrupt was delivered.
8643          */
8644         if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8645             (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8646                 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8647                 tw32(MSGINT_MODE, val);
8648         }
8649
8650         err = request_irq(tnapi->irq_vec, tg3_test_isr,
8651                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8652         if (err)
8653                 return err;
8654
8655         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8656         tg3_enable_ints(tp);
8657
8658         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8659                tnapi->coal_now);
8660
8661         for (i = 0; i < 5; i++) {
8662                 u32 int_mbox, misc_host_ctrl;
8663
8664                 int_mbox = tr32_mailbox(tnapi->int_mbox);
8665                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8666
8667                 if ((int_mbox != 0) ||
8668                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8669                         intr_ok = 1;
8670                         break;
8671                 }
8672
8673                 msleep(10);
8674         }
8675
8676         tg3_disable_ints(tp);
8677
8678         free_irq(tnapi->irq_vec, tnapi);
8679
8680         err = tg3_request_irq(tp, 0);
8681
8682         if (err)
8683                 return err;
8684
8685         if (intr_ok) {
8686                 /* Reenable MSI one shot mode. */
8687                 if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8688                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8689                         val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8690                         tw32(MSGINT_MODE, val);
8691                 }
8692                 return 0;
8693         }
8694
8695         return -EIO;
8696 }
8697
8698 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8699  * successfully restored
8700  */
8701 static int tg3_test_msi(struct tg3 *tp)
8702 {
8703         int err;
8704         u16 pci_cmd;
8705
8706         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8707                 return 0;
8708
8709         /* Turn off SERR reporting in case MSI terminates with Master
8710          * Abort.
8711          */
8712         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8713         pci_write_config_word(tp->pdev, PCI_COMMAND,
8714                               pci_cmd & ~PCI_COMMAND_SERR);
8715
8716         err = tg3_test_interrupt(tp);
8717
8718         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8719
8720         if (!err)
8721                 return 0;
8722
8723         /* other failures */
8724         if (err != -EIO)
8725                 return err;
8726
8727         /* MSI test failed, go back to INTx mode */
8728         netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
8729                     "to INTx mode. Please report this failure to the PCI "
8730                     "maintainer and include system chipset information\n");
8731
8732         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8733
8734         pci_disable_msi(tp->pdev);
8735
8736         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8737         tp->napi[0].irq_vec = tp->pdev->irq;
8738
8739         err = tg3_request_irq(tp, 0);
8740         if (err)
8741                 return err;
8742
8743         /* Need to reset the chip because the MSI cycle may have terminated
8744          * with Master Abort.
8745          */
8746         tg3_full_lock(tp, 1);
8747
8748         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8749         err = tg3_init_hw(tp, 1);
8750
8751         tg3_full_unlock(tp);
8752
8753         if (err)
8754                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8755
8756         return err;
8757 }
8758
8759 static int tg3_request_firmware(struct tg3 *tp)
8760 {
8761         const __be32 *fw_data;
8762
8763         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8764                 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
8765                            tp->fw_needed);
8766                 return -ENOENT;
8767         }
8768
8769         fw_data = (void *)tp->fw->data;
8770
8771         /* Firmware blob starts with version numbers, followed by
8772          * start address and _full_ length including BSS sections
8773          * (which must be longer than the actual data, of course
8774          */
8775
8776         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
8777         if (tp->fw_len < (tp->fw->size - 12)) {
8778                 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
8779                            tp->fw_len, tp->fw_needed);
8780                 release_firmware(tp->fw);
8781                 tp->fw = NULL;
8782                 return -EINVAL;
8783         }
8784
8785         /* We no longer need firmware; we have it. */
8786         tp->fw_needed = NULL;
8787         return 0;
8788 }
8789
8790 static bool tg3_enable_msix(struct tg3 *tp)
8791 {
8792         int i, rc, cpus = num_online_cpus();
8793         struct msix_entry msix_ent[tp->irq_max];
8794
8795         if (cpus == 1)
8796                 /* Just fallback to the simpler MSI mode. */
8797                 return false;
8798
8799         /*
8800          * We want as many rx rings enabled as there are cpus.
8801          * The first MSIX vector only deals with link interrupts, etc,
8802          * so we add one to the number of vectors we are requesting.
8803          */
8804         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8805
8806         for (i = 0; i < tp->irq_max; i++) {
8807                 msix_ent[i].entry  = i;
8808                 msix_ent[i].vector = 0;
8809         }
8810
8811         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8812         if (rc < 0) {
8813                 return false;
8814         } else if (rc != 0) {
8815                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8816                         return false;
8817                 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
8818                               tp->irq_cnt, rc);
8819                 tp->irq_cnt = rc;
8820         }
8821
8822         for (i = 0; i < tp->irq_max; i++)
8823                 tp->napi[i].irq_vec = msix_ent[i].vector;
8824
8825         tp->dev->real_num_tx_queues = 1;
8826         if (tp->irq_cnt > 1)
8827                 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8828
8829         return true;
8830 }
8831
8832 static void tg3_ints_init(struct tg3 *tp)
8833 {
8834         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8835             !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8836                 /* All MSI supporting chips should support tagged
8837                  * status.  Assert that this is the case.
8838                  */
8839                 netdev_warn(tp->dev,
8840                             "MSI without TAGGED_STATUS? Not using MSI\n");
8841                 goto defcfg;
8842         }
8843
8844         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8845                 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8846         else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8847                  pci_enable_msi(tp->pdev) == 0)
8848                 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8849
8850         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8851                 u32 msi_mode = tr32(MSGINT_MODE);
8852                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8853                         msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8854                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8855         }
8856 defcfg:
8857         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8858                 tp->irq_cnt = 1;
8859                 tp->napi[0].irq_vec = tp->pdev->irq;
8860                 tp->dev->real_num_tx_queues = 1;
8861         }
8862 }
8863
8864 static void tg3_ints_fini(struct tg3 *tp)
8865 {
8866         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8867                 pci_disable_msix(tp->pdev);
8868         else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8869                 pci_disable_msi(tp->pdev);
8870         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8871         tp->tg3_flags3 &= ~(TG3_FLG3_ENABLE_RSS | TG3_FLG3_ENABLE_TSS);
8872 }
8873
8874 static int tg3_open(struct net_device *dev)
8875 {
8876         struct tg3 *tp = netdev_priv(dev);
8877         int i, err;
8878
8879         if (tp->fw_needed) {
8880                 err = tg3_request_firmware(tp);
8881                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8882                         if (err)
8883                                 return err;
8884                 } else if (err) {
8885                         netdev_warn(tp->dev, "TSO capability disabled\n");
8886                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8887                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8888                         netdev_notice(tp->dev, "TSO capability restored\n");
8889                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8890                 }
8891         }
8892
8893         netif_carrier_off(tp->dev);
8894
8895         err = tg3_set_power_state(tp, PCI_D0);
8896         if (err)
8897                 return err;
8898
8899         tg3_full_lock(tp, 0);
8900
8901         tg3_disable_ints(tp);
8902         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8903
8904         tg3_full_unlock(tp);
8905
8906         /*
8907          * Setup interrupts first so we know how
8908          * many NAPI resources to allocate
8909          */
8910         tg3_ints_init(tp);
8911
8912         /* The placement of this call is tied
8913          * to the setup and use of Host TX descriptors.
8914          */
8915         err = tg3_alloc_consistent(tp);
8916         if (err)
8917                 goto err_out1;
8918
8919         tg3_napi_enable(tp);
8920
8921         for (i = 0; i < tp->irq_cnt; i++) {
8922                 struct tg3_napi *tnapi = &tp->napi[i];
8923                 err = tg3_request_irq(tp, i);
8924                 if (err) {
8925                         for (i--; i >= 0; i--)
8926                                 free_irq(tnapi->irq_vec, tnapi);
8927                         break;
8928                 }
8929         }
8930
8931         if (err)
8932                 goto err_out2;
8933
8934         tg3_full_lock(tp, 0);
8935
8936         err = tg3_init_hw(tp, 1);
8937         if (err) {
8938                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8939                 tg3_free_rings(tp);
8940         } else {
8941                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8942                         tp->timer_offset = HZ;
8943                 else
8944                         tp->timer_offset = HZ / 10;
8945
8946                 BUG_ON(tp->timer_offset > HZ);
8947                 tp->timer_counter = tp->timer_multiplier =
8948                         (HZ / tp->timer_offset);
8949                 tp->asf_counter = tp->asf_multiplier =
8950                         ((HZ / tp->timer_offset) * 2);
8951
8952                 init_timer(&tp->timer);
8953                 tp->timer.expires = jiffies + tp->timer_offset;
8954                 tp->timer.data = (unsigned long) tp;
8955                 tp->timer.function = tg3_timer;
8956         }
8957
8958         tg3_full_unlock(tp);
8959
8960         if (err)
8961                 goto err_out3;
8962
8963         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8964                 err = tg3_test_msi(tp);
8965
8966                 if (err) {
8967                         tg3_full_lock(tp, 0);
8968                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8969                         tg3_free_rings(tp);
8970                         tg3_full_unlock(tp);
8971
8972                         goto err_out2;
8973                 }
8974
8975                 if (!(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8976                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8977                         u32 val = tr32(PCIE_TRANSACTION_CFG);
8978
8979                         tw32(PCIE_TRANSACTION_CFG,
8980                              val | PCIE_TRANS_CFG_1SHOT_MSI);
8981                 }
8982         }
8983
8984         tg3_phy_start(tp);
8985
8986         tg3_full_lock(tp, 0);
8987
8988         add_timer(&tp->timer);
8989         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8990         tg3_enable_ints(tp);
8991
8992         tg3_full_unlock(tp);
8993
8994         netif_tx_start_all_queues(dev);
8995
8996         return 0;
8997
8998 err_out3:
8999         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9000                 struct tg3_napi *tnapi = &tp->napi[i];
9001                 free_irq(tnapi->irq_vec, tnapi);
9002         }
9003
9004 err_out2:
9005         tg3_napi_disable(tp);
9006         tg3_free_consistent(tp);
9007
9008 err_out1:
9009         tg3_ints_fini(tp);
9010         return err;
9011 }
9012
9013 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
9014                                                  struct rtnl_link_stats64 *);
9015 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9016
9017 static int tg3_close(struct net_device *dev)
9018 {
9019         int i;
9020         struct tg3 *tp = netdev_priv(dev);
9021
9022         tg3_napi_disable(tp);
9023         cancel_work_sync(&tp->reset_task);
9024
9025         netif_tx_stop_all_queues(dev);
9026
9027         del_timer_sync(&tp->timer);
9028
9029         tg3_phy_stop(tp);
9030
9031         tg3_full_lock(tp, 1);
9032
9033         tg3_disable_ints(tp);
9034
9035         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9036         tg3_free_rings(tp);
9037         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9038
9039         tg3_full_unlock(tp);
9040
9041         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9042                 struct tg3_napi *tnapi = &tp->napi[i];
9043                 free_irq(tnapi->irq_vec, tnapi);
9044         }
9045
9046         tg3_ints_fini(tp);
9047
9048         tg3_get_stats64(tp->dev, &tp->net_stats_prev);
9049
9050         memcpy(&tp->estats_prev, tg3_get_estats(tp),
9051                sizeof(tp->estats_prev));
9052
9053         tg3_free_consistent(tp);
9054
9055         tg3_set_power_state(tp, PCI_D3hot);
9056
9057         netif_carrier_off(tp->dev);
9058
9059         return 0;
9060 }
9061
9062 static inline u64 get_stat64(tg3_stat64_t *val)
9063 {
9064        return ((u64)val->high << 32) | ((u64)val->low);
9065 }
9066
9067 static u64 calc_crc_errors(struct tg3 *tp)
9068 {
9069         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9070
9071         if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9072             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9073              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9074                 u32 val;
9075
9076                 spin_lock_bh(&tp->lock);
9077                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9078                         tg3_writephy(tp, MII_TG3_TEST1,
9079                                      val | MII_TG3_TEST1_CRC_EN);
9080                         tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
9081                 } else
9082                         val = 0;
9083                 spin_unlock_bh(&tp->lock);
9084
9085                 tp->phy_crc_errors += val;
9086
9087                 return tp->phy_crc_errors;
9088         }
9089
9090         return get_stat64(&hw_stats->rx_fcs_errors);
9091 }
9092
9093 #define ESTAT_ADD(member) \
9094         estats->member =        old_estats->member + \
9095                                 get_stat64(&hw_stats->member)
9096
9097 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9098 {
9099         struct tg3_ethtool_stats *estats = &tp->estats;
9100         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9101         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9102
9103         if (!hw_stats)
9104                 return old_estats;
9105
9106         ESTAT_ADD(rx_octets);
9107         ESTAT_ADD(rx_fragments);
9108         ESTAT_ADD(rx_ucast_packets);
9109         ESTAT_ADD(rx_mcast_packets);
9110         ESTAT_ADD(rx_bcast_packets);
9111         ESTAT_ADD(rx_fcs_errors);
9112         ESTAT_ADD(rx_align_errors);
9113         ESTAT_ADD(rx_xon_pause_rcvd);
9114         ESTAT_ADD(rx_xoff_pause_rcvd);
9115         ESTAT_ADD(rx_mac_ctrl_rcvd);
9116         ESTAT_ADD(rx_xoff_entered);
9117         ESTAT_ADD(rx_frame_too_long_errors);
9118         ESTAT_ADD(rx_jabbers);
9119         ESTAT_ADD(rx_undersize_packets);
9120         ESTAT_ADD(rx_in_length_errors);
9121         ESTAT_ADD(rx_out_length_errors);
9122         ESTAT_ADD(rx_64_or_less_octet_packets);
9123         ESTAT_ADD(rx_65_to_127_octet_packets);
9124         ESTAT_ADD(rx_128_to_255_octet_packets);
9125         ESTAT_ADD(rx_256_to_511_octet_packets);
9126         ESTAT_ADD(rx_512_to_1023_octet_packets);
9127         ESTAT_ADD(rx_1024_to_1522_octet_packets);
9128         ESTAT_ADD(rx_1523_to_2047_octet_packets);
9129         ESTAT_ADD(rx_2048_to_4095_octet_packets);
9130         ESTAT_ADD(rx_4096_to_8191_octet_packets);
9131         ESTAT_ADD(rx_8192_to_9022_octet_packets);
9132
9133         ESTAT_ADD(tx_octets);
9134         ESTAT_ADD(tx_collisions);
9135         ESTAT_ADD(tx_xon_sent);
9136         ESTAT_ADD(tx_xoff_sent);
9137         ESTAT_ADD(tx_flow_control);
9138         ESTAT_ADD(tx_mac_errors);
9139         ESTAT_ADD(tx_single_collisions);
9140         ESTAT_ADD(tx_mult_collisions);
9141         ESTAT_ADD(tx_deferred);
9142         ESTAT_ADD(tx_excessive_collisions);
9143         ESTAT_ADD(tx_late_collisions);
9144         ESTAT_ADD(tx_collide_2times);
9145         ESTAT_ADD(tx_collide_3times);
9146         ESTAT_ADD(tx_collide_4times);
9147         ESTAT_ADD(tx_collide_5times);
9148         ESTAT_ADD(tx_collide_6times);
9149         ESTAT_ADD(tx_collide_7times);
9150         ESTAT_ADD(tx_collide_8times);
9151         ESTAT_ADD(tx_collide_9times);
9152         ESTAT_ADD(tx_collide_10times);
9153         ESTAT_ADD(tx_collide_11times);
9154         ESTAT_ADD(tx_collide_12times);
9155         ESTAT_ADD(tx_collide_13times);
9156         ESTAT_ADD(tx_collide_14times);
9157         ESTAT_ADD(tx_collide_15times);
9158         ESTAT_ADD(tx_ucast_packets);
9159         ESTAT_ADD(tx_mcast_packets);
9160         ESTAT_ADD(tx_bcast_packets);
9161         ESTAT_ADD(tx_carrier_sense_errors);
9162         ESTAT_ADD(tx_discards);
9163         ESTAT_ADD(tx_errors);
9164
9165         ESTAT_ADD(dma_writeq_full);
9166         ESTAT_ADD(dma_write_prioq_full);
9167         ESTAT_ADD(rxbds_empty);
9168         ESTAT_ADD(rx_discards);
9169         ESTAT_ADD(rx_errors);
9170         ESTAT_ADD(rx_threshold_hit);
9171
9172         ESTAT_ADD(dma_readq_full);
9173         ESTAT_ADD(dma_read_prioq_full);
9174         ESTAT_ADD(tx_comp_queue_full);
9175
9176         ESTAT_ADD(ring_set_send_prod_index);
9177         ESTAT_ADD(ring_status_update);
9178         ESTAT_ADD(nic_irqs);
9179         ESTAT_ADD(nic_avoided_irqs);
9180         ESTAT_ADD(nic_tx_threshold_hit);
9181
9182         return estats;
9183 }
9184
9185 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
9186                                                  struct rtnl_link_stats64 *stats)
9187 {
9188         struct tg3 *tp = netdev_priv(dev);
9189         struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
9190         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9191
9192         if (!hw_stats)
9193                 return old_stats;
9194
9195         stats->rx_packets = old_stats->rx_packets +
9196                 get_stat64(&hw_stats->rx_ucast_packets) +
9197                 get_stat64(&hw_stats->rx_mcast_packets) +
9198                 get_stat64(&hw_stats->rx_bcast_packets);
9199
9200         stats->tx_packets = old_stats->tx_packets +
9201                 get_stat64(&hw_stats->tx_ucast_packets) +
9202                 get_stat64(&hw_stats->tx_mcast_packets) +
9203                 get_stat64(&hw_stats->tx_bcast_packets);
9204
9205         stats->rx_bytes = old_stats->rx_bytes +
9206                 get_stat64(&hw_stats->rx_octets);
9207         stats->tx_bytes = old_stats->tx_bytes +
9208                 get_stat64(&hw_stats->tx_octets);
9209
9210         stats->rx_errors = old_stats->rx_errors +
9211                 get_stat64(&hw_stats->rx_errors);
9212         stats->tx_errors = old_stats->tx_errors +
9213                 get_stat64(&hw_stats->tx_errors) +
9214                 get_stat64(&hw_stats->tx_mac_errors) +
9215                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9216                 get_stat64(&hw_stats->tx_discards);
9217
9218         stats->multicast = old_stats->multicast +
9219                 get_stat64(&hw_stats->rx_mcast_packets);
9220         stats->collisions = old_stats->collisions +
9221                 get_stat64(&hw_stats->tx_collisions);
9222
9223         stats->rx_length_errors = old_stats->rx_length_errors +
9224                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9225                 get_stat64(&hw_stats->rx_undersize_packets);
9226
9227         stats->rx_over_errors = old_stats->rx_over_errors +
9228                 get_stat64(&hw_stats->rxbds_empty);
9229         stats->rx_frame_errors = old_stats->rx_frame_errors +
9230                 get_stat64(&hw_stats->rx_align_errors);
9231         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9232                 get_stat64(&hw_stats->tx_discards);
9233         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9234                 get_stat64(&hw_stats->tx_carrier_sense_errors);
9235
9236         stats->rx_crc_errors = old_stats->rx_crc_errors +
9237                 calc_crc_errors(tp);
9238
9239         stats->rx_missed_errors = old_stats->rx_missed_errors +
9240                 get_stat64(&hw_stats->rx_discards);
9241
9242         return stats;
9243 }
9244
9245 static inline u32 calc_crc(unsigned char *buf, int len)
9246 {
9247         u32 reg;
9248         u32 tmp;
9249         int j, k;
9250
9251         reg = 0xffffffff;
9252
9253         for (j = 0; j < len; j++) {
9254                 reg ^= buf[j];
9255
9256                 for (k = 0; k < 8; k++) {
9257                         tmp = reg & 0x01;
9258
9259                         reg >>= 1;
9260
9261                         if (tmp)
9262                                 reg ^= 0xedb88320;
9263                 }
9264         }
9265
9266         return ~reg;
9267 }
9268
9269 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9270 {
9271         /* accept or reject all multicast frames */
9272         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9273         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9274         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9275         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9276 }
9277
9278 static void __tg3_set_rx_mode(struct net_device *dev)
9279 {
9280         struct tg3 *tp = netdev_priv(dev);
9281         u32 rx_mode;
9282
9283         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9284                                   RX_MODE_KEEP_VLAN_TAG);
9285
9286         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9287          * flag clear.
9288          */
9289 #if TG3_VLAN_TAG_USED
9290         if (!tp->vlgrp &&
9291             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9292                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9293 #else
9294         /* By definition, VLAN is disabled always in this
9295          * case.
9296          */
9297         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9298                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9299 #endif
9300
9301         if (dev->flags & IFF_PROMISC) {
9302                 /* Promiscuous mode. */
9303                 rx_mode |= RX_MODE_PROMISC;
9304         } else if (dev->flags & IFF_ALLMULTI) {
9305                 /* Accept all multicast. */
9306                 tg3_set_multi(tp, 1);
9307         } else if (netdev_mc_empty(dev)) {
9308                 /* Reject all multicast. */
9309                 tg3_set_multi(tp, 0);
9310         } else {
9311                 /* Accept one or more multicast(s). */
9312                 struct netdev_hw_addr *ha;
9313                 u32 mc_filter[4] = { 0, };
9314                 u32 regidx;
9315                 u32 bit;
9316                 u32 crc;
9317
9318                 netdev_for_each_mc_addr(ha, dev) {
9319                         crc = calc_crc(ha->addr, ETH_ALEN);
9320                         bit = ~crc & 0x7f;
9321                         regidx = (bit & 0x60) >> 5;
9322                         bit &= 0x1f;
9323                         mc_filter[regidx] |= (1 << bit);
9324                 }
9325
9326                 tw32(MAC_HASH_REG_0, mc_filter[0]);
9327                 tw32(MAC_HASH_REG_1, mc_filter[1]);
9328                 tw32(MAC_HASH_REG_2, mc_filter[2]);
9329                 tw32(MAC_HASH_REG_3, mc_filter[3]);
9330         }
9331
9332         if (rx_mode != tp->rx_mode) {
9333                 tp->rx_mode = rx_mode;
9334                 tw32_f(MAC_RX_MODE, rx_mode);
9335                 udelay(10);
9336         }
9337 }
9338
9339 static void tg3_set_rx_mode(struct net_device *dev)
9340 {
9341         struct tg3 *tp = netdev_priv(dev);
9342
9343         if (!netif_running(dev))
9344                 return;
9345
9346         tg3_full_lock(tp, 0);
9347         __tg3_set_rx_mode(dev);
9348         tg3_full_unlock(tp);
9349 }
9350
9351 #define TG3_REGDUMP_LEN         (32 * 1024)
9352
9353 static int tg3_get_regs_len(struct net_device *dev)
9354 {
9355         return TG3_REGDUMP_LEN;
9356 }
9357
9358 static void tg3_get_regs(struct net_device *dev,
9359                 struct ethtool_regs *regs, void *_p)
9360 {
9361         u32 *p = _p;
9362         struct tg3 *tp = netdev_priv(dev);
9363         u8 *orig_p = _p;
9364         int i;
9365
9366         regs->version = 0;
9367
9368         memset(p, 0, TG3_REGDUMP_LEN);
9369
9370         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9371                 return;
9372
9373         tg3_full_lock(tp, 0);
9374
9375 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
9376 #define GET_REG32_LOOP(base, len)               \
9377 do {    p = (u32 *)(orig_p + (base));           \
9378         for (i = 0; i < len; i += 4)            \
9379                 __GET_REG32((base) + i);        \
9380 } while (0)
9381 #define GET_REG32_1(reg)                        \
9382 do {    p = (u32 *)(orig_p + (reg));            \
9383         __GET_REG32((reg));                     \
9384 } while (0)
9385
9386         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9387         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9388         GET_REG32_LOOP(MAC_MODE, 0x4f0);
9389         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9390         GET_REG32_1(SNDDATAC_MODE);
9391         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9392         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9393         GET_REG32_1(SNDBDC_MODE);
9394         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9395         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9396         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9397         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9398         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9399         GET_REG32_1(RCVDCC_MODE);
9400         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9401         GET_REG32_LOOP(RCVCC_MODE, 0x14);
9402         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9403         GET_REG32_1(MBFREE_MODE);
9404         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9405         GET_REG32_LOOP(MEMARB_MODE, 0x10);
9406         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9407         GET_REG32_LOOP(RDMAC_MODE, 0x08);
9408         GET_REG32_LOOP(WDMAC_MODE, 0x08);
9409         GET_REG32_1(RX_CPU_MODE);
9410         GET_REG32_1(RX_CPU_STATE);
9411         GET_REG32_1(RX_CPU_PGMCTR);
9412         GET_REG32_1(RX_CPU_HWBKPT);
9413         GET_REG32_1(TX_CPU_MODE);
9414         GET_REG32_1(TX_CPU_STATE);
9415         GET_REG32_1(TX_CPU_PGMCTR);
9416         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9417         GET_REG32_LOOP(FTQ_RESET, 0x120);
9418         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9419         GET_REG32_1(DMAC_MODE);
9420         GET_REG32_LOOP(GRC_MODE, 0x4c);
9421         if (tp->tg3_flags & TG3_FLAG_NVRAM)
9422                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9423
9424 #undef __GET_REG32
9425 #undef GET_REG32_LOOP
9426 #undef GET_REG32_1
9427
9428         tg3_full_unlock(tp);
9429 }
9430
9431 static int tg3_get_eeprom_len(struct net_device *dev)
9432 {
9433         struct tg3 *tp = netdev_priv(dev);
9434
9435         return tp->nvram_size;
9436 }
9437
9438 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9439 {
9440         struct tg3 *tp = netdev_priv(dev);
9441         int ret;
9442         u8  *pd;
9443         u32 i, offset, len, b_offset, b_count;
9444         __be32 val;
9445
9446         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9447                 return -EINVAL;
9448
9449         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9450                 return -EAGAIN;
9451
9452         offset = eeprom->offset;
9453         len = eeprom->len;
9454         eeprom->len = 0;
9455
9456         eeprom->magic = TG3_EEPROM_MAGIC;
9457
9458         if (offset & 3) {
9459                 /* adjustments to start on required 4 byte boundary */
9460                 b_offset = offset & 3;
9461                 b_count = 4 - b_offset;
9462                 if (b_count > len) {
9463                         /* i.e. offset=1 len=2 */
9464                         b_count = len;
9465                 }
9466                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9467                 if (ret)
9468                         return ret;
9469                 memcpy(data, ((char *)&val) + b_offset, b_count);
9470                 len -= b_count;
9471                 offset += b_count;
9472                 eeprom->len += b_count;
9473         }
9474
9475         /* read bytes upto the last 4 byte boundary */
9476         pd = &data[eeprom->len];
9477         for (i = 0; i < (len - (len & 3)); i += 4) {
9478                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9479                 if (ret) {
9480                         eeprom->len += i;
9481                         return ret;
9482                 }
9483                 memcpy(pd + i, &val, 4);
9484         }
9485         eeprom->len += i;
9486
9487         if (len & 3) {
9488                 /* read last bytes not ending on 4 byte boundary */
9489                 pd = &data[eeprom->len];
9490                 b_count = len & 3;
9491                 b_offset = offset + len - b_count;
9492                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9493                 if (ret)
9494                         return ret;
9495                 memcpy(pd, &val, b_count);
9496                 eeprom->len += b_count;
9497         }
9498         return 0;
9499 }
9500
9501 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9502
9503 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9504 {
9505         struct tg3 *tp = netdev_priv(dev);
9506         int ret;
9507         u32 offset, len, b_offset, odd_len;
9508         u8 *buf;
9509         __be32 start, end;
9510
9511         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9512                 return -EAGAIN;
9513
9514         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9515             eeprom->magic != TG3_EEPROM_MAGIC)
9516                 return -EINVAL;
9517
9518         offset = eeprom->offset;
9519         len = eeprom->len;
9520
9521         if ((b_offset = (offset & 3))) {
9522                 /* adjustments to start on required 4 byte boundary */
9523                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9524                 if (ret)
9525                         return ret;
9526                 len += b_offset;
9527                 offset &= ~3;
9528                 if (len < 4)
9529                         len = 4;
9530         }
9531
9532         odd_len = 0;
9533         if (len & 3) {
9534                 /* adjustments to end on required 4 byte boundary */
9535                 odd_len = 1;
9536                 len = (len + 3) & ~3;
9537                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9538                 if (ret)
9539                         return ret;
9540         }
9541
9542         buf = data;
9543         if (b_offset || odd_len) {
9544                 buf = kmalloc(len, GFP_KERNEL);
9545                 if (!buf)
9546                         return -ENOMEM;
9547                 if (b_offset)
9548                         memcpy(buf, &start, 4);
9549                 if (odd_len)
9550                         memcpy(buf+len-4, &end, 4);
9551                 memcpy(buf + b_offset, data, eeprom->len);
9552         }
9553
9554         ret = tg3_nvram_write_block(tp, offset, len, buf);
9555
9556         if (buf != data)
9557                 kfree(buf);
9558
9559         return ret;
9560 }
9561
9562 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9563 {
9564         struct tg3 *tp = netdev_priv(dev);
9565
9566         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9567                 struct phy_device *phydev;
9568                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9569                         return -EAGAIN;
9570                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9571                 return phy_ethtool_gset(phydev, cmd);
9572         }
9573
9574         cmd->supported = (SUPPORTED_Autoneg);
9575
9576         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9577                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9578                                    SUPPORTED_1000baseT_Full);
9579
9580         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
9581                 cmd->supported |= (SUPPORTED_100baseT_Half |
9582                                   SUPPORTED_100baseT_Full |
9583                                   SUPPORTED_10baseT_Half |
9584                                   SUPPORTED_10baseT_Full |
9585                                   SUPPORTED_TP);
9586                 cmd->port = PORT_TP;
9587         } else {
9588                 cmd->supported |= SUPPORTED_FIBRE;
9589                 cmd->port = PORT_FIBRE;
9590         }
9591
9592         cmd->advertising = tp->link_config.advertising;
9593         if (netif_running(dev)) {
9594                 cmd->speed = tp->link_config.active_speed;
9595                 cmd->duplex = tp->link_config.active_duplex;
9596         }
9597         cmd->phy_address = tp->phy_addr;
9598         cmd->transceiver = XCVR_INTERNAL;
9599         cmd->autoneg = tp->link_config.autoneg;
9600         cmd->maxtxpkt = 0;
9601         cmd->maxrxpkt = 0;
9602         return 0;
9603 }
9604
9605 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9606 {
9607         struct tg3 *tp = netdev_priv(dev);
9608
9609         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9610                 struct phy_device *phydev;
9611                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9612                         return -EAGAIN;
9613                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9614                 return phy_ethtool_sset(phydev, cmd);
9615         }
9616
9617         if (cmd->autoneg != AUTONEG_ENABLE &&
9618             cmd->autoneg != AUTONEG_DISABLE)
9619                 return -EINVAL;
9620
9621         if (cmd->autoneg == AUTONEG_DISABLE &&
9622             cmd->duplex != DUPLEX_FULL &&
9623             cmd->duplex != DUPLEX_HALF)
9624                 return -EINVAL;
9625
9626         if (cmd->autoneg == AUTONEG_ENABLE) {
9627                 u32 mask = ADVERTISED_Autoneg |
9628                            ADVERTISED_Pause |
9629                            ADVERTISED_Asym_Pause;
9630
9631                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9632                         mask |= ADVERTISED_1000baseT_Half |
9633                                 ADVERTISED_1000baseT_Full;
9634
9635                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
9636                         mask |= ADVERTISED_100baseT_Half |
9637                                 ADVERTISED_100baseT_Full |
9638                                 ADVERTISED_10baseT_Half |
9639                                 ADVERTISED_10baseT_Full |
9640                                 ADVERTISED_TP;
9641                 else
9642                         mask |= ADVERTISED_FIBRE;
9643
9644                 if (cmd->advertising & ~mask)
9645                         return -EINVAL;
9646
9647                 mask &= (ADVERTISED_1000baseT_Half |
9648                          ADVERTISED_1000baseT_Full |
9649                          ADVERTISED_100baseT_Half |
9650                          ADVERTISED_100baseT_Full |
9651                          ADVERTISED_10baseT_Half |
9652                          ADVERTISED_10baseT_Full);
9653
9654                 cmd->advertising &= mask;
9655         } else {
9656                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
9657                         if (cmd->speed != SPEED_1000)
9658                                 return -EINVAL;
9659
9660                         if (cmd->duplex != DUPLEX_FULL)
9661                                 return -EINVAL;
9662                 } else {
9663                         if (cmd->speed != SPEED_100 &&
9664                             cmd->speed != SPEED_10)
9665                                 return -EINVAL;
9666                 }
9667         }
9668
9669         tg3_full_lock(tp, 0);
9670
9671         tp->link_config.autoneg = cmd->autoneg;
9672         if (cmd->autoneg == AUTONEG_ENABLE) {
9673                 tp->link_config.advertising = (cmd->advertising |
9674                                               ADVERTISED_Autoneg);
9675                 tp->link_config.speed = SPEED_INVALID;
9676                 tp->link_config.duplex = DUPLEX_INVALID;
9677         } else {
9678                 tp->link_config.advertising = 0;
9679                 tp->link_config.speed = cmd->speed;
9680                 tp->link_config.duplex = cmd->duplex;
9681         }
9682
9683         tp->link_config.orig_speed = tp->link_config.speed;
9684         tp->link_config.orig_duplex = tp->link_config.duplex;
9685         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9686
9687         if (netif_running(dev))
9688                 tg3_setup_phy(tp, 1);
9689
9690         tg3_full_unlock(tp);
9691
9692         return 0;
9693 }
9694
9695 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9696 {
9697         struct tg3 *tp = netdev_priv(dev);
9698
9699         strcpy(info->driver, DRV_MODULE_NAME);
9700         strcpy(info->version, DRV_MODULE_VERSION);
9701         strcpy(info->fw_version, tp->fw_ver);
9702         strcpy(info->bus_info, pci_name(tp->pdev));
9703 }
9704
9705 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9706 {
9707         struct tg3 *tp = netdev_priv(dev);
9708
9709         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9710             device_can_wakeup(&tp->pdev->dev))
9711                 wol->supported = WAKE_MAGIC;
9712         else
9713                 wol->supported = 0;
9714         wol->wolopts = 0;
9715         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9716             device_can_wakeup(&tp->pdev->dev))
9717                 wol->wolopts = WAKE_MAGIC;
9718         memset(&wol->sopass, 0, sizeof(wol->sopass));
9719 }
9720
9721 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9722 {
9723         struct tg3 *tp = netdev_priv(dev);
9724         struct device *dp = &tp->pdev->dev;
9725
9726         if (wol->wolopts & ~WAKE_MAGIC)
9727                 return -EINVAL;
9728         if ((wol->wolopts & WAKE_MAGIC) &&
9729             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9730                 return -EINVAL;
9731
9732         spin_lock_bh(&tp->lock);
9733         if (wol->wolopts & WAKE_MAGIC) {
9734                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9735                 device_set_wakeup_enable(dp, true);
9736         } else {
9737                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9738                 device_set_wakeup_enable(dp, false);
9739         }
9740         spin_unlock_bh(&tp->lock);
9741
9742         return 0;
9743 }
9744
9745 static u32 tg3_get_msglevel(struct net_device *dev)
9746 {
9747         struct tg3 *tp = netdev_priv(dev);
9748         return tp->msg_enable;
9749 }
9750
9751 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9752 {
9753         struct tg3 *tp = netdev_priv(dev);
9754         tp->msg_enable = value;
9755 }
9756
9757 static int tg3_set_tso(struct net_device *dev, u32 value)
9758 {
9759         struct tg3 *tp = netdev_priv(dev);
9760
9761         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9762                 if (value)
9763                         return -EINVAL;
9764                 return 0;
9765         }
9766         if ((dev->features & NETIF_F_IPV6_CSUM) &&
9767             ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9768              (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9769                 if (value) {
9770                         dev->features |= NETIF_F_TSO6;
9771                         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9772                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9773                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9774                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9775                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9776                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9777                                 dev->features |= NETIF_F_TSO_ECN;
9778                 } else
9779                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9780         }
9781         return ethtool_op_set_tso(dev, value);
9782 }
9783
9784 static int tg3_nway_reset(struct net_device *dev)
9785 {
9786         struct tg3 *tp = netdev_priv(dev);
9787         int r;
9788
9789         if (!netif_running(dev))
9790                 return -EAGAIN;
9791
9792         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
9793                 return -EINVAL;
9794
9795         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9796                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9797                         return -EAGAIN;
9798                 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9799         } else {
9800                 u32 bmcr;
9801
9802                 spin_lock_bh(&tp->lock);
9803                 r = -EINVAL;
9804                 tg3_readphy(tp, MII_BMCR, &bmcr);
9805                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9806                     ((bmcr & BMCR_ANENABLE) ||
9807                      (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
9808                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9809                                                    BMCR_ANENABLE);
9810                         r = 0;
9811                 }
9812                 spin_unlock_bh(&tp->lock);
9813         }
9814
9815         return r;
9816 }
9817
9818 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9819 {
9820         struct tg3 *tp = netdev_priv(dev);
9821
9822         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9823         ering->rx_mini_max_pending = 0;
9824         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9825                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9826         else
9827                 ering->rx_jumbo_max_pending = 0;
9828
9829         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9830
9831         ering->rx_pending = tp->rx_pending;
9832         ering->rx_mini_pending = 0;
9833         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9834                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9835         else
9836                 ering->rx_jumbo_pending = 0;
9837
9838         ering->tx_pending = tp->napi[0].tx_pending;
9839 }
9840
9841 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9842 {
9843         struct tg3 *tp = netdev_priv(dev);
9844         int i, irq_sync = 0, err = 0;
9845
9846         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9847             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9848             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9849             (ering->tx_pending <= MAX_SKB_FRAGS) ||
9850             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9851              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9852                 return -EINVAL;
9853
9854         if (netif_running(dev)) {
9855                 tg3_phy_stop(tp);
9856                 tg3_netif_stop(tp);
9857                 irq_sync = 1;
9858         }
9859
9860         tg3_full_lock(tp, irq_sync);
9861
9862         tp->rx_pending = ering->rx_pending;
9863
9864         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9865             tp->rx_pending > 63)
9866                 tp->rx_pending = 63;
9867         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9868
9869         for (i = 0; i < tp->irq_max; i++)
9870                 tp->napi[i].tx_pending = ering->tx_pending;
9871
9872         if (netif_running(dev)) {
9873                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9874                 err = tg3_restart_hw(tp, 1);
9875                 if (!err)
9876                         tg3_netif_start(tp);
9877         }
9878
9879         tg3_full_unlock(tp);
9880
9881         if (irq_sync && !err)
9882                 tg3_phy_start(tp);
9883
9884         return err;
9885 }
9886
9887 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9888 {
9889         struct tg3 *tp = netdev_priv(dev);
9890
9891         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9892
9893         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9894                 epause->rx_pause = 1;
9895         else
9896                 epause->rx_pause = 0;
9897
9898         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9899                 epause->tx_pause = 1;
9900         else
9901                 epause->tx_pause = 0;
9902 }
9903
9904 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9905 {
9906         struct tg3 *tp = netdev_priv(dev);
9907         int err = 0;
9908
9909         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9910                 u32 newadv;
9911                 struct phy_device *phydev;
9912
9913                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9914
9915                 if (!(phydev->supported & SUPPORTED_Pause) ||
9916                     (!(phydev->supported & SUPPORTED_Asym_Pause) &&
9917                      ((epause->rx_pause && !epause->tx_pause) ||
9918                       (!epause->rx_pause && epause->tx_pause))))
9919                         return -EINVAL;
9920
9921                 tp->link_config.flowctrl = 0;
9922                 if (epause->rx_pause) {
9923                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
9924
9925                         if (epause->tx_pause) {
9926                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9927                                 newadv = ADVERTISED_Pause;
9928                         } else
9929                                 newadv = ADVERTISED_Pause |
9930                                          ADVERTISED_Asym_Pause;
9931                 } else if (epause->tx_pause) {
9932                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
9933                         newadv = ADVERTISED_Asym_Pause;
9934                 } else
9935                         newadv = 0;
9936
9937                 if (epause->autoneg)
9938                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9939                 else
9940                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9941
9942                 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
9943                         u32 oldadv = phydev->advertising &
9944                                      (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
9945                         if (oldadv != newadv) {
9946                                 phydev->advertising &=
9947                                         ~(ADVERTISED_Pause |
9948                                           ADVERTISED_Asym_Pause);
9949                                 phydev->advertising |= newadv;
9950                                 if (phydev->autoneg) {
9951                                         /*
9952                                          * Always renegotiate the link to
9953                                          * inform our link partner of our
9954                                          * flow control settings, even if the
9955                                          * flow control is forced.  Let
9956                                          * tg3_adjust_link() do the final
9957                                          * flow control setup.
9958                                          */
9959                                         return phy_start_aneg(phydev);
9960                                 }
9961                         }
9962
9963                         if (!epause->autoneg)
9964                                 tg3_setup_flow_control(tp, 0, 0);
9965                 } else {
9966                         tp->link_config.orig_advertising &=
9967                                         ~(ADVERTISED_Pause |
9968                                           ADVERTISED_Asym_Pause);
9969                         tp->link_config.orig_advertising |= newadv;
9970                 }
9971         } else {
9972                 int irq_sync = 0;
9973
9974                 if (netif_running(dev)) {
9975                         tg3_netif_stop(tp);
9976                         irq_sync = 1;
9977                 }
9978
9979                 tg3_full_lock(tp, irq_sync);
9980
9981                 if (epause->autoneg)
9982                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9983                 else
9984                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9985                 if (epause->rx_pause)
9986                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
9987                 else
9988                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9989                 if (epause->tx_pause)
9990                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
9991                 else
9992                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9993
9994                 if (netif_running(dev)) {
9995                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9996                         err = tg3_restart_hw(tp, 1);
9997                         if (!err)
9998                                 tg3_netif_start(tp);
9999                 }
10000
10001                 tg3_full_unlock(tp);
10002         }
10003
10004         return err;
10005 }
10006
10007 static u32 tg3_get_rx_csum(struct net_device *dev)
10008 {
10009         struct tg3 *tp = netdev_priv(dev);
10010         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10011 }
10012
10013 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10014 {
10015         struct tg3 *tp = netdev_priv(dev);
10016
10017         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10018                 if (data != 0)
10019                         return -EINVAL;
10020                 return 0;
10021         }
10022
10023         spin_lock_bh(&tp->lock);
10024         if (data)
10025                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10026         else
10027                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10028         spin_unlock_bh(&tp->lock);
10029
10030         return 0;
10031 }
10032
10033 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10034 {
10035         struct tg3 *tp = netdev_priv(dev);
10036
10037         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10038                 if (data != 0)
10039                         return -EINVAL;
10040                 return 0;
10041         }
10042
10043         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10044                 ethtool_op_set_tx_ipv6_csum(dev, data);
10045         else
10046                 ethtool_op_set_tx_csum(dev, data);
10047
10048         return 0;
10049 }
10050
10051 static int tg3_get_sset_count(struct net_device *dev, int sset)
10052 {
10053         switch (sset) {
10054         case ETH_SS_TEST:
10055                 return TG3_NUM_TEST;
10056         case ETH_SS_STATS:
10057                 return TG3_NUM_STATS;
10058         default:
10059                 return -EOPNOTSUPP;
10060         }
10061 }
10062
10063 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
10064 {
10065         switch (stringset) {
10066         case ETH_SS_STATS:
10067                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10068                 break;
10069         case ETH_SS_TEST:
10070                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10071                 break;
10072         default:
10073                 WARN_ON(1);     /* we need a WARN() */
10074                 break;
10075         }
10076 }
10077
10078 static int tg3_phys_id(struct net_device *dev, u32 data)
10079 {
10080         struct tg3 *tp = netdev_priv(dev);
10081         int i;
10082
10083         if (!netif_running(tp->dev))
10084                 return -EAGAIN;
10085
10086         if (data == 0)
10087                 data = UINT_MAX / 2;
10088
10089         for (i = 0; i < (data * 2); i++) {
10090                 if ((i % 2) == 0)
10091                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10092                                            LED_CTRL_1000MBPS_ON |
10093                                            LED_CTRL_100MBPS_ON |
10094                                            LED_CTRL_10MBPS_ON |
10095                                            LED_CTRL_TRAFFIC_OVERRIDE |
10096                                            LED_CTRL_TRAFFIC_BLINK |
10097                                            LED_CTRL_TRAFFIC_LED);
10098
10099                 else
10100                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10101                                            LED_CTRL_TRAFFIC_OVERRIDE);
10102
10103                 if (msleep_interruptible(500))
10104                         break;
10105         }
10106         tw32(MAC_LED_CTRL, tp->led_ctrl);
10107         return 0;
10108 }
10109
10110 static void tg3_get_ethtool_stats(struct net_device *dev,
10111                                    struct ethtool_stats *estats, u64 *tmp_stats)
10112 {
10113         struct tg3 *tp = netdev_priv(dev);
10114         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10115 }
10116
10117 #define NVRAM_TEST_SIZE 0x100
10118 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
10119 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
10120 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
10121 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10122 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10123
10124 static int tg3_test_nvram(struct tg3 *tp)
10125 {
10126         u32 csum, magic;
10127         __be32 *buf;
10128         int i, j, k, err = 0, size;
10129
10130         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10131                 return 0;
10132
10133         if (tg3_nvram_read(tp, 0, &magic) != 0)
10134                 return -EIO;
10135
10136         if (magic == TG3_EEPROM_MAGIC)
10137                 size = NVRAM_TEST_SIZE;
10138         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10139                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10140                     TG3_EEPROM_SB_FORMAT_1) {
10141                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10142                         case TG3_EEPROM_SB_REVISION_0:
10143                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10144                                 break;
10145                         case TG3_EEPROM_SB_REVISION_2:
10146                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10147                                 break;
10148                         case TG3_EEPROM_SB_REVISION_3:
10149                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10150                                 break;
10151                         default:
10152                                 return 0;
10153                         }
10154                 } else
10155                         return 0;
10156         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10157                 size = NVRAM_SELFBOOT_HW_SIZE;
10158         else
10159                 return -EIO;
10160
10161         buf = kmalloc(size, GFP_KERNEL);
10162         if (buf == NULL)
10163                 return -ENOMEM;
10164
10165         err = -EIO;
10166         for (i = 0, j = 0; i < size; i += 4, j++) {
10167                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10168                 if (err)
10169                         break;
10170         }
10171         if (i < size)
10172                 goto out;
10173
10174         /* Selfboot format */
10175         magic = be32_to_cpu(buf[0]);
10176         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10177             TG3_EEPROM_MAGIC_FW) {
10178                 u8 *buf8 = (u8 *) buf, csum8 = 0;
10179
10180                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10181                     TG3_EEPROM_SB_REVISION_2) {
10182                         /* For rev 2, the csum doesn't include the MBA. */
10183                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10184                                 csum8 += buf8[i];
10185                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10186                                 csum8 += buf8[i];
10187                 } else {
10188                         for (i = 0; i < size; i++)
10189                                 csum8 += buf8[i];
10190                 }
10191
10192                 if (csum8 == 0) {
10193                         err = 0;
10194                         goto out;
10195                 }
10196
10197                 err = -EIO;
10198                 goto out;
10199         }
10200
10201         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10202             TG3_EEPROM_MAGIC_HW) {
10203                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10204                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10205                 u8 *buf8 = (u8 *) buf;
10206
10207                 /* Separate the parity bits and the data bytes.  */
10208                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10209                         if ((i == 0) || (i == 8)) {
10210                                 int l;
10211                                 u8 msk;
10212
10213                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10214                                         parity[k++] = buf8[i] & msk;
10215                                 i++;
10216                         } else if (i == 16) {
10217                                 int l;
10218                                 u8 msk;
10219
10220                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10221                                         parity[k++] = buf8[i] & msk;
10222                                 i++;
10223
10224                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10225                                         parity[k++] = buf8[i] & msk;
10226                                 i++;
10227                         }
10228                         data[j++] = buf8[i];
10229                 }
10230
10231                 err = -EIO;
10232                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10233                         u8 hw8 = hweight8(data[i]);
10234
10235                         if ((hw8 & 0x1) && parity[i])
10236                                 goto out;
10237                         else if (!(hw8 & 0x1) && !parity[i])
10238                                 goto out;
10239                 }
10240                 err = 0;
10241                 goto out;
10242         }
10243
10244         /* Bootstrap checksum at offset 0x10 */
10245         csum = calc_crc((unsigned char *) buf, 0x10);
10246         if (csum != be32_to_cpu(buf[0x10/4]))
10247                 goto out;
10248
10249         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10250         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10251         if (csum != be32_to_cpu(buf[0xfc/4]))
10252                 goto out;
10253
10254         err = 0;
10255
10256 out:
10257         kfree(buf);
10258         return err;
10259 }
10260
10261 #define TG3_SERDES_TIMEOUT_SEC  2
10262 #define TG3_COPPER_TIMEOUT_SEC  6
10263
10264 static int tg3_test_link(struct tg3 *tp)
10265 {
10266         int i, max;
10267
10268         if (!netif_running(tp->dev))
10269                 return -ENODEV;
10270
10271         if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
10272                 max = TG3_SERDES_TIMEOUT_SEC;
10273         else
10274                 max = TG3_COPPER_TIMEOUT_SEC;
10275
10276         for (i = 0; i < max; i++) {
10277                 if (netif_carrier_ok(tp->dev))
10278                         return 0;
10279
10280                 if (msleep_interruptible(1000))
10281                         break;
10282         }
10283
10284         return -EIO;
10285 }
10286
10287 /* Only test the commonly used registers */
10288 static int tg3_test_registers(struct tg3 *tp)
10289 {
10290         int i, is_5705, is_5750;
10291         u32 offset, read_mask, write_mask, val, save_val, read_val;
10292         static struct {
10293                 u16 offset;
10294                 u16 flags;
10295 #define TG3_FL_5705     0x1
10296 #define TG3_FL_NOT_5705 0x2
10297 #define TG3_FL_NOT_5788 0x4
10298 #define TG3_FL_NOT_5750 0x8
10299                 u32 read_mask;
10300                 u32 write_mask;
10301         } reg_tbl[] = {
10302                 /* MAC Control Registers */
10303                 { MAC_MODE, TG3_FL_NOT_5705,
10304                         0x00000000, 0x00ef6f8c },
10305                 { MAC_MODE, TG3_FL_5705,
10306                         0x00000000, 0x01ef6b8c },
10307                 { MAC_STATUS, TG3_FL_NOT_5705,
10308                         0x03800107, 0x00000000 },
10309                 { MAC_STATUS, TG3_FL_5705,
10310                         0x03800100, 0x00000000 },
10311                 { MAC_ADDR_0_HIGH, 0x0000,
10312                         0x00000000, 0x0000ffff },
10313                 { MAC_ADDR_0_LOW, 0x0000,
10314                         0x00000000, 0xffffffff },
10315                 { MAC_RX_MTU_SIZE, 0x0000,
10316                         0x00000000, 0x0000ffff },
10317                 { MAC_TX_MODE, 0x0000,
10318                         0x00000000, 0x00000070 },
10319                 { MAC_TX_LENGTHS, 0x0000,
10320                         0x00000000, 0x00003fff },
10321                 { MAC_RX_MODE, TG3_FL_NOT_5705,
10322                         0x00000000, 0x000007fc },
10323                 { MAC_RX_MODE, TG3_FL_5705,
10324                         0x00000000, 0x000007dc },
10325                 { MAC_HASH_REG_0, 0x0000,
10326                         0x00000000, 0xffffffff },
10327                 { MAC_HASH_REG_1, 0x0000,
10328                         0x00000000, 0xffffffff },
10329                 { MAC_HASH_REG_2, 0x0000,
10330                         0x00000000, 0xffffffff },
10331                 { MAC_HASH_REG_3, 0x0000,
10332                         0x00000000, 0xffffffff },
10333
10334                 /* Receive Data and Receive BD Initiator Control Registers. */
10335                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10336                         0x00000000, 0xffffffff },
10337                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10338                         0x00000000, 0xffffffff },
10339                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10340                         0x00000000, 0x00000003 },
10341                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10342                         0x00000000, 0xffffffff },
10343                 { RCVDBDI_STD_BD+0, 0x0000,
10344                         0x00000000, 0xffffffff },
10345                 { RCVDBDI_STD_BD+4, 0x0000,
10346                         0x00000000, 0xffffffff },
10347                 { RCVDBDI_STD_BD+8, 0x0000,
10348                         0x00000000, 0xffff0002 },
10349                 { RCVDBDI_STD_BD+0xc, 0x0000,
10350                         0x00000000, 0xffffffff },
10351
10352                 /* Receive BD Initiator Control Registers. */
10353                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10354                         0x00000000, 0xffffffff },
10355                 { RCVBDI_STD_THRESH, TG3_FL_5705,
10356                         0x00000000, 0x000003ff },
10357                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10358                         0x00000000, 0xffffffff },
10359
10360                 /* Host Coalescing Control Registers. */
10361                 { HOSTCC_MODE, TG3_FL_NOT_5705,
10362                         0x00000000, 0x00000004 },
10363                 { HOSTCC_MODE, TG3_FL_5705,
10364                         0x00000000, 0x000000f6 },
10365                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10366                         0x00000000, 0xffffffff },
10367                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10368                         0x00000000, 0x000003ff },
10369                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10370                         0x00000000, 0xffffffff },
10371                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10372                         0x00000000, 0x000003ff },
10373                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10374                         0x00000000, 0xffffffff },
10375                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10376                         0x00000000, 0x000000ff },
10377                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10378                         0x00000000, 0xffffffff },
10379                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10380                         0x00000000, 0x000000ff },
10381                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10382                         0x00000000, 0xffffffff },
10383                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10384                         0x00000000, 0xffffffff },
10385                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10386                         0x00000000, 0xffffffff },
10387                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10388                         0x00000000, 0x000000ff },
10389                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10390                         0x00000000, 0xffffffff },
10391                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10392                         0x00000000, 0x000000ff },
10393                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10394                         0x00000000, 0xffffffff },
10395                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10396                         0x00000000, 0xffffffff },
10397                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10398                         0x00000000, 0xffffffff },
10399                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10400                         0x00000000, 0xffffffff },
10401                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10402                         0x00000000, 0xffffffff },
10403                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10404                         0xffffffff, 0x00000000 },
10405                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10406                         0xffffffff, 0x00000000 },
10407
10408                 /* Buffer Manager Control Registers. */
10409                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10410                         0x00000000, 0x007fff80 },
10411                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10412                         0x00000000, 0x007fffff },
10413                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10414                         0x00000000, 0x0000003f },
10415                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10416                         0x00000000, 0x000001ff },
10417                 { BUFMGR_MB_HIGH_WATER, 0x0000,
10418                         0x00000000, 0x000001ff },
10419                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10420                         0xffffffff, 0x00000000 },
10421                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10422                         0xffffffff, 0x00000000 },
10423
10424                 /* Mailbox Registers */
10425                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10426                         0x00000000, 0x000001ff },
10427                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10428                         0x00000000, 0x000001ff },
10429                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10430                         0x00000000, 0x000007ff },
10431                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10432                         0x00000000, 0x000001ff },
10433
10434                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10435         };
10436
10437         is_5705 = is_5750 = 0;
10438         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10439                 is_5705 = 1;
10440                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10441                         is_5750 = 1;
10442         }
10443
10444         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10445                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10446                         continue;
10447
10448                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10449                         continue;
10450
10451                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10452                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
10453                         continue;
10454
10455                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10456                         continue;
10457
10458                 offset = (u32) reg_tbl[i].offset;
10459                 read_mask = reg_tbl[i].read_mask;
10460                 write_mask = reg_tbl[i].write_mask;
10461
10462                 /* Save the original register content */
10463                 save_val = tr32(offset);
10464
10465                 /* Determine the read-only value. */
10466                 read_val = save_val & read_mask;
10467
10468                 /* Write zero to the register, then make sure the read-only bits
10469                  * are not changed and the read/write bits are all zeros.
10470                  */
10471                 tw32(offset, 0);
10472
10473                 val = tr32(offset);
10474
10475                 /* Test the read-only and read/write bits. */
10476                 if (((val & read_mask) != read_val) || (val & write_mask))
10477                         goto out;
10478
10479                 /* Write ones to all the bits defined by RdMask and WrMask, then
10480                  * make sure the read-only bits are not changed and the
10481                  * read/write bits are all ones.
10482                  */
10483                 tw32(offset, read_mask | write_mask);
10484
10485                 val = tr32(offset);
10486
10487                 /* Test the read-only bits. */
10488                 if ((val & read_mask) != read_val)
10489                         goto out;
10490
10491                 /* Test the read/write bits. */
10492                 if ((val & write_mask) != write_mask)
10493                         goto out;
10494
10495                 tw32(offset, save_val);
10496         }
10497
10498         return 0;
10499
10500 out:
10501         if (netif_msg_hw(tp))
10502                 netdev_err(tp->dev,
10503                            "Register test failed at offset %x\n", offset);
10504         tw32(offset, save_val);
10505         return -EIO;
10506 }
10507
10508 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10509 {
10510         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10511         int i;
10512         u32 j;
10513
10514         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10515                 for (j = 0; j < len; j += 4) {
10516                         u32 val;
10517
10518                         tg3_write_mem(tp, offset + j, test_pattern[i]);
10519                         tg3_read_mem(tp, offset + j, &val);
10520                         if (val != test_pattern[i])
10521                                 return -EIO;
10522                 }
10523         }
10524         return 0;
10525 }
10526
10527 static int tg3_test_memory(struct tg3 *tp)
10528 {
10529         static struct mem_entry {
10530                 u32 offset;
10531                 u32 len;
10532         } mem_tbl_570x[] = {
10533                 { 0x00000000, 0x00b50},
10534                 { 0x00002000, 0x1c000},
10535                 { 0xffffffff, 0x00000}
10536         }, mem_tbl_5705[] = {
10537                 { 0x00000100, 0x0000c},
10538                 { 0x00000200, 0x00008},
10539                 { 0x00004000, 0x00800},
10540                 { 0x00006000, 0x01000},
10541                 { 0x00008000, 0x02000},
10542                 { 0x00010000, 0x0e000},
10543                 { 0xffffffff, 0x00000}
10544         }, mem_tbl_5755[] = {
10545                 { 0x00000200, 0x00008},
10546                 { 0x00004000, 0x00800},
10547                 { 0x00006000, 0x00800},
10548                 { 0x00008000, 0x02000},
10549                 { 0x00010000, 0x0c000},
10550                 { 0xffffffff, 0x00000}
10551         }, mem_tbl_5906[] = {
10552                 { 0x00000200, 0x00008},
10553                 { 0x00004000, 0x00400},
10554                 { 0x00006000, 0x00400},
10555                 { 0x00008000, 0x01000},
10556                 { 0x00010000, 0x01000},
10557                 { 0xffffffff, 0x00000}
10558         }, mem_tbl_5717[] = {
10559                 { 0x00000200, 0x00008},
10560                 { 0x00010000, 0x0a000},
10561                 { 0x00020000, 0x13c00},
10562                 { 0xffffffff, 0x00000}
10563         }, mem_tbl_57765[] = {
10564                 { 0x00000200, 0x00008},
10565                 { 0x00004000, 0x00800},
10566                 { 0x00006000, 0x09800},
10567                 { 0x00010000, 0x0a000},
10568                 { 0xffffffff, 0x00000}
10569         };
10570         struct mem_entry *mem_tbl;
10571         int err = 0;
10572         int i;
10573
10574         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
10575             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
10576                 mem_tbl = mem_tbl_5717;
10577         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10578                 mem_tbl = mem_tbl_57765;
10579         else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10580                 mem_tbl = mem_tbl_5755;
10581         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10582                 mem_tbl = mem_tbl_5906;
10583         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10584                 mem_tbl = mem_tbl_5705;
10585         else
10586                 mem_tbl = mem_tbl_570x;
10587
10588         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10589                 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
10590                 if (err)
10591                         break;
10592         }
10593
10594         return err;
10595 }
10596
10597 #define TG3_MAC_LOOPBACK        0
10598 #define TG3_PHY_LOOPBACK        1
10599
10600 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10601 {
10602         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10603         u32 desc_idx, coal_now;
10604         struct sk_buff *skb, *rx_skb;
10605         u8 *tx_data;
10606         dma_addr_t map;
10607         int num_pkts, tx_len, rx_len, i, err;
10608         struct tg3_rx_buffer_desc *desc;
10609         struct tg3_napi *tnapi, *rnapi;
10610         struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
10611
10612         tnapi = &tp->napi[0];
10613         rnapi = &tp->napi[0];
10614         if (tp->irq_cnt > 1) {
10615                 rnapi = &tp->napi[1];
10616                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
10617                         tnapi = &tp->napi[1];
10618         }
10619         coal_now = tnapi->coal_now | rnapi->coal_now;
10620
10621         if (loopback_mode == TG3_MAC_LOOPBACK) {
10622                 /* HW errata - mac loopback fails in some cases on 5780.
10623                  * Normal traffic and PHY loopback are not affected by
10624                  * errata.
10625                  */
10626                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10627                         return 0;
10628
10629                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10630                            MAC_MODE_PORT_INT_LPBACK;
10631                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10632                         mac_mode |= MAC_MODE_LINK_POLARITY;
10633                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
10634                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10635                 else
10636                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10637                 tw32(MAC_MODE, mac_mode);
10638         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10639                 u32 val;
10640
10641                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10642                         tg3_phy_fet_toggle_apd(tp, false);
10643                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10644                 } else
10645                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10646
10647                 tg3_phy_toggle_automdix(tp, 0);
10648
10649                 tg3_writephy(tp, MII_BMCR, val);
10650                 udelay(40);
10651
10652                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10653                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10654                         tg3_writephy(tp, MII_TG3_FET_PTEST,
10655                                      MII_TG3_FET_PTEST_FRC_TX_LINK |
10656                                      MII_TG3_FET_PTEST_FRC_TX_LOCK);
10657                         /* The write needs to be flushed for the AC131 */
10658                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10659                                 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
10660                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10661                 } else
10662                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10663
10664                 /* reset to prevent losing 1st rx packet intermittently */
10665                 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10666                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10667                         udelay(10);
10668                         tw32_f(MAC_RX_MODE, tp->rx_mode);
10669                 }
10670                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10671                         u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
10672                         if (masked_phy_id == TG3_PHY_ID_BCM5401)
10673                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10674                         else if (masked_phy_id == TG3_PHY_ID_BCM5411)
10675                                 mac_mode |= MAC_MODE_LINK_POLARITY;
10676                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
10677                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10678                 }
10679                 tw32(MAC_MODE, mac_mode);
10680         } else {
10681                 return -EINVAL;
10682         }
10683
10684         err = -EIO;
10685
10686         tx_len = 1514;
10687         skb = netdev_alloc_skb(tp->dev, tx_len);
10688         if (!skb)
10689                 return -ENOMEM;
10690
10691         tx_data = skb_put(skb, tx_len);
10692         memcpy(tx_data, tp->dev->dev_addr, 6);
10693         memset(tx_data + 6, 0x0, 8);
10694
10695         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10696
10697         for (i = 14; i < tx_len; i++)
10698                 tx_data[i] = (u8) (i & 0xff);
10699
10700         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10701         if (pci_dma_mapping_error(tp->pdev, map)) {
10702                 dev_kfree_skb(skb);
10703                 return -EIO;
10704         }
10705
10706         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10707                rnapi->coal_now);
10708
10709         udelay(10);
10710
10711         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10712
10713         num_pkts = 0;
10714
10715         tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10716
10717         tnapi->tx_prod++;
10718         num_pkts++;
10719
10720         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10721         tr32_mailbox(tnapi->prodmbox);
10722
10723         udelay(10);
10724
10725         /* 350 usec to allow enough time on some 10/100 Mbps devices.  */
10726         for (i = 0; i < 35; i++) {
10727                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10728                        coal_now);
10729
10730                 udelay(10);
10731
10732                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10733                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10734                 if ((tx_idx == tnapi->tx_prod) &&
10735                     (rx_idx == (rx_start_idx + num_pkts)))
10736                         break;
10737         }
10738
10739         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10740         dev_kfree_skb(skb);
10741
10742         if (tx_idx != tnapi->tx_prod)
10743                 goto out;
10744
10745         if (rx_idx != rx_start_idx + num_pkts)
10746                 goto out;
10747
10748         desc = &rnapi->rx_rcb[rx_start_idx];
10749         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10750         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10751         if (opaque_key != RXD_OPAQUE_RING_STD)
10752                 goto out;
10753
10754         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10755             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10756                 goto out;
10757
10758         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10759         if (rx_len != tx_len)
10760                 goto out;
10761
10762         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10763
10764         map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10765         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10766
10767         for (i = 14; i < tx_len; i++) {
10768                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10769                         goto out;
10770         }
10771         err = 0;
10772
10773         /* tg3_free_rings will unmap and free the rx_skb */
10774 out:
10775         return err;
10776 }
10777
10778 #define TG3_MAC_LOOPBACK_FAILED         1
10779 #define TG3_PHY_LOOPBACK_FAILED         2
10780 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
10781                                          TG3_PHY_LOOPBACK_FAILED)
10782
10783 static int tg3_test_loopback(struct tg3 *tp)
10784 {
10785         int err = 0;
10786         u32 cpmuctrl = 0;
10787
10788         if (!netif_running(tp->dev))
10789                 return TG3_LOOPBACK_FAILED;
10790
10791         err = tg3_reset_hw(tp, 1);
10792         if (err)
10793                 return TG3_LOOPBACK_FAILED;
10794
10795         /* Turn off gphy autopowerdown. */
10796         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
10797                 tg3_phy_toggle_apd(tp, false);
10798
10799         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10800                 int i;
10801                 u32 status;
10802
10803                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10804
10805                 /* Wait for up to 40 microseconds to acquire lock. */
10806                 for (i = 0; i < 4; i++) {
10807                         status = tr32(TG3_CPMU_MUTEX_GNT);
10808                         if (status == CPMU_MUTEX_GNT_DRIVER)
10809                                 break;
10810                         udelay(10);
10811                 }
10812
10813                 if (status != CPMU_MUTEX_GNT_DRIVER)
10814                         return TG3_LOOPBACK_FAILED;
10815
10816                 /* Turn off link-based power management. */
10817                 cpmuctrl = tr32(TG3_CPMU_CTRL);
10818                 tw32(TG3_CPMU_CTRL,
10819                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10820                                   CPMU_CTRL_LINK_AWARE_MODE));
10821         }
10822
10823         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10824                 err |= TG3_MAC_LOOPBACK_FAILED;
10825
10826         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10827                 tw32(TG3_CPMU_CTRL, cpmuctrl);
10828
10829                 /* Release the mutex */
10830                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10831         }
10832
10833         if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10834             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10835                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10836                         err |= TG3_PHY_LOOPBACK_FAILED;
10837         }
10838
10839         /* Re-enable gphy autopowerdown. */
10840         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
10841                 tg3_phy_toggle_apd(tp, true);
10842
10843         return err;
10844 }
10845
10846 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10847                           u64 *data)
10848 {
10849         struct tg3 *tp = netdev_priv(dev);
10850
10851         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10852                 tg3_set_power_state(tp, PCI_D0);
10853
10854         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10855
10856         if (tg3_test_nvram(tp) != 0) {
10857                 etest->flags |= ETH_TEST_FL_FAILED;
10858                 data[0] = 1;
10859         }
10860         if (tg3_test_link(tp) != 0) {
10861                 etest->flags |= ETH_TEST_FL_FAILED;
10862                 data[1] = 1;
10863         }
10864         if (etest->flags & ETH_TEST_FL_OFFLINE) {
10865                 int err, err2 = 0, irq_sync = 0;
10866
10867                 if (netif_running(dev)) {
10868                         tg3_phy_stop(tp);
10869                         tg3_netif_stop(tp);
10870                         irq_sync = 1;
10871                 }
10872
10873                 tg3_full_lock(tp, irq_sync);
10874
10875                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10876                 err = tg3_nvram_lock(tp);
10877                 tg3_halt_cpu(tp, RX_CPU_BASE);
10878                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10879                         tg3_halt_cpu(tp, TX_CPU_BASE);
10880                 if (!err)
10881                         tg3_nvram_unlock(tp);
10882
10883                 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
10884                         tg3_phy_reset(tp);
10885
10886                 if (tg3_test_registers(tp) != 0) {
10887                         etest->flags |= ETH_TEST_FL_FAILED;
10888                         data[2] = 1;
10889                 }
10890                 if (tg3_test_memory(tp) != 0) {
10891                         etest->flags |= ETH_TEST_FL_FAILED;
10892                         data[3] = 1;
10893                 }
10894                 if ((data[4] = tg3_test_loopback(tp)) != 0)
10895                         etest->flags |= ETH_TEST_FL_FAILED;
10896
10897                 tg3_full_unlock(tp);
10898
10899                 if (tg3_test_interrupt(tp) != 0) {
10900                         etest->flags |= ETH_TEST_FL_FAILED;
10901                         data[5] = 1;
10902                 }
10903
10904                 tg3_full_lock(tp, 0);
10905
10906                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10907                 if (netif_running(dev)) {
10908                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10909                         err2 = tg3_restart_hw(tp, 1);
10910                         if (!err2)
10911                                 tg3_netif_start(tp);
10912                 }
10913
10914                 tg3_full_unlock(tp);
10915
10916                 if (irq_sync && !err2)
10917                         tg3_phy_start(tp);
10918         }
10919         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10920                 tg3_set_power_state(tp, PCI_D3hot);
10921
10922 }
10923
10924 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10925 {
10926         struct mii_ioctl_data *data = if_mii(ifr);
10927         struct tg3 *tp = netdev_priv(dev);
10928         int err;
10929
10930         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10931                 struct phy_device *phydev;
10932                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10933                         return -EAGAIN;
10934                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10935                 return phy_mii_ioctl(phydev, ifr, cmd);
10936         }
10937
10938         switch (cmd) {
10939         case SIOCGMIIPHY:
10940                 data->phy_id = tp->phy_addr;
10941
10942                 /* fallthru */
10943         case SIOCGMIIREG: {
10944                 u32 mii_regval;
10945
10946                 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
10947                         break;                  /* We have no PHY */
10948
10949                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10950                         return -EAGAIN;
10951
10952                 spin_lock_bh(&tp->lock);
10953                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10954                 spin_unlock_bh(&tp->lock);
10955
10956                 data->val_out = mii_regval;
10957
10958                 return err;
10959         }
10960
10961         case SIOCSMIIREG:
10962                 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
10963                         break;                  /* We have no PHY */
10964
10965                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10966                         return -EAGAIN;
10967
10968                 spin_lock_bh(&tp->lock);
10969                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10970                 spin_unlock_bh(&tp->lock);
10971
10972                 return err;
10973
10974         default:
10975                 /* do nothing */
10976                 break;
10977         }
10978         return -EOPNOTSUPP;
10979 }
10980
10981 #if TG3_VLAN_TAG_USED
10982 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10983 {
10984         struct tg3 *tp = netdev_priv(dev);
10985
10986         if (!netif_running(dev)) {
10987                 tp->vlgrp = grp;
10988                 return;
10989         }
10990
10991         tg3_netif_stop(tp);
10992
10993         tg3_full_lock(tp, 0);
10994
10995         tp->vlgrp = grp;
10996
10997         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10998         __tg3_set_rx_mode(dev);
10999
11000         tg3_netif_start(tp);
11001
11002         tg3_full_unlock(tp);
11003 }
11004 #endif
11005
11006 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11007 {
11008         struct tg3 *tp = netdev_priv(dev);
11009
11010         memcpy(ec, &tp->coal, sizeof(*ec));
11011         return 0;
11012 }
11013
11014 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11015 {
11016         struct tg3 *tp = netdev_priv(dev);
11017         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11018         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11019
11020         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11021                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11022                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11023                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11024                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11025         }
11026
11027         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11028             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11029             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11030             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11031             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11032             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11033             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11034             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11035             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11036             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11037                 return -EINVAL;
11038
11039         /* No rx interrupts will be generated if both are zero */
11040         if ((ec->rx_coalesce_usecs == 0) &&
11041             (ec->rx_max_coalesced_frames == 0))
11042                 return -EINVAL;
11043
11044         /* No tx interrupts will be generated if both are zero */
11045         if ((ec->tx_coalesce_usecs == 0) &&
11046             (ec->tx_max_coalesced_frames == 0))
11047                 return -EINVAL;
11048
11049         /* Only copy relevant parameters, ignore all others. */
11050         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11051         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11052         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11053         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11054         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11055         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11056         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11057         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11058         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11059
11060         if (netif_running(dev)) {
11061                 tg3_full_lock(tp, 0);
11062                 __tg3_set_coalesce(tp, &tp->coal);
11063                 tg3_full_unlock(tp);
11064         }
11065         return 0;
11066 }
11067
11068 static const struct ethtool_ops tg3_ethtool_ops = {
11069         .get_settings           = tg3_get_settings,
11070         .set_settings           = tg3_set_settings,
11071         .get_drvinfo            = tg3_get_drvinfo,
11072         .get_regs_len           = tg3_get_regs_len,
11073         .get_regs               = tg3_get_regs,
11074         .get_wol                = tg3_get_wol,
11075         .set_wol                = tg3_set_wol,
11076         .get_msglevel           = tg3_get_msglevel,
11077         .set_msglevel           = tg3_set_msglevel,
11078         .nway_reset             = tg3_nway_reset,
11079         .get_link               = ethtool_op_get_link,
11080         .get_eeprom_len         = tg3_get_eeprom_len,
11081         .get_eeprom             = tg3_get_eeprom,
11082         .set_eeprom             = tg3_set_eeprom,
11083         .get_ringparam          = tg3_get_ringparam,
11084         .set_ringparam          = tg3_set_ringparam,
11085         .get_pauseparam         = tg3_get_pauseparam,
11086         .set_pauseparam         = tg3_set_pauseparam,
11087         .get_rx_csum            = tg3_get_rx_csum,
11088         .set_rx_csum            = tg3_set_rx_csum,
11089         .set_tx_csum            = tg3_set_tx_csum,
11090         .set_sg                 = ethtool_op_set_sg,
11091         .set_tso                = tg3_set_tso,
11092         .self_test              = tg3_self_test,
11093         .get_strings            = tg3_get_strings,
11094         .phys_id                = tg3_phys_id,
11095         .get_ethtool_stats      = tg3_get_ethtool_stats,
11096         .get_coalesce           = tg3_get_coalesce,
11097         .set_coalesce           = tg3_set_coalesce,
11098         .get_sset_count         = tg3_get_sset_count,
11099 };
11100
11101 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11102 {
11103         u32 cursize, val, magic;
11104
11105         tp->nvram_size = EEPROM_CHIP_SIZE;
11106
11107         if (tg3_nvram_read(tp, 0, &magic) != 0)
11108                 return;
11109
11110         if ((magic != TG3_EEPROM_MAGIC) &&
11111             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11112             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11113                 return;
11114
11115         /*
11116          * Size the chip by reading offsets at increasing powers of two.
11117          * When we encounter our validation signature, we know the addressing
11118          * has wrapped around, and thus have our chip size.
11119          */
11120         cursize = 0x10;
11121
11122         while (cursize < tp->nvram_size) {
11123                 if (tg3_nvram_read(tp, cursize, &val) != 0)
11124                         return;
11125
11126                 if (val == magic)
11127                         break;
11128
11129                 cursize <<= 1;
11130         }
11131
11132         tp->nvram_size = cursize;
11133 }
11134
11135 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11136 {
11137         u32 val;
11138
11139         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11140             tg3_nvram_read(tp, 0, &val) != 0)
11141                 return;
11142
11143         /* Selfboot format */
11144         if (val != TG3_EEPROM_MAGIC) {
11145                 tg3_get_eeprom_size(tp);
11146                 return;
11147         }
11148
11149         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11150                 if (val != 0) {
11151                         /* This is confusing.  We want to operate on the
11152                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
11153                          * call will read from NVRAM and byteswap the data
11154                          * according to the byteswapping settings for all
11155                          * other register accesses.  This ensures the data we
11156                          * want will always reside in the lower 16-bits.
11157                          * However, the data in NVRAM is in LE format, which
11158                          * means the data from the NVRAM read will always be
11159                          * opposite the endianness of the CPU.  The 16-bit
11160                          * byteswap then brings the data to CPU endianness.
11161                          */
11162                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11163                         return;
11164                 }
11165         }
11166         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11167 }
11168
11169 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11170 {
11171         u32 nvcfg1;
11172
11173         nvcfg1 = tr32(NVRAM_CFG1);
11174         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11175                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11176         } else {
11177                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11178                 tw32(NVRAM_CFG1, nvcfg1);
11179         }
11180
11181         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11182             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11183                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11184                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11185                         tp->nvram_jedecnum = JEDEC_ATMEL;
11186                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11187                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11188                         break;
11189                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11190                         tp->nvram_jedecnum = JEDEC_ATMEL;
11191                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11192                         break;
11193                 case FLASH_VENDOR_ATMEL_EEPROM:
11194                         tp->nvram_jedecnum = JEDEC_ATMEL;
11195                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11196                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11197                         break;
11198                 case FLASH_VENDOR_ST:
11199                         tp->nvram_jedecnum = JEDEC_ST;
11200                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11201                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11202                         break;
11203                 case FLASH_VENDOR_SAIFUN:
11204                         tp->nvram_jedecnum = JEDEC_SAIFUN;
11205                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11206                         break;
11207                 case FLASH_VENDOR_SST_SMALL:
11208                 case FLASH_VENDOR_SST_LARGE:
11209                         tp->nvram_jedecnum = JEDEC_SST;
11210                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11211                         break;
11212                 }
11213         } else {
11214                 tp->nvram_jedecnum = JEDEC_ATMEL;
11215                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11216                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11217         }
11218 }
11219
11220 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11221 {
11222         switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11223         case FLASH_5752PAGE_SIZE_256:
11224                 tp->nvram_pagesize = 256;
11225                 break;
11226         case FLASH_5752PAGE_SIZE_512:
11227                 tp->nvram_pagesize = 512;
11228                 break;
11229         case FLASH_5752PAGE_SIZE_1K:
11230                 tp->nvram_pagesize = 1024;
11231                 break;
11232         case FLASH_5752PAGE_SIZE_2K:
11233                 tp->nvram_pagesize = 2048;
11234                 break;
11235         case FLASH_5752PAGE_SIZE_4K:
11236                 tp->nvram_pagesize = 4096;
11237                 break;
11238         case FLASH_5752PAGE_SIZE_264:
11239                 tp->nvram_pagesize = 264;
11240                 break;
11241         case FLASH_5752PAGE_SIZE_528:
11242                 tp->nvram_pagesize = 528;
11243                 break;
11244         }
11245 }
11246
11247 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11248 {
11249         u32 nvcfg1;
11250
11251         nvcfg1 = tr32(NVRAM_CFG1);
11252
11253         /* NVRAM protection for TPM */
11254         if (nvcfg1 & (1 << 27))
11255                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11256
11257         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11258         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11259         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11260                 tp->nvram_jedecnum = JEDEC_ATMEL;
11261                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11262                 break;
11263         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11264                 tp->nvram_jedecnum = JEDEC_ATMEL;
11265                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11266                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11267                 break;
11268         case FLASH_5752VENDOR_ST_M45PE10:
11269         case FLASH_5752VENDOR_ST_M45PE20:
11270         case FLASH_5752VENDOR_ST_M45PE40:
11271                 tp->nvram_jedecnum = JEDEC_ST;
11272                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11273                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11274                 break;
11275         }
11276
11277         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11278                 tg3_nvram_get_pagesize(tp, nvcfg1);
11279         } else {
11280                 /* For eeprom, set pagesize to maximum eeprom size */
11281                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11282
11283                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11284                 tw32(NVRAM_CFG1, nvcfg1);
11285         }
11286 }
11287
11288 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11289 {
11290         u32 nvcfg1, protect = 0;
11291
11292         nvcfg1 = tr32(NVRAM_CFG1);
11293
11294         /* NVRAM protection for TPM */
11295         if (nvcfg1 & (1 << 27)) {
11296                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11297                 protect = 1;
11298         }
11299
11300         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11301         switch (nvcfg1) {
11302         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11303         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11304         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11305         case FLASH_5755VENDOR_ATMEL_FLASH_5:
11306                 tp->nvram_jedecnum = JEDEC_ATMEL;
11307                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11308                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11309                 tp->nvram_pagesize = 264;
11310                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11311                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11312                         tp->nvram_size = (protect ? 0x3e200 :
11313                                           TG3_NVRAM_SIZE_512KB);
11314                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11315                         tp->nvram_size = (protect ? 0x1f200 :
11316                                           TG3_NVRAM_SIZE_256KB);
11317                 else
11318                         tp->nvram_size = (protect ? 0x1f200 :
11319                                           TG3_NVRAM_SIZE_128KB);
11320                 break;
11321         case FLASH_5752VENDOR_ST_M45PE10:
11322         case FLASH_5752VENDOR_ST_M45PE20:
11323         case FLASH_5752VENDOR_ST_M45PE40:
11324                 tp->nvram_jedecnum = JEDEC_ST;
11325                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11326                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11327                 tp->nvram_pagesize = 256;
11328                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11329                         tp->nvram_size = (protect ?
11330                                           TG3_NVRAM_SIZE_64KB :
11331                                           TG3_NVRAM_SIZE_128KB);
11332                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11333                         tp->nvram_size = (protect ?
11334                                           TG3_NVRAM_SIZE_64KB :
11335                                           TG3_NVRAM_SIZE_256KB);
11336                 else
11337                         tp->nvram_size = (protect ?
11338                                           TG3_NVRAM_SIZE_128KB :
11339                                           TG3_NVRAM_SIZE_512KB);
11340                 break;
11341         }
11342 }
11343
11344 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11345 {
11346         u32 nvcfg1;
11347
11348         nvcfg1 = tr32(NVRAM_CFG1);
11349
11350         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11351         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11352         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11353         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11354         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11355                 tp->nvram_jedecnum = JEDEC_ATMEL;
11356                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11357                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11358
11359                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11360                 tw32(NVRAM_CFG1, nvcfg1);
11361                 break;
11362         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11363         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11364         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11365         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11366                 tp->nvram_jedecnum = JEDEC_ATMEL;
11367                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11368                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11369                 tp->nvram_pagesize = 264;
11370                 break;
11371         case FLASH_5752VENDOR_ST_M45PE10:
11372         case FLASH_5752VENDOR_ST_M45PE20:
11373         case FLASH_5752VENDOR_ST_M45PE40:
11374                 tp->nvram_jedecnum = JEDEC_ST;
11375                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11376                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11377                 tp->nvram_pagesize = 256;
11378                 break;
11379         }
11380 }
11381
11382 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11383 {
11384         u32 nvcfg1, protect = 0;
11385
11386         nvcfg1 = tr32(NVRAM_CFG1);
11387
11388         /* NVRAM protection for TPM */
11389         if (nvcfg1 & (1 << 27)) {
11390                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11391                 protect = 1;
11392         }
11393
11394         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11395         switch (nvcfg1) {
11396         case FLASH_5761VENDOR_ATMEL_ADB021D:
11397         case FLASH_5761VENDOR_ATMEL_ADB041D:
11398         case FLASH_5761VENDOR_ATMEL_ADB081D:
11399         case FLASH_5761VENDOR_ATMEL_ADB161D:
11400         case FLASH_5761VENDOR_ATMEL_MDB021D:
11401         case FLASH_5761VENDOR_ATMEL_MDB041D:
11402         case FLASH_5761VENDOR_ATMEL_MDB081D:
11403         case FLASH_5761VENDOR_ATMEL_MDB161D:
11404                 tp->nvram_jedecnum = JEDEC_ATMEL;
11405                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11406                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11407                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11408                 tp->nvram_pagesize = 256;
11409                 break;
11410         case FLASH_5761VENDOR_ST_A_M45PE20:
11411         case FLASH_5761VENDOR_ST_A_M45PE40:
11412         case FLASH_5761VENDOR_ST_A_M45PE80:
11413         case FLASH_5761VENDOR_ST_A_M45PE16:
11414         case FLASH_5761VENDOR_ST_M_M45PE20:
11415         case FLASH_5761VENDOR_ST_M_M45PE40:
11416         case FLASH_5761VENDOR_ST_M_M45PE80:
11417         case FLASH_5761VENDOR_ST_M_M45PE16:
11418                 tp->nvram_jedecnum = JEDEC_ST;
11419                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11420                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11421                 tp->nvram_pagesize = 256;
11422                 break;
11423         }
11424
11425         if (protect) {
11426                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11427         } else {
11428                 switch (nvcfg1) {
11429                 case FLASH_5761VENDOR_ATMEL_ADB161D:
11430                 case FLASH_5761VENDOR_ATMEL_MDB161D:
11431                 case FLASH_5761VENDOR_ST_A_M45PE16:
11432                 case FLASH_5761VENDOR_ST_M_M45PE16:
11433                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11434                         break;
11435                 case FLASH_5761VENDOR_ATMEL_ADB081D:
11436                 case FLASH_5761VENDOR_ATMEL_MDB081D:
11437                 case FLASH_5761VENDOR_ST_A_M45PE80:
11438                 case FLASH_5761VENDOR_ST_M_M45PE80:
11439                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11440                         break;
11441                 case FLASH_5761VENDOR_ATMEL_ADB041D:
11442                 case FLASH_5761VENDOR_ATMEL_MDB041D:
11443                 case FLASH_5761VENDOR_ST_A_M45PE40:
11444                 case FLASH_5761VENDOR_ST_M_M45PE40:
11445                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11446                         break;
11447                 case FLASH_5761VENDOR_ATMEL_ADB021D:
11448                 case FLASH_5761VENDOR_ATMEL_MDB021D:
11449                 case FLASH_5761VENDOR_ST_A_M45PE20:
11450                 case FLASH_5761VENDOR_ST_M_M45PE20:
11451                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11452                         break;
11453                 }
11454         }
11455 }
11456
11457 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11458 {
11459         tp->nvram_jedecnum = JEDEC_ATMEL;
11460         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11461         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11462 }
11463
11464 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11465 {
11466         u32 nvcfg1;
11467
11468         nvcfg1 = tr32(NVRAM_CFG1);
11469
11470         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11471         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11472         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11473                 tp->nvram_jedecnum = JEDEC_ATMEL;
11474                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11475                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11476
11477                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11478                 tw32(NVRAM_CFG1, nvcfg1);
11479                 return;
11480         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11481         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11482         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11483         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11484         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11485         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11486         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11487                 tp->nvram_jedecnum = JEDEC_ATMEL;
11488                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11489                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11490
11491                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11492                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11493                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11494                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11495                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11496                         break;
11497                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11498                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11499                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11500                         break;
11501                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11502                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11503                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11504                         break;
11505                 }
11506                 break;
11507         case FLASH_5752VENDOR_ST_M45PE10:
11508         case FLASH_5752VENDOR_ST_M45PE20:
11509         case FLASH_5752VENDOR_ST_M45PE40:
11510                 tp->nvram_jedecnum = JEDEC_ST;
11511                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11512                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11513
11514                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11515                 case FLASH_5752VENDOR_ST_M45PE10:
11516                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11517                         break;
11518                 case FLASH_5752VENDOR_ST_M45PE20:
11519                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11520                         break;
11521                 case FLASH_5752VENDOR_ST_M45PE40:
11522                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11523                         break;
11524                 }
11525                 break;
11526         default:
11527                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11528                 return;
11529         }
11530
11531         tg3_nvram_get_pagesize(tp, nvcfg1);
11532         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11533                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11534 }
11535
11536
11537 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11538 {
11539         u32 nvcfg1;
11540
11541         nvcfg1 = tr32(NVRAM_CFG1);
11542
11543         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11544         case FLASH_5717VENDOR_ATMEL_EEPROM:
11545         case FLASH_5717VENDOR_MICRO_EEPROM:
11546                 tp->nvram_jedecnum = JEDEC_ATMEL;
11547                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11548                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11549
11550                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11551                 tw32(NVRAM_CFG1, nvcfg1);
11552                 return;
11553         case FLASH_5717VENDOR_ATMEL_MDB011D:
11554         case FLASH_5717VENDOR_ATMEL_ADB011B:
11555         case FLASH_5717VENDOR_ATMEL_ADB011D:
11556         case FLASH_5717VENDOR_ATMEL_MDB021D:
11557         case FLASH_5717VENDOR_ATMEL_ADB021B:
11558         case FLASH_5717VENDOR_ATMEL_ADB021D:
11559         case FLASH_5717VENDOR_ATMEL_45USPT:
11560                 tp->nvram_jedecnum = JEDEC_ATMEL;
11561                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11562                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11563
11564                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11565                 case FLASH_5717VENDOR_ATMEL_MDB021D:
11566                 case FLASH_5717VENDOR_ATMEL_ADB021B:
11567                 case FLASH_5717VENDOR_ATMEL_ADB021D:
11568                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11569                         break;
11570                 default:
11571                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11572                         break;
11573                 }
11574                 break;
11575         case FLASH_5717VENDOR_ST_M_M25PE10:
11576         case FLASH_5717VENDOR_ST_A_M25PE10:
11577         case FLASH_5717VENDOR_ST_M_M45PE10:
11578         case FLASH_5717VENDOR_ST_A_M45PE10:
11579         case FLASH_5717VENDOR_ST_M_M25PE20:
11580         case FLASH_5717VENDOR_ST_A_M25PE20:
11581         case FLASH_5717VENDOR_ST_M_M45PE20:
11582         case FLASH_5717VENDOR_ST_A_M45PE20:
11583         case FLASH_5717VENDOR_ST_25USPT:
11584         case FLASH_5717VENDOR_ST_45USPT:
11585                 tp->nvram_jedecnum = JEDEC_ST;
11586                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11587                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11588
11589                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11590                 case FLASH_5717VENDOR_ST_M_M25PE20:
11591                 case FLASH_5717VENDOR_ST_A_M25PE20:
11592                 case FLASH_5717VENDOR_ST_M_M45PE20:
11593                 case FLASH_5717VENDOR_ST_A_M45PE20:
11594                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11595                         break;
11596                 default:
11597                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11598                         break;
11599                 }
11600                 break;
11601         default:
11602                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11603                 return;
11604         }
11605
11606         tg3_nvram_get_pagesize(tp, nvcfg1);
11607         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11608                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11609 }
11610
11611 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11612 static void __devinit tg3_nvram_init(struct tg3 *tp)
11613 {
11614         tw32_f(GRC_EEPROM_ADDR,
11615              (EEPROM_ADDR_FSM_RESET |
11616               (EEPROM_DEFAULT_CLOCK_PERIOD <<
11617                EEPROM_ADDR_CLKPERD_SHIFT)));
11618
11619         msleep(1);
11620
11621         /* Enable seeprom accesses. */
11622         tw32_f(GRC_LOCAL_CTRL,
11623              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11624         udelay(100);
11625
11626         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11627             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11628                 tp->tg3_flags |= TG3_FLAG_NVRAM;
11629
11630                 if (tg3_nvram_lock(tp)) {
11631                         netdev_warn(tp->dev,
11632                                     "Cannot get nvram lock, %s failed\n",
11633                                     __func__);
11634                         return;
11635                 }
11636                 tg3_enable_nvram_access(tp);
11637
11638                 tp->nvram_size = 0;
11639
11640                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11641                         tg3_get_5752_nvram_info(tp);
11642                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11643                         tg3_get_5755_nvram_info(tp);
11644                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11645                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11646                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11647                         tg3_get_5787_nvram_info(tp);
11648                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11649                         tg3_get_5761_nvram_info(tp);
11650                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11651                         tg3_get_5906_nvram_info(tp);
11652                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11653                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11654                         tg3_get_57780_nvram_info(tp);
11655                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
11656                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
11657                         tg3_get_5717_nvram_info(tp);
11658                 else
11659                         tg3_get_nvram_info(tp);
11660
11661                 if (tp->nvram_size == 0)
11662                         tg3_get_nvram_size(tp);
11663
11664                 tg3_disable_nvram_access(tp);
11665                 tg3_nvram_unlock(tp);
11666
11667         } else {
11668                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11669
11670                 tg3_get_eeprom_size(tp);
11671         }
11672 }
11673
11674 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11675                                     u32 offset, u32 len, u8 *buf)
11676 {
11677         int i, j, rc = 0;
11678         u32 val;
11679
11680         for (i = 0; i < len; i += 4) {
11681                 u32 addr;
11682                 __be32 data;
11683
11684                 addr = offset + i;
11685
11686                 memcpy(&data, buf + i, 4);
11687
11688                 /*
11689                  * The SEEPROM interface expects the data to always be opposite
11690                  * the native endian format.  We accomplish this by reversing
11691                  * all the operations that would have been performed on the
11692                  * data from a call to tg3_nvram_read_be32().
11693                  */
11694                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11695
11696                 val = tr32(GRC_EEPROM_ADDR);
11697                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11698
11699                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11700                         EEPROM_ADDR_READ);
11701                 tw32(GRC_EEPROM_ADDR, val |
11702                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
11703                         (addr & EEPROM_ADDR_ADDR_MASK) |
11704                         EEPROM_ADDR_START |
11705                         EEPROM_ADDR_WRITE);
11706
11707                 for (j = 0; j < 1000; j++) {
11708                         val = tr32(GRC_EEPROM_ADDR);
11709
11710                         if (val & EEPROM_ADDR_COMPLETE)
11711                                 break;
11712                         msleep(1);
11713                 }
11714                 if (!(val & EEPROM_ADDR_COMPLETE)) {
11715                         rc = -EBUSY;
11716                         break;
11717                 }
11718         }
11719
11720         return rc;
11721 }
11722
11723 /* offset and length are dword aligned */
11724 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11725                 u8 *buf)
11726 {
11727         int ret = 0;
11728         u32 pagesize = tp->nvram_pagesize;
11729         u32 pagemask = pagesize - 1;
11730         u32 nvram_cmd;
11731         u8 *tmp;
11732
11733         tmp = kmalloc(pagesize, GFP_KERNEL);
11734         if (tmp == NULL)
11735                 return -ENOMEM;
11736
11737         while (len) {
11738                 int j;
11739                 u32 phy_addr, page_off, size;
11740
11741                 phy_addr = offset & ~pagemask;
11742
11743                 for (j = 0; j < pagesize; j += 4) {
11744                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
11745                                                   (__be32 *) (tmp + j));
11746                         if (ret)
11747                                 break;
11748                 }
11749                 if (ret)
11750                         break;
11751
11752                 page_off = offset & pagemask;
11753                 size = pagesize;
11754                 if (len < size)
11755                         size = len;
11756
11757                 len -= size;
11758
11759                 memcpy(tmp + page_off, buf, size);
11760
11761                 offset = offset + (pagesize - page_off);
11762
11763                 tg3_enable_nvram_access(tp);
11764
11765                 /*
11766                  * Before we can erase the flash page, we need
11767                  * to issue a special "write enable" command.
11768                  */
11769                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11770
11771                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11772                         break;
11773
11774                 /* Erase the target page */
11775                 tw32(NVRAM_ADDR, phy_addr);
11776
11777                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11778                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11779
11780                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11781                         break;
11782
11783                 /* Issue another write enable to start the write. */
11784                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11785
11786                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11787                         break;
11788
11789                 for (j = 0; j < pagesize; j += 4) {
11790                         __be32 data;
11791
11792                         data = *((__be32 *) (tmp + j));
11793
11794                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
11795
11796                         tw32(NVRAM_ADDR, phy_addr + j);
11797
11798                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11799                                 NVRAM_CMD_WR;
11800
11801                         if (j == 0)
11802                                 nvram_cmd |= NVRAM_CMD_FIRST;
11803                         else if (j == (pagesize - 4))
11804                                 nvram_cmd |= NVRAM_CMD_LAST;
11805
11806                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11807                                 break;
11808                 }
11809                 if (ret)
11810                         break;
11811         }
11812
11813         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11814         tg3_nvram_exec_cmd(tp, nvram_cmd);
11815
11816         kfree(tmp);
11817
11818         return ret;
11819 }
11820
11821 /* offset and length are dword aligned */
11822 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11823                 u8 *buf)
11824 {
11825         int i, ret = 0;
11826
11827         for (i = 0; i < len; i += 4, offset += 4) {
11828                 u32 page_off, phy_addr, nvram_cmd;
11829                 __be32 data;
11830
11831                 memcpy(&data, buf + i, 4);
11832                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11833
11834                 page_off = offset % tp->nvram_pagesize;
11835
11836                 phy_addr = tg3_nvram_phys_addr(tp, offset);
11837
11838                 tw32(NVRAM_ADDR, phy_addr);
11839
11840                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11841
11842                 if (page_off == 0 || i == 0)
11843                         nvram_cmd |= NVRAM_CMD_FIRST;
11844                 if (page_off == (tp->nvram_pagesize - 4))
11845                         nvram_cmd |= NVRAM_CMD_LAST;
11846
11847                 if (i == (len - 4))
11848                         nvram_cmd |= NVRAM_CMD_LAST;
11849
11850                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11851                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11852                     (tp->nvram_jedecnum == JEDEC_ST) &&
11853                     (nvram_cmd & NVRAM_CMD_FIRST)) {
11854
11855                         if ((ret = tg3_nvram_exec_cmd(tp,
11856                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11857                                 NVRAM_CMD_DONE)))
11858
11859                                 break;
11860                 }
11861                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11862                         /* We always do complete word writes to eeprom. */
11863                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11864                 }
11865
11866                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11867                         break;
11868         }
11869         return ret;
11870 }
11871
11872 /* offset and length are dword aligned */
11873 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11874 {
11875         int ret;
11876
11877         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11878                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11879                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
11880                 udelay(40);
11881         }
11882
11883         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11884                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11885         } else {
11886                 u32 grc_mode;
11887
11888                 ret = tg3_nvram_lock(tp);
11889                 if (ret)
11890                         return ret;
11891
11892                 tg3_enable_nvram_access(tp);
11893                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11894                     !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
11895                         tw32(NVRAM_WRITE1, 0x406);
11896
11897                 grc_mode = tr32(GRC_MODE);
11898                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11899
11900                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11901                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11902
11903                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
11904                                 buf);
11905                 } else {
11906                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11907                                 buf);
11908                 }
11909
11910                 grc_mode = tr32(GRC_MODE);
11911                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11912
11913                 tg3_disable_nvram_access(tp);
11914                 tg3_nvram_unlock(tp);
11915         }
11916
11917         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11918                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11919                 udelay(40);
11920         }
11921
11922         return ret;
11923 }
11924
11925 struct subsys_tbl_ent {
11926         u16 subsys_vendor, subsys_devid;
11927         u32 phy_id;
11928 };
11929
11930 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
11931         /* Broadcom boards. */
11932         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11933           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
11934         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11935           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
11936         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11937           TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
11938         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11939           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
11940         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11941           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
11942         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11943           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
11944         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11945           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
11946         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11947           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
11948         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11949           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
11950         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11951           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
11952         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11953           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
11954
11955         /* 3com boards. */
11956         { TG3PCI_SUBVENDOR_ID_3COM,
11957           TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
11958         { TG3PCI_SUBVENDOR_ID_3COM,
11959           TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
11960         { TG3PCI_SUBVENDOR_ID_3COM,
11961           TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
11962         { TG3PCI_SUBVENDOR_ID_3COM,
11963           TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
11964         { TG3PCI_SUBVENDOR_ID_3COM,
11965           TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
11966
11967         /* DELL boards. */
11968         { TG3PCI_SUBVENDOR_ID_DELL,
11969           TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
11970         { TG3PCI_SUBVENDOR_ID_DELL,
11971           TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
11972         { TG3PCI_SUBVENDOR_ID_DELL,
11973           TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
11974         { TG3PCI_SUBVENDOR_ID_DELL,
11975           TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
11976
11977         /* Compaq boards. */
11978         { TG3PCI_SUBVENDOR_ID_COMPAQ,
11979           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
11980         { TG3PCI_SUBVENDOR_ID_COMPAQ,
11981           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
11982         { TG3PCI_SUBVENDOR_ID_COMPAQ,
11983           TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
11984         { TG3PCI_SUBVENDOR_ID_COMPAQ,
11985           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
11986         { TG3PCI_SUBVENDOR_ID_COMPAQ,
11987           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
11988
11989         /* IBM boards. */
11990         { TG3PCI_SUBVENDOR_ID_IBM,
11991           TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
11992 };
11993
11994 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
11995 {
11996         int i;
11997
11998         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11999                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12000                      tp->pdev->subsystem_vendor) &&
12001                     (subsys_id_to_phy_id[i].subsys_devid ==
12002                      tp->pdev->subsystem_device))
12003                         return &subsys_id_to_phy_id[i];
12004         }
12005         return NULL;
12006 }
12007
12008 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12009 {
12010         u32 val;
12011         u16 pmcsr;
12012
12013         /* On some early chips the SRAM cannot be accessed in D3hot state,
12014          * so need make sure we're in D0.
12015          */
12016         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12017         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12018         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12019         msleep(1);
12020
12021         /* Make sure register accesses (indirect or otherwise)
12022          * will function correctly.
12023          */
12024         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12025                                tp->misc_host_ctrl);
12026
12027         /* The memory arbiter has to be enabled in order for SRAM accesses
12028          * to succeed.  Normally on powerup the tg3 chip firmware will make
12029          * sure it is enabled, but other entities such as system netboot
12030          * code might disable it.
12031          */
12032         val = tr32(MEMARB_MODE);
12033         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12034
12035         tp->phy_id = TG3_PHY_ID_INVALID;
12036         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12037
12038         /* Assume an onboard device and WOL capable by default.  */
12039         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12040
12041         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12042                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12043                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12044                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12045                 }
12046                 val = tr32(VCPU_CFGSHDW);
12047                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12048                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12049                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12050                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
12051                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12052                 goto done;
12053         }
12054
12055         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12056         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12057                 u32 nic_cfg, led_cfg;
12058                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12059                 int eeprom_phy_serdes = 0;
12060
12061                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12062                 tp->nic_sram_data_cfg = nic_cfg;
12063
12064                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12065                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12066                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12067                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12068                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12069                     (ver > 0) && (ver < 0x100))
12070                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12071
12072                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12073                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12074
12075                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12076                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12077                         eeprom_phy_serdes = 1;
12078
12079                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12080                 if (nic_phy_id != 0) {
12081                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12082                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12083
12084                         eeprom_phy_id  = (id1 >> 16) << 10;
12085                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
12086                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
12087                 } else
12088                         eeprom_phy_id = 0;
12089
12090                 tp->phy_id = eeprom_phy_id;
12091                 if (eeprom_phy_serdes) {
12092                         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12093                                 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12094                         else
12095                                 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
12096                 }
12097
12098                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12099                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12100                                     SHASTA_EXT_LED_MODE_MASK);
12101                 else
12102                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12103
12104                 switch (led_cfg) {
12105                 default:
12106                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12107                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12108                         break;
12109
12110                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12111                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12112                         break;
12113
12114                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12115                         tp->led_ctrl = LED_CTRL_MODE_MAC;
12116
12117                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12118                          * read on some older 5700/5701 bootcode.
12119                          */
12120                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12121                             ASIC_REV_5700 ||
12122                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
12123                             ASIC_REV_5701)
12124                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12125
12126                         break;
12127
12128                 case SHASTA_EXT_LED_SHARED:
12129                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
12130                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12131                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12132                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12133                                                  LED_CTRL_MODE_PHY_2);
12134                         break;
12135
12136                 case SHASTA_EXT_LED_MAC:
12137                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12138                         break;
12139
12140                 case SHASTA_EXT_LED_COMBO:
12141                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
12142                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12143                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12144                                                  LED_CTRL_MODE_PHY_2);
12145                         break;
12146
12147                 }
12148
12149                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12150                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12151                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12152                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12153
12154                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12155                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12156
12157                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12158                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12159                         if ((tp->pdev->subsystem_vendor ==
12160                              PCI_VENDOR_ID_ARIMA) &&
12161                             (tp->pdev->subsystem_device == 0x205a ||
12162                              tp->pdev->subsystem_device == 0x2063))
12163                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12164                 } else {
12165                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12166                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12167                 }
12168
12169                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12170                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12171                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12172                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12173                 }
12174
12175                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12176                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12177                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12178
12179                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
12180                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12181                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12182
12183                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12184                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12185                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12186
12187                 if (cfg2 & (1 << 17))
12188                         tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
12189
12190                 /* serdes signal pre-emphasis in register 0x590 set by */
12191                 /* bootcode if bit 18 is set */
12192                 if (cfg2 & (1 << 18))
12193                         tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
12194
12195                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12196                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
12197                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12198                         tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
12199
12200                 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12201                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12202                     !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
12203                         u32 cfg3;
12204
12205                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12206                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12207                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12208                 }
12209
12210                 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12211                         tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
12212                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12213                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12214                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12215                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12216         }
12217 done:
12218         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12219         device_set_wakeup_enable(&tp->pdev->dev,
12220                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12221 }
12222
12223 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12224 {
12225         int i;
12226         u32 val;
12227
12228         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12229         tw32(OTP_CTRL, cmd);
12230
12231         /* Wait for up to 1 ms for command to execute. */
12232         for (i = 0; i < 100; i++) {
12233                 val = tr32(OTP_STATUS);
12234                 if (val & OTP_STATUS_CMD_DONE)
12235                         break;
12236                 udelay(10);
12237         }
12238
12239         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12240 }
12241
12242 /* Read the gphy configuration from the OTP region of the chip.  The gphy
12243  * configuration is a 32-bit value that straddles the alignment boundary.
12244  * We do two 32-bit reads and then shift and merge the results.
12245  */
12246 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12247 {
12248         u32 bhalf_otp, thalf_otp;
12249
12250         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12251
12252         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12253                 return 0;
12254
12255         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12256
12257         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12258                 return 0;
12259
12260         thalf_otp = tr32(OTP_READ_DATA);
12261
12262         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12263
12264         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12265                 return 0;
12266
12267         bhalf_otp = tr32(OTP_READ_DATA);
12268
12269         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12270 }
12271
12272 static int __devinit tg3_phy_probe(struct tg3 *tp)
12273 {
12274         u32 hw_phy_id_1, hw_phy_id_2;
12275         u32 hw_phy_id, hw_phy_id_masked;
12276         int err;
12277
12278         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12279                 return tg3_phy_init(tp);
12280
12281         /* Reading the PHY ID register can conflict with ASF
12282          * firmware access to the PHY hardware.
12283          */
12284         err = 0;
12285         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12286             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12287                 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
12288         } else {
12289                 /* Now read the physical PHY_ID from the chip and verify
12290                  * that it is sane.  If it doesn't look good, we fall back
12291                  * to either the hard-coded table based PHY_ID and failing
12292                  * that the value found in the eeprom area.
12293                  */
12294                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12295                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12296
12297                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
12298                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12299                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
12300
12301                 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
12302         }
12303
12304         if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
12305                 tp->phy_id = hw_phy_id;
12306                 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
12307                         tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12308                 else
12309                         tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
12310         } else {
12311                 if (tp->phy_id != TG3_PHY_ID_INVALID) {
12312                         /* Do nothing, phy ID already set up in
12313                          * tg3_get_eeprom_hw_cfg().
12314                          */
12315                 } else {
12316                         struct subsys_tbl_ent *p;
12317
12318                         /* No eeprom signature?  Try the hardcoded
12319                          * subsys device table.
12320                          */
12321                         p = tg3_lookup_by_subsys(tp);
12322                         if (!p)
12323                                 return -ENODEV;
12324
12325                         tp->phy_id = p->phy_id;
12326                         if (!tp->phy_id ||
12327                             tp->phy_id == TG3_PHY_ID_BCM8002)
12328                                 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12329                 }
12330         }
12331
12332         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
12333             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12334             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12335                 u32 bmsr, adv_reg, tg3_ctrl, mask;
12336
12337                 tg3_readphy(tp, MII_BMSR, &bmsr);
12338                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12339                     (bmsr & BMSR_LSTATUS))
12340                         goto skip_phy_reset;
12341
12342                 err = tg3_phy_reset(tp);
12343                 if (err)
12344                         return err;
12345
12346                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12347                            ADVERTISE_100HALF | ADVERTISE_100FULL |
12348                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12349                 tg3_ctrl = 0;
12350                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
12351                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12352                                     MII_TG3_CTRL_ADV_1000_FULL);
12353                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12354                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12355                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12356                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
12357                 }
12358
12359                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12360                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12361                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12362                 if (!tg3_copper_is_advertising_all(tp, mask)) {
12363                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12364
12365                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12366                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12367
12368                         tg3_writephy(tp, MII_BMCR,
12369                                      BMCR_ANENABLE | BMCR_ANRESTART);
12370                 }
12371                 tg3_phy_set_wirespeed(tp);
12372
12373                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12374                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12375                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12376         }
12377
12378 skip_phy_reset:
12379         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
12380                 err = tg3_init_5401phy_dsp(tp);
12381                 if (err)
12382                         return err;
12383
12384                 err = tg3_init_5401phy_dsp(tp);
12385         }
12386
12387         if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
12388                 tp->link_config.advertising =
12389                         (ADVERTISED_1000baseT_Half |
12390                          ADVERTISED_1000baseT_Full |
12391                          ADVERTISED_Autoneg |
12392                          ADVERTISED_FIBRE);
12393         if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
12394                 tp->link_config.advertising &=
12395                         ~(ADVERTISED_1000baseT_Half |
12396                           ADVERTISED_1000baseT_Full);
12397
12398         return err;
12399 }
12400
12401 static void __devinit tg3_read_vpd(struct tg3 *tp)
12402 {
12403         u8 *vpd_data;
12404         unsigned int block_end, rosize, len;
12405         int j, i = 0;
12406         u32 magic;
12407
12408         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12409             tg3_nvram_read(tp, 0x0, &magic))
12410                 goto out_no_vpd;
12411
12412         vpd_data = kmalloc(TG3_NVM_VPD_LEN, GFP_KERNEL);
12413         if (!vpd_data)
12414                 goto out_no_vpd;
12415
12416         if (magic == TG3_EEPROM_MAGIC) {
12417                 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12418                         u32 tmp;
12419
12420                         /* The data is in little-endian format in NVRAM.
12421                          * Use the big-endian read routines to preserve
12422                          * the byte order as it exists in NVRAM.
12423                          */
12424                         if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12425                                 goto out_not_found;
12426
12427                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12428                 }
12429         } else {
12430                 ssize_t cnt;
12431                 unsigned int pos = 0;
12432
12433                 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12434                         cnt = pci_read_vpd(tp->pdev, pos,
12435                                            TG3_NVM_VPD_LEN - pos,
12436                                            &vpd_data[pos]);
12437                         if (cnt == -ETIMEDOUT || -EINTR)
12438                                 cnt = 0;
12439                         else if (cnt < 0)
12440                                 goto out_not_found;
12441                 }
12442                 if (pos != TG3_NVM_VPD_LEN)
12443                         goto out_not_found;
12444         }
12445
12446         i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
12447                              PCI_VPD_LRDT_RO_DATA);
12448         if (i < 0)
12449                 goto out_not_found;
12450
12451         rosize = pci_vpd_lrdt_size(&vpd_data[i]);
12452         block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
12453         i += PCI_VPD_LRDT_TAG_SIZE;
12454
12455         if (block_end > TG3_NVM_VPD_LEN)
12456                 goto out_not_found;
12457
12458         j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12459                                       PCI_VPD_RO_KEYWORD_MFR_ID);
12460         if (j > 0) {
12461                 len = pci_vpd_info_field_size(&vpd_data[j]);
12462
12463                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12464                 if (j + len > block_end || len != 4 ||
12465                     memcmp(&vpd_data[j], "1028", 4))
12466                         goto partno;
12467
12468                 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12469                                               PCI_VPD_RO_KEYWORD_VENDOR0);
12470                 if (j < 0)
12471                         goto partno;
12472
12473                 len = pci_vpd_info_field_size(&vpd_data[j]);
12474
12475                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12476                 if (j + len > block_end)
12477                         goto partno;
12478
12479                 memcpy(tp->fw_ver, &vpd_data[j], len);
12480                 strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
12481         }
12482
12483 partno:
12484         i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12485                                       PCI_VPD_RO_KEYWORD_PARTNO);
12486         if (i < 0)
12487                 goto out_not_found;
12488
12489         len = pci_vpd_info_field_size(&vpd_data[i]);
12490
12491         i += PCI_VPD_INFO_FLD_HDR_SIZE;
12492         if (len > TG3_BPN_SIZE ||
12493             (len + i) > TG3_NVM_VPD_LEN)
12494                 goto out_not_found;
12495
12496         memcpy(tp->board_part_number, &vpd_data[i], len);
12497
12498 out_not_found:
12499         kfree(vpd_data);
12500         if (!tp->board_part_number[0])
12501                 return;
12502
12503 out_no_vpd:
12504         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12505                 strcpy(tp->board_part_number, "BCM95906");
12506         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12507                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12508                 strcpy(tp->board_part_number, "BCM57780");
12509         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12510                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12511                 strcpy(tp->board_part_number, "BCM57760");
12512         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12513                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12514                 strcpy(tp->board_part_number, "BCM57790");
12515         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12516                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12517                 strcpy(tp->board_part_number, "BCM57788");
12518         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12519                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
12520                 strcpy(tp->board_part_number, "BCM57761");
12521         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12522                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
12523                 strcpy(tp->board_part_number, "BCM57765");
12524         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12525                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
12526                 strcpy(tp->board_part_number, "BCM57781");
12527         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12528                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
12529                 strcpy(tp->board_part_number, "BCM57785");
12530         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12531                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
12532                 strcpy(tp->board_part_number, "BCM57791");
12533         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12534                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12535                 strcpy(tp->board_part_number, "BCM57795");
12536         else
12537                 strcpy(tp->board_part_number, "none");
12538 }
12539
12540 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12541 {
12542         u32 val;
12543
12544         if (tg3_nvram_read(tp, offset, &val) ||
12545             (val & 0xfc000000) != 0x0c000000 ||
12546             tg3_nvram_read(tp, offset + 4, &val) ||
12547             val != 0)
12548                 return 0;
12549
12550         return 1;
12551 }
12552
12553 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12554 {
12555         u32 val, offset, start, ver_offset;
12556         int i, dst_off;
12557         bool newver = false;
12558
12559         if (tg3_nvram_read(tp, 0xc, &offset) ||
12560             tg3_nvram_read(tp, 0x4, &start))
12561                 return;
12562
12563         offset = tg3_nvram_logical_addr(tp, offset);
12564
12565         if (tg3_nvram_read(tp, offset, &val))
12566                 return;
12567
12568         if ((val & 0xfc000000) == 0x0c000000) {
12569                 if (tg3_nvram_read(tp, offset + 4, &val))
12570                         return;
12571
12572                 if (val == 0)
12573                         newver = true;
12574         }
12575
12576         dst_off = strlen(tp->fw_ver);
12577
12578         if (newver) {
12579                 if (TG3_VER_SIZE - dst_off < 16 ||
12580                     tg3_nvram_read(tp, offset + 8, &ver_offset))
12581                         return;
12582
12583                 offset = offset + ver_offset - start;
12584                 for (i = 0; i < 16; i += 4) {
12585                         __be32 v;
12586                         if (tg3_nvram_read_be32(tp, offset + i, &v))
12587                                 return;
12588
12589                         memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
12590                 }
12591         } else {
12592                 u32 major, minor;
12593
12594                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12595                         return;
12596
12597                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12598                         TG3_NVM_BCVER_MAJSFT;
12599                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12600                 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
12601                          "v%d.%02d", major, minor);
12602         }
12603 }
12604
12605 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12606 {
12607         u32 val, major, minor;
12608
12609         /* Use native endian representation */
12610         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12611                 return;
12612
12613         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12614                 TG3_NVM_HWSB_CFG1_MAJSFT;
12615         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12616                 TG3_NVM_HWSB_CFG1_MINSFT;
12617
12618         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12619 }
12620
12621 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12622 {
12623         u32 offset, major, minor, build;
12624
12625         strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
12626
12627         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12628                 return;
12629
12630         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12631         case TG3_EEPROM_SB_REVISION_0:
12632                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12633                 break;
12634         case TG3_EEPROM_SB_REVISION_2:
12635                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12636                 break;
12637         case TG3_EEPROM_SB_REVISION_3:
12638                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12639                 break;
12640         case TG3_EEPROM_SB_REVISION_4:
12641                 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
12642                 break;
12643         case TG3_EEPROM_SB_REVISION_5:
12644                 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
12645                 break;
12646         default:
12647                 return;
12648         }
12649
12650         if (tg3_nvram_read(tp, offset, &val))
12651                 return;
12652
12653         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12654                 TG3_EEPROM_SB_EDH_BLD_SHFT;
12655         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12656                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12657         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
12658
12659         if (minor > 99 || build > 26)
12660                 return;
12661
12662         offset = strlen(tp->fw_ver);
12663         snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
12664                  " v%d.%02d", major, minor);
12665
12666         if (build > 0) {
12667                 offset = strlen(tp->fw_ver);
12668                 if (offset < TG3_VER_SIZE - 1)
12669                         tp->fw_ver[offset] = 'a' + build - 1;
12670         }
12671 }
12672
12673 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12674 {
12675         u32 val, offset, start;
12676         int i, vlen;
12677
12678         for (offset = TG3_NVM_DIR_START;
12679              offset < TG3_NVM_DIR_END;
12680              offset += TG3_NVM_DIRENT_SIZE) {
12681                 if (tg3_nvram_read(tp, offset, &val))
12682                         return;
12683
12684                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12685                         break;
12686         }
12687
12688         if (offset == TG3_NVM_DIR_END)
12689                 return;
12690
12691         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12692                 start = 0x08000000;
12693         else if (tg3_nvram_read(tp, offset - 4, &start))
12694                 return;
12695
12696         if (tg3_nvram_read(tp, offset + 4, &offset) ||
12697             !tg3_fw_img_is_valid(tp, offset) ||
12698             tg3_nvram_read(tp, offset + 8, &val))
12699                 return;
12700
12701         offset += val - start;
12702
12703         vlen = strlen(tp->fw_ver);
12704
12705         tp->fw_ver[vlen++] = ',';
12706         tp->fw_ver[vlen++] = ' ';
12707
12708         for (i = 0; i < 4; i++) {
12709                 __be32 v;
12710                 if (tg3_nvram_read_be32(tp, offset, &v))
12711                         return;
12712
12713                 offset += sizeof(v);
12714
12715                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12716                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12717                         break;
12718                 }
12719
12720                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12721                 vlen += sizeof(v);
12722         }
12723 }
12724
12725 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12726 {
12727         int vlen;
12728         u32 apedata;
12729         char *fwtype;
12730
12731         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12732             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
12733                 return;
12734
12735         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12736         if (apedata != APE_SEG_SIG_MAGIC)
12737                 return;
12738
12739         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12740         if (!(apedata & APE_FW_STATUS_READY))
12741                 return;
12742
12743         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12744
12745         if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) {
12746                 tp->tg3_flags3 |= TG3_FLG3_APE_HAS_NCSI;
12747                 fwtype = "NCSI";
12748         } else {
12749                 fwtype = "DASH";
12750         }
12751
12752         vlen = strlen(tp->fw_ver);
12753
12754         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
12755                  fwtype,
12756                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12757                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12758                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12759                  (apedata & APE_FW_VERSION_BLDMSK));
12760 }
12761
12762 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12763 {
12764         u32 val;
12765         bool vpd_vers = false;
12766
12767         if (tp->fw_ver[0] != 0)
12768                 vpd_vers = true;
12769
12770         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12771                 strcat(tp->fw_ver, "sb");
12772                 return;
12773         }
12774
12775         if (tg3_nvram_read(tp, 0, &val))
12776                 return;
12777
12778         if (val == TG3_EEPROM_MAGIC)
12779                 tg3_read_bc_ver(tp);
12780         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12781                 tg3_read_sb_ver(tp, val);
12782         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12783                 tg3_read_hwsb_ver(tp);
12784         else
12785                 return;
12786
12787         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12788              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
12789                 goto done;
12790
12791         tg3_read_mgmtfw_ver(tp);
12792
12793 done:
12794         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12795 }
12796
12797 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12798
12799 static void inline vlan_features_add(struct net_device *dev, unsigned long flags)
12800 {
12801 #if TG3_VLAN_TAG_USED
12802         dev->vlan_features |= flags;
12803 #endif
12804 }
12805
12806 static int __devinit tg3_get_invariants(struct tg3 *tp)
12807 {
12808         static struct pci_device_id write_reorder_chipsets[] = {
12809                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12810                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12811                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12812                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12813                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12814                              PCI_DEVICE_ID_VIA_8385_0) },
12815                 { },
12816         };
12817         u32 misc_ctrl_reg;
12818         u32 pci_state_reg, grc_misc_cfg;
12819         u32 val;
12820         u16 pci_cmd;
12821         int err;
12822
12823         /* Force memory write invalidate off.  If we leave it on,
12824          * then on 5700_BX chips we have to enable a workaround.
12825          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12826          * to match the cacheline size.  The Broadcom driver have this
12827          * workaround but turns MWI off all the times so never uses
12828          * it.  This seems to suggest that the workaround is insufficient.
12829          */
12830         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12831         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12832         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12833
12834         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12835          * has the register indirect write enable bit set before
12836          * we try to access any of the MMIO registers.  It is also
12837          * critical that the PCI-X hw workaround situation is decided
12838          * before that as well.
12839          */
12840         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12841                               &misc_ctrl_reg);
12842
12843         tp->pci_chip_rev_id = (misc_ctrl_reg >>
12844                                MISC_HOST_CTRL_CHIPREV_SHIFT);
12845         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12846                 u32 prod_id_asic_rev;
12847
12848                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12849                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12850                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724 ||
12851                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719)
12852                         pci_read_config_dword(tp->pdev,
12853                                               TG3PCI_GEN2_PRODID_ASICREV,
12854                                               &prod_id_asic_rev);
12855                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
12856                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
12857                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
12858                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
12859                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
12860                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12861                         pci_read_config_dword(tp->pdev,
12862                                               TG3PCI_GEN15_PRODID_ASICREV,
12863                                               &prod_id_asic_rev);
12864                 else
12865                         pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12866                                               &prod_id_asic_rev);
12867
12868                 tp->pci_chip_rev_id = prod_id_asic_rev;
12869         }
12870
12871         /* Wrong chip ID in 5752 A0. This code can be removed later
12872          * as A0 is not in production.
12873          */
12874         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12875                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12876
12877         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12878          * we need to disable memory and use config. cycles
12879          * only to access all registers. The 5702/03 chips
12880          * can mistakenly decode the special cycles from the
12881          * ICH chipsets as memory write cycles, causing corruption
12882          * of register and memory space. Only certain ICH bridges
12883          * will drive special cycles with non-zero data during the
12884          * address phase which can fall within the 5703's address
12885          * range. This is not an ICH bug as the PCI spec allows
12886          * non-zero address during special cycles. However, only
12887          * these ICH bridges are known to drive non-zero addresses
12888          * during special cycles.
12889          *
12890          * Since special cycles do not cross PCI bridges, we only
12891          * enable this workaround if the 5703 is on the secondary
12892          * bus of these ICH bridges.
12893          */
12894         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12895             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12896                 static struct tg3_dev_id {
12897                         u32     vendor;
12898                         u32     device;
12899                         u32     rev;
12900                 } ich_chipsets[] = {
12901                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12902                           PCI_ANY_ID },
12903                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12904                           PCI_ANY_ID },
12905                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12906                           0xa },
12907                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12908                           PCI_ANY_ID },
12909                         { },
12910                 };
12911                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12912                 struct pci_dev *bridge = NULL;
12913
12914                 while (pci_id->vendor != 0) {
12915                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
12916                                                 bridge);
12917                         if (!bridge) {
12918                                 pci_id++;
12919                                 continue;
12920                         }
12921                         if (pci_id->rev != PCI_ANY_ID) {
12922                                 if (bridge->revision > pci_id->rev)
12923                                         continue;
12924                         }
12925                         if (bridge->subordinate &&
12926                             (bridge->subordinate->number ==
12927                              tp->pdev->bus->number)) {
12928
12929                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12930                                 pci_dev_put(bridge);
12931                                 break;
12932                         }
12933                 }
12934         }
12935
12936         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12937                 static struct tg3_dev_id {
12938                         u32     vendor;
12939                         u32     device;
12940                 } bridge_chipsets[] = {
12941                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12942                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12943                         { },
12944                 };
12945                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12946                 struct pci_dev *bridge = NULL;
12947
12948                 while (pci_id->vendor != 0) {
12949                         bridge = pci_get_device(pci_id->vendor,
12950                                                 pci_id->device,
12951                                                 bridge);
12952                         if (!bridge) {
12953                                 pci_id++;
12954                                 continue;
12955                         }
12956                         if (bridge->subordinate &&
12957                             (bridge->subordinate->number <=
12958                              tp->pdev->bus->number) &&
12959                             (bridge->subordinate->subordinate >=
12960                              tp->pdev->bus->number)) {
12961                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12962                                 pci_dev_put(bridge);
12963                                 break;
12964                         }
12965                 }
12966         }
12967
12968         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12969          * DMA addresses > 40-bit. This bridge may have other additional
12970          * 57xx devices behind it in some 4-port NIC designs for example.
12971          * Any tg3 device found behind the bridge will also need the 40-bit
12972          * DMA workaround.
12973          */
12974         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12975             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12976                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
12977                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12978                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
12979         } else {
12980                 struct pci_dev *bridge = NULL;
12981
12982                 do {
12983                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12984                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
12985                                                 bridge);
12986                         if (bridge && bridge->subordinate &&
12987                             (bridge->subordinate->number <=
12988                              tp->pdev->bus->number) &&
12989                             (bridge->subordinate->subordinate >=
12990                              tp->pdev->bus->number)) {
12991                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12992                                 pci_dev_put(bridge);
12993                                 break;
12994                         }
12995                 } while (bridge);
12996         }
12997
12998         /* Initialize misc host control in PCI block. */
12999         tp->misc_host_ctrl |= (misc_ctrl_reg &
13000                                MISC_HOST_CTRL_CHIPREV);
13001         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13002                                tp->misc_host_ctrl);
13003
13004         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13005             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13006             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13007                 tp->pdev_peer = tg3_find_peer(tp);
13008
13009         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13010             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13011             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13012                 tp->tg3_flags3 |= TG3_FLG3_5717_PLUS;
13013
13014         /* Intentionally exclude ASIC_REV_5906 */
13015         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13016             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13017             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13018             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13019             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13020             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13021             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13022                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13023
13024         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13025             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13026             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13027             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13028             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13029                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13030
13031         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13032             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13033                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13034
13035         /* 5700 B0 chips do not support checksumming correctly due
13036          * to hardware bugs.
13037          */
13038         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13039                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13040         else {
13041                 unsigned long features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_GRO;
13042
13043                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13044                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13045                         features |= NETIF_F_IPV6_CSUM;
13046                 tp->dev->features |= features;
13047                 vlan_features_add(tp->dev, features);
13048         }
13049
13050         /* Determine TSO capabilities */
13051         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13052                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13053         else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13054                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13055                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13056         else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13057                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13058                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13059                     tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13060                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13061         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13062                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13063                    tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13064                 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13065                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13066                         tp->fw_needed = FIRMWARE_TG3TSO5;
13067                 else
13068                         tp->fw_needed = FIRMWARE_TG3TSO;
13069         }
13070
13071         tp->irq_max = 1;
13072
13073         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13074                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13075                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13076                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13077                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13078                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13079                      tp->pdev_peer == tp->pdev))
13080                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13081
13082                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13083                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13084                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13085                 }
13086
13087                 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
13088                         tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13089                         tp->irq_max = TG3_IRQ_MAX_VECS;
13090                 }
13091         }
13092
13093         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13094             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13095             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13096                 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13097         else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13098                 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13099                 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13100         }
13101
13102         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13103                 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13104
13105         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13106             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13107             (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13108                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13109
13110         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13111                               &pci_state_reg);
13112
13113         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13114         if (tp->pcie_cap != 0) {
13115                 u16 lnkctl;
13116
13117                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13118
13119                 pcie_set_readrq(tp->pdev, 4096);
13120
13121                 pci_read_config_word(tp->pdev,
13122                                      tp->pcie_cap + PCI_EXP_LNKCTL,
13123                                      &lnkctl);
13124                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13125                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13126                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13127                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13128                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13129                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13130                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13131                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13132                 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13133                         tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13134                 }
13135         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13136                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13137         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13138                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13139                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13140                 if (!tp->pcix_cap) {
13141                         dev_err(&tp->pdev->dev,
13142                                 "Cannot find PCI-X capability, aborting\n");
13143                         return -EIO;
13144                 }
13145
13146                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13147                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13148         }
13149
13150         /* If we have an AMD 762 or VIA K8T800 chipset, write
13151          * reordering to the mailbox registers done by the host
13152          * controller can cause major troubles.  We read back from
13153          * every mailbox register write to force the writes to be
13154          * posted to the chip in order.
13155          */
13156         if (pci_dev_present(write_reorder_chipsets) &&
13157             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13158                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13159
13160         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13161                              &tp->pci_cacheline_sz);
13162         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13163                              &tp->pci_lat_timer);
13164         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13165             tp->pci_lat_timer < 64) {
13166                 tp->pci_lat_timer = 64;
13167                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13168                                       tp->pci_lat_timer);
13169         }
13170
13171         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13172                 /* 5700 BX chips need to have their TX producer index
13173                  * mailboxes written twice to workaround a bug.
13174                  */
13175                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13176
13177                 /* If we are in PCI-X mode, enable register write workaround.
13178                  *
13179                  * The workaround is to use indirect register accesses
13180                  * for all chip writes not to mailbox registers.
13181                  */
13182                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13183                         u32 pm_reg;
13184
13185                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13186
13187                         /* The chip can have it's power management PCI config
13188                          * space registers clobbered due to this bug.
13189                          * So explicitly force the chip into D0 here.
13190                          */
13191                         pci_read_config_dword(tp->pdev,
13192                                               tp->pm_cap + PCI_PM_CTRL,
13193                                               &pm_reg);
13194                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13195                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13196                         pci_write_config_dword(tp->pdev,
13197                                                tp->pm_cap + PCI_PM_CTRL,
13198                                                pm_reg);
13199
13200                         /* Also, force SERR#/PERR# in PCI command. */
13201                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13202                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13203                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13204                 }
13205         }
13206
13207         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13208                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13209         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13210                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13211
13212         /* Chip-specific fixup from Broadcom driver */
13213         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13214             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13215                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13216                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13217         }
13218
13219         /* Default fast path register access methods */
13220         tp->read32 = tg3_read32;
13221         tp->write32 = tg3_write32;
13222         tp->read32_mbox = tg3_read32;
13223         tp->write32_mbox = tg3_write32;
13224         tp->write32_tx_mbox = tg3_write32;
13225         tp->write32_rx_mbox = tg3_write32;
13226
13227         /* Various workaround register access methods */
13228         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13229                 tp->write32 = tg3_write_indirect_reg32;
13230         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13231                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13232                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13233                 /*
13234                  * Back to back register writes can cause problems on these
13235                  * chips, the workaround is to read back all reg writes
13236                  * except those to mailbox regs.
13237                  *
13238                  * See tg3_write_indirect_reg32().
13239                  */
13240                 tp->write32 = tg3_write_flush_reg32;
13241         }
13242
13243         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13244             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13245                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13246                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13247                         tp->write32_rx_mbox = tg3_write_flush_reg32;
13248         }
13249
13250         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13251                 tp->read32 = tg3_read_indirect_reg32;
13252                 tp->write32 = tg3_write_indirect_reg32;
13253                 tp->read32_mbox = tg3_read_indirect_mbox;
13254                 tp->write32_mbox = tg3_write_indirect_mbox;
13255                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13256                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13257
13258                 iounmap(tp->regs);
13259                 tp->regs = NULL;
13260
13261                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13262                 pci_cmd &= ~PCI_COMMAND_MEMORY;
13263                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13264         }
13265         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13266                 tp->read32_mbox = tg3_read32_mbox_5906;
13267                 tp->write32_mbox = tg3_write32_mbox_5906;
13268                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13269                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13270         }
13271
13272         if (tp->write32 == tg3_write_indirect_reg32 ||
13273             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13274              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13275               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13276                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13277
13278         /* Get eeprom hw config before calling tg3_set_power_state().
13279          * In particular, the TG3_FLG2_IS_NIC flag must be
13280          * determined before calling tg3_set_power_state() so that
13281          * we know whether or not to switch out of Vaux power.
13282          * When the flag is set, it means that GPIO1 is used for eeprom
13283          * write protect and also implies that it is a LOM where GPIOs
13284          * are not used to switch power.
13285          */
13286         tg3_get_eeprom_hw_cfg(tp);
13287
13288         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13289                 /* Allow reads and writes to the
13290                  * APE register and memory space.
13291                  */
13292                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13293                                  PCISTATE_ALLOW_APE_SHMEM_WR |
13294                                  PCISTATE_ALLOW_APE_PSPACE_WR;
13295                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13296                                        pci_state_reg);
13297         }
13298
13299         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13300             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13301             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13302             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13303             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13304                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13305
13306         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13307          * GPIO1 driven high will bring 5700's external PHY out of reset.
13308          * It is also used as eeprom write protect on LOMs.
13309          */
13310         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13311         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13312             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13313                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13314                                        GRC_LCLCTRL_GPIO_OUTPUT1);
13315         /* Unused GPIO3 must be driven as output on 5752 because there
13316          * are no pull-up resistors on unused GPIO pins.
13317          */
13318         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13319                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13320
13321         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13322             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13323             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13324                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13325
13326         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13327             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13328                 /* Turn off the debug UART. */
13329                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13330                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13331                         /* Keep VMain power. */
13332                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13333                                               GRC_LCLCTRL_GPIO_OUTPUT0;
13334         }
13335
13336         /* Force the chip into D0. */
13337         err = tg3_set_power_state(tp, PCI_D0);
13338         if (err) {
13339                 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
13340                 return err;
13341         }
13342
13343         /* Derive initial jumbo mode from MTU assigned in
13344          * ether_setup() via the alloc_etherdev() call
13345          */
13346         if (tp->dev->mtu > ETH_DATA_LEN &&
13347             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13348                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13349
13350         /* Determine WakeOnLan speed to use. */
13351         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13352             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13353             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13354             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13355                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13356         } else {
13357                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13358         }
13359
13360         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13361                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
13362
13363         /* A few boards don't want Ethernet@WireSpeed phy feature */
13364         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13365             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13366              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13367              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13368             (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
13369             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
13370                 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
13371
13372         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13373             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13374                 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
13375         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13376                 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
13377
13378         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13379             !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
13380             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13381             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13382             !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
13383                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13384                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13385                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13386                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13387                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13388                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13389                                 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
13390                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13391                                 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
13392                 } else
13393                         tp->phy_flags |= TG3_PHYFLG_BER_BUG;
13394         }
13395
13396         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13397             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13398                 tp->phy_otp = tg3_read_otp_phycfg(tp);
13399                 if (tp->phy_otp == 0)
13400                         tp->phy_otp = TG3_OTP_DEFAULT;
13401         }
13402
13403         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13404                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13405         else
13406                 tp->mi_mode = MAC_MI_MODE_BASE;
13407
13408         tp->coalesce_mode = 0;
13409         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13410             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13411                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13412
13413         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13414             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13415                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13416
13417         err = tg3_mdio_init(tp);
13418         if (err)
13419                 return err;
13420
13421         /* Initialize data/descriptor byte/word swapping. */
13422         val = tr32(GRC_MODE);
13423         val &= GRC_MODE_HOST_STACKUP;
13424         tw32(GRC_MODE, val | tp->grc_mode);
13425
13426         tg3_switch_clocks(tp);
13427
13428         /* Clear this out for sanity. */
13429         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13430
13431         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13432                               &pci_state_reg);
13433         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13434             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13435                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13436
13437                 if (chiprevid == CHIPREV_ID_5701_A0 ||
13438                     chiprevid == CHIPREV_ID_5701_B0 ||
13439                     chiprevid == CHIPREV_ID_5701_B2 ||
13440                     chiprevid == CHIPREV_ID_5701_B5) {
13441                         void __iomem *sram_base;
13442
13443                         /* Write some dummy words into the SRAM status block
13444                          * area, see if it reads back correctly.  If the return
13445                          * value is bad, force enable the PCIX workaround.
13446                          */
13447                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13448
13449                         writel(0x00000000, sram_base);
13450                         writel(0x00000000, sram_base + 4);
13451                         writel(0xffffffff, sram_base + 4);
13452                         if (readl(sram_base) != 0x00000000)
13453                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13454                 }
13455         }
13456
13457         udelay(50);
13458         tg3_nvram_init(tp);
13459
13460         grc_misc_cfg = tr32(GRC_MISC_CFG);
13461         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13462
13463         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13464             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13465              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13466                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13467
13468         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13469             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13470                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13471         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13472                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13473                                       HOSTCC_MODE_CLRTICK_TXBD);
13474
13475                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13476                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13477                                        tp->misc_host_ctrl);
13478         }
13479
13480         /* Preserve the APE MAC_MODE bits */
13481         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13482                 tp->mac_mode = tr32(MAC_MODE) |
13483                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13484         else
13485                 tp->mac_mode = TG3_DEF_MAC_MODE;
13486
13487         /* these are limited to 10/100 only */
13488         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13489              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13490             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13491              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13492              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13493               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13494               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13495             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13496              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13497               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13498               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13499             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13500             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13501             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
13502             (tp->phy_flags & TG3_PHYFLG_IS_FET))
13503                 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
13504
13505         err = tg3_phy_probe(tp);
13506         if (err) {
13507                 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
13508                 /* ... but do not return immediately ... */
13509                 tg3_mdio_fini(tp);
13510         }
13511
13512         tg3_read_vpd(tp);
13513         tg3_read_fw_ver(tp);
13514
13515         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
13516                 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
13517         } else {
13518                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13519                         tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
13520                 else
13521                         tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
13522         }
13523
13524         /* 5700 {AX,BX} chips have a broken status block link
13525          * change bit implementation, so we must use the
13526          * status register in those cases.
13527          */
13528         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13529                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13530         else
13531                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13532
13533         /* The led_ctrl is set during tg3_phy_probe, here we might
13534          * have to force the link status polling mechanism based
13535          * upon subsystem IDs.
13536          */
13537         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13538             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13539             !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
13540                 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
13541                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13542         }
13543
13544         /* For all SERDES we poll the MAC status register. */
13545         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
13546                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13547         else
13548                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13549
13550         tp->rx_offset = NET_IP_ALIGN + TG3_RX_HEADROOM;
13551         tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
13552         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13553             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
13554                 tp->rx_offset -= NET_IP_ALIGN;
13555 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
13556                 tp->rx_copy_thresh = ~(u16)0;
13557 #endif
13558         }
13559
13560         tp->rx_std_max_post = TG3_RX_RING_SIZE;
13561
13562         /* Increment the rx prod index on the rx std ring by at most
13563          * 8 for these chips to workaround hw errata.
13564          */
13565         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13566             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13567             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13568                 tp->rx_std_max_post = 8;
13569
13570         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13571                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13572                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
13573
13574         return err;
13575 }
13576
13577 #ifdef CONFIG_SPARC
13578 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13579 {
13580         struct net_device *dev = tp->dev;
13581         struct pci_dev *pdev = tp->pdev;
13582         struct device_node *dp = pci_device_to_OF_node(pdev);
13583         const unsigned char *addr;
13584         int len;
13585
13586         addr = of_get_property(dp, "local-mac-address", &len);
13587         if (addr && len == 6) {
13588                 memcpy(dev->dev_addr, addr, 6);
13589                 memcpy(dev->perm_addr, dev->dev_addr, 6);
13590                 return 0;
13591         }
13592         return -ENODEV;
13593 }
13594
13595 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13596 {
13597         struct net_device *dev = tp->dev;
13598
13599         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13600         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13601         return 0;
13602 }
13603 #endif
13604
13605 static int __devinit tg3_get_device_address(struct tg3 *tp)
13606 {
13607         struct net_device *dev = tp->dev;
13608         u32 hi, lo, mac_offset;
13609         int addr_ok = 0;
13610
13611 #ifdef CONFIG_SPARC
13612         if (!tg3_get_macaddr_sparc(tp))
13613                 return 0;
13614 #endif
13615
13616         mac_offset = 0x7c;
13617         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13618             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13619                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13620                         mac_offset = 0xcc;
13621                 if (tg3_nvram_lock(tp))
13622                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13623                 else
13624                         tg3_nvram_unlock(tp);
13625         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13626                    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
13627                 if (PCI_FUNC(tp->pdev->devfn) & 1)
13628                         mac_offset = 0xcc;
13629                 if (PCI_FUNC(tp->pdev->devfn) > 1)
13630                         mac_offset += 0x18c;
13631         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13632                 mac_offset = 0x10;
13633
13634         /* First try to get it from MAC address mailbox. */
13635         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13636         if ((hi >> 16) == 0x484b) {
13637                 dev->dev_addr[0] = (hi >>  8) & 0xff;
13638                 dev->dev_addr[1] = (hi >>  0) & 0xff;
13639
13640                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13641                 dev->dev_addr[2] = (lo >> 24) & 0xff;
13642                 dev->dev_addr[3] = (lo >> 16) & 0xff;
13643                 dev->dev_addr[4] = (lo >>  8) & 0xff;
13644                 dev->dev_addr[5] = (lo >>  0) & 0xff;
13645
13646                 /* Some old bootcode may report a 0 MAC address in SRAM */
13647                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13648         }
13649         if (!addr_ok) {
13650                 /* Next, try NVRAM. */
13651                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13652                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13653                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13654                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13655                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13656                 }
13657                 /* Finally just fetch it out of the MAC control regs. */
13658                 else {
13659                         hi = tr32(MAC_ADDR_0_HIGH);
13660                         lo = tr32(MAC_ADDR_0_LOW);
13661
13662                         dev->dev_addr[5] = lo & 0xff;
13663                         dev->dev_addr[4] = (lo >> 8) & 0xff;
13664                         dev->dev_addr[3] = (lo >> 16) & 0xff;
13665                         dev->dev_addr[2] = (lo >> 24) & 0xff;
13666                         dev->dev_addr[1] = hi & 0xff;
13667                         dev->dev_addr[0] = (hi >> 8) & 0xff;
13668                 }
13669         }
13670
13671         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13672 #ifdef CONFIG_SPARC
13673                 if (!tg3_get_default_macaddr_sparc(tp))
13674                         return 0;
13675 #endif
13676                 return -EINVAL;
13677         }
13678         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13679         return 0;
13680 }
13681
13682 #define BOUNDARY_SINGLE_CACHELINE       1
13683 #define BOUNDARY_MULTI_CACHELINE        2
13684
13685 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13686 {
13687         int cacheline_size;
13688         u8 byte;
13689         int goal;
13690
13691         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13692         if (byte == 0)
13693                 cacheline_size = 1024;
13694         else
13695                 cacheline_size = (int) byte * 4;
13696
13697         /* On 5703 and later chips, the boundary bits have no
13698          * effect.
13699          */
13700         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13701             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13702             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13703                 goto out;
13704
13705 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13706         goal = BOUNDARY_MULTI_CACHELINE;
13707 #else
13708 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13709         goal = BOUNDARY_SINGLE_CACHELINE;
13710 #else
13711         goal = 0;
13712 #endif
13713 #endif
13714
13715         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
13716                 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13717                 goto out;
13718         }
13719
13720         if (!goal)
13721                 goto out;
13722
13723         /* PCI controllers on most RISC systems tend to disconnect
13724          * when a device tries to burst across a cache-line boundary.
13725          * Therefore, letting tg3 do so just wastes PCI bandwidth.
13726          *
13727          * Unfortunately, for PCI-E there are only limited
13728          * write-side controls for this, and thus for reads
13729          * we will still get the disconnects.  We'll also waste
13730          * these PCI cycles for both read and write for chips
13731          * other than 5700 and 5701 which do not implement the
13732          * boundary bits.
13733          */
13734         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13735             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13736                 switch (cacheline_size) {
13737                 case 16:
13738                 case 32:
13739                 case 64:
13740                 case 128:
13741                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13742                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13743                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13744                         } else {
13745                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13746                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13747                         }
13748                         break;
13749
13750                 case 256:
13751                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13752                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13753                         break;
13754
13755                 default:
13756                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13757                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13758                         break;
13759                 }
13760         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13761                 switch (cacheline_size) {
13762                 case 16:
13763                 case 32:
13764                 case 64:
13765                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13766                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13767                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13768                                 break;
13769                         }
13770                         /* fallthrough */
13771                 case 128:
13772                 default:
13773                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13774                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13775                         break;
13776                 }
13777         } else {
13778                 switch (cacheline_size) {
13779                 case 16:
13780                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13781                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13782                                         DMA_RWCTRL_WRITE_BNDRY_16);
13783                                 break;
13784                         }
13785                         /* fallthrough */
13786                 case 32:
13787                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13788                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13789                                         DMA_RWCTRL_WRITE_BNDRY_32);
13790                                 break;
13791                         }
13792                         /* fallthrough */
13793                 case 64:
13794                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13795                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13796                                         DMA_RWCTRL_WRITE_BNDRY_64);
13797                                 break;
13798                         }
13799                         /* fallthrough */
13800                 case 128:
13801                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13802                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13803                                         DMA_RWCTRL_WRITE_BNDRY_128);
13804                                 break;
13805                         }
13806                         /* fallthrough */
13807                 case 256:
13808                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
13809                                 DMA_RWCTRL_WRITE_BNDRY_256);
13810                         break;
13811                 case 512:
13812                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
13813                                 DMA_RWCTRL_WRITE_BNDRY_512);
13814                         break;
13815                 case 1024:
13816                 default:
13817                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13818                                 DMA_RWCTRL_WRITE_BNDRY_1024);
13819                         break;
13820                 }
13821         }
13822
13823 out:
13824         return val;
13825 }
13826
13827 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13828 {
13829         struct tg3_internal_buffer_desc test_desc;
13830         u32 sram_dma_descs;
13831         int i, ret;
13832
13833         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13834
13835         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13836         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13837         tw32(RDMAC_STATUS, 0);
13838         tw32(WDMAC_STATUS, 0);
13839
13840         tw32(BUFMGR_MODE, 0);
13841         tw32(FTQ_RESET, 0);
13842
13843         test_desc.addr_hi = ((u64) buf_dma) >> 32;
13844         test_desc.addr_lo = buf_dma & 0xffffffff;
13845         test_desc.nic_mbuf = 0x00002100;
13846         test_desc.len = size;
13847
13848         /*
13849          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13850          * the *second* time the tg3 driver was getting loaded after an
13851          * initial scan.
13852          *
13853          * Broadcom tells me:
13854          *   ...the DMA engine is connected to the GRC block and a DMA
13855          *   reset may affect the GRC block in some unpredictable way...
13856          *   The behavior of resets to individual blocks has not been tested.
13857          *
13858          * Broadcom noted the GRC reset will also reset all sub-components.
13859          */
13860         if (to_device) {
13861                 test_desc.cqid_sqid = (13 << 8) | 2;
13862
13863                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13864                 udelay(40);
13865         } else {
13866                 test_desc.cqid_sqid = (16 << 8) | 7;
13867
13868                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13869                 udelay(40);
13870         }
13871         test_desc.flags = 0x00000005;
13872
13873         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13874                 u32 val;
13875
13876                 val = *(((u32 *)&test_desc) + i);
13877                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13878                                        sram_dma_descs + (i * sizeof(u32)));
13879                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13880         }
13881         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13882
13883         if (to_device)
13884                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13885         else
13886                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13887
13888         ret = -ENODEV;
13889         for (i = 0; i < 40; i++) {
13890                 u32 val;
13891
13892                 if (to_device)
13893                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13894                 else
13895                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13896                 if ((val & 0xffff) == sram_dma_descs) {
13897                         ret = 0;
13898                         break;
13899                 }
13900
13901                 udelay(100);
13902         }
13903
13904         return ret;
13905 }
13906
13907 #define TEST_BUFFER_SIZE        0x2000
13908
13909 static int __devinit tg3_test_dma(struct tg3 *tp)
13910 {
13911         dma_addr_t buf_dma;
13912         u32 *buf, saved_dma_rwctrl;
13913         int ret = 0;
13914
13915         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13916         if (!buf) {
13917                 ret = -ENOMEM;
13918                 goto out_nofree;
13919         }
13920
13921         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13922                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13923
13924         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13925
13926         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13927                 goto out;
13928
13929         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13930                 /* DMA read watermark not used on PCIE */
13931                 tp->dma_rwctrl |= 0x00180000;
13932         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
13933                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13934                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
13935                         tp->dma_rwctrl |= 0x003f0000;
13936                 else
13937                         tp->dma_rwctrl |= 0x003f000f;
13938         } else {
13939                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13940                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13941                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
13942                         u32 read_water = 0x7;
13943
13944                         /* If the 5704 is behind the EPB bridge, we can
13945                          * do the less restrictive ONE_DMA workaround for
13946                          * better performance.
13947                          */
13948                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13949                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13950                                 tp->dma_rwctrl |= 0x8000;
13951                         else if (ccval == 0x6 || ccval == 0x7)
13952                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13953
13954                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13955                                 read_water = 4;
13956                         /* Set bit 23 to enable PCIX hw bug fix */
13957                         tp->dma_rwctrl |=
13958                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13959                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13960                                 (1 << 23);
13961                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13962                         /* 5780 always in PCIX mode */
13963                         tp->dma_rwctrl |= 0x00144000;
13964                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13965                         /* 5714 always in PCIX mode */
13966                         tp->dma_rwctrl |= 0x00148000;
13967                 } else {
13968                         tp->dma_rwctrl |= 0x001b000f;
13969                 }
13970         }
13971
13972         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13973             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13974                 tp->dma_rwctrl &= 0xfffffff0;
13975
13976         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13977             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13978                 /* Remove this if it causes problems for some boards. */
13979                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13980
13981                 /* On 5700/5701 chips, we need to set this bit.
13982                  * Otherwise the chip will issue cacheline transactions
13983                  * to streamable DMA memory with not all the byte
13984                  * enables turned on.  This is an error on several
13985                  * RISC PCI controllers, in particular sparc64.
13986                  *
13987                  * On 5703/5704 chips, this bit has been reassigned
13988                  * a different meaning.  In particular, it is used
13989                  * on those chips to enable a PCI-X workaround.
13990                  */
13991                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13992         }
13993
13994         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13995
13996 #if 0
13997         /* Unneeded, already done by tg3_get_invariants.  */
13998         tg3_switch_clocks(tp);
13999 #endif
14000
14001         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14002             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14003                 goto out;
14004
14005         /* It is best to perform DMA test with maximum write burst size
14006          * to expose the 5700/5701 write DMA bug.
14007          */
14008         saved_dma_rwctrl = tp->dma_rwctrl;
14009         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14010         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14011
14012         while (1) {
14013                 u32 *p = buf, i;
14014
14015                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14016                         p[i] = i;
14017
14018                 /* Send the buffer to the chip. */
14019                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14020                 if (ret) {
14021                         dev_err(&tp->pdev->dev,
14022                                 "%s: Buffer write failed. err = %d\n",
14023                                 __func__, ret);
14024                         break;
14025                 }
14026
14027 #if 0
14028                 /* validate data reached card RAM correctly. */
14029                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14030                         u32 val;
14031                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
14032                         if (le32_to_cpu(val) != p[i]) {
14033                                 dev_err(&tp->pdev->dev,
14034                                         "%s: Buffer corrupted on device! "
14035                                         "(%d != %d)\n", __func__, val, i);
14036                                 /* ret = -ENODEV here? */
14037                         }
14038                         p[i] = 0;
14039                 }
14040 #endif
14041                 /* Now read it back. */
14042                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14043                 if (ret) {
14044                         dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
14045                                 "err = %d\n", __func__, ret);
14046                         break;
14047                 }
14048
14049                 /* Verify it. */
14050                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14051                         if (p[i] == i)
14052                                 continue;
14053
14054                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14055                             DMA_RWCTRL_WRITE_BNDRY_16) {
14056                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14057                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14058                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14059                                 break;
14060                         } else {
14061                                 dev_err(&tp->pdev->dev,
14062                                         "%s: Buffer corrupted on read back! "
14063                                         "(%d != %d)\n", __func__, p[i], i);
14064                                 ret = -ENODEV;
14065                                 goto out;
14066                         }
14067                 }
14068
14069                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14070                         /* Success. */
14071                         ret = 0;
14072                         break;
14073                 }
14074         }
14075         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14076             DMA_RWCTRL_WRITE_BNDRY_16) {
14077                 static struct pci_device_id dma_wait_state_chipsets[] = {
14078                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14079                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14080                         { },
14081                 };
14082
14083                 /* DMA test passed without adjusting DMA boundary,
14084                  * now look for chipsets that are known to expose the
14085                  * DMA bug without failing the test.
14086                  */
14087                 if (pci_dev_present(dma_wait_state_chipsets)) {
14088                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14089                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14090                 } else {
14091                         /* Safe to use the calculated DMA boundary. */
14092                         tp->dma_rwctrl = saved_dma_rwctrl;
14093                 }
14094
14095                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14096         }
14097
14098 out:
14099         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14100 out_nofree:
14101         return ret;
14102 }
14103
14104 static void __devinit tg3_init_link_config(struct tg3 *tp)
14105 {
14106         tp->link_config.advertising =
14107                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14108                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14109                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14110                  ADVERTISED_Autoneg | ADVERTISED_MII);
14111         tp->link_config.speed = SPEED_INVALID;
14112         tp->link_config.duplex = DUPLEX_INVALID;
14113         tp->link_config.autoneg = AUTONEG_ENABLE;
14114         tp->link_config.active_speed = SPEED_INVALID;
14115         tp->link_config.active_duplex = DUPLEX_INVALID;
14116         tp->link_config.orig_speed = SPEED_INVALID;
14117         tp->link_config.orig_duplex = DUPLEX_INVALID;
14118         tp->link_config.orig_autoneg = AUTONEG_INVALID;
14119 }
14120
14121 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14122 {
14123         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
14124                 tp->bufmgr_config.mbuf_read_dma_low_water =
14125                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14126                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14127                         DEFAULT_MB_MACRX_LOW_WATER_57765;
14128                 tp->bufmgr_config.mbuf_high_water =
14129                         DEFAULT_MB_HIGH_WATER_57765;
14130
14131                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14132                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14133                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14134                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14135                 tp->bufmgr_config.mbuf_high_water_jumbo =
14136                         DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14137         } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14138                 tp->bufmgr_config.mbuf_read_dma_low_water =
14139                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14140                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14141                         DEFAULT_MB_MACRX_LOW_WATER_5705;
14142                 tp->bufmgr_config.mbuf_high_water =
14143                         DEFAULT_MB_HIGH_WATER_5705;
14144                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14145                         tp->bufmgr_config.mbuf_mac_rx_low_water =
14146                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
14147                         tp->bufmgr_config.mbuf_high_water =
14148                                 DEFAULT_MB_HIGH_WATER_5906;
14149                 }
14150
14151                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14152                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14153                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14154                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14155                 tp->bufmgr_config.mbuf_high_water_jumbo =
14156                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14157         } else {
14158                 tp->bufmgr_config.mbuf_read_dma_low_water =
14159                         DEFAULT_MB_RDMA_LOW_WATER;
14160                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14161                         DEFAULT_MB_MACRX_LOW_WATER;
14162                 tp->bufmgr_config.mbuf_high_water =
14163                         DEFAULT_MB_HIGH_WATER;
14164
14165                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14166                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14167                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14168                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14169                 tp->bufmgr_config.mbuf_high_water_jumbo =
14170                         DEFAULT_MB_HIGH_WATER_JUMBO;
14171         }
14172
14173         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14174         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14175 }
14176
14177 static char * __devinit tg3_phy_string(struct tg3 *tp)
14178 {
14179         switch (tp->phy_id & TG3_PHY_ID_MASK) {
14180         case TG3_PHY_ID_BCM5400:        return "5400";
14181         case TG3_PHY_ID_BCM5401:        return "5401";
14182         case TG3_PHY_ID_BCM5411:        return "5411";
14183         case TG3_PHY_ID_BCM5701:        return "5701";
14184         case TG3_PHY_ID_BCM5703:        return "5703";
14185         case TG3_PHY_ID_BCM5704:        return "5704";
14186         case TG3_PHY_ID_BCM5705:        return "5705";
14187         case TG3_PHY_ID_BCM5750:        return "5750";
14188         case TG3_PHY_ID_BCM5752:        return "5752";
14189         case TG3_PHY_ID_BCM5714:        return "5714";
14190         case TG3_PHY_ID_BCM5780:        return "5780";
14191         case TG3_PHY_ID_BCM5755:        return "5755";
14192         case TG3_PHY_ID_BCM5787:        return "5787";
14193         case TG3_PHY_ID_BCM5784:        return "5784";
14194         case TG3_PHY_ID_BCM5756:        return "5722/5756";
14195         case TG3_PHY_ID_BCM5906:        return "5906";
14196         case TG3_PHY_ID_BCM5761:        return "5761";
14197         case TG3_PHY_ID_BCM5718C:       return "5718C";
14198         case TG3_PHY_ID_BCM5718S:       return "5718S";
14199         case TG3_PHY_ID_BCM57765:       return "57765";
14200         case TG3_PHY_ID_BCM5719C:       return "5719C";
14201         case TG3_PHY_ID_BCM8002:        return "8002/serdes";
14202         case 0:                 return "serdes";
14203         default:                return "unknown";
14204         }
14205 }
14206
14207 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14208 {
14209         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14210                 strcpy(str, "PCI Express");
14211                 return str;
14212         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14213                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14214
14215                 strcpy(str, "PCIX:");
14216
14217                 if ((clock_ctrl == 7) ||
14218                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14219                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14220                         strcat(str, "133MHz");
14221                 else if (clock_ctrl == 0)
14222                         strcat(str, "33MHz");
14223                 else if (clock_ctrl == 2)
14224                         strcat(str, "50MHz");
14225                 else if (clock_ctrl == 4)
14226                         strcat(str, "66MHz");
14227                 else if (clock_ctrl == 6)
14228                         strcat(str, "100MHz");
14229         } else {
14230                 strcpy(str, "PCI:");
14231                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14232                         strcat(str, "66MHz");
14233                 else
14234                         strcat(str, "33MHz");
14235         }
14236         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14237                 strcat(str, ":32-bit");
14238         else
14239                 strcat(str, ":64-bit");
14240         return str;
14241 }
14242
14243 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14244 {
14245         struct pci_dev *peer;
14246         unsigned int func, devnr = tp->pdev->devfn & ~7;
14247
14248         for (func = 0; func < 8; func++) {
14249                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14250                 if (peer && peer != tp->pdev)
14251                         break;
14252                 pci_dev_put(peer);
14253         }
14254         /* 5704 can be configured in single-port mode, set peer to
14255          * tp->pdev in that case.
14256          */
14257         if (!peer) {
14258                 peer = tp->pdev;
14259                 return peer;
14260         }
14261
14262         /*
14263          * We don't need to keep the refcount elevated; there's no way
14264          * to remove one half of this device without removing the other
14265          */
14266         pci_dev_put(peer);
14267
14268         return peer;
14269 }
14270
14271 static void __devinit tg3_init_coal(struct tg3 *tp)
14272 {
14273         struct ethtool_coalesce *ec = &tp->coal;
14274
14275         memset(ec, 0, sizeof(*ec));
14276         ec->cmd = ETHTOOL_GCOALESCE;
14277         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14278         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14279         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14280         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14281         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14282         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14283         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14284         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14285         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14286
14287         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14288                                  HOSTCC_MODE_CLRTICK_TXBD)) {
14289                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14290                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14291                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14292                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14293         }
14294
14295         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14296                 ec->rx_coalesce_usecs_irq = 0;
14297                 ec->tx_coalesce_usecs_irq = 0;
14298                 ec->stats_block_coalesce_usecs = 0;
14299         }
14300 }
14301
14302 static const struct net_device_ops tg3_netdev_ops = {
14303         .ndo_open               = tg3_open,
14304         .ndo_stop               = tg3_close,
14305         .ndo_start_xmit         = tg3_start_xmit,
14306         .ndo_get_stats64        = tg3_get_stats64,
14307         .ndo_validate_addr      = eth_validate_addr,
14308         .ndo_set_multicast_list = tg3_set_rx_mode,
14309         .ndo_set_mac_address    = tg3_set_mac_addr,
14310         .ndo_do_ioctl           = tg3_ioctl,
14311         .ndo_tx_timeout         = tg3_tx_timeout,
14312         .ndo_change_mtu         = tg3_change_mtu,
14313 #if TG3_VLAN_TAG_USED
14314         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14315 #endif
14316 #ifdef CONFIG_NET_POLL_CONTROLLER
14317         .ndo_poll_controller    = tg3_poll_controller,
14318 #endif
14319 };
14320
14321 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14322         .ndo_open               = tg3_open,
14323         .ndo_stop               = tg3_close,
14324         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
14325         .ndo_get_stats64        = tg3_get_stats64,
14326         .ndo_validate_addr      = eth_validate_addr,
14327         .ndo_set_multicast_list = tg3_set_rx_mode,
14328         .ndo_set_mac_address    = tg3_set_mac_addr,
14329         .ndo_do_ioctl           = tg3_ioctl,
14330         .ndo_tx_timeout         = tg3_tx_timeout,
14331         .ndo_change_mtu         = tg3_change_mtu,
14332 #if TG3_VLAN_TAG_USED
14333         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14334 #endif
14335 #ifdef CONFIG_NET_POLL_CONTROLLER
14336         .ndo_poll_controller    = tg3_poll_controller,
14337 #endif
14338 };
14339
14340 static int __devinit tg3_init_one(struct pci_dev *pdev,
14341                                   const struct pci_device_id *ent)
14342 {
14343         struct net_device *dev;
14344         struct tg3 *tp;
14345         int i, err, pm_cap;
14346         u32 sndmbx, rcvmbx, intmbx;
14347         char str[40];
14348         u64 dma_mask, persist_dma_mask;
14349
14350         printk_once(KERN_INFO "%s\n", version);
14351
14352         err = pci_enable_device(pdev);
14353         if (err) {
14354                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
14355                 return err;
14356         }
14357
14358         err = pci_request_regions(pdev, DRV_MODULE_NAME);
14359         if (err) {
14360                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
14361                 goto err_out_disable_pdev;
14362         }
14363
14364         pci_set_master(pdev);
14365
14366         /* Find power-management capability. */
14367         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14368         if (pm_cap == 0) {
14369                 dev_err(&pdev->dev,
14370                         "Cannot find Power Management capability, aborting\n");
14371                 err = -EIO;
14372                 goto err_out_free_res;
14373         }
14374
14375         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14376         if (!dev) {
14377                 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
14378                 err = -ENOMEM;
14379                 goto err_out_free_res;
14380         }
14381
14382         SET_NETDEV_DEV(dev, &pdev->dev);
14383
14384 #if TG3_VLAN_TAG_USED
14385         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14386 #endif
14387
14388         tp = netdev_priv(dev);
14389         tp->pdev = pdev;
14390         tp->dev = dev;
14391         tp->pm_cap = pm_cap;
14392         tp->rx_mode = TG3_DEF_RX_MODE;
14393         tp->tx_mode = TG3_DEF_TX_MODE;
14394
14395         if (tg3_debug > 0)
14396                 tp->msg_enable = tg3_debug;
14397         else
14398                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14399
14400         /* The word/byte swap controls here control register access byte
14401          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
14402          * setting below.
14403          */
14404         tp->misc_host_ctrl =
14405                 MISC_HOST_CTRL_MASK_PCI_INT |
14406                 MISC_HOST_CTRL_WORD_SWAP |
14407                 MISC_HOST_CTRL_INDIR_ACCESS |
14408                 MISC_HOST_CTRL_PCISTATE_RW;
14409
14410         /* The NONFRM (non-frame) byte/word swap controls take effect
14411          * on descriptor entries, anything which isn't packet data.
14412          *
14413          * The StrongARM chips on the board (one for tx, one for rx)
14414          * are running in big-endian mode.
14415          */
14416         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14417                         GRC_MODE_WSWAP_NONFRM_DATA);
14418 #ifdef __BIG_ENDIAN
14419         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14420 #endif
14421         spin_lock_init(&tp->lock);
14422         spin_lock_init(&tp->indirect_lock);
14423         INIT_WORK(&tp->reset_task, tg3_reset_task);
14424
14425         tp->regs = pci_ioremap_bar(pdev, BAR_0);
14426         if (!tp->regs) {
14427                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
14428                 err = -ENOMEM;
14429                 goto err_out_free_dev;
14430         }
14431
14432         tg3_init_link_config(tp);
14433
14434         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14435         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14436
14437         dev->ethtool_ops = &tg3_ethtool_ops;
14438         dev->watchdog_timeo = TG3_TX_TIMEOUT;
14439         dev->irq = pdev->irq;
14440
14441         err = tg3_get_invariants(tp);
14442         if (err) {
14443                 dev_err(&pdev->dev,
14444                         "Problem fetching invariants of chip, aborting\n");
14445                 goto err_out_iounmap;
14446         }
14447
14448         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14449             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
14450             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
14451                 dev->netdev_ops = &tg3_netdev_ops;
14452         else
14453                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14454
14455
14456         /* The EPB bridge inside 5714, 5715, and 5780 and any
14457          * device behind the EPB cannot support DMA addresses > 40-bit.
14458          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14459          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14460          * do DMA address check in tg3_start_xmit().
14461          */
14462         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14463                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14464         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14465                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14466 #ifdef CONFIG_HIGHMEM
14467                 dma_mask = DMA_BIT_MASK(64);
14468 #endif
14469         } else
14470                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14471
14472         /* Configure DMA attributes. */
14473         if (dma_mask > DMA_BIT_MASK(32)) {
14474                 err = pci_set_dma_mask(pdev, dma_mask);
14475                 if (!err) {
14476                         dev->features |= NETIF_F_HIGHDMA;
14477                         err = pci_set_consistent_dma_mask(pdev,
14478                                                           persist_dma_mask);
14479                         if (err < 0) {
14480                                 dev_err(&pdev->dev, "Unable to obtain 64 bit "
14481                                         "DMA for consistent allocations\n");
14482                                 goto err_out_iounmap;
14483                         }
14484                 }
14485         }
14486         if (err || dma_mask == DMA_BIT_MASK(32)) {
14487                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14488                 if (err) {
14489                         dev_err(&pdev->dev,
14490                                 "No usable DMA configuration, aborting\n");
14491                         goto err_out_iounmap;
14492                 }
14493         }
14494
14495         tg3_init_bufmgr_config(tp);
14496
14497         /* Selectively allow TSO based on operating conditions */
14498         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14499             (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14500                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14501         else {
14502                 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14503                 tp->fw_needed = NULL;
14504         }
14505
14506         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14507                 tp->fw_needed = FIRMWARE_TG3;
14508
14509         /* TSO is on by default on chips that support hardware TSO.
14510          * Firmware TSO on older chips gives lower performance, so it
14511          * is off by default, but can be enabled using ethtool.
14512          */
14513         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14514             (dev->features & NETIF_F_IP_CSUM)) {
14515                 dev->features |= NETIF_F_TSO;
14516                 vlan_features_add(dev, NETIF_F_TSO);
14517         }
14518         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14519             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14520                 if (dev->features & NETIF_F_IPV6_CSUM) {
14521                         dev->features |= NETIF_F_TSO6;
14522                         vlan_features_add(dev, NETIF_F_TSO6);
14523                 }
14524                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14525                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14526                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14527                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14528                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14529                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
14530                         dev->features |= NETIF_F_TSO_ECN;
14531                         vlan_features_add(dev, NETIF_F_TSO_ECN);
14532                 }
14533         }
14534
14535         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14536             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14537             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14538                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14539                 tp->rx_pending = 63;
14540         }
14541
14542         err = tg3_get_device_address(tp);
14543         if (err) {
14544                 dev_err(&pdev->dev,
14545                         "Could not obtain valid ethernet address, aborting\n");
14546                 goto err_out_iounmap;
14547         }
14548
14549         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14550                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14551                 if (!tp->aperegs) {
14552                         dev_err(&pdev->dev,
14553                                 "Cannot map APE registers, aborting\n");
14554                         err = -ENOMEM;
14555                         goto err_out_iounmap;
14556                 }
14557
14558                 tg3_ape_lock_init(tp);
14559
14560                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14561                         tg3_read_dash_ver(tp);
14562         }
14563
14564         /*
14565          * Reset chip in case UNDI or EFI driver did not shutdown
14566          * DMA self test will enable WDMAC and we'll see (spurious)
14567          * pending DMA on the PCI bus at that point.
14568          */
14569         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14570             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14571                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14572                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14573         }
14574
14575         err = tg3_test_dma(tp);
14576         if (err) {
14577                 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
14578                 goto err_out_apeunmap;
14579         }
14580
14581         /* flow control autonegotiation is default behavior */
14582         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14583         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14584
14585         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14586         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14587         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14588         for (i = 0; i < tp->irq_max; i++) {
14589                 struct tg3_napi *tnapi = &tp->napi[i];
14590
14591                 tnapi->tp = tp;
14592                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14593
14594                 tnapi->int_mbox = intmbx;
14595                 if (i < 4)
14596                         intmbx += 0x8;
14597                 else
14598                         intmbx += 0x4;
14599
14600                 tnapi->consmbox = rcvmbx;
14601                 tnapi->prodmbox = sndmbx;
14602
14603                 if (i) {
14604                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14605                         netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14606                 } else {
14607                         tnapi->coal_now = HOSTCC_MODE_NOW;
14608                         netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14609                 }
14610
14611                 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14612                         break;
14613
14614                 /*
14615                  * If we support MSIX, we'll be using RSS.  If we're using
14616                  * RSS, the first vector only handles link interrupts and the
14617                  * remaining vectors handle rx and tx interrupts.  Reuse the
14618                  * mailbox values for the next iteration.  The values we setup
14619                  * above are still useful for the single vectored mode.
14620                  */
14621                 if (!i)
14622                         continue;
14623
14624                 rcvmbx += 0x8;
14625
14626                 if (sndmbx & 0x4)
14627                         sndmbx -= 0x4;
14628                 else
14629                         sndmbx += 0xc;
14630         }
14631
14632         tg3_init_coal(tp);
14633
14634         pci_set_drvdata(pdev, dev);
14635
14636         err = register_netdev(dev);
14637         if (err) {
14638                 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
14639                 goto err_out_apeunmap;
14640         }
14641
14642         netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14643                     tp->board_part_number,
14644                     tp->pci_chip_rev_id,
14645                     tg3_bus_string(tp, str),
14646                     dev->dev_addr);
14647
14648         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
14649                 struct phy_device *phydev;
14650                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14651                 netdev_info(dev,
14652                             "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14653                             phydev->drv->name, dev_name(&phydev->dev));
14654         } else {
14655                 char *ethtype;
14656
14657                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
14658                         ethtype = "10/100Base-TX";
14659                 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
14660                         ethtype = "1000Base-SX";
14661                 else
14662                         ethtype = "10/100/1000Base-T";
14663
14664                 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
14665                             "(WireSpeed[%d])\n", tg3_phy_string(tp), ethtype,
14666                           (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0);
14667         }
14668
14669         netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14670                     (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14671                     (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14672                     (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
14673                     (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14674                     (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14675         netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14676                     tp->dma_rwctrl,
14677                     pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
14678                     ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
14679
14680         return 0;
14681
14682 err_out_apeunmap:
14683         if (tp->aperegs) {
14684                 iounmap(tp->aperegs);
14685                 tp->aperegs = NULL;
14686         }
14687
14688 err_out_iounmap:
14689         if (tp->regs) {
14690                 iounmap(tp->regs);
14691                 tp->regs = NULL;
14692         }
14693
14694 err_out_free_dev:
14695         free_netdev(dev);
14696
14697 err_out_free_res:
14698         pci_release_regions(pdev);
14699
14700 err_out_disable_pdev:
14701         pci_disable_device(pdev);
14702         pci_set_drvdata(pdev, NULL);
14703         return err;
14704 }
14705
14706 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14707 {
14708         struct net_device *dev = pci_get_drvdata(pdev);
14709
14710         if (dev) {
14711                 struct tg3 *tp = netdev_priv(dev);
14712
14713                 if (tp->fw)
14714                         release_firmware(tp->fw);
14715
14716                 flush_scheduled_work();
14717
14718                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14719                         tg3_phy_fini(tp);
14720                         tg3_mdio_fini(tp);
14721                 }
14722
14723                 unregister_netdev(dev);
14724                 if (tp->aperegs) {
14725                         iounmap(tp->aperegs);
14726                         tp->aperegs = NULL;
14727                 }
14728                 if (tp->regs) {
14729                         iounmap(tp->regs);
14730                         tp->regs = NULL;
14731                 }
14732                 free_netdev(dev);
14733                 pci_release_regions(pdev);
14734                 pci_disable_device(pdev);
14735                 pci_set_drvdata(pdev, NULL);
14736         }
14737 }
14738
14739 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14740 {
14741         struct net_device *dev = pci_get_drvdata(pdev);
14742         struct tg3 *tp = netdev_priv(dev);
14743         pci_power_t target_state;
14744         int err;
14745
14746         /* PCI register 4 needs to be saved whether netif_running() or not.
14747          * MSI address and data need to be saved if using MSI and
14748          * netif_running().
14749          */
14750         pci_save_state(pdev);
14751
14752         if (!netif_running(dev))
14753                 return 0;
14754
14755         flush_scheduled_work();
14756         tg3_phy_stop(tp);
14757         tg3_netif_stop(tp);
14758
14759         del_timer_sync(&tp->timer);
14760
14761         tg3_full_lock(tp, 1);
14762         tg3_disable_ints(tp);
14763         tg3_full_unlock(tp);
14764
14765         netif_device_detach(dev);
14766
14767         tg3_full_lock(tp, 0);
14768         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14769         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14770         tg3_full_unlock(tp);
14771
14772         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14773
14774         err = tg3_set_power_state(tp, target_state);
14775         if (err) {
14776                 int err2;
14777
14778                 tg3_full_lock(tp, 0);
14779
14780                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14781                 err2 = tg3_restart_hw(tp, 1);
14782                 if (err2)
14783                         goto out;
14784
14785                 tp->timer.expires = jiffies + tp->timer_offset;
14786                 add_timer(&tp->timer);
14787
14788                 netif_device_attach(dev);
14789                 tg3_netif_start(tp);
14790
14791 out:
14792                 tg3_full_unlock(tp);
14793
14794                 if (!err2)
14795                         tg3_phy_start(tp);
14796         }
14797
14798         return err;
14799 }
14800
14801 static int tg3_resume(struct pci_dev *pdev)
14802 {
14803         struct net_device *dev = pci_get_drvdata(pdev);
14804         struct tg3 *tp = netdev_priv(dev);
14805         int err;
14806
14807         pci_restore_state(tp->pdev);
14808
14809         if (!netif_running(dev))
14810                 return 0;
14811
14812         err = tg3_set_power_state(tp, PCI_D0);
14813         if (err)
14814                 return err;
14815
14816         netif_device_attach(dev);
14817
14818         tg3_full_lock(tp, 0);
14819
14820         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14821         err = tg3_restart_hw(tp, 1);
14822         if (err)
14823                 goto out;
14824
14825         tp->timer.expires = jiffies + tp->timer_offset;
14826         add_timer(&tp->timer);
14827
14828         tg3_netif_start(tp);
14829
14830 out:
14831         tg3_full_unlock(tp);
14832
14833         if (!err)
14834                 tg3_phy_start(tp);
14835
14836         return err;
14837 }
14838
14839 static struct pci_driver tg3_driver = {
14840         .name           = DRV_MODULE_NAME,
14841         .id_table       = tg3_pci_tbl,
14842         .probe          = tg3_init_one,
14843         .remove         = __devexit_p(tg3_remove_one),
14844         .suspend        = tg3_suspend,
14845         .resume         = tg3_resume
14846 };
14847
14848 static int __init tg3_init(void)
14849 {
14850         return pci_register_driver(&tg3_driver);
14851 }
14852
14853 static void __exit tg3_cleanup(void)
14854 {
14855         pci_unregister_driver(&tg3_driver);
14856 }
14857
14858 module_init(tg3_init);
14859 module_exit(tg3_cleanup);