drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2010 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/stringify.h>
  22 #include <linux/kernel.h>
  23 #include <linux/types.h>
  24 #include <linux/compiler.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/in.h>
  28 #include <linux/init.h>
  29 #include <linux/ioport.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/ethtool.h>
  35 #include <linux/mii.h>
  36 #include <linux/phy.h>
  37 #include <linux/brcmphy.h>
  38 #include <linux/if_vlan.h>
  39 #include <linux/ip.h>
  40 #include <linux/tcp.h>
  41 #include <linux/workqueue.h>
  42 #include <linux/prefetch.h>
  43 #include <linux/dma-mapping.h>
  44 #include <linux/firmware.h>
  45
  46 #include <net/checksum.h>
  47 #include <net/ip.h>
  48
  49 #include <asm/system.h>
  50 #include <asm/io.h>
  51 #include <asm/byteorder.h>
  52 #include <asm/uaccess.h>
  53
  54 #ifdef CONFIG_SPARC
  55 #include <asm/idprom.h>
  56 #include <asm/prom.h>
  57 #endif
  58
  59 #define BAR_0   0
  60 #define BAR_2   2
  61
  62 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  63 #define TG3_VLAN_TAG_USED 1
  64 #else
  65 #define TG3_VLAN_TAG_USED 0
  66 #endif
  67
  68 #include "tg3.h"
  69
  70 #define DRV_MODULE_NAME         "tg3"
  71 #define TG3_MAJ_NUM                     3
  72 #define TG3_MIN_NUM                     113
  73 #define DRV_MODULE_VERSION      \
  74         __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
  75 #define DRV_MODULE_RELDATE      "August 2, 2010"
  76
  77 #define TG3_DEF_MAC_MODE        0
  78 #define TG3_DEF_RX_MODE         0
  79 #define TG3_DEF_TX_MODE         0
  80 #define TG3_DEF_MSG_ENABLE        \
  81         (NETIF_MSG_DRV          | \
  82          NETIF_MSG_PROBE        | \
  83          NETIF_MSG_LINK         | \
  84          NETIF_MSG_TIMER        | \
  85          NETIF_MSG_IFDOWN       | \
  86          NETIF_MSG_IFUP         | \
  87          NETIF_MSG_RX_ERR       | \
  88          NETIF_MSG_TX_ERR)
  89
  90 /* length of time before we decide the hardware is borked,
  91  * and dev->tx_timeout() should be called to fix the problem
  92  */
  93 #define TG3_TX_TIMEOUT                  (5 * HZ)
  94
  95 /* hardware minimum and maximum for a single frame's data payload */
  96 #define TG3_MIN_MTU                     60
  97 #define TG3_MAX_MTU(tp) \
  98         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  99
 100 /* These numbers seem to be hard coded in the NIC firmware somehow.
 101  * You can't change the ring sizes, but you can change where you place
 102  * them in the NIC onboard memory.
 103  */
 104 #define TG3_RX_RING_SIZE                512
 105 #define TG3_DEF_RX_RING_PENDING         200
 106 #define TG3_RX_JUMBO_RING_SIZE          256
 107 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 108 #define TG3_RSS_INDIR_TBL_SIZE          128
 109
 110 /* Do not place this n-ring entries value into the tp struct itself,
 111  * we really want to expose these constants to GCC so that modulo et
 112  * al.  operations are done with shifts and masks instead of with
 113  * hw multiply/modulo instructions.  Another solution would be to
 114  * replace things like '% foo' with '& (foo - 1)'.
 115  */
 116 #define TG3_RX_RCB_RING_SIZE(tp)        \
 117         (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
 118           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
 119
 120 #define TG3_TX_RING_SIZE                512
 121 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 122
 123 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 124                                  TG3_RX_RING_SIZE)
 125 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
 126                                  TG3_RX_JUMBO_RING_SIZE)
 127 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 128                                  TG3_RX_RCB_RING_SIZE(tp))
 129 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 130                                  TG3_TX_RING_SIZE)
 131 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 132
 133 #define TG3_RX_DMA_ALIGN                16
 134 #define TG3_RX_HEADROOM                 ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
 135
 136 #define TG3_DMA_BYTE_ENAB               64
 137
 138 #define TG3_RX_STD_DMA_SZ               1536
 139 #define TG3_RX_JMB_DMA_SZ               9046
 140
 141 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 142
 143 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 144 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 145
 146 #define TG3_RX_STD_BUFF_RING_SIZE \
 147         (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
 148
 149 #define TG3_RX_JMB_BUFF_RING_SIZE \
 150         (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
 151
 152 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
 153  * that are at least dword aligned when used in PCIX mode.  The driver
 154  * works around this bug by double copying the packet.  This workaround
 155  * is built into the normal double copy length check for efficiency.
 156  *
 157  * However, the double copy is only necessary on those architectures
 158  * where unaligned memory accesses are inefficient.  For those architectures
 159  * where unaligned memory accesses incur little penalty, we can reintegrate
 160  * the 5701 in the normal rx path.  Doing so saves a device structure
 161  * dereference by hardcoding the double copy threshold in place.
 162  */
 163 #define TG3_RX_COPY_THRESHOLD           256
 164 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
 165         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
 166 #else
 167         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
 168 #endif
 169
 170 /* minimum number of free TX descriptors required to wake up TX process */
 171 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 172
 173 #define TG3_RAW_IP_ALIGN 2
 174
 175 /* number of ETHTOOL_GSTATS u64's */
 176 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 177
 178 #define TG3_NUM_TEST            6
 179
 180 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
 181
 182 #define FIRMWARE_TG3            "tigon/tg3.bin"
 183 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 184 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 185
 186 static char version[] __devinitdata =
 187         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
 188
 189 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 190 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 191 MODULE_LICENSE("GPL");
 192 MODULE_VERSION(DRV_MODULE_VERSION);
 193 MODULE_FIRMWARE(FIRMWARE_TG3);
 194 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 195 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 196
 197 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 198 module_param(tg3_debug, int, 0);
 199 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 200
 201 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 255         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 256         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 257         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 258         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 259         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 260         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 261         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 262         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 263         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 264         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 265         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
 266         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
 267         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
 268         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
 269         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
 270         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
 271         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
 272         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
 273         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
 274         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
 275         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 276         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 277         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 278         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 279         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 280         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 281         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 282         {}
 283 };
 284
 285 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 286
 287 static const struct {
 288         const char string[ETH_GSTRING_LEN];
 289 } ethtool_stats_keys[TG3_NUM_STATS] = {
 290         { "rx_octets" },
 291         { "rx_fragments" },
 292         { "rx_ucast_packets" },
 293         { "rx_mcast_packets" },
 294         { "rx_bcast_packets" },
 295         { "rx_fcs_errors" },
 296         { "rx_align_errors" },
 297         { "rx_xon_pause_rcvd" },
 298         { "rx_xoff_pause_rcvd" },
 299         { "rx_mac_ctrl_rcvd" },
 300         { "rx_xoff_entered" },
 301         { "rx_frame_too_long_errors" },
 302         { "rx_jabbers" },
 303         { "rx_undersize_packets" },
 304         { "rx_in_length_errors" },
 305         { "rx_out_length_errors" },
 306         { "rx_64_or_less_octet_packets" },
 307         { "rx_65_to_127_octet_packets" },
 308         { "rx_128_to_255_octet_packets" },
 309         { "rx_256_to_511_octet_packets" },
 310         { "rx_512_to_1023_octet_packets" },
 311         { "rx_1024_to_1522_octet_packets" },
 312         { "rx_1523_to_2047_octet_packets" },
 313         { "rx_2048_to_4095_octet_packets" },
 314         { "rx_4096_to_8191_octet_packets" },
 315         { "rx_8192_to_9022_octet_packets" },
 316
 317         { "tx_octets" },
 318         { "tx_collisions" },
 319
 320         { "tx_xon_sent" },
 321         { "tx_xoff_sent" },
 322         { "tx_flow_control" },
 323         { "tx_mac_errors" },
 324         { "tx_single_collisions" },
 325         { "tx_mult_collisions" },
 326         { "tx_deferred" },
 327         { "tx_excessive_collisions" },
 328         { "tx_late_collisions" },
 329         { "tx_collide_2times" },
 330         { "tx_collide_3times" },
 331         { "tx_collide_4times" },
 332         { "tx_collide_5times" },
 333         { "tx_collide_6times" },
 334         { "tx_collide_7times" },
 335         { "tx_collide_8times" },
 336         { "tx_collide_9times" },
 337         { "tx_collide_10times" },
 338         { "tx_collide_11times" },
 339         { "tx_collide_12times" },
 340         { "tx_collide_13times" },
 341         { "tx_collide_14times" },
 342         { "tx_collide_15times" },
 343         { "tx_ucast_packets" },
 344         { "tx_mcast_packets" },
 345         { "tx_bcast_packets" },
 346         { "tx_carrier_sense_errors" },
 347         { "tx_discards" },
 348         { "tx_errors" },
 349
 350         { "dma_writeq_full" },
 351         { "dma_write_prioq_full" },
 352         { "rxbds_empty" },
 353         { "rx_discards" },
 354         { "rx_errors" },
 355         { "rx_threshold_hit" },
 356
 357         { "dma_readq_full" },
 358         { "dma_read_prioq_full" },
 359         { "tx_comp_queue_full" },
 360
 361         { "ring_set_send_prod_index" },
 362         { "ring_status_update" },
 363         { "nic_irqs" },
 364         { "nic_avoided_irqs" },
 365         { "nic_tx_threshold_hit" }
 366 };
 367
 368 static const struct {
 369         const char string[ETH_GSTRING_LEN];
 370 } ethtool_test_keys[TG3_NUM_TEST] = {
 371         { "nvram test     (online) " },
 372         { "link test      (online) " },
 373         { "register test  (offline)" },
 374         { "memory test    (offline)" },
 375         { "loopback test  (offline)" },
 376         { "interrupt test (offline)" },
 377 };
 378
 379 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 380 {
 381         writel(val, tp->regs + off);
 382 }
 383
 384 static u32 tg3_read32(struct tg3 *tp, u32 off)
 385 {
 386         return readl(tp->regs + off);
 387 }
 388
 389 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 390 {
 391         writel(val, tp->aperegs + off);
 392 }
 393
 394 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 395 {
 396         return readl(tp->aperegs + off);
 397 }
 398
 399 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 400 {
 401         unsigned long flags;
 402
 403         spin_lock_irqsave(&tp->indirect_lock, flags);
 404         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 405         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 406         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 407 }
 408
 409 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 410 {
 411         writel(val, tp->regs + off);
 412         readl(tp->regs + off);
 413 }
 414
 415 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 416 {
 417         unsigned long flags;
 418         u32 val;
 419
 420         spin_lock_irqsave(&tp->indirect_lock, flags);
 421         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 422         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 423         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 424         return val;
 425 }
 426
 427 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 428 {
 429         unsigned long flags;
 430
 431         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 432                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 433                                        TG3_64BIT_REG_LOW, val);
 434                 return;
 435         }
 436         if (off == TG3_RX_STD_PROD_IDX_REG) {
 437                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 438                                        TG3_64BIT_REG_LOW, val);
 439                 return;
 440         }
 441
 442         spin_lock_irqsave(&tp->indirect_lock, flags);
 443         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 444         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 445         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 446
 447         /* In indirect mode when disabling interrupts, we also need
 448          * to clear the interrupt bit in the GRC local ctrl register.
 449          */
 450         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 451             (val == 0x1)) {
 452                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 453                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 454         }
 455 }
 456
 457 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 458 {
 459         unsigned long flags;
 460         u32 val;
 461
 462         spin_lock_irqsave(&tp->indirect_lock, flags);
 463         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 464         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 465         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 466         return val;
 467 }
 468
 469 /* usec_wait specifies the wait time in usec when writing to certain registers
 470  * where it is unsafe to read back the register without some delay.
 471  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 472  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 473  */
 474 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 475 {
 476         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 477             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 478                 /* Non-posted methods */
 479                 tp->write32(tp, off, val);
 480         else {
 481                 /* Posted method */
 482                 tg3_write32(tp, off, val);
 483                 if (usec_wait)
 484                         udelay(usec_wait);
 485                 tp->read32(tp, off);
 486         }
 487         /* Wait again after the read for the posted method to guarantee that
 488          * the wait time is met.
 489          */
 490         if (usec_wait)
 491                 udelay(usec_wait);
 492 }
 493
 494 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 495 {
 496         tp->write32_mbox(tp, off, val);
 497         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 498             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 499                 tp->read32_mbox(tp, off);
 500 }
 501
 502 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 503 {
 504         void __iomem *mbox = tp->regs + off;
 505         writel(val, mbox);
 506         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 507                 writel(val, mbox);
 508         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 509                 readl(mbox);
 510 }
 511
 512 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 513 {
 514         return readl(tp->regs + off + GRCMBOX_BASE);
 515 }
 516
 517 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 518 {
 519         writel(val, tp->regs + off + GRCMBOX_BASE);
 520 }
 521
 522 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
 523 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 524 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
 525 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
 526 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
 527
 528 #define tw32(reg, val)                  tp->write32(tp, reg, val)
 529 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
 530 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
 531 #define tr32(reg)                       tp->read32(tp, reg)
 532
 533 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 534 {
 535         unsigned long flags;
 536
 537         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 538             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 539                 return;
 540
 541         spin_lock_irqsave(&tp->indirect_lock, flags);
 542         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 543                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 544                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 545
 546                 /* Always leave this as zero. */
 547                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 548         } else {
 549                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 550                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 551
 552                 /* Always leave this as zero. */
 553                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 554         }
 555         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 556 }
 557
 558 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 559 {
 560         unsigned long flags;
 561
 562         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 563             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 564                 *val = 0;
 565                 return;
 566         }
 567
 568         spin_lock_irqsave(&tp->indirect_lock, flags);
 569         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 570                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 571                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 572
 573                 /* Always leave this as zero. */
 574                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 575         } else {
 576                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 577                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 578
 579                 /* Always leave this as zero. */
 580                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 581         }
 582         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 583 }
 584
 585 static void tg3_ape_lock_init(struct tg3 *tp)
 586 {
 587         int i;
 588         u32 regbase;
 589
 590         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 591                 regbase = TG3_APE_LOCK_GRANT;
 592         else
 593                 regbase = TG3_APE_PER_LOCK_GRANT;
 594
 595         /* Make sure the driver hasn't any stale locks. */
 596         for (i = 0; i < 8; i++)
 597                 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
 598 }
 599
 600 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 601 {
 602         int i, off;
 603         int ret = 0;
 604         u32 status, req, gnt;
 605
 606         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 607                 return 0;
 608
 609         switch (locknum) {
 610         case TG3_APE_LOCK_GRC:
 611         case TG3_APE_LOCK_MEM:
 612                 break;
 613         default:
 614                 return -EINVAL;
 615         }
 616
 617         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
 618                 req = TG3_APE_LOCK_REQ;
 619                 gnt = TG3_APE_LOCK_GRANT;
 620         } else {
 621                 req = TG3_APE_PER_LOCK_REQ;
 622                 gnt = TG3_APE_PER_LOCK_GRANT;
 623         }
 624
 625         off = 4 * locknum;
 626
 627         tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
 628
 629         /* Wait for up to 1 millisecond to acquire lock. */
 630         for (i = 0; i < 100; i++) {
 631                 status = tg3_ape_read32(tp, gnt + off);
 632                 if (status == APE_LOCK_GRANT_DRIVER)
 633                         break;
 634                 udelay(10);
 635         }
 636
 637         if (status != APE_LOCK_GRANT_DRIVER) {
 638                 /* Revoke the lock request. */
 639                 tg3_ape_write32(tp, gnt + off,
 640                                 APE_LOCK_GRANT_DRIVER);
 641
 642                 ret = -EBUSY;
 643         }
 644
 645         return ret;
 646 }
 647
 648 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 649 {
 650         u32 gnt;
 651
 652         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 653                 return;
 654
 655         switch (locknum) {
 656         case TG3_APE_LOCK_GRC:
 657         case TG3_APE_LOCK_MEM:
 658                 break;
 659         default:
 660                 return;
 661         }
 662
 663         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 664                 gnt = TG3_APE_LOCK_GRANT;
 665         else
 666                 gnt = TG3_APE_PER_LOCK_GRANT;
 667
 668         tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
 669 }
 670
 671 static void tg3_disable_ints(struct tg3 *tp)
 672 {
 673         int i;
 674
 675         tw32(TG3PCI_MISC_HOST_CTRL,
 676              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 677         for (i = 0; i < tp->irq_max; i++)
 678                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 679 }
 680
 681 static void tg3_enable_ints(struct tg3 *tp)
 682 {
 683         int i;
 684
 685         tp->irq_sync = 0;
 686         wmb();
 687
 688         tw32(TG3PCI_MISC_HOST_CTRL,
 689              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 690
 691         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
 692         for (i = 0; i < tp->irq_cnt; i++) {
 693                 struct tg3_napi *tnapi = &tp->napi[i];
 694
 695                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 696                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 697                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 698
 699                 tp->coal_now |= tnapi->coal_now;
 700         }
 701
 702         /* Force an initial interrupt */
 703         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 704             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 705                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 706         else
 707                 tw32(HOSTCC_MODE, tp->coal_now);
 708
 709         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
 710 }
 711
 712 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 713 {
 714         struct tg3 *tp = tnapi->tp;
 715         struct tg3_hw_status *sblk = tnapi->hw_status;
 716         unsigned int work_exists = 0;
 717
 718         /* check for phy events */
 719         if (!(tp->tg3_flags &
 720               (TG3_FLAG_USE_LINKCHG_REG |
 721                TG3_FLAG_POLL_SERDES))) {
 722                 if (sblk->status & SD_STATUS_LINK_CHG)
 723                         work_exists = 1;
 724         }
 725         /* check for RX/TX work to do */
 726         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 727             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
 728                 work_exists = 1;
 729
 730         return work_exists;
 731 }
 732
 733 /* tg3_int_reenable
 734  *  similar to tg3_enable_ints, but it accurately determines whether there
 735  *  is new work pending and can return without flushing the PIO write
 736  *  which reenables interrupts
 737  */
 738 static void tg3_int_reenable(struct tg3_napi *tnapi)
 739 {
 740         struct tg3 *tp = tnapi->tp;
 741
 742         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 743         mmiowb();
 744
 745         /* When doing tagged status, this work check is unnecessary.
 746          * The last_tag we write above tells the chip which piece of
 747          * work we've completed.
 748          */
 749         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 750             tg3_has_work(tnapi))
 751                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 752                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 753 }
 754
 755 static void tg3_napi_disable(struct tg3 *tp)
 756 {
 757         int i;
 758
 759         for (i = tp->irq_cnt - 1; i >= 0; i--)
 760                 napi_disable(&tp->napi[i].napi);
 761 }
 762
 763 static void tg3_napi_enable(struct tg3 *tp)
 764 {
 765         int i;
 766
 767         for (i = 0; i < tp->irq_cnt; i++)
 768                 napi_enable(&tp->napi[i].napi);
 769 }
 770
 771 static inline void tg3_netif_stop(struct tg3 *tp)
 772 {
 773         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 774         tg3_napi_disable(tp);
 775         netif_tx_disable(tp->dev);
 776 }
 777
 778 static inline void tg3_netif_start(struct tg3 *tp)
 779 {
 780         /* NOTE: unconditional netif_tx_wake_all_queues is only
 781          * appropriate so long as all callers are assured to
 782          * have free tx slots (such as after tg3_init_hw)
 783          */
 784         netif_tx_wake_all_queues(tp->dev);
 785
 786         tg3_napi_enable(tp);
 787         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
 788         tg3_enable_ints(tp);
 789 }
 790
 791 static void tg3_switch_clocks(struct tg3 *tp)
 792 {
 793         u32 clock_ctrl;
 794         u32 orig_clock_ctrl;
 795
 796         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 797             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 798                 return;
 799
 800         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 801
 802         orig_clock_ctrl = clock_ctrl;
 803         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 804                        CLOCK_CTRL_CLKRUN_OENABLE |
 805                        0x1f);
 806         tp->pci_clock_ctrl = clock_ctrl;
 807
 808         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 809                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 810                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 811                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 812                 }
 813         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 814                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 815                             clock_ctrl |
 816                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 817                             40);
 818                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 819                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 820                             40);
 821         }
 822         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 823 }
 824
 825 #define PHY_BUSY_LOOPS  5000
 826
 827 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 828 {
 829         u32 frame_val;
 830         unsigned int loops;
 831         int ret;
 832
 833         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 834                 tw32_f(MAC_MI_MODE,
 835                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 836                 udelay(80);
 837         }
 838
 839         *val = 0x0;
 840
 841         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 842                       MI_COM_PHY_ADDR_MASK);
 843         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 844                       MI_COM_REG_ADDR_MASK);
 845         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 846
 847         tw32_f(MAC_MI_COM, frame_val);
 848
 849         loops = PHY_BUSY_LOOPS;
 850         while (loops != 0) {
 851                 udelay(10);
 852                 frame_val = tr32(MAC_MI_COM);
 853
 854                 if ((frame_val & MI_COM_BUSY) == 0) {
 855                         udelay(5);
 856                         frame_val = tr32(MAC_MI_COM);
 857                         break;
 858                 }
 859                 loops -= 1;
 860         }
 861
 862         ret = -EBUSY;
 863         if (loops != 0) {
 864                 *val = frame_val & MI_COM_DATA_MASK;
 865                 ret = 0;
 866         }
 867
 868         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 869                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 870                 udelay(80);
 871         }
 872
 873         return ret;
 874 }
 875
 876 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 877 {
 878         u32 frame_val;
 879         unsigned int loops;
 880         int ret;
 881
 882         if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
 883             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 884                 return 0;
 885
 886         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 887                 tw32_f(MAC_MI_MODE,
 888                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 889                 udelay(80);
 890         }
 891
 892         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 893                       MI_COM_PHY_ADDR_MASK);
 894         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 895                       MI_COM_REG_ADDR_MASK);
 896         frame_val |= (val & MI_COM_DATA_MASK);
 897         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 898
 899         tw32_f(MAC_MI_COM, frame_val);
 900
 901         loops = PHY_BUSY_LOOPS;
 902         while (loops != 0) {
 903                 udelay(10);
 904                 frame_val = tr32(MAC_MI_COM);
 905                 if ((frame_val & MI_COM_BUSY) == 0) {
 906                         udelay(5);
 907                         frame_val = tr32(MAC_MI_COM);
 908                         break;
 909                 }
 910                 loops -= 1;
 911         }
 912
 913         ret = -EBUSY;
 914         if (loops != 0)
 915                 ret = 0;
 916
 917         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 918                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 919                 udelay(80);
 920         }
 921
 922         return ret;
 923 }
 924
 925 static int tg3_bmcr_reset(struct tg3 *tp)
 926 {
 927         u32 phy_control;
 928         int limit, err;
 929
 930         /* OK, reset it, and poll the BMCR_RESET bit until it
 931          * clears or we time out.
 932          */
 933         phy_control = BMCR_RESET;
 934         err = tg3_writephy(tp, MII_BMCR, phy_control);
 935         if (err != 0)
 936                 return -EBUSY;
 937
 938         limit = 5000;
 939         while (limit--) {
 940                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 941                 if (err != 0)
 942                         return -EBUSY;
 943
 944                 if ((phy_control & BMCR_RESET) == 0) {
 945                         udelay(40);
 946                         break;
 947                 }
 948                 udelay(10);
 949         }
 950         if (limit < 0)
 951                 return -EBUSY;
 952
 953         return 0;
 954 }
 955
 956 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 957 {
 958         struct tg3 *tp = bp->priv;
 959         u32 val;
 960
 961         spin_lock_bh(&tp->lock);
 962
 963         if (tg3_readphy(tp, reg, &val))
 964                 val = -EIO;
 965
 966         spin_unlock_bh(&tp->lock);
 967
 968         return val;
 969 }
 970
 971 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 972 {
 973         struct tg3 *tp = bp->priv;
 974         u32 ret = 0;
 975
 976         spin_lock_bh(&tp->lock);
 977
 978         if (tg3_writephy(tp, reg, val))
 979                 ret = -EIO;
 980
 981         spin_unlock_bh(&tp->lock);
 982
 983         return ret;
 984 }
 985
 986 static int tg3_mdio_reset(struct mii_bus *bp)
 987 {
 988         return 0;
 989 }
 990
 991 static void tg3_mdio_config_5785(struct tg3 *tp)
 992 {
 993         u32 val;
 994         struct phy_device *phydev;
 995
 996         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
 997         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 998         case PHY_ID_BCM50610:
 999         case PHY_ID_BCM50610M:
1000                 val = MAC_PHYCFG2_50610_LED_MODES;
1001                 break;
1002         case PHY_ID_BCMAC131:
1003                 val = MAC_PHYCFG2_AC131_LED_MODES;
1004                 break;
1005         case PHY_ID_RTL8211C:
1006                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1007                 break;
1008         case PHY_ID_RTL8201E:
1009                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1010                 break;
1011         default:
1012                 return;
1013         }
1014
1015         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1016                 tw32(MAC_PHYCFG2, val);
1017
1018                 val = tr32(MAC_PHYCFG1);
1019                 val &= ~(MAC_PHYCFG1_RGMII_INT |
1020                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1021                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1022                 tw32(MAC_PHYCFG1, val);
1023
1024                 return;
1025         }
1026
1027         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
1028                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1029                        MAC_PHYCFG2_FMODE_MASK_MASK |
1030                        MAC_PHYCFG2_GMODE_MASK_MASK |
1031                        MAC_PHYCFG2_ACT_MASK_MASK   |
1032                        MAC_PHYCFG2_QUAL_MASK_MASK |
1033                        MAC_PHYCFG2_INBAND_ENABLE;
1034
1035         tw32(MAC_PHYCFG2, val);
1036
1037         val = tr32(MAC_PHYCFG1);
1038         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1039                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1040         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1041                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1042                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1043                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1044                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1045         }
1046         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1047                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1048         tw32(MAC_PHYCFG1, val);
1049
1050         val = tr32(MAC_EXT_RGMII_MODE);
1051         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1052                  MAC_RGMII_MODE_RX_QUALITY |
1053                  MAC_RGMII_MODE_RX_ACTIVITY |
1054                  MAC_RGMII_MODE_RX_ENG_DET |
1055                  MAC_RGMII_MODE_TX_ENABLE |
1056                  MAC_RGMII_MODE_TX_LOWPWR |
1057                  MAC_RGMII_MODE_TX_RESET);
1058         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1059                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1060                         val |= MAC_RGMII_MODE_RX_INT_B |
1061                                MAC_RGMII_MODE_RX_QUALITY |
1062                                MAC_RGMII_MODE_RX_ACTIVITY |
1063                                MAC_RGMII_MODE_RX_ENG_DET;
1064                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1065                         val |= MAC_RGMII_MODE_TX_ENABLE |
1066                                MAC_RGMII_MODE_TX_LOWPWR |
1067                                MAC_RGMII_MODE_TX_RESET;
1068         }
1069         tw32(MAC_EXT_RGMII_MODE, val);
1070 }
1071
1072 static void tg3_mdio_start(struct tg3 *tp)
1073 {
1074         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1075         tw32_f(MAC_MI_MODE, tp->mi_mode);
1076         udelay(80);
1077
1078         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1079             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1080                 tg3_mdio_config_5785(tp);
1081 }
1082
1083 static int tg3_mdio_init(struct tg3 *tp)
1084 {
1085         int i;
1086         u32 reg;
1087         struct phy_device *phydev;
1088
1089         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1090             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
1091                 u32 is_serdes;
1092
1093                 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1094
1095                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1096                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1097                 else
1098                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1099                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1100                 if (is_serdes)
1101                         tp->phy_addr += 7;
1102         } else
1103                 tp->phy_addr = TG3_PHY_MII_ADDR;
1104
1105         tg3_mdio_start(tp);
1106
1107         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1108             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1109                 return 0;
1110
1111         tp->mdio_bus = mdiobus_alloc();
1112         if (tp->mdio_bus == NULL)
1113                 return -ENOMEM;
1114
1115         tp->mdio_bus->name     = "tg3 mdio bus";
1116         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1117                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1118         tp->mdio_bus->priv     = tp;
1119         tp->mdio_bus->parent   = &tp->pdev->dev;
1120         tp->mdio_bus->read     = &tg3_mdio_read;
1121         tp->mdio_bus->write    = &tg3_mdio_write;
1122         tp->mdio_bus->reset    = &tg3_mdio_reset;
1123         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1124         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1125
1126         for (i = 0; i < PHY_MAX_ADDR; i++)
1127                 tp->mdio_bus->irq[i] = PHY_POLL;
1128
1129         /* The bus registration will look for all the PHYs on the mdio bus.
1130          * Unfortunately, it does not ensure the PHY is powered up before
1131          * accessing the PHY ID registers.  A chip reset is the
1132          * quickest way to bring the device back to an operational state..
1133          */
1134         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1135                 tg3_bmcr_reset(tp);
1136
1137         i = mdiobus_register(tp->mdio_bus);
1138         if (i) {
1139                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1140                 mdiobus_free(tp->mdio_bus);
1141                 return i;
1142         }
1143
1144         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1145
1146         if (!phydev || !phydev->drv) {
1147                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1148                 mdiobus_unregister(tp->mdio_bus);
1149                 mdiobus_free(tp->mdio_bus);
1150                 return -ENODEV;
1151         }
1152
1153         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1154         case PHY_ID_BCM57780:
1155                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1156                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1157                 break;
1158         case PHY_ID_BCM50610:
1159         case PHY_ID_BCM50610M:
1160                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1161                                      PHY_BRCM_RX_REFCLK_UNUSED |
1162                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1163                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1164                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1165                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1166                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1167                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1168                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1169                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1170                 /* fallthru */
1171         case PHY_ID_RTL8211C:
1172                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1173                 break;
1174         case PHY_ID_RTL8201E:
1175         case PHY_ID_BCMAC131:
1176                 phydev->interface = PHY_INTERFACE_MODE_MII;
1177                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1178                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1179                 break;
1180         }
1181
1182         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1183
1184         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1185                 tg3_mdio_config_5785(tp);
1186
1187         return 0;
1188 }
1189
1190 static void tg3_mdio_fini(struct tg3 *tp)
1191 {
1192         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1193                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1194                 mdiobus_unregister(tp->mdio_bus);
1195                 mdiobus_free(tp->mdio_bus);
1196         }
1197 }
1198
1199 /* tp->lock is held. */
1200 static inline void tg3_generate_fw_event(struct tg3 *tp)
1201 {
1202         u32 val;
1203
1204         val = tr32(GRC_RX_CPU_EVENT);
1205         val |= GRC_RX_CPU_DRIVER_EVENT;
1206         tw32_f(GRC_RX_CPU_EVENT, val);
1207
1208         tp->last_event_jiffies = jiffies;
1209 }
1210
1211 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1212
1213 /* tp->lock is held. */
1214 static void tg3_wait_for_event_ack(struct tg3 *tp)
1215 {
1216         int i;
1217         unsigned int delay_cnt;
1218         long time_remain;
1219
1220         /* If enough time has passed, no wait is necessary. */
1221         time_remain = (long)(tp->last_event_jiffies + 1 +
1222                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1223                       (long)jiffies;
1224         if (time_remain < 0)
1225                 return;
1226
1227         /* Check if we can shorten the wait time. */
1228         delay_cnt = jiffies_to_usecs(time_remain);
1229         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1230                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1231         delay_cnt = (delay_cnt >> 3) + 1;
1232
1233         for (i = 0; i < delay_cnt; i++) {
1234                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1235                         break;
1236                 udelay(8);
1237         }
1238 }
1239
1240 /* tp->lock is held. */
1241 static void tg3_ump_link_report(struct tg3 *tp)
1242 {
1243         u32 reg;
1244         u32 val;
1245
1246         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1247             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1248                 return;
1249
1250         tg3_wait_for_event_ack(tp);
1251
1252         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1253
1254         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1255
1256         val = 0;
1257         if (!tg3_readphy(tp, MII_BMCR, &reg))
1258                 val = reg << 16;
1259         if (!tg3_readphy(tp, MII_BMSR, &reg))
1260                 val |= (reg & 0xffff);
1261         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1262
1263         val = 0;
1264         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1265                 val = reg << 16;
1266         if (!tg3_readphy(tp, MII_LPA, &reg))
1267                 val |= (reg & 0xffff);
1268         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1269
1270         val = 0;
1271         if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1272                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1273                         val = reg << 16;
1274                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1275                         val |= (reg & 0xffff);
1276         }
1277         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1278
1279         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1280                 val = reg << 16;
1281         else
1282                 val = 0;
1283         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1284
1285         tg3_generate_fw_event(tp);
1286 }
1287
1288 static void tg3_link_report(struct tg3 *tp)
1289 {
1290         if (!netif_carrier_ok(tp->dev)) {
1291                 netif_info(tp, link, tp->dev, "Link is down\n");
1292                 tg3_ump_link_report(tp);
1293         } else if (netif_msg_link(tp)) {
1294                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1295                             (tp->link_config.active_speed == SPEED_1000 ?
1296                              1000 :
1297                              (tp->link_config.active_speed == SPEED_100 ?
1298                               100 : 10)),
1299                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1300                              "full" : "half"));
1301
1302                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1303                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1304                             "on" : "off",
1305                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1306                             "on" : "off");
1307                 tg3_ump_link_report(tp);
1308         }
1309 }
1310
1311 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1312 {
1313         u16 miireg;
1314
1315         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1316                 miireg = ADVERTISE_PAUSE_CAP;
1317         else if (flow_ctrl & FLOW_CTRL_TX)
1318                 miireg = ADVERTISE_PAUSE_ASYM;
1319         else if (flow_ctrl & FLOW_CTRL_RX)
1320                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1321         else
1322                 miireg = 0;
1323
1324         return miireg;
1325 }
1326
1327 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1328 {
1329         u16 miireg;
1330
1331         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1332                 miireg = ADVERTISE_1000XPAUSE;
1333         else if (flow_ctrl & FLOW_CTRL_TX)
1334                 miireg = ADVERTISE_1000XPSE_ASYM;
1335         else if (flow_ctrl & FLOW_CTRL_RX)
1336                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1337         else
1338                 miireg = 0;
1339
1340         return miireg;
1341 }
1342
1343 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1344 {
1345         u8 cap = 0;
1346
1347         if (lcladv & ADVERTISE_1000XPAUSE) {
1348                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1349                         if (rmtadv & LPA_1000XPAUSE)
1350                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1351                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1352                                 cap = FLOW_CTRL_RX;
1353                 } else {
1354                         if (rmtadv & LPA_1000XPAUSE)
1355                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1356                 }
1357         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1358                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1359                         cap = FLOW_CTRL_TX;
1360         }
1361
1362         return cap;
1363 }
1364
1365 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1366 {
1367         u8 autoneg;
1368         u8 flowctrl = 0;
1369         u32 old_rx_mode = tp->rx_mode;
1370         u32 old_tx_mode = tp->tx_mode;
1371
1372         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1373                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1374         else
1375                 autoneg = tp->link_config.autoneg;
1376
1377         if (autoneg == AUTONEG_ENABLE &&
1378             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1379                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1380                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1381                 else
1382                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1383         } else
1384                 flowctrl = tp->link_config.flowctrl;
1385
1386         tp->link_config.active_flowctrl = flowctrl;
1387
1388         if (flowctrl & FLOW_CTRL_RX)
1389                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1390         else
1391                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1392
1393         if (old_rx_mode != tp->rx_mode)
1394                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1395
1396         if (flowctrl & FLOW_CTRL_TX)
1397                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1398         else
1399                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1400
1401         if (old_tx_mode != tp->tx_mode)
1402                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1403 }
1404
1405 static void tg3_adjust_link(struct net_device *dev)
1406 {
1407         u8 oldflowctrl, linkmesg = 0;
1408         u32 mac_mode, lcl_adv, rmt_adv;
1409         struct tg3 *tp = netdev_priv(dev);
1410         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1411
1412         spin_lock_bh(&tp->lock);
1413
1414         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1415                                     MAC_MODE_HALF_DUPLEX);
1416
1417         oldflowctrl = tp->link_config.active_flowctrl;
1418
1419         if (phydev->link) {
1420                 lcl_adv = 0;
1421                 rmt_adv = 0;
1422
1423                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1424                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1425                 else if (phydev->speed == SPEED_1000 ||
1426                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1427                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1428                 else
1429                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1430
1431                 if (phydev->duplex == DUPLEX_HALF)
1432                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1433                 else {
1434                         lcl_adv = tg3_advert_flowctrl_1000T(
1435                                   tp->link_config.flowctrl);
1436
1437                         if (phydev->pause)
1438                                 rmt_adv = LPA_PAUSE_CAP;
1439                         if (phydev->asym_pause)
1440                                 rmt_adv |= LPA_PAUSE_ASYM;
1441                 }
1442
1443                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1444         } else
1445                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1446
1447         if (mac_mode != tp->mac_mode) {
1448                 tp->mac_mode = mac_mode;
1449                 tw32_f(MAC_MODE, tp->mac_mode);
1450                 udelay(40);
1451         }
1452
1453         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1454                 if (phydev->speed == SPEED_10)
1455                         tw32(MAC_MI_STAT,
1456                              MAC_MI_STAT_10MBPS_MODE |
1457                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1458                 else
1459                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1460         }
1461
1462         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1463                 tw32(MAC_TX_LENGTHS,
1464                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1465                       (6 << TX_LENGTHS_IPG_SHIFT) |
1466                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1467         else
1468                 tw32(MAC_TX_LENGTHS,
1469                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1470                       (6 << TX_LENGTHS_IPG_SHIFT) |
1471                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1472
1473         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1474             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1475             phydev->speed != tp->link_config.active_speed ||
1476             phydev->duplex != tp->link_config.active_duplex ||
1477             oldflowctrl != tp->link_config.active_flowctrl)
1478                 linkmesg = 1;
1479
1480         tp->link_config.active_speed = phydev->speed;
1481         tp->link_config.active_duplex = phydev->duplex;
1482
1483         spin_unlock_bh(&tp->lock);
1484
1485         if (linkmesg)
1486                 tg3_link_report(tp);
1487 }
1488
1489 static int tg3_phy_init(struct tg3 *tp)
1490 {
1491         struct phy_device *phydev;
1492
1493         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1494                 return 0;
1495
1496         /* Bring the PHY back to a known state. */
1497         tg3_bmcr_reset(tp);
1498
1499         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1500
1501         /* Attach the MAC to the PHY. */
1502         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1503                              phydev->dev_flags, phydev->interface);
1504         if (IS_ERR(phydev)) {
1505                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1506                 return PTR_ERR(phydev);
1507         }
1508
1509         /* Mask with MAC supported features. */
1510         switch (phydev->interface) {
1511         case PHY_INTERFACE_MODE_GMII:
1512         case PHY_INTERFACE_MODE_RGMII:
1513                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1514                         phydev->supported &= (PHY_GBIT_FEATURES |
1515                                               SUPPORTED_Pause |
1516                                               SUPPORTED_Asym_Pause);
1517                         break;
1518                 }
1519                 /* fallthru */
1520         case PHY_INTERFACE_MODE_MII:
1521                 phydev->supported &= (PHY_BASIC_FEATURES |
1522                                       SUPPORTED_Pause |
1523                                       SUPPORTED_Asym_Pause);
1524                 break;
1525         default:
1526                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1527                 return -EINVAL;
1528         }
1529
1530         tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1531
1532         phydev->advertising = phydev->supported;
1533
1534         return 0;
1535 }
1536
1537 static void tg3_phy_start(struct tg3 *tp)
1538 {
1539         struct phy_device *phydev;
1540
1541         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1542                 return;
1543
1544         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1545
1546         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1547                 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1548                 phydev->speed = tp->link_config.orig_speed;
1549                 phydev->duplex = tp->link_config.orig_duplex;
1550                 phydev->autoneg = tp->link_config.orig_autoneg;
1551                 phydev->advertising = tp->link_config.orig_advertising;
1552         }
1553
1554         phy_start(phydev);
1555
1556         phy_start_aneg(phydev);
1557 }
1558
1559 static void tg3_phy_stop(struct tg3 *tp)
1560 {
1561         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1562                 return;
1563
1564         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1565 }
1566
1567 static void tg3_phy_fini(struct tg3 *tp)
1568 {
1569         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1570                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1571                 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1572         }
1573 }
1574
1575 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1576 {
1577         int err;
1578
1579         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1580         if (!err)
1581                 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1582
1583         return err;
1584 }
1585
1586 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1587 {
1588         u32 phytest;
1589
1590         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1591                 u32 phy;
1592
1593                 tg3_writephy(tp, MII_TG3_FET_TEST,
1594                              phytest | MII_TG3_FET_SHADOW_EN);
1595                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1596                         if (enable)
1597                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1598                         else
1599                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1600                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1601                 }
1602                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1603         }
1604 }
1605
1606 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1607 {
1608         u32 reg;
1609
1610         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1611             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1612               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1613              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1614                 return;
1615
1616         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1617                 tg3_phy_fet_toggle_apd(tp, enable);
1618                 return;
1619         }
1620
1621         reg = MII_TG3_MISC_SHDW_WREN |
1622               MII_TG3_MISC_SHDW_SCR5_SEL |
1623               MII_TG3_MISC_SHDW_SCR5_LPED |
1624               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1625               MII_TG3_MISC_SHDW_SCR5_SDTL |
1626               MII_TG3_MISC_SHDW_SCR5_C125OE;
1627         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1628                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1629
1630         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1631
1632
1633         reg = MII_TG3_MISC_SHDW_WREN |
1634               MII_TG3_MISC_SHDW_APD_SEL |
1635               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1636         if (enable)
1637                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1638
1639         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1640 }
1641
1642 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1643 {
1644         u32 phy;
1645
1646         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1647             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
1648                 return;
1649
1650         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1651                 u32 ephy;
1652
1653                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1654                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1655
1656                         tg3_writephy(tp, MII_TG3_FET_TEST,
1657                                      ephy | MII_TG3_FET_SHADOW_EN);
1658                         if (!tg3_readphy(tp, reg, &phy)) {
1659                                 if (enable)
1660                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1661                                 else
1662                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1663                                 tg3_writephy(tp, reg, phy);
1664                         }
1665                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1666                 }
1667         } else {
1668                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1669                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1670                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1671                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1672                         if (enable)
1673                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1674                         else
1675                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1676                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1677                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1678                 }
1679         }
1680 }
1681
1682 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1683 {
1684         u32 val;
1685
1686         if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1687                 return;
1688
1689         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1690             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1691                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1692                              (val | (1 << 15) | (1 << 4)));
1693 }
1694
1695 static void tg3_phy_apply_otp(struct tg3 *tp)
1696 {
1697         u32 otp, phy;
1698
1699         if (!tp->phy_otp)
1700                 return;
1701
1702         otp = tp->phy_otp;
1703
1704         /* Enable SM_DSP clock and tx 6dB coding. */
1705         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1706               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1707               MII_TG3_AUXCTL_ACTL_TX_6DB;
1708         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1709
1710         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1711         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1712         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1713
1714         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1715               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1716         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1717
1718         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1719         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1720         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1721
1722         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1723         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1724
1725         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1726         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1727
1728         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1729               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1730         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1731
1732         /* Turn off SM_DSP clock. */
1733         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1734               MII_TG3_AUXCTL_ACTL_TX_6DB;
1735         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1736 }
1737
1738 static int tg3_wait_macro_done(struct tg3 *tp)
1739 {
1740         int limit = 100;
1741
1742         while (limit--) {
1743                 u32 tmp32;
1744
1745                 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1746                         if ((tmp32 & 0x1000) == 0)
1747                                 break;
1748                 }
1749         }
1750         if (limit < 0)
1751                 return -EBUSY;
1752
1753         return 0;
1754 }
1755
1756 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1757 {
1758         static const u32 test_pat[4][6] = {
1759         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1760         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1761         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1762         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1763         };
1764         int chan;
1765
1766         for (chan = 0; chan < 4; chan++) {
1767                 int i;
1768
1769                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1770                              (chan * 0x2000) | 0x0200);
1771                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1772
1773                 for (i = 0; i < 6; i++)
1774                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1775                                      test_pat[chan][i]);
1776
1777                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1778                 if (tg3_wait_macro_done(tp)) {
1779                         *resetp = 1;
1780                         return -EBUSY;
1781                 }
1782
1783                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1784                              (chan * 0x2000) | 0x0200);
1785                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1786                 if (tg3_wait_macro_done(tp)) {
1787                         *resetp = 1;
1788                         return -EBUSY;
1789                 }
1790
1791                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1792                 if (tg3_wait_macro_done(tp)) {
1793                         *resetp = 1;
1794                         return -EBUSY;
1795                 }
1796
1797                 for (i = 0; i < 6; i += 2) {
1798                         u32 low, high;
1799
1800                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1801                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1802                             tg3_wait_macro_done(tp)) {
1803                                 *resetp = 1;
1804                                 return -EBUSY;
1805                         }
1806                         low &= 0x7fff;
1807                         high &= 0x000f;
1808                         if (low != test_pat[chan][i] ||
1809                             high != test_pat[chan][i+1]) {
1810                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1811                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1812                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1813
1814                                 return -EBUSY;
1815                         }
1816                 }
1817         }
1818
1819         return 0;
1820 }
1821
1822 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1823 {
1824         int chan;
1825
1826         for (chan = 0; chan < 4; chan++) {
1827                 int i;
1828
1829                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1830                              (chan * 0x2000) | 0x0200);
1831                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1832                 for (i = 0; i < 6; i++)
1833                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1834                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1835                 if (tg3_wait_macro_done(tp))
1836                         return -EBUSY;
1837         }
1838
1839         return 0;
1840 }
1841
1842 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1843 {
1844         u32 reg32, phy9_orig;
1845         int retries, do_phy_reset, err;
1846
1847         retries = 10;
1848         do_phy_reset = 1;
1849         do {
1850                 if (do_phy_reset) {
1851                         err = tg3_bmcr_reset(tp);
1852                         if (err)
1853                                 return err;
1854                         do_phy_reset = 0;
1855                 }
1856
1857                 /* Disable transmitter and interrupt.  */
1858                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1859                         continue;
1860
1861                 reg32 |= 0x3000;
1862                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1863
1864                 /* Set full-duplex, 1000 mbps.  */
1865                 tg3_writephy(tp, MII_BMCR,
1866                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1867
1868                 /* Set to master mode.  */
1869                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1870                         continue;
1871
1872                 tg3_writephy(tp, MII_TG3_CTRL,
1873                              (MII_TG3_CTRL_AS_MASTER |
1874                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1875
1876                 /* Enable SM_DSP_CLOCK and 6dB.  */
1877                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1878
1879                 /* Block the PHY control access.  */
1880                 tg3_phydsp_write(tp, 0x8005, 0x0800);
1881
1882                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1883                 if (!err)
1884                         break;
1885         } while (--retries);
1886
1887         err = tg3_phy_reset_chanpat(tp);
1888         if (err)
1889                 return err;
1890
1891         tg3_phydsp_write(tp, 0x8005, 0x0000);
1892
1893         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1894         tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1895
1896         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1897             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1898                 /* Set Extended packet length bit for jumbo frames */
1899                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1900         } else {
1901                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1902         }
1903
1904         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1905
1906         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1907                 reg32 &= ~0x3000;
1908                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1909         } else if (!err)
1910                 err = -EBUSY;
1911
1912         return err;
1913 }
1914
1915 /* This will reset the tigon3 PHY if there is no valid
1916  * link unless the FORCE argument is non-zero.
1917  */
1918 static int tg3_phy_reset(struct tg3 *tp)
1919 {
1920         u32 val, cpmuctrl;
1921         int err;
1922
1923         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1924                 val = tr32(GRC_MISC_CFG);
1925                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1926                 udelay(40);
1927         }
1928         err  = tg3_readphy(tp, MII_BMSR, &val);
1929         err |= tg3_readphy(tp, MII_BMSR, &val);
1930         if (err != 0)
1931                 return -EBUSY;
1932
1933         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1934                 netif_carrier_off(tp->dev);
1935                 tg3_link_report(tp);
1936         }
1937
1938         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1939             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1940             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1941                 err = tg3_phy_reset_5703_4_5(tp);
1942                 if (err)
1943                         return err;
1944                 goto out;
1945         }
1946
1947         cpmuctrl = 0;
1948         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1949             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1950                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1951                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1952                         tw32(TG3_CPMU_CTRL,
1953                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1954         }
1955
1956         err = tg3_bmcr_reset(tp);
1957         if (err)
1958                 return err;
1959
1960         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1961                 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1962                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
1963
1964                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1965         }
1966
1967         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1968             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1969                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1970                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1971                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1972                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1973                         udelay(40);
1974                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1975                 }
1976         }
1977
1978         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1979              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1980             (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
1981                 return 0;
1982
1983         tg3_phy_apply_otp(tp);
1984
1985         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
1986                 tg3_phy_toggle_apd(tp, true);
1987         else
1988                 tg3_phy_toggle_apd(tp, false);
1989
1990 out:
1991         if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) {
1992                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1993                 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
1994                 tg3_phydsp_write(tp, 0x000a, 0x0323);
1995                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1996         }
1997         if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
1998                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
1999                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2000         }
2001         if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2002                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2003                 tg3_phydsp_write(tp, 0x000a, 0x310b);
2004                 tg3_phydsp_write(tp, 0x201f, 0x9506);
2005                 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2006                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2007         } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2008                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2009                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2010                 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2011                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2012                         tg3_writephy(tp, MII_TG3_TEST1,
2013                                      MII_TG3_TEST1_TRIM_EN | 0x4);
2014                 } else
2015                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2016                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2017         }
2018         /* Set Extended packet length bit (bit 14) on all chips that */
2019         /* support jumbo frames */
2020         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2021                 /* Cannot do read-modify-write on 5401 */
2022                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2023         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2024                 /* Set bit 14 with read-modify-write to preserve other bits */
2025                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2026                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
2027                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val | 0x4000);
2028         }
2029
2030         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2031          * jumbo frames transmission.
2032          */
2033         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2034                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2035                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2036                                      val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2037         }
2038
2039         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2040                 /* adjust output voltage */
2041                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2042         }
2043
2044         tg3_phy_toggle_automdix(tp, 1);
2045         tg3_phy_set_wirespeed(tp);
2046         return 0;
2047 }
2048
2049 static void tg3_frob_aux_power(struct tg3 *tp)
2050 {
2051         struct tg3 *tp_peer = tp;
2052
2053         /* The GPIOs do something completely different on 57765. */
2054         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2055             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2056             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2057                 return;
2058
2059         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2060             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2061             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2062                 struct net_device *dev_peer;
2063
2064                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2065                 /* remove_one() may have been run on the peer. */
2066                 if (!dev_peer)
2067                         tp_peer = tp;
2068                 else
2069                         tp_peer = netdev_priv(dev_peer);
2070         }
2071
2072         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2073             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2074             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2075             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2076                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2077                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2078                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2079                                     (GRC_LCLCTRL_GPIO_OE0 |
2080                                      GRC_LCLCTRL_GPIO_OE1 |
2081                                      GRC_LCLCTRL_GPIO_OE2 |
2082                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2083                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2084                                     100);
2085                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2086                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2087                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2088                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2089                                              GRC_LCLCTRL_GPIO_OE1 |
2090                                              GRC_LCLCTRL_GPIO_OE2 |
2091                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2092                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2093                                              tp->grc_local_ctrl;
2094                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2095
2096                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2097                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2098
2099                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2100                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2101                 } else {
2102                         u32 no_gpio2;
2103                         u32 grc_local_ctrl = 0;
2104
2105                         if (tp_peer != tp &&
2106                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2107                                 return;
2108
2109                         /* Workaround to prevent overdrawing Amps. */
2110                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2111                             ASIC_REV_5714) {
2112                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2113                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2114                                             grc_local_ctrl, 100);
2115                         }
2116
2117                         /* On 5753 and variants, GPIO2 cannot be used. */
2118                         no_gpio2 = tp->nic_sram_data_cfg &
2119                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2120
2121                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2122                                          GRC_LCLCTRL_GPIO_OE1 |
2123                                          GRC_LCLCTRL_GPIO_OE2 |
2124                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2125                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2126                         if (no_gpio2) {
2127                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2128                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2129                         }
2130                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2131                                                     grc_local_ctrl, 100);
2132
2133                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2134
2135                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2136                                                     grc_local_ctrl, 100);
2137
2138                         if (!no_gpio2) {
2139                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2140                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2141                                             grc_local_ctrl, 100);
2142                         }
2143                 }
2144         } else {
2145                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2146                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2147                         if (tp_peer != tp &&
2148                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2149                                 return;
2150
2151                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2152                                     (GRC_LCLCTRL_GPIO_OE1 |
2153                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2154
2155                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2156                                     GRC_LCLCTRL_GPIO_OE1, 100);
2157
2158                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2159                                     (GRC_LCLCTRL_GPIO_OE1 |
2160                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2161                 }
2162         }
2163 }
2164
2165 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2166 {
2167         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2168                 return 1;
2169         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2170                 if (speed != SPEED_10)
2171                         return 1;
2172         } else if (speed == SPEED_10)
2173                 return 1;
2174
2175         return 0;
2176 }
2177
2178 static int tg3_setup_phy(struct tg3 *, int);
2179
2180 #define RESET_KIND_SHUTDOWN     0
2181 #define RESET_KIND_INIT         1
2182 #define RESET_KIND_SUSPEND      2
2183
2184 static void tg3_write_sig_post_reset(struct tg3 *, int);
2185 static int tg3_halt_cpu(struct tg3 *, u32);
2186
2187 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2188 {
2189         u32 val;
2190
2191         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2192                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2193                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2194                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2195
2196                         sg_dig_ctrl |=
2197                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2198                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2199                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2200                 }
2201                 return;
2202         }
2203
2204         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2205                 tg3_bmcr_reset(tp);
2206                 val = tr32(GRC_MISC_CFG);
2207                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2208                 udelay(40);
2209                 return;
2210         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2211                 u32 phytest;
2212                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2213                         u32 phy;
2214
2215                         tg3_writephy(tp, MII_ADVERTISE, 0);
2216                         tg3_writephy(tp, MII_BMCR,
2217                                      BMCR_ANENABLE | BMCR_ANRESTART);
2218
2219                         tg3_writephy(tp, MII_TG3_FET_TEST,
2220                                      phytest | MII_TG3_FET_SHADOW_EN);
2221                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2222                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2223                                 tg3_writephy(tp,
2224                                              MII_TG3_FET_SHDW_AUXMODE4,
2225                                              phy);
2226                         }
2227                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2228                 }
2229                 return;
2230         } else if (do_low_power) {
2231                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2232                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2233
2234                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2235                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2236                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2237                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2238                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2239         }
2240
2241         /* The PHY should not be powered down on some chips because
2242          * of bugs.
2243          */
2244         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2245             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2246             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2247              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2248                 return;
2249
2250         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2251             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2252                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2253                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2254                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2255                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2256         }
2257
2258         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2259 }
2260
2261 /* tp->lock is held. */
2262 static int tg3_nvram_lock(struct tg3 *tp)
2263 {
2264         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2265                 int i;
2266
2267                 if (tp->nvram_lock_cnt == 0) {
2268                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2269                         for (i = 0; i < 8000; i++) {
2270                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2271                                         break;
2272                                 udelay(20);
2273                         }
2274                         if (i == 8000) {
2275                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2276                                 return -ENODEV;
2277                         }
2278                 }
2279                 tp->nvram_lock_cnt++;
2280         }
2281         return 0;
2282 }
2283
2284 /* tp->lock is held. */
2285 static void tg3_nvram_unlock(struct tg3 *tp)
2286 {
2287         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2288                 if (tp->nvram_lock_cnt > 0)
2289                         tp->nvram_lock_cnt--;
2290                 if (tp->nvram_lock_cnt == 0)
2291                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2292         }
2293 }
2294
2295 /* tp->lock is held. */
2296 static void tg3_enable_nvram_access(struct tg3 *tp)
2297 {
2298         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2299             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2300                 u32 nvaccess = tr32(NVRAM_ACCESS);
2301
2302                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2303         }
2304 }
2305
2306 /* tp->lock is held. */
2307 static void tg3_disable_nvram_access(struct tg3 *tp)
2308 {
2309         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2310             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2311                 u32 nvaccess = tr32(NVRAM_ACCESS);
2312
2313                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2314         }
2315 }
2316
2317 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2318                                         u32 offset, u32 *val)
2319 {
2320         u32 tmp;
2321         int i;
2322
2323         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2324                 return -EINVAL;
2325
2326         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2327                                         EEPROM_ADDR_DEVID_MASK |
2328                                         EEPROM_ADDR_READ);
2329         tw32(GRC_EEPROM_ADDR,
2330              tmp |
2331              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2332              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2333               EEPROM_ADDR_ADDR_MASK) |
2334              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2335
2336         for (i = 0; i < 1000; i++) {
2337                 tmp = tr32(GRC_EEPROM_ADDR);
2338
2339                 if (tmp & EEPROM_ADDR_COMPLETE)
2340                         break;
2341                 msleep(1);
2342         }
2343         if (!(tmp & EEPROM_ADDR_COMPLETE))
2344                 return -EBUSY;
2345
2346         tmp = tr32(GRC_EEPROM_DATA);
2347
2348         /*
2349          * The data will always be opposite the native endian
2350          * format.  Perform a blind byteswap to compensate.
2351          */
2352         *val = swab32(tmp);
2353
2354         return 0;
2355 }
2356
2357 #define NVRAM_CMD_TIMEOUT 10000
2358
2359 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2360 {
2361         int i;
2362
2363         tw32(NVRAM_CMD, nvram_cmd);
2364         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2365                 udelay(10);
2366                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2367                         udelay(10);
2368                         break;
2369                 }
2370         }
2371
2372         if (i == NVRAM_CMD_TIMEOUT)
2373                 return -EBUSY;
2374
2375         return 0;
2376 }
2377
2378 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2379 {
2380         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2381             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2382             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2383            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2384             (tp->nvram_jedecnum == JEDEC_ATMEL))
2385
2386                 addr = ((addr / tp->nvram_pagesize) <<
2387                         ATMEL_AT45DB0X1B_PAGE_POS) +
2388                        (addr % tp->nvram_pagesize);
2389
2390         return addr;
2391 }
2392
2393 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2394 {
2395         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2396             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2397             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2398            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2399             (tp->nvram_jedecnum == JEDEC_ATMEL))
2400
2401                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2402                         tp->nvram_pagesize) +
2403                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2404
2405         return addr;
2406 }
2407
2408 /* NOTE: Data read in from NVRAM is byteswapped according to
2409  * the byteswapping settings for all other register accesses.
2410  * tg3 devices are BE devices, so on a BE machine, the data
2411  * returned will be exactly as it is seen in NVRAM.  On a LE
2412  * machine, the 32-bit value will be byteswapped.
2413  */
2414 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2415 {
2416         int ret;
2417
2418         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2419                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2420
2421         offset = tg3_nvram_phys_addr(tp, offset);
2422
2423         if (offset > NVRAM_ADDR_MSK)
2424                 return -EINVAL;
2425
2426         ret = tg3_nvram_lock(tp);
2427         if (ret)
2428                 return ret;
2429
2430         tg3_enable_nvram_access(tp);
2431
2432         tw32(NVRAM_ADDR, offset);
2433         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2434                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2435
2436         if (ret == 0)
2437                 *val = tr32(NVRAM_RDDATA);
2438
2439         tg3_disable_nvram_access(tp);
2440
2441         tg3_nvram_unlock(tp);
2442
2443         return ret;
2444 }
2445
2446 /* Ensures NVRAM data is in bytestream format. */
2447 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2448 {
2449         u32 v;
2450         int res = tg3_nvram_read(tp, offset, &v);
2451         if (!res)
2452                 *val = cpu_to_be32(v);
2453         return res;
2454 }
2455
2456 /* tp->lock is held. */
2457 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2458 {
2459         u32 addr_high, addr_low;
2460         int i;
2461
2462         addr_high = ((tp->dev->dev_addr[0] << 8) |
2463                      tp->dev->dev_addr[1]);
2464         addr_low = ((tp->dev->dev_addr[2] << 24) |
2465                     (tp->dev->dev_addr[3] << 16) |
2466                     (tp->dev->dev_addr[4] <<  8) |
2467                     (tp->dev->dev_addr[5] <<  0));
2468         for (i = 0; i < 4; i++) {
2469                 if (i == 1 && skip_mac_1)
2470                         continue;
2471                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2472                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2473         }
2474
2475         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2476             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2477                 for (i = 0; i < 12; i++) {
2478                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2479                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2480                 }
2481         }
2482
2483         addr_high = (tp->dev->dev_addr[0] +
2484                      tp->dev->dev_addr[1] +
2485                      tp->dev->dev_addr[2] +
2486                      tp->dev->dev_addr[3] +
2487                      tp->dev->dev_addr[4] +
2488                      tp->dev->dev_addr[5]) &
2489                 TX_BACKOFF_SEED_MASK;
2490         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2491 }
2492
2493 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2494 {
2495         u32 misc_host_ctrl;
2496         bool device_should_wake, do_low_power;
2497
2498         /* Make sure register accesses (indirect or otherwise)
2499          * will function correctly.
2500          */
2501         pci_write_config_dword(tp->pdev,
2502                                TG3PCI_MISC_HOST_CTRL,
2503                                tp->misc_host_ctrl);
2504
2505         switch (state) {
2506         case PCI_D0:
2507                 pci_enable_wake(tp->pdev, state, false);
2508                 pci_set_power_state(tp->pdev, PCI_D0);
2509
2510                 /* Switch out of Vaux if it is a NIC */
2511                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2512                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2513
2514                 return 0;
2515
2516         case PCI_D1:
2517         case PCI_D2:
2518         case PCI_D3hot:
2519                 break;
2520
2521         default:
2522                 netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
2523                            state);
2524                 return -EINVAL;
2525         }
2526
2527         /* Restore the CLKREQ setting. */
2528         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2529                 u16 lnkctl;
2530
2531                 pci_read_config_word(tp->pdev,
2532                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2533                                      &lnkctl);
2534                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2535                 pci_write_config_word(tp->pdev,
2536                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2537                                       lnkctl);
2538         }
2539
2540         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2541         tw32(TG3PCI_MISC_HOST_CTRL,
2542              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2543
2544         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2545                              device_may_wakeup(&tp->pdev->dev) &&
2546                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2547
2548         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2549                 do_low_power = false;
2550                 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
2551                     !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2552                         struct phy_device *phydev;
2553                         u32 phyid, advertising;
2554
2555                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2556
2557                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2558
2559                         tp->link_config.orig_speed = phydev->speed;
2560                         tp->link_config.orig_duplex = phydev->duplex;
2561                         tp->link_config.orig_autoneg = phydev->autoneg;
2562                         tp->link_config.orig_advertising = phydev->advertising;
2563
2564                         advertising = ADVERTISED_TP |
2565                                       ADVERTISED_Pause |
2566                                       ADVERTISED_Autoneg |
2567                                       ADVERTISED_10baseT_Half;
2568
2569                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2570                             device_should_wake) {
2571                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2572                                         advertising |=
2573                                                 ADVERTISED_100baseT_Half |
2574                                                 ADVERTISED_100baseT_Full |
2575                                                 ADVERTISED_10baseT_Full;
2576                                 else
2577                                         advertising |= ADVERTISED_10baseT_Full;
2578                         }
2579
2580                         phydev->advertising = advertising;
2581
2582                         phy_start_aneg(phydev);
2583
2584                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2585                         if (phyid != PHY_ID_BCMAC131) {
2586                                 phyid &= PHY_BCM_OUI_MASK;
2587                                 if (phyid == PHY_BCM_OUI_1 ||
2588                                     phyid == PHY_BCM_OUI_2 ||
2589                                     phyid == PHY_BCM_OUI_3)
2590                                         do_low_power = true;
2591                         }
2592                 }
2593         } else {
2594                 do_low_power = true;
2595
2596                 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2597                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2598                         tp->link_config.orig_speed = tp->link_config.speed;
2599                         tp->link_config.orig_duplex = tp->link_config.duplex;
2600                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2601                 }
2602
2603                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
2604                         tp->link_config.speed = SPEED_10;
2605                         tp->link_config.duplex = DUPLEX_HALF;
2606                         tp->link_config.autoneg = AUTONEG_ENABLE;
2607                         tg3_setup_phy(tp, 0);
2608                 }
2609         }
2610
2611         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2612                 u32 val;
2613
2614                 val = tr32(GRC_VCPU_EXT_CTRL);
2615                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2616         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2617                 int i;
2618                 u32 val;
2619
2620                 for (i = 0; i < 200; i++) {
2621                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2622                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2623                                 break;
2624                         msleep(1);
2625                 }
2626         }
2627         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2628                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2629                                                      WOL_DRV_STATE_SHUTDOWN |
2630                                                      WOL_DRV_WOL |
2631                                                      WOL_SET_MAGIC_PKT);
2632
2633         if (device_should_wake) {
2634                 u32 mac_mode;
2635
2636                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
2637                         if (do_low_power) {
2638                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2639                                 udelay(40);
2640                         }
2641
2642                         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
2643                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2644                         else
2645                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2646
2647                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2648                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2649                             ASIC_REV_5700) {
2650                                 u32 speed = (tp->tg3_flags &
2651                                              TG3_FLAG_WOL_SPEED_100MB) ?
2652                                              SPEED_100 : SPEED_10;
2653                                 if (tg3_5700_link_polarity(tp, speed))
2654                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2655                                 else
2656                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2657                         }
2658                 } else {
2659                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2660                 }
2661
2662                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2663                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2664
2665                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2666                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2667                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2668                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2669                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2670                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2671
2672                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2673                         mac_mode |= tp->mac_mode &
2674                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2675                         if (mac_mode & MAC_MODE_APE_TX_EN)
2676                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2677                 }
2678
2679                 tw32_f(MAC_MODE, mac_mode);
2680                 udelay(100);
2681
2682                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2683                 udelay(10);
2684         }
2685
2686         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2687             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2688              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2689                 u32 base_val;
2690
2691                 base_val = tp->pci_clock_ctrl;
2692                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2693                              CLOCK_CTRL_TXCLK_DISABLE);
2694
2695                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2696                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2697         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2698                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2699                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2700                 /* do nothing */
2701         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2702                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2703                 u32 newbits1, newbits2;
2704
2705                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2706                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2707                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2708                                     CLOCK_CTRL_TXCLK_DISABLE |
2709                                     CLOCK_CTRL_ALTCLK);
2710                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2711                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2712                         newbits1 = CLOCK_CTRL_625_CORE;
2713                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2714                 } else {
2715                         newbits1 = CLOCK_CTRL_ALTCLK;
2716                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2717                 }
2718
2719                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2720                             40);
2721
2722                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2723                             40);
2724
2725                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2726                         u32 newbits3;
2727
2728                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2729                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2730                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2731                                             CLOCK_CTRL_TXCLK_DISABLE |
2732                                             CLOCK_CTRL_44MHZ_CORE);
2733                         } else {
2734                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2735                         }
2736
2737                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2738                                     tp->pci_clock_ctrl | newbits3, 40);
2739                 }
2740         }
2741
2742         if (!(device_should_wake) &&
2743             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2744                 tg3_power_down_phy(tp, do_low_power);
2745
2746         tg3_frob_aux_power(tp);
2747
2748         /* Workaround for unstable PLL clock */
2749         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2750             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2751                 u32 val = tr32(0x7d00);
2752
2753                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2754                 tw32(0x7d00, val);
2755                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2756                         int err;
2757
2758                         err = tg3_nvram_lock(tp);
2759                         tg3_halt_cpu(tp, RX_CPU_BASE);
2760                         if (!err)
2761                                 tg3_nvram_unlock(tp);
2762                 }
2763         }
2764
2765         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2766
2767         if (device_should_wake)
2768                 pci_enable_wake(tp->pdev, state, true);
2769
2770         /* Finally, set the new power state. */
2771         pci_set_power_state(tp->pdev, state);
2772
2773         return 0;
2774 }
2775
2776 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2777 {
2778         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2779         case MII_TG3_AUX_STAT_10HALF:
2780                 *speed = SPEED_10;
2781                 *duplex = DUPLEX_HALF;
2782                 break;
2783
2784         case MII_TG3_AUX_STAT_10FULL:
2785                 *speed = SPEED_10;
2786                 *duplex = DUPLEX_FULL;
2787                 break;
2788
2789         case MII_TG3_AUX_STAT_100HALF:
2790                 *speed = SPEED_100;
2791                 *duplex = DUPLEX_HALF;
2792                 break;
2793
2794         case MII_TG3_AUX_STAT_100FULL:
2795                 *speed = SPEED_100;
2796                 *duplex = DUPLEX_FULL;
2797                 break;
2798
2799         case MII_TG3_AUX_STAT_1000HALF:
2800                 *speed = SPEED_1000;
2801                 *duplex = DUPLEX_HALF;
2802                 break;
2803
2804         case MII_TG3_AUX_STAT_1000FULL:
2805                 *speed = SPEED_1000;
2806                 *duplex = DUPLEX_FULL;
2807                 break;
2808
2809         default:
2810                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2811                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2812                                  SPEED_10;
2813                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2814                                   DUPLEX_HALF;
2815                         break;
2816                 }
2817                 *speed = SPEED_INVALID;
2818                 *duplex = DUPLEX_INVALID;
2819                 break;
2820         }
2821 }
2822
2823 static void tg3_phy_copper_begin(struct tg3 *tp)
2824 {
2825         u32 new_adv;
2826         int i;
2827
2828         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2829                 /* Entering low power mode.  Disable gigabit and
2830                  * 100baseT advertisements.
2831                  */
2832                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2833
2834                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2835                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2836                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2837                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2838
2839                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2840         } else if (tp->link_config.speed == SPEED_INVALID) {
2841                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
2842                         tp->link_config.advertising &=
2843                                 ~(ADVERTISED_1000baseT_Half |
2844                                   ADVERTISED_1000baseT_Full);
2845
2846                 new_adv = ADVERTISE_CSMA;
2847                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2848                         new_adv |= ADVERTISE_10HALF;
2849                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2850                         new_adv |= ADVERTISE_10FULL;
2851                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2852                         new_adv |= ADVERTISE_100HALF;
2853                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2854                         new_adv |= ADVERTISE_100FULL;
2855
2856                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2857
2858                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2859
2860                 if (tp->link_config.advertising &
2861                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2862                         new_adv = 0;
2863                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2864                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2865                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2866                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2867                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) &&
2868                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2869                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2870                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2871                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2872                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2873                 } else {
2874                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2875                 }
2876         } else {
2877                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2878                 new_adv |= ADVERTISE_CSMA;
2879
2880                 /* Asking for a specific link mode. */
2881                 if (tp->link_config.speed == SPEED_1000) {
2882                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2883
2884                         if (tp->link_config.duplex == DUPLEX_FULL)
2885                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2886                         else
2887                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2888                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2889                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2890                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2891                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2892                 } else {
2893                         if (tp->link_config.speed == SPEED_100) {
2894                                 if (tp->link_config.duplex == DUPLEX_FULL)
2895                                         new_adv |= ADVERTISE_100FULL;
2896                                 else
2897                                         new_adv |= ADVERTISE_100HALF;
2898                         } else {
2899                                 if (tp->link_config.duplex == DUPLEX_FULL)
2900                                         new_adv |= ADVERTISE_10FULL;
2901                                 else
2902                                         new_adv |= ADVERTISE_10HALF;
2903                         }
2904                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2905
2906                         new_adv = 0;
2907                 }
2908
2909                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2910         }
2911
2912         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2913             tp->link_config.speed != SPEED_INVALID) {
2914                 u32 bmcr, orig_bmcr;
2915
2916                 tp->link_config.active_speed = tp->link_config.speed;
2917                 tp->link_config.active_duplex = tp->link_config.duplex;
2918
2919                 bmcr = 0;
2920                 switch (tp->link_config.speed) {
2921                 default:
2922                 case SPEED_10:
2923                         break;
2924
2925                 case SPEED_100:
2926                         bmcr |= BMCR_SPEED100;
2927                         break;
2928
2929                 case SPEED_1000:
2930                         bmcr |= TG3_BMCR_SPEED1000;
2931                         break;
2932                 }
2933
2934                 if (tp->link_config.duplex == DUPLEX_FULL)
2935                         bmcr |= BMCR_FULLDPLX;
2936
2937                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2938                     (bmcr != orig_bmcr)) {
2939                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2940                         for (i = 0; i < 1500; i++) {
2941                                 u32 tmp;
2942
2943                                 udelay(10);
2944                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2945                                     tg3_readphy(tp, MII_BMSR, &tmp))
2946                                         continue;
2947                                 if (!(tmp & BMSR_LSTATUS)) {
2948                                         udelay(40);
2949                                         break;
2950                                 }
2951                         }
2952                         tg3_writephy(tp, MII_BMCR, bmcr);
2953                         udelay(40);
2954                 }
2955         } else {
2956                 tg3_writephy(tp, MII_BMCR,
2957                              BMCR_ANENABLE | BMCR_ANRESTART);
2958         }
2959 }
2960
2961 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2962 {
2963         int err;
2964
2965         /* Turn off tap power management. */
2966         /* Set Extended packet length bit */
2967         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2968
2969         err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
2970         err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
2971         err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
2972         err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
2973         err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
2974
2975         udelay(40);
2976
2977         return err;
2978 }
2979
2980 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2981 {
2982         u32 adv_reg, all_mask = 0;
2983
2984         if (mask & ADVERTISED_10baseT_Half)
2985                 all_mask |= ADVERTISE_10HALF;
2986         if (mask & ADVERTISED_10baseT_Full)
2987                 all_mask |= ADVERTISE_10FULL;
2988         if (mask & ADVERTISED_100baseT_Half)
2989                 all_mask |= ADVERTISE_100HALF;
2990         if (mask & ADVERTISED_100baseT_Full)
2991                 all_mask |= ADVERTISE_100FULL;
2992
2993         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2994                 return 0;
2995
2996         if ((adv_reg & all_mask) != all_mask)
2997                 return 0;
2998         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
2999                 u32 tg3_ctrl;
3000
3001                 all_mask = 0;
3002                 if (mask & ADVERTISED_1000baseT_Half)
3003                         all_mask |= ADVERTISE_1000HALF;
3004                 if (mask & ADVERTISED_1000baseT_Full)
3005                         all_mask |= ADVERTISE_1000FULL;
3006
3007                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3008                         return 0;
3009
3010                 if ((tg3_ctrl & all_mask) != all_mask)
3011                         return 0;
3012         }
3013         return 1;
3014 }
3015
3016 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3017 {
3018         u32 curadv, reqadv;
3019
3020         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3021                 return 1;
3022
3023         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3024         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3025
3026         if (tp->link_config.active_duplex == DUPLEX_FULL) {
3027                 if (curadv != reqadv)
3028                         return 0;
3029
3030                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3031                         tg3_readphy(tp, MII_LPA, rmtadv);
3032         } else {
3033                 /* Reprogram the advertisement register, even if it
3034                  * does not affect the current link.  If the link
3035                  * gets renegotiated in the future, we can save an
3036                  * additional renegotiation cycle by advertising
3037                  * it correctly in the first place.
3038                  */
3039                 if (curadv != reqadv) {
3040                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3041                                      ADVERTISE_PAUSE_ASYM);
3042                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3043                 }
3044         }
3045
3046         return 1;
3047 }
3048
3049 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3050 {
3051         int current_link_up;
3052         u32 bmsr, val;
3053         u32 lcl_adv, rmt_adv;
3054         u16 current_speed;
3055         u8 current_duplex;
3056         int i, err;
3057
3058         tw32(MAC_EVENT, 0);
3059
3060         tw32_f(MAC_STATUS,
3061              (MAC_STATUS_SYNC_CHANGED |
3062               MAC_STATUS_CFG_CHANGED |
3063               MAC_STATUS_MI_COMPLETION |
3064               MAC_STATUS_LNKSTATE_CHANGED));
3065         udelay(40);
3066
3067         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3068                 tw32_f(MAC_MI_MODE,
3069                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3070                 udelay(80);
3071         }
3072
3073         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3074
3075         /* Some third-party PHYs need to be reset on link going
3076          * down.
3077          */
3078         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3079              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3080              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3081             netif_carrier_ok(tp->dev)) {
3082                 tg3_readphy(tp, MII_BMSR, &bmsr);
3083                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3084                     !(bmsr & BMSR_LSTATUS))
3085                         force_reset = 1;
3086         }
3087         if (force_reset)
3088                 tg3_phy_reset(tp);
3089
3090         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3091                 tg3_readphy(tp, MII_BMSR, &bmsr);
3092                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3093                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3094                         bmsr = 0;
3095
3096                 if (!(bmsr & BMSR_LSTATUS)) {
3097                         err = tg3_init_5401phy_dsp(tp);
3098                         if (err)
3099                                 return err;
3100
3101                         tg3_readphy(tp, MII_BMSR, &bmsr);
3102                         for (i = 0; i < 1000; i++) {
3103                                 udelay(10);
3104                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3105                                     (bmsr & BMSR_LSTATUS)) {
3106                                         udelay(40);
3107                                         break;
3108                                 }
3109                         }
3110
3111                         if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3112                             TG3_PHY_REV_BCM5401_B0 &&
3113                             !(bmsr & BMSR_LSTATUS) &&
3114                             tp->link_config.active_speed == SPEED_1000) {
3115                                 err = tg3_phy_reset(tp);
3116                                 if (!err)
3117                                         err = tg3_init_5401phy_dsp(tp);
3118                                 if (err)
3119                                         return err;
3120                         }
3121                 }
3122         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3123                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3124                 /* 5701 {A0,B0} CRC bug workaround */
3125                 tg3_writephy(tp, 0x15, 0x0a75);
3126                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3127                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3128                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3129         }
3130
3131         /* Clear pending interrupts... */
3132         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3133         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3134
3135         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3136                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3137         else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3138                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3139
3140         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3141             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3142                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3143                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3144                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3145                 else
3146                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3147         }
3148
3149         current_link_up = 0;
3150         current_speed = SPEED_INVALID;
3151         current_duplex = DUPLEX_INVALID;
3152
3153         if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3154                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3155                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3156                 if (!(val & (1 << 10))) {
3157                         val |= (1 << 10);
3158                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3159                         goto relink;
3160                 }
3161         }
3162
3163         bmsr = 0;
3164         for (i = 0; i < 100; i++) {
3165                 tg3_readphy(tp, MII_BMSR, &bmsr);
3166                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3167                     (bmsr & BMSR_LSTATUS))
3168                         break;
3169                 udelay(40);
3170         }
3171
3172         if (bmsr & BMSR_LSTATUS) {
3173                 u32 aux_stat, bmcr;
3174
3175                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3176                 for (i = 0; i < 2000; i++) {
3177                         udelay(10);
3178                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3179                             aux_stat)
3180                                 break;
3181                 }
3182
3183                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3184                                              &current_speed,
3185                                              &current_duplex);
3186
3187                 bmcr = 0;
3188                 for (i = 0; i < 200; i++) {
3189                         tg3_readphy(tp, MII_BMCR, &bmcr);
3190                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3191                                 continue;
3192                         if (bmcr && bmcr != 0x7fff)
3193                                 break;
3194                         udelay(10);
3195                 }
3196
3197                 lcl_adv = 0;
3198                 rmt_adv = 0;
3199
3200                 tp->link_config.active_speed = current_speed;
3201                 tp->link_config.active_duplex = current_duplex;
3202
3203                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3204                         if ((bmcr & BMCR_ANENABLE) &&
3205                             tg3_copper_is_advertising_all(tp,
3206                                                 tp->link_config.advertising)) {
3207                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3208                                                                   &rmt_adv))
3209                                         current_link_up = 1;
3210                         }
3211                 } else {
3212                         if (!(bmcr & BMCR_ANENABLE) &&
3213                             tp->link_config.speed == current_speed &&
3214                             tp->link_config.duplex == current_duplex &&
3215                             tp->link_config.flowctrl ==
3216                             tp->link_config.active_flowctrl) {
3217                                 current_link_up = 1;
3218                         }
3219                 }
3220
3221                 if (current_link_up == 1 &&
3222                     tp->link_config.active_duplex == DUPLEX_FULL)
3223                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3224         }
3225
3226 relink:
3227         if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3228                 tg3_phy_copper_begin(tp);
3229
3230                 tg3_readphy(tp, MII_BMSR, &bmsr);
3231                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3232                     (bmsr & BMSR_LSTATUS))
3233                         current_link_up = 1;
3234         }
3235
3236         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3237         if (current_link_up == 1) {
3238                 if (tp->link_config.active_speed == SPEED_100 ||
3239                     tp->link_config.active_speed == SPEED_10)
3240                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3241                 else
3242                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3243         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
3244                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3245         else
3246                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3247
3248         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3249         if (tp->link_config.active_duplex == DUPLEX_HALF)
3250                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3251
3252         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3253                 if (current_link_up == 1 &&
3254                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3255                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3256                 else
3257                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3258         }
3259
3260         /* ??? Without this setting Netgear GA302T PHY does not
3261          * ??? send/receive packets...
3262          */
3263         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3264             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3265                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3266                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3267                 udelay(80);
3268         }
3269
3270         tw32_f(MAC_MODE, tp->mac_mode);
3271         udelay(40);
3272
3273         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3274                 /* Polled via timer. */
3275                 tw32_f(MAC_EVENT, 0);
3276         } else {
3277                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3278         }
3279         udelay(40);
3280
3281         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3282             current_link_up == 1 &&
3283             tp->link_config.active_speed == SPEED_1000 &&
3284             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3285              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3286                 udelay(120);
3287                 tw32_f(MAC_STATUS,
3288                      (MAC_STATUS_SYNC_CHANGED |
3289                       MAC_STATUS_CFG_CHANGED));
3290                 udelay(40);
3291                 tg3_write_mem(tp,
3292                               NIC_SRAM_FIRMWARE_MBOX,
3293                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3294         }
3295
3296         /* Prevent send BD corruption. */
3297         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3298                 u16 oldlnkctl, newlnkctl;
3299
3300                 pci_read_config_word(tp->pdev,
3301                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3302                                      &oldlnkctl);
3303                 if (tp->link_config.active_speed == SPEED_100 ||
3304                     tp->link_config.active_speed == SPEED_10)
3305                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3306                 else
3307                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3308                 if (newlnkctl != oldlnkctl)
3309                         pci_write_config_word(tp->pdev,
3310                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3311                                               newlnkctl);
3312         }
3313
3314         if (current_link_up != netif_carrier_ok(tp->dev)) {
3315                 if (current_link_up)
3316                         netif_carrier_on(tp->dev);
3317                 else
3318                         netif_carrier_off(tp->dev);
3319                 tg3_link_report(tp);
3320         }
3321
3322         return 0;
3323 }
3324
3325 struct tg3_fiber_aneginfo {
3326         int state;
3327 #define ANEG_STATE_UNKNOWN              0
3328 #define ANEG_STATE_AN_ENABLE            1
3329 #define ANEG_STATE_RESTART_INIT         2
3330 #define ANEG_STATE_RESTART              3
3331 #define ANEG_STATE_DISABLE_LINK_OK      4
3332 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3333 #define ANEG_STATE_ABILITY_DETECT       6
3334 #define ANEG_STATE_ACK_DETECT_INIT      7
3335 #define ANEG_STATE_ACK_DETECT           8
3336 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3337 #define ANEG_STATE_COMPLETE_ACK         10
3338 #define ANEG_STATE_IDLE_DETECT_INIT     11
3339 #define ANEG_STATE_IDLE_DETECT          12
3340 #define ANEG_STATE_LINK_OK              13
3341 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3342 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3343
3344         u32 flags;
3345 #define MR_AN_ENABLE            0x00000001
3346 #define MR_RESTART_AN           0x00000002
3347 #define MR_AN_COMPLETE          0x00000004
3348 #define MR_PAGE_RX              0x00000008
3349 #define MR_NP_LOADED            0x00000010
3350 #define MR_TOGGLE_TX            0x00000020
3351 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3352 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3353 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3354 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3355 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3356 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3357 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3358 #define MR_TOGGLE_RX            0x00002000
3359 #define MR_NP_RX                0x00004000
3360
3361 #define MR_LINK_OK              0x80000000
3362
3363         unsigned long link_time, cur_time;
3364
3365         u32 ability_match_cfg;
3366         int ability_match_count;
3367
3368         char ability_match, idle_match, ack_match;
3369
3370         u32 txconfig, rxconfig;
3371 #define ANEG_CFG_NP             0x00000080
3372 #define ANEG_CFG_ACK            0x00000040
3373 #define ANEG_CFG_RF2            0x00000020
3374 #define ANEG_CFG_RF1            0x00000010
3375 #define ANEG_CFG_PS2            0x00000001
3376 #define ANEG_CFG_PS1            0x00008000
3377 #define ANEG_CFG_HD             0x00004000
3378 #define ANEG_CFG_FD             0x00002000
3379 #define ANEG_CFG_INVAL          0x00001f06
3380
3381 };
3382 #define ANEG_OK         0
3383 #define ANEG_DONE       1
3384 #define ANEG_TIMER_ENAB 2
3385 #define ANEG_FAILED     -1
3386
3387 #define ANEG_STATE_SETTLE_TIME  10000
3388
3389 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3390                                    struct tg3_fiber_aneginfo *ap)
3391 {
3392         u16 flowctrl;
3393         unsigned long delta;
3394         u32 rx_cfg_reg;
3395         int ret;
3396
3397         if (ap->state == ANEG_STATE_UNKNOWN) {
3398                 ap->rxconfig = 0;
3399                 ap->link_time = 0;
3400                 ap->cur_time = 0;
3401                 ap->ability_match_cfg = 0;
3402                 ap->ability_match_count = 0;
3403                 ap->ability_match = 0;
3404                 ap->idle_match = 0;
3405                 ap->ack_match = 0;
3406         }
3407         ap->cur_time++;
3408
3409         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3410                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3411
3412                 if (rx_cfg_reg != ap->ability_match_cfg) {
3413                         ap->ability_match_cfg = rx_cfg_reg;
3414                         ap->ability_match = 0;
3415                         ap->ability_match_count = 0;
3416                 } else {
3417                         if (++ap->ability_match_count > 1) {
3418                                 ap->ability_match = 1;
3419                                 ap->ability_match_cfg = rx_cfg_reg;
3420                         }
3421                 }
3422                 if (rx_cfg_reg & ANEG_CFG_ACK)
3423                         ap->ack_match = 1;
3424                 else
3425                         ap->ack_match = 0;
3426
3427                 ap->idle_match = 0;
3428         } else {
3429                 ap->idle_match = 1;
3430                 ap->ability_match_cfg = 0;
3431                 ap->ability_match_count = 0;
3432                 ap->ability_match = 0;
3433                 ap->ack_match = 0;
3434
3435                 rx_cfg_reg = 0;
3436         }
3437
3438         ap->rxconfig = rx_cfg_reg;
3439         ret = ANEG_OK;
3440
3441         switch (ap->state) {
3442         case ANEG_STATE_UNKNOWN:
3443                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3444                         ap->state = ANEG_STATE_AN_ENABLE;
3445
3446                 /* fallthru */
3447         case ANEG_STATE_AN_ENABLE:
3448                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3449                 if (ap->flags & MR_AN_ENABLE) {
3450                         ap->link_time = 0;
3451                         ap->cur_time = 0;
3452                         ap->ability_match_cfg = 0;
3453                         ap->ability_match_count = 0;
3454                         ap->ability_match = 0;
3455                         ap->idle_match = 0;
3456                         ap->ack_match = 0;
3457
3458                         ap->state = ANEG_STATE_RESTART_INIT;
3459                 } else {
3460                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3461                 }
3462                 break;
3463
3464         case ANEG_STATE_RESTART_INIT:
3465                 ap->link_time = ap->cur_time;
3466                 ap->flags &= ~(MR_NP_LOADED);
3467                 ap->txconfig = 0;
3468                 tw32(MAC_TX_AUTO_NEG, 0);
3469                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3470                 tw32_f(MAC_MODE, tp->mac_mode);
3471                 udelay(40);
3472
3473                 ret = ANEG_TIMER_ENAB;
3474                 ap->state = ANEG_STATE_RESTART;
3475
3476                 /* fallthru */
3477         case ANEG_STATE_RESTART:
3478                 delta = ap->cur_time - ap->link_time;
3479                 if (delta > ANEG_STATE_SETTLE_TIME)
3480                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3481                 else
3482                         ret = ANEG_TIMER_ENAB;
3483                 break;
3484
3485         case ANEG_STATE_DISABLE_LINK_OK:
3486                 ret = ANEG_DONE;
3487                 break;
3488
3489         case ANEG_STATE_ABILITY_DETECT_INIT:
3490                 ap->flags &= ~(MR_TOGGLE_TX);
3491                 ap->txconfig = ANEG_CFG_FD;
3492                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3493                 if (flowctrl & ADVERTISE_1000XPAUSE)
3494                         ap->txconfig |= ANEG_CFG_PS1;
3495                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3496                         ap->txconfig |= ANEG_CFG_PS2;
3497                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3498                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3499                 tw32_f(MAC_MODE, tp->mac_mode);
3500                 udelay(40);
3501
3502                 ap->state = ANEG_STATE_ABILITY_DETECT;
3503                 break;
3504
3505         case ANEG_STATE_ABILITY_DETECT:
3506                 if (ap->ability_match != 0 && ap->rxconfig != 0)
3507                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3508                 break;
3509
3510         case ANEG_STATE_ACK_DETECT_INIT:
3511                 ap->txconfig |= ANEG_CFG_ACK;
3512                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3513                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3514                 tw32_f(MAC_MODE, tp->mac_mode);
3515                 udelay(40);
3516
3517                 ap->state = ANEG_STATE_ACK_DETECT;
3518
3519                 /* fallthru */
3520         case ANEG_STATE_ACK_DETECT:
3521                 if (ap->ack_match != 0) {
3522                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3523                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3524                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3525                         } else {
3526                                 ap->state = ANEG_STATE_AN_ENABLE;
3527                         }
3528                 } else if (ap->ability_match != 0 &&
3529                            ap->rxconfig == 0) {
3530                         ap->state = ANEG_STATE_AN_ENABLE;
3531                 }
3532                 break;
3533
3534         case ANEG_STATE_COMPLETE_ACK_INIT:
3535                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3536                         ret = ANEG_FAILED;
3537                         break;
3538                 }
3539                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3540                                MR_LP_ADV_HALF_DUPLEX |
3541                                MR_LP_ADV_SYM_PAUSE |
3542                                MR_LP_ADV_ASYM_PAUSE |
3543                                MR_LP_ADV_REMOTE_FAULT1 |
3544                                MR_LP_ADV_REMOTE_FAULT2 |
3545                                MR_LP_ADV_NEXT_PAGE |
3546                                MR_TOGGLE_RX |
3547                                MR_NP_RX);
3548                 if (ap->rxconfig & ANEG_CFG_FD)
3549                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3550                 if (ap->rxconfig & ANEG_CFG_HD)
3551                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3552                 if (ap->rxconfig & ANEG_CFG_PS1)
3553                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3554                 if (ap->rxconfig & ANEG_CFG_PS2)
3555                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3556                 if (ap->rxconfig & ANEG_CFG_RF1)
3557                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3558                 if (ap->rxconfig & ANEG_CFG_RF2)
3559                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3560                 if (ap->rxconfig & ANEG_CFG_NP)
3561                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3562
3563                 ap->link_time = ap->cur_time;
3564
3565                 ap->flags ^= (MR_TOGGLE_TX);
3566                 if (ap->rxconfig & 0x0008)
3567                         ap->flags |= MR_TOGGLE_RX;
3568                 if (ap->rxconfig & ANEG_CFG_NP)
3569                         ap->flags |= MR_NP_RX;
3570                 ap->flags |= MR_PAGE_RX;
3571
3572                 ap->state = ANEG_STATE_COMPLETE_ACK;
3573                 ret = ANEG_TIMER_ENAB;
3574                 break;
3575
3576         case ANEG_STATE_COMPLETE_ACK:
3577                 if (ap->ability_match != 0 &&
3578                     ap->rxconfig == 0) {
3579                         ap->state = ANEG_STATE_AN_ENABLE;
3580                         break;
3581                 }
3582                 delta = ap->cur_time - ap->link_time;
3583                 if (delta > ANEG_STATE_SETTLE_TIME) {
3584                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3585                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3586                         } else {
3587                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3588                                     !(ap->flags & MR_NP_RX)) {
3589                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3590                                 } else {
3591                                         ret = ANEG_FAILED;
3592                                 }
3593                         }
3594                 }
3595                 break;
3596
3597         case ANEG_STATE_IDLE_DETECT_INIT:
3598                 ap->link_time = ap->cur_time;
3599                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3600                 tw32_f(MAC_MODE, tp->mac_mode);
3601                 udelay(40);
3602
3603                 ap->state = ANEG_STATE_IDLE_DETECT;
3604                 ret = ANEG_TIMER_ENAB;
3605                 break;
3606
3607         case ANEG_STATE_IDLE_DETECT:
3608                 if (ap->ability_match != 0 &&
3609                     ap->rxconfig == 0) {
3610                         ap->state = ANEG_STATE_AN_ENABLE;
3611                         break;
3612                 }
3613                 delta = ap->cur_time - ap->link_time;
3614                 if (delta > ANEG_STATE_SETTLE_TIME) {
3615                         /* XXX another gem from the Broadcom driver :( */
3616                         ap->state = ANEG_STATE_LINK_OK;
3617                 }
3618                 break;
3619
3620         case ANEG_STATE_LINK_OK:
3621                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3622                 ret = ANEG_DONE;
3623                 break;
3624
3625         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3626                 /* ??? unimplemented */
3627                 break;
3628
3629         case ANEG_STATE_NEXT_PAGE_WAIT:
3630                 /* ??? unimplemented */
3631                 break;
3632
3633         default:
3634                 ret = ANEG_FAILED;
3635                 break;
3636         }
3637
3638         return ret;
3639 }
3640
3641 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3642 {
3643         int res = 0;
3644         struct tg3_fiber_aneginfo aninfo;
3645         int status = ANEG_FAILED;
3646         unsigned int tick;
3647         u32 tmp;
3648
3649         tw32_f(MAC_TX_AUTO_NEG, 0);
3650
3651         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3652         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3653         udelay(40);
3654
3655         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3656         udelay(40);
3657
3658         memset(&aninfo, 0, sizeof(aninfo));
3659         aninfo.flags |= MR_AN_ENABLE;
3660         aninfo.state = ANEG_STATE_UNKNOWN;
3661         aninfo.cur_time = 0;
3662         tick = 0;
3663         while (++tick < 195000) {
3664                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3665                 if (status == ANEG_DONE || status == ANEG_FAILED)
3666                         break;
3667
3668                 udelay(1);
3669         }
3670
3671         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3672         tw32_f(MAC_MODE, tp->mac_mode);
3673         udelay(40);
3674
3675         *txflags = aninfo.txconfig;
3676         *rxflags = aninfo.flags;
3677
3678         if (status == ANEG_DONE &&
3679             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3680                              MR_LP_ADV_FULL_DUPLEX)))
3681                 res = 1;
3682
3683         return res;
3684 }
3685
3686 static void tg3_init_bcm8002(struct tg3 *tp)
3687 {
3688         u32 mac_status = tr32(MAC_STATUS);
3689         int i;
3690
3691         /* Reset when initting first time or we have a link. */
3692         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3693             !(mac_status & MAC_STATUS_PCS_SYNCED))
3694                 return;
3695
3696         /* Set PLL lock range. */
3697         tg3_writephy(tp, 0x16, 0x8007);
3698
3699         /* SW reset */
3700         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3701
3702         /* Wait for reset to complete. */
3703         /* XXX schedule_timeout() ... */
3704         for (i = 0; i < 500; i++)
3705                 udelay(10);
3706
3707         /* Config mode; select PMA/Ch 1 regs. */
3708         tg3_writephy(tp, 0x10, 0x8411);
3709
3710         /* Enable auto-lock and comdet, select txclk for tx. */
3711         tg3_writephy(tp, 0x11, 0x0a10);
3712
3713         tg3_writephy(tp, 0x18, 0x00a0);
3714         tg3_writephy(tp, 0x16, 0x41ff);
3715
3716         /* Assert and deassert POR. */
3717         tg3_writephy(tp, 0x13, 0x0400);
3718         udelay(40);
3719         tg3_writephy(tp, 0x13, 0x0000);
3720
3721         tg3_writephy(tp, 0x11, 0x0a50);
3722         udelay(40);
3723         tg3_writephy(tp, 0x11, 0x0a10);
3724
3725         /* Wait for signal to stabilize */
3726         /* XXX schedule_timeout() ... */
3727         for (i = 0; i < 15000; i++)
3728                 udelay(10);
3729
3730         /* Deselect the channel register so we can read the PHYID
3731          * later.
3732          */
3733         tg3_writephy(tp, 0x10, 0x8011);
3734 }
3735
3736 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3737 {
3738         u16 flowctrl;
3739         u32 sg_dig_ctrl, sg_dig_status;
3740         u32 serdes_cfg, expected_sg_dig_ctrl;
3741         int workaround, port_a;
3742         int current_link_up;
3743
3744         serdes_cfg = 0;
3745         expected_sg_dig_ctrl = 0;
3746         workaround = 0;
3747         port_a = 1;
3748         current_link_up = 0;
3749
3750         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3751             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3752                 workaround = 1;
3753                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3754                         port_a = 0;
3755
3756                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3757                 /* preserve bits 20-23 for voltage regulator */
3758                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3759         }
3760
3761         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3762
3763         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3764                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3765                         if (workaround) {
3766                                 u32 val = serdes_cfg;
3767
3768                                 if (port_a)
3769                                         val |= 0xc010000;
3770                                 else
3771                                         val |= 0x4010000;
3772                                 tw32_f(MAC_SERDES_CFG, val);
3773                         }
3774
3775                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3776                 }
3777                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3778                         tg3_setup_flow_control(tp, 0, 0);
3779                         current_link_up = 1;
3780                 }
3781                 goto out;
3782         }
3783
3784         /* Want auto-negotiation.  */
3785         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3786
3787         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3788         if (flowctrl & ADVERTISE_1000XPAUSE)
3789                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3790         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3791                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3792
3793         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3794                 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3795                     tp->serdes_counter &&
3796                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3797                                     MAC_STATUS_RCVD_CFG)) ==
3798                      MAC_STATUS_PCS_SYNCED)) {
3799                         tp->serdes_counter--;
3800                         current_link_up = 1;
3801                         goto out;
3802                 }
3803 restart_autoneg:
3804                 if (workaround)
3805                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3806                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3807                 udelay(5);
3808                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3809
3810                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3811                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3812         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3813                                  MAC_STATUS_SIGNAL_DET)) {
3814                 sg_dig_status = tr32(SG_DIG_STATUS);
3815                 mac_status = tr32(MAC_STATUS);
3816
3817                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3818                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3819                         u32 local_adv = 0, remote_adv = 0;
3820
3821                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3822                                 local_adv |= ADVERTISE_1000XPAUSE;
3823                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3824                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3825
3826                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3827                                 remote_adv |= LPA_1000XPAUSE;
3828                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3829                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3830
3831                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3832                         current_link_up = 1;
3833                         tp->serdes_counter = 0;
3834                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3835                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3836                         if (tp->serdes_counter)
3837                                 tp->serdes_counter--;
3838                         else {
3839                                 if (workaround) {
3840                                         u32 val = serdes_cfg;
3841
3842                                         if (port_a)
3843                                                 val |= 0xc010000;
3844                                         else
3845                                                 val |= 0x4010000;
3846
3847                                         tw32_f(MAC_SERDES_CFG, val);
3848                                 }
3849
3850                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3851                                 udelay(40);
3852
3853                                 /* Link parallel detection - link is up */
3854                                 /* only if we have PCS_SYNC and not */
3855                                 /* receiving config code words */
3856                                 mac_status = tr32(MAC_STATUS);
3857                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3858                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3859                                         tg3_setup_flow_control(tp, 0, 0);
3860                                         current_link_up = 1;
3861                                         tp->phy_flags |=
3862                                                 TG3_PHYFLG_PARALLEL_DETECT;
3863                                         tp->serdes_counter =
3864                                                 SERDES_PARALLEL_DET_TIMEOUT;
3865                                 } else
3866                                         goto restart_autoneg;
3867                         }
3868                 }
3869         } else {
3870                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3871                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3872         }
3873
3874 out:
3875         return current_link_up;
3876 }
3877
3878 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3879 {
3880         int current_link_up = 0;
3881
3882         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3883                 goto out;
3884
3885         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3886                 u32 txflags, rxflags;
3887                 int i;
3888
3889                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3890                         u32 local_adv = 0, remote_adv = 0;
3891
3892                         if (txflags & ANEG_CFG_PS1)
3893                                 local_adv |= ADVERTISE_1000XPAUSE;
3894                         if (txflags & ANEG_CFG_PS2)
3895                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3896
3897                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3898                                 remote_adv |= LPA_1000XPAUSE;
3899                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3900                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3901
3902                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3903
3904                         current_link_up = 1;
3905                 }
3906                 for (i = 0; i < 30; i++) {
3907                         udelay(20);
3908                         tw32_f(MAC_STATUS,
3909                                (MAC_STATUS_SYNC_CHANGED |
3910                                 MAC_STATUS_CFG_CHANGED));
3911                         udelay(40);
3912                         if ((tr32(MAC_STATUS) &
3913                              (MAC_STATUS_SYNC_CHANGED |
3914                               MAC_STATUS_CFG_CHANGED)) == 0)
3915                                 break;
3916                 }
3917
3918                 mac_status = tr32(MAC_STATUS);
3919                 if (current_link_up == 0 &&
3920                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3921                     !(mac_status & MAC_STATUS_RCVD_CFG))
3922                         current_link_up = 1;
3923         } else {
3924                 tg3_setup_flow_control(tp, 0, 0);
3925
3926                 /* Forcing 1000FD link up. */
3927                 current_link_up = 1;
3928
3929                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3930                 udelay(40);
3931
3932                 tw32_f(MAC_MODE, tp->mac_mode);
3933                 udelay(40);
3934         }
3935
3936 out:
3937         return current_link_up;
3938 }
3939
3940 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3941 {
3942         u32 orig_pause_cfg;
3943         u16 orig_active_speed;
3944         u8 orig_active_duplex;
3945         u32 mac_status;
3946         int current_link_up;
3947         int i;
3948
3949         orig_pause_cfg = tp->link_config.active_flowctrl;
3950         orig_active_speed = tp->link_config.active_speed;
3951         orig_active_duplex = tp->link_config.active_duplex;
3952
3953         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3954             netif_carrier_ok(tp->dev) &&
3955             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3956                 mac_status = tr32(MAC_STATUS);
3957                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3958                                MAC_STATUS_SIGNAL_DET |
3959                                MAC_STATUS_CFG_CHANGED |
3960                                MAC_STATUS_RCVD_CFG);
3961                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3962                                    MAC_STATUS_SIGNAL_DET)) {
3963                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3964                                             MAC_STATUS_CFG_CHANGED));
3965                         return 0;
3966                 }
3967         }
3968
3969         tw32_f(MAC_TX_AUTO_NEG, 0);
3970
3971         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3972         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3973         tw32_f(MAC_MODE, tp->mac_mode);
3974         udelay(40);
3975
3976         if (tp->phy_id == TG3_PHY_ID_BCM8002)
3977                 tg3_init_bcm8002(tp);
3978
3979         /* Enable link change event even when serdes polling.  */
3980         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3981         udelay(40);
3982
3983         current_link_up = 0;
3984         mac_status = tr32(MAC_STATUS);
3985
3986         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3987                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3988         else
3989                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3990
3991         tp->napi[0].hw_status->status =
3992                 (SD_STATUS_UPDATED |
3993                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3994
3995         for (i = 0; i < 100; i++) {
3996                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3997                                     MAC_STATUS_CFG_CHANGED));
3998                 udelay(5);
3999                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4000                                          MAC_STATUS_CFG_CHANGED |
4001                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4002                         break;
4003         }
4004
4005         mac_status = tr32(MAC_STATUS);
4006         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4007                 current_link_up = 0;
4008                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4009                     tp->serdes_counter == 0) {
4010                         tw32_f(MAC_MODE, (tp->mac_mode |
4011                                           MAC_MODE_SEND_CONFIGS));
4012                         udelay(1);
4013                         tw32_f(MAC_MODE, tp->mac_mode);
4014                 }
4015         }
4016
4017         if (current_link_up == 1) {
4018                 tp->link_config.active_speed = SPEED_1000;
4019                 tp->link_config.active_duplex = DUPLEX_FULL;
4020                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4021                                     LED_CTRL_LNKLED_OVERRIDE |
4022                                     LED_CTRL_1000MBPS_ON));
4023         } else {
4024                 tp->link_config.active_speed = SPEED_INVALID;
4025                 tp->link_config.active_duplex = DUPLEX_INVALID;
4026                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4027                                     LED_CTRL_LNKLED_OVERRIDE |
4028                                     LED_CTRL_TRAFFIC_OVERRIDE));
4029         }
4030
4031         if (current_link_up != netif_carrier_ok(tp->dev)) {
4032                 if (current_link_up)
4033                         netif_carrier_on(tp->dev);
4034                 else
4035                         netif_carrier_off(tp->dev);
4036                 tg3_link_report(tp);
4037         } else {
4038                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4039                 if (orig_pause_cfg != now_pause_cfg ||
4040                     orig_active_speed != tp->link_config.active_speed ||
4041                     orig_active_duplex != tp->link_config.active_duplex)
4042                         tg3_link_report(tp);
4043         }
4044
4045         return 0;
4046 }
4047
4048 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4049 {
4050         int current_link_up, err = 0;
4051         u32 bmsr, bmcr;
4052         u16 current_speed;
4053         u8 current_duplex;
4054         u32 local_adv, remote_adv;
4055
4056         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4057         tw32_f(MAC_MODE, tp->mac_mode);
4058         udelay(40);
4059
4060         tw32(MAC_EVENT, 0);
4061
4062         tw32_f(MAC_STATUS,
4063              (MAC_STATUS_SYNC_CHANGED |
4064               MAC_STATUS_CFG_CHANGED |
4065               MAC_STATUS_MI_COMPLETION |
4066               MAC_STATUS_LNKSTATE_CHANGED));
4067         udelay(40);
4068
4069         if (force_reset)
4070                 tg3_phy_reset(tp);
4071
4072         current_link_up = 0;
4073         current_speed = SPEED_INVALID;
4074         current_duplex = DUPLEX_INVALID;
4075
4076         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4077         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4078         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4079                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4080                         bmsr |= BMSR_LSTATUS;
4081                 else
4082                         bmsr &= ~BMSR_LSTATUS;
4083         }
4084
4085         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4086
4087         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4088             (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4089                 /* do nothing, just check for link up at the end */
4090         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4091                 u32 adv, new_adv;
4092
4093                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4094                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4095                                   ADVERTISE_1000XPAUSE |
4096                                   ADVERTISE_1000XPSE_ASYM |
4097                                   ADVERTISE_SLCT);
4098
4099                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4100
4101                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4102                         new_adv |= ADVERTISE_1000XHALF;
4103                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4104                         new_adv |= ADVERTISE_1000XFULL;
4105
4106                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4107                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4108                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4109                         tg3_writephy(tp, MII_BMCR, bmcr);
4110
4111                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4112                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4113                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4114
4115                         return err;
4116                 }
4117         } else {
4118                 u32 new_bmcr;
4119
4120                 bmcr &= ~BMCR_SPEED1000;
4121                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4122
4123                 if (tp->link_config.duplex == DUPLEX_FULL)
4124                         new_bmcr |= BMCR_FULLDPLX;
4125
4126                 if (new_bmcr != bmcr) {
4127                         /* BMCR_SPEED1000 is a reserved bit that needs
4128                          * to be set on write.
4129                          */
4130                         new_bmcr |= BMCR_SPEED1000;
4131
4132                         /* Force a linkdown */
4133                         if (netif_carrier_ok(tp->dev)) {
4134                                 u32 adv;
4135
4136                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4137                                 adv &= ~(ADVERTISE_1000XFULL |
4138                                          ADVERTISE_1000XHALF |
4139                                          ADVERTISE_SLCT);
4140                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4141                                 tg3_writephy(tp, MII_BMCR, bmcr |
4142                                                            BMCR_ANRESTART |
4143                                                            BMCR_ANENABLE);
4144                                 udelay(10);
4145                                 netif_carrier_off(tp->dev);
4146                         }
4147                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4148                         bmcr = new_bmcr;
4149                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4150                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4151                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4152                             ASIC_REV_5714) {
4153                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4154                                         bmsr |= BMSR_LSTATUS;
4155                                 else
4156                                         bmsr &= ~BMSR_LSTATUS;
4157                         }
4158                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4159                 }
4160         }
4161
4162         if (bmsr & BMSR_LSTATUS) {
4163                 current_speed = SPEED_1000;
4164                 current_link_up = 1;
4165                 if (bmcr & BMCR_FULLDPLX)
4166                         current_duplex = DUPLEX_FULL;
4167                 else
4168                         current_duplex = DUPLEX_HALF;
4169
4170                 local_adv = 0;
4171                 remote_adv = 0;
4172
4173                 if (bmcr & BMCR_ANENABLE) {
4174                         u32 common;
4175
4176                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4177                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4178                         common = local_adv & remote_adv;
4179                         if (common & (ADVERTISE_1000XHALF |
4180                                       ADVERTISE_1000XFULL)) {
4181                                 if (common & ADVERTISE_1000XFULL)
4182                                         current_duplex = DUPLEX_FULL;
4183                                 else
4184                                         current_duplex = DUPLEX_HALF;
4185                         } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4186                                 /* Link is up via parallel detect */
4187                         } else {
4188                                 current_link_up = 0;
4189                         }
4190                 }
4191         }
4192
4193         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4194                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4195
4196         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4197         if (tp->link_config.active_duplex == DUPLEX_HALF)
4198                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4199
4200         tw32_f(MAC_MODE, tp->mac_mode);
4201         udelay(40);
4202
4203         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4204
4205         tp->link_config.active_speed = current_speed;
4206         tp->link_config.active_duplex = current_duplex;
4207
4208         if (current_link_up != netif_carrier_ok(tp->dev)) {
4209                 if (current_link_up)
4210                         netif_carrier_on(tp->dev);
4211                 else {
4212                         netif_carrier_off(tp->dev);
4213                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4214                 }
4215                 tg3_link_report(tp);
4216         }
4217         return err;
4218 }
4219
4220 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4221 {
4222         if (tp->serdes_counter) {
4223                 /* Give autoneg time to complete. */
4224                 tp->serdes_counter--;
4225                 return;
4226         }
4227
4228         if (!netif_carrier_ok(tp->dev) &&
4229             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4230                 u32 bmcr;
4231
4232                 tg3_readphy(tp, MII_BMCR, &bmcr);
4233                 if (bmcr & BMCR_ANENABLE) {
4234                         u32 phy1, phy2;
4235
4236                         /* Select shadow register 0x1f */
4237                         tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
4238                         tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
4239
4240                         /* Select expansion interrupt status register */
4241                         tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4242                                          MII_TG3_DSP_EXP1_INT_STAT);
4243                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4244                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4245
4246                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4247                                 /* We have signal detect and not receiving
4248                                  * config code words, link is up by parallel
4249                                  * detection.
4250                                  */
4251
4252                                 bmcr &= ~BMCR_ANENABLE;
4253                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4254                                 tg3_writephy(tp, MII_BMCR, bmcr);
4255                                 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
4256                         }
4257                 }
4258         } else if (netif_carrier_ok(tp->dev) &&
4259                    (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4260                    (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4261                 u32 phy2;
4262
4263                 /* Select expansion interrupt status register */
4264                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4265                                  MII_TG3_DSP_EXP1_INT_STAT);
4266                 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4267                 if (phy2 & 0x20) {
4268                         u32 bmcr;
4269
4270                         /* Config code words received, turn on autoneg. */
4271                         tg3_readphy(tp, MII_BMCR, &bmcr);
4272                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4273
4274                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4275
4276                 }
4277         }
4278 }
4279
4280 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4281 {
4282         int err;
4283
4284         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
4285                 err = tg3_setup_fiber_phy(tp, force_reset);
4286         else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4287                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4288         else
4289                 err = tg3_setup_copper_phy(tp, force_reset);
4290
4291         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4292                 u32 val, scale;
4293
4294                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4295                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4296                         scale = 65;
4297                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4298                         scale = 6;
4299                 else
4300                         scale = 12;
4301
4302                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4303                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4304                 tw32(GRC_MISC_CFG, val);
4305         }
4306
4307         if (tp->link_config.active_speed == SPEED_1000 &&
4308             tp->link_config.active_duplex == DUPLEX_HALF)
4309                 tw32(MAC_TX_LENGTHS,
4310                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4311                       (6 << TX_LENGTHS_IPG_SHIFT) |
4312                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4313         else
4314                 tw32(MAC_TX_LENGTHS,
4315                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4316                       (6 << TX_LENGTHS_IPG_SHIFT) |
4317                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4318
4319         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4320                 if (netif_carrier_ok(tp->dev)) {
4321                         tw32(HOSTCC_STAT_COAL_TICKS,
4322                              tp->coal.stats_block_coalesce_usecs);
4323                 } else {
4324                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4325                 }
4326         }
4327
4328         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4329                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4330                 if (!netif_carrier_ok(tp->dev))
4331                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4332                               tp->pwrmgmt_thresh;
4333                 else
4334                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4335                 tw32(PCIE_PWR_MGMT_THRESH, val);
4336         }
4337
4338         return err;
4339 }
4340
4341 /* This is called whenever we suspect that the system chipset is re-
4342  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4343  * is bogus tx completions. We try to recover by setting the
4344  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4345  * in the workqueue.
4346  */
4347 static void tg3_tx_recover(struct tg3 *tp)
4348 {
4349         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4350                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4351
4352         netdev_warn(tp->dev,
4353                     "The system may be re-ordering memory-mapped I/O "
4354                     "cycles to the network device, attempting to recover. "
4355                     "Please report the problem to the driver maintainer "
4356                     "and include system chipset information.\n");
4357
4358         spin_lock(&tp->lock);
4359         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4360         spin_unlock(&tp->lock);
4361 }
4362
4363 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4364 {
4365         /* Tell compiler to fetch tx indices from memory. */
4366         barrier();
4367         return tnapi->tx_pending -
4368                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4369 }
4370
4371 /* Tigon3 never reports partial packet sends.  So we do not
4372  * need special logic to handle SKBs that have not had all
4373  * of their frags sent yet, like SunGEM does.
4374  */
4375 static void tg3_tx(struct tg3_napi *tnapi)
4376 {
4377         struct tg3 *tp = tnapi->tp;
4378         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4379         u32 sw_idx = tnapi->tx_cons;
4380         struct netdev_queue *txq;
4381         int index = tnapi - tp->napi;
4382
4383         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4384                 index--;
4385
4386         txq = netdev_get_tx_queue(tp->dev, index);
4387
4388         while (sw_idx != hw_idx) {
4389                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4390                 struct sk_buff *skb = ri->skb;
4391                 int i, tx_bug = 0;
4392
4393                 if (unlikely(skb == NULL)) {
4394                         tg3_tx_recover(tp);
4395                         return;
4396                 }
4397
4398                 pci_unmap_single(tp->pdev,
4399                                  dma_unmap_addr(ri, mapping),
4400                                  skb_headlen(skb),
4401                                  PCI_DMA_TODEVICE);
4402
4403                 ri->skb = NULL;
4404
4405                 sw_idx = NEXT_TX(sw_idx);
4406
4407                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4408                         ri = &tnapi->tx_buffers[sw_idx];
4409                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4410                                 tx_bug = 1;
4411
4412                         pci_unmap_page(tp->pdev,
4413                                        dma_unmap_addr(ri, mapping),
4414                                        skb_shinfo(skb)->frags[i].size,
4415                                        PCI_DMA_TODEVICE);
4416                         sw_idx = NEXT_TX(sw_idx);
4417                 }
4418
4419                 dev_kfree_skb(skb);
4420
4421                 if (unlikely(tx_bug)) {
4422                         tg3_tx_recover(tp);
4423                         return;
4424                 }
4425         }
4426
4427         tnapi->tx_cons = sw_idx;
4428
4429         /* Need to make the tx_cons update visible to tg3_start_xmit()
4430          * before checking for netif_queue_stopped().  Without the
4431          * memory barrier, there is a small possibility that tg3_start_xmit()
4432          * will miss it and cause the queue to be stopped forever.
4433          */
4434         smp_mb();
4435
4436         if (unlikely(netif_tx_queue_stopped(txq) &&
4437                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4438                 __netif_tx_lock(txq, smp_processor_id());
4439                 if (netif_tx_queue_stopped(txq) &&
4440                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4441                         netif_tx_wake_queue(txq);
4442                 __netif_tx_unlock(txq);
4443         }
4444 }
4445
4446 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4447 {
4448         if (!ri->skb)
4449                 return;
4450
4451         pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4452                          map_sz, PCI_DMA_FROMDEVICE);
4453         dev_kfree_skb_any(ri->skb);
4454         ri->skb = NULL;
4455 }
4456
4457 /* Returns size of skb allocated or < 0 on error.
4458  *
4459  * We only need to fill in the address because the other members
4460  * of the RX descriptor are invariant, see tg3_init_rings.
4461  *
4462  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4463  * posting buffers we only dirty the first cache line of the RX
4464  * descriptor (containing the address).  Whereas for the RX status
4465  * buffers the cpu only reads the last cacheline of the RX descriptor
4466  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4467  */
4468 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4469                             u32 opaque_key, u32 dest_idx_unmasked)
4470 {
4471         struct tg3_rx_buffer_desc *desc;
4472         struct ring_info *map, *src_map;
4473         struct sk_buff *skb;
4474         dma_addr_t mapping;
4475         int skb_size, dest_idx;
4476
4477         src_map = NULL;
4478         switch (opaque_key) {
4479         case RXD_OPAQUE_RING_STD:
4480                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4481                 desc = &tpr->rx_std[dest_idx];
4482                 map = &tpr->rx_std_buffers[dest_idx];
4483                 skb_size = tp->rx_pkt_map_sz;
4484                 break;
4485
4486         case RXD_OPAQUE_RING_JUMBO:
4487                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4488                 desc = &tpr->rx_jmb[dest_idx].std;
4489                 map = &tpr->rx_jmb_buffers[dest_idx];
4490                 skb_size = TG3_RX_JMB_MAP_SZ;
4491                 break;
4492
4493         default:
4494                 return -EINVAL;
4495         }
4496
4497         /* Do not overwrite any of the map or rp information
4498          * until we are sure we can commit to a new buffer.
4499          *
4500          * Callers depend upon this behavior and assume that
4501          * we leave everything unchanged if we fail.
4502          */
4503         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4504         if (skb == NULL)
4505                 return -ENOMEM;
4506
4507         skb_reserve(skb, tp->rx_offset);
4508
4509         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4510                                  PCI_DMA_FROMDEVICE);
4511         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4512                 dev_kfree_skb(skb);
4513                 return -EIO;
4514         }
4515
4516         map->skb = skb;
4517         dma_unmap_addr_set(map, mapping, mapping);
4518
4519         desc->addr_hi = ((u64)mapping >> 32);
4520         desc->addr_lo = ((u64)mapping & 0xffffffff);
4521
4522         return skb_size;
4523 }
4524
4525 /* We only need to move over in the address because the other
4526  * members of the RX descriptor are invariant.  See notes above
4527  * tg3_alloc_rx_skb for full details.
4528  */
4529 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4530                            struct tg3_rx_prodring_set *dpr,
4531                            u32 opaque_key, int src_idx,
4532                            u32 dest_idx_unmasked)
4533 {
4534         struct tg3 *tp = tnapi->tp;
4535         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4536         struct ring_info *src_map, *dest_map;
4537         struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
4538         int dest_idx;
4539
4540         switch (opaque_key) {
4541         case RXD_OPAQUE_RING_STD:
4542                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4543                 dest_desc = &dpr->rx_std[dest_idx];
4544                 dest_map = &dpr->rx_std_buffers[dest_idx];
4545                 src_desc = &spr->rx_std[src_idx];
4546                 src_map = &spr->rx_std_buffers[src_idx];
4547                 break;
4548
4549         case RXD_OPAQUE_RING_JUMBO:
4550                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4551                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4552                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4553                 src_desc = &spr->rx_jmb[src_idx].std;
4554                 src_map = &spr->rx_jmb_buffers[src_idx];
4555                 break;
4556
4557         default:
4558                 return;
4559         }
4560
4561         dest_map->skb = src_map->skb;
4562         dma_unmap_addr_set(dest_map, mapping,
4563                            dma_unmap_addr(src_map, mapping));
4564         dest_desc->addr_hi = src_desc->addr_hi;
4565         dest_desc->addr_lo = src_desc->addr_lo;
4566
4567         /* Ensure that the update to the skb happens after the physical
4568          * addresses have been transferred to the new BD location.
4569          */
4570         smp_wmb();
4571
4572         src_map->skb = NULL;
4573 }
4574
4575 /* The RX ring scheme is composed of multiple rings which post fresh
4576  * buffers to the chip, and one special ring the chip uses to report
4577  * status back to the host.
4578  *
4579  * The special ring reports the status of received packets to the
4580  * host.  The chip does not write into the original descriptor the
4581  * RX buffer was obtained from.  The chip simply takes the original
4582  * descriptor as provided by the host, updates the status and length
4583  * field, then writes this into the next status ring entry.
4584  *
4585  * Each ring the host uses to post buffers to the chip is described
4586  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4587  * it is first placed into the on-chip ram.  When the packet's length
4588  * is known, it walks down the TG3_BDINFO entries to select the ring.
4589  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4590  * which is within the range of the new packet's length is chosen.
4591  *
4592  * The "separate ring for rx status" scheme may sound queer, but it makes
4593  * sense from a cache coherency perspective.  If only the host writes
4594  * to the buffer post rings, and only the chip writes to the rx status
4595  * rings, then cache lines never move beyond shared-modified state.
4596  * If both the host and chip were to write into the same ring, cache line
4597  * eviction could occur since both entities want it in an exclusive state.
4598  */
4599 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4600 {
4601         struct tg3 *tp = tnapi->tp;
4602         u32 work_mask, rx_std_posted = 0;
4603         u32 std_prod_idx, jmb_prod_idx;
4604         u32 sw_idx = tnapi->rx_rcb_ptr;
4605         u16 hw_idx;
4606         int received;
4607         struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
4608
4609         hw_idx = *(tnapi->rx_rcb_prod_idx);
4610         /*
4611          * We need to order the read of hw_idx and the read of
4612          * the opaque cookie.
4613          */
4614         rmb();
4615         work_mask = 0;
4616         received = 0;
4617         std_prod_idx = tpr->rx_std_prod_idx;
4618         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4619         while (sw_idx != hw_idx && budget > 0) {
4620                 struct ring_info *ri;
4621                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4622                 unsigned int len;
4623                 struct sk_buff *skb;
4624                 dma_addr_t dma_addr;
4625                 u32 opaque_key, desc_idx, *post_ptr;
4626                 bool hw_vlan __maybe_unused = false;
4627                 u16 vtag __maybe_unused = 0;
4628
4629                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4630                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4631                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4632                         ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4633                         dma_addr = dma_unmap_addr(ri, mapping);
4634                         skb = ri->skb;
4635                         post_ptr = &std_prod_idx;
4636                         rx_std_posted++;
4637                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4638                         ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4639                         dma_addr = dma_unmap_addr(ri, mapping);
4640                         skb = ri->skb;
4641                         post_ptr = &jmb_prod_idx;
4642                 } else
4643                         goto next_pkt_nopost;
4644
4645                 work_mask |= opaque_key;
4646
4647                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4648                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4649                 drop_it:
4650                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4651                                        desc_idx, *post_ptr);
4652                 drop_it_no_recycle:
4653                         /* Other statistics kept track of by card. */
4654                         tp->net_stats.rx_dropped++;
4655                         goto next_pkt;
4656                 }
4657
4658                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4659                       ETH_FCS_LEN;
4660
4661                 if (len > TG3_RX_COPY_THRESH(tp)) {
4662                         int skb_size;
4663
4664                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4665                                                     *post_ptr);
4666                         if (skb_size < 0)
4667                                 goto drop_it;
4668
4669                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4670                                          PCI_DMA_FROMDEVICE);
4671
4672                         /* Ensure that the update to the skb happens
4673                          * after the usage of the old DMA mapping.
4674                          */
4675                         smp_wmb();
4676
4677                         ri->skb = NULL;
4678
4679                         skb_put(skb, len);
4680                 } else {
4681                         struct sk_buff *copy_skb;
4682
4683                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4684                                        desc_idx, *post_ptr);
4685
4686                         copy_skb = netdev_alloc_skb(tp->dev, len + VLAN_HLEN +
4687                                                     TG3_RAW_IP_ALIGN);
4688                         if (copy_skb == NULL)
4689                                 goto drop_it_no_recycle;
4690
4691                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN + VLAN_HLEN);
4692                         skb_put(copy_skb, len);
4693                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4694                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4695                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4696
4697                         /* We'll reuse the original ring buffer. */
4698                         skb = copy_skb;
4699                 }
4700
4701                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4702                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4703                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4704                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4705                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4706                 else
4707                         skb_checksum_none_assert(skb);
4708
4709                 skb->protocol = eth_type_trans(skb, tp->dev);
4710
4711                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4712                     skb->protocol != htons(ETH_P_8021Q)) {
4713                         dev_kfree_skb(skb);
4714                         goto next_pkt;
4715                 }
4716
4717                 if (desc->type_flags & RXD_FLAG_VLAN &&
4718                     !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) {
4719                         vtag = desc->err_vlan & RXD_VLAN_MASK;
4720 #if TG3_VLAN_TAG_USED
4721                         if (tp->vlgrp)
4722                                 hw_vlan = true;
4723                         else
4724 #endif
4725                         {
4726                                 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
4727                                                     __skb_push(skb, VLAN_HLEN);
4728
4729                                 memmove(ve, skb->data + VLAN_HLEN,
4730                                         ETH_ALEN * 2);
4731                                 ve->h_vlan_proto = htons(ETH_P_8021Q);
4732                                 ve->h_vlan_TCI = htons(vtag);
4733                         }
4734                 }
4735
4736 #if TG3_VLAN_TAG_USED
4737                 if (hw_vlan)
4738                         vlan_gro_receive(&tnapi->napi, tp->vlgrp, vtag, skb);
4739                 else
4740 #endif
4741                         napi_gro_receive(&tnapi->napi, skb);
4742
4743                 received++;
4744                 budget--;
4745
4746 next_pkt:
4747                 (*post_ptr)++;
4748
4749                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4750                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4751                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4752                                      tpr->rx_std_prod_idx);
4753                         work_mask &= ~RXD_OPAQUE_RING_STD;
4754                         rx_std_posted = 0;
4755                 }
4756 next_pkt_nopost:
4757                 sw_idx++;
4758                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4759
4760                 /* Refresh hw_idx to see if there is new work */
4761                 if (sw_idx == hw_idx) {
4762                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4763                         rmb();
4764                 }
4765         }
4766
4767         /* ACK the status ring. */
4768         tnapi->rx_rcb_ptr = sw_idx;
4769         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4770
4771         /* Refill RX ring(s). */
4772         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4773                 if (work_mask & RXD_OPAQUE_RING_STD) {
4774                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4775                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4776                                      tpr->rx_std_prod_idx);
4777                 }
4778                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4779                         tpr->rx_jmb_prod_idx = jmb_prod_idx %
4780                                                TG3_RX_JUMBO_RING_SIZE;
4781                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4782                                      tpr->rx_jmb_prod_idx);
4783                 }
4784                 mmiowb();
4785         } else if (work_mask) {
4786                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4787                  * updated before the producer indices can be updated.
4788                  */
4789                 smp_wmb();
4790
4791                 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4792                 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
4793
4794                 if (tnapi != &tp->napi[1])
4795                         napi_schedule(&tp->napi[1].napi);
4796         }
4797
4798         return received;
4799 }
4800
4801 static void tg3_poll_link(struct tg3 *tp)
4802 {
4803         /* handle link change and other phy events */
4804         if (!(tp->tg3_flags &
4805               (TG3_FLAG_USE_LINKCHG_REG |
4806                TG3_FLAG_POLL_SERDES))) {
4807                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4808
4809                 if (sblk->status & SD_STATUS_LINK_CHG) {
4810                         sblk->status = SD_STATUS_UPDATED |
4811                                        (sblk->status & ~SD_STATUS_LINK_CHG);
4812                         spin_lock(&tp->lock);
4813                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4814                                 tw32_f(MAC_STATUS,
4815                                      (MAC_STATUS_SYNC_CHANGED |
4816                                       MAC_STATUS_CFG_CHANGED |
4817                                       MAC_STATUS_MI_COMPLETION |
4818                                       MAC_STATUS_LNKSTATE_CHANGED));
4819                                 udelay(40);
4820                         } else
4821                                 tg3_setup_phy(tp, 0);
4822                         spin_unlock(&tp->lock);
4823                 }
4824         }
4825 }
4826
4827 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4828                                 struct tg3_rx_prodring_set *dpr,
4829                                 struct tg3_rx_prodring_set *spr)
4830 {
4831         u32 si, di, cpycnt, src_prod_idx;
4832         int i, err = 0;
4833
4834         while (1) {
4835                 src_prod_idx = spr->rx_std_prod_idx;
4836
4837                 /* Make sure updates to the rx_std_buffers[] entries and the
4838                  * standard producer index are seen in the correct order.
4839                  */
4840                 smp_rmb();
4841
4842                 if (spr->rx_std_cons_idx == src_prod_idx)
4843                         break;
4844
4845                 if (spr->rx_std_cons_idx < src_prod_idx)
4846                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4847                 else
4848                         cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4849
4850                 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4851
4852                 si = spr->rx_std_cons_idx;
4853                 di = dpr->rx_std_prod_idx;
4854
4855                 for (i = di; i < di + cpycnt; i++) {
4856                         if (dpr->rx_std_buffers[i].skb) {
4857                                 cpycnt = i - di;
4858                                 err = -ENOSPC;
4859                                 break;
4860                         }
4861                 }
4862
4863                 if (!cpycnt)
4864                         break;
4865
4866                 /* Ensure that updates to the rx_std_buffers ring and the
4867                  * shadowed hardware producer ring from tg3_recycle_skb() are
4868                  * ordered correctly WRT the skb check above.
4869                  */
4870                 smp_rmb();
4871
4872                 memcpy(&dpr->rx_std_buffers[di],
4873                        &spr->rx_std_buffers[si],
4874                        cpycnt * sizeof(struct ring_info));
4875
4876                 for (i = 0; i < cpycnt; i++, di++, si++) {
4877                         struct tg3_rx_buffer_desc *sbd, *dbd;
4878                         sbd = &spr->rx_std[si];
4879                         dbd = &dpr->rx_std[di];
4880                         dbd->addr_hi = sbd->addr_hi;
4881                         dbd->addr_lo = sbd->addr_lo;
4882                 }
4883
4884                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4885                                        TG3_RX_RING_SIZE;
4886                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4887                                        TG3_RX_RING_SIZE;
4888         }
4889
4890         while (1) {
4891                 src_prod_idx = spr->rx_jmb_prod_idx;
4892
4893                 /* Make sure updates to the rx_jmb_buffers[] entries and
4894                  * the jumbo producer index are seen in the correct order.
4895                  */
4896                 smp_rmb();
4897
4898                 if (spr->rx_jmb_cons_idx == src_prod_idx)
4899                         break;
4900
4901                 if (spr->rx_jmb_cons_idx < src_prod_idx)
4902                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4903                 else
4904                         cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4905
4906                 cpycnt = min(cpycnt,
4907                              TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4908
4909                 si = spr->rx_jmb_cons_idx;
4910                 di = dpr->rx_jmb_prod_idx;
4911
4912                 for (i = di; i < di + cpycnt; i++) {
4913                         if (dpr->rx_jmb_buffers[i].skb) {
4914                                 cpycnt = i - di;
4915                                 err = -ENOSPC;
4916                                 break;
4917                         }
4918                 }
4919
4920                 if (!cpycnt)
4921                         break;
4922
4923                 /* Ensure that updates to the rx_jmb_buffers ring and the
4924                  * shadowed hardware producer ring from tg3_recycle_skb() are
4925                  * ordered correctly WRT the skb check above.
4926                  */
4927                 smp_rmb();
4928
4929                 memcpy(&dpr->rx_jmb_buffers[di],
4930                        &spr->rx_jmb_buffers[si],
4931                        cpycnt * sizeof(struct ring_info));
4932
4933                 for (i = 0; i < cpycnt; i++, di++, si++) {
4934                         struct tg3_rx_buffer_desc *sbd, *dbd;
4935                         sbd = &spr->rx_jmb[si].std;
4936                         dbd = &dpr->rx_jmb[di].std;
4937                         dbd->addr_hi = sbd->addr_hi;
4938                         dbd->addr_lo = sbd->addr_lo;
4939                 }
4940
4941                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4942                                        TG3_RX_JUMBO_RING_SIZE;
4943                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4944                                        TG3_RX_JUMBO_RING_SIZE;
4945         }
4946
4947         return err;
4948 }
4949
4950 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4951 {
4952         struct tg3 *tp = tnapi->tp;
4953
4954         /* run TX completion thread */
4955         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4956                 tg3_tx(tnapi);
4957                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4958                         return work_done;
4959         }
4960
4961         /* run RX thread, within the bounds set by NAPI.
4962          * All RX "locking" is done by ensuring outside
4963          * code synchronizes with tg3->napi.poll()
4964          */
4965         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4966                 work_done += tg3_rx(tnapi, budget - work_done);
4967
4968         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4969                 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
4970                 int i, err = 0;
4971                 u32 std_prod_idx = dpr->rx_std_prod_idx;
4972                 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
4973
4974                 for (i = 1; i < tp->irq_cnt; i++)
4975                         err |= tg3_rx_prodring_xfer(tp, dpr,
4976                                                     &tp->napi[i].prodring);
4977
4978                 wmb();
4979
4980                 if (std_prod_idx != dpr->rx_std_prod_idx)
4981                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4982                                      dpr->rx_std_prod_idx);
4983
4984                 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
4985                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4986                                      dpr->rx_jmb_prod_idx);
4987
4988                 mmiowb();
4989
4990                 if (err)
4991                         tw32_f(HOSTCC_MODE, tp->coal_now);
4992         }
4993
4994         return work_done;
4995 }
4996
4997 static int tg3_poll_msix(struct napi_struct *napi, int budget)
4998 {
4999         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5000         struct tg3 *tp = tnapi->tp;
5001         int work_done = 0;
5002         struct tg3_hw_status *sblk = tnapi->hw_status;
5003
5004         while (1) {
5005                 work_done = tg3_poll_work(tnapi, work_done, budget);
5006
5007                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5008                         goto tx_recovery;
5009
5010                 if (unlikely(work_done >= budget))
5011                         break;
5012
5013                 /* tp->last_tag is used in tg3_int_reenable() below
5014                  * to tell the hw how much work has been processed,
5015                  * so we must read it before checking for more work.
5016                  */
5017                 tnapi->last_tag = sblk->status_tag;
5018                 tnapi->last_irq_tag = tnapi->last_tag;
5019                 rmb();
5020
5021                 /* check for RX/TX work to do */
5022                 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5023                            *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5024                         napi_complete(napi);
5025                         /* Reenable interrupts. */
5026                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5027                         mmiowb();
5028                         break;
5029                 }
5030         }
5031
5032         return work_done;
5033
5034 tx_recovery:
5035         /* work_done is guaranteed to be less than budget. */
5036         napi_complete(napi);
5037         schedule_work(&tp->reset_task);
5038         return work_done;
5039 }
5040
5041 static int tg3_poll(struct napi_struct *napi, int budget)
5042 {
5043         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5044         struct tg3 *tp = tnapi->tp;
5045         int work_done = 0;
5046         struct tg3_hw_status *sblk = tnapi->hw_status;
5047
5048         while (1) {
5049                 tg3_poll_link(tp);
5050
5051                 work_done = tg3_poll_work(tnapi, work_done, budget);
5052
5053                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5054                         goto tx_recovery;
5055
5056                 if (unlikely(work_done >= budget))
5057                         break;
5058
5059                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5060                         /* tp->last_tag is used in tg3_int_reenable() below
5061                          * to tell the hw how much work has been processed,
5062                          * so we must read it before checking for more work.
5063                          */
5064                         tnapi->last_tag = sblk->status_tag;
5065                         tnapi->last_irq_tag = tnapi->last_tag;
5066                         rmb();
5067                 } else
5068                         sblk->status &= ~SD_STATUS_UPDATED;
5069
5070                 if (likely(!tg3_has_work(tnapi))) {
5071                         napi_complete(napi);
5072                         tg3_int_reenable(tnapi);
5073                         break;
5074                 }
5075         }
5076
5077         return work_done;
5078
5079 tx_recovery:
5080         /* work_done is guaranteed to be less than budget. */
5081         napi_complete(napi);
5082         schedule_work(&tp->reset_task);
5083         return work_done;
5084 }
5085
5086 static void tg3_irq_quiesce(struct tg3 *tp)
5087 {
5088         int i;
5089
5090         BUG_ON(tp->irq_sync);
5091
5092         tp->irq_sync = 1;
5093         smp_mb();
5094
5095         for (i = 0; i < tp->irq_cnt; i++)
5096                 synchronize_irq(tp->napi[i].irq_vec);
5097 }
5098
5099 static inline int tg3_irq_sync(struct tg3 *tp)
5100 {
5101         return tp->irq_sync;
5102 }
5103
5104 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5105  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5106  * with as well.  Most of the time, this is not necessary except when
5107  * shutting down the device.
5108  */
5109 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5110 {
5111         spin_lock_bh(&tp->lock);
5112         if (irq_sync)
5113                 tg3_irq_quiesce(tp);
5114 }
5115
5116 static inline void tg3_full_unlock(struct tg3 *tp)
5117 {
5118         spin_unlock_bh(&tp->lock);
5119 }
5120
5121 /* One-shot MSI handler - Chip automatically disables interrupt
5122  * after sending MSI so driver doesn't have to do it.
5123  */
5124 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5125 {
5126         struct tg3_napi *tnapi = dev_id;
5127         struct tg3 *tp = tnapi->tp;
5128
5129         prefetch(tnapi->hw_status);
5130         if (tnapi->rx_rcb)
5131                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5132
5133         if (likely(!tg3_irq_sync(tp)))
5134                 napi_schedule(&tnapi->napi);
5135
5136         return IRQ_HANDLED;
5137 }
5138
5139 /* MSI ISR - No need to check for interrupt sharing and no need to
5140  * flush status block and interrupt mailbox. PCI ordering rules
5141  * guarantee that MSI will arrive after the status block.
5142  */
5143 static irqreturn_t tg3_msi(int irq, void *dev_id)
5144 {
5145         struct tg3_napi *tnapi = dev_id;
5146         struct tg3 *tp = tnapi->tp;
5147
5148         prefetch(tnapi->hw_status);
5149         if (tnapi->rx_rcb)
5150                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5151         /*
5152          * Writing any value to intr-mbox-0 clears PCI INTA# and
5153          * chip-internal interrupt pending events.
5154          * Writing non-zero to intr-mbox-0 additional tells the
5155          * NIC to stop sending us irqs, engaging "in-intr-handler"
5156          * event coalescing.
5157          */
5158         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5159         if (likely(!tg3_irq_sync(tp)))
5160                 napi_schedule(&tnapi->napi);
5161
5162         return IRQ_RETVAL(1);
5163 }
5164
5165 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5166 {
5167         struct tg3_napi *tnapi = dev_id;
5168         struct tg3 *tp = tnapi->tp;
5169         struct tg3_hw_status *sblk = tnapi->hw_status;
5170         unsigned int handled = 1;
5171
5172         /* In INTx mode, it is possible for the interrupt to arrive at
5173          * the CPU before the status block posted prior to the interrupt.
5174          * Reading the PCI State register will confirm whether the
5175          * interrupt is ours and will flush the status block.
5176          */
5177         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5178                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5179                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5180                         handled = 0;
5181                         goto out;
5182                 }
5183         }
5184
5185         /*
5186          * Writing any value to intr-mbox-0 clears PCI INTA# and
5187          * chip-internal interrupt pending events.
5188          * Writing non-zero to intr-mbox-0 additional tells the
5189          * NIC to stop sending us irqs, engaging "in-intr-handler"
5190          * event coalescing.
5191          *
5192          * Flush the mailbox to de-assert the IRQ immediately to prevent
5193          * spurious interrupts.  The flush impacts performance but
5194          * excessive spurious interrupts can be worse in some cases.
5195          */
5196         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5197         if (tg3_irq_sync(tp))
5198                 goto out;
5199         sblk->status &= ~SD_STATUS_UPDATED;
5200         if (likely(tg3_has_work(tnapi))) {
5201                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5202                 napi_schedule(&tnapi->napi);
5203         } else {
5204                 /* No work, shared interrupt perhaps?  re-enable
5205                  * interrupts, and flush that PCI write
5206                  */
5207                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5208                                0x00000000);
5209         }
5210 out:
5211         return IRQ_RETVAL(handled);
5212 }
5213
5214 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5215 {
5216         struct tg3_napi *tnapi = dev_id;
5217         struct tg3 *tp = tnapi->tp;
5218         struct tg3_hw_status *sblk = tnapi->hw_status;
5219         unsigned int handled = 1;
5220
5221         /* In INTx mode, it is possible for the interrupt to arrive at
5222          * the CPU before the status block posted prior to the interrupt.
5223          * Reading the PCI State register will confirm whether the
5224          * interrupt is ours and will flush the status block.
5225          */
5226         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5227                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5228                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5229                         handled = 0;
5230                         goto out;
5231                 }
5232         }
5233
5234         /*
5235          * writing any value to intr-mbox-0 clears PCI INTA# and
5236          * chip-internal interrupt pending events.
5237          * writing non-zero to intr-mbox-0 additional tells the
5238          * NIC to stop sending us irqs, engaging "in-intr-handler"
5239          * event coalescing.
5240          *
5241          * Flush the mailbox to de-assert the IRQ immediately to prevent
5242          * spurious interrupts.  The flush impacts performance but
5243          * excessive spurious interrupts can be worse in some cases.
5244          */
5245         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5246
5247         /*
5248          * In a shared interrupt configuration, sometimes other devices'
5249          * interrupts will scream.  We record the current status tag here
5250          * so that the above check can report that the screaming interrupts
5251          * are unhandled.  Eventually they will be silenced.
5252          */
5253         tnapi->last_irq_tag = sblk->status_tag;
5254
5255         if (tg3_irq_sync(tp))
5256                 goto out;
5257
5258         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5259
5260         napi_schedule(&tnapi->napi);
5261
5262 out:
5263         return IRQ_RETVAL(handled);
5264 }
5265
5266 /* ISR for interrupt test */
5267 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5268 {
5269         struct tg3_napi *tnapi = dev_id;
5270         struct tg3 *tp = tnapi->tp;
5271         struct tg3_hw_status *sblk = tnapi->hw_status;
5272
5273         if ((sblk->status & SD_STATUS_UPDATED) ||
5274             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5275                 tg3_disable_ints(tp);
5276                 return IRQ_RETVAL(1);
5277         }
5278         return IRQ_RETVAL(0);
5279 }
5280
5281 static int tg3_init_hw(struct tg3 *, int);
5282 static int tg3_halt(struct tg3 *, int, int);
5283
5284 /* Restart hardware after configuration changes, self-test, etc.
5285  * Invoked with tp->lock held.
5286  */
5287 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5288         __releases(tp->lock)
5289         __acquires(tp->lock)
5290 {
5291         int err;
5292
5293         err = tg3_init_hw(tp, reset_phy);
5294         if (err) {
5295                 netdev_err(tp->dev,
5296                            "Failed to re-initialize device, aborting\n");
5297                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5298                 tg3_full_unlock(tp);
5299                 del_timer_sync(&tp->timer);
5300                 tp->irq_sync = 0;
5301                 tg3_napi_enable(tp);
5302                 dev_close(tp->dev);
5303                 tg3_full_lock(tp, 0);
5304         }
5305         return err;
5306 }
5307
5308 #ifdef CONFIG_NET_POLL_CONTROLLER
5309 static void tg3_poll_controller(struct net_device *dev)
5310 {
5311         int i;
5312         struct tg3 *tp = netdev_priv(dev);
5313
5314         for (i = 0; i < tp->irq_cnt; i++)
5315                 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5316 }
5317 #endif
5318
5319 static void tg3_reset_task(struct work_struct *work)
5320 {
5321         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5322         int err;
5323         unsigned int restart_timer;
5324
5325         tg3_full_lock(tp, 0);
5326
5327         if (!netif_running(tp->dev)) {
5328                 tg3_full_unlock(tp);
5329                 return;
5330         }
5331
5332         tg3_full_unlock(tp);
5333
5334         tg3_phy_stop(tp);
5335
5336         tg3_netif_stop(tp);
5337
5338         tg3_full_lock(tp, 1);
5339
5340         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5341         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5342
5343         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5344                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5345                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5346                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5347                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5348         }
5349
5350         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5351         err = tg3_init_hw(tp, 1);
5352         if (err)
5353                 goto out;
5354
5355         tg3_netif_start(tp);
5356
5357         if (restart_timer)
5358                 mod_timer(&tp->timer, jiffies + 1);
5359
5360 out:
5361         tg3_full_unlock(tp);
5362
5363         if (!err)
5364                 tg3_phy_start(tp);
5365 }
5366
5367 static void tg3_dump_short_state(struct tg3 *tp)
5368 {
5369         netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5370                    tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5371         netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5372                    tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5373 }
5374
5375 static void tg3_tx_timeout(struct net_device *dev)
5376 {
5377         struct tg3 *tp = netdev_priv(dev);
5378
5379         if (netif_msg_tx_err(tp)) {
5380                 netdev_err(dev, "transmit timed out, resetting\n");
5381                 tg3_dump_short_state(tp);
5382         }
5383
5384         schedule_work(&tp->reset_task);
5385 }
5386
5387 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5388 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5389 {
5390         u32 base = (u32) mapping & 0xffffffff;
5391
5392         return (base > 0xffffdcc0) && (base + len + 8 < base);
5393 }
5394
5395 /* Test for DMA addresses > 40-bit */
5396 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5397                                           int len)
5398 {
5399 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5400         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5401                 return ((u64) mapping + len) > DMA_BIT_MASK(40);
5402         return 0;
5403 #else
5404         return 0;
5405 #endif
5406 }
5407
5408 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5409
5410 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5411 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5412                                        struct sk_buff *skb, u32 last_plus_one,
5413                                        u32 *start, u32 base_flags, u32 mss)
5414 {
5415         struct tg3 *tp = tnapi->tp;
5416         struct sk_buff *new_skb;
5417         dma_addr_t new_addr = 0;
5418         u32 entry = *start;
5419         int i, ret = 0;
5420
5421         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5422                 new_skb = skb_copy(skb, GFP_ATOMIC);
5423         else {
5424                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5425
5426                 new_skb = skb_copy_expand(skb,
5427                                           skb_headroom(skb) + more_headroom,
5428                                           skb_tailroom(skb), GFP_ATOMIC);
5429         }
5430
5431         if (!new_skb) {
5432                 ret = -1;
5433         } else {
5434                 /* New SKB is guaranteed to be linear. */
5435                 entry = *start;
5436                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5437                                           PCI_DMA_TODEVICE);
5438                 /* Make sure the mapping succeeded */
5439                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5440                         ret = -1;
5441                         dev_kfree_skb(new_skb);
5442                         new_skb = NULL;
5443
5444                 /* Make sure new skb does not cross any 4G boundaries.
5445                  * Drop the packet if it does.
5446                  */
5447                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5448                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5449                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5450                                          PCI_DMA_TODEVICE);
5451                         ret = -1;
5452                         dev_kfree_skb(new_skb);
5453                         new_skb = NULL;
5454                 } else {
5455                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5456                                     base_flags, 1 | (mss << 1));
5457                         *start = NEXT_TX(entry);
5458                 }
5459         }
5460
5461         /* Now clean up the sw ring entries. */
5462         i = 0;
5463         while (entry != last_plus_one) {
5464                 int len;
5465
5466                 if (i == 0)
5467                         len = skb_headlen(skb);
5468                 else
5469                         len = skb_shinfo(skb)->frags[i-1].size;
5470
5471                 pci_unmap_single(tp->pdev,
5472                                  dma_unmap_addr(&tnapi->tx_buffers[entry],
5473                                                 mapping),
5474                                  len, PCI_DMA_TODEVICE);
5475                 if (i == 0) {
5476                         tnapi->tx_buffers[entry].skb = new_skb;
5477                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5478                                            new_addr);
5479                 } else {
5480                         tnapi->tx_buffers[entry].skb = NULL;
5481                 }
5482                 entry = NEXT_TX(entry);
5483                 i++;
5484         }
5485
5486         dev_kfree_skb(skb);
5487
5488         return ret;
5489 }
5490
5491 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5492                         dma_addr_t mapping, int len, u32 flags,
5493                         u32 mss_and_is_end)
5494 {
5495         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5496         int is_end = (mss_and_is_end & 0x1);
5497         u32 mss = (mss_and_is_end >> 1);
5498         u32 vlan_tag = 0;
5499
5500         if (is_end)
5501                 flags |= TXD_FLAG_END;
5502         if (flags & TXD_FLAG_VLAN) {
5503                 vlan_tag = flags >> 16;
5504                 flags &= 0xffff;
5505         }
5506         vlan_tag |= (mss << TXD_MSS_SHIFT);
5507
5508         txd->addr_hi = ((u64) mapping >> 32);
5509         txd->addr_lo = ((u64) mapping & 0xffffffff);
5510         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5511         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5512 }
5513
5514 /* hard_start_xmit for devices that don't have any bugs and
5515  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5516  */
5517 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5518                                   struct net_device *dev)
5519 {
5520         struct tg3 *tp = netdev_priv(dev);
5521         u32 len, entry, base_flags, mss;
5522         dma_addr_t mapping;
5523         struct tg3_napi *tnapi;
5524         struct netdev_queue *txq;
5525         unsigned int i, last;
5526
5527         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5528         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5529         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5530                 tnapi++;
5531
5532         /* We are running in BH disabled context with netif_tx_lock
5533          * and TX reclaim runs via tp->napi.poll inside of a software
5534          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5535          * no IRQ context deadlocks to worry about either.  Rejoice!
5536          */
5537         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5538                 if (!netif_tx_queue_stopped(txq)) {
5539                         netif_tx_stop_queue(txq);
5540
5541                         /* This is a hard error, log it. */
5542                         netdev_err(dev,
5543                                    "BUG! Tx Ring full when queue awake!\n");
5544                 }
5545                 return NETDEV_TX_BUSY;
5546         }
5547
5548         entry = tnapi->tx_prod;
5549         base_flags = 0;
5550         mss = skb_shinfo(skb)->gso_size;
5551         if (mss) {
5552                 int tcp_opt_len, ip_tcp_len;
5553                 u32 hdrlen;
5554
5555                 if (skb_header_cloned(skb) &&
5556                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5557                         dev_kfree_skb(skb);
5558                         goto out_unlock;
5559                 }
5560
5561                 if (skb_is_gso_v6(skb)) {
5562                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5563                 } else {
5564                         struct iphdr *iph = ip_hdr(skb);
5565
5566                         tcp_opt_len = tcp_optlen(skb);
5567                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5568
5569                         iph->check = 0;
5570                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5571                         hdrlen = ip_tcp_len + tcp_opt_len;
5572                 }
5573
5574                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5575                         mss |= (hdrlen & 0xc) << 12;
5576                         if (hdrlen & 0x10)
5577                                 base_flags |= 0x00000010;
5578                         base_flags |= (hdrlen & 0x3e0) << 5;
5579                 } else
5580                         mss |= hdrlen << 9;
5581
5582                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5583                                TXD_FLAG_CPU_POST_DMA);
5584
5585                 tcp_hdr(skb)->check = 0;
5586
5587         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5588                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5589         }
5590
5591 #if TG3_VLAN_TAG_USED
5592         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5593                 base_flags |= (TXD_FLAG_VLAN |
5594                                (vlan_tx_tag_get(skb) << 16));
5595 #endif
5596
5597         len = skb_headlen(skb);
5598
5599         /* Queue skb data, a.k.a. the main skb fragment. */
5600         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5601         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5602                 dev_kfree_skb(skb);
5603                 goto out_unlock;
5604         }
5605
5606         tnapi->tx_buffers[entry].skb = skb;
5607         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5608
5609         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5610             !mss && skb->len > ETH_DATA_LEN)
5611                 base_flags |= TXD_FLAG_JMB_PKT;
5612
5613         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5614                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5615
5616         entry = NEXT_TX(entry);
5617
5618         /* Now loop through additional data fragments, and queue them. */
5619         if (skb_shinfo(skb)->nr_frags > 0) {
5620                 last = skb_shinfo(skb)->nr_frags - 1;
5621                 for (i = 0; i <= last; i++) {
5622                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5623
5624                         len = frag->size;
5625                         mapping = pci_map_page(tp->pdev,
5626                                                frag->page,
5627                                                frag->page_offset,
5628                                                len, PCI_DMA_TODEVICE);
5629                         if (pci_dma_mapping_error(tp->pdev, mapping))
5630                                 goto dma_error;
5631
5632                         tnapi->tx_buffers[entry].skb = NULL;
5633                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5634                                            mapping);
5635
5636                         tg3_set_txd(tnapi, entry, mapping, len,
5637                                     base_flags, (i == last) | (mss << 1));
5638
5639                         entry = NEXT_TX(entry);
5640                 }
5641         }
5642
5643         /* Packets are ready, update Tx producer idx local and on card. */
5644         tw32_tx_mbox(tnapi->prodmbox, entry);
5645
5646         tnapi->tx_prod = entry;
5647         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5648                 netif_tx_stop_queue(txq);
5649
5650                 /* netif_tx_stop_queue() must be done before checking
5651                  * checking tx index in tg3_tx_avail() below, because in
5652                  * tg3_tx(), we update tx index before checking for
5653                  * netif_tx_queue_stopped().
5654                  */
5655                 smp_mb();
5656                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5657                         netif_tx_wake_queue(txq);
5658         }
5659
5660 out_unlock:
5661         mmiowb();
5662
5663         return NETDEV_TX_OK;
5664
5665 dma_error:
5666         last = i;
5667         entry = tnapi->tx_prod;
5668         tnapi->tx_buffers[entry].skb = NULL;
5669         pci_unmap_single(tp->pdev,
5670                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5671                          skb_headlen(skb),
5672                          PCI_DMA_TODEVICE);
5673         for (i = 0; i <= last; i++) {
5674                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5675                 entry = NEXT_TX(entry);
5676
5677                 pci_unmap_page(tp->pdev,
5678                                dma_unmap_addr(&tnapi->tx_buffers[entry],
5679                                               mapping),
5680                                frag->size, PCI_DMA_TODEVICE);
5681         }
5682
5683         dev_kfree_skb(skb);
5684         return NETDEV_TX_OK;
5685 }
5686
5687 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5688                                           struct net_device *);
5689
5690 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5691  * TSO header is greater than 80 bytes.
5692  */
5693 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5694 {
5695         struct sk_buff *segs, *nskb;
5696         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5697
5698         /* Estimate the number of fragments in the worst case */
5699         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5700                 netif_stop_queue(tp->dev);
5701
5702                 /* netif_tx_stop_queue() must be done before checking
5703                  * checking tx index in tg3_tx_avail() below, because in
5704                  * tg3_tx(), we update tx index before checking for
5705                  * netif_tx_queue_stopped().
5706                  */
5707                 smp_mb();
5708                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5709                         return NETDEV_TX_BUSY;
5710
5711                 netif_wake_queue(tp->dev);
5712         }
5713
5714         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5715         if (IS_ERR(segs))
5716                 goto tg3_tso_bug_end;
5717
5718         do {
5719                 nskb = segs;
5720                 segs = segs->next;
5721                 nskb->next = NULL;
5722                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5723         } while (segs);
5724
5725 tg3_tso_bug_end:
5726         dev_kfree_skb(skb);
5727
5728         return NETDEV_TX_OK;
5729 }
5730
5731 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5732  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5733  */
5734 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5735                                           struct net_device *dev)
5736 {
5737         struct tg3 *tp = netdev_priv(dev);
5738         u32 len, entry, base_flags, mss;
5739         int would_hit_hwbug;
5740         dma_addr_t mapping;
5741         struct tg3_napi *tnapi;
5742         struct netdev_queue *txq;
5743         unsigned int i, last;
5744
5745         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5746         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5747         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5748                 tnapi++;
5749
5750         /* We are running in BH disabled context with netif_tx_lock
5751          * and TX reclaim runs via tp->napi.poll inside of a software
5752          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5753          * no IRQ context deadlocks to worry about either.  Rejoice!
5754          */
5755         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5756                 if (!netif_tx_queue_stopped(txq)) {
5757                         netif_tx_stop_queue(txq);
5758
5759                         /* This is a hard error, log it. */
5760                         netdev_err(dev,
5761                                    "BUG! Tx Ring full when queue awake!\n");
5762                 }
5763                 return NETDEV_TX_BUSY;
5764         }
5765
5766         entry = tnapi->tx_prod;
5767         base_flags = 0;
5768         if (skb->ip_summed == CHECKSUM_PARTIAL)
5769                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5770
5771         mss = skb_shinfo(skb)->gso_size;
5772         if (mss) {
5773                 struct iphdr *iph;
5774                 u32 tcp_opt_len, hdr_len;
5775
5776                 if (skb_header_cloned(skb) &&
5777                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5778                         dev_kfree_skb(skb);
5779                         goto out_unlock;
5780                 }
5781
5782                 iph = ip_hdr(skb);
5783                 tcp_opt_len = tcp_optlen(skb);
5784
5785                 if (skb_is_gso_v6(skb)) {
5786                         hdr_len = skb_headlen(skb) - ETH_HLEN;
5787                 } else {
5788                         u32 ip_tcp_len;
5789
5790                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5791                         hdr_len = ip_tcp_len + tcp_opt_len;
5792
5793                         iph->check = 0;
5794                         iph->tot_len = htons(mss + hdr_len);
5795                 }
5796
5797                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5798                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5799                         return tg3_tso_bug(tp, skb);
5800
5801                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5802                                TXD_FLAG_CPU_POST_DMA);
5803
5804                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5805                         tcp_hdr(skb)->check = 0;
5806                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5807                 } else
5808                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5809                                                                  iph->daddr, 0,
5810                                                                  IPPROTO_TCP,
5811                                                                  0);
5812
5813                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5814                         mss |= (hdr_len & 0xc) << 12;
5815                         if (hdr_len & 0x10)
5816                                 base_flags |= 0x00000010;
5817                         base_flags |= (hdr_len & 0x3e0) << 5;
5818                 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5819                         mss |= hdr_len << 9;
5820                 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5821                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5822                         if (tcp_opt_len || iph->ihl > 5) {
5823                                 int tsflags;
5824
5825                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5826                                 mss |= (tsflags << 11);
5827                         }
5828                 } else {
5829                         if (tcp_opt_len || iph->ihl > 5) {
5830                                 int tsflags;
5831
5832                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5833                                 base_flags |= tsflags << 12;
5834                         }
5835                 }
5836         }
5837 #if TG3_VLAN_TAG_USED
5838         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5839                 base_flags |= (TXD_FLAG_VLAN |
5840                                (vlan_tx_tag_get(skb) << 16));
5841 #endif
5842
5843         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5844             !mss && skb->len > ETH_DATA_LEN)
5845                 base_flags |= TXD_FLAG_JMB_PKT;
5846
5847         len = skb_headlen(skb);
5848
5849         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5850         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5851                 dev_kfree_skb(skb);
5852                 goto out_unlock;
5853         }
5854
5855         tnapi->tx_buffers[entry].skb = skb;
5856         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5857
5858         would_hit_hwbug = 0;
5859
5860         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5861                 would_hit_hwbug = 1;
5862
5863         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5864             tg3_4g_overflow_test(mapping, len))
5865                 would_hit_hwbug = 1;
5866
5867         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5868             tg3_40bit_overflow_test(tp, mapping, len))
5869                 would_hit_hwbug = 1;
5870
5871         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5872                 would_hit_hwbug = 1;
5873
5874         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5875                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5876
5877         entry = NEXT_TX(entry);
5878
5879         /* Now loop through additional data fragments, and queue them. */
5880         if (skb_shinfo(skb)->nr_frags > 0) {
5881                 last = skb_shinfo(skb)->nr_frags - 1;
5882                 for (i = 0; i <= last; i++) {
5883                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5884
5885                         len = frag->size;
5886                         mapping = pci_map_page(tp->pdev,
5887                                                frag->page,
5888                                                frag->page_offset,
5889                                                len, PCI_DMA_TODEVICE);
5890
5891                         tnapi->tx_buffers[entry].skb = NULL;
5892                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5893                                            mapping);
5894                         if (pci_dma_mapping_error(tp->pdev, mapping))
5895                                 goto dma_error;
5896
5897                         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5898                             len <= 8)
5899                                 would_hit_hwbug = 1;
5900
5901                         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5902                             tg3_4g_overflow_test(mapping, len))
5903                                 would_hit_hwbug = 1;
5904
5905                         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5906                             tg3_40bit_overflow_test(tp, mapping, len))
5907                                 would_hit_hwbug = 1;
5908
5909                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5910                                 tg3_set_txd(tnapi, entry, mapping, len,
5911                                             base_flags, (i == last)|(mss << 1));
5912                         else
5913                                 tg3_set_txd(tnapi, entry, mapping, len,
5914                                             base_flags, (i == last));
5915
5916                         entry = NEXT_TX(entry);
5917                 }
5918         }
5919
5920         if (would_hit_hwbug) {
5921                 u32 last_plus_one = entry;
5922                 u32 start;
5923
5924                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5925                 start &= (TG3_TX_RING_SIZE - 1);
5926
5927                 /* If the workaround fails due to memory/mapping
5928                  * failure, silently drop this packet.
5929                  */
5930                 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
5931                                                 &start, base_flags, mss))
5932                         goto out_unlock;
5933
5934                 entry = start;
5935         }
5936
5937         /* Packets are ready, update Tx producer idx local and on card. */
5938         tw32_tx_mbox(tnapi->prodmbox, entry);
5939
5940         tnapi->tx_prod = entry;
5941         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5942                 netif_tx_stop_queue(txq);
5943
5944                 /* netif_tx_stop_queue() must be done before checking
5945                  * checking tx index in tg3_tx_avail() below, because in
5946                  * tg3_tx(), we update tx index before checking for
5947                  * netif_tx_queue_stopped().
5948                  */
5949                 smp_mb();
5950                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5951                         netif_tx_wake_queue(txq);
5952         }
5953
5954 out_unlock:
5955         mmiowb();
5956
5957         return NETDEV_TX_OK;
5958
5959 dma_error:
5960         last = i;
5961         entry = tnapi->tx_prod;
5962         tnapi->tx_buffers[entry].skb = NULL;
5963         pci_unmap_single(tp->pdev,
5964                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5965                          skb_headlen(skb),
5966                          PCI_DMA_TODEVICE);
5967         for (i = 0; i <= last; i++) {
5968                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5969                 entry = NEXT_TX(entry);
5970
5971                 pci_unmap_page(tp->pdev,
5972                                dma_unmap_addr(&tnapi->tx_buffers[entry],
5973                                               mapping),
5974                                frag->size, PCI_DMA_TODEVICE);
5975         }
5976
5977         dev_kfree_skb(skb);
5978         return NETDEV_TX_OK;
5979 }
5980
5981 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5982                                int new_mtu)
5983 {
5984         dev->mtu = new_mtu;
5985
5986         if (new_mtu > ETH_DATA_LEN) {
5987                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5988                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5989                         ethtool_op_set_tso(dev, 0);
5990                 } else {
5991                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5992                 }
5993         } else {
5994                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5995                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5996                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5997         }
5998 }
5999
6000 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
6001 {
6002         struct tg3 *tp = netdev_priv(dev);
6003         int err;
6004
6005         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
6006                 return -EINVAL;
6007
6008         if (!netif_running(dev)) {
6009                 /* We'll just catch it later when the
6010                  * device is up'd.
6011                  */
6012                 tg3_set_mtu(dev, tp, new_mtu);
6013                 return 0;
6014         }
6015
6016         tg3_phy_stop(tp);
6017
6018         tg3_netif_stop(tp);
6019
6020         tg3_full_lock(tp, 1);
6021
6022         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6023
6024         tg3_set_mtu(dev, tp, new_mtu);
6025
6026         err = tg3_restart_hw(tp, 0);
6027
6028         if (!err)
6029                 tg3_netif_start(tp);
6030
6031         tg3_full_unlock(tp);
6032
6033         if (!err)
6034                 tg3_phy_start(tp);
6035
6036         return err;
6037 }
6038
6039 static void tg3_rx_prodring_free(struct tg3 *tp,
6040                                  struct tg3_rx_prodring_set *tpr)
6041 {
6042         int i;
6043
6044         if (tpr != &tp->napi[0].prodring) {
6045                 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
6046                      i = (i + 1) % TG3_RX_RING_SIZE)
6047                         tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6048                                         tp->rx_pkt_map_sz);
6049
6050                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6051                         for (i = tpr->rx_jmb_cons_idx;
6052                              i != tpr->rx_jmb_prod_idx;
6053                              i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
6054                                 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6055                                                 TG3_RX_JMB_MAP_SZ);
6056                         }
6057                 }
6058
6059                 return;
6060         }
6061
6062         for (i = 0; i < TG3_RX_RING_SIZE; i++)
6063                 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6064                                 tp->rx_pkt_map_sz);
6065
6066         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6067                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
6068                         tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6069                                         TG3_RX_JMB_MAP_SZ);
6070         }
6071 }
6072
6073 /* Initialize rx rings for packet processing.
6074  *
6075  * The chip has been shut down and the driver detached from
6076  * the networking, so no interrupts or new tx packets will
6077  * end up in the driver.  tp->{tx,}lock are held and thus
6078  * we may not sleep.
6079  */
6080 static int tg3_rx_prodring_alloc(struct tg3 *tp,
6081                                  struct tg3_rx_prodring_set *tpr)
6082 {
6083         u32 i, rx_pkt_dma_sz;
6084
6085         tpr->rx_std_cons_idx = 0;
6086         tpr->rx_std_prod_idx = 0;
6087         tpr->rx_jmb_cons_idx = 0;
6088         tpr->rx_jmb_prod_idx = 0;
6089
6090         if (tpr != &tp->napi[0].prodring) {
6091                 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
6092                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
6093                         memset(&tpr->rx_jmb_buffers[0], 0,
6094                                TG3_RX_JMB_BUFF_RING_SIZE);
6095                 goto done;
6096         }
6097
6098         /* Zero out all descriptors. */
6099         memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
6100
6101         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6102         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
6103             tp->dev->mtu > ETH_DATA_LEN)
6104                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6105         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6106
6107         /* Initialize invariants of the rings, we only set this
6108          * stuff once.  This works because the card does not
6109          * write into the rx buffer posting rings.
6110          */
6111         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
6112                 struct tg3_rx_buffer_desc *rxd;
6113
6114                 rxd = &tpr->rx_std[i];
6115                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6116                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6117                 rxd->opaque = (RXD_OPAQUE_RING_STD |
6118                                (i << RXD_OPAQUE_INDEX_SHIFT));
6119         }
6120
6121         /* Now allocate fresh SKBs for each rx ring. */
6122         for (i = 0; i < tp->rx_pending; i++) {
6123                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6124                         netdev_warn(tp->dev,
6125                                     "Using a smaller RX standard ring. Only "
6126                                     "%d out of %d buffers were allocated "
6127                                     "successfully\n", i, tp->rx_pending);
6128                         if (i == 0)
6129                                 goto initfail;
6130                         tp->rx_pending = i;
6131                         break;
6132                 }
6133         }
6134
6135         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6136                 goto done;
6137
6138         memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
6139
6140         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
6141                 goto done;
6142
6143         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
6144                 struct tg3_rx_buffer_desc *rxd;
6145
6146                 rxd = &tpr->rx_jmb[i].std;
6147                 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6148                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6149                                   RXD_FLAG_JUMBO;
6150                 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6151                        (i << RXD_OPAQUE_INDEX_SHIFT));
6152         }
6153
6154         for (i = 0; i < tp->rx_jumbo_pending; i++) {
6155                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
6156                         netdev_warn(tp->dev,
6157                                     "Using a smaller RX jumbo ring. Only %d "
6158                                     "out of %d buffers were allocated "
6159                                     "successfully\n", i, tp->rx_jumbo_pending);
6160                         if (i == 0)
6161                                 goto initfail;
6162                         tp->rx_jumbo_pending = i;
6163                         break;
6164                 }
6165         }
6166
6167 done:
6168         return 0;
6169
6170 initfail:
6171         tg3_rx_prodring_free(tp, tpr);
6172         return -ENOMEM;
6173 }
6174
6175 static void tg3_rx_prodring_fini(struct tg3 *tp,
6176                                  struct tg3_rx_prodring_set *tpr)
6177 {
6178         kfree(tpr->rx_std_buffers);
6179         tpr->rx_std_buffers = NULL;
6180         kfree(tpr->rx_jmb_buffers);
6181         tpr->rx_jmb_buffers = NULL;
6182         if (tpr->rx_std) {
6183                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
6184                                     tpr->rx_std, tpr->rx_std_mapping);
6185                 tpr->rx_std = NULL;
6186         }
6187         if (tpr->rx_jmb) {
6188                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
6189                                     tpr->rx_jmb, tpr->rx_jmb_mapping);
6190                 tpr->rx_jmb = NULL;
6191         }
6192 }
6193
6194 static int tg3_rx_prodring_init(struct tg3 *tp,
6195                                 struct tg3_rx_prodring_set *tpr)
6196 {
6197         tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
6198         if (!tpr->rx_std_buffers)
6199                 return -ENOMEM;
6200
6201         tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6202                                            &tpr->rx_std_mapping);
6203         if (!tpr->rx_std)
6204                 goto err_out;
6205
6206         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6207                 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
6208                                               GFP_KERNEL);
6209                 if (!tpr->rx_jmb_buffers)
6210                         goto err_out;
6211
6212                 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6213                                                    TG3_RX_JUMBO_RING_BYTES,
6214                                                    &tpr->rx_jmb_mapping);
6215                 if (!tpr->rx_jmb)
6216                         goto err_out;
6217         }
6218
6219         return 0;
6220
6221 err_out:
6222         tg3_rx_prodring_fini(tp, tpr);
6223         return -ENOMEM;
6224 }
6225
6226 /* Free up pending packets in all rx/tx rings.
6227  *
6228  * The chip has been shut down and the driver detached from
6229  * the networking, so no interrupts or new tx packets will
6230  * end up in the driver.  tp->{tx,}lock is not held and we are not
6231  * in an interrupt context and thus may sleep.
6232  */
6233 static void tg3_free_rings(struct tg3 *tp)
6234 {
6235         int i, j;
6236
6237         for (j = 0; j < tp->irq_cnt; j++) {
6238                 struct tg3_napi *tnapi = &tp->napi[j];
6239
6240                 tg3_rx_prodring_free(tp, &tnapi->prodring);
6241
6242                 if (!tnapi->tx_buffers)
6243                         continue;
6244
6245                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6246                         struct ring_info *txp;
6247                         struct sk_buff *skb;
6248                         unsigned int k;
6249
6250                         txp = &tnapi->tx_buffers[i];
6251                         skb = txp->skb;
6252
6253                         if (skb == NULL) {
6254                                 i++;
6255                                 continue;
6256                         }
6257
6258                         pci_unmap_single(tp->pdev,
6259                                          dma_unmap_addr(txp, mapping),
6260                                          skb_headlen(skb),
6261                                          PCI_DMA_TODEVICE);
6262                         txp->skb = NULL;
6263
6264                         i++;
6265
6266                         for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6267                                 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6268                                 pci_unmap_page(tp->pdev,
6269                                                dma_unmap_addr(txp, mapping),
6270                                                skb_shinfo(skb)->frags[k].size,
6271                                                PCI_DMA_TODEVICE);
6272                                 i++;
6273                         }
6274
6275                         dev_kfree_skb_any(skb);
6276                 }
6277         }
6278 }
6279
6280 /* Initialize tx/rx rings for packet processing.
6281  *
6282  * The chip has been shut down and the driver detached from
6283  * the networking, so no interrupts or new tx packets will
6284  * end up in the driver.  tp->{tx,}lock are held and thus
6285  * we may not sleep.
6286  */
6287 static int tg3_init_rings(struct tg3 *tp)
6288 {
6289         int i;
6290
6291         /* Free up all the SKBs. */
6292         tg3_free_rings(tp);
6293
6294         for (i = 0; i < tp->irq_cnt; i++) {
6295                 struct tg3_napi *tnapi = &tp->napi[i];
6296
6297                 tnapi->last_tag = 0;
6298                 tnapi->last_irq_tag = 0;
6299                 tnapi->hw_status->status = 0;
6300                 tnapi->hw_status->status_tag = 0;
6301                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6302
6303                 tnapi->tx_prod = 0;
6304                 tnapi->tx_cons = 0;
6305                 if (tnapi->tx_ring)
6306                         memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6307
6308                 tnapi->rx_rcb_ptr = 0;
6309                 if (tnapi->rx_rcb)
6310                         memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6311
6312                 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
6313                         tg3_free_rings(tp);
6314                         return -ENOMEM;
6315                 }
6316         }
6317
6318         return 0;
6319 }
6320
6321 /*
6322  * Must not be invoked with interrupt sources disabled and
6323  * the hardware shutdown down.
6324  */
6325 static void tg3_free_consistent(struct tg3 *tp)
6326 {
6327         int i;
6328
6329         for (i = 0; i < tp->irq_cnt; i++) {
6330                 struct tg3_napi *tnapi = &tp->napi[i];
6331
6332                 if (tnapi->tx_ring) {
6333                         pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6334                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
6335                         tnapi->tx_ring = NULL;
6336                 }
6337
6338                 kfree(tnapi->tx_buffers);
6339                 tnapi->tx_buffers = NULL;
6340
6341                 if (tnapi->rx_rcb) {
6342                         pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6343                                             tnapi->rx_rcb,
6344                                             tnapi->rx_rcb_mapping);
6345                         tnapi->rx_rcb = NULL;
6346                 }
6347
6348                 tg3_rx_prodring_fini(tp, &tnapi->prodring);
6349
6350                 if (tnapi->hw_status) {
6351                         pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6352                                             tnapi->hw_status,
6353                                             tnapi->status_mapping);
6354                         tnapi->hw_status = NULL;
6355                 }
6356         }
6357
6358         if (tp->hw_stats) {
6359                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6360                                     tp->hw_stats, tp->stats_mapping);
6361                 tp->hw_stats = NULL;
6362         }
6363 }
6364
6365 /*
6366  * Must not be invoked with interrupt sources disabled and
6367  * the hardware shutdown down.  Can sleep.
6368  */
6369 static int tg3_alloc_consistent(struct tg3 *tp)
6370 {
6371         int i;
6372
6373         tp->hw_stats = pci_alloc_consistent(tp->pdev,
6374                                             sizeof(struct tg3_hw_stats),
6375                                             &tp->stats_mapping);
6376         if (!tp->hw_stats)
6377                 goto err_out;
6378
6379         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6380
6381         for (i = 0; i < tp->irq_cnt; i++) {
6382                 struct tg3_napi *tnapi = &tp->napi[i];
6383                 struct tg3_hw_status *sblk;
6384
6385                 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6386                                                         TG3_HW_STATUS_SIZE,
6387                                                         &tnapi->status_mapping);
6388                 if (!tnapi->hw_status)
6389                         goto err_out;
6390
6391                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6392                 sblk = tnapi->hw_status;
6393
6394                 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
6395                         goto err_out;
6396
6397                 /* If multivector TSS is enabled, vector 0 does not handle
6398                  * tx interrupts.  Don't allocate any resources for it.
6399                  */
6400                 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6401                     (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6402                         tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6403                                                     TG3_TX_RING_SIZE,
6404                                                     GFP_KERNEL);
6405                         if (!tnapi->tx_buffers)
6406                                 goto err_out;
6407
6408                         tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6409                                                               TG3_TX_RING_BYTES,
6410                                                        &tnapi->tx_desc_mapping);
6411                         if (!tnapi->tx_ring)
6412                                 goto err_out;
6413                 }
6414
6415                 /*
6416                  * When RSS is enabled, the status block format changes
6417                  * slightly.  The "rx_jumbo_consumer", "reserved",
6418                  * and "rx_mini_consumer" members get mapped to the
6419                  * other three rx return ring producer indexes.
6420                  */
6421                 switch (i) {
6422                 default:
6423                         tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6424                         break;
6425                 case 2:
6426                         tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6427                         break;
6428                 case 3:
6429                         tnapi->rx_rcb_prod_idx = &sblk->reserved;
6430                         break;
6431                 case 4:
6432                         tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6433                         break;
6434                 }
6435
6436                 /*
6437                  * If multivector RSS is enabled, vector 0 does not handle
6438                  * rx or tx interrupts.  Don't allocate any resources for it.
6439                  */
6440                 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6441                         continue;
6442
6443                 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6444                                                      TG3_RX_RCB_RING_BYTES(tp),
6445                                                      &tnapi->rx_rcb_mapping);
6446                 if (!tnapi->rx_rcb)
6447                         goto err_out;
6448
6449                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6450         }
6451
6452         return 0;
6453
6454 err_out:
6455         tg3_free_consistent(tp);
6456         return -ENOMEM;
6457 }
6458
6459 #define MAX_WAIT_CNT 1000
6460
6461 /* To stop a block, clear the enable bit and poll till it
6462  * clears.  tp->lock is held.
6463  */
6464 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6465 {
6466         unsigned int i;
6467         u32 val;
6468
6469         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6470                 switch (ofs) {
6471                 case RCVLSC_MODE:
6472                 case DMAC_MODE:
6473                 case MBFREE_MODE:
6474                 case BUFMGR_MODE:
6475                 case MEMARB_MODE:
6476                         /* We can't enable/disable these bits of the
6477                          * 5705/5750, just say success.
6478                          */
6479                         return 0;
6480
6481                 default:
6482                         break;
6483                 }
6484         }
6485
6486         val = tr32(ofs);
6487         val &= ~enable_bit;
6488         tw32_f(ofs, val);
6489
6490         for (i = 0; i < MAX_WAIT_CNT; i++) {
6491                 udelay(100);
6492                 val = tr32(ofs);
6493                 if ((val & enable_bit) == 0)
6494                         break;
6495         }
6496
6497         if (i == MAX_WAIT_CNT && !silent) {
6498                 dev_err(&tp->pdev->dev,
6499                         "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6500                         ofs, enable_bit);
6501                 return -ENODEV;
6502         }
6503
6504         return 0;
6505 }
6506
6507 /* tp->lock is held. */
6508 static int tg3_abort_hw(struct tg3 *tp, int silent)
6509 {
6510         int i, err;
6511
6512         tg3_disable_ints(tp);
6513
6514         tp->rx_mode &= ~RX_MODE_ENABLE;
6515         tw32_f(MAC_RX_MODE, tp->rx_mode);
6516         udelay(10);
6517
6518         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6519         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6520         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6521         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6522         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6523         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6524
6525         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6526         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6527         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6528         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6529         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6530         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6531         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6532
6533         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6534         tw32_f(MAC_MODE, tp->mac_mode);
6535         udelay(40);
6536
6537         tp->tx_mode &= ~TX_MODE_ENABLE;
6538         tw32_f(MAC_TX_MODE, tp->tx_mode);
6539
6540         for (i = 0; i < MAX_WAIT_CNT; i++) {
6541                 udelay(100);
6542                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6543                         break;
6544         }
6545         if (i >= MAX_WAIT_CNT) {
6546                 dev_err(&tp->pdev->dev,
6547                         "%s timed out, TX_MODE_ENABLE will not clear "
6548                         "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
6549                 err |= -ENODEV;
6550         }
6551
6552         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6553         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6554         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6555
6556         tw32(FTQ_RESET, 0xffffffff);
6557         tw32(FTQ_RESET, 0x00000000);
6558
6559         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6560         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6561
6562         for (i = 0; i < tp->irq_cnt; i++) {
6563                 struct tg3_napi *tnapi = &tp->napi[i];
6564                 if (tnapi->hw_status)
6565                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6566         }
6567         if (tp->hw_stats)
6568                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6569
6570         return err;
6571 }
6572
6573 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6574 {
6575         int i;
6576         u32 apedata;
6577
6578         /* NCSI does not support APE events */
6579         if (tp->tg3_flags3 & TG3_FLG3_APE_HAS_NCSI)
6580                 return;
6581
6582         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6583         if (apedata != APE_SEG_SIG_MAGIC)
6584                 return;
6585
6586         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6587         if (!(apedata & APE_FW_STATUS_READY))
6588                 return;
6589
6590         /* Wait for up to 1 millisecond for APE to service previous event. */
6591         for (i = 0; i < 10; i++) {
6592                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6593                         return;
6594
6595                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6596
6597                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6598                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6599                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6600
6601                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6602
6603                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6604                         break;
6605
6606                 udelay(100);
6607         }
6608
6609         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6610                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6611 }
6612
6613 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6614 {
6615         u32 event;
6616         u32 apedata;
6617
6618         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6619                 return;
6620
6621         switch (kind) {
6622         case RESET_KIND_INIT:
6623                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6624                                 APE_HOST_SEG_SIG_MAGIC);
6625                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6626                                 APE_HOST_SEG_LEN_MAGIC);
6627                 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6628                 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6629                 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6630                         APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
6631                 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6632                                 APE_HOST_BEHAV_NO_PHYLOCK);
6633                 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
6634                                     TG3_APE_HOST_DRVR_STATE_START);
6635
6636                 event = APE_EVENT_STATUS_STATE_START;
6637                 break;
6638         case RESET_KIND_SHUTDOWN:
6639                 /* With the interface we are currently using,
6640                  * APE does not track driver state.  Wiping
6641                  * out the HOST SEGMENT SIGNATURE forces
6642                  * the APE to assume OS absent status.
6643                  */
6644                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6645
6646                 if (device_may_wakeup(&tp->pdev->dev) &&
6647                     (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) {
6648                         tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
6649                                             TG3_APE_HOST_WOL_SPEED_AUTO);
6650                         apedata = TG3_APE_HOST_DRVR_STATE_WOL;
6651                 } else
6652                         apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
6653
6654                 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
6655
6656                 event = APE_EVENT_STATUS_STATE_UNLOAD;
6657                 break;
6658         case RESET_KIND_SUSPEND:
6659                 event = APE_EVENT_STATUS_STATE_SUSPEND;
6660                 break;
6661         default:
6662                 return;
6663         }
6664
6665         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6666
6667         tg3_ape_send_event(tp, event);
6668 }
6669
6670 /* tp->lock is held. */
6671 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6672 {
6673         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6674                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6675
6676         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6677                 switch (kind) {
6678                 case RESET_KIND_INIT:
6679                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6680                                       DRV_STATE_START);
6681                         break;
6682
6683                 case RESET_KIND_SHUTDOWN:
6684                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6685                                       DRV_STATE_UNLOAD);
6686                         break;
6687
6688                 case RESET_KIND_SUSPEND:
6689                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6690                                       DRV_STATE_SUSPEND);
6691                         break;
6692
6693                 default:
6694                         break;
6695                 }
6696         }
6697
6698         if (kind == RESET_KIND_INIT ||
6699             kind == RESET_KIND_SUSPEND)
6700                 tg3_ape_driver_state_change(tp, kind);
6701 }
6702
6703 /* tp->lock is held. */
6704 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6705 {
6706         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6707                 switch (kind) {
6708                 case RESET_KIND_INIT:
6709                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6710                                       DRV_STATE_START_DONE);
6711                         break;
6712
6713                 case RESET_KIND_SHUTDOWN:
6714                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6715                                       DRV_STATE_UNLOAD_DONE);
6716                         break;
6717
6718                 default:
6719                         break;
6720                 }
6721         }
6722
6723         if (kind == RESET_KIND_SHUTDOWN)
6724                 tg3_ape_driver_state_change(tp, kind);
6725 }
6726
6727 /* tp->lock is held. */
6728 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6729 {
6730         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6731                 switch (kind) {
6732                 case RESET_KIND_INIT:
6733                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6734                                       DRV_STATE_START);
6735                         break;
6736
6737                 case RESET_KIND_SHUTDOWN:
6738                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6739                                       DRV_STATE_UNLOAD);
6740                         break;
6741
6742                 case RESET_KIND_SUSPEND:
6743                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6744                                       DRV_STATE_SUSPEND);
6745                         break;
6746
6747                 default:
6748                         break;
6749                 }
6750         }
6751 }
6752
6753 static int tg3_poll_fw(struct tg3 *tp)
6754 {
6755         int i;
6756         u32 val;
6757
6758         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6759                 /* Wait up to 20ms for init done. */
6760                 for (i = 0; i < 200; i++) {
6761                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6762                                 return 0;
6763                         udelay(100);
6764                 }
6765                 return -ENODEV;
6766         }
6767
6768         /* Wait for firmware initialization to complete. */
6769         for (i = 0; i < 100000; i++) {
6770                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6771                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6772                         break;
6773                 udelay(10);
6774         }
6775
6776         /* Chip might not be fitted with firmware.  Some Sun onboard
6777          * parts are configured like that.  So don't signal the timeout
6778          * of the above loop as an error, but do report the lack of
6779          * running firmware once.
6780          */
6781         if (i >= 100000 &&
6782             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6783                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6784
6785                 netdev_info(tp->dev, "No firmware running\n");
6786         }
6787
6788         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6789                 /* The 57765 A0 needs a little more
6790                  * time to do some important work.
6791                  */
6792                 mdelay(10);
6793         }
6794
6795         return 0;
6796 }
6797
6798 /* Save PCI command register before chip reset */
6799 static void tg3_save_pci_state(struct tg3 *tp)
6800 {
6801         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6802 }
6803
6804 /* Restore PCI state after chip reset */
6805 static void tg3_restore_pci_state(struct tg3 *tp)
6806 {
6807         u32 val;
6808
6809         /* Re-enable indirect register accesses. */
6810         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6811                                tp->misc_host_ctrl);
6812
6813         /* Set MAX PCI retry to zero. */
6814         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6815         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6816             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6817                 val |= PCISTATE_RETRY_SAME_DMA;
6818         /* Allow reads and writes to the APE register and memory space. */
6819         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6820                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6821                        PCISTATE_ALLOW_APE_SHMEM_WR |
6822                        PCISTATE_ALLOW_APE_PSPACE_WR;
6823         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6824
6825         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6826
6827         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6828                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6829                         pcie_set_readrq(tp->pdev, 4096);
6830                 else {
6831                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6832                                               tp->pci_cacheline_sz);
6833                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6834                                               tp->pci_lat_timer);
6835                 }
6836         }
6837
6838         /* Make sure PCI-X relaxed ordering bit is clear. */
6839         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6840                 u16 pcix_cmd;
6841
6842                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6843                                      &pcix_cmd);
6844                 pcix_cmd &= ~PCI_X_CMD_ERO;
6845                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6846                                       pcix_cmd);
6847         }
6848
6849         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6850
6851                 /* Chip reset on 5780 will reset MSI enable bit,
6852                  * so need to restore it.
6853                  */
6854                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6855                         u16 ctrl;
6856
6857                         pci_read_config_word(tp->pdev,
6858                                              tp->msi_cap + PCI_MSI_FLAGS,
6859                                              &ctrl);
6860                         pci_write_config_word(tp->pdev,
6861                                               tp->msi_cap + PCI_MSI_FLAGS,
6862                                               ctrl | PCI_MSI_FLAGS_ENABLE);
6863                         val = tr32(MSGINT_MODE);
6864                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6865                 }
6866         }
6867 }
6868
6869 static void tg3_stop_fw(struct tg3 *);
6870
6871 /* tp->lock is held. */
6872 static int tg3_chip_reset(struct tg3 *tp)
6873 {
6874         u32 val;
6875         void (*write_op)(struct tg3 *, u32, u32);
6876         int i, err;
6877
6878         tg3_nvram_lock(tp);
6879
6880         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6881
6882         /* No matching tg3_nvram_unlock() after this because
6883          * chip reset below will undo the nvram lock.
6884          */
6885         tp->nvram_lock_cnt = 0;
6886
6887         /* GRC_MISC_CFG core clock reset will clear the memory
6888          * enable bit in PCI register 4 and the MSI enable bit
6889          * on some chips, so we save relevant registers here.
6890          */
6891         tg3_save_pci_state(tp);
6892
6893         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6894             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6895                 tw32(GRC_FASTBOOT_PC, 0);
6896
6897         /*
6898          * We must avoid the readl() that normally takes place.
6899          * It locks machines, causes machine checks, and other
6900          * fun things.  So, temporarily disable the 5701
6901          * hardware workaround, while we do the reset.
6902          */
6903         write_op = tp->write32;
6904         if (write_op == tg3_write_flush_reg32)
6905                 tp->write32 = tg3_write32;
6906
6907         /* Prevent the irq handler from reading or writing PCI registers
6908          * during chip reset when the memory enable bit in the PCI command
6909          * register may be cleared.  The chip does not generate interrupt
6910          * at this time, but the irq handler may still be called due to irq
6911          * sharing or irqpoll.
6912          */
6913         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6914         for (i = 0; i < tp->irq_cnt; i++) {
6915                 struct tg3_napi *tnapi = &tp->napi[i];
6916                 if (tnapi->hw_status) {
6917                         tnapi->hw_status->status = 0;
6918                         tnapi->hw_status->status_tag = 0;
6919                 }
6920                 tnapi->last_tag = 0;
6921                 tnapi->last_irq_tag = 0;
6922         }
6923         smp_mb();
6924
6925         for (i = 0; i < tp->irq_cnt; i++)
6926                 synchronize_irq(tp->napi[i].irq_vec);
6927
6928         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6929                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6930                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6931         }
6932
6933         /* do the reset */
6934         val = GRC_MISC_CFG_CORECLK_RESET;
6935
6936         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6937                 /* Force PCIe 1.0a mode */
6938                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
6939                     !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
6940                     tr32(TG3_PCIE_PHY_TSTCTL) ==
6941                     (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
6942                         tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
6943
6944                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6945                         tw32(GRC_MISC_CFG, (1 << 29));
6946                         val |= (1 << 29);
6947                 }
6948         }
6949
6950         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6951                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6952                 tw32(GRC_VCPU_EXT_CTRL,
6953                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6954         }
6955
6956         /* Manage gphy power for all CPMU absent PCIe devices. */
6957         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6958             !(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
6959                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6960
6961         tw32(GRC_MISC_CFG, val);
6962
6963         /* restore 5701 hardware bug workaround write method */
6964         tp->write32 = write_op;
6965
6966         /* Unfortunately, we have to delay before the PCI read back.
6967          * Some 575X chips even will not respond to a PCI cfg access
6968          * when the reset command is given to the chip.
6969          *
6970          * How do these hardware designers expect things to work
6971          * properly if the PCI write is posted for a long period
6972          * of time?  It is always necessary to have some method by
6973          * which a register read back can occur to push the write
6974          * out which does the reset.
6975          *
6976          * For most tg3 variants the trick below was working.
6977          * Ho hum...
6978          */
6979         udelay(120);
6980
6981         /* Flush PCI posted writes.  The normal MMIO registers
6982          * are inaccessible at this time so this is the only
6983          * way to make this reliably (actually, this is no longer
6984          * the case, see above).  I tried to use indirect
6985          * register read/write but this upset some 5701 variants.
6986          */
6987         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6988
6989         udelay(120);
6990
6991         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6992                 u16 val16;
6993
6994                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6995                         int i;
6996                         u32 cfg_val;
6997
6998                         /* Wait for link training to complete.  */
6999                         for (i = 0; i < 5000; i++)
7000                                 udelay(100);
7001
7002                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
7003                         pci_write_config_dword(tp->pdev, 0xc4,
7004                                                cfg_val | (1 << 15));
7005                 }
7006
7007                 /* Clear the "no snoop" and "relaxed ordering" bits. */
7008                 pci_read_config_word(tp->pdev,
7009                                      tp->pcie_cap + PCI_EXP_DEVCTL,
7010                                      &val16);
7011                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
7012                            PCI_EXP_DEVCTL_NOSNOOP_EN);
7013                 /*
7014                  * Older PCIe devices only support the 128 byte
7015                  * MPS setting.  Enforce the restriction.
7016                  */
7017                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7018                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
7019                 pci_write_config_word(tp->pdev,
7020                                       tp->pcie_cap + PCI_EXP_DEVCTL,
7021                                       val16);
7022
7023                 pcie_set_readrq(tp->pdev, 4096);
7024
7025                 /* Clear error status */
7026                 pci_write_config_word(tp->pdev,
7027                                       tp->pcie_cap + PCI_EXP_DEVSTA,
7028                                       PCI_EXP_DEVSTA_CED |
7029                                       PCI_EXP_DEVSTA_NFED |
7030                                       PCI_EXP_DEVSTA_FED |
7031                                       PCI_EXP_DEVSTA_URD);
7032         }
7033
7034         tg3_restore_pci_state(tp);
7035
7036         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
7037
7038         val = 0;
7039         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
7040                 val = tr32(MEMARB_MODE);
7041         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7042
7043         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7044                 tg3_stop_fw(tp);
7045                 tw32(0x5000, 0x400);
7046         }
7047
7048         tw32(GRC_MODE, tp->grc_mode);
7049
7050         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
7051                 val = tr32(0xc4);
7052
7053                 tw32(0xc4, val | (1 << 15));
7054         }
7055
7056         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7057             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7058                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7059                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7060                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7061                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7062         }
7063
7064         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
7065                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
7066                 tw32_f(MAC_MODE, tp->mac_mode);
7067         } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
7068                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
7069                 tw32_f(MAC_MODE, tp->mac_mode);
7070         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7071                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
7072                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
7073                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
7074                 tw32_f(MAC_MODE, tp->mac_mode);
7075         } else
7076                 tw32_f(MAC_MODE, 0);
7077         udelay(40);
7078
7079         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7080
7081         err = tg3_poll_fw(tp);
7082         if (err)
7083                 return err;
7084
7085         tg3_mdio_start(tp);
7086
7087         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
7088             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7089             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7090             !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
7091                 val = tr32(0x7c00);
7092
7093                 tw32(0x7c00, val | (1 << 25));
7094         }
7095
7096         /* Reprobe ASF enable state.  */
7097         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7098         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7099         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7100         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7101                 u32 nic_cfg;
7102
7103                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7104                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7105                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7106                         tp->last_event_jiffies = jiffies;
7107                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7108                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7109                 }
7110         }
7111
7112         return 0;
7113 }
7114
7115 /* tp->lock is held. */
7116 static void tg3_stop_fw(struct tg3 *tp)
7117 {
7118         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7119            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7120                 /* Wait for RX cpu to ACK the previous event. */
7121                 tg3_wait_for_event_ack(tp);
7122
7123                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7124
7125                 tg3_generate_fw_event(tp);
7126
7127                 /* Wait for RX cpu to ACK this event. */
7128                 tg3_wait_for_event_ack(tp);
7129         }
7130 }
7131
7132 /* tp->lock is held. */
7133 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7134 {
7135         int err;
7136
7137         tg3_stop_fw(tp);
7138
7139         tg3_write_sig_pre_reset(tp, kind);
7140
7141         tg3_abort_hw(tp, silent);
7142         err = tg3_chip_reset(tp);
7143
7144         __tg3_set_mac_addr(tp, 0);
7145
7146         tg3_write_sig_legacy(tp, kind);
7147         tg3_write_sig_post_reset(tp, kind);
7148
7149         if (err)
7150                 return err;
7151
7152         return 0;
7153 }
7154
7155 #define RX_CPU_SCRATCH_BASE     0x30000
7156 #define RX_CPU_SCRATCH_SIZE     0x04000
7157 #define TX_CPU_SCRATCH_BASE     0x34000
7158 #define TX_CPU_SCRATCH_SIZE     0x04000
7159
7160 /* tp->lock is held. */
7161 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7162 {
7163         int i;
7164
7165         BUG_ON(offset == TX_CPU_BASE &&
7166             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7167
7168         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7169                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7170
7171                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7172                 return 0;
7173         }
7174         if (offset == RX_CPU_BASE) {
7175                 for (i = 0; i < 10000; i++) {
7176                         tw32(offset + CPU_STATE, 0xffffffff);
7177                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7178                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7179                                 break;
7180                 }
7181
7182                 tw32(offset + CPU_STATE, 0xffffffff);
7183                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
7184                 udelay(10);
7185         } else {
7186                 for (i = 0; i < 10000; i++) {
7187                         tw32(offset + CPU_STATE, 0xffffffff);
7188                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7189                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7190                                 break;
7191                 }
7192         }
7193
7194         if (i >= 10000) {
7195                 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7196                            __func__, offset == RX_CPU_BASE ? "RX" : "TX");
7197                 return -ENODEV;
7198         }
7199
7200         /* Clear firmware's nvram arbitration. */
7201         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7202                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7203         return 0;
7204 }
7205
7206 struct fw_info {
7207         unsigned int fw_base;
7208         unsigned int fw_len;
7209         const __be32 *fw_data;
7210 };
7211
7212 /* tp->lock is held. */
7213 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7214                                  int cpu_scratch_size, struct fw_info *info)
7215 {
7216         int err, lock_err, i;
7217         void (*write_op)(struct tg3 *, u32, u32);
7218
7219         if (cpu_base == TX_CPU_BASE &&
7220             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7221                 netdev_err(tp->dev,
7222                            "%s: Trying to load TX cpu firmware which is 5705\n",
7223                            __func__);
7224                 return -EINVAL;
7225         }
7226
7227         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7228                 write_op = tg3_write_mem;
7229         else
7230                 write_op = tg3_write_indirect_reg32;
7231
7232         /* It is possible that bootcode is still loading at this point.
7233          * Get the nvram lock first before halting the cpu.
7234          */
7235         lock_err = tg3_nvram_lock(tp);
7236         err = tg3_halt_cpu(tp, cpu_base);
7237         if (!lock_err)
7238                 tg3_nvram_unlock(tp);
7239         if (err)
7240                 goto out;
7241
7242         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7243                 write_op(tp, cpu_scratch_base + i, 0);
7244         tw32(cpu_base + CPU_STATE, 0xffffffff);
7245         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7246         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7247                 write_op(tp, (cpu_scratch_base +
7248                               (info->fw_base & 0xffff) +
7249                               (i * sizeof(u32))),
7250                               be32_to_cpu(info->fw_data[i]));
7251
7252         err = 0;
7253
7254 out:
7255         return err;
7256 }
7257
7258 /* tp->lock is held. */
7259 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7260 {
7261         struct fw_info info;
7262         const __be32 *fw_data;
7263         int err, i;
7264
7265         fw_data = (void *)tp->fw->data;
7266
7267         /* Firmware blob starts with version numbers, followed by
7268            start address and length. We are setting complete length.
7269            length = end_address_of_bss - start_address_of_text.
7270            Remainder is the blob to be loaded contiguously
7271            from start address. */
7272
7273         info.fw_base = be32_to_cpu(fw_data[1]);
7274         info.fw_len = tp->fw->size - 12;
7275         info.fw_data = &fw_data[3];
7276
7277         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7278                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7279                                     &info);
7280         if (err)
7281                 return err;
7282
7283         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7284                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7285                                     &info);
7286         if (err)
7287                 return err;
7288
7289         /* Now startup only the RX cpu. */
7290         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7291         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7292
7293         for (i = 0; i < 5; i++) {
7294                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7295                         break;
7296                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7297                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
7298                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7299                 udelay(1000);
7300         }
7301         if (i >= 5) {
7302                 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7303                            "should be %08x\n", __func__,
7304                            tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
7305                 return -ENODEV;
7306         }
7307         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7308         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
7309
7310         return 0;
7311 }
7312
7313 /* 5705 needs a special version of the TSO firmware.  */
7314
7315 /* tp->lock is held. */
7316 static int tg3_load_tso_firmware(struct tg3 *tp)
7317 {
7318         struct fw_info info;
7319         const __be32 *fw_data;
7320         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7321         int err, i;
7322
7323         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7324                 return 0;
7325
7326         fw_data = (void *)tp->fw->data;
7327
7328         /* Firmware blob starts with version numbers, followed by
7329            start address and length. We are setting complete length.
7330            length = end_address_of_bss - start_address_of_text.
7331            Remainder is the blob to be loaded contiguously
7332            from start address. */
7333
7334         info.fw_base = be32_to_cpu(fw_data[1]);
7335         cpu_scratch_size = tp->fw_len;
7336         info.fw_len = tp->fw->size - 12;
7337         info.fw_data = &fw_data[3];
7338
7339         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7340                 cpu_base = RX_CPU_BASE;
7341                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7342         } else {
7343                 cpu_base = TX_CPU_BASE;
7344                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7345                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7346         }
7347
7348         err = tg3_load_firmware_cpu(tp, cpu_base,
7349                                     cpu_scratch_base, cpu_scratch_size,
7350                                     &info);
7351         if (err)
7352                 return err;
7353
7354         /* Now startup the cpu. */
7355         tw32(cpu_base + CPU_STATE, 0xffffffff);
7356         tw32_f(cpu_base + CPU_PC, info.fw_base);
7357
7358         for (i = 0; i < 5; i++) {
7359                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7360                         break;
7361                 tw32(cpu_base + CPU_STATE, 0xffffffff);
7362                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
7363                 tw32_f(cpu_base + CPU_PC, info.fw_base);
7364                 udelay(1000);
7365         }
7366         if (i >= 5) {
7367                 netdev_err(tp->dev,
7368                            "%s fails to set CPU PC, is %08x should be %08x\n",
7369                            __func__, tr32(cpu_base + CPU_PC), info.fw_base);
7370                 return -ENODEV;
7371         }
7372         tw32(cpu_base + CPU_STATE, 0xffffffff);
7373         tw32_f(cpu_base + CPU_MODE,  0x00000000);
7374         return 0;
7375 }
7376
7377
7378 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7379 {
7380         struct tg3 *tp = netdev_priv(dev);
7381         struct sockaddr *addr = p;
7382         int err = 0, skip_mac_1 = 0;
7383
7384         if (!is_valid_ether_addr(addr->sa_data))
7385                 return -EINVAL;
7386
7387         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7388
7389         if (!netif_running(dev))
7390                 return 0;
7391
7392         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7393                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7394
7395                 addr0_high = tr32(MAC_ADDR_0_HIGH);
7396                 addr0_low = tr32(MAC_ADDR_0_LOW);
7397                 addr1_high = tr32(MAC_ADDR_1_HIGH);
7398                 addr1_low = tr32(MAC_ADDR_1_LOW);
7399
7400                 /* Skip MAC addr 1 if ASF is using it. */
7401                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7402                     !(addr1_high == 0 && addr1_low == 0))
7403                         skip_mac_1 = 1;
7404         }
7405         spin_lock_bh(&tp->lock);
7406         __tg3_set_mac_addr(tp, skip_mac_1);
7407         spin_unlock_bh(&tp->lock);
7408
7409         return err;
7410 }
7411
7412 /* tp->lock is held. */
7413 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7414                            dma_addr_t mapping, u32 maxlen_flags,
7415                            u32 nic_addr)
7416 {
7417         tg3_write_mem(tp,
7418                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7419                       ((u64) mapping >> 32));
7420         tg3_write_mem(tp,
7421                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7422                       ((u64) mapping & 0xffffffff));
7423         tg3_write_mem(tp,
7424                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7425                        maxlen_flags);
7426
7427         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7428                 tg3_write_mem(tp,
7429                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7430                               nic_addr);
7431 }
7432
7433 static void __tg3_set_rx_mode(struct net_device *);
7434 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7435 {
7436         int i;
7437
7438         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7439                 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7440                 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7441                 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7442         } else {
7443                 tw32(HOSTCC_TXCOL_TICKS, 0);
7444                 tw32(HOSTCC_TXMAX_FRAMES, 0);
7445                 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7446         }
7447
7448         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
7449                 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7450                 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7451                 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7452         } else {
7453                 tw32(HOSTCC_RXCOL_TICKS, 0);
7454                 tw32(HOSTCC_RXMAX_FRAMES, 0);
7455                 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7456         }
7457
7458         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7459                 u32 val = ec->stats_block_coalesce_usecs;
7460
7461                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7462                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7463
7464                 if (!netif_carrier_ok(tp->dev))
7465                         val = 0;
7466
7467                 tw32(HOSTCC_STAT_COAL_TICKS, val);
7468         }
7469
7470         for (i = 0; i < tp->irq_cnt - 1; i++) {
7471                 u32 reg;
7472
7473                 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7474                 tw32(reg, ec->rx_coalesce_usecs);
7475                 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7476                 tw32(reg, ec->rx_max_coalesced_frames);
7477                 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7478                 tw32(reg, ec->rx_max_coalesced_frames_irq);
7479
7480                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7481                         reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7482                         tw32(reg, ec->tx_coalesce_usecs);
7483                         reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7484                         tw32(reg, ec->tx_max_coalesced_frames);
7485                         reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7486                         tw32(reg, ec->tx_max_coalesced_frames_irq);
7487                 }
7488         }
7489
7490         for (; i < tp->irq_max - 1; i++) {
7491                 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7492                 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7493                 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7494
7495                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7496                         tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7497                         tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7498                         tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7499                 }
7500         }
7501 }
7502
7503 /* tp->lock is held. */
7504 static void tg3_rings_reset(struct tg3 *tp)
7505 {
7506         int i;
7507         u32 stblk, txrcb, rxrcb, limit;
7508         struct tg3_napi *tnapi = &tp->napi[0];
7509
7510         /* Disable all transmit rings but the first. */
7511         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7512                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7513         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7514                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7515         else
7516                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7517
7518         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7519              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7520                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7521                               BDINFO_FLAGS_DISABLED);
7522
7523
7524         /* Disable all receive return rings but the first. */
7525         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7526             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7527                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7528         else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7529                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7530         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7531                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7532                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7533         else
7534                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7535
7536         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7537              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7538                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7539                               BDINFO_FLAGS_DISABLED);
7540
7541         /* Disable interrupts */
7542         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7543
7544         /* Zero mailbox registers. */
7545         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7546                 for (i = 1; i < tp->irq_max; i++) {
7547                         tp->napi[i].tx_prod = 0;
7548                         tp->napi[i].tx_cons = 0;
7549                         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7550                                 tw32_mailbox(tp->napi[i].prodmbox, 0);
7551                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
7552                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7553                 }
7554                 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7555                         tw32_mailbox(tp->napi[0].prodmbox, 0);
7556         } else {
7557                 tp->napi[0].tx_prod = 0;
7558                 tp->napi[0].tx_cons = 0;
7559                 tw32_mailbox(tp->napi[0].prodmbox, 0);
7560                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7561         }
7562
7563         /* Make sure the NIC-based send BD rings are disabled. */
7564         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7565                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7566                 for (i = 0; i < 16; i++)
7567                         tw32_tx_mbox(mbox + i * 8, 0);
7568         }
7569
7570         txrcb = NIC_SRAM_SEND_RCB;
7571         rxrcb = NIC_SRAM_RCV_RET_RCB;
7572
7573         /* Clear status block in ram. */
7574         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7575
7576         /* Set status block DMA address */
7577         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7578              ((u64) tnapi->status_mapping >> 32));
7579         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7580              ((u64) tnapi->status_mapping & 0xffffffff));
7581
7582         if (tnapi->tx_ring) {
7583                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7584                                (TG3_TX_RING_SIZE <<
7585                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7586                                NIC_SRAM_TX_BUFFER_DESC);
7587                 txrcb += TG3_BDINFO_SIZE;
7588         }
7589
7590         if (tnapi->rx_rcb) {
7591                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7592                                (TG3_RX_RCB_RING_SIZE(tp) <<
7593                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7594                 rxrcb += TG3_BDINFO_SIZE;
7595         }
7596
7597         stblk = HOSTCC_STATBLCK_RING1;
7598
7599         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7600                 u64 mapping = (u64)tnapi->status_mapping;
7601                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7602                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7603
7604                 /* Clear status block in ram. */
7605                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7606
7607                 if (tnapi->tx_ring) {
7608                         tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7609                                        (TG3_TX_RING_SIZE <<
7610                                         BDINFO_FLAGS_MAXLEN_SHIFT),
7611                                        NIC_SRAM_TX_BUFFER_DESC);
7612                         txrcb += TG3_BDINFO_SIZE;
7613                 }
7614
7615                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7616                                (TG3_RX_RCB_RING_SIZE(tp) <<
7617                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7618
7619                 stblk += 8;
7620                 rxrcb += TG3_BDINFO_SIZE;
7621         }
7622 }
7623
7624 /* tp->lock is held. */
7625 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7626 {
7627         u32 val, rdmac_mode;
7628         int i, err, limit;
7629         struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
7630
7631         tg3_disable_ints(tp);
7632
7633         tg3_stop_fw(tp);
7634
7635         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7636
7637         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
7638                 tg3_abort_hw(tp, 1);
7639
7640         if (reset_phy)
7641                 tg3_phy_reset(tp);
7642
7643         err = tg3_chip_reset(tp);
7644         if (err)
7645                 return err;
7646
7647         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7648
7649         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7650                 val = tr32(TG3_CPMU_CTRL);
7651                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7652                 tw32(TG3_CPMU_CTRL, val);
7653
7654                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7655                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7656                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7657                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7658
7659                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7660                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7661                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7662                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7663
7664                 val = tr32(TG3_CPMU_HST_ACC);
7665                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7666                 val |= CPMU_HST_ACC_MACCLK_6_25;
7667                 tw32(TG3_CPMU_HST_ACC, val);
7668         }
7669
7670         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7671                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7672                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7673                        PCIE_PWR_MGMT_L1_THRESH_4MS;
7674                 tw32(PCIE_PWR_MGMT_THRESH, val);
7675
7676                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7677                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7678
7679                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7680
7681                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7682                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7683         }
7684
7685         if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7686                 u32 grc_mode = tr32(GRC_MODE);
7687
7688                 /* Access the lower 1K of PL PCIE block registers. */
7689                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7690                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7691
7692                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7693                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7694                      val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7695
7696                 tw32(GRC_MODE, grc_mode);
7697         }
7698
7699         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
7700                 u32 grc_mode = tr32(GRC_MODE);
7701
7702                 /* Access the lower 1K of PL PCIE block registers. */
7703                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7704                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7705
7706                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5);
7707                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
7708                      val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
7709
7710                 tw32(GRC_MODE, grc_mode);
7711
7712                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7713                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7714                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7715                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7716         }
7717
7718         /* This works around an issue with Athlon chipsets on
7719          * B3 tigon3 silicon.  This bit has no effect on any
7720          * other revision.  But do not set this on PCI Express
7721          * chips and don't even touch the clocks if the CPMU is present.
7722          */
7723         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7724                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7725                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7726                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7727         }
7728
7729         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7730             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7731                 val = tr32(TG3PCI_PCISTATE);
7732                 val |= PCISTATE_RETRY_SAME_DMA;
7733                 tw32(TG3PCI_PCISTATE, val);
7734         }
7735
7736         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7737                 /* Allow reads and writes to the
7738                  * APE register and memory space.
7739                  */
7740                 val = tr32(TG3PCI_PCISTATE);
7741                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7742                        PCISTATE_ALLOW_APE_SHMEM_WR |
7743                        PCISTATE_ALLOW_APE_PSPACE_WR;
7744                 tw32(TG3PCI_PCISTATE, val);
7745         }
7746
7747         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7748                 /* Enable some hw fixes.  */
7749                 val = tr32(TG3PCI_MSI_DATA);
7750                 val |= (1 << 26) | (1 << 28) | (1 << 29);
7751                 tw32(TG3PCI_MSI_DATA, val);
7752         }
7753
7754         /* Descriptor ring init may make accesses to the
7755          * NIC SRAM area to setup the TX descriptors, so we
7756          * can only do this after the hardware has been
7757          * successfully reset.
7758          */
7759         err = tg3_init_rings(tp);
7760         if (err)
7761                 return err;
7762
7763         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
7764                 val = tr32(TG3PCI_DMA_RW_CTRL) &
7765                       ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7766                 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
7767                         val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
7768                 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7769         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7770                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7771                 /* This value is determined during the probe time DMA
7772                  * engine test, tg3_test_dma.
7773                  */
7774                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7775         }
7776
7777         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7778                           GRC_MODE_4X_NIC_SEND_RINGS |
7779                           GRC_MODE_NO_TX_PHDR_CSUM |
7780                           GRC_MODE_NO_RX_PHDR_CSUM);
7781         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7782
7783         /* Pseudo-header checksum is done by hardware logic and not
7784          * the offload processers, so make the chip do the pseudo-
7785          * header checksums on receive.  For transmit it is more
7786          * convenient to do the pseudo-header checksum in software
7787          * as Linux does that on transmit for us in all cases.
7788          */
7789         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7790
7791         tw32(GRC_MODE,
7792              tp->grc_mode |
7793              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7794
7795         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7796         val = tr32(GRC_MISC_CFG);
7797         val &= ~0xff;
7798         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7799         tw32(GRC_MISC_CFG, val);
7800
7801         /* Initialize MBUF/DESC pool. */
7802         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7803                 /* Do nothing.  */
7804         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7805                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7806                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7807                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7808                 else
7809                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7810                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7811                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7812         } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7813                 int fw_len;
7814
7815                 fw_len = tp->fw_len;
7816                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7817                 tw32(BUFMGR_MB_POOL_ADDR,
7818                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7819                 tw32(BUFMGR_MB_POOL_SIZE,
7820                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7821         }
7822
7823         if (tp->dev->mtu <= ETH_DATA_LEN) {
7824                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7825                      tp->bufmgr_config.mbuf_read_dma_low_water);
7826                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7827                      tp->bufmgr_config.mbuf_mac_rx_low_water);
7828                 tw32(BUFMGR_MB_HIGH_WATER,
7829                      tp->bufmgr_config.mbuf_high_water);
7830         } else {
7831                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7832                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7833                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7834                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7835                 tw32(BUFMGR_MB_HIGH_WATER,
7836                      tp->bufmgr_config.mbuf_high_water_jumbo);
7837         }
7838         tw32(BUFMGR_DMA_LOW_WATER,
7839              tp->bufmgr_config.dma_low_water);
7840         tw32(BUFMGR_DMA_HIGH_WATER,
7841              tp->bufmgr_config.dma_high_water);
7842
7843         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7844         for (i = 0; i < 2000; i++) {
7845                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7846                         break;
7847                 udelay(10);
7848         }
7849         if (i >= 2000) {
7850                 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
7851                 return -ENODEV;
7852         }
7853
7854         /* Setup replenish threshold. */
7855         val = tp->rx_pending / 8;
7856         if (val == 0)
7857                 val = 1;
7858         else if (val > tp->rx_std_max_post)
7859                 val = tp->rx_std_max_post;
7860         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7861                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7862                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7863
7864                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7865                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7866         }
7867
7868         tw32(RCVBDI_STD_THRESH, val);
7869
7870         /* Initialize TG3_BDINFO's at:
7871          *  RCVDBDI_STD_BD:     standard eth size rx ring
7872          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
7873          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
7874          *
7875          * like so:
7876          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
7877          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
7878          *                              ring attribute flags
7879          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
7880          *
7881          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7882          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7883          *
7884          * The size of each ring is fixed in the firmware, but the location is
7885          * configurable.
7886          */
7887         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7888              ((u64) tpr->rx_std_mapping >> 32));
7889         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7890              ((u64) tpr->rx_std_mapping & 0xffffffff));
7891         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
7892             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
7893                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7894                      NIC_SRAM_RX_BUFFER_DESC);
7895
7896         /* Disable the mini ring */
7897         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7898                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7899                      BDINFO_FLAGS_DISABLED);
7900
7901         /* Program the jumbo buffer descriptor ring control
7902          * blocks on those devices that have them.
7903          */
7904         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7905             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7906                 /* Setup replenish threshold. */
7907                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7908
7909                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7910                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7911                              ((u64) tpr->rx_jmb_mapping >> 32));
7912                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7913                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7914                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7915                              (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7916                              BDINFO_FLAGS_USE_EXT_RECV);
7917                         if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) ||
7918                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7919                                 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7920                                      NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7921                 } else {
7922                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7923                              BDINFO_FLAGS_DISABLED);
7924                 }
7925
7926                 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
7927                         val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7928                               (TG3_RX_STD_DMA_SZ << 2);
7929                 else
7930                         val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
7931         } else
7932                 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7933
7934         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7935
7936         tpr->rx_std_prod_idx = tp->rx_pending;
7937         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
7938
7939         tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7940                           tp->rx_jumbo_pending : 0;
7941         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
7942
7943         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
7944                 tw32(STD_REPLENISH_LWM, 32);
7945                 tw32(JMB_REPLENISH_LWM, 16);
7946         }
7947
7948         tg3_rings_reset(tp);
7949
7950         /* Initialize MAC address and backoff seed. */
7951         __tg3_set_mac_addr(tp, 0);
7952
7953         /* MTU + ethernet header + FCS + optional VLAN tag */
7954         tw32(MAC_RX_MTU_SIZE,
7955              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7956
7957         /* The slot time is changed by tg3_setup_phy if we
7958          * run at gigabit with half duplex.
7959          */
7960         tw32(MAC_TX_LENGTHS,
7961              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7962              (6 << TX_LENGTHS_IPG_SHIFT) |
7963              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7964
7965         /* Receive rules. */
7966         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7967         tw32(RCVLPC_CONFIG, 0x0181);
7968
7969         /* Calculate RDMAC_MODE setting early, we need it to determine
7970          * the RCVLPC_STATE_ENABLE mask.
7971          */
7972         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7973                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7974                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7975                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7976                       RDMAC_MODE_LNGREAD_ENAB);
7977
7978         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7979             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7980                 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
7981
7982         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7983             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7984             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7985                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7986                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7987                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7988
7989         /* If statement applies to 5705 and 5750 PCI devices only */
7990         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7991              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7992             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7993                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7994                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7995                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7996                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7997                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7998                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7999                 }
8000         }
8001
8002         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
8003                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8004
8005         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8006                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8007
8008         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
8009             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8010             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8011                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
8012
8013         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8014             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8015             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8016             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
8017             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
8018                 val = tr32(TG3_RDMA_RSRVCTRL_REG);
8019                 tw32(TG3_RDMA_RSRVCTRL_REG,
8020                      val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
8021         }
8022
8023         /* Receive/send statistics. */
8024         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
8025                 val = tr32(RCVLPC_STATS_ENABLE);
8026                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8027                 tw32(RCVLPC_STATS_ENABLE, val);
8028         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8029                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8030                 val = tr32(RCVLPC_STATS_ENABLE);
8031                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8032                 tw32(RCVLPC_STATS_ENABLE, val);
8033         } else {
8034                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8035         }
8036         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8037         tw32(SNDDATAI_STATSENAB, 0xffffff);
8038         tw32(SNDDATAI_STATSCTRL,
8039              (SNDDATAI_SCTRL_ENABLE |
8040               SNDDATAI_SCTRL_FASTUPD));
8041
8042         /* Setup host coalescing engine. */
8043         tw32(HOSTCC_MODE, 0);
8044         for (i = 0; i < 2000; i++) {
8045                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8046                         break;
8047                 udelay(10);
8048         }
8049
8050         __tg3_set_coalesce(tp, &tp->coal);
8051
8052         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8053                 /* Status/statistics block address.  See tg3_timer,
8054                  * the tg3_periodic_fetch_stats call there, and
8055                  * tg3_get_stats to see how this works for 5705/5750 chips.
8056                  */
8057                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8058                      ((u64) tp->stats_mapping >> 32));
8059                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8060                      ((u64) tp->stats_mapping & 0xffffffff));
8061                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8062
8063                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
8064
8065                 /* Clear statistics and status block memory areas */
8066                 for (i = NIC_SRAM_STATS_BLK;
8067                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8068                      i += sizeof(u32)) {
8069                         tg3_write_mem(tp, i, 0);
8070                         udelay(40);
8071                 }
8072         }
8073
8074         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8075
8076         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8077         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8078         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8079                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8080
8081         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
8082                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
8083                 /* reset to prevent losing 1st rx packet intermittently */
8084                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8085                 udelay(10);
8086         }
8087
8088         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8089                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8090         else
8091                 tp->mac_mode = 0;
8092         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8093                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
8094         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8095             !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8096             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8097                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8098         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8099         udelay(40);
8100
8101         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8102          * If TG3_FLG2_IS_NIC is zero, we should read the
8103          * register to preserve the GPIO settings for LOMs. The GPIOs,
8104          * whether used as inputs or outputs, are set by boot code after
8105          * reset.
8106          */
8107         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
8108                 u32 gpio_mask;
8109
8110                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8111                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8112                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8113
8114                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8115                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8116                                      GRC_LCLCTRL_GPIO_OUTPUT3;
8117
8118                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8119                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8120
8121                 tp->grc_local_ctrl &= ~gpio_mask;
8122                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8123
8124                 /* GPIO1 must be driven high for eeprom write protect */
8125                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8126                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8127                                                GRC_LCLCTRL_GPIO_OUTPUT1);
8128         }
8129         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8130         udelay(100);
8131
8132         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
8133                 val = tr32(MSGINT_MODE);
8134                 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8135                 tw32(MSGINT_MODE, val);
8136         }
8137
8138         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8139                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8140                 udelay(40);
8141         }
8142
8143         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8144                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8145                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8146                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8147                WDMAC_MODE_LNGREAD_ENAB);
8148
8149         /* If statement applies to 5705 and 5750 PCI devices only */
8150         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8151              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8152             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
8153                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8154                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8155                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8156                         /* nothing */
8157                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8158                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8159                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8160                         val |= WDMAC_MODE_RX_ACCEL;
8161                 }
8162         }
8163
8164         /* Enable host coalescing bug fix */
8165         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8166                 val |= WDMAC_MODE_STATUS_TAG_FIX;
8167
8168         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8169                 val |= WDMAC_MODE_BURST_ALL_DATA;
8170
8171         tw32_f(WDMAC_MODE, val);
8172         udelay(40);
8173
8174         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8175                 u16 pcix_cmd;
8176
8177                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8178                                      &pcix_cmd);
8179                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8180                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8181                         pcix_cmd |= PCI_X_CMD_READ_2K;
8182                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8183                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8184                         pcix_cmd |= PCI_X_CMD_READ_2K;
8185                 }
8186                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8187                                       pcix_cmd);
8188         }
8189
8190         tw32_f(RDMAC_MODE, rdmac_mode);
8191         udelay(40);
8192
8193         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8194         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8195                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8196
8197         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8198                 tw32(SNDDATAC_MODE,
8199                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8200         else
8201                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8202
8203         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8204         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8205         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8206         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8207         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8208                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8209         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8210         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8211                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8212         tw32(SNDBDI_MODE, val);
8213         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8214
8215         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8216                 err = tg3_load_5701_a0_firmware_fix(tp);
8217                 if (err)
8218                         return err;
8219         }
8220
8221         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8222                 err = tg3_load_tso_firmware(tp);
8223                 if (err)
8224                         return err;
8225         }
8226
8227         tp->tx_mode = TX_MODE_ENABLE;
8228         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
8229             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8230                 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
8231         tw32_f(MAC_TX_MODE, tp->tx_mode);
8232         udelay(100);
8233
8234         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8235                 u32 reg = MAC_RSS_INDIR_TBL_0;
8236                 u8 *ent = (u8 *)&val;
8237
8238                 /* Setup the indirection table */
8239                 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8240                         int idx = i % sizeof(val);
8241
8242                         ent[idx] = i % (tp->irq_cnt - 1);
8243                         if (idx == sizeof(val) - 1) {
8244                                 tw32(reg, val);
8245                                 reg += 4;
8246                         }
8247                 }
8248
8249                 /* Setup the "secret" hash key. */
8250                 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8251                 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8252                 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8253                 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8254                 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8255                 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8256                 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8257                 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8258                 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8259                 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8260         }
8261
8262         tp->rx_mode = RX_MODE_ENABLE;
8263         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8264                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8265
8266         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8267                 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8268                                RX_MODE_RSS_ITBL_HASH_BITS_7 |
8269                                RX_MODE_RSS_IPV6_HASH_EN |
8270                                RX_MODE_RSS_TCP_IPV6_HASH_EN |
8271                                RX_MODE_RSS_IPV4_HASH_EN |
8272                                RX_MODE_RSS_TCP_IPV4_HASH_EN;
8273
8274         tw32_f(MAC_RX_MODE, tp->rx_mode);
8275         udelay(10);
8276
8277         tw32(MAC_LED_CTRL, tp->led_ctrl);
8278
8279         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8280         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8281                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8282                 udelay(10);
8283         }
8284         tw32_f(MAC_RX_MODE, tp->rx_mode);
8285         udelay(10);
8286
8287         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8288                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8289                         !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
8290                         /* Set drive transmission level to 1.2V  */
8291                         /* only if the signal pre-emphasis bit is not set  */
8292                         val = tr32(MAC_SERDES_CFG);
8293                         val &= 0xfffff000;
8294                         val |= 0x880;
8295                         tw32(MAC_SERDES_CFG, val);
8296                 }
8297                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8298                         tw32(MAC_SERDES_CFG, 0x616000);
8299         }
8300
8301         /* Prevent chip from dropping frames when flow control
8302          * is enabled.
8303          */
8304         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8305                 val = 1;
8306         else
8307                 val = 2;
8308         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8309
8310         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8311             (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
8312                 /* Use hardware link auto-negotiation */
8313                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8314         }
8315
8316         if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8317             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8318                 u32 tmp;
8319
8320                 tmp = tr32(SERDES_RX_CTRL);
8321                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8322                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8323                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8324                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8325         }
8326
8327         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8328                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
8329                         tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
8330                         tp->link_config.speed = tp->link_config.orig_speed;
8331                         tp->link_config.duplex = tp->link_config.orig_duplex;
8332                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
8333                 }
8334
8335                 err = tg3_setup_phy(tp, 0);
8336                 if (err)
8337                         return err;
8338
8339                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8340                     !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8341                         u32 tmp;
8342
8343                         /* Clear CRC stats. */
8344                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8345                                 tg3_writephy(tp, MII_TG3_TEST1,
8346                                              tmp | MII_TG3_TEST1_CRC_EN);
8347                                 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
8348                         }
8349                 }
8350         }
8351
8352         __tg3_set_rx_mode(tp->dev);
8353
8354         /* Initialize receive rules. */
8355         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
8356         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8357         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
8358         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8359
8360         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8361             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8362                 limit = 8;
8363         else
8364                 limit = 16;
8365         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8366                 limit -= 4;
8367         switch (limit) {
8368         case 16:
8369                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
8370         case 15:
8371                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
8372         case 14:
8373                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
8374         case 13:
8375                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
8376         case 12:
8377                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
8378         case 11:
8379                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
8380         case 10:
8381                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
8382         case 9:
8383                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
8384         case 8:
8385                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
8386         case 7:
8387                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
8388         case 6:
8389                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
8390         case 5:
8391                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
8392         case 4:
8393                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
8394         case 3:
8395                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
8396         case 2:
8397         case 1:
8398
8399         default:
8400                 break;
8401         }
8402
8403         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8404                 /* Write our heartbeat update interval to APE. */
8405                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8406                                 APE_HOST_HEARTBEAT_INT_DISABLE);
8407
8408         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8409
8410         return 0;
8411 }
8412
8413 /* Called at device open time to get the chip ready for
8414  * packet processing.  Invoked with tp->lock held.
8415  */
8416 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8417 {
8418         tg3_switch_clocks(tp);
8419
8420         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8421
8422         return tg3_reset_hw(tp, reset_phy);
8423 }
8424
8425 #define TG3_STAT_ADD32(PSTAT, REG) \
8426 do {    u32 __val = tr32(REG); \
8427         (PSTAT)->low += __val; \
8428         if ((PSTAT)->low < __val) \
8429                 (PSTAT)->high += 1; \
8430 } while (0)
8431
8432 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8433 {
8434         struct tg3_hw_stats *sp = tp->hw_stats;
8435
8436         if (!netif_carrier_ok(tp->dev))
8437                 return;
8438
8439         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8440         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8441         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8442         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8443         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8444         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8445         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8446         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8447         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8448         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8449         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8450         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8451         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8452
8453         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8454         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8455         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8456         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8457         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8458         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8459         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8460         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8461         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8462         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8463         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8464         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8465         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8466         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8467
8468         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8469         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8470         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8471 }
8472
8473 static void tg3_timer(unsigned long __opaque)
8474 {
8475         struct tg3 *tp = (struct tg3 *) __opaque;
8476
8477         if (tp->irq_sync)
8478                 goto restart_timer;
8479
8480         spin_lock(&tp->lock);
8481
8482         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8483                 /* All of this garbage is because when using non-tagged
8484                  * IRQ status the mailbox/status_block protocol the chip
8485                  * uses with the cpu is race prone.
8486                  */
8487                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8488                         tw32(GRC_LOCAL_CTRL,
8489                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8490                 } else {
8491                         tw32(HOSTCC_MODE, tp->coalesce_mode |
8492                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8493                 }
8494
8495                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8496                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8497                         spin_unlock(&tp->lock);
8498                         schedule_work(&tp->reset_task);
8499                         return;
8500                 }
8501         }
8502
8503         /* This part only runs once per second. */
8504         if (!--tp->timer_counter) {
8505                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8506                         tg3_periodic_fetch_stats(tp);
8507
8508                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8509                         u32 mac_stat;
8510                         int phy_event;
8511
8512                         mac_stat = tr32(MAC_STATUS);
8513
8514                         phy_event = 0;
8515                         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
8516                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8517                                         phy_event = 1;
8518                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8519                                 phy_event = 1;
8520
8521                         if (phy_event)
8522                                 tg3_setup_phy(tp, 0);
8523                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8524                         u32 mac_stat = tr32(MAC_STATUS);
8525                         int need_setup = 0;
8526
8527                         if (netif_carrier_ok(tp->dev) &&
8528                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8529                                 need_setup = 1;
8530                         }
8531                         if (!netif_carrier_ok(tp->dev) &&
8532                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
8533                                          MAC_STATUS_SIGNAL_DET))) {
8534                                 need_setup = 1;
8535                         }
8536                         if (need_setup) {
8537                                 if (!tp->serdes_counter) {
8538                                         tw32_f(MAC_MODE,
8539                                              (tp->mac_mode &
8540                                               ~MAC_MODE_PORT_MODE_MASK));
8541                                         udelay(40);
8542                                         tw32_f(MAC_MODE, tp->mac_mode);
8543                                         udelay(40);
8544                                 }
8545                                 tg3_setup_phy(tp, 0);
8546                         }
8547                 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8548                            (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8549                         tg3_serdes_parallel_detect(tp);
8550                 }
8551
8552                 tp->timer_counter = tp->timer_multiplier;
8553         }
8554
8555         /* Heartbeat is only sent once every 2 seconds.
8556          *
8557          * The heartbeat is to tell the ASF firmware that the host
8558          * driver is still alive.  In the event that the OS crashes,
8559          * ASF needs to reset the hardware to free up the FIFO space
8560          * that may be filled with rx packets destined for the host.
8561          * If the FIFO is full, ASF will no longer function properly.
8562          *
8563          * Unintended resets have been reported on real time kernels
8564          * where the timer doesn't run on time.  Netpoll will also have
8565          * same problem.
8566          *
8567          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8568          * to check the ring condition when the heartbeat is expiring
8569          * before doing the reset.  This will prevent most unintended
8570          * resets.
8571          */
8572         if (!--tp->asf_counter) {
8573                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8574                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8575                         tg3_wait_for_event_ack(tp);
8576
8577                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8578                                       FWCMD_NICDRV_ALIVE3);
8579                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8580                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
8581                                       TG3_FW_UPDATE_TIMEOUT_SEC);
8582
8583                         tg3_generate_fw_event(tp);
8584                 }
8585                 tp->asf_counter = tp->asf_multiplier;
8586         }
8587
8588         spin_unlock(&tp->lock);
8589
8590 restart_timer:
8591         tp->timer.expires = jiffies + tp->timer_offset;
8592         add_timer(&tp->timer);
8593 }
8594
8595 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8596 {
8597         irq_handler_t fn;
8598         unsigned long flags;
8599         char *name;
8600         struct tg3_napi *tnapi = &tp->napi[irq_num];
8601
8602         if (tp->irq_cnt == 1)
8603                 name = tp->dev->name;
8604         else {
8605                 name = &tnapi->irq_lbl[0];
8606                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8607                 name[IFNAMSIZ-1] = 0;
8608         }
8609
8610         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8611                 fn = tg3_msi;
8612                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8613                         fn = tg3_msi_1shot;
8614                 flags = IRQF_SAMPLE_RANDOM;
8615         } else {
8616                 fn = tg3_interrupt;
8617                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8618                         fn = tg3_interrupt_tagged;
8619                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8620         }
8621
8622         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8623 }
8624
8625 static int tg3_test_interrupt(struct tg3 *tp)
8626 {
8627         struct tg3_napi *tnapi = &tp->napi[0];
8628         struct net_device *dev = tp->dev;
8629         int err, i, intr_ok = 0;
8630         u32 val;
8631
8632         if (!netif_running(dev))
8633                 return -ENODEV;
8634
8635         tg3_disable_ints(tp);
8636
8637         free_irq(tnapi->irq_vec, tnapi);
8638
8639         /*
8640          * Turn off MSI one shot mode.  Otherwise this test has no
8641          * observable way to know whether the interrupt was delivered.
8642          */
8643         if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8644             (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8645                 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8646                 tw32(MSGINT_MODE, val);
8647         }
8648
8649         err = request_irq(tnapi->irq_vec, tg3_test_isr,
8650                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8651         if (err)
8652                 return err;
8653
8654         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8655         tg3_enable_ints(tp);
8656
8657         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8658                tnapi->coal_now);
8659
8660         for (i = 0; i < 5; i++) {
8661                 u32 int_mbox, misc_host_ctrl;
8662
8663                 int_mbox = tr32_mailbox(tnapi->int_mbox);
8664                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8665
8666                 if ((int_mbox != 0) ||
8667                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8668                         intr_ok = 1;
8669                         break;
8670                 }
8671
8672                 msleep(10);
8673         }
8674
8675         tg3_disable_ints(tp);
8676
8677         free_irq(tnapi->irq_vec, tnapi);
8678
8679         err = tg3_request_irq(tp, 0);
8680
8681         if (err)
8682                 return err;
8683
8684         if (intr_ok) {
8685                 /* Reenable MSI one shot mode. */
8686                 if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8687                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8688                         val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8689                         tw32(MSGINT_MODE, val);
8690                 }
8691                 return 0;
8692         }
8693
8694         return -EIO;
8695 }
8696
8697 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8698  * successfully restored
8699  */
8700 static int tg3_test_msi(struct tg3 *tp)
8701 {
8702         int err;
8703         u16 pci_cmd;
8704
8705         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8706                 return 0;
8707
8708         /* Turn off SERR reporting in case MSI terminates with Master
8709          * Abort.
8710          */
8711         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8712         pci_write_config_word(tp->pdev, PCI_COMMAND,
8713                               pci_cmd & ~PCI_COMMAND_SERR);
8714
8715         err = tg3_test_interrupt(tp);
8716
8717         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8718
8719         if (!err)
8720                 return 0;
8721
8722         /* other failures */
8723         if (err != -EIO)
8724                 return err;
8725
8726         /* MSI test failed, go back to INTx mode */
8727         netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
8728                     "to INTx mode. Please report this failure to the PCI "
8729                     "maintainer and include system chipset information\n");
8730
8731         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8732
8733         pci_disable_msi(tp->pdev);
8734
8735         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8736         tp->napi[0].irq_vec = tp->pdev->irq;
8737
8738         err = tg3_request_irq(tp, 0);
8739         if (err)
8740                 return err;
8741
8742         /* Need to reset the chip because the MSI cycle may have terminated
8743          * with Master Abort.
8744          */
8745         tg3_full_lock(tp, 1);
8746
8747         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8748         err = tg3_init_hw(tp, 1);
8749
8750         tg3_full_unlock(tp);
8751
8752         if (err)
8753                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8754
8755         return err;
8756 }
8757
8758 static int tg3_request_firmware(struct tg3 *tp)
8759 {
8760         const __be32 *fw_data;
8761
8762         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8763                 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
8764                            tp->fw_needed);
8765                 return -ENOENT;
8766         }
8767
8768         fw_data = (void *)tp->fw->data;
8769
8770         /* Firmware blob starts with version numbers, followed by
8771          * start address and _full_ length including BSS sections
8772          * (which must be longer than the actual data, of course
8773          */
8774
8775         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
8776         if (tp->fw_len < (tp->fw->size - 12)) {
8777                 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
8778                            tp->fw_len, tp->fw_needed);
8779                 release_firmware(tp->fw);
8780                 tp->fw = NULL;
8781                 return -EINVAL;
8782         }
8783
8784         /* We no longer need firmware; we have it. */
8785         tp->fw_needed = NULL;
8786         return 0;
8787 }
8788
8789 static bool tg3_enable_msix(struct tg3 *tp)
8790 {
8791         int i, rc, cpus = num_online_cpus();
8792         struct msix_entry msix_ent[tp->irq_max];
8793
8794         if (cpus == 1)
8795                 /* Just fallback to the simpler MSI mode. */
8796                 return false;
8797
8798         /*
8799          * We want as many rx rings enabled as there are cpus.
8800          * The first MSIX vector only deals with link interrupts, etc,
8801          * so we add one to the number of vectors we are requesting.
8802          */
8803         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8804
8805         for (i = 0; i < tp->irq_max; i++) {
8806                 msix_ent[i].entry  = i;
8807                 msix_ent[i].vector = 0;
8808         }
8809
8810         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8811         if (rc < 0) {
8812                 return false;
8813         } else if (rc != 0) {
8814                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8815                         return false;
8816                 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
8817                               tp->irq_cnt, rc);
8818                 tp->irq_cnt = rc;
8819         }
8820
8821         for (i = 0; i < tp->irq_max; i++)
8822                 tp->napi[i].irq_vec = msix_ent[i].vector;
8823
8824         tp->dev->real_num_tx_queues = 1;
8825         if (tp->irq_cnt > 1)
8826                 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8827
8828         return true;
8829 }
8830
8831 static void tg3_ints_init(struct tg3 *tp)
8832 {
8833         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8834             !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8835                 /* All MSI supporting chips should support tagged
8836                  * status.  Assert that this is the case.
8837                  */
8838                 netdev_warn(tp->dev,
8839                             "MSI without TAGGED_STATUS? Not using MSI\n");
8840                 goto defcfg;
8841         }
8842
8843         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8844                 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8845         else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8846                  pci_enable_msi(tp->pdev) == 0)
8847                 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8848
8849         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8850                 u32 msi_mode = tr32(MSGINT_MODE);
8851                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8852                         msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8853                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8854         }
8855 defcfg:
8856         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8857                 tp->irq_cnt = 1;
8858                 tp->napi[0].irq_vec = tp->pdev->irq;
8859                 tp->dev->real_num_tx_queues = 1;
8860         }
8861 }
8862
8863 static void tg3_ints_fini(struct tg3 *tp)
8864 {
8865         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8866                 pci_disable_msix(tp->pdev);
8867         else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8868                 pci_disable_msi(tp->pdev);
8869         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8870         tp->tg3_flags3 &= ~(TG3_FLG3_ENABLE_RSS | TG3_FLG3_ENABLE_TSS);
8871 }
8872
8873 static int tg3_open(struct net_device *dev)
8874 {
8875         struct tg3 *tp = netdev_priv(dev);
8876         int i, err;
8877
8878         if (tp->fw_needed) {
8879                 err = tg3_request_firmware(tp);
8880                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8881                         if (err)
8882                                 return err;
8883                 } else if (err) {
8884                         netdev_warn(tp->dev, "TSO capability disabled\n");
8885                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8886                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8887                         netdev_notice(tp->dev, "TSO capability restored\n");
8888                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8889                 }
8890         }
8891
8892         netif_carrier_off(tp->dev);
8893
8894         err = tg3_set_power_state(tp, PCI_D0);
8895         if (err)
8896                 return err;
8897
8898         tg3_full_lock(tp, 0);
8899
8900         tg3_disable_ints(tp);
8901         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8902
8903         tg3_full_unlock(tp);
8904
8905         /*
8906          * Setup interrupts first so we know how
8907          * many NAPI resources to allocate
8908          */
8909         tg3_ints_init(tp);
8910
8911         /* The placement of this call is tied
8912          * to the setup and use of Host TX descriptors.
8913          */
8914         err = tg3_alloc_consistent(tp);
8915         if (err)
8916                 goto err_out1;
8917
8918         tg3_napi_enable(tp);
8919
8920         for (i = 0; i < tp->irq_cnt; i++) {
8921                 struct tg3_napi *tnapi = &tp->napi[i];
8922                 err = tg3_request_irq(tp, i);
8923                 if (err) {
8924                         for (i--; i >= 0; i--)
8925                                 free_irq(tnapi->irq_vec, tnapi);
8926                         break;
8927                 }
8928         }
8929
8930         if (err)
8931                 goto err_out2;
8932
8933         tg3_full_lock(tp, 0);
8934
8935         err = tg3_init_hw(tp, 1);
8936         if (err) {
8937                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8938                 tg3_free_rings(tp);
8939         } else {
8940                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8941                         tp->timer_offset = HZ;
8942                 else
8943                         tp->timer_offset = HZ / 10;
8944
8945                 BUG_ON(tp->timer_offset > HZ);
8946                 tp->timer_counter = tp->timer_multiplier =
8947                         (HZ / tp->timer_offset);
8948                 tp->asf_counter = tp->asf_multiplier =
8949                         ((HZ / tp->timer_offset) * 2);
8950
8951                 init_timer(&tp->timer);
8952                 tp->timer.expires = jiffies + tp->timer_offset;
8953                 tp->timer.data = (unsigned long) tp;
8954                 tp->timer.function = tg3_timer;
8955         }
8956
8957         tg3_full_unlock(tp);
8958
8959         if (err)
8960                 goto err_out3;
8961
8962         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8963                 err = tg3_test_msi(tp);
8964
8965                 if (err) {
8966                         tg3_full_lock(tp, 0);
8967                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8968                         tg3_free_rings(tp);
8969                         tg3_full_unlock(tp);
8970
8971                         goto err_out2;
8972                 }
8973
8974                 if (!(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8975                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8976                         u32 val = tr32(PCIE_TRANSACTION_CFG);
8977
8978                         tw32(PCIE_TRANSACTION_CFG,
8979                              val | PCIE_TRANS_CFG_1SHOT_MSI);
8980                 }
8981         }
8982
8983         tg3_phy_start(tp);
8984
8985         tg3_full_lock(tp, 0);
8986
8987         add_timer(&tp->timer);
8988         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8989         tg3_enable_ints(tp);
8990
8991         tg3_full_unlock(tp);
8992
8993         netif_tx_start_all_queues(dev);
8994
8995         return 0;
8996
8997 err_out3:
8998         for (i = tp->irq_cnt - 1; i >= 0; i--) {
8999                 struct tg3_napi *tnapi = &tp->napi[i];
9000                 free_irq(tnapi->irq_vec, tnapi);
9001         }
9002
9003 err_out2:
9004         tg3_napi_disable(tp);
9005         tg3_free_consistent(tp);
9006
9007 err_out1:
9008         tg3_ints_fini(tp);
9009         return err;
9010 }
9011
9012 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
9013                                                  struct rtnl_link_stats64 *);
9014 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9015
9016 static int tg3_close(struct net_device *dev)
9017 {
9018         int i;
9019         struct tg3 *tp = netdev_priv(dev);
9020
9021         tg3_napi_disable(tp);
9022         cancel_work_sync(&tp->reset_task);
9023
9024         netif_tx_stop_all_queues(dev);
9025
9026         del_timer_sync(&tp->timer);
9027
9028         tg3_phy_stop(tp);
9029
9030         tg3_full_lock(tp, 1);
9031
9032         tg3_disable_ints(tp);
9033
9034         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9035         tg3_free_rings(tp);
9036         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9037
9038         tg3_full_unlock(tp);
9039
9040         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9041                 struct tg3_napi *tnapi = &tp->napi[i];
9042                 free_irq(tnapi->irq_vec, tnapi);
9043         }
9044
9045         tg3_ints_fini(tp);
9046
9047         tg3_get_stats64(tp->dev, &tp->net_stats_prev);
9048
9049         memcpy(&tp->estats_prev, tg3_get_estats(tp),
9050                sizeof(tp->estats_prev));
9051
9052         tg3_free_consistent(tp);
9053
9054         tg3_set_power_state(tp, PCI_D3hot);
9055
9056         netif_carrier_off(tp->dev);
9057
9058         return 0;
9059 }
9060
9061 static inline u64 get_stat64(tg3_stat64_t *val)
9062 {
9063        return ((u64)val->high << 32) | ((u64)val->low);
9064 }
9065
9066 static u64 calc_crc_errors(struct tg3 *tp)
9067 {
9068         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9069
9070         if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9071             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9072              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9073                 u32 val;
9074
9075                 spin_lock_bh(&tp->lock);
9076                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9077                         tg3_writephy(tp, MII_TG3_TEST1,
9078                                      val | MII_TG3_TEST1_CRC_EN);
9079                         tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
9080                 } else
9081                         val = 0;
9082                 spin_unlock_bh(&tp->lock);
9083
9084                 tp->phy_crc_errors += val;
9085
9086                 return tp->phy_crc_errors;
9087         }
9088
9089         return get_stat64(&hw_stats->rx_fcs_errors);
9090 }
9091
9092 #define ESTAT_ADD(member) \
9093         estats->member =        old_estats->member + \
9094                                 get_stat64(&hw_stats->member)
9095
9096 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9097 {
9098         struct tg3_ethtool_stats *estats = &tp->estats;
9099         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9100         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9101
9102         if (!hw_stats)
9103                 return old_estats;
9104
9105         ESTAT_ADD(rx_octets);
9106         ESTAT_ADD(rx_fragments);
9107         ESTAT_ADD(rx_ucast_packets);
9108         ESTAT_ADD(rx_mcast_packets);
9109         ESTAT_ADD(rx_bcast_packets);
9110         ESTAT_ADD(rx_fcs_errors);
9111         ESTAT_ADD(rx_align_errors);
9112         ESTAT_ADD(rx_xon_pause_rcvd);
9113         ESTAT_ADD(rx_xoff_pause_rcvd);
9114         ESTAT_ADD(rx_mac_ctrl_rcvd);
9115         ESTAT_ADD(rx_xoff_entered);
9116         ESTAT_ADD(rx_frame_too_long_errors);
9117         ESTAT_ADD(rx_jabbers);
9118         ESTAT_ADD(rx_undersize_packets);
9119         ESTAT_ADD(rx_in_length_errors);
9120         ESTAT_ADD(rx_out_length_errors);
9121         ESTAT_ADD(rx_64_or_less_octet_packets);
9122         ESTAT_ADD(rx_65_to_127_octet_packets);
9123         ESTAT_ADD(rx_128_to_255_octet_packets);
9124         ESTAT_ADD(rx_256_to_511_octet_packets);
9125         ESTAT_ADD(rx_512_to_1023_octet_packets);
9126         ESTAT_ADD(rx_1024_to_1522_octet_packets);
9127         ESTAT_ADD(rx_1523_to_2047_octet_packets);
9128         ESTAT_ADD(rx_2048_to_4095_octet_packets);
9129         ESTAT_ADD(rx_4096_to_8191_octet_packets);
9130         ESTAT_ADD(rx_8192_to_9022_octet_packets);
9131
9132         ESTAT_ADD(tx_octets);
9133         ESTAT_ADD(tx_collisions);
9134         ESTAT_ADD(tx_xon_sent);
9135         ESTAT_ADD(tx_xoff_sent);
9136         ESTAT_ADD(tx_flow_control);
9137         ESTAT_ADD(tx_mac_errors);
9138         ESTAT_ADD(tx_single_collisions);
9139         ESTAT_ADD(tx_mult_collisions);
9140         ESTAT_ADD(tx_deferred);
9141         ESTAT_ADD(tx_excessive_collisions);
9142         ESTAT_ADD(tx_late_collisions);
9143         ESTAT_ADD(tx_collide_2times);
9144         ESTAT_ADD(tx_collide_3times);
9145         ESTAT_ADD(tx_collide_4times);
9146         ESTAT_ADD(tx_collide_5times);
9147         ESTAT_ADD(tx_collide_6times);
9148         ESTAT_ADD(tx_collide_7times);
9149         ESTAT_ADD(tx_collide_8times);
9150         ESTAT_ADD(tx_collide_9times);
9151         ESTAT_ADD(tx_collide_10times);
9152         ESTAT_ADD(tx_collide_11times);
9153         ESTAT_ADD(tx_collide_12times);
9154         ESTAT_ADD(tx_collide_13times);
9155         ESTAT_ADD(tx_collide_14times);
9156         ESTAT_ADD(tx_collide_15times);
9157         ESTAT_ADD(tx_ucast_packets);
9158         ESTAT_ADD(tx_mcast_packets);
9159         ESTAT_ADD(tx_bcast_packets);
9160         ESTAT_ADD(tx_carrier_sense_errors);
9161         ESTAT_ADD(tx_discards);
9162         ESTAT_ADD(tx_errors);
9163
9164         ESTAT_ADD(dma_writeq_full);
9165         ESTAT_ADD(dma_write_prioq_full);
9166         ESTAT_ADD(rxbds_empty);
9167         ESTAT_ADD(rx_discards);
9168         ESTAT_ADD(rx_errors);
9169         ESTAT_ADD(rx_threshold_hit);
9170
9171         ESTAT_ADD(dma_readq_full);
9172         ESTAT_ADD(dma_read_prioq_full);
9173         ESTAT_ADD(tx_comp_queue_full);
9174
9175         ESTAT_ADD(ring_set_send_prod_index);
9176         ESTAT_ADD(ring_status_update);
9177         ESTAT_ADD(nic_irqs);
9178         ESTAT_ADD(nic_avoided_irqs);
9179         ESTAT_ADD(nic_tx_threshold_hit);
9180
9181         return estats;
9182 }
9183
9184 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
9185                                                  struct rtnl_link_stats64 *stats)
9186 {
9187         struct tg3 *tp = netdev_priv(dev);
9188         struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
9189         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9190
9191         if (!hw_stats)
9192                 return old_stats;
9193
9194         stats->rx_packets = old_stats->rx_packets +
9195                 get_stat64(&hw_stats->rx_ucast_packets) +
9196                 get_stat64(&hw_stats->rx_mcast_packets) +
9197                 get_stat64(&hw_stats->rx_bcast_packets);
9198
9199         stats->tx_packets = old_stats->tx_packets +
9200                 get_stat64(&hw_stats->tx_ucast_packets) +
9201                 get_stat64(&hw_stats->tx_mcast_packets) +
9202                 get_stat64(&hw_stats->tx_bcast_packets);
9203
9204         stats->rx_bytes = old_stats->rx_bytes +
9205                 get_stat64(&hw_stats->rx_octets);
9206         stats->tx_bytes = old_stats->tx_bytes +
9207                 get_stat64(&hw_stats->tx_octets);
9208
9209         stats->rx_errors = old_stats->rx_errors +
9210                 get_stat64(&hw_stats->rx_errors);
9211         stats->tx_errors = old_stats->tx_errors +
9212                 get_stat64(&hw_stats->tx_errors) +
9213                 get_stat64(&hw_stats->tx_mac_errors) +
9214                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9215                 get_stat64(&hw_stats->tx_discards);
9216
9217         stats->multicast = old_stats->multicast +
9218                 get_stat64(&hw_stats->rx_mcast_packets);
9219         stats->collisions = old_stats->collisions +
9220                 get_stat64(&hw_stats->tx_collisions);
9221
9222         stats->rx_length_errors = old_stats->rx_length_errors +
9223                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9224                 get_stat64(&hw_stats->rx_undersize_packets);
9225
9226         stats->rx_over_errors = old_stats->rx_over_errors +
9227                 get_stat64(&hw_stats->rxbds_empty);
9228         stats->rx_frame_errors = old_stats->rx_frame_errors +
9229                 get_stat64(&hw_stats->rx_align_errors);
9230         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9231                 get_stat64(&hw_stats->tx_discards);
9232         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9233                 get_stat64(&hw_stats->tx_carrier_sense_errors);
9234
9235         stats->rx_crc_errors = old_stats->rx_crc_errors +
9236                 calc_crc_errors(tp);
9237
9238         stats->rx_missed_errors = old_stats->rx_missed_errors +
9239                 get_stat64(&hw_stats->rx_discards);
9240
9241         return stats;
9242 }
9243
9244 static inline u32 calc_crc(unsigned char *buf, int len)
9245 {
9246         u32 reg;
9247         u32 tmp;
9248         int j, k;
9249
9250         reg = 0xffffffff;
9251
9252         for (j = 0; j < len; j++) {
9253                 reg ^= buf[j];
9254
9255                 for (k = 0; k < 8; k++) {
9256                         tmp = reg & 0x01;
9257
9258                         reg >>= 1;
9259
9260                         if (tmp)
9261                                 reg ^= 0xedb88320;
9262                 }
9263         }
9264
9265         return ~reg;
9266 }
9267
9268 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9269 {
9270         /* accept or reject all multicast frames */
9271         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9272         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9273         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9274         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9275 }
9276
9277 static void __tg3_set_rx_mode(struct net_device *dev)
9278 {
9279         struct tg3 *tp = netdev_priv(dev);
9280         u32 rx_mode;
9281
9282         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9283                                   RX_MODE_KEEP_VLAN_TAG);
9284
9285         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9286          * flag clear.
9287          */
9288 #if TG3_VLAN_TAG_USED
9289         if (!tp->vlgrp &&
9290             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9291                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9292 #else
9293         /* By definition, VLAN is disabled always in this
9294          * case.
9295          */
9296         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9297                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9298 #endif
9299
9300         if (dev->flags & IFF_PROMISC) {
9301                 /* Promiscuous mode. */
9302                 rx_mode |= RX_MODE_PROMISC;
9303         } else if (dev->flags & IFF_ALLMULTI) {
9304                 /* Accept all multicast. */
9305                 tg3_set_multi(tp, 1);
9306         } else if (netdev_mc_empty(dev)) {
9307                 /* Reject all multicast. */
9308                 tg3_set_multi(tp, 0);
9309         } else {
9310                 /* Accept one or more multicast(s). */
9311                 struct netdev_hw_addr *ha;
9312                 u32 mc_filter[4] = { 0, };
9313                 u32 regidx;
9314                 u32 bit;
9315                 u32 crc;
9316
9317                 netdev_for_each_mc_addr(ha, dev) {
9318                         crc = calc_crc(ha->addr, ETH_ALEN);
9319                         bit = ~crc & 0x7f;
9320                         regidx = (bit & 0x60) >> 5;
9321                         bit &= 0x1f;
9322                         mc_filter[regidx] |= (1 << bit);
9323                 }
9324
9325                 tw32(MAC_HASH_REG_0, mc_filter[0]);
9326                 tw32(MAC_HASH_REG_1, mc_filter[1]);
9327                 tw32(MAC_HASH_REG_2, mc_filter[2]);
9328                 tw32(MAC_HASH_REG_3, mc_filter[3]);
9329         }
9330
9331         if (rx_mode != tp->rx_mode) {
9332                 tp->rx_mode = rx_mode;
9333                 tw32_f(MAC_RX_MODE, rx_mode);
9334                 udelay(10);
9335         }
9336 }
9337
9338 static void tg3_set_rx_mode(struct net_device *dev)
9339 {
9340         struct tg3 *tp = netdev_priv(dev);
9341
9342         if (!netif_running(dev))
9343                 return;
9344
9345         tg3_full_lock(tp, 0);
9346         __tg3_set_rx_mode(dev);
9347         tg3_full_unlock(tp);
9348 }
9349
9350 #define TG3_REGDUMP_LEN         (32 * 1024)
9351
9352 static int tg3_get_regs_len(struct net_device *dev)
9353 {
9354         return TG3_REGDUMP_LEN;
9355 }
9356
9357 static void tg3_get_regs(struct net_device *dev,
9358                 struct ethtool_regs *regs, void *_p)
9359 {
9360         u32 *p = _p;
9361         struct tg3 *tp = netdev_priv(dev);
9362         u8 *orig_p = _p;
9363         int i;
9364
9365         regs->version = 0;
9366
9367         memset(p, 0, TG3_REGDUMP_LEN);
9368
9369         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9370                 return;
9371
9372         tg3_full_lock(tp, 0);
9373
9374 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
9375 #define GET_REG32_LOOP(base, len)               \
9376 do {    p = (u32 *)(orig_p + (base));           \
9377         for (i = 0; i < len; i += 4)            \
9378                 __GET_REG32((base) + i);        \
9379 } while (0)
9380 #define GET_REG32_1(reg)                        \
9381 do {    p = (u32 *)(orig_p + (reg));            \
9382         __GET_REG32((reg));                     \
9383 } while (0)
9384
9385         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9386         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9387         GET_REG32_LOOP(MAC_MODE, 0x4f0);
9388         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9389         GET_REG32_1(SNDDATAC_MODE);
9390         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9391         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9392         GET_REG32_1(SNDBDC_MODE);
9393         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9394         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9395         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9396         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9397         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9398         GET_REG32_1(RCVDCC_MODE);
9399         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9400         GET_REG32_LOOP(RCVCC_MODE, 0x14);
9401         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9402         GET_REG32_1(MBFREE_MODE);
9403         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9404         GET_REG32_LOOP(MEMARB_MODE, 0x10);
9405         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9406         GET_REG32_LOOP(RDMAC_MODE, 0x08);
9407         GET_REG32_LOOP(WDMAC_MODE, 0x08);
9408         GET_REG32_1(RX_CPU_MODE);
9409         GET_REG32_1(RX_CPU_STATE);
9410         GET_REG32_1(RX_CPU_PGMCTR);
9411         GET_REG32_1(RX_CPU_HWBKPT);
9412         GET_REG32_1(TX_CPU_MODE);
9413         GET_REG32_1(TX_CPU_STATE);
9414         GET_REG32_1(TX_CPU_PGMCTR);
9415         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9416         GET_REG32_LOOP(FTQ_RESET, 0x120);
9417         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9418         GET_REG32_1(DMAC_MODE);
9419         GET_REG32_LOOP(GRC_MODE, 0x4c);
9420         if (tp->tg3_flags & TG3_FLAG_NVRAM)
9421                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9422
9423 #undef __GET_REG32
9424 #undef GET_REG32_LOOP
9425 #undef GET_REG32_1
9426
9427         tg3_full_unlock(tp);
9428 }
9429
9430 static int tg3_get_eeprom_len(struct net_device *dev)
9431 {
9432         struct tg3 *tp = netdev_priv(dev);
9433
9434         return tp->nvram_size;
9435 }
9436
9437 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9438 {
9439         struct tg3 *tp = netdev_priv(dev);
9440         int ret;
9441         u8  *pd;
9442         u32 i, offset, len, b_offset, b_count;
9443         __be32 val;
9444
9445         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9446                 return -EINVAL;
9447
9448         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9449                 return -EAGAIN;
9450
9451         offset = eeprom->offset;
9452         len = eeprom->len;
9453         eeprom->len = 0;
9454
9455         eeprom->magic = TG3_EEPROM_MAGIC;
9456
9457         if (offset & 3) {
9458                 /* adjustments to start on required 4 byte boundary */
9459                 b_offset = offset & 3;
9460                 b_count = 4 - b_offset;
9461                 if (b_count > len) {
9462                         /* i.e. offset=1 len=2 */
9463                         b_count = len;
9464                 }
9465                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9466                 if (ret)
9467                         return ret;
9468                 memcpy(data, ((char *)&val) + b_offset, b_count);
9469                 len -= b_count;
9470                 offset += b_count;
9471                 eeprom->len += b_count;
9472         }
9473
9474         /* read bytes upto the last 4 byte boundary */
9475         pd = &data[eeprom->len];
9476         for (i = 0; i < (len - (len & 3)); i += 4) {
9477                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9478                 if (ret) {
9479                         eeprom->len += i;
9480                         return ret;
9481                 }
9482                 memcpy(pd + i, &val, 4);
9483         }
9484         eeprom->len += i;
9485
9486         if (len & 3) {
9487                 /* read last bytes not ending on 4 byte boundary */
9488                 pd = &data[eeprom->len];
9489                 b_count = len & 3;
9490                 b_offset = offset + len - b_count;
9491                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9492                 if (ret)
9493                         return ret;
9494                 memcpy(pd, &val, b_count);
9495                 eeprom->len += b_count;
9496         }
9497         return 0;
9498 }
9499
9500 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9501
9502 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9503 {
9504         struct tg3 *tp = netdev_priv(dev);
9505         int ret;
9506         u32 offset, len, b_offset, odd_len;
9507         u8 *buf;
9508         __be32 start, end;
9509
9510         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9511                 return -EAGAIN;
9512
9513         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9514             eeprom->magic != TG3_EEPROM_MAGIC)
9515                 return -EINVAL;
9516
9517         offset = eeprom->offset;
9518         len = eeprom->len;
9519
9520         if ((b_offset = (offset & 3))) {
9521                 /* adjustments to start on required 4 byte boundary */
9522                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9523                 if (ret)
9524                         return ret;
9525                 len += b_offset;
9526                 offset &= ~3;
9527                 if (len < 4)
9528                         len = 4;
9529         }
9530
9531         odd_len = 0;
9532         if (len & 3) {
9533                 /* adjustments to end on required 4 byte boundary */
9534                 odd_len = 1;
9535                 len = (len + 3) & ~3;
9536                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9537                 if (ret)
9538                         return ret;
9539         }
9540
9541         buf = data;
9542         if (b_offset || odd_len) {
9543                 buf = kmalloc(len, GFP_KERNEL);
9544                 if (!buf)
9545                         return -ENOMEM;
9546                 if (b_offset)
9547                         memcpy(buf, &start, 4);
9548                 if (odd_len)
9549                         memcpy(buf+len-4, &end, 4);
9550                 memcpy(buf + b_offset, data, eeprom->len);
9551         }
9552
9553         ret = tg3_nvram_write_block(tp, offset, len, buf);
9554
9555         if (buf != data)
9556                 kfree(buf);
9557
9558         return ret;
9559 }
9560
9561 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9562 {
9563         struct tg3 *tp = netdev_priv(dev);
9564
9565         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9566                 struct phy_device *phydev;
9567                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9568                         return -EAGAIN;
9569                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9570                 return phy_ethtool_gset(phydev, cmd);
9571         }
9572
9573         cmd->supported = (SUPPORTED_Autoneg);
9574
9575         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9576                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9577                                    SUPPORTED_1000baseT_Full);
9578
9579         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
9580                 cmd->supported |= (SUPPORTED_100baseT_Half |
9581                                   SUPPORTED_100baseT_Full |
9582                                   SUPPORTED_10baseT_Half |
9583                                   SUPPORTED_10baseT_Full |
9584                                   SUPPORTED_TP);
9585                 cmd->port = PORT_TP;
9586         } else {
9587                 cmd->supported |= SUPPORTED_FIBRE;
9588                 cmd->port = PORT_FIBRE;
9589         }
9590
9591         cmd->advertising = tp->link_config.advertising;
9592         if (netif_running(dev)) {
9593                 cmd->speed = tp->link_config.active_speed;
9594                 cmd->duplex = tp->link_config.active_duplex;
9595         }
9596         cmd->phy_address = tp->phy_addr;
9597         cmd->transceiver = XCVR_INTERNAL;
9598         cmd->autoneg = tp->link_config.autoneg;
9599         cmd->maxtxpkt = 0;
9600         cmd->maxrxpkt = 0;
9601         return 0;
9602 }
9603
9604 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9605 {
9606         struct tg3 *tp = netdev_priv(dev);
9607
9608         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9609                 struct phy_device *phydev;
9610                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9611                         return -EAGAIN;
9612                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9613                 return phy_ethtool_sset(phydev, cmd);
9614         }
9615
9616         if (cmd->autoneg != AUTONEG_ENABLE &&
9617             cmd->autoneg != AUTONEG_DISABLE)
9618                 return -EINVAL;
9619
9620         if (cmd->autoneg == AUTONEG_DISABLE &&
9621             cmd->duplex != DUPLEX_FULL &&
9622             cmd->duplex != DUPLEX_HALF)
9623                 return -EINVAL;
9624
9625         if (cmd->autoneg == AUTONEG_ENABLE) {
9626                 u32 mask = ADVERTISED_Autoneg |
9627                            ADVERTISED_Pause |
9628                            ADVERTISED_Asym_Pause;
9629
9630                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9631                         mask |= ADVERTISED_1000baseT_Half |
9632                                 ADVERTISED_1000baseT_Full;
9633
9634                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
9635                         mask |= ADVERTISED_100baseT_Half |
9636                                 ADVERTISED_100baseT_Full |
9637                                 ADVERTISED_10baseT_Half |
9638                                 ADVERTISED_10baseT_Full |
9639                                 ADVERTISED_TP;
9640                 else
9641                         mask |= ADVERTISED_FIBRE;
9642
9643                 if (cmd->advertising & ~mask)
9644                         return -EINVAL;
9645
9646                 mask &= (ADVERTISED_1000baseT_Half |
9647                          ADVERTISED_1000baseT_Full |
9648                          ADVERTISED_100baseT_Half |
9649                          ADVERTISED_100baseT_Full |
9650                          ADVERTISED_10baseT_Half |
9651                          ADVERTISED_10baseT_Full);
9652
9653                 cmd->advertising &= mask;
9654         } else {
9655                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
9656                         if (cmd->speed != SPEED_1000)
9657                                 return -EINVAL;
9658
9659                         if (cmd->duplex != DUPLEX_FULL)
9660                                 return -EINVAL;
9661                 } else {
9662                         if (cmd->speed != SPEED_100 &&
9663                             cmd->speed != SPEED_10)
9664                                 return -EINVAL;
9665                 }
9666         }
9667
9668         tg3_full_lock(tp, 0);
9669
9670         tp->link_config.autoneg = cmd->autoneg;
9671         if (cmd->autoneg == AUTONEG_ENABLE) {
9672                 tp->link_config.advertising = (cmd->advertising |
9673                                               ADVERTISED_Autoneg);
9674                 tp->link_config.speed = SPEED_INVALID;
9675                 tp->link_config.duplex = DUPLEX_INVALID;
9676         } else {
9677                 tp->link_config.advertising = 0;
9678                 tp->link_config.speed = cmd->speed;
9679                 tp->link_config.duplex = cmd->duplex;
9680         }
9681
9682         tp->link_config.orig_speed = tp->link_config.speed;
9683         tp->link_config.orig_duplex = tp->link_config.duplex;
9684         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9685
9686         if (netif_running(dev))
9687                 tg3_setup_phy(tp, 1);
9688
9689         tg3_full_unlock(tp);
9690
9691         return 0;
9692 }
9693
9694 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9695 {
9696         struct tg3 *tp = netdev_priv(dev);
9697
9698         strcpy(info->driver, DRV_MODULE_NAME);
9699         strcpy(info->version, DRV_MODULE_VERSION);
9700         strcpy(info->fw_version, tp->fw_ver);
9701         strcpy(info->bus_info, pci_name(tp->pdev));
9702 }
9703
9704 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9705 {
9706         struct tg3 *tp = netdev_priv(dev);
9707
9708         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9709             device_can_wakeup(&tp->pdev->dev))
9710                 wol->supported = WAKE_MAGIC;
9711         else
9712                 wol->supported = 0;
9713         wol->wolopts = 0;
9714         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9715             device_can_wakeup(&tp->pdev->dev))
9716                 wol->wolopts = WAKE_MAGIC;
9717         memset(&wol->sopass, 0, sizeof(wol->sopass));
9718 }
9719
9720 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9721 {
9722         struct tg3 *tp = netdev_priv(dev);
9723         struct device *dp = &tp->pdev->dev;
9724
9725         if (wol->wolopts & ~WAKE_MAGIC)
9726                 return -EINVAL;
9727         if ((wol->wolopts & WAKE_MAGIC) &&
9728             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9729                 return -EINVAL;
9730
9731         spin_lock_bh(&tp->lock);
9732         if (wol->wolopts & WAKE_MAGIC) {
9733                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9734                 device_set_wakeup_enable(dp, true);
9735         } else {
9736                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9737                 device_set_wakeup_enable(dp, false);
9738         }
9739         spin_unlock_bh(&tp->lock);
9740
9741         return 0;
9742 }
9743
9744 static u32 tg3_get_msglevel(struct net_device *dev)
9745 {
9746         struct tg3 *tp = netdev_priv(dev);
9747         return tp->msg_enable;
9748 }
9749
9750 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9751 {
9752         struct tg3 *tp = netdev_priv(dev);
9753         tp->msg_enable = value;
9754 }
9755
9756 static int tg3_set_tso(struct net_device *dev, u32 value)
9757 {
9758         struct tg3 *tp = netdev_priv(dev);
9759
9760         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9761                 if (value)
9762                         return -EINVAL;
9763                 return 0;
9764         }
9765         if ((dev->features & NETIF_F_IPV6_CSUM) &&
9766             ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9767              (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9768                 if (value) {
9769                         dev->features |= NETIF_F_TSO6;
9770                         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9771                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9772                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9773                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9774                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9775                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9776                                 dev->features |= NETIF_F_TSO_ECN;
9777                 } else
9778                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9779         }
9780         return ethtool_op_set_tso(dev, value);
9781 }
9782
9783 static int tg3_nway_reset(struct net_device *dev)
9784 {
9785         struct tg3 *tp = netdev_priv(dev);
9786         int r;
9787
9788         if (!netif_running(dev))
9789                 return -EAGAIN;
9790
9791         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
9792                 return -EINVAL;
9793
9794         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9795                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9796                         return -EAGAIN;
9797                 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9798         } else {
9799                 u32 bmcr;
9800
9801                 spin_lock_bh(&tp->lock);
9802                 r = -EINVAL;
9803                 tg3_readphy(tp, MII_BMCR, &bmcr);
9804                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9805                     ((bmcr & BMCR_ANENABLE) ||
9806                      (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
9807                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9808                                                    BMCR_ANENABLE);
9809                         r = 0;
9810                 }
9811                 spin_unlock_bh(&tp->lock);
9812         }
9813
9814         return r;
9815 }
9816
9817 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9818 {
9819         struct tg3 *tp = netdev_priv(dev);
9820
9821         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9822         ering->rx_mini_max_pending = 0;
9823         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9824                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9825         else
9826                 ering->rx_jumbo_max_pending = 0;
9827
9828         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9829
9830         ering->rx_pending = tp->rx_pending;
9831         ering->rx_mini_pending = 0;
9832         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9833                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9834         else
9835                 ering->rx_jumbo_pending = 0;
9836
9837         ering->tx_pending = tp->napi[0].tx_pending;
9838 }
9839
9840 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9841 {
9842         struct tg3 *tp = netdev_priv(dev);
9843         int i, irq_sync = 0, err = 0;
9844
9845         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9846             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9847             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9848             (ering->tx_pending <= MAX_SKB_FRAGS) ||
9849             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9850              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9851                 return -EINVAL;
9852
9853         if (netif_running(dev)) {
9854                 tg3_phy_stop(tp);
9855                 tg3_netif_stop(tp);
9856                 irq_sync = 1;
9857         }
9858
9859         tg3_full_lock(tp, irq_sync);
9860
9861         tp->rx_pending = ering->rx_pending;
9862
9863         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9864             tp->rx_pending > 63)
9865                 tp->rx_pending = 63;
9866         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9867
9868         for (i = 0; i < tp->irq_max; i++)
9869                 tp->napi[i].tx_pending = ering->tx_pending;
9870
9871         if (netif_running(dev)) {
9872                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9873                 err = tg3_restart_hw(tp, 1);
9874                 if (!err)
9875                         tg3_netif_start(tp);
9876         }
9877
9878         tg3_full_unlock(tp);
9879
9880         if (irq_sync && !err)
9881                 tg3_phy_start(tp);
9882
9883         return err;
9884 }
9885
9886 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9887 {
9888         struct tg3 *tp = netdev_priv(dev);
9889
9890         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9891
9892         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9893                 epause->rx_pause = 1;
9894         else
9895                 epause->rx_pause = 0;
9896
9897         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9898                 epause->tx_pause = 1;
9899         else
9900                 epause->tx_pause = 0;
9901 }
9902
9903 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9904 {
9905         struct tg3 *tp = netdev_priv(dev);
9906         int err = 0;
9907
9908         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9909                 u32 newadv;
9910                 struct phy_device *phydev;
9911
9912                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9913
9914                 if (!(phydev->supported & SUPPORTED_Pause) ||
9915                     (!(phydev->supported & SUPPORTED_Asym_Pause) &&
9916                      ((epause->rx_pause && !epause->tx_pause) ||
9917                       (!epause->rx_pause && epause->tx_pause))))
9918                         return -EINVAL;
9919
9920                 tp->link_config.flowctrl = 0;
9921                 if (epause->rx_pause) {
9922                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
9923
9924                         if (epause->tx_pause) {
9925                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9926                                 newadv = ADVERTISED_Pause;
9927                         } else
9928                                 newadv = ADVERTISED_Pause |
9929                                          ADVERTISED_Asym_Pause;
9930                 } else if (epause->tx_pause) {
9931                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
9932                         newadv = ADVERTISED_Asym_Pause;
9933                 } else
9934                         newadv = 0;
9935
9936                 if (epause->autoneg)
9937                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9938                 else
9939                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9940
9941                 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
9942                         u32 oldadv = phydev->advertising &
9943                                      (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
9944                         if (oldadv != newadv) {
9945                                 phydev->advertising &=
9946                                         ~(ADVERTISED_Pause |
9947                                           ADVERTISED_Asym_Pause);
9948                                 phydev->advertising |= newadv;
9949                                 if (phydev->autoneg) {
9950                                         /*
9951                                          * Always renegotiate the link to
9952                                          * inform our link partner of our
9953                                          * flow control settings, even if the
9954                                          * flow control is forced.  Let
9955                                          * tg3_adjust_link() do the final
9956                                          * flow control setup.
9957                                          */
9958                                         return phy_start_aneg(phydev);
9959                                 }
9960                         }
9961
9962                         if (!epause->autoneg)
9963                                 tg3_setup_flow_control(tp, 0, 0);
9964                 } else {
9965                         tp->link_config.orig_advertising &=
9966                                         ~(ADVERTISED_Pause |
9967                                           ADVERTISED_Asym_Pause);
9968                         tp->link_config.orig_advertising |= newadv;
9969                 }
9970         } else {
9971                 int irq_sync = 0;
9972
9973                 if (netif_running(dev)) {
9974                         tg3_netif_stop(tp);
9975                         irq_sync = 1;
9976                 }
9977
9978                 tg3_full_lock(tp, irq_sync);
9979
9980                 if (epause->autoneg)
9981                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9982                 else
9983                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9984                 if (epause->rx_pause)
9985                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
9986                 else
9987                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9988                 if (epause->tx_pause)
9989                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
9990                 else
9991                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9992
9993                 if (netif_running(dev)) {
9994                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9995                         err = tg3_restart_hw(tp, 1);
9996                         if (!err)
9997                                 tg3_netif_start(tp);
9998                 }
9999
10000                 tg3_full_unlock(tp);
10001         }
10002
10003         return err;
10004 }
10005
10006 static u32 tg3_get_rx_csum(struct net_device *dev)
10007 {
10008         struct tg3 *tp = netdev_priv(dev);
10009         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10010 }
10011
10012 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10013 {
10014         struct tg3 *tp = netdev_priv(dev);
10015
10016         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10017                 if (data != 0)
10018                         return -EINVAL;
10019                 return 0;
10020         }
10021
10022         spin_lock_bh(&tp->lock);
10023         if (data)
10024                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10025         else
10026                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10027         spin_unlock_bh(&tp->lock);
10028
10029         return 0;
10030 }
10031
10032 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10033 {
10034         struct tg3 *tp = netdev_priv(dev);
10035
10036         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10037                 if (data != 0)
10038                         return -EINVAL;
10039                 return 0;
10040         }
10041
10042         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10043                 ethtool_op_set_tx_ipv6_csum(dev, data);
10044         else
10045                 ethtool_op_set_tx_csum(dev, data);
10046
10047         return 0;
10048 }
10049
10050 static int tg3_get_sset_count(struct net_device *dev, int sset)
10051 {
10052         switch (sset) {
10053         case ETH_SS_TEST:
10054                 return TG3_NUM_TEST;
10055         case ETH_SS_STATS:
10056                 return TG3_NUM_STATS;
10057         default:
10058                 return -EOPNOTSUPP;
10059         }
10060 }
10061
10062 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
10063 {
10064         switch (stringset) {
10065         case ETH_SS_STATS:
10066                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10067                 break;
10068         case ETH_SS_TEST:
10069                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10070                 break;
10071         default:
10072                 WARN_ON(1);     /* we need a WARN() */
10073                 break;
10074         }
10075 }
10076
10077 static int tg3_phys_id(struct net_device *dev, u32 data)
10078 {
10079         struct tg3 *tp = netdev_priv(dev);
10080         int i;
10081
10082         if (!netif_running(tp->dev))
10083                 return -EAGAIN;
10084
10085         if (data == 0)
10086                 data = UINT_MAX / 2;
10087
10088         for (i = 0; i < (data * 2); i++) {
10089                 if ((i % 2) == 0)
10090                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10091                                            LED_CTRL_1000MBPS_ON |
10092                                            LED_CTRL_100MBPS_ON |
10093                                            LED_CTRL_10MBPS_ON |
10094                                            LED_CTRL_TRAFFIC_OVERRIDE |
10095                                            LED_CTRL_TRAFFIC_BLINK |
10096                                            LED_CTRL_TRAFFIC_LED);
10097
10098                 else
10099                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10100                                            LED_CTRL_TRAFFIC_OVERRIDE);
10101
10102                 if (msleep_interruptible(500))
10103                         break;
10104         }
10105         tw32(MAC_LED_CTRL, tp->led_ctrl);
10106         return 0;
10107 }
10108
10109 static void tg3_get_ethtool_stats(struct net_device *dev,
10110                                    struct ethtool_stats *estats, u64 *tmp_stats)
10111 {
10112         struct tg3 *tp = netdev_priv(dev);
10113         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10114 }
10115
10116 #define NVRAM_TEST_SIZE 0x100
10117 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
10118 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
10119 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
10120 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10121 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10122
10123 static int tg3_test_nvram(struct tg3 *tp)
10124 {
10125         u32 csum, magic;
10126         __be32 *buf;
10127         int i, j, k, err = 0, size;
10128
10129         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10130                 return 0;
10131
10132         if (tg3_nvram_read(tp, 0, &magic) != 0)
10133                 return -EIO;
10134
10135         if (magic == TG3_EEPROM_MAGIC)
10136                 size = NVRAM_TEST_SIZE;
10137         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10138                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10139                     TG3_EEPROM_SB_FORMAT_1) {
10140                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10141                         case TG3_EEPROM_SB_REVISION_0:
10142                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10143                                 break;
10144                         case TG3_EEPROM_SB_REVISION_2:
10145                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10146                                 break;
10147                         case TG3_EEPROM_SB_REVISION_3:
10148                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10149                                 break;
10150                         default:
10151                                 return 0;
10152                         }
10153                 } else
10154                         return 0;
10155         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10156                 size = NVRAM_SELFBOOT_HW_SIZE;
10157         else
10158                 return -EIO;
10159
10160         buf = kmalloc(size, GFP_KERNEL);
10161         if (buf == NULL)
10162                 return -ENOMEM;
10163
10164         err = -EIO;
10165         for (i = 0, j = 0; i < size; i += 4, j++) {
10166                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10167                 if (err)
10168                         break;
10169         }
10170         if (i < size)
10171                 goto out;
10172
10173         /* Selfboot format */
10174         magic = be32_to_cpu(buf[0]);
10175         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10176             TG3_EEPROM_MAGIC_FW) {
10177                 u8 *buf8 = (u8 *) buf, csum8 = 0;
10178
10179                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10180                     TG3_EEPROM_SB_REVISION_2) {
10181                         /* For rev 2, the csum doesn't include the MBA. */
10182                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10183                                 csum8 += buf8[i];
10184                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10185                                 csum8 += buf8[i];
10186                 } else {
10187                         for (i = 0; i < size; i++)
10188                                 csum8 += buf8[i];
10189                 }
10190
10191                 if (csum8 == 0) {
10192                         err = 0;
10193                         goto out;
10194                 }
10195
10196                 err = -EIO;
10197                 goto out;
10198         }
10199
10200         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10201             TG3_EEPROM_MAGIC_HW) {
10202                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10203                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10204                 u8 *buf8 = (u8 *) buf;
10205
10206                 /* Separate the parity bits and the data bytes.  */
10207                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10208                         if ((i == 0) || (i == 8)) {
10209                                 int l;
10210                                 u8 msk;
10211
10212                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10213                                         parity[k++] = buf8[i] & msk;
10214                                 i++;
10215                         } else if (i == 16) {
10216                                 int l;
10217                                 u8 msk;
10218
10219                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10220                                         parity[k++] = buf8[i] & msk;
10221                                 i++;
10222
10223                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10224                                         parity[k++] = buf8[i] & msk;
10225                                 i++;
10226                         }
10227                         data[j++] = buf8[i];
10228                 }
10229
10230                 err = -EIO;
10231                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10232                         u8 hw8 = hweight8(data[i]);
10233
10234                         if ((hw8 & 0x1) && parity[i])
10235                                 goto out;
10236                         else if (!(hw8 & 0x1) && !parity[i])
10237                                 goto out;
10238                 }
10239                 err = 0;
10240                 goto out;
10241         }
10242
10243         /* Bootstrap checksum at offset 0x10 */
10244         csum = calc_crc((unsigned char *) buf, 0x10);
10245         if (csum != be32_to_cpu(buf[0x10/4]))
10246                 goto out;
10247
10248         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10249         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10250         if (csum != be32_to_cpu(buf[0xfc/4]))
10251                 goto out;
10252
10253         err = 0;
10254
10255 out:
10256         kfree(buf);
10257         return err;
10258 }
10259
10260 #define TG3_SERDES_TIMEOUT_SEC  2
10261 #define TG3_COPPER_TIMEOUT_SEC  6
10262
10263 static int tg3_test_link(struct tg3 *tp)
10264 {
10265         int i, max;
10266
10267         if (!netif_running(tp->dev))
10268                 return -ENODEV;
10269
10270         if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
10271                 max = TG3_SERDES_TIMEOUT_SEC;
10272         else
10273                 max = TG3_COPPER_TIMEOUT_SEC;
10274
10275         for (i = 0; i < max; i++) {
10276                 if (netif_carrier_ok(tp->dev))
10277                         return 0;
10278
10279                 if (msleep_interruptible(1000))
10280                         break;
10281         }
10282
10283         return -EIO;
10284 }
10285
10286 /* Only test the commonly used registers */
10287 static int tg3_test_registers(struct tg3 *tp)
10288 {
10289         int i, is_5705, is_5750;
10290         u32 offset, read_mask, write_mask, val, save_val, read_val;
10291         static struct {
10292                 u16 offset;
10293                 u16 flags;
10294 #define TG3_FL_5705     0x1
10295 #define TG3_FL_NOT_5705 0x2
10296 #define TG3_FL_NOT_5788 0x4
10297 #define TG3_FL_NOT_5750 0x8
10298                 u32 read_mask;
10299                 u32 write_mask;
10300         } reg_tbl[] = {
10301                 /* MAC Control Registers */
10302                 { MAC_MODE, TG3_FL_NOT_5705,
10303                         0x00000000, 0x00ef6f8c },
10304                 { MAC_MODE, TG3_FL_5705,
10305                         0x00000000, 0x01ef6b8c },
10306                 { MAC_STATUS, TG3_FL_NOT_5705,
10307                         0x03800107, 0x00000000 },
10308                 { MAC_STATUS, TG3_FL_5705,
10309                         0x03800100, 0x00000000 },
10310                 { MAC_ADDR_0_HIGH, 0x0000,
10311                         0x00000000, 0x0000ffff },
10312                 { MAC_ADDR_0_LOW, 0x0000,
10313                         0x00000000, 0xffffffff },
10314                 { MAC_RX_MTU_SIZE, 0x0000,
10315                         0x00000000, 0x0000ffff },
10316                 { MAC_TX_MODE, 0x0000,
10317                         0x00000000, 0x00000070 },
10318                 { MAC_TX_LENGTHS, 0x0000,
10319                         0x00000000, 0x00003fff },
10320                 { MAC_RX_MODE, TG3_FL_NOT_5705,
10321                         0x00000000, 0x000007fc },
10322                 { MAC_RX_MODE, TG3_FL_5705,
10323                         0x00000000, 0x000007dc },
10324                 { MAC_HASH_REG_0, 0x0000,
10325                         0x00000000, 0xffffffff },
10326                 { MAC_HASH_REG_1, 0x0000,
10327                         0x00000000, 0xffffffff },
10328                 { MAC_HASH_REG_2, 0x0000,
10329                         0x00000000, 0xffffffff },
10330                 { MAC_HASH_REG_3, 0x0000,
10331                         0x00000000, 0xffffffff },
10332
10333                 /* Receive Data and Receive BD Initiator Control Registers. */
10334                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10335                         0x00000000, 0xffffffff },
10336                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10337                         0x00000000, 0xffffffff },
10338                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10339                         0x00000000, 0x00000003 },
10340                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10341                         0x00000000, 0xffffffff },
10342                 { RCVDBDI_STD_BD+0, 0x0000,
10343                         0x00000000, 0xffffffff },
10344                 { RCVDBDI_STD_BD+4, 0x0000,
10345                         0x00000000, 0xffffffff },
10346                 { RCVDBDI_STD_BD+8, 0x0000,
10347                         0x00000000, 0xffff0002 },
10348                 { RCVDBDI_STD_BD+0xc, 0x0000,
10349                         0x00000000, 0xffffffff },
10350
10351                 /* Receive BD Initiator Control Registers. */
10352                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10353                         0x00000000, 0xffffffff },
10354                 { RCVBDI_STD_THRESH, TG3_FL_5705,
10355                         0x00000000, 0x000003ff },
10356                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10357                         0x00000000, 0xffffffff },
10358
10359                 /* Host Coalescing Control Registers. */
10360                 { HOSTCC_MODE, TG3_FL_NOT_5705,
10361                         0x00000000, 0x00000004 },
10362                 { HOSTCC_MODE, TG3_FL_5705,
10363                         0x00000000, 0x000000f6 },
10364                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10365                         0x00000000, 0xffffffff },
10366                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10367                         0x00000000, 0x000003ff },
10368                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10369                         0x00000000, 0xffffffff },
10370                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10371                         0x00000000, 0x000003ff },
10372                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10373                         0x00000000, 0xffffffff },
10374                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10375                         0x00000000, 0x000000ff },
10376                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10377                         0x00000000, 0xffffffff },
10378                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10379                         0x00000000, 0x000000ff },
10380                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10381                         0x00000000, 0xffffffff },
10382                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10383                         0x00000000, 0xffffffff },
10384                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10385                         0x00000000, 0xffffffff },
10386                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10387                         0x00000000, 0x000000ff },
10388                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10389                         0x00000000, 0xffffffff },
10390                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10391                         0x00000000, 0x000000ff },
10392                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10393                         0x00000000, 0xffffffff },
10394                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10395                         0x00000000, 0xffffffff },
10396                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10397                         0x00000000, 0xffffffff },
10398                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10399                         0x00000000, 0xffffffff },
10400                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10401                         0x00000000, 0xffffffff },
10402                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10403                         0xffffffff, 0x00000000 },
10404                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10405                         0xffffffff, 0x00000000 },
10406
10407                 /* Buffer Manager Control Registers. */
10408                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10409                         0x00000000, 0x007fff80 },
10410                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10411                         0x00000000, 0x007fffff },
10412                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10413                         0x00000000, 0x0000003f },
10414                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10415                         0x00000000, 0x000001ff },
10416                 { BUFMGR_MB_HIGH_WATER, 0x0000,
10417                         0x00000000, 0x000001ff },
10418                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10419                         0xffffffff, 0x00000000 },
10420                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10421                         0xffffffff, 0x00000000 },
10422
10423                 /* Mailbox Registers */
10424                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10425                         0x00000000, 0x000001ff },
10426                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10427                         0x00000000, 0x000001ff },
10428                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10429                         0x00000000, 0x000007ff },
10430                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10431                         0x00000000, 0x000001ff },
10432
10433                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10434         };
10435
10436         is_5705 = is_5750 = 0;
10437         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10438                 is_5705 = 1;
10439                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10440                         is_5750 = 1;
10441         }
10442
10443         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10444                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10445                         continue;
10446
10447                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10448                         continue;
10449
10450                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10451                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
10452                         continue;
10453
10454                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10455                         continue;
10456
10457                 offset = (u32) reg_tbl[i].offset;
10458                 read_mask = reg_tbl[i].read_mask;
10459                 write_mask = reg_tbl[i].write_mask;
10460
10461                 /* Save the original register content */
10462                 save_val = tr32(offset);
10463
10464                 /* Determine the read-only value. */
10465                 read_val = save_val & read_mask;
10466
10467                 /* Write zero to the register, then make sure the read-only bits
10468                  * are not changed and the read/write bits are all zeros.
10469                  */
10470                 tw32(offset, 0);
10471
10472                 val = tr32(offset);
10473
10474                 /* Test the read-only and read/write bits. */
10475                 if (((val & read_mask) != read_val) || (val & write_mask))
10476                         goto out;
10477
10478                 /* Write ones to all the bits defined by RdMask and WrMask, then
10479                  * make sure the read-only bits are not changed and the
10480                  * read/write bits are all ones.
10481                  */
10482                 tw32(offset, read_mask | write_mask);
10483
10484                 val = tr32(offset);
10485
10486                 /* Test the read-only bits. */
10487                 if ((val & read_mask) != read_val)
10488                         goto out;
10489
10490                 /* Test the read/write bits. */
10491                 if ((val & write_mask) != write_mask)
10492                         goto out;
10493
10494                 tw32(offset, save_val);
10495         }
10496
10497         return 0;
10498
10499 out:
10500         if (netif_msg_hw(tp))
10501                 netdev_err(tp->dev,
10502                            "Register test failed at offset %x\n", offset);
10503         tw32(offset, save_val);
10504         return -EIO;
10505 }
10506
10507 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10508 {
10509         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10510         int i;
10511         u32 j;
10512
10513         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10514                 for (j = 0; j < len; j += 4) {
10515                         u32 val;
10516
10517                         tg3_write_mem(tp, offset + j, test_pattern[i]);
10518                         tg3_read_mem(tp, offset + j, &val);
10519                         if (val != test_pattern[i])
10520                                 return -EIO;
10521                 }
10522         }
10523         return 0;
10524 }
10525
10526 static int tg3_test_memory(struct tg3 *tp)
10527 {
10528         static struct mem_entry {
10529                 u32 offset;
10530                 u32 len;
10531         } mem_tbl_570x[] = {
10532                 { 0x00000000, 0x00b50},
10533                 { 0x00002000, 0x1c000},
10534                 { 0xffffffff, 0x00000}
10535         }, mem_tbl_5705[] = {
10536                 { 0x00000100, 0x0000c},
10537                 { 0x00000200, 0x00008},
10538                 { 0x00004000, 0x00800},
10539                 { 0x00006000, 0x01000},
10540                 { 0x00008000, 0x02000},
10541                 { 0x00010000, 0x0e000},
10542                 { 0xffffffff, 0x00000}
10543         }, mem_tbl_5755[] = {
10544                 { 0x00000200, 0x00008},
10545                 { 0x00004000, 0x00800},
10546                 { 0x00006000, 0x00800},
10547                 { 0x00008000, 0x02000},
10548                 { 0x00010000, 0x0c000},
10549                 { 0xffffffff, 0x00000}
10550         }, mem_tbl_5906[] = {
10551                 { 0x00000200, 0x00008},
10552                 { 0x00004000, 0x00400},
10553                 { 0x00006000, 0x00400},
10554                 { 0x00008000, 0x01000},
10555                 { 0x00010000, 0x01000},
10556                 { 0xffffffff, 0x00000}
10557         }, mem_tbl_5717[] = {
10558                 { 0x00000200, 0x00008},
10559                 { 0x00010000, 0x0a000},
10560                 { 0x00020000, 0x13c00},
10561                 { 0xffffffff, 0x00000}
10562         }, mem_tbl_57765[] = {
10563                 { 0x00000200, 0x00008},
10564                 { 0x00004000, 0x00800},
10565                 { 0x00006000, 0x09800},
10566                 { 0x00010000, 0x0a000},
10567                 { 0xffffffff, 0x00000}
10568         };
10569         struct mem_entry *mem_tbl;
10570         int err = 0;
10571         int i;
10572
10573         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
10574             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
10575                 mem_tbl = mem_tbl_5717;
10576         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10577                 mem_tbl = mem_tbl_57765;
10578         else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10579                 mem_tbl = mem_tbl_5755;
10580         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10581                 mem_tbl = mem_tbl_5906;
10582         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10583                 mem_tbl = mem_tbl_5705;
10584         else
10585                 mem_tbl = mem_tbl_570x;
10586
10587         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10588                 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
10589                 if (err)
10590                         break;
10591         }
10592
10593         return err;
10594 }
10595
10596 #define TG3_MAC_LOOPBACK        0
10597 #define TG3_PHY_LOOPBACK        1
10598
10599 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10600 {
10601         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10602         u32 desc_idx, coal_now;
10603         struct sk_buff *skb, *rx_skb;
10604         u8 *tx_data;
10605         dma_addr_t map;
10606         int num_pkts, tx_len, rx_len, i, err;
10607         struct tg3_rx_buffer_desc *desc;
10608         struct tg3_napi *tnapi, *rnapi;
10609         struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
10610
10611         tnapi = &tp->napi[0];
10612         rnapi = &tp->napi[0];
10613         if (tp->irq_cnt > 1) {
10614                 rnapi = &tp->napi[1];
10615                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
10616                         tnapi = &tp->napi[1];
10617         }
10618         coal_now = tnapi->coal_now | rnapi->coal_now;
10619
10620         if (loopback_mode == TG3_MAC_LOOPBACK) {
10621                 /* HW errata - mac loopback fails in some cases on 5780.
10622                  * Normal traffic and PHY loopback are not affected by
10623                  * errata.
10624                  */
10625                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10626                         return 0;
10627
10628                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10629                            MAC_MODE_PORT_INT_LPBACK;
10630                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10631                         mac_mode |= MAC_MODE_LINK_POLARITY;
10632                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
10633                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10634                 else
10635                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10636                 tw32(MAC_MODE, mac_mode);
10637         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10638                 u32 val;
10639
10640                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10641                         tg3_phy_fet_toggle_apd(tp, false);
10642                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10643                 } else
10644                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10645
10646                 tg3_phy_toggle_automdix(tp, 0);
10647
10648                 tg3_writephy(tp, MII_BMCR, val);
10649                 udelay(40);
10650
10651                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10652                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10653                         tg3_writephy(tp, MII_TG3_FET_PTEST,
10654                                      MII_TG3_FET_PTEST_FRC_TX_LINK |
10655                                      MII_TG3_FET_PTEST_FRC_TX_LOCK);
10656                         /* The write needs to be flushed for the AC131 */
10657                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10658                                 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
10659                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10660                 } else
10661                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10662
10663                 /* reset to prevent losing 1st rx packet intermittently */
10664                 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10665                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10666                         udelay(10);
10667                         tw32_f(MAC_RX_MODE, tp->rx_mode);
10668                 }
10669                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10670                         u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
10671                         if (masked_phy_id == TG3_PHY_ID_BCM5401)
10672                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10673                         else if (masked_phy_id == TG3_PHY_ID_BCM5411)
10674                                 mac_mode |= MAC_MODE_LINK_POLARITY;
10675                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
10676                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10677                 }
10678                 tw32(MAC_MODE, mac_mode);
10679         } else {
10680                 return -EINVAL;
10681         }
10682
10683         err = -EIO;
10684
10685         tx_len = 1514;
10686         skb = netdev_alloc_skb(tp->dev, tx_len);
10687         if (!skb)
10688                 return -ENOMEM;
10689
10690         tx_data = skb_put(skb, tx_len);
10691         memcpy(tx_data, tp->dev->dev_addr, 6);
10692         memset(tx_data + 6, 0x0, 8);
10693
10694         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10695
10696         for (i = 14; i < tx_len; i++)
10697                 tx_data[i] = (u8) (i & 0xff);
10698
10699         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10700         if (pci_dma_mapping_error(tp->pdev, map)) {
10701                 dev_kfree_skb(skb);
10702                 return -EIO;
10703         }
10704
10705         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10706                rnapi->coal_now);
10707
10708         udelay(10);
10709
10710         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10711
10712         num_pkts = 0;
10713
10714         tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10715
10716         tnapi->tx_prod++;
10717         num_pkts++;
10718
10719         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10720         tr32_mailbox(tnapi->prodmbox);
10721
10722         udelay(10);
10723
10724         /* 350 usec to allow enough time on some 10/100 Mbps devices.  */
10725         for (i = 0; i < 35; i++) {
10726                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10727                        coal_now);
10728
10729                 udelay(10);
10730
10731                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10732                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10733                 if ((tx_idx == tnapi->tx_prod) &&
10734                     (rx_idx == (rx_start_idx + num_pkts)))
10735                         break;
10736         }
10737
10738         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10739         dev_kfree_skb(skb);
10740
10741         if (tx_idx != tnapi->tx_prod)
10742                 goto out;
10743
10744         if (rx_idx != rx_start_idx + num_pkts)
10745                 goto out;
10746
10747         desc = &rnapi->rx_rcb[rx_start_idx];
10748         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10749         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10750         if (opaque_key != RXD_OPAQUE_RING_STD)
10751                 goto out;
10752
10753         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10754             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10755                 goto out;
10756
10757         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10758         if (rx_len != tx_len)
10759                 goto out;
10760
10761         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10762
10763         map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10764         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10765
10766         for (i = 14; i < tx_len; i++) {
10767                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10768                         goto out;
10769         }
10770         err = 0;
10771
10772         /* tg3_free_rings will unmap and free the rx_skb */
10773 out:
10774         return err;
10775 }
10776
10777 #define TG3_MAC_LOOPBACK_FAILED         1
10778 #define TG3_PHY_LOOPBACK_FAILED         2
10779 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
10780                                          TG3_PHY_LOOPBACK_FAILED)
10781
10782 static int tg3_test_loopback(struct tg3 *tp)
10783 {
10784         int err = 0;
10785         u32 cpmuctrl = 0;
10786
10787         if (!netif_running(tp->dev))
10788                 return TG3_LOOPBACK_FAILED;
10789
10790         err = tg3_reset_hw(tp, 1);
10791         if (err)
10792                 return TG3_LOOPBACK_FAILED;
10793
10794         /* Turn off gphy autopowerdown. */
10795         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
10796                 tg3_phy_toggle_apd(tp, false);
10797
10798         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10799                 int i;
10800                 u32 status;
10801
10802                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10803
10804                 /* Wait for up to 40 microseconds to acquire lock. */
10805                 for (i = 0; i < 4; i++) {
10806                         status = tr32(TG3_CPMU_MUTEX_GNT);
10807                         if (status == CPMU_MUTEX_GNT_DRIVER)
10808                                 break;
10809                         udelay(10);
10810                 }
10811
10812                 if (status != CPMU_MUTEX_GNT_DRIVER)
10813                         return TG3_LOOPBACK_FAILED;
10814
10815                 /* Turn off link-based power management. */
10816                 cpmuctrl = tr32(TG3_CPMU_CTRL);
10817                 tw32(TG3_CPMU_CTRL,
10818                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10819                                   CPMU_CTRL_LINK_AWARE_MODE));
10820         }
10821
10822         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10823                 err |= TG3_MAC_LOOPBACK_FAILED;
10824
10825         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10826                 tw32(TG3_CPMU_CTRL, cpmuctrl);
10827
10828                 /* Release the mutex */
10829                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10830         }
10831
10832         if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10833             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10834                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10835                         err |= TG3_PHY_LOOPBACK_FAILED;
10836         }
10837
10838         /* Re-enable gphy autopowerdown. */
10839         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
10840                 tg3_phy_toggle_apd(tp, true);
10841
10842         return err;
10843 }
10844
10845 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10846                           u64 *data)
10847 {
10848         struct tg3 *tp = netdev_priv(dev);
10849
10850         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10851                 tg3_set_power_state(tp, PCI_D0);
10852
10853         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10854
10855         if (tg3_test_nvram(tp) != 0) {
10856                 etest->flags |= ETH_TEST_FL_FAILED;
10857                 data[0] = 1;
10858         }
10859         if (tg3_test_link(tp) != 0) {
10860                 etest->flags |= ETH_TEST_FL_FAILED;
10861                 data[1] = 1;
10862         }
10863         if (etest->flags & ETH_TEST_FL_OFFLINE) {
10864                 int err, err2 = 0, irq_sync = 0;
10865
10866                 if (netif_running(dev)) {
10867                         tg3_phy_stop(tp);
10868                         tg3_netif_stop(tp);
10869                         irq_sync = 1;
10870                 }
10871
10872                 tg3_full_lock(tp, irq_sync);
10873
10874                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10875                 err = tg3_nvram_lock(tp);
10876                 tg3_halt_cpu(tp, RX_CPU_BASE);
10877                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10878                         tg3_halt_cpu(tp, TX_CPU_BASE);
10879                 if (!err)
10880                         tg3_nvram_unlock(tp);
10881
10882                 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
10883                         tg3_phy_reset(tp);
10884
10885                 if (tg3_test_registers(tp) != 0) {
10886                         etest->flags |= ETH_TEST_FL_FAILED;
10887                         data[2] = 1;
10888                 }
10889                 if (tg3_test_memory(tp) != 0) {
10890                         etest->flags |= ETH_TEST_FL_FAILED;
10891                         data[3] = 1;
10892                 }
10893                 if ((data[4] = tg3_test_loopback(tp)) != 0)
10894                         etest->flags |= ETH_TEST_FL_FAILED;
10895
10896                 tg3_full_unlock(tp);
10897
10898                 if (tg3_test_interrupt(tp) != 0) {
10899                         etest->flags |= ETH_TEST_FL_FAILED;
10900                         data[5] = 1;
10901                 }
10902
10903                 tg3_full_lock(tp, 0);
10904
10905                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10906                 if (netif_running(dev)) {
10907                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10908                         err2 = tg3_restart_hw(tp, 1);
10909                         if (!err2)
10910                                 tg3_netif_start(tp);
10911                 }
10912
10913                 tg3_full_unlock(tp);
10914
10915                 if (irq_sync && !err2)
10916                         tg3_phy_start(tp);
10917         }
10918         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10919                 tg3_set_power_state(tp, PCI_D3hot);
10920
10921 }
10922
10923 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10924 {
10925         struct mii_ioctl_data *data = if_mii(ifr);
10926         struct tg3 *tp = netdev_priv(dev);
10927         int err;
10928
10929         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10930                 struct phy_device *phydev;
10931                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10932                         return -EAGAIN;
10933                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10934                 return phy_mii_ioctl(phydev, ifr, cmd);
10935         }
10936
10937         switch (cmd) {
10938         case SIOCGMIIPHY:
10939                 data->phy_id = tp->phy_addr;
10940
10941                 /* fallthru */
10942         case SIOCGMIIREG: {
10943                 u32 mii_regval;
10944
10945                 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
10946                         break;                  /* We have no PHY */
10947
10948                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10949                         return -EAGAIN;
10950
10951                 spin_lock_bh(&tp->lock);
10952                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10953                 spin_unlock_bh(&tp->lock);
10954
10955                 data->val_out = mii_regval;
10956
10957                 return err;
10958         }
10959
10960         case SIOCSMIIREG:
10961                 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
10962                         break;                  /* We have no PHY */
10963
10964                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10965                         return -EAGAIN;
10966
10967                 spin_lock_bh(&tp->lock);
10968                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10969                 spin_unlock_bh(&tp->lock);
10970
10971                 return err;
10972
10973         default:
10974                 /* do nothing */
10975                 break;
10976         }
10977         return -EOPNOTSUPP;
10978 }
10979
10980 #if TG3_VLAN_TAG_USED
10981 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10982 {
10983         struct tg3 *tp = netdev_priv(dev);
10984
10985         if (!netif_running(dev)) {
10986                 tp->vlgrp = grp;
10987                 return;
10988         }
10989
10990         tg3_netif_stop(tp);
10991
10992         tg3_full_lock(tp, 0);
10993
10994         tp->vlgrp = grp;
10995
10996         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10997         __tg3_set_rx_mode(dev);
10998
10999         tg3_netif_start(tp);
11000
11001         tg3_full_unlock(tp);
11002 }
11003 #endif
11004
11005 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11006 {
11007         struct tg3 *tp = netdev_priv(dev);
11008
11009         memcpy(ec, &tp->coal, sizeof(*ec));
11010         return 0;
11011 }
11012
11013 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11014 {
11015         struct tg3 *tp = netdev_priv(dev);
11016         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11017         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11018
11019         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11020                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11021                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11022                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11023                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11024         }
11025
11026         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11027             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11028             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11029             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11030             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11031             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11032             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11033             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11034             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11035             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11036                 return -EINVAL;
11037
11038         /* No rx interrupts will be generated if both are zero */
11039         if ((ec->rx_coalesce_usecs == 0) &&
11040             (ec->rx_max_coalesced_frames == 0))
11041                 return -EINVAL;
11042
11043         /* No tx interrupts will be generated if both are zero */
11044         if ((ec->tx_coalesce_usecs == 0) &&
11045             (ec->tx_max_coalesced_frames == 0))
11046                 return -EINVAL;
11047
11048         /* Only copy relevant parameters, ignore all others. */
11049         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11050         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11051         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11052         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11053         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11054         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11055         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11056         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11057         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11058
11059         if (netif_running(dev)) {
11060                 tg3_full_lock(tp, 0);
11061                 __tg3_set_coalesce(tp, &tp->coal);
11062                 tg3_full_unlock(tp);
11063         }
11064         return 0;
11065 }
11066
11067 static const struct ethtool_ops tg3_ethtool_ops = {
11068         .get_settings           = tg3_get_settings,
11069         .set_settings           = tg3_set_settings,
11070         .get_drvinfo            = tg3_get_drvinfo,
11071         .get_regs_len           = tg3_get_regs_len,
11072         .get_regs               = tg3_get_regs,
11073         .get_wol                = tg3_get_wol,
11074         .set_wol                = tg3_set_wol,
11075         .get_msglevel           = tg3_get_msglevel,
11076         .set_msglevel           = tg3_set_msglevel,
11077         .nway_reset             = tg3_nway_reset,
11078         .get_link               = ethtool_op_get_link,
11079         .get_eeprom_len         = tg3_get_eeprom_len,
11080         .get_eeprom             = tg3_get_eeprom,
11081         .set_eeprom             = tg3_set_eeprom,
11082         .get_ringparam          = tg3_get_ringparam,
11083         .set_ringparam          = tg3_set_ringparam,
11084         .get_pauseparam         = tg3_get_pauseparam,
11085         .set_pauseparam         = tg3_set_pauseparam,
11086         .get_rx_csum            = tg3_get_rx_csum,
11087         .set_rx_csum            = tg3_set_rx_csum,
11088         .set_tx_csum            = tg3_set_tx_csum,
11089         .set_sg                 = ethtool_op_set_sg,
11090         .set_tso                = tg3_set_tso,
11091         .self_test              = tg3_self_test,
11092         .get_strings            = tg3_get_strings,
11093         .phys_id                = tg3_phys_id,
11094         .get_ethtool_stats      = tg3_get_ethtool_stats,
11095         .get_coalesce           = tg3_get_coalesce,
11096         .set_coalesce           = tg3_set_coalesce,
11097         .get_sset_count         = tg3_get_sset_count,
11098 };
11099
11100 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11101 {
11102         u32 cursize, val, magic;
11103
11104         tp->nvram_size = EEPROM_CHIP_SIZE;
11105
11106         if (tg3_nvram_read(tp, 0, &magic) != 0)
11107                 return;
11108
11109         if ((magic != TG3_EEPROM_MAGIC) &&
11110             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11111             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11112                 return;
11113
11114         /*
11115          * Size the chip by reading offsets at increasing powers of two.
11116          * When we encounter our validation signature, we know the addressing
11117          * has wrapped around, and thus have our chip size.
11118          */
11119         cursize = 0x10;
11120
11121         while (cursize < tp->nvram_size) {
11122                 if (tg3_nvram_read(tp, cursize, &val) != 0)
11123                         return;
11124
11125                 if (val == magic)
11126                         break;
11127
11128                 cursize <<= 1;
11129         }
11130
11131         tp->nvram_size = cursize;
11132 }
11133
11134 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11135 {
11136         u32 val;
11137
11138         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11139             tg3_nvram_read(tp, 0, &val) != 0)
11140                 return;
11141
11142         /* Selfboot format */
11143         if (val != TG3_EEPROM_MAGIC) {
11144                 tg3_get_eeprom_size(tp);
11145                 return;
11146         }
11147
11148         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11149                 if (val != 0) {
11150                         /* This is confusing.  We want to operate on the
11151                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
11152                          * call will read from NVRAM and byteswap the data
11153                          * according to the byteswapping settings for all
11154                          * other register accesses.  This ensures the data we
11155                          * want will always reside in the lower 16-bits.
11156                          * However, the data in NVRAM is in LE format, which
11157                          * means the data from the NVRAM read will always be
11158                          * opposite the endianness of the CPU.  The 16-bit
11159                          * byteswap then brings the data to CPU endianness.
11160                          */
11161                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11162                         return;
11163                 }
11164         }
11165         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11166 }
11167
11168 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11169 {
11170         u32 nvcfg1;
11171
11172         nvcfg1 = tr32(NVRAM_CFG1);
11173         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11174                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11175         } else {
11176                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11177                 tw32(NVRAM_CFG1, nvcfg1);
11178         }
11179
11180         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11181             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11182                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11183                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11184                         tp->nvram_jedecnum = JEDEC_ATMEL;
11185                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11186                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11187                         break;
11188                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11189                         tp->nvram_jedecnum = JEDEC_ATMEL;
11190                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11191                         break;
11192                 case FLASH_VENDOR_ATMEL_EEPROM:
11193                         tp->nvram_jedecnum = JEDEC_ATMEL;
11194                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11195                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11196                         break;
11197                 case FLASH_VENDOR_ST:
11198                         tp->nvram_jedecnum = JEDEC_ST;
11199                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11200                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11201                         break;
11202                 case FLASH_VENDOR_SAIFUN:
11203                         tp->nvram_jedecnum = JEDEC_SAIFUN;
11204                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11205                         break;
11206                 case FLASH_VENDOR_SST_SMALL:
11207                 case FLASH_VENDOR_SST_LARGE:
11208                         tp->nvram_jedecnum = JEDEC_SST;
11209                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11210                         break;
11211                 }
11212         } else {
11213                 tp->nvram_jedecnum = JEDEC_ATMEL;
11214                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11215                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11216         }
11217 }
11218
11219 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11220 {
11221         switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11222         case FLASH_5752PAGE_SIZE_256:
11223                 tp->nvram_pagesize = 256;
11224                 break;
11225         case FLASH_5752PAGE_SIZE_512:
11226                 tp->nvram_pagesize = 512;
11227                 break;
11228         case FLASH_5752PAGE_SIZE_1K:
11229                 tp->nvram_pagesize = 1024;
11230                 break;
11231         case FLASH_5752PAGE_SIZE_2K:
11232                 tp->nvram_pagesize = 2048;
11233                 break;
11234         case FLASH_5752PAGE_SIZE_4K:
11235                 tp->nvram_pagesize = 4096;
11236                 break;
11237         case FLASH_5752PAGE_SIZE_264:
11238                 tp->nvram_pagesize = 264;
11239                 break;
11240         case FLASH_5752PAGE_SIZE_528:
11241                 tp->nvram_pagesize = 528;
11242                 break;
11243         }
11244 }
11245
11246 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11247 {
11248         u32 nvcfg1;
11249
11250         nvcfg1 = tr32(NVRAM_CFG1);
11251
11252         /* NVRAM protection for TPM */
11253         if (nvcfg1 & (1 << 27))
11254                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11255
11256         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11257         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11258         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11259                 tp->nvram_jedecnum = JEDEC_ATMEL;
11260                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11261                 break;
11262         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11263                 tp->nvram_jedecnum = JEDEC_ATMEL;
11264                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11265                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11266                 break;
11267         case FLASH_5752VENDOR_ST_M45PE10:
11268         case FLASH_5752VENDOR_ST_M45PE20:
11269         case FLASH_5752VENDOR_ST_M45PE40:
11270                 tp->nvram_jedecnum = JEDEC_ST;
11271                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11272                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11273                 break;
11274         }
11275
11276         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11277                 tg3_nvram_get_pagesize(tp, nvcfg1);
11278         } else {
11279                 /* For eeprom, set pagesize to maximum eeprom size */
11280                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11281
11282                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11283                 tw32(NVRAM_CFG1, nvcfg1);
11284         }
11285 }
11286
11287 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11288 {
11289         u32 nvcfg1, protect = 0;
11290
11291         nvcfg1 = tr32(NVRAM_CFG1);
11292
11293         /* NVRAM protection for TPM */
11294         if (nvcfg1 & (1 << 27)) {
11295                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11296                 protect = 1;
11297         }
11298
11299         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11300         switch (nvcfg1) {
11301         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11302         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11303         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11304         case FLASH_5755VENDOR_ATMEL_FLASH_5:
11305                 tp->nvram_jedecnum = JEDEC_ATMEL;
11306                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11307                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11308                 tp->nvram_pagesize = 264;
11309                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11310                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11311                         tp->nvram_size = (protect ? 0x3e200 :
11312                                           TG3_NVRAM_SIZE_512KB);
11313                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11314                         tp->nvram_size = (protect ? 0x1f200 :
11315                                           TG3_NVRAM_SIZE_256KB);
11316                 else
11317                         tp->nvram_size = (protect ? 0x1f200 :
11318                                           TG3_NVRAM_SIZE_128KB);
11319                 break;
11320         case FLASH_5752VENDOR_ST_M45PE10:
11321         case FLASH_5752VENDOR_ST_M45PE20:
11322         case FLASH_5752VENDOR_ST_M45PE40:
11323                 tp->nvram_jedecnum = JEDEC_ST;
11324                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11325                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11326                 tp->nvram_pagesize = 256;
11327                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11328                         tp->nvram_size = (protect ?
11329                                           TG3_NVRAM_SIZE_64KB :
11330                                           TG3_NVRAM_SIZE_128KB);
11331                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11332                         tp->nvram_size = (protect ?
11333                                           TG3_NVRAM_SIZE_64KB :
11334                                           TG3_NVRAM_SIZE_256KB);
11335                 else
11336                         tp->nvram_size = (protect ?
11337                                           TG3_NVRAM_SIZE_128KB :
11338                                           TG3_NVRAM_SIZE_512KB);
11339                 break;
11340         }
11341 }
11342
11343 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11344 {
11345         u32 nvcfg1;
11346
11347         nvcfg1 = tr32(NVRAM_CFG1);
11348
11349         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11350         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11351         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11352         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11353         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11354                 tp->nvram_jedecnum = JEDEC_ATMEL;
11355                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11356                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11357
11358                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11359                 tw32(NVRAM_CFG1, nvcfg1);
11360                 break;
11361         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11362         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11363         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11364         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11365                 tp->nvram_jedecnum = JEDEC_ATMEL;
11366                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11367                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11368                 tp->nvram_pagesize = 264;
11369                 break;
11370         case FLASH_5752VENDOR_ST_M45PE10:
11371         case FLASH_5752VENDOR_ST_M45PE20:
11372         case FLASH_5752VENDOR_ST_M45PE40:
11373                 tp->nvram_jedecnum = JEDEC_ST;
11374                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11375                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11376                 tp->nvram_pagesize = 256;
11377                 break;
11378         }
11379 }
11380
11381 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11382 {
11383         u32 nvcfg1, protect = 0;
11384
11385         nvcfg1 = tr32(NVRAM_CFG1);
11386
11387         /* NVRAM protection for TPM */
11388         if (nvcfg1 & (1 << 27)) {
11389                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11390                 protect = 1;
11391         }
11392
11393         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11394         switch (nvcfg1) {
11395         case FLASH_5761VENDOR_ATMEL_ADB021D:
11396         case FLASH_5761VENDOR_ATMEL_ADB041D:
11397         case FLASH_5761VENDOR_ATMEL_ADB081D:
11398         case FLASH_5761VENDOR_ATMEL_ADB161D:
11399         case FLASH_5761VENDOR_ATMEL_MDB021D:
11400         case FLASH_5761VENDOR_ATMEL_MDB041D:
11401         case FLASH_5761VENDOR_ATMEL_MDB081D:
11402         case FLASH_5761VENDOR_ATMEL_MDB161D:
11403                 tp->nvram_jedecnum = JEDEC_ATMEL;
11404                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11405                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11406                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11407                 tp->nvram_pagesize = 256;
11408                 break;
11409         case FLASH_5761VENDOR_ST_A_M45PE20:
11410         case FLASH_5761VENDOR_ST_A_M45PE40:
11411         case FLASH_5761VENDOR_ST_A_M45PE80:
11412         case FLASH_5761VENDOR_ST_A_M45PE16:
11413         case FLASH_5761VENDOR_ST_M_M45PE20:
11414         case FLASH_5761VENDOR_ST_M_M45PE40:
11415         case FLASH_5761VENDOR_ST_M_M45PE80:
11416         case FLASH_5761VENDOR_ST_M_M45PE16:
11417                 tp->nvram_jedecnum = JEDEC_ST;
11418                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11419                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11420                 tp->nvram_pagesize = 256;
11421                 break;
11422         }
11423
11424         if (protect) {
11425                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11426         } else {
11427                 switch (nvcfg1) {
11428                 case FLASH_5761VENDOR_ATMEL_ADB161D:
11429                 case FLASH_5761VENDOR_ATMEL_MDB161D:
11430                 case FLASH_5761VENDOR_ST_A_M45PE16:
11431                 case FLASH_5761VENDOR_ST_M_M45PE16:
11432                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11433                         break;
11434                 case FLASH_5761VENDOR_ATMEL_ADB081D:
11435                 case FLASH_5761VENDOR_ATMEL_MDB081D:
11436                 case FLASH_5761VENDOR_ST_A_M45PE80:
11437                 case FLASH_5761VENDOR_ST_M_M45PE80:
11438                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11439                         break;
11440                 case FLASH_5761VENDOR_ATMEL_ADB041D:
11441                 case FLASH_5761VENDOR_ATMEL_MDB041D:
11442                 case FLASH_5761VENDOR_ST_A_M45PE40:
11443                 case FLASH_5761VENDOR_ST_M_M45PE40:
11444                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11445                         break;
11446                 case FLASH_5761VENDOR_ATMEL_ADB021D:
11447                 case FLASH_5761VENDOR_ATMEL_MDB021D:
11448                 case FLASH_5761VENDOR_ST_A_M45PE20:
11449                 case FLASH_5761VENDOR_ST_M_M45PE20:
11450                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11451                         break;
11452                 }
11453         }
11454 }
11455
11456 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11457 {
11458         tp->nvram_jedecnum = JEDEC_ATMEL;
11459         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11460         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11461 }
11462
11463 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11464 {
11465         u32 nvcfg1;
11466
11467         nvcfg1 = tr32(NVRAM_CFG1);
11468
11469         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11470         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11471         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11472                 tp->nvram_jedecnum = JEDEC_ATMEL;
11473                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11474                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11475
11476                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11477                 tw32(NVRAM_CFG1, nvcfg1);
11478                 return;
11479         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11480         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11481         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11482         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11483         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11484         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11485         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11486                 tp->nvram_jedecnum = JEDEC_ATMEL;
11487                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11488                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11489
11490                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11491                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11492                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11493                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11494                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11495                         break;
11496                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11497                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11498                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11499                         break;
11500                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11501                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11502                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11503                         break;
11504                 }
11505                 break;
11506         case FLASH_5752VENDOR_ST_M45PE10:
11507         case FLASH_5752VENDOR_ST_M45PE20:
11508         case FLASH_5752VENDOR_ST_M45PE40:
11509                 tp->nvram_jedecnum = JEDEC_ST;
11510                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11511                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11512
11513                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11514                 case FLASH_5752VENDOR_ST_M45PE10:
11515                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11516                         break;
11517                 case FLASH_5752VENDOR_ST_M45PE20:
11518                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11519                         break;
11520                 case FLASH_5752VENDOR_ST_M45PE40:
11521                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11522                         break;
11523                 }
11524                 break;
11525         default:
11526                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11527                 return;
11528         }
11529
11530         tg3_nvram_get_pagesize(tp, nvcfg1);
11531         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11532                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11533 }
11534
11535
11536 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11537 {
11538         u32 nvcfg1;
11539
11540         nvcfg1 = tr32(NVRAM_CFG1);
11541
11542         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11543         case FLASH_5717VENDOR_ATMEL_EEPROM:
11544         case FLASH_5717VENDOR_MICRO_EEPROM:
11545                 tp->nvram_jedecnum = JEDEC_ATMEL;
11546                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11547                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11548
11549                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11550                 tw32(NVRAM_CFG1, nvcfg1);
11551                 return;
11552         case FLASH_5717VENDOR_ATMEL_MDB011D:
11553         case FLASH_5717VENDOR_ATMEL_ADB011B:
11554         case FLASH_5717VENDOR_ATMEL_ADB011D:
11555         case FLASH_5717VENDOR_ATMEL_MDB021D:
11556         case FLASH_5717VENDOR_ATMEL_ADB021B:
11557         case FLASH_5717VENDOR_ATMEL_ADB021D:
11558         case FLASH_5717VENDOR_ATMEL_45USPT:
11559                 tp->nvram_jedecnum = JEDEC_ATMEL;
11560                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11561                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11562
11563                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11564                 case FLASH_5717VENDOR_ATMEL_MDB021D:
11565                 case FLASH_5717VENDOR_ATMEL_ADB021B:
11566                 case FLASH_5717VENDOR_ATMEL_ADB021D:
11567                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11568                         break;
11569                 default:
11570                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11571                         break;
11572                 }
11573                 break;
11574         case FLASH_5717VENDOR_ST_M_M25PE10:
11575         case FLASH_5717VENDOR_ST_A_M25PE10:
11576         case FLASH_5717VENDOR_ST_M_M45PE10:
11577         case FLASH_5717VENDOR_ST_A_M45PE10:
11578         case FLASH_5717VENDOR_ST_M_M25PE20:
11579         case FLASH_5717VENDOR_ST_A_M25PE20:
11580         case FLASH_5717VENDOR_ST_M_M45PE20:
11581         case FLASH_5717VENDOR_ST_A_M45PE20:
11582         case FLASH_5717VENDOR_ST_25USPT:
11583         case FLASH_5717VENDOR_ST_45USPT:
11584                 tp->nvram_jedecnum = JEDEC_ST;
11585                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11586                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11587
11588                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11589                 case FLASH_5717VENDOR_ST_M_M25PE20:
11590                 case FLASH_5717VENDOR_ST_A_M25PE20:
11591                 case FLASH_5717VENDOR_ST_M_M45PE20:
11592                 case FLASH_5717VENDOR_ST_A_M45PE20:
11593                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11594                         break;
11595                 default:
11596                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11597                         break;
11598                 }
11599                 break;
11600         default:
11601                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11602                 return;
11603         }
11604
11605         tg3_nvram_get_pagesize(tp, nvcfg1);
11606         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11607                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11608 }
11609
11610 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11611 static void __devinit tg3_nvram_init(struct tg3 *tp)
11612 {
11613         tw32_f(GRC_EEPROM_ADDR,
11614              (EEPROM_ADDR_FSM_RESET |
11615               (EEPROM_DEFAULT_CLOCK_PERIOD <<
11616                EEPROM_ADDR_CLKPERD_SHIFT)));
11617
11618         msleep(1);
11619
11620         /* Enable seeprom accesses. */
11621         tw32_f(GRC_LOCAL_CTRL,
11622              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11623         udelay(100);
11624
11625         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11626             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11627                 tp->tg3_flags |= TG3_FLAG_NVRAM;
11628
11629                 if (tg3_nvram_lock(tp)) {
11630                         netdev_warn(tp->dev,
11631                                     "Cannot get nvram lock, %s failed\n",
11632                                     __func__);
11633                         return;
11634                 }
11635                 tg3_enable_nvram_access(tp);
11636
11637                 tp->nvram_size = 0;
11638
11639                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11640                         tg3_get_5752_nvram_info(tp);
11641                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11642                         tg3_get_5755_nvram_info(tp);
11643                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11644                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11645                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11646                         tg3_get_5787_nvram_info(tp);
11647                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11648                         tg3_get_5761_nvram_info(tp);
11649                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11650                         tg3_get_5906_nvram_info(tp);
11651                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11652                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11653                         tg3_get_57780_nvram_info(tp);
11654                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
11655                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
11656                         tg3_get_5717_nvram_info(tp);
11657                 else
11658                         tg3_get_nvram_info(tp);
11659
11660                 if (tp->nvram_size == 0)
11661                         tg3_get_nvram_size(tp);
11662
11663                 tg3_disable_nvram_access(tp);
11664                 tg3_nvram_unlock(tp);
11665
11666         } else {
11667                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11668
11669                 tg3_get_eeprom_size(tp);
11670         }
11671 }
11672
11673 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11674                                     u32 offset, u32 len, u8 *buf)
11675 {
11676         int i, j, rc = 0;
11677         u32 val;
11678
11679         for (i = 0; i < len; i += 4) {
11680                 u32 addr;
11681                 __be32 data;
11682
11683                 addr = offset + i;
11684
11685                 memcpy(&data, buf + i, 4);
11686
11687                 /*
11688                  * The SEEPROM interface expects the data to always be opposite
11689                  * the native endian format.  We accomplish this by reversing
11690                  * all the operations that would have been performed on the
11691                  * data from a call to tg3_nvram_read_be32().
11692                  */
11693                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11694
11695                 val = tr32(GRC_EEPROM_ADDR);
11696                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11697
11698                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11699                         EEPROM_ADDR_READ);
11700                 tw32(GRC_EEPROM_ADDR, val |
11701                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
11702                         (addr & EEPROM_ADDR_ADDR_MASK) |
11703                         EEPROM_ADDR_START |
11704                         EEPROM_ADDR_WRITE);
11705
11706                 for (j = 0; j < 1000; j++) {
11707                         val = tr32(GRC_EEPROM_ADDR);
11708
11709                         if (val & EEPROM_ADDR_COMPLETE)
11710                                 break;
11711                         msleep(1);
11712                 }
11713                 if (!(val & EEPROM_ADDR_COMPLETE)) {
11714                         rc = -EBUSY;
11715                         break;
11716                 }
11717         }
11718
11719         return rc;
11720 }
11721
11722 /* offset and length are dword aligned */
11723 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11724                 u8 *buf)
11725 {
11726         int ret = 0;
11727         u32 pagesize = tp->nvram_pagesize;
11728         u32 pagemask = pagesize - 1;
11729         u32 nvram_cmd;
11730         u8 *tmp;
11731
11732         tmp = kmalloc(pagesize, GFP_KERNEL);
11733         if (tmp == NULL)
11734                 return -ENOMEM;
11735
11736         while (len) {
11737                 int j;
11738                 u32 phy_addr, page_off, size;
11739
11740                 phy_addr = offset & ~pagemask;
11741
11742                 for (j = 0; j < pagesize; j += 4) {
11743                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
11744                                                   (__be32 *) (tmp + j));
11745                         if (ret)
11746                                 break;
11747                 }
11748                 if (ret)
11749                         break;
11750
11751                 page_off = offset & pagemask;
11752                 size = pagesize;
11753                 if (len < size)
11754                         size = len;
11755
11756                 len -= size;
11757
11758                 memcpy(tmp + page_off, buf, size);
11759
11760                 offset = offset + (pagesize - page_off);
11761
11762                 tg3_enable_nvram_access(tp);
11763
11764                 /*
11765                  * Before we can erase the flash page, we need
11766                  * to issue a special "write enable" command.
11767                  */
11768                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11769
11770                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11771                         break;
11772
11773                 /* Erase the target page */
11774                 tw32(NVRAM_ADDR, phy_addr);
11775
11776                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11777                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11778
11779                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11780                         break;
11781
11782                 /* Issue another write enable to start the write. */
11783                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11784
11785                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11786                         break;
11787
11788                 for (j = 0; j < pagesize; j += 4) {
11789                         __be32 data;
11790
11791                         data = *((__be32 *) (tmp + j));
11792
11793                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
11794
11795                         tw32(NVRAM_ADDR, phy_addr + j);
11796
11797                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11798                                 NVRAM_CMD_WR;
11799
11800                         if (j == 0)
11801                                 nvram_cmd |= NVRAM_CMD_FIRST;
11802                         else if (j == (pagesize - 4))
11803                                 nvram_cmd |= NVRAM_CMD_LAST;
11804
11805                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11806                                 break;
11807                 }
11808                 if (ret)
11809                         break;
11810         }
11811
11812         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11813         tg3_nvram_exec_cmd(tp, nvram_cmd);
11814
11815         kfree(tmp);
11816
11817         return ret;
11818 }
11819
11820 /* offset and length are dword aligned */
11821 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11822                 u8 *buf)
11823 {
11824         int i, ret = 0;
11825
11826         for (i = 0; i < len; i += 4, offset += 4) {
11827                 u32 page_off, phy_addr, nvram_cmd;
11828                 __be32 data;
11829
11830                 memcpy(&data, buf + i, 4);
11831                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11832
11833                 page_off = offset % tp->nvram_pagesize;
11834
11835                 phy_addr = tg3_nvram_phys_addr(tp, offset);
11836
11837                 tw32(NVRAM_ADDR, phy_addr);
11838
11839                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11840
11841                 if (page_off == 0 || i == 0)
11842                         nvram_cmd |= NVRAM_CMD_FIRST;
11843                 if (page_off == (tp->nvram_pagesize - 4))
11844                         nvram_cmd |= NVRAM_CMD_LAST;
11845
11846                 if (i == (len - 4))
11847                         nvram_cmd |= NVRAM_CMD_LAST;
11848
11849                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11850                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11851                     (tp->nvram_jedecnum == JEDEC_ST) &&
11852                     (nvram_cmd & NVRAM_CMD_FIRST)) {
11853
11854                         if ((ret = tg3_nvram_exec_cmd(tp,
11855                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11856                                 NVRAM_CMD_DONE)))
11857
11858                                 break;
11859                 }
11860                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11861                         /* We always do complete word writes to eeprom. */
11862                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11863                 }
11864
11865                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11866                         break;
11867         }
11868         return ret;
11869 }
11870
11871 /* offset and length are dword aligned */
11872 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11873 {
11874         int ret;
11875
11876         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11877                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11878                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
11879                 udelay(40);
11880         }
11881
11882         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11883                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11884         } else {
11885                 u32 grc_mode;
11886
11887                 ret = tg3_nvram_lock(tp);
11888                 if (ret)
11889                         return ret;
11890
11891                 tg3_enable_nvram_access(tp);
11892                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11893                     !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
11894                         tw32(NVRAM_WRITE1, 0x406);
11895
11896                 grc_mode = tr32(GRC_MODE);
11897                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11898
11899                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11900                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11901
11902                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
11903                                 buf);
11904                 } else {
11905                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11906                                 buf);
11907                 }
11908
11909                 grc_mode = tr32(GRC_MODE);
11910                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11911
11912                 tg3_disable_nvram_access(tp);
11913                 tg3_nvram_unlock(tp);
11914         }
11915
11916         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11917                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11918                 udelay(40);
11919         }
11920
11921         return ret;
11922 }
11923
11924 struct subsys_tbl_ent {
11925         u16 subsys_vendor, subsys_devid;
11926         u32 phy_id;
11927 };
11928
11929 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
11930         /* Broadcom boards. */
11931         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11932           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
11933         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11934           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
11935         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11936           TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
11937         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11938           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
11939         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11940           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
11941         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11942           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
11943         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11944           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
11945         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11946           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
11947         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11948           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
11949         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11950           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
11951         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11952           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
11953
11954         /* 3com boards. */
11955         { TG3PCI_SUBVENDOR_ID_3COM,
11956           TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
11957         { TG3PCI_SUBVENDOR_ID_3COM,
11958           TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
11959         { TG3PCI_SUBVENDOR_ID_3COM,
11960           TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
11961         { TG3PCI_SUBVENDOR_ID_3COM,
11962           TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
11963         { TG3PCI_SUBVENDOR_ID_3COM,
11964           TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
11965
11966         /* DELL boards. */
11967         { TG3PCI_SUBVENDOR_ID_DELL,
11968           TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
11969         { TG3PCI_SUBVENDOR_ID_DELL,
11970           TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
11971         { TG3PCI_SUBVENDOR_ID_DELL,
11972           TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
11973         { TG3PCI_SUBVENDOR_ID_DELL,
11974           TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
11975
11976         /* Compaq boards. */
11977         { TG3PCI_SUBVENDOR_ID_COMPAQ,
11978           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
11979         { TG3PCI_SUBVENDOR_ID_COMPAQ,
11980           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
11981         { TG3PCI_SUBVENDOR_ID_COMPAQ,
11982           TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
11983         { TG3PCI_SUBVENDOR_ID_COMPAQ,
11984           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
11985         { TG3PCI_SUBVENDOR_ID_COMPAQ,
11986           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
11987
11988         /* IBM boards. */
11989         { TG3PCI_SUBVENDOR_ID_IBM,
11990           TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
11991 };
11992
11993 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
11994 {
11995         int i;
11996
11997         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11998                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11999                      tp->pdev->subsystem_vendor) &&
12000                     (subsys_id_to_phy_id[i].subsys_devid ==
12001                      tp->pdev->subsystem_device))
12002                         return &subsys_id_to_phy_id[i];
12003         }
12004         return NULL;
12005 }
12006
12007 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12008 {
12009         u32 val;
12010         u16 pmcsr;
12011
12012         /* On some early chips the SRAM cannot be accessed in D3hot state,
12013          * so need make sure we're in D0.
12014          */
12015         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12016         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12017         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12018         msleep(1);
12019
12020         /* Make sure register accesses (indirect or otherwise)
12021          * will function correctly.
12022          */
12023         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12024                                tp->misc_host_ctrl);
12025
12026         /* The memory arbiter has to be enabled in order for SRAM accesses
12027          * to succeed.  Normally on powerup the tg3 chip firmware will make
12028          * sure it is enabled, but other entities such as system netboot
12029          * code might disable it.
12030          */
12031         val = tr32(MEMARB_MODE);
12032         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12033
12034         tp->phy_id = TG3_PHY_ID_INVALID;
12035         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12036
12037         /* Assume an onboard device and WOL capable by default.  */
12038         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12039
12040         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12041                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12042                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12043                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12044                 }
12045                 val = tr32(VCPU_CFGSHDW);
12046                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12047                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12048                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12049                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
12050                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12051                 goto done;
12052         }
12053
12054         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12055         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12056                 u32 nic_cfg, led_cfg;
12057                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12058                 int eeprom_phy_serdes = 0;
12059
12060                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12061                 tp->nic_sram_data_cfg = nic_cfg;
12062
12063                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12064                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12065                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12066                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12067                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12068                     (ver > 0) && (ver < 0x100))
12069                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12070
12071                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12072                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12073
12074                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12075                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12076                         eeprom_phy_serdes = 1;
12077
12078                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12079                 if (nic_phy_id != 0) {
12080                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12081                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12082
12083                         eeprom_phy_id  = (id1 >> 16) << 10;
12084                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
12085                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
12086                 } else
12087                         eeprom_phy_id = 0;
12088
12089                 tp->phy_id = eeprom_phy_id;
12090                 if (eeprom_phy_serdes) {
12091                         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12092                                 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12093                         else
12094                                 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
12095                 }
12096
12097                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12098                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12099                                     SHASTA_EXT_LED_MODE_MASK);
12100                 else
12101                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12102
12103                 switch (led_cfg) {
12104                 default:
12105                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12106                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12107                         break;
12108
12109                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12110                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12111                         break;
12112
12113                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12114                         tp->led_ctrl = LED_CTRL_MODE_MAC;
12115
12116                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12117                          * read on some older 5700/5701 bootcode.
12118                          */
12119                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12120                             ASIC_REV_5700 ||
12121                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
12122                             ASIC_REV_5701)
12123                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12124
12125                         break;
12126
12127                 case SHASTA_EXT_LED_SHARED:
12128                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
12129                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12130                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12131                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12132                                                  LED_CTRL_MODE_PHY_2);
12133                         break;
12134
12135                 case SHASTA_EXT_LED_MAC:
12136                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12137                         break;
12138
12139                 case SHASTA_EXT_LED_COMBO:
12140                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
12141                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12142                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12143                                                  LED_CTRL_MODE_PHY_2);
12144                         break;
12145
12146                 }
12147
12148                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12149                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12150                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12151                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12152
12153                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12154                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12155
12156                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12157                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12158                         if ((tp->pdev->subsystem_vendor ==
12159                              PCI_VENDOR_ID_ARIMA) &&
12160                             (tp->pdev->subsystem_device == 0x205a ||
12161                              tp->pdev->subsystem_device == 0x2063))
12162                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12163                 } else {
12164                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12165                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12166                 }
12167
12168                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12169                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12170                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12171                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12172                 }
12173
12174                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12175                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12176                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12177
12178                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
12179                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12180                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12181
12182                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12183                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12184                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12185
12186                 if (cfg2 & (1 << 17))
12187                         tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
12188
12189                 /* serdes signal pre-emphasis in register 0x590 set by */
12190                 /* bootcode if bit 18 is set */
12191                 if (cfg2 & (1 << 18))
12192                         tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
12193
12194                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12195                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
12196                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12197                         tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
12198
12199                 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12200                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12201                     !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
12202                         u32 cfg3;
12203
12204                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12205                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12206                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12207                 }
12208
12209                 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12210                         tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
12211                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12212                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12213                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12214                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12215         }
12216 done:
12217         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12218         device_set_wakeup_enable(&tp->pdev->dev,
12219                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12220 }
12221
12222 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12223 {
12224         int i;
12225         u32 val;
12226
12227         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12228         tw32(OTP_CTRL, cmd);
12229
12230         /* Wait for up to 1 ms for command to execute. */
12231         for (i = 0; i < 100; i++) {
12232                 val = tr32(OTP_STATUS);
12233                 if (val & OTP_STATUS_CMD_DONE)
12234                         break;
12235                 udelay(10);
12236         }
12237
12238         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12239 }
12240
12241 /* Read the gphy configuration from the OTP region of the chip.  The gphy
12242  * configuration is a 32-bit value that straddles the alignment boundary.
12243  * We do two 32-bit reads and then shift and merge the results.
12244  */
12245 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12246 {
12247         u32 bhalf_otp, thalf_otp;
12248
12249         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12250
12251         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12252                 return 0;
12253
12254         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12255
12256         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12257                 return 0;
12258
12259         thalf_otp = tr32(OTP_READ_DATA);
12260
12261         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12262
12263         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12264                 return 0;
12265
12266         bhalf_otp = tr32(OTP_READ_DATA);
12267
12268         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12269 }
12270
12271 static int __devinit tg3_phy_probe(struct tg3 *tp)
12272 {
12273         u32 hw_phy_id_1, hw_phy_id_2;
12274         u32 hw_phy_id, hw_phy_id_masked;
12275         int err;
12276
12277         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12278                 return tg3_phy_init(tp);
12279
12280         /* Reading the PHY ID register can conflict with ASF
12281          * firmware access to the PHY hardware.
12282          */
12283         err = 0;
12284         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12285             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12286                 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
12287         } else {
12288                 /* Now read the physical PHY_ID from the chip and verify
12289                  * that it is sane.  If it doesn't look good, we fall back
12290                  * to either the hard-coded table based PHY_ID and failing
12291                  * that the value found in the eeprom area.
12292                  */
12293                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12294                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12295
12296                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
12297                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12298                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
12299
12300                 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
12301         }
12302
12303         if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
12304                 tp->phy_id = hw_phy_id;
12305                 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
12306                         tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12307                 else
12308                         tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
12309         } else {
12310                 if (tp->phy_id != TG3_PHY_ID_INVALID) {
12311                         /* Do nothing, phy ID already set up in
12312                          * tg3_get_eeprom_hw_cfg().
12313                          */
12314                 } else {
12315                         struct subsys_tbl_ent *p;
12316
12317                         /* No eeprom signature?  Try the hardcoded
12318                          * subsys device table.
12319                          */
12320                         p = tg3_lookup_by_subsys(tp);
12321                         if (!p)
12322                                 return -ENODEV;
12323
12324                         tp->phy_id = p->phy_id;
12325                         if (!tp->phy_id ||
12326                             tp->phy_id == TG3_PHY_ID_BCM8002)
12327                                 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12328                 }
12329         }
12330
12331         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
12332             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12333             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12334                 u32 bmsr, adv_reg, tg3_ctrl, mask;
12335
12336                 tg3_readphy(tp, MII_BMSR, &bmsr);
12337                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12338                     (bmsr & BMSR_LSTATUS))
12339                         goto skip_phy_reset;
12340
12341                 err = tg3_phy_reset(tp);
12342                 if (err)
12343                         return err;
12344
12345                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12346                            ADVERTISE_100HALF | ADVERTISE_100FULL |
12347                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12348                 tg3_ctrl = 0;
12349                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
12350                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12351                                     MII_TG3_CTRL_ADV_1000_FULL);
12352                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12353                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12354                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12355                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
12356                 }
12357
12358                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12359                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12360                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12361                 if (!tg3_copper_is_advertising_all(tp, mask)) {
12362                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12363
12364                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12365                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12366
12367                         tg3_writephy(tp, MII_BMCR,
12368                                      BMCR_ANENABLE | BMCR_ANRESTART);
12369                 }
12370                 tg3_phy_set_wirespeed(tp);
12371
12372                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12373                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12374                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12375         }
12376
12377 skip_phy_reset:
12378         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
12379                 err = tg3_init_5401phy_dsp(tp);
12380                 if (err)
12381                         return err;
12382
12383                 err = tg3_init_5401phy_dsp(tp);
12384         }
12385
12386         if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
12387                 tp->link_config.advertising =
12388                         (ADVERTISED_1000baseT_Half |
12389                          ADVERTISED_1000baseT_Full |
12390                          ADVERTISED_Autoneg |
12391                          ADVERTISED_FIBRE);
12392         if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
12393                 tp->link_config.advertising &=
12394                         ~(ADVERTISED_1000baseT_Half |
12395                           ADVERTISED_1000baseT_Full);
12396
12397         return err;
12398 }
12399
12400 static void __devinit tg3_read_vpd(struct tg3 *tp)
12401 {
12402         u8 *vpd_data;
12403         unsigned int block_end, rosize, len;
12404         int j, i = 0;
12405         u32 magic;
12406
12407         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12408             tg3_nvram_read(tp, 0x0, &magic))
12409                 goto out_no_vpd;
12410
12411         vpd_data = kmalloc(TG3_NVM_VPD_LEN, GFP_KERNEL);
12412         if (!vpd_data)
12413                 goto out_no_vpd;
12414
12415         if (magic == TG3_EEPROM_MAGIC) {
12416                 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12417                         u32 tmp;
12418
12419                         /* The data is in little-endian format in NVRAM.
12420                          * Use the big-endian read routines to preserve
12421                          * the byte order as it exists in NVRAM.
12422                          */
12423                         if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12424                                 goto out_not_found;
12425
12426                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12427                 }
12428         } else {
12429                 ssize_t cnt;
12430                 unsigned int pos = 0;
12431
12432                 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12433                         cnt = pci_read_vpd(tp->pdev, pos,
12434                                            TG3_NVM_VPD_LEN - pos,
12435                                            &vpd_data[pos]);
12436                         if (cnt == -ETIMEDOUT || -EINTR)
12437                                 cnt = 0;
12438                         else if (cnt < 0)
12439                                 goto out_not_found;
12440                 }
12441                 if (pos != TG3_NVM_VPD_LEN)
12442                         goto out_not_found;
12443         }
12444
12445         i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
12446                              PCI_VPD_LRDT_RO_DATA);
12447         if (i < 0)
12448                 goto out_not_found;
12449
12450         rosize = pci_vpd_lrdt_size(&vpd_data[i]);
12451         block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
12452         i += PCI_VPD_LRDT_TAG_SIZE;
12453
12454         if (block_end > TG3_NVM_VPD_LEN)
12455                 goto out_not_found;
12456
12457         j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12458                                       PCI_VPD_RO_KEYWORD_MFR_ID);
12459         if (j > 0) {
12460                 len = pci_vpd_info_field_size(&vpd_data[j]);
12461
12462                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12463                 if (j + len > block_end || len != 4 ||
12464                     memcmp(&vpd_data[j], "1028", 4))
12465                         goto partno;
12466
12467                 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12468                                               PCI_VPD_RO_KEYWORD_VENDOR0);
12469                 if (j < 0)
12470                         goto partno;
12471
12472                 len = pci_vpd_info_field_size(&vpd_data[j]);
12473
12474                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12475                 if (j + len > block_end)
12476                         goto partno;
12477
12478                 memcpy(tp->fw_ver, &vpd_data[j], len);
12479                 strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
12480         }
12481
12482 partno:
12483         i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12484                                       PCI_VPD_RO_KEYWORD_PARTNO);
12485         if (i < 0)
12486                 goto out_not_found;
12487
12488         len = pci_vpd_info_field_size(&vpd_data[i]);
12489
12490         i += PCI_VPD_INFO_FLD_HDR_SIZE;
12491         if (len > TG3_BPN_SIZE ||
12492             (len + i) > TG3_NVM_VPD_LEN)
12493                 goto out_not_found;
12494
12495         memcpy(tp->board_part_number, &vpd_data[i], len);
12496
12497 out_not_found:
12498         kfree(vpd_data);
12499         if (!tp->board_part_number[0])
12500                 return;
12501
12502 out_no_vpd:
12503         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12504                 strcpy(tp->board_part_number, "BCM95906");
12505         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12506                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12507                 strcpy(tp->board_part_number, "BCM57780");
12508         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12509                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12510                 strcpy(tp->board_part_number, "BCM57760");
12511         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12512                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12513                 strcpy(tp->board_part_number, "BCM57790");
12514         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12515                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12516                 strcpy(tp->board_part_number, "BCM57788");
12517         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12518                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
12519                 strcpy(tp->board_part_number, "BCM57761");
12520         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12521                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
12522                 strcpy(tp->board_part_number, "BCM57765");
12523         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12524                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
12525                 strcpy(tp->board_part_number, "BCM57781");
12526         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12527                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
12528                 strcpy(tp->board_part_number, "BCM57785");
12529         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12530                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
12531                 strcpy(tp->board_part_number, "BCM57791");
12532         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12533                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12534                 strcpy(tp->board_part_number, "BCM57795");
12535         else
12536                 strcpy(tp->board_part_number, "none");
12537 }
12538
12539 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12540 {
12541         u32 val;
12542
12543         if (tg3_nvram_read(tp, offset, &val) ||
12544             (val & 0xfc000000) != 0x0c000000 ||
12545             tg3_nvram_read(tp, offset + 4, &val) ||
12546             val != 0)
12547                 return 0;
12548
12549         return 1;
12550 }
12551
12552 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12553 {
12554         u32 val, offset, start, ver_offset;
12555         int i, dst_off;
12556         bool newver = false;
12557
12558         if (tg3_nvram_read(tp, 0xc, &offset) ||
12559             tg3_nvram_read(tp, 0x4, &start))
12560                 return;
12561
12562         offset = tg3_nvram_logical_addr(tp, offset);
12563
12564         if (tg3_nvram_read(tp, offset, &val))
12565                 return;
12566
12567         if ((val & 0xfc000000) == 0x0c000000) {
12568                 if (tg3_nvram_read(tp, offset + 4, &val))
12569                         return;
12570
12571                 if (val == 0)
12572                         newver = true;
12573         }
12574
12575         dst_off = strlen(tp->fw_ver);
12576
12577         if (newver) {
12578                 if (TG3_VER_SIZE - dst_off < 16 ||
12579                     tg3_nvram_read(tp, offset + 8, &ver_offset))
12580                         return;
12581
12582                 offset = offset + ver_offset - start;
12583                 for (i = 0; i < 16; i += 4) {
12584                         __be32 v;
12585                         if (tg3_nvram_read_be32(tp, offset + i, &v))
12586                                 return;
12587
12588                         memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
12589                 }
12590         } else {
12591                 u32 major, minor;
12592
12593                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12594                         return;
12595
12596                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12597                         TG3_NVM_BCVER_MAJSFT;
12598                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12599                 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
12600                          "v%d.%02d", major, minor);
12601         }
12602 }
12603
12604 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12605 {
12606         u32 val, major, minor;
12607
12608         /* Use native endian representation */
12609         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12610                 return;
12611
12612         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12613                 TG3_NVM_HWSB_CFG1_MAJSFT;
12614         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12615                 TG3_NVM_HWSB_CFG1_MINSFT;
12616
12617         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12618 }
12619
12620 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12621 {
12622         u32 offset, major, minor, build;
12623
12624         strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
12625
12626         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12627                 return;
12628
12629         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12630         case TG3_EEPROM_SB_REVISION_0:
12631                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12632                 break;
12633         case TG3_EEPROM_SB_REVISION_2:
12634                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12635                 break;
12636         case TG3_EEPROM_SB_REVISION_3:
12637                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12638                 break;
12639         case TG3_EEPROM_SB_REVISION_4:
12640                 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
12641                 break;
12642         case TG3_EEPROM_SB_REVISION_5:
12643                 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
12644                 break;
12645         default:
12646                 return;
12647         }
12648
12649         if (tg3_nvram_read(tp, offset, &val))
12650                 return;
12651
12652         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12653                 TG3_EEPROM_SB_EDH_BLD_SHFT;
12654         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12655                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12656         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
12657
12658         if (minor > 99 || build > 26)
12659                 return;
12660
12661         offset = strlen(tp->fw_ver);
12662         snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
12663                  " v%d.%02d", major, minor);
12664
12665         if (build > 0) {
12666                 offset = strlen(tp->fw_ver);
12667                 if (offset < TG3_VER_SIZE - 1)
12668                         tp->fw_ver[offset] = 'a' + build - 1;
12669         }
12670 }
12671
12672 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12673 {
12674         u32 val, offset, start;
12675         int i, vlen;
12676
12677         for (offset = TG3_NVM_DIR_START;
12678              offset < TG3_NVM_DIR_END;
12679              offset += TG3_NVM_DIRENT_SIZE) {
12680                 if (tg3_nvram_read(tp, offset, &val))
12681                         return;
12682
12683                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12684                         break;
12685         }
12686
12687         if (offset == TG3_NVM_DIR_END)
12688                 return;
12689
12690         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12691                 start = 0x08000000;
12692         else if (tg3_nvram_read(tp, offset - 4, &start))
12693                 return;
12694
12695         if (tg3_nvram_read(tp, offset + 4, &offset) ||
12696             !tg3_fw_img_is_valid(tp, offset) ||
12697             tg3_nvram_read(tp, offset + 8, &val))
12698                 return;
12699
12700         offset += val - start;
12701
12702         vlen = strlen(tp->fw_ver);
12703
12704         tp->fw_ver[vlen++] = ',';
12705         tp->fw_ver[vlen++] = ' ';
12706
12707         for (i = 0; i < 4; i++) {
12708                 __be32 v;
12709                 if (tg3_nvram_read_be32(tp, offset, &v))
12710                         return;
12711
12712                 offset += sizeof(v);
12713
12714                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12715                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12716                         break;
12717                 }
12718
12719                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12720                 vlen += sizeof(v);
12721         }
12722 }
12723
12724 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12725 {
12726         int vlen;
12727         u32 apedata;
12728         char *fwtype;
12729
12730         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12731             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
12732                 return;
12733
12734         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12735         if (apedata != APE_SEG_SIG_MAGIC)
12736                 return;
12737
12738         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12739         if (!(apedata & APE_FW_STATUS_READY))
12740                 return;
12741
12742         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12743
12744         if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) {
12745                 tp->tg3_flags3 |= TG3_FLG3_APE_HAS_NCSI;
12746                 fwtype = "NCSI";
12747         } else {
12748                 fwtype = "DASH";
12749         }
12750
12751         vlen = strlen(tp->fw_ver);
12752
12753         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
12754                  fwtype,
12755                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12756                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12757                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12758                  (apedata & APE_FW_VERSION_BLDMSK));
12759 }
12760
12761 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12762 {
12763         u32 val;
12764         bool vpd_vers = false;
12765
12766         if (tp->fw_ver[0] != 0)
12767                 vpd_vers = true;
12768
12769         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12770                 strcat(tp->fw_ver, "sb");
12771                 return;
12772         }
12773
12774         if (tg3_nvram_read(tp, 0, &val))
12775                 return;
12776
12777         if (val == TG3_EEPROM_MAGIC)
12778                 tg3_read_bc_ver(tp);
12779         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12780                 tg3_read_sb_ver(tp, val);
12781         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12782                 tg3_read_hwsb_ver(tp);
12783         else
12784                 return;
12785
12786         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12787              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
12788                 goto done;
12789
12790         tg3_read_mgmtfw_ver(tp);
12791
12792 done:
12793         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12794 }
12795
12796 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12797
12798 static void inline vlan_features_add(struct net_device *dev, unsigned long flags)
12799 {
12800 #if TG3_VLAN_TAG_USED
12801         dev->vlan_features |= flags;
12802 #endif
12803 }
12804
12805 static int __devinit tg3_get_invariants(struct tg3 *tp)
12806 {
12807         static struct pci_device_id write_reorder_chipsets[] = {
12808                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12809                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12810                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12811                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12812                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12813                              PCI_DEVICE_ID_VIA_8385_0) },
12814                 { },
12815         };
12816         u32 misc_ctrl_reg;
12817         u32 pci_state_reg, grc_misc_cfg;
12818         u32 val;
12819         u16 pci_cmd;
12820         int err;
12821
12822         /* Force memory write invalidate off.  If we leave it on,
12823          * then on 5700_BX chips we have to enable a workaround.
12824          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12825          * to match the cacheline size.  The Broadcom driver have this
12826          * workaround but turns MWI off all the times so never uses
12827          * it.  This seems to suggest that the workaround is insufficient.
12828          */
12829         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12830         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12831         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12832
12833         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12834          * has the register indirect write enable bit set before
12835          * we try to access any of the MMIO registers.  It is also
12836          * critical that the PCI-X hw workaround situation is decided
12837          * before that as well.
12838          */
12839         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12840                               &misc_ctrl_reg);
12841
12842         tp->pci_chip_rev_id = (misc_ctrl_reg >>
12843                                MISC_HOST_CTRL_CHIPREV_SHIFT);
12844         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12845                 u32 prod_id_asic_rev;
12846
12847                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12848                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12849                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724 ||
12850                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719)
12851                         pci_read_config_dword(tp->pdev,
12852                                               TG3PCI_GEN2_PRODID_ASICREV,
12853                                               &prod_id_asic_rev);
12854                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
12855                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
12856                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
12857                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
12858                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
12859                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12860                         pci_read_config_dword(tp->pdev,
12861                                               TG3PCI_GEN15_PRODID_ASICREV,
12862                                               &prod_id_asic_rev);
12863                 else
12864                         pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12865                                               &prod_id_asic_rev);
12866
12867                 tp->pci_chip_rev_id = prod_id_asic_rev;
12868         }
12869
12870         /* Wrong chip ID in 5752 A0. This code can be removed later
12871          * as A0 is not in production.
12872          */
12873         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12874                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12875
12876         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12877          * we need to disable memory and use config. cycles
12878          * only to access all registers. The 5702/03 chips
12879          * can mistakenly decode the special cycles from the
12880          * ICH chipsets as memory write cycles, causing corruption
12881          * of register and memory space. Only certain ICH bridges
12882          * will drive special cycles with non-zero data during the
12883          * address phase which can fall within the 5703's address
12884          * range. This is not an ICH bug as the PCI spec allows
12885          * non-zero address during special cycles. However, only
12886          * these ICH bridges are known to drive non-zero addresses
12887          * during special cycles.
12888          *
12889          * Since special cycles do not cross PCI bridges, we only
12890          * enable this workaround if the 5703 is on the secondary
12891          * bus of these ICH bridges.
12892          */
12893         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12894             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12895                 static struct tg3_dev_id {
12896                         u32     vendor;
12897                         u32     device;
12898                         u32     rev;
12899                 } ich_chipsets[] = {
12900                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12901                           PCI_ANY_ID },
12902                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12903                           PCI_ANY_ID },
12904                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12905                           0xa },
12906                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12907                           PCI_ANY_ID },
12908                         { },
12909                 };
12910                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12911                 struct pci_dev *bridge = NULL;
12912
12913                 while (pci_id->vendor != 0) {
12914                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
12915                                                 bridge);
12916                         if (!bridge) {
12917                                 pci_id++;
12918                                 continue;
12919                         }
12920                         if (pci_id->rev != PCI_ANY_ID) {
12921                                 if (bridge->revision > pci_id->rev)
12922                                         continue;
12923                         }
12924                         if (bridge->subordinate &&
12925                             (bridge->subordinate->number ==
12926                              tp->pdev->bus->number)) {
12927
12928                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12929                                 pci_dev_put(bridge);
12930                                 break;
12931                         }
12932                 }
12933         }
12934
12935         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12936                 static struct tg3_dev_id {
12937                         u32     vendor;
12938                         u32     device;
12939                 } bridge_chipsets[] = {
12940                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12941                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12942                         { },
12943                 };
12944                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12945                 struct pci_dev *bridge = NULL;
12946
12947                 while (pci_id->vendor != 0) {
12948                         bridge = pci_get_device(pci_id->vendor,
12949                                                 pci_id->device,
12950                                                 bridge);
12951                         if (!bridge) {
12952                                 pci_id++;
12953                                 continue;
12954                         }
12955                         if (bridge->subordinate &&
12956                             (bridge->subordinate->number <=
12957                              tp->pdev->bus->number) &&
12958                             (bridge->subordinate->subordinate >=
12959                              tp->pdev->bus->number)) {
12960                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12961                                 pci_dev_put(bridge);
12962                                 break;
12963                         }
12964                 }
12965         }
12966
12967         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12968          * DMA addresses > 40-bit. This bridge may have other additional
12969          * 57xx devices behind it in some 4-port NIC designs for example.
12970          * Any tg3 device found behind the bridge will also need the 40-bit
12971          * DMA workaround.
12972          */
12973         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12974             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12975                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
12976                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12977                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
12978         } else {
12979                 struct pci_dev *bridge = NULL;
12980
12981                 do {
12982                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12983                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
12984                                                 bridge);
12985                         if (bridge && bridge->subordinate &&
12986                             (bridge->subordinate->number <=
12987                              tp->pdev->bus->number) &&
12988                             (bridge->subordinate->subordinate >=
12989                              tp->pdev->bus->number)) {
12990                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12991                                 pci_dev_put(bridge);
12992                                 break;
12993                         }
12994                 } while (bridge);
12995         }
12996
12997         /* Initialize misc host control in PCI block. */
12998         tp->misc_host_ctrl |= (misc_ctrl_reg &
12999                                MISC_HOST_CTRL_CHIPREV);
13000         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13001                                tp->misc_host_ctrl);
13002
13003         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13004             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13005             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13006                 tp->pdev_peer = tg3_find_peer(tp);
13007
13008         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13009             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13010             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13011                 tp->tg3_flags3 |= TG3_FLG3_5717_PLUS;
13012
13013         /* Intentionally exclude ASIC_REV_5906 */
13014         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13015             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13016             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13017             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13018             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13019             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13020             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13021                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13022
13023         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13024             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13025             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13026             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13027             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13028                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13029
13030         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13031             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13032                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13033
13034         /* 5700 B0 chips do not support checksumming correctly due
13035          * to hardware bugs.
13036          */
13037         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13038                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13039         else {
13040                 unsigned long features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_GRO;
13041
13042                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13043                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13044                         features |= NETIF_F_IPV6_CSUM;
13045                 tp->dev->features |= features;
13046                 vlan_features_add(tp->dev, features);
13047         }
13048
13049         /* Determine TSO capabilities */
13050         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13051                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13052         else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13053                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13054                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13055         else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13056                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13057                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13058                     tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13059                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13060         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13061                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13062                    tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13063                 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13064                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13065                         tp->fw_needed = FIRMWARE_TG3TSO5;
13066                 else
13067                         tp->fw_needed = FIRMWARE_TG3TSO;
13068         }
13069
13070         tp->irq_max = 1;
13071
13072         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13073                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13074                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13075                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13076                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13077                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13078                      tp->pdev_peer == tp->pdev))
13079                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13080
13081                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13082                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13083                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13084                 }
13085
13086                 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
13087                         tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13088                         tp->irq_max = TG3_IRQ_MAX_VECS;
13089                 }
13090         }
13091
13092         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13093             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13094             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13095                 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13096         else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13097                 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13098                 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13099         }
13100
13101         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13102                 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13103
13104         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13105             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13106             (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13107                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13108
13109         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13110                               &pci_state_reg);
13111
13112         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13113         if (tp->pcie_cap != 0) {
13114                 u16 lnkctl;
13115
13116                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13117
13118                 pcie_set_readrq(tp->pdev, 4096);
13119
13120                 pci_read_config_word(tp->pdev,
13121                                      tp->pcie_cap + PCI_EXP_LNKCTL,
13122                                      &lnkctl);
13123                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13124                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13125                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13126                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13127                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13128                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13129                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13130                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13131                 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13132                         tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13133                 }
13134         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13135                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13136         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13137                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13138                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13139                 if (!tp->pcix_cap) {
13140                         dev_err(&tp->pdev->dev,
13141                                 "Cannot find PCI-X capability, aborting\n");
13142                         return -EIO;
13143                 }
13144
13145                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13146                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13147         }
13148
13149         /* If we have an AMD 762 or VIA K8T800 chipset, write
13150          * reordering to the mailbox registers done by the host
13151          * controller can cause major troubles.  We read back from
13152          * every mailbox register write to force the writes to be
13153          * posted to the chip in order.
13154          */
13155         if (pci_dev_present(write_reorder_chipsets) &&
13156             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13157                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13158
13159         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13160                              &tp->pci_cacheline_sz);
13161         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13162                              &tp->pci_lat_timer);
13163         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13164             tp->pci_lat_timer < 64) {
13165                 tp->pci_lat_timer = 64;
13166                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13167                                       tp->pci_lat_timer);
13168         }
13169
13170         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13171                 /* 5700 BX chips need to have their TX producer index
13172                  * mailboxes written twice to workaround a bug.
13173                  */
13174                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13175
13176                 /* If we are in PCI-X mode, enable register write workaround.
13177                  *
13178                  * The workaround is to use indirect register accesses
13179                  * for all chip writes not to mailbox registers.
13180                  */
13181                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13182                         u32 pm_reg;
13183
13184                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13185
13186                         /* The chip can have it's power management PCI config
13187                          * space registers clobbered due to this bug.
13188                          * So explicitly force the chip into D0 here.
13189                          */
13190                         pci_read_config_dword(tp->pdev,
13191                                               tp->pm_cap + PCI_PM_CTRL,
13192                                               &pm_reg);
13193                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13194                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13195                         pci_write_config_dword(tp->pdev,
13196                                                tp->pm_cap + PCI_PM_CTRL,
13197                                                pm_reg);
13198
13199                         /* Also, force SERR#/PERR# in PCI command. */
13200                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13201                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13202                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13203                 }
13204         }
13205
13206         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13207                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13208         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13209                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13210
13211         /* Chip-specific fixup from Broadcom driver */
13212         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13213             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13214                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13215                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13216         }
13217
13218         /* Default fast path register access methods */
13219         tp->read32 = tg3_read32;
13220         tp->write32 = tg3_write32;
13221         tp->read32_mbox = tg3_read32;
13222         tp->write32_mbox = tg3_write32;
13223         tp->write32_tx_mbox = tg3_write32;
13224         tp->write32_rx_mbox = tg3_write32;
13225
13226         /* Various workaround register access methods */
13227         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13228                 tp->write32 = tg3_write_indirect_reg32;
13229         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13230                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13231                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13232                 /*
13233                  * Back to back register writes can cause problems on these
13234                  * chips, the workaround is to read back all reg writes
13235                  * except those to mailbox regs.
13236                  *
13237                  * See tg3_write_indirect_reg32().
13238                  */
13239                 tp->write32 = tg3_write_flush_reg32;
13240         }
13241
13242         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13243             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13244                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13245                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13246                         tp->write32_rx_mbox = tg3_write_flush_reg32;
13247         }
13248
13249         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13250                 tp->read32 = tg3_read_indirect_reg32;
13251                 tp->write32 = tg3_write_indirect_reg32;
13252                 tp->read32_mbox = tg3_read_indirect_mbox;
13253                 tp->write32_mbox = tg3_write_indirect_mbox;
13254                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13255                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13256
13257                 iounmap(tp->regs);
13258                 tp->regs = NULL;
13259
13260                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13261                 pci_cmd &= ~PCI_COMMAND_MEMORY;
13262                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13263         }
13264         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13265                 tp->read32_mbox = tg3_read32_mbox_5906;
13266                 tp->write32_mbox = tg3_write32_mbox_5906;
13267                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13268                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13269         }
13270
13271         if (tp->write32 == tg3_write_indirect_reg32 ||
13272             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13273              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13274               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13275                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13276
13277         /* Get eeprom hw config before calling tg3_set_power_state().
13278          * In particular, the TG3_FLG2_IS_NIC flag must be
13279          * determined before calling tg3_set_power_state() so that
13280          * we know whether or not to switch out of Vaux power.
13281          * When the flag is set, it means that GPIO1 is used for eeprom
13282          * write protect and also implies that it is a LOM where GPIOs
13283          * are not used to switch power.
13284          */
13285         tg3_get_eeprom_hw_cfg(tp);
13286
13287         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13288                 /* Allow reads and writes to the
13289                  * APE register and memory space.
13290                  */
13291                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13292                                  PCISTATE_ALLOW_APE_SHMEM_WR |
13293                                  PCISTATE_ALLOW_APE_PSPACE_WR;
13294                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13295                                        pci_state_reg);
13296         }
13297
13298         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13299             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13300             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13301             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13302             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13303                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13304
13305         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13306          * GPIO1 driven high will bring 5700's external PHY out of reset.
13307          * It is also used as eeprom write protect on LOMs.
13308          */
13309         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13310         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13311             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13312                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13313                                        GRC_LCLCTRL_GPIO_OUTPUT1);
13314         /* Unused GPIO3 must be driven as output on 5752 because there
13315          * are no pull-up resistors on unused GPIO pins.
13316          */
13317         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13318                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13319
13320         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13321             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13322             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13323                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13324
13325         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13326             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13327                 /* Turn off the debug UART. */
13328                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13329                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13330                         /* Keep VMain power. */
13331                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13332                                               GRC_LCLCTRL_GPIO_OUTPUT0;
13333         }
13334
13335         /* Force the chip into D0. */
13336         err = tg3_set_power_state(tp, PCI_D0);
13337         if (err) {
13338                 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
13339                 return err;
13340         }
13341
13342         /* Derive initial jumbo mode from MTU assigned in
13343          * ether_setup() via the alloc_etherdev() call
13344          */
13345         if (tp->dev->mtu > ETH_DATA_LEN &&
13346             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13347                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13348
13349         /* Determine WakeOnLan speed to use. */
13350         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13351             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13352             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13353             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13354                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13355         } else {
13356                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13357         }
13358
13359         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13360                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
13361
13362         /* A few boards don't want Ethernet@WireSpeed phy feature */
13363         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13364             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13365              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13366              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13367             (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
13368             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
13369                 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
13370
13371         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13372             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13373                 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
13374         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13375                 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
13376
13377         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13378             !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
13379             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13380             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13381             !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
13382                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13383                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13384                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13385                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13386                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13387                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13388                                 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
13389                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13390                                 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
13391                 } else
13392                         tp->phy_flags |= TG3_PHYFLG_BER_BUG;
13393         }
13394
13395         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13396             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13397                 tp->phy_otp = tg3_read_otp_phycfg(tp);
13398                 if (tp->phy_otp == 0)
13399                         tp->phy_otp = TG3_OTP_DEFAULT;
13400         }
13401
13402         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13403                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13404         else
13405                 tp->mi_mode = MAC_MI_MODE_BASE;
13406
13407         tp->coalesce_mode = 0;
13408         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13409             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13410                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13411
13412         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13413             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13414                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13415
13416         err = tg3_mdio_init(tp);
13417         if (err)
13418                 return err;
13419
13420         /* Initialize data/descriptor byte/word swapping. */
13421         val = tr32(GRC_MODE);
13422         val &= GRC_MODE_HOST_STACKUP;
13423         tw32(GRC_MODE, val | tp->grc_mode);
13424
13425         tg3_switch_clocks(tp);
13426
13427         /* Clear this out for sanity. */
13428         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13429
13430         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13431                               &pci_state_reg);
13432         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13433             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13434                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13435
13436                 if (chiprevid == CHIPREV_ID_5701_A0 ||
13437                     chiprevid == CHIPREV_ID_5701_B0 ||
13438                     chiprevid == CHIPREV_ID_5701_B2 ||
13439                     chiprevid == CHIPREV_ID_5701_B5) {
13440                         void __iomem *sram_base;
13441
13442                         /* Write some dummy words into the SRAM status block
13443                          * area, see if it reads back correctly.  If the return
13444                          * value is bad, force enable the PCIX workaround.
13445                          */
13446                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13447
13448                         writel(0x00000000, sram_base);
13449                         writel(0x00000000, sram_base + 4);
13450                         writel(0xffffffff, sram_base + 4);
13451                         if (readl(sram_base) != 0x00000000)
13452                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13453                 }
13454         }
13455
13456         udelay(50);
13457         tg3_nvram_init(tp);
13458
13459         grc_misc_cfg = tr32(GRC_MISC_CFG);
13460         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13461
13462         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13463             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13464              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13465                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13466
13467         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13468             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13469                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13470         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13471                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13472                                       HOSTCC_MODE_CLRTICK_TXBD);
13473
13474                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13475                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13476                                        tp->misc_host_ctrl);
13477         }
13478
13479         /* Preserve the APE MAC_MODE bits */
13480         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13481                 tp->mac_mode = tr32(MAC_MODE) |
13482                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13483         else
13484                 tp->mac_mode = TG3_DEF_MAC_MODE;
13485
13486         /* these are limited to 10/100 only */
13487         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13488              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13489             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13490              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13491              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13492               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13493               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13494             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13495              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13496               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13497               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13498             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13499             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13500             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
13501             (tp->phy_flags & TG3_PHYFLG_IS_FET))
13502                 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
13503
13504         err = tg3_phy_probe(tp);
13505         if (err) {
13506                 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
13507                 /* ... but do not return immediately ... */
13508                 tg3_mdio_fini(tp);
13509         }
13510
13511         tg3_read_vpd(tp);
13512         tg3_read_fw_ver(tp);
13513
13514         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
13515                 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
13516         } else {
13517                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13518                         tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
13519                 else
13520                         tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
13521         }
13522
13523         /* 5700 {AX,BX} chips have a broken status block link
13524          * change bit implementation, so we must use the
13525          * status register in those cases.
13526          */
13527         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13528                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13529         else
13530                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13531
13532         /* The led_ctrl is set during tg3_phy_probe, here we might
13533          * have to force the link status polling mechanism based
13534          * upon subsystem IDs.
13535          */
13536         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13537             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13538             !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
13539                 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
13540                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13541         }
13542
13543         /* For all SERDES we poll the MAC status register. */
13544         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
13545                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13546         else
13547                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13548
13549         tp->rx_offset = NET_IP_ALIGN + TG3_RX_HEADROOM;
13550         tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
13551         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13552             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
13553                 tp->rx_offset -= NET_IP_ALIGN;
13554 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
13555                 tp->rx_copy_thresh = ~(u16)0;
13556 #endif
13557         }
13558
13559         tp->rx_std_max_post = TG3_RX_RING_SIZE;
13560
13561         /* Increment the rx prod index on the rx std ring by at most
13562          * 8 for these chips to workaround hw errata.
13563          */
13564         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13565             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13566             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13567                 tp->rx_std_max_post = 8;
13568
13569         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13570                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13571                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
13572
13573         return err;
13574 }
13575
13576 #ifdef CONFIG_SPARC
13577 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13578 {
13579         struct net_device *dev = tp->dev;
13580         struct pci_dev *pdev = tp->pdev;
13581         struct device_node *dp = pci_device_to_OF_node(pdev);
13582         const unsigned char *addr;
13583         int len;
13584
13585         addr = of_get_property(dp, "local-mac-address", &len);
13586         if (addr && len == 6) {
13587                 memcpy(dev->dev_addr, addr, 6);
13588                 memcpy(dev->perm_addr, dev->dev_addr, 6);
13589                 return 0;
13590         }
13591         return -ENODEV;
13592 }
13593
13594 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13595 {
13596         struct net_device *dev = tp->dev;
13597
13598         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13599         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13600         return 0;
13601 }
13602 #endif
13603
13604 static int __devinit tg3_get_device_address(struct tg3 *tp)
13605 {
13606         struct net_device *dev = tp->dev;
13607         u32 hi, lo, mac_offset;
13608         int addr_ok = 0;
13609
13610 #ifdef CONFIG_SPARC
13611         if (!tg3_get_macaddr_sparc(tp))
13612                 return 0;
13613 #endif
13614
13615         mac_offset = 0x7c;
13616         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13617             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13618                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13619                         mac_offset = 0xcc;
13620                 if (tg3_nvram_lock(tp))
13621                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13622                 else
13623                         tg3_nvram_unlock(tp);
13624         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13625                    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
13626                 if (PCI_FUNC(tp->pdev->devfn) & 1)
13627                         mac_offset = 0xcc;
13628                 if (PCI_FUNC(tp->pdev->devfn) > 1)
13629                         mac_offset += 0x18c;
13630         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13631                 mac_offset = 0x10;
13632
13633         /* First try to get it from MAC address mailbox. */
13634         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13635         if ((hi >> 16) == 0x484b) {
13636                 dev->dev_addr[0] = (hi >>  8) & 0xff;
13637                 dev->dev_addr[1] = (hi >>  0) & 0xff;
13638
13639                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13640                 dev->dev_addr[2] = (lo >> 24) & 0xff;
13641                 dev->dev_addr[3] = (lo >> 16) & 0xff;
13642                 dev->dev_addr[4] = (lo >>  8) & 0xff;
13643                 dev->dev_addr[5] = (lo >>  0) & 0xff;
13644
13645                 /* Some old bootcode may report a 0 MAC address in SRAM */
13646                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13647         }
13648         if (!addr_ok) {
13649                 /* Next, try NVRAM. */
13650                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13651                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13652                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13653                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13654                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13655                 }
13656                 /* Finally just fetch it out of the MAC control regs. */
13657                 else {
13658                         hi = tr32(MAC_ADDR_0_HIGH);
13659                         lo = tr32(MAC_ADDR_0_LOW);
13660
13661                         dev->dev_addr[5] = lo & 0xff;
13662                         dev->dev_addr[4] = (lo >> 8) & 0xff;
13663                         dev->dev_addr[3] = (lo >> 16) & 0xff;
13664                         dev->dev_addr[2] = (lo >> 24) & 0xff;
13665                         dev->dev_addr[1] = hi & 0xff;
13666                         dev->dev_addr[0] = (hi >> 8) & 0xff;
13667                 }
13668         }
13669
13670         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13671 #ifdef CONFIG_SPARC
13672                 if (!tg3_get_default_macaddr_sparc(tp))
13673                         return 0;
13674 #endif
13675                 return -EINVAL;
13676         }
13677         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13678         return 0;
13679 }
13680
13681 #define BOUNDARY_SINGLE_CACHELINE       1
13682 #define BOUNDARY_MULTI_CACHELINE        2
13683
13684 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13685 {
13686         int cacheline_size;
13687         u8 byte;
13688         int goal;
13689
13690         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13691         if (byte == 0)
13692                 cacheline_size = 1024;
13693         else
13694                 cacheline_size = (int) byte * 4;
13695
13696         /* On 5703 and later chips, the boundary bits have no
13697          * effect.
13698          */
13699         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13700             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13701             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13702                 goto out;
13703
13704 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13705         goal = BOUNDARY_MULTI_CACHELINE;
13706 #else
13707 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13708         goal = BOUNDARY_SINGLE_CACHELINE;
13709 #else
13710         goal = 0;
13711 #endif
13712 #endif
13713
13714         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
13715                 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13716                 goto out;
13717         }
13718
13719         if (!goal)
13720                 goto out;
13721
13722         /* PCI controllers on most RISC systems tend to disconnect
13723          * when a device tries to burst across a cache-line boundary.
13724          * Therefore, letting tg3 do so just wastes PCI bandwidth.
13725          *
13726          * Unfortunately, for PCI-E there are only limited
13727          * write-side controls for this, and thus for reads
13728          * we will still get the disconnects.  We'll also waste
13729          * these PCI cycles for both read and write for chips
13730          * other than 5700 and 5701 which do not implement the
13731          * boundary bits.
13732          */
13733         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13734             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13735                 switch (cacheline_size) {
13736                 case 16:
13737                 case 32:
13738                 case 64:
13739                 case 128:
13740                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13741                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13742                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13743                         } else {
13744                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13745                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13746                         }
13747                         break;
13748
13749                 case 256:
13750                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13751                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13752                         break;
13753
13754                 default:
13755                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13756                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13757                         break;
13758                 }
13759         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13760                 switch (cacheline_size) {
13761                 case 16:
13762                 case 32:
13763                 case 64:
13764                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13765                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13766                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13767                                 break;
13768                         }
13769                         /* fallthrough */
13770                 case 128:
13771                 default:
13772                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13773                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13774                         break;
13775                 }
13776         } else {
13777                 switch (cacheline_size) {
13778                 case 16:
13779                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13780                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13781                                         DMA_RWCTRL_WRITE_BNDRY_16);
13782                                 break;
13783                         }
13784                         /* fallthrough */
13785                 case 32:
13786                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13787                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13788                                         DMA_RWCTRL_WRITE_BNDRY_32);
13789                                 break;
13790                         }
13791                         /* fallthrough */
13792                 case 64:
13793                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13794                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13795                                         DMA_RWCTRL_WRITE_BNDRY_64);
13796                                 break;
13797                         }
13798                         /* fallthrough */
13799                 case 128:
13800                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13801                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13802                                         DMA_RWCTRL_WRITE_BNDRY_128);
13803                                 break;
13804                         }
13805                         /* fallthrough */
13806                 case 256:
13807                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
13808                                 DMA_RWCTRL_WRITE_BNDRY_256);
13809                         break;
13810                 case 512:
13811                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
13812                                 DMA_RWCTRL_WRITE_BNDRY_512);
13813                         break;
13814                 case 1024:
13815                 default:
13816                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13817                                 DMA_RWCTRL_WRITE_BNDRY_1024);
13818                         break;
13819                 }
13820         }
13821
13822 out:
13823         return val;
13824 }
13825
13826 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13827 {
13828         struct tg3_internal_buffer_desc test_desc;
13829         u32 sram_dma_descs;
13830         int i, ret;
13831
13832         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13833
13834         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13835         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13836         tw32(RDMAC_STATUS, 0);
13837         tw32(WDMAC_STATUS, 0);
13838
13839         tw32(BUFMGR_MODE, 0);
13840         tw32(FTQ_RESET, 0);
13841
13842         test_desc.addr_hi = ((u64) buf_dma) >> 32;
13843         test_desc.addr_lo = buf_dma & 0xffffffff;
13844         test_desc.nic_mbuf = 0x00002100;
13845         test_desc.len = size;
13846
13847         /*
13848          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13849          * the *second* time the tg3 driver was getting loaded after an
13850          * initial scan.
13851          *
13852          * Broadcom tells me:
13853          *   ...the DMA engine is connected to the GRC block and a DMA
13854          *   reset may affect the GRC block in some unpredictable way...
13855          *   The behavior of resets to individual blocks has not been tested.
13856          *
13857          * Broadcom noted the GRC reset will also reset all sub-components.
13858          */
13859         if (to_device) {
13860                 test_desc.cqid_sqid = (13 << 8) | 2;
13861
13862                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13863                 udelay(40);
13864         } else {
13865                 test_desc.cqid_sqid = (16 << 8) | 7;
13866
13867                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13868                 udelay(40);
13869         }
13870         test_desc.flags = 0x00000005;
13871
13872         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13873                 u32 val;
13874
13875                 val = *(((u32 *)&test_desc) + i);
13876                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13877                                        sram_dma_descs + (i * sizeof(u32)));
13878                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13879         }
13880         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13881
13882         if (to_device)
13883                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13884         else
13885                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13886
13887         ret = -ENODEV;
13888         for (i = 0; i < 40; i++) {
13889                 u32 val;
13890
13891                 if (to_device)
13892                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13893                 else
13894                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13895                 if ((val & 0xffff) == sram_dma_descs) {
13896                         ret = 0;
13897                         break;
13898                 }
13899
13900                 udelay(100);
13901         }
13902
13903         return ret;
13904 }
13905
13906 #define TEST_BUFFER_SIZE        0x2000
13907
13908 static int __devinit tg3_test_dma(struct tg3 *tp)
13909 {
13910         dma_addr_t buf_dma;
13911         u32 *buf, saved_dma_rwctrl;
13912         int ret = 0;
13913
13914         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13915         if (!buf) {
13916                 ret = -ENOMEM;
13917                 goto out_nofree;
13918         }
13919
13920         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13921                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13922
13923         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13924
13925         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13926                 goto out;
13927
13928         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13929                 /* DMA read watermark not used on PCIE */
13930                 tp->dma_rwctrl |= 0x00180000;
13931         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
13932                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13933                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
13934                         tp->dma_rwctrl |= 0x003f0000;
13935                 else
13936                         tp->dma_rwctrl |= 0x003f000f;
13937         } else {
13938                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13939                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13940                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
13941                         u32 read_water = 0x7;
13942
13943                         /* If the 5704 is behind the EPB bridge, we can
13944                          * do the less restrictive ONE_DMA workaround for
13945                          * better performance.
13946                          */
13947                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13948                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13949                                 tp->dma_rwctrl |= 0x8000;
13950                         else if (ccval == 0x6 || ccval == 0x7)
13951                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13952
13953                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13954                                 read_water = 4;
13955                         /* Set bit 23 to enable PCIX hw bug fix */
13956                         tp->dma_rwctrl |=
13957                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13958                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13959                                 (1 << 23);
13960                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13961                         /* 5780 always in PCIX mode */
13962                         tp->dma_rwctrl |= 0x00144000;
13963                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13964                         /* 5714 always in PCIX mode */
13965                         tp->dma_rwctrl |= 0x00148000;
13966                 } else {
13967                         tp->dma_rwctrl |= 0x001b000f;
13968                 }
13969         }
13970
13971         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13972             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13973                 tp->dma_rwctrl &= 0xfffffff0;
13974
13975         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13976             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13977                 /* Remove this if it causes problems for some boards. */
13978                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13979
13980                 /* On 5700/5701 chips, we need to set this bit.
13981                  * Otherwise the chip will issue cacheline transactions
13982                  * to streamable DMA memory with not all the byte
13983                  * enables turned on.  This is an error on several
13984                  * RISC PCI controllers, in particular sparc64.
13985                  *
13986                  * On 5703/5704 chips, this bit has been reassigned
13987                  * a different meaning.  In particular, it is used
13988                  * on those chips to enable a PCI-X workaround.
13989                  */
13990                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13991         }
13992
13993         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13994
13995 #if 0
13996         /* Unneeded, already done by tg3_get_invariants.  */
13997         tg3_switch_clocks(tp);
13998 #endif
13999
14000         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14001             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14002                 goto out;
14003
14004         /* It is best to perform DMA test with maximum write burst size
14005          * to expose the 5700/5701 write DMA bug.
14006          */
14007         saved_dma_rwctrl = tp->dma_rwctrl;
14008         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14009         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14010
14011         while (1) {
14012                 u32 *p = buf, i;
14013
14014                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14015                         p[i] = i;
14016
14017                 /* Send the buffer to the chip. */
14018                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14019                 if (ret) {
14020                         dev_err(&tp->pdev->dev,
14021                                 "%s: Buffer write failed. err = %d\n",
14022                                 __func__, ret);
14023                         break;
14024                 }
14025
14026 #if 0
14027                 /* validate data reached card RAM correctly. */
14028                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14029                         u32 val;
14030                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
14031                         if (le32_to_cpu(val) != p[i]) {
14032                                 dev_err(&tp->pdev->dev,
14033                                         "%s: Buffer corrupted on device! "
14034                                         "(%d != %d)\n", __func__, val, i);
14035                                 /* ret = -ENODEV here? */
14036                         }
14037                         p[i] = 0;
14038                 }
14039 #endif
14040                 /* Now read it back. */
14041                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14042                 if (ret) {
14043                         dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
14044                                 "err = %d\n", __func__, ret);
14045                         break;
14046                 }
14047
14048                 /* Verify it. */
14049                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14050                         if (p[i] == i)
14051                                 continue;
14052
14053                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14054                             DMA_RWCTRL_WRITE_BNDRY_16) {
14055                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14056                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14057                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14058                                 break;
14059                         } else {
14060                                 dev_err(&tp->pdev->dev,
14061                                         "%s: Buffer corrupted on read back! "
14062                                         "(%d != %d)\n", __func__, p[i], i);
14063                                 ret = -ENODEV;
14064                                 goto out;
14065                         }
14066                 }
14067
14068                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14069                         /* Success. */
14070                         ret = 0;
14071                         break;
14072                 }
14073         }
14074         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14075             DMA_RWCTRL_WRITE_BNDRY_16) {
14076                 static struct pci_device_id dma_wait_state_chipsets[] = {
14077                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14078                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14079                         { },
14080                 };
14081
14082                 /* DMA test passed without adjusting DMA boundary,
14083                  * now look for chipsets that are known to expose the
14084                  * DMA bug without failing the test.
14085                  */
14086                 if (pci_dev_present(dma_wait_state_chipsets)) {
14087                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14088                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14089                 } else {
14090                         /* Safe to use the calculated DMA boundary. */
14091                         tp->dma_rwctrl = saved_dma_rwctrl;
14092                 }
14093
14094                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14095         }
14096
14097 out:
14098         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14099 out_nofree:
14100         return ret;
14101 }
14102
14103 static void __devinit tg3_init_link_config(struct tg3 *tp)
14104 {
14105         tp->link_config.advertising =
14106                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14107                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14108                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14109                  ADVERTISED_Autoneg | ADVERTISED_MII);
14110         tp->link_config.speed = SPEED_INVALID;
14111         tp->link_config.duplex = DUPLEX_INVALID;
14112         tp->link_config.autoneg = AUTONEG_ENABLE;
14113         tp->link_config.active_speed = SPEED_INVALID;
14114         tp->link_config.active_duplex = DUPLEX_INVALID;
14115         tp->link_config.orig_speed = SPEED_INVALID;
14116         tp->link_config.orig_duplex = DUPLEX_INVALID;
14117         tp->link_config.orig_autoneg = AUTONEG_INVALID;
14118 }
14119
14120 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14121 {
14122         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
14123                 tp->bufmgr_config.mbuf_read_dma_low_water =
14124                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14125                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14126                         DEFAULT_MB_MACRX_LOW_WATER_57765;
14127                 tp->bufmgr_config.mbuf_high_water =
14128                         DEFAULT_MB_HIGH_WATER_57765;
14129
14130                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14131                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14132                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14133                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14134                 tp->bufmgr_config.mbuf_high_water_jumbo =
14135                         DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14136         } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14137                 tp->bufmgr_config.mbuf_read_dma_low_water =
14138                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14139                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14140                         DEFAULT_MB_MACRX_LOW_WATER_5705;
14141                 tp->bufmgr_config.mbuf_high_water =
14142                         DEFAULT_MB_HIGH_WATER_5705;
14143                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14144                         tp->bufmgr_config.mbuf_mac_rx_low_water =
14145                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
14146                         tp->bufmgr_config.mbuf_high_water =
14147                                 DEFAULT_MB_HIGH_WATER_5906;
14148                 }
14149
14150                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14151                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14152                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14153                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14154                 tp->bufmgr_config.mbuf_high_water_jumbo =
14155                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14156         } else {
14157                 tp->bufmgr_config.mbuf_read_dma_low_water =
14158                         DEFAULT_MB_RDMA_LOW_WATER;
14159                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14160                         DEFAULT_MB_MACRX_LOW_WATER;
14161                 tp->bufmgr_config.mbuf_high_water =
14162                         DEFAULT_MB_HIGH_WATER;
14163
14164                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14165                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14166                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14167                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14168                 tp->bufmgr_config.mbuf_high_water_jumbo =
14169                         DEFAULT_MB_HIGH_WATER_JUMBO;
14170         }
14171
14172         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14173         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14174 }
14175
14176 static char * __devinit tg3_phy_string(struct tg3 *tp)
14177 {
14178         switch (tp->phy_id & TG3_PHY_ID_MASK) {
14179         case TG3_PHY_ID_BCM5400:        return "5400";
14180         case TG3_PHY_ID_BCM5401:        return "5401";
14181         case TG3_PHY_ID_BCM5411:        return "5411";
14182         case TG3_PHY_ID_BCM5701:        return "5701";
14183         case TG3_PHY_ID_BCM5703:        return "5703";
14184         case TG3_PHY_ID_BCM5704:        return "5704";
14185         case TG3_PHY_ID_BCM5705:        return "5705";
14186         case TG3_PHY_ID_BCM5750:        return "5750";
14187         case TG3_PHY_ID_BCM5752:        return "5752";
14188         case TG3_PHY_ID_BCM5714:        return "5714";
14189         case TG3_PHY_ID_BCM5780:        return "5780";
14190         case TG3_PHY_ID_BCM5755:        return "5755";
14191         case TG3_PHY_ID_BCM5787:        return "5787";
14192         case TG3_PHY_ID_BCM5784:        return "5784";
14193         case TG3_PHY_ID_BCM5756:        return "5722/5756";
14194         case TG3_PHY_ID_BCM5906:        return "5906";
14195         case TG3_PHY_ID_BCM5761:        return "5761";
14196         case TG3_PHY_ID_BCM5718C:       return "5718C";
14197         case TG3_PHY_ID_BCM5718S:       return "5718S";
14198         case TG3_PHY_ID_BCM57765:       return "57765";
14199         case TG3_PHY_ID_BCM5719C:       return "5719C";
14200         case TG3_PHY_ID_BCM8002:        return "8002/serdes";
14201         case 0:                 return "serdes";
14202         default:                return "unknown";
14203         }
14204 }
14205
14206 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14207 {
14208         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14209                 strcpy(str, "PCI Express");
14210                 return str;
14211         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14212                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14213
14214                 strcpy(str, "PCIX:");
14215
14216                 if ((clock_ctrl == 7) ||
14217                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14218                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14219                         strcat(str, "133MHz");
14220                 else if (clock_ctrl == 0)
14221                         strcat(str, "33MHz");
14222                 else if (clock_ctrl == 2)
14223                         strcat(str, "50MHz");
14224                 else if (clock_ctrl == 4)
14225                         strcat(str, "66MHz");
14226                 else if (clock_ctrl == 6)
14227                         strcat(str, "100MHz");
14228         } else {
14229                 strcpy(str, "PCI:");
14230                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14231                         strcat(str, "66MHz");
14232                 else
14233                         strcat(str, "33MHz");
14234         }
14235         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14236                 strcat(str, ":32-bit");
14237         else
14238                 strcat(str, ":64-bit");
14239         return str;
14240 }
14241
14242 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14243 {
14244         struct pci_dev *peer;
14245         unsigned int func, devnr = tp->pdev->devfn & ~7;
14246
14247         for (func = 0; func < 8; func++) {
14248                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14249                 if (peer && peer != tp->pdev)
14250                         break;
14251                 pci_dev_put(peer);
14252         }
14253         /* 5704 can be configured in single-port mode, set peer to
14254          * tp->pdev in that case.
14255          */
14256         if (!peer) {
14257                 peer = tp->pdev;
14258                 return peer;
14259         }
14260
14261         /*
14262          * We don't need to keep the refcount elevated; there's no way
14263          * to remove one half of this device without removing the other
14264          */
14265         pci_dev_put(peer);
14266
14267         return peer;
14268 }
14269
14270 static void __devinit tg3_init_coal(struct tg3 *tp)
14271 {
14272         struct ethtool_coalesce *ec = &tp->coal;
14273
14274         memset(ec, 0, sizeof(*ec));
14275         ec->cmd = ETHTOOL_GCOALESCE;
14276         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14277         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14278         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14279         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14280         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14281         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14282         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14283         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14284         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14285
14286         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14287                                  HOSTCC_MODE_CLRTICK_TXBD)) {
14288                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14289                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14290                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14291                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14292         }
14293
14294         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14295                 ec->rx_coalesce_usecs_irq = 0;
14296                 ec->tx_coalesce_usecs_irq = 0;
14297                 ec->stats_block_coalesce_usecs = 0;
14298         }
14299 }
14300
14301 static const struct net_device_ops tg3_netdev_ops = {
14302         .ndo_open               = tg3_open,
14303         .ndo_stop               = tg3_close,
14304         .ndo_start_xmit         = tg3_start_xmit,
14305         .ndo_get_stats64        = tg3_get_stats64,
14306         .ndo_validate_addr      = eth_validate_addr,
14307         .ndo_set_multicast_list = tg3_set_rx_mode,
14308         .ndo_set_mac_address    = tg3_set_mac_addr,
14309         .ndo_do_ioctl           = tg3_ioctl,
14310         .ndo_tx_timeout         = tg3_tx_timeout,
14311         .ndo_change_mtu         = tg3_change_mtu,
14312 #if TG3_VLAN_TAG_USED
14313         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14314 #endif
14315 #ifdef CONFIG_NET_POLL_CONTROLLER
14316         .ndo_poll_controller    = tg3_poll_controller,
14317 #endif
14318 };
14319
14320 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14321         .ndo_open               = tg3_open,
14322         .ndo_stop               = tg3_close,
14323         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
14324         .ndo_get_stats64        = tg3_get_stats64,
14325         .ndo_validate_addr      = eth_validate_addr,
14326         .ndo_set_multicast_list = tg3_set_rx_mode,
14327         .ndo_set_mac_address    = tg3_set_mac_addr,
14328         .ndo_do_ioctl           = tg3_ioctl,
14329         .ndo_tx_timeout         = tg3_tx_timeout,
14330         .ndo_change_mtu         = tg3_change_mtu,
14331 #if TG3_VLAN_TAG_USED
14332         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14333 #endif
14334 #ifdef CONFIG_NET_POLL_CONTROLLER
14335         .ndo_poll_controller    = tg3_poll_controller,
14336 #endif
14337 };
14338
14339 static int __devinit tg3_init_one(struct pci_dev *pdev,
14340                                   const struct pci_device_id *ent)
14341 {
14342         struct net_device *dev;
14343         struct tg3 *tp;
14344         int i, err, pm_cap;
14345         u32 sndmbx, rcvmbx, intmbx;
14346         char str[40];
14347         u64 dma_mask, persist_dma_mask;
14348
14349         printk_once(KERN_INFO "%s\n", version);
14350
14351         err = pci_enable_device(pdev);
14352         if (err) {
14353                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
14354                 return err;
14355         }
14356
14357         err = pci_request_regions(pdev, DRV_MODULE_NAME);
14358         if (err) {
14359                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
14360                 goto err_out_disable_pdev;
14361         }
14362
14363         pci_set_master(pdev);
14364
14365         /* Find power-management capability. */
14366         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14367         if (pm_cap == 0) {
14368                 dev_err(&pdev->dev,
14369                         "Cannot find Power Management capability, aborting\n");
14370                 err = -EIO;
14371                 goto err_out_free_res;
14372         }
14373
14374         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14375         if (!dev) {
14376                 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
14377                 err = -ENOMEM;
14378                 goto err_out_free_res;
14379         }
14380
14381         SET_NETDEV_DEV(dev, &pdev->dev);
14382
14383 #if TG3_VLAN_TAG_USED
14384         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14385 #endif
14386
14387         tp = netdev_priv(dev);
14388         tp->pdev = pdev;
14389         tp->dev = dev;
14390         tp->pm_cap = pm_cap;
14391         tp->rx_mode = TG3_DEF_RX_MODE;
14392         tp->tx_mode = TG3_DEF_TX_MODE;
14393
14394         if (tg3_debug > 0)
14395                 tp->msg_enable = tg3_debug;
14396         else
14397                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14398
14399         /* The word/byte swap controls here control register access byte
14400          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
14401          * setting below.
14402          */
14403         tp->misc_host_ctrl =
14404                 MISC_HOST_CTRL_MASK_PCI_INT |
14405                 MISC_HOST_CTRL_WORD_SWAP |
14406                 MISC_HOST_CTRL_INDIR_ACCESS |
14407                 MISC_HOST_CTRL_PCISTATE_RW;
14408
14409         /* The NONFRM (non-frame) byte/word swap controls take effect
14410          * on descriptor entries, anything which isn't packet data.
14411          *
14412          * The StrongARM chips on the board (one for tx, one for rx)
14413          * are running in big-endian mode.
14414          */
14415         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14416                         GRC_MODE_WSWAP_NONFRM_DATA);
14417 #ifdef __BIG_ENDIAN
14418         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14419 #endif
14420         spin_lock_init(&tp->lock);
14421         spin_lock_init(&tp->indirect_lock);
14422         INIT_WORK(&tp->reset_task, tg3_reset_task);
14423
14424         tp->regs = pci_ioremap_bar(pdev, BAR_0);
14425         if (!tp->regs) {
14426                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
14427                 err = -ENOMEM;
14428                 goto err_out_free_dev;
14429         }
14430
14431         tg3_init_link_config(tp);
14432
14433         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14434         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14435
14436         dev->ethtool_ops = &tg3_ethtool_ops;
14437         dev->watchdog_timeo = TG3_TX_TIMEOUT;
14438         dev->irq = pdev->irq;
14439
14440         err = tg3_get_invariants(tp);
14441         if (err) {
14442                 dev_err(&pdev->dev,
14443                         "Problem fetching invariants of chip, aborting\n");
14444                 goto err_out_iounmap;
14445         }
14446
14447         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14448             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
14449             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
14450                 dev->netdev_ops = &tg3_netdev_ops;
14451         else
14452                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14453
14454
14455         /* The EPB bridge inside 5714, 5715, and 5780 and any
14456          * device behind the EPB cannot support DMA addresses > 40-bit.
14457          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14458          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14459          * do DMA address check in tg3_start_xmit().
14460          */
14461         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14462                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14463         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14464                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14465 #ifdef CONFIG_HIGHMEM
14466                 dma_mask = DMA_BIT_MASK(64);
14467 #endif
14468         } else
14469                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14470
14471         /* Configure DMA attributes. */
14472         if (dma_mask > DMA_BIT_MASK(32)) {
14473                 err = pci_set_dma_mask(pdev, dma_mask);
14474                 if (!err) {
14475                         dev->features |= NETIF_F_HIGHDMA;
14476                         err = pci_set_consistent_dma_mask(pdev,
14477                                                           persist_dma_mask);
14478                         if (err < 0) {
14479                                 dev_err(&pdev->dev, "Unable to obtain 64 bit "
14480                                         "DMA for consistent allocations\n");
14481                                 goto err_out_iounmap;
14482                         }
14483                 }
14484         }
14485         if (err || dma_mask == DMA_BIT_MASK(32)) {
14486                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14487                 if (err) {
14488                         dev_err(&pdev->dev,
14489                                 "No usable DMA configuration, aborting\n");
14490                         goto err_out_iounmap;
14491                 }
14492         }
14493
14494         tg3_init_bufmgr_config(tp);
14495
14496         /* Selectively allow TSO based on operating conditions */
14497         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14498             (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14499                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14500         else {
14501                 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14502                 tp->fw_needed = NULL;
14503         }
14504
14505         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14506                 tp->fw_needed = FIRMWARE_TG3;
14507
14508         /* TSO is on by default on chips that support hardware TSO.
14509          * Firmware TSO on older chips gives lower performance, so it
14510          * is off by default, but can be enabled using ethtool.
14511          */
14512         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14513             (dev->features & NETIF_F_IP_CSUM)) {
14514                 dev->features |= NETIF_F_TSO;
14515                 vlan_features_add(dev, NETIF_F_TSO);
14516         }
14517         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14518             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14519                 if (dev->features & NETIF_F_IPV6_CSUM) {
14520                         dev->features |= NETIF_F_TSO6;
14521                         vlan_features_add(dev, NETIF_F_TSO6);
14522                 }
14523                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14524                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14525                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14526                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14527                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14528                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
14529                         dev->features |= NETIF_F_TSO_ECN;
14530                         vlan_features_add(dev, NETIF_F_TSO_ECN);
14531                 }
14532         }
14533
14534         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14535             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14536             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14537                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14538                 tp->rx_pending = 63;
14539         }
14540
14541         err = tg3_get_device_address(tp);
14542         if (err) {
14543                 dev_err(&pdev->dev,
14544                         "Could not obtain valid ethernet address, aborting\n");
14545                 goto err_out_iounmap;
14546         }
14547
14548         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14549                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14550                 if (!tp->aperegs) {
14551                         dev_err(&pdev->dev,
14552                                 "Cannot map APE registers, aborting\n");
14553                         err = -ENOMEM;
14554                         goto err_out_iounmap;
14555                 }
14556
14557                 tg3_ape_lock_init(tp);
14558
14559                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14560                         tg3_read_dash_ver(tp);
14561         }
14562
14563         /*
14564          * Reset chip in case UNDI or EFI driver did not shutdown
14565          * DMA self test will enable WDMAC and we'll see (spurious)
14566          * pending DMA on the PCI bus at that point.
14567          */
14568         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14569             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14570                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14571                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14572         }
14573
14574         err = tg3_test_dma(tp);
14575         if (err) {
14576                 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
14577                 goto err_out_apeunmap;
14578         }
14579
14580         /* flow control autonegotiation is default behavior */
14581         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14582         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14583
14584         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14585         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14586         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14587         for (i = 0; i < tp->irq_max; i++) {
14588                 struct tg3_napi *tnapi = &tp->napi[i];
14589
14590                 tnapi->tp = tp;
14591                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14592
14593                 tnapi->int_mbox = intmbx;
14594                 if (i < 4)
14595                         intmbx += 0x8;
14596                 else
14597                         intmbx += 0x4;
14598
14599                 tnapi->consmbox = rcvmbx;
14600                 tnapi->prodmbox = sndmbx;
14601
14602                 if (i) {
14603                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14604                         netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14605                 } else {
14606                         tnapi->coal_now = HOSTCC_MODE_NOW;
14607                         netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14608                 }
14609
14610                 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14611                         break;
14612
14613                 /*
14614                  * If we support MSIX, we'll be using RSS.  If we're using
14615                  * RSS, the first vector only handles link interrupts and the
14616                  * remaining vectors handle rx and tx interrupts.  Reuse the
14617                  * mailbox values for the next iteration.  The values we setup
14618                  * above are still useful for the single vectored mode.
14619                  */
14620                 if (!i)
14621                         continue;
14622
14623                 rcvmbx += 0x8;
14624
14625                 if (sndmbx & 0x4)
14626                         sndmbx -= 0x4;
14627                 else
14628                         sndmbx += 0xc;
14629         }
14630
14631         tg3_init_coal(tp);
14632
14633         pci_set_drvdata(pdev, dev);
14634
14635         err = register_netdev(dev);
14636         if (err) {
14637                 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
14638                 goto err_out_apeunmap;
14639         }
14640
14641         netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14642                     tp->board_part_number,
14643                     tp->pci_chip_rev_id,
14644                     tg3_bus_string(tp, str),
14645                     dev->dev_addr);
14646
14647         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
14648                 struct phy_device *phydev;
14649                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14650                 netdev_info(dev,
14651                             "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14652                             phydev->drv->name, dev_name(&phydev->dev));
14653         } else {
14654                 char *ethtype;
14655
14656                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
14657                         ethtype = "10/100Base-TX";
14658                 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
14659                         ethtype = "1000Base-SX";
14660                 else
14661                         ethtype = "10/100/1000Base-T";
14662
14663                 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
14664                             "(WireSpeed[%d])\n", tg3_phy_string(tp), ethtype,
14665                           (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0);
14666         }
14667
14668         netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14669                     (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14670                     (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14671                     (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
14672                     (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14673                     (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14674         netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14675                     tp->dma_rwctrl,
14676                     pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
14677                     ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
14678
14679         return 0;
14680
14681 err_out_apeunmap:
14682         if (tp->aperegs) {
14683                 iounmap(tp->aperegs);
14684                 tp->aperegs = NULL;
14685         }
14686
14687 err_out_iounmap:
14688         if (tp->regs) {
14689                 iounmap(tp->regs);
14690                 tp->regs = NULL;
14691         }
14692
14693 err_out_free_dev:
14694         free_netdev(dev);
14695
14696 err_out_free_res:
14697         pci_release_regions(pdev);
14698
14699 err_out_disable_pdev:
14700         pci_disable_device(pdev);
14701         pci_set_drvdata(pdev, NULL);
14702         return err;
14703 }
14704
14705 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14706 {
14707         struct net_device *dev = pci_get_drvdata(pdev);
14708
14709         if (dev) {
14710                 struct tg3 *tp = netdev_priv(dev);
14711
14712                 if (tp->fw)
14713                         release_firmware(tp->fw);
14714
14715                 flush_scheduled_work();
14716
14717                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14718                         tg3_phy_fini(tp);
14719                         tg3_mdio_fini(tp);
14720                 }
14721
14722                 unregister_netdev(dev);
14723                 if (tp->aperegs) {
14724                         iounmap(tp->aperegs);
14725                         tp->aperegs = NULL;
14726                 }
14727                 if (tp->regs) {
14728                         iounmap(tp->regs);
14729                         tp->regs = NULL;
14730                 }
14731                 free_netdev(dev);
14732                 pci_release_regions(pdev);
14733                 pci_disable_device(pdev);
14734                 pci_set_drvdata(pdev, NULL);
14735         }
14736 }
14737
14738 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14739 {
14740         struct net_device *dev = pci_get_drvdata(pdev);
14741         struct tg3 *tp = netdev_priv(dev);
14742         pci_power_t target_state;
14743         int err;
14744
14745         /* PCI register 4 needs to be saved whether netif_running() or not.
14746          * MSI address and data need to be saved if using MSI and
14747          * netif_running().
14748          */
14749         pci_save_state(pdev);
14750
14751         if (!netif_running(dev))
14752                 return 0;
14753
14754         flush_scheduled_work();
14755         tg3_phy_stop(tp);
14756         tg3_netif_stop(tp);
14757
14758         del_timer_sync(&tp->timer);
14759
14760         tg3_full_lock(tp, 1);
14761         tg3_disable_ints(tp);
14762         tg3_full_unlock(tp);
14763
14764         netif_device_detach(dev);
14765
14766         tg3_full_lock(tp, 0);
14767         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14768         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14769         tg3_full_unlock(tp);
14770
14771         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14772
14773         err = tg3_set_power_state(tp, target_state);
14774         if (err) {
14775                 int err2;
14776
14777                 tg3_full_lock(tp, 0);
14778
14779                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14780                 err2 = tg3_restart_hw(tp, 1);
14781                 if (err2)
14782                         goto out;
14783
14784                 tp->timer.expires = jiffies + tp->timer_offset;
14785                 add_timer(&tp->timer);
14786
14787                 netif_device_attach(dev);
14788                 tg3_netif_start(tp);
14789
14790 out:
14791                 tg3_full_unlock(tp);
14792
14793                 if (!err2)
14794                         tg3_phy_start(tp);
14795         }
14796
14797         return err;
14798 }
14799
14800 static int tg3_resume(struct pci_dev *pdev)
14801 {
14802         struct net_device *dev = pci_get_drvdata(pdev);
14803         struct tg3 *tp = netdev_priv(dev);
14804         int err;
14805
14806         pci_restore_state(tp->pdev);
14807
14808         if (!netif_running(dev))
14809                 return 0;
14810
14811         err = tg3_set_power_state(tp, PCI_D0);
14812         if (err)
14813                 return err;
14814
14815         netif_device_attach(dev);
14816
14817         tg3_full_lock(tp, 0);
14818
14819         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14820         err = tg3_restart_hw(tp, 1);
14821         if (err)
14822                 goto out;
14823
14824         tp->timer.expires = jiffies + tp->timer_offset;
14825         add_timer(&tp->timer);
14826
14827         tg3_netif_start(tp);
14828
14829 out:
14830         tg3_full_unlock(tp);
14831
14832         if (!err)
14833                 tg3_phy_start(tp);
14834
14835         return err;
14836 }
14837
14838 static struct pci_driver tg3_driver = {
14839         .name           = DRV_MODULE_NAME,
14840         .id_table       = tg3_pci_tbl,
14841         .probe          = tg3_init_one,
14842         .remove         = __devexit_p(tg3_remove_one),
14843         .suspend        = tg3_suspend,
14844         .resume         = tg3_resume
14845 };
14846
14847 static int __init tg3_init(void)
14848 {
14849         return pci_register_driver(&tg3_driver);
14850 }
14851
14852 static void __exit tg3_cleanup(void)
14853 {
14854         pci_unregister_driver(&tg3_driver);
14855 }
14856
14857 module_init(tg3_init);
14858 module_exit(tg3_cleanup);