drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2010 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/stringify.h>
  22 #include <linux/kernel.h>
  23 #include <linux/types.h>
  24 #include <linux/compiler.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/in.h>
  28 #include <linux/init.h>
  29 #include <linux/ioport.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/ethtool.h>
  35 #include <linux/mii.h>
  36 #include <linux/phy.h>
  37 #include <linux/brcmphy.h>
  38 #include <linux/if_vlan.h>
  39 #include <linux/ip.h>
  40 #include <linux/tcp.h>
  41 #include <linux/workqueue.h>
  42 #include <linux/prefetch.h>
  43 #include <linux/dma-mapping.h>
  44 #include <linux/firmware.h>
  45
  46 #include <net/checksum.h>
  47 #include <net/ip.h>
  48
  49 #include <asm/system.h>
  50 #include <asm/io.h>
  51 #include <asm/byteorder.h>
  52 #include <asm/uaccess.h>
  53
  54 #ifdef CONFIG_SPARC
  55 #include <asm/idprom.h>
  56 #include <asm/prom.h>
  57 #endif
  58
  59 #define BAR_0   0
  60 #define BAR_2   2
  61
  62 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  63 #define TG3_VLAN_TAG_USED 1
  64 #else
  65 #define TG3_VLAN_TAG_USED 0
  66 #endif
  67
  68 #include "tg3.h"
  69
  70 #define DRV_MODULE_NAME         "tg3"
  71 #define TG3_MAJ_NUM                     3
  72 #define TG3_MIN_NUM                     113
  73 #define DRV_MODULE_VERSION      \
  74         __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
  75 #define DRV_MODULE_RELDATE      "August 2, 2010"
  76
  77 #define TG3_DEF_MAC_MODE        0
  78 #define TG3_DEF_RX_MODE         0
  79 #define TG3_DEF_TX_MODE         0
  80 #define TG3_DEF_MSG_ENABLE        \
  81         (NETIF_MSG_DRV          | \
  82          NETIF_MSG_PROBE        | \
  83          NETIF_MSG_LINK         | \
  84          NETIF_MSG_TIMER        | \
  85          NETIF_MSG_IFDOWN       | \
  86          NETIF_MSG_IFUP         | \
  87          NETIF_MSG_RX_ERR       | \
  88          NETIF_MSG_TX_ERR)
  89
  90 /* length of time before we decide the hardware is borked,
  91  * and dev->tx_timeout() should be called to fix the problem
  92  */
  93 #define TG3_TX_TIMEOUT                  (5 * HZ)
  94
  95 /* hardware minimum and maximum for a single frame's data payload */
  96 #define TG3_MIN_MTU                     60
  97 #define TG3_MAX_MTU(tp) \
  98         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  99
 100 /* These numbers seem to be hard coded in the NIC firmware somehow.
 101  * You can't change the ring sizes, but you can change where you place
 102  * them in the NIC onboard memory.
 103  */
 104 #define TG3_RX_RING_SIZE                512
 105 #define TG3_DEF_RX_RING_PENDING         200
 106 #define TG3_RX_JUMBO_RING_SIZE          256
 107 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 108 #define TG3_RSS_INDIR_TBL_SIZE          128
 109
 110 /* Do not place this n-ring entries value into the tp struct itself,
 111  * we really want to expose these constants to GCC so that modulo et
 112  * al.  operations are done with shifts and masks instead of with
 113  * hw multiply/modulo instructions.  Another solution would be to
 114  * replace things like '% foo' with '& (foo - 1)'.
 115  */
 116 #define TG3_RX_RCB_RING_SIZE(tp)        \
 117         (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
 118           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
 119
 120 #define TG3_TX_RING_SIZE                512
 121 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 122
 123 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 124                                  TG3_RX_RING_SIZE)
 125 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
 126                                  TG3_RX_JUMBO_RING_SIZE)
 127 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 128                                  TG3_RX_RCB_RING_SIZE(tp))
 129 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 130                                  TG3_TX_RING_SIZE)
 131 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 132
 133 #define TG3_RX_DMA_ALIGN                16
 134 #define TG3_RX_HEADROOM                 ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
 135
 136 #define TG3_DMA_BYTE_ENAB               64
 137
 138 #define TG3_RX_STD_DMA_SZ               1536
 139 #define TG3_RX_JMB_DMA_SZ               9046
 140
 141 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 142
 143 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 144 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 145
 146 #define TG3_RX_STD_BUFF_RING_SIZE \
 147         (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
 148
 149 #define TG3_RX_JMB_BUFF_RING_SIZE \
 150         (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
 151
 152 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
 153  * that are at least dword aligned when used in PCIX mode.  The driver
 154  * works around this bug by double copying the packet.  This workaround
 155  * is built into the normal double copy length check for efficiency.
 156  *
 157  * However, the double copy is only necessary on those architectures
 158  * where unaligned memory accesses are inefficient.  For those architectures
 159  * where unaligned memory accesses incur little penalty, we can reintegrate
 160  * the 5701 in the normal rx path.  Doing so saves a device structure
 161  * dereference by hardcoding the double copy threshold in place.
 162  */
 163 #define TG3_RX_COPY_THRESHOLD           256
 164 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
 165         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
 166 #else
 167         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
 168 #endif
 169
 170 /* minimum number of free TX descriptors required to wake up TX process */
 171 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 172
 173 #define TG3_RAW_IP_ALIGN 2
 174
 175 /* number of ETHTOOL_GSTATS u64's */
 176 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 177
 178 #define TG3_NUM_TEST            6
 179
 180 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
 181
 182 #define FIRMWARE_TG3            "tigon/tg3.bin"
 183 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 184 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 185
 186 static char version[] __devinitdata =
 187         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
 188
 189 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 190 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 191 MODULE_LICENSE("GPL");
 192 MODULE_VERSION(DRV_MODULE_VERSION);
 193 MODULE_FIRMWARE(FIRMWARE_TG3);
 194 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 195 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 196
 197 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 198 module_param(tg3_debug, int, 0);
 199 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 200
 201 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 255         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 256         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 257         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 258         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 259         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 260         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 261         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 262         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 263         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 264         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 265         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
 266         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
 267         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
 268         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
 269         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
 270         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
 271         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
 272         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
 273         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
 274         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
 275         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 276         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 277         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 278         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 279         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 280         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 281         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 282         {}
 283 };
 284
 285 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 286
 287 static const struct {
 288         const char string[ETH_GSTRING_LEN];
 289 } ethtool_stats_keys[TG3_NUM_STATS] = {
 290         { "rx_octets" },
 291         { "rx_fragments" },
 292         { "rx_ucast_packets" },
 293         { "rx_mcast_packets" },
 294         { "rx_bcast_packets" },
 295         { "rx_fcs_errors" },
 296         { "rx_align_errors" },
 297         { "rx_xon_pause_rcvd" },
 298         { "rx_xoff_pause_rcvd" },
 299         { "rx_mac_ctrl_rcvd" },
 300         { "rx_xoff_entered" },
 301         { "rx_frame_too_long_errors" },
 302         { "rx_jabbers" },
 303         { "rx_undersize_packets" },
 304         { "rx_in_length_errors" },
 305         { "rx_out_length_errors" },
 306         { "rx_64_or_less_octet_packets" },
 307         { "rx_65_to_127_octet_packets" },
 308         { "rx_128_to_255_octet_packets" },
 309         { "rx_256_to_511_octet_packets" },
 310         { "rx_512_to_1023_octet_packets" },
 311         { "rx_1024_to_1522_octet_packets" },
 312         { "rx_1523_to_2047_octet_packets" },
 313         { "rx_2048_to_4095_octet_packets" },
 314         { "rx_4096_to_8191_octet_packets" },
 315         { "rx_8192_to_9022_octet_packets" },
 316
 317         { "tx_octets" },
 318         { "tx_collisions" },
 319
 320         { "tx_xon_sent" },
 321         { "tx_xoff_sent" },
 322         { "tx_flow_control" },
 323         { "tx_mac_errors" },
 324         { "tx_single_collisions" },
 325         { "tx_mult_collisions" },
 326         { "tx_deferred" },
 327         { "tx_excessive_collisions" },
 328         { "tx_late_collisions" },
 329         { "tx_collide_2times" },
 330         { "tx_collide_3times" },
 331         { "tx_collide_4times" },
 332         { "tx_collide_5times" },
 333         { "tx_collide_6times" },
 334         { "tx_collide_7times" },
 335         { "tx_collide_8times" },
 336         { "tx_collide_9times" },
 337         { "tx_collide_10times" },
 338         { "tx_collide_11times" },
 339         { "tx_collide_12times" },
 340         { "tx_collide_13times" },
 341         { "tx_collide_14times" },
 342         { "tx_collide_15times" },
 343         { "tx_ucast_packets" },
 344         { "tx_mcast_packets" },
 345         { "tx_bcast_packets" },
 346         { "tx_carrier_sense_errors" },
 347         { "tx_discards" },
 348         { "tx_errors" },
 349
 350         { "dma_writeq_full" },
 351         { "dma_write_prioq_full" },
 352         { "rxbds_empty" },
 353         { "rx_discards" },
 354         { "rx_errors" },
 355         { "rx_threshold_hit" },
 356
 357         { "dma_readq_full" },
 358         { "dma_read_prioq_full" },
 359         { "tx_comp_queue_full" },
 360
 361         { "ring_set_send_prod_index" },
 362         { "ring_status_update" },
 363         { "nic_irqs" },
 364         { "nic_avoided_irqs" },
 365         { "nic_tx_threshold_hit" }
 366 };
 367
 368 static const struct {
 369         const char string[ETH_GSTRING_LEN];
 370 } ethtool_test_keys[TG3_NUM_TEST] = {
 371         { "nvram test     (online) " },
 372         { "link test      (online) " },
 373         { "register test  (offline)" },
 374         { "memory test    (offline)" },
 375         { "loopback test  (offline)" },
 376         { "interrupt test (offline)" },
 377 };
 378
 379 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 380 {
 381         writel(val, tp->regs + off);
 382 }
 383
 384 static u32 tg3_read32(struct tg3 *tp, u32 off)
 385 {
 386         return readl(tp->regs + off);
 387 }
 388
 389 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 390 {
 391         writel(val, tp->aperegs + off);
 392 }
 393
 394 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 395 {
 396         return readl(tp->aperegs + off);
 397 }
 398
 399 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 400 {
 401         unsigned long flags;
 402
 403         spin_lock_irqsave(&tp->indirect_lock, flags);
 404         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 405         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 406         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 407 }
 408
 409 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 410 {
 411         writel(val, tp->regs + off);
 412         readl(tp->regs + off);
 413 }
 414
 415 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 416 {
 417         unsigned long flags;
 418         u32 val;
 419
 420         spin_lock_irqsave(&tp->indirect_lock, flags);
 421         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 422         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 423         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 424         return val;
 425 }
 426
 427 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 428 {
 429         unsigned long flags;
 430
 431         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 432                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 433                                        TG3_64BIT_REG_LOW, val);
 434                 return;
 435         }
 436         if (off == TG3_RX_STD_PROD_IDX_REG) {
 437                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 438                                        TG3_64BIT_REG_LOW, val);
 439                 return;
 440         }
 441
 442         spin_lock_irqsave(&tp->indirect_lock, flags);
 443         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 444         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 445         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 446
 447         /* In indirect mode when disabling interrupts, we also need
 448          * to clear the interrupt bit in the GRC local ctrl register.
 449          */
 450         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 451             (val == 0x1)) {
 452                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 453                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 454         }
 455 }
 456
 457 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 458 {
 459         unsigned long flags;
 460         u32 val;
 461
 462         spin_lock_irqsave(&tp->indirect_lock, flags);
 463         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 464         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 465         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 466         return val;
 467 }
 468
 469 /* usec_wait specifies the wait time in usec when writing to certain registers
 470  * where it is unsafe to read back the register without some delay.
 471  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 472  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 473  */
 474 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 475 {
 476         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 477             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 478                 /* Non-posted methods */
 479                 tp->write32(tp, off, val);
 480         else {
 481                 /* Posted method */
 482                 tg3_write32(tp, off, val);
 483                 if (usec_wait)
 484                         udelay(usec_wait);
 485                 tp->read32(tp, off);
 486         }
 487         /* Wait again after the read for the posted method to guarantee that
 488          * the wait time is met.
 489          */
 490         if (usec_wait)
 491                 udelay(usec_wait);
 492 }
 493
 494 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 495 {
 496         tp->write32_mbox(tp, off, val);
 497         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 498             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 499                 tp->read32_mbox(tp, off);
 500 }
 501
 502 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 503 {
 504         void __iomem *mbox = tp->regs + off;
 505         writel(val, mbox);
 506         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 507                 writel(val, mbox);
 508         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 509                 readl(mbox);
 510 }
 511
 512 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 513 {
 514         return readl(tp->regs + off + GRCMBOX_BASE);
 515 }
 516
 517 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 518 {
 519         writel(val, tp->regs + off + GRCMBOX_BASE);
 520 }
 521
 522 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
 523 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 524 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
 525 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
 526 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
 527
 528 #define tw32(reg, val)                  tp->write32(tp, reg, val)
 529 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
 530 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
 531 #define tr32(reg)                       tp->read32(tp, reg)
 532
 533 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 534 {
 535         unsigned long flags;
 536
 537         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 538             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 539                 return;
 540
 541         spin_lock_irqsave(&tp->indirect_lock, flags);
 542         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 543                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 544                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 545
 546                 /* Always leave this as zero. */
 547                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 548         } else {
 549                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 550                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 551
 552                 /* Always leave this as zero. */
 553                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 554         }
 555         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 556 }
 557
 558 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 559 {
 560         unsigned long flags;
 561
 562         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 563             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 564                 *val = 0;
 565                 return;
 566         }
 567
 568         spin_lock_irqsave(&tp->indirect_lock, flags);
 569         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 570                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 571                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 572
 573                 /* Always leave this as zero. */
 574                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 575         } else {
 576                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 577                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 578
 579                 /* Always leave this as zero. */
 580                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 581         }
 582         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 583 }
 584
 585 static void tg3_ape_lock_init(struct tg3 *tp)
 586 {
 587         int i;
 588         u32 regbase;
 589
 590         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 591                 regbase = TG3_APE_LOCK_GRANT;
 592         else
 593                 regbase = TG3_APE_PER_LOCK_GRANT;
 594
 595         /* Make sure the driver hasn't any stale locks. */
 596         for (i = 0; i < 8; i++)
 597                 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
 598 }
 599
 600 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 601 {
 602         int i, off;
 603         int ret = 0;
 604         u32 status, req, gnt;
 605
 606         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 607                 return 0;
 608
 609         switch (locknum) {
 610         case TG3_APE_LOCK_GRC:
 611         case TG3_APE_LOCK_MEM:
 612                 break;
 613         default:
 614                 return -EINVAL;
 615         }
 616
 617         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
 618                 req = TG3_APE_LOCK_REQ;
 619                 gnt = TG3_APE_LOCK_GRANT;
 620         } else {
 621                 req = TG3_APE_PER_LOCK_REQ;
 622                 gnt = TG3_APE_PER_LOCK_GRANT;
 623         }
 624
 625         off = 4 * locknum;
 626
 627         tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
 628
 629         /* Wait for up to 1 millisecond to acquire lock. */
 630         for (i = 0; i < 100; i++) {
 631                 status = tg3_ape_read32(tp, gnt + off);
 632                 if (status == APE_LOCK_GRANT_DRIVER)
 633                         break;
 634                 udelay(10);
 635         }
 636
 637         if (status != APE_LOCK_GRANT_DRIVER) {
 638                 /* Revoke the lock request. */
 639                 tg3_ape_write32(tp, gnt + off,
 640                                 APE_LOCK_GRANT_DRIVER);
 641
 642                 ret = -EBUSY;
 643         }
 644
 645         return ret;
 646 }
 647
 648 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 649 {
 650         u32 gnt;
 651
 652         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 653                 return;
 654
 655         switch (locknum) {
 656         case TG3_APE_LOCK_GRC:
 657         case TG3_APE_LOCK_MEM:
 658                 break;
 659         default:
 660                 return;
 661         }
 662
 663         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 664                 gnt = TG3_APE_LOCK_GRANT;
 665         else
 666                 gnt = TG3_APE_PER_LOCK_GRANT;
 667
 668         tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
 669 }
 670
 671 static void tg3_disable_ints(struct tg3 *tp)
 672 {
 673         int i;
 674
 675         tw32(TG3PCI_MISC_HOST_CTRL,
 676              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 677         for (i = 0; i < tp->irq_max; i++)
 678                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 679 }
 680
 681 static void tg3_enable_ints(struct tg3 *tp)
 682 {
 683         int i;
 684
 685         tp->irq_sync = 0;
 686         wmb();
 687
 688         tw32(TG3PCI_MISC_HOST_CTRL,
 689              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 690
 691         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
 692         for (i = 0; i < tp->irq_cnt; i++) {
 693                 struct tg3_napi *tnapi = &tp->napi[i];
 694
 695                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 696                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 697                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 698
 699                 tp->coal_now |= tnapi->coal_now;
 700         }
 701
 702         /* Force an initial interrupt */
 703         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 704             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 705                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 706         else
 707                 tw32(HOSTCC_MODE, tp->coal_now);
 708
 709         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
 710 }
 711
 712 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 713 {
 714         struct tg3 *tp = tnapi->tp;
 715         struct tg3_hw_status *sblk = tnapi->hw_status;
 716         unsigned int work_exists = 0;
 717
 718         /* check for phy events */
 719         if (!(tp->tg3_flags &
 720               (TG3_FLAG_USE_LINKCHG_REG |
 721                TG3_FLAG_POLL_SERDES))) {
 722                 if (sblk->status & SD_STATUS_LINK_CHG)
 723                         work_exists = 1;
 724         }
 725         /* check for RX/TX work to do */
 726         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 727             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
 728                 work_exists = 1;
 729
 730         return work_exists;
 731 }
 732
 733 /* tg3_int_reenable
 734  *  similar to tg3_enable_ints, but it accurately determines whether there
 735  *  is new work pending and can return without flushing the PIO write
 736  *  which reenables interrupts
 737  */
 738 static void tg3_int_reenable(struct tg3_napi *tnapi)
 739 {
 740         struct tg3 *tp = tnapi->tp;
 741
 742         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 743         mmiowb();
 744
 745         /* When doing tagged status, this work check is unnecessary.
 746          * The last_tag we write above tells the chip which piece of
 747          * work we've completed.
 748          */
 749         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 750             tg3_has_work(tnapi))
 751                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 752                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 753 }
 754
 755 static void tg3_napi_disable(struct tg3 *tp)
 756 {
 757         int i;
 758
 759         for (i = tp->irq_cnt - 1; i >= 0; i--)
 760                 napi_disable(&tp->napi[i].napi);
 761 }
 762
 763 static void tg3_napi_enable(struct tg3 *tp)
 764 {
 765         int i;
 766
 767         for (i = 0; i < tp->irq_cnt; i++)
 768                 napi_enable(&tp->napi[i].napi);
 769 }
 770
 771 static inline void tg3_netif_stop(struct tg3 *tp)
 772 {
 773         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 774         tg3_napi_disable(tp);
 775         netif_tx_disable(tp->dev);
 776 }
 777
 778 static inline void tg3_netif_start(struct tg3 *tp)
 779 {
 780         /* NOTE: unconditional netif_tx_wake_all_queues is only
 781          * appropriate so long as all callers are assured to
 782          * have free tx slots (such as after tg3_init_hw)
 783          */
 784         netif_tx_wake_all_queues(tp->dev);
 785
 786         tg3_napi_enable(tp);
 787         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
 788         tg3_enable_ints(tp);
 789 }
 790
 791 static void tg3_switch_clocks(struct tg3 *tp)
 792 {
 793         u32 clock_ctrl;
 794         u32 orig_clock_ctrl;
 795
 796         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 797             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 798                 return;
 799
 800         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 801
 802         orig_clock_ctrl = clock_ctrl;
 803         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 804                        CLOCK_CTRL_CLKRUN_OENABLE |
 805                        0x1f);
 806         tp->pci_clock_ctrl = clock_ctrl;
 807
 808         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 809                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 810                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 811                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 812                 }
 813         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 814                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 815                             clock_ctrl |
 816                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 817                             40);
 818                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 819                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 820                             40);
 821         }
 822         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 823 }
 824
 825 #define PHY_BUSY_LOOPS  5000
 826
 827 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 828 {
 829         u32 frame_val;
 830         unsigned int loops;
 831         int ret;
 832
 833         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 834                 tw32_f(MAC_MI_MODE,
 835                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 836                 udelay(80);
 837         }
 838
 839         *val = 0x0;
 840
 841         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 842                       MI_COM_PHY_ADDR_MASK);
 843         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 844                       MI_COM_REG_ADDR_MASK);
 845         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 846
 847         tw32_f(MAC_MI_COM, frame_val);
 848
 849         loops = PHY_BUSY_LOOPS;
 850         while (loops != 0) {
 851                 udelay(10);
 852                 frame_val = tr32(MAC_MI_COM);
 853
 854                 if ((frame_val & MI_COM_BUSY) == 0) {
 855                         udelay(5);
 856                         frame_val = tr32(MAC_MI_COM);
 857                         break;
 858                 }
 859                 loops -= 1;
 860         }
 861
 862         ret = -EBUSY;
 863         if (loops != 0) {
 864                 *val = frame_val & MI_COM_DATA_MASK;
 865                 ret = 0;
 866         }
 867
 868         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 869                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 870                 udelay(80);
 871         }
 872
 873         return ret;
 874 }
 875
 876 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 877 {
 878         u32 frame_val;
 879         unsigned int loops;
 880         int ret;
 881
 882         if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
 883             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 884                 return 0;
 885
 886         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 887                 tw32_f(MAC_MI_MODE,
 888                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 889                 udelay(80);
 890         }
 891
 892         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 893                       MI_COM_PHY_ADDR_MASK);
 894         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 895                       MI_COM_REG_ADDR_MASK);
 896         frame_val |= (val & MI_COM_DATA_MASK);
 897         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 898
 899         tw32_f(MAC_MI_COM, frame_val);
 900
 901         loops = PHY_BUSY_LOOPS;
 902         while (loops != 0) {
 903                 udelay(10);
 904                 frame_val = tr32(MAC_MI_COM);
 905                 if ((frame_val & MI_COM_BUSY) == 0) {
 906                         udelay(5);
 907                         frame_val = tr32(MAC_MI_COM);
 908                         break;
 909                 }
 910                 loops -= 1;
 911         }
 912
 913         ret = -EBUSY;
 914         if (loops != 0)
 915                 ret = 0;
 916
 917         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 918                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 919                 udelay(80);
 920         }
 921
 922         return ret;
 923 }
 924
 925 static int tg3_bmcr_reset(struct tg3 *tp)
 926 {
 927         u32 phy_control;
 928         int limit, err;
 929
 930         /* OK, reset it, and poll the BMCR_RESET bit until it
 931          * clears or we time out.
 932          */
 933         phy_control = BMCR_RESET;
 934         err = tg3_writephy(tp, MII_BMCR, phy_control);
 935         if (err != 0)
 936                 return -EBUSY;
 937
 938         limit = 5000;
 939         while (limit--) {
 940                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 941                 if (err != 0)
 942                         return -EBUSY;
 943
 944                 if ((phy_control & BMCR_RESET) == 0) {
 945                         udelay(40);
 946                         break;
 947                 }
 948                 udelay(10);
 949         }
 950         if (limit < 0)
 951                 return -EBUSY;
 952
 953         return 0;
 954 }
 955
 956 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 957 {
 958         struct tg3 *tp = bp->priv;
 959         u32 val;
 960
 961         spin_lock_bh(&tp->lock);
 962
 963         if (tg3_readphy(tp, reg, &val))
 964                 val = -EIO;
 965
 966         spin_unlock_bh(&tp->lock);
 967
 968         return val;
 969 }
 970
 971 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 972 {
 973         struct tg3 *tp = bp->priv;
 974         u32 ret = 0;
 975
 976         spin_lock_bh(&tp->lock);
 977
 978         if (tg3_writephy(tp, reg, val))
 979                 ret = -EIO;
 980
 981         spin_unlock_bh(&tp->lock);
 982
 983         return ret;
 984 }
 985
 986 static int tg3_mdio_reset(struct mii_bus *bp)
 987 {
 988         return 0;
 989 }
 990
 991 static void tg3_mdio_config_5785(struct tg3 *tp)
 992 {
 993         u32 val;
 994         struct phy_device *phydev;
 995
 996         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
 997         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 998         case PHY_ID_BCM50610:
 999         case PHY_ID_BCM50610M:
1000                 val = MAC_PHYCFG2_50610_LED_MODES;
1001                 break;
1002         case PHY_ID_BCMAC131:
1003                 val = MAC_PHYCFG2_AC131_LED_MODES;
1004                 break;
1005         case PHY_ID_RTL8211C:
1006                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1007                 break;
1008         case PHY_ID_RTL8201E:
1009                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1010                 break;
1011         default:
1012                 return;
1013         }
1014
1015         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1016                 tw32(MAC_PHYCFG2, val);
1017
1018                 val = tr32(MAC_PHYCFG1);
1019                 val &= ~(MAC_PHYCFG1_RGMII_INT |
1020                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1021                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1022                 tw32(MAC_PHYCFG1, val);
1023
1024                 return;
1025         }
1026
1027         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
1028                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1029                        MAC_PHYCFG2_FMODE_MASK_MASK |
1030                        MAC_PHYCFG2_GMODE_MASK_MASK |
1031                        MAC_PHYCFG2_ACT_MASK_MASK   |
1032                        MAC_PHYCFG2_QUAL_MASK_MASK |
1033                        MAC_PHYCFG2_INBAND_ENABLE;
1034
1035         tw32(MAC_PHYCFG2, val);
1036
1037         val = tr32(MAC_PHYCFG1);
1038         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1039                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1040         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1041                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1042                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1043                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1044                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1045         }
1046         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1047                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1048         tw32(MAC_PHYCFG1, val);
1049
1050         val = tr32(MAC_EXT_RGMII_MODE);
1051         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1052                  MAC_RGMII_MODE_RX_QUALITY |
1053                  MAC_RGMII_MODE_RX_ACTIVITY |
1054                  MAC_RGMII_MODE_RX_ENG_DET |
1055                  MAC_RGMII_MODE_TX_ENABLE |
1056                  MAC_RGMII_MODE_TX_LOWPWR |
1057                  MAC_RGMII_MODE_TX_RESET);
1058         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1059                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1060                         val |= MAC_RGMII_MODE_RX_INT_B |
1061                                MAC_RGMII_MODE_RX_QUALITY |
1062                                MAC_RGMII_MODE_RX_ACTIVITY |
1063                                MAC_RGMII_MODE_RX_ENG_DET;
1064                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1065                         val |= MAC_RGMII_MODE_TX_ENABLE |
1066                                MAC_RGMII_MODE_TX_LOWPWR |
1067                                MAC_RGMII_MODE_TX_RESET;
1068         }
1069         tw32(MAC_EXT_RGMII_MODE, val);
1070 }
1071
1072 static void tg3_mdio_start(struct tg3 *tp)
1073 {
1074         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1075         tw32_f(MAC_MI_MODE, tp->mi_mode);
1076         udelay(80);
1077
1078         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1079             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1080                 tg3_mdio_config_5785(tp);
1081 }
1082
1083 static int tg3_mdio_init(struct tg3 *tp)
1084 {
1085         int i;
1086         u32 reg;
1087         struct phy_device *phydev;
1088
1089         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1090             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
1091                 u32 is_serdes;
1092
1093                 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1094
1095                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1096                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1097                 else
1098                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1099                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1100                 if (is_serdes)
1101                         tp->phy_addr += 7;
1102         } else
1103                 tp->phy_addr = TG3_PHY_MII_ADDR;
1104
1105         tg3_mdio_start(tp);
1106
1107         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1108             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1109                 return 0;
1110
1111         tp->mdio_bus = mdiobus_alloc();
1112         if (tp->mdio_bus == NULL)
1113                 return -ENOMEM;
1114
1115         tp->mdio_bus->name     = "tg3 mdio bus";
1116         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1117                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1118         tp->mdio_bus->priv     = tp;
1119         tp->mdio_bus->parent   = &tp->pdev->dev;
1120         tp->mdio_bus->read     = &tg3_mdio_read;
1121         tp->mdio_bus->write    = &tg3_mdio_write;
1122         tp->mdio_bus->reset    = &tg3_mdio_reset;
1123         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1124         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1125
1126         for (i = 0; i < PHY_MAX_ADDR; i++)
1127                 tp->mdio_bus->irq[i] = PHY_POLL;
1128
1129         /* The bus registration will look for all the PHYs on the mdio bus.
1130          * Unfortunately, it does not ensure the PHY is powered up before
1131          * accessing the PHY ID registers.  A chip reset is the
1132          * quickest way to bring the device back to an operational state..
1133          */
1134         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1135                 tg3_bmcr_reset(tp);
1136
1137         i = mdiobus_register(tp->mdio_bus);
1138         if (i) {
1139                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1140                 mdiobus_free(tp->mdio_bus);
1141                 return i;
1142         }
1143
1144         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1145
1146         if (!phydev || !phydev->drv) {
1147                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1148                 mdiobus_unregister(tp->mdio_bus);
1149                 mdiobus_free(tp->mdio_bus);
1150                 return -ENODEV;
1151         }
1152
1153         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1154         case PHY_ID_BCM57780:
1155                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1156                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1157                 break;
1158         case PHY_ID_BCM50610:
1159         case PHY_ID_BCM50610M:
1160                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1161                                      PHY_BRCM_RX_REFCLK_UNUSED |
1162                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1163                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1164                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1165                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1166                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1167                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1168                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1169                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1170                 /* fallthru */
1171         case PHY_ID_RTL8211C:
1172                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1173                 break;
1174         case PHY_ID_RTL8201E:
1175         case PHY_ID_BCMAC131:
1176                 phydev->interface = PHY_INTERFACE_MODE_MII;
1177                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1178                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1179                 break;
1180         }
1181
1182         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1183
1184         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1185                 tg3_mdio_config_5785(tp);
1186
1187         return 0;
1188 }
1189
1190 static void tg3_mdio_fini(struct tg3 *tp)
1191 {
1192         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1193                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1194                 mdiobus_unregister(tp->mdio_bus);
1195                 mdiobus_free(tp->mdio_bus);
1196         }
1197 }
1198
1199 /* tp->lock is held. */
1200 static inline void tg3_generate_fw_event(struct tg3 *tp)
1201 {
1202         u32 val;
1203
1204         val = tr32(GRC_RX_CPU_EVENT);
1205         val |= GRC_RX_CPU_DRIVER_EVENT;
1206         tw32_f(GRC_RX_CPU_EVENT, val);
1207
1208         tp->last_event_jiffies = jiffies;
1209 }
1210
1211 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1212
1213 /* tp->lock is held. */
1214 static void tg3_wait_for_event_ack(struct tg3 *tp)
1215 {
1216         int i;
1217         unsigned int delay_cnt;
1218         long time_remain;
1219
1220         /* If enough time has passed, no wait is necessary. */
1221         time_remain = (long)(tp->last_event_jiffies + 1 +
1222                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1223                       (long)jiffies;
1224         if (time_remain < 0)
1225                 return;
1226
1227         /* Check if we can shorten the wait time. */
1228         delay_cnt = jiffies_to_usecs(time_remain);
1229         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1230                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1231         delay_cnt = (delay_cnt >> 3) + 1;
1232
1233         for (i = 0; i < delay_cnt; i++) {
1234                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1235                         break;
1236                 udelay(8);
1237         }
1238 }
1239
1240 /* tp->lock is held. */
1241 static void tg3_ump_link_report(struct tg3 *tp)
1242 {
1243         u32 reg;
1244         u32 val;
1245
1246         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1247             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1248                 return;
1249
1250         tg3_wait_for_event_ack(tp);
1251
1252         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1253
1254         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1255
1256         val = 0;
1257         if (!tg3_readphy(tp, MII_BMCR, &reg))
1258                 val = reg << 16;
1259         if (!tg3_readphy(tp, MII_BMSR, &reg))
1260                 val |= (reg & 0xffff);
1261         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1262
1263         val = 0;
1264         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1265                 val = reg << 16;
1266         if (!tg3_readphy(tp, MII_LPA, &reg))
1267                 val |= (reg & 0xffff);
1268         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1269
1270         val = 0;
1271         if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1272                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1273                         val = reg << 16;
1274                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1275                         val |= (reg & 0xffff);
1276         }
1277         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1278
1279         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1280                 val = reg << 16;
1281         else
1282                 val = 0;
1283         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1284
1285         tg3_generate_fw_event(tp);
1286 }
1287
1288 static void tg3_link_report(struct tg3 *tp)
1289 {
1290         if (!netif_carrier_ok(tp->dev)) {
1291                 netif_info(tp, link, tp->dev, "Link is down\n");
1292                 tg3_ump_link_report(tp);
1293         } else if (netif_msg_link(tp)) {
1294                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1295                             (tp->link_config.active_speed == SPEED_1000 ?
1296                              1000 :
1297                              (tp->link_config.active_speed == SPEED_100 ?
1298                               100 : 10)),
1299                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1300                              "full" : "half"));
1301
1302                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1303                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1304                             "on" : "off",
1305                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1306                             "on" : "off");
1307                 tg3_ump_link_report(tp);
1308         }
1309 }
1310
1311 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1312 {
1313         u16 miireg;
1314
1315         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1316                 miireg = ADVERTISE_PAUSE_CAP;
1317         else if (flow_ctrl & FLOW_CTRL_TX)
1318                 miireg = ADVERTISE_PAUSE_ASYM;
1319         else if (flow_ctrl & FLOW_CTRL_RX)
1320                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1321         else
1322                 miireg = 0;
1323
1324         return miireg;
1325 }
1326
1327 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1328 {
1329         u16 miireg;
1330
1331         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1332                 miireg = ADVERTISE_1000XPAUSE;
1333         else if (flow_ctrl & FLOW_CTRL_TX)
1334                 miireg = ADVERTISE_1000XPSE_ASYM;
1335         else if (flow_ctrl & FLOW_CTRL_RX)
1336                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1337         else
1338                 miireg = 0;
1339
1340         return miireg;
1341 }
1342
1343 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1344 {
1345         u8 cap = 0;
1346
1347         if (lcladv & ADVERTISE_1000XPAUSE) {
1348                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1349                         if (rmtadv & LPA_1000XPAUSE)
1350                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1351                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1352                                 cap = FLOW_CTRL_RX;
1353                 } else {
1354                         if (rmtadv & LPA_1000XPAUSE)
1355                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1356                 }
1357         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1358                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1359                         cap = FLOW_CTRL_TX;
1360         }
1361
1362         return cap;
1363 }
1364
1365 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1366 {
1367         u8 autoneg;
1368         u8 flowctrl = 0;
1369         u32 old_rx_mode = tp->rx_mode;
1370         u32 old_tx_mode = tp->tx_mode;
1371
1372         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1373                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1374         else
1375                 autoneg = tp->link_config.autoneg;
1376
1377         if (autoneg == AUTONEG_ENABLE &&
1378             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1379                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1380                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1381                 else
1382                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1383         } else
1384                 flowctrl = tp->link_config.flowctrl;
1385
1386         tp->link_config.active_flowctrl = flowctrl;
1387
1388         if (flowctrl & FLOW_CTRL_RX)
1389                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1390         else
1391                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1392
1393         if (old_rx_mode != tp->rx_mode)
1394                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1395
1396         if (flowctrl & FLOW_CTRL_TX)
1397                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1398         else
1399                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1400
1401         if (old_tx_mode != tp->tx_mode)
1402                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1403 }
1404
1405 static void tg3_adjust_link(struct net_device *dev)
1406 {
1407         u8 oldflowctrl, linkmesg = 0;
1408         u32 mac_mode, lcl_adv, rmt_adv;
1409         struct tg3 *tp = netdev_priv(dev);
1410         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1411
1412         spin_lock_bh(&tp->lock);
1413
1414         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1415                                     MAC_MODE_HALF_DUPLEX);
1416
1417         oldflowctrl = tp->link_config.active_flowctrl;
1418
1419         if (phydev->link) {
1420                 lcl_adv = 0;
1421                 rmt_adv = 0;
1422
1423                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1424                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1425                 else if (phydev->speed == SPEED_1000 ||
1426                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1427                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1428                 else
1429                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1430
1431                 if (phydev->duplex == DUPLEX_HALF)
1432                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1433                 else {
1434                         lcl_adv = tg3_advert_flowctrl_1000T(
1435                                   tp->link_config.flowctrl);
1436
1437                         if (phydev->pause)
1438                                 rmt_adv = LPA_PAUSE_CAP;
1439                         if (phydev->asym_pause)
1440                                 rmt_adv |= LPA_PAUSE_ASYM;
1441                 }
1442
1443                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1444         } else
1445                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1446
1447         if (mac_mode != tp->mac_mode) {
1448                 tp->mac_mode = mac_mode;
1449                 tw32_f(MAC_MODE, tp->mac_mode);
1450                 udelay(40);
1451         }
1452
1453         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1454                 if (phydev->speed == SPEED_10)
1455                         tw32(MAC_MI_STAT,
1456                              MAC_MI_STAT_10MBPS_MODE |
1457                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1458                 else
1459                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1460         }
1461
1462         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1463                 tw32(MAC_TX_LENGTHS,
1464                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1465                       (6 << TX_LENGTHS_IPG_SHIFT) |
1466                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1467         else
1468                 tw32(MAC_TX_LENGTHS,
1469                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1470                       (6 << TX_LENGTHS_IPG_SHIFT) |
1471                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1472
1473         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1474             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1475             phydev->speed != tp->link_config.active_speed ||
1476             phydev->duplex != tp->link_config.active_duplex ||
1477             oldflowctrl != tp->link_config.active_flowctrl)
1478                 linkmesg = 1;
1479
1480         tp->link_config.active_speed = phydev->speed;
1481         tp->link_config.active_duplex = phydev->duplex;
1482
1483         spin_unlock_bh(&tp->lock);
1484
1485         if (linkmesg)
1486                 tg3_link_report(tp);
1487 }
1488
1489 static int tg3_phy_init(struct tg3 *tp)
1490 {
1491         struct phy_device *phydev;
1492
1493         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1494                 return 0;
1495
1496         /* Bring the PHY back to a known state. */
1497         tg3_bmcr_reset(tp);
1498
1499         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1500
1501         /* Attach the MAC to the PHY. */
1502         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1503                              phydev->dev_flags, phydev->interface);
1504         if (IS_ERR(phydev)) {
1505                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1506                 return PTR_ERR(phydev);
1507         }
1508
1509         /* Mask with MAC supported features. */
1510         switch (phydev->interface) {
1511         case PHY_INTERFACE_MODE_GMII:
1512         case PHY_INTERFACE_MODE_RGMII:
1513                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1514                         phydev->supported &= (PHY_GBIT_FEATURES |
1515                                               SUPPORTED_Pause |
1516                                               SUPPORTED_Asym_Pause);
1517                         break;
1518                 }
1519                 /* fallthru */
1520         case PHY_INTERFACE_MODE_MII:
1521                 phydev->supported &= (PHY_BASIC_FEATURES |
1522                                       SUPPORTED_Pause |
1523                                       SUPPORTED_Asym_Pause);
1524                 break;
1525         default:
1526                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1527                 return -EINVAL;
1528         }
1529
1530         tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1531
1532         phydev->advertising = phydev->supported;
1533
1534         return 0;
1535 }
1536
1537 static void tg3_phy_start(struct tg3 *tp)
1538 {
1539         struct phy_device *phydev;
1540
1541         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1542                 return;
1543
1544         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1545
1546         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1547                 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1548                 phydev->speed = tp->link_config.orig_speed;
1549                 phydev->duplex = tp->link_config.orig_duplex;
1550                 phydev->autoneg = tp->link_config.orig_autoneg;
1551                 phydev->advertising = tp->link_config.orig_advertising;
1552         }
1553
1554         phy_start(phydev);
1555
1556         phy_start_aneg(phydev);
1557 }
1558
1559 static void tg3_phy_stop(struct tg3 *tp)
1560 {
1561         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1562                 return;
1563
1564         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1565 }
1566
1567 static void tg3_phy_fini(struct tg3 *tp)
1568 {
1569         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1570                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1571                 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1572         }
1573 }
1574
1575 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1576 {
1577         int err;
1578
1579         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1580         if (!err)
1581                 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1582
1583         return err;
1584 }
1585
1586 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1587 {
1588         u32 phytest;
1589
1590         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1591                 u32 phy;
1592
1593                 tg3_writephy(tp, MII_TG3_FET_TEST,
1594                              phytest | MII_TG3_FET_SHADOW_EN);
1595                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1596                         if (enable)
1597                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1598                         else
1599                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1600                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1601                 }
1602                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1603         }
1604 }
1605
1606 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1607 {
1608         u32 reg;
1609
1610         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1611             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1612               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1613              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1614                 return;
1615
1616         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1617                 tg3_phy_fet_toggle_apd(tp, enable);
1618                 return;
1619         }
1620
1621         reg = MII_TG3_MISC_SHDW_WREN |
1622               MII_TG3_MISC_SHDW_SCR5_SEL |
1623               MII_TG3_MISC_SHDW_SCR5_LPED |
1624               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1625               MII_TG3_MISC_SHDW_SCR5_SDTL |
1626               MII_TG3_MISC_SHDW_SCR5_C125OE;
1627         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1628                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1629
1630         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1631
1632
1633         reg = MII_TG3_MISC_SHDW_WREN |
1634               MII_TG3_MISC_SHDW_APD_SEL |
1635               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1636         if (enable)
1637                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1638
1639         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1640 }
1641
1642 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1643 {
1644         u32 phy;
1645
1646         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1647             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
1648                 return;
1649
1650         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1651                 u32 ephy;
1652
1653                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1654                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1655
1656                         tg3_writephy(tp, MII_TG3_FET_TEST,
1657                                      ephy | MII_TG3_FET_SHADOW_EN);
1658                         if (!tg3_readphy(tp, reg, &phy)) {
1659                                 if (enable)
1660                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1661                                 else
1662                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1663                                 tg3_writephy(tp, reg, phy);
1664                         }
1665                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1666                 }
1667         } else {
1668                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1669                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1670                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1671                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1672                         if (enable)
1673                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1674                         else
1675                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1676                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1677                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1678                 }
1679         }
1680 }
1681
1682 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1683 {
1684         u32 val;
1685
1686         if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1687                 return;
1688
1689         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1690             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1691                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1692                              (val | (1 << 15) | (1 << 4)));
1693 }
1694
1695 static void tg3_phy_apply_otp(struct tg3 *tp)
1696 {
1697         u32 otp, phy;
1698
1699         if (!tp->phy_otp)
1700                 return;
1701
1702         otp = tp->phy_otp;
1703
1704         /* Enable SM_DSP clock and tx 6dB coding. */
1705         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1706               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1707               MII_TG3_AUXCTL_ACTL_TX_6DB;
1708         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1709
1710         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1711         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1712         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1713
1714         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1715               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1716         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1717
1718         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1719         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1720         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1721
1722         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1723         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1724
1725         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1726         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1727
1728         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1729               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1730         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1731
1732         /* Turn off SM_DSP clock. */
1733         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1734               MII_TG3_AUXCTL_ACTL_TX_6DB;
1735         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1736 }
1737
1738 static int tg3_wait_macro_done(struct tg3 *tp)
1739 {
1740         int limit = 100;
1741
1742         while (limit--) {
1743                 u32 tmp32;
1744
1745                 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1746                         if ((tmp32 & 0x1000) == 0)
1747                                 break;
1748                 }
1749         }
1750         if (limit < 0)
1751                 return -EBUSY;
1752
1753         return 0;
1754 }
1755
1756 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1757 {
1758         static const u32 test_pat[4][6] = {
1759         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1760         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1761         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1762         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1763         };
1764         int chan;
1765
1766         for (chan = 0; chan < 4; chan++) {
1767                 int i;
1768
1769                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1770                              (chan * 0x2000) | 0x0200);
1771                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1772
1773                 for (i = 0; i < 6; i++)
1774                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1775                                      test_pat[chan][i]);
1776
1777                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1778                 if (tg3_wait_macro_done(tp)) {
1779                         *resetp = 1;
1780                         return -EBUSY;
1781                 }
1782
1783                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1784                              (chan * 0x2000) | 0x0200);
1785                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1786                 if (tg3_wait_macro_done(tp)) {
1787                         *resetp = 1;
1788                         return -EBUSY;
1789                 }
1790
1791                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1792                 if (tg3_wait_macro_done(tp)) {
1793                         *resetp = 1;
1794                         return -EBUSY;
1795                 }
1796
1797                 for (i = 0; i < 6; i += 2) {
1798                         u32 low, high;
1799
1800                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1801                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1802                             tg3_wait_macro_done(tp)) {
1803                                 *resetp = 1;
1804                                 return -EBUSY;
1805                         }
1806                         low &= 0x7fff;
1807                         high &= 0x000f;
1808                         if (low != test_pat[chan][i] ||
1809                             high != test_pat[chan][i+1]) {
1810                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1811                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1812                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1813
1814                                 return -EBUSY;
1815                         }
1816                 }
1817         }
1818
1819         return 0;
1820 }
1821
1822 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1823 {
1824         int chan;
1825
1826         for (chan = 0; chan < 4; chan++) {
1827                 int i;
1828
1829                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1830                              (chan * 0x2000) | 0x0200);
1831                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1832                 for (i = 0; i < 6; i++)
1833                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1834                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1835                 if (tg3_wait_macro_done(tp))
1836                         return -EBUSY;
1837         }
1838
1839         return 0;
1840 }
1841
1842 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1843 {
1844         u32 reg32, phy9_orig;
1845         int retries, do_phy_reset, err;
1846
1847         retries = 10;
1848         do_phy_reset = 1;
1849         do {
1850                 if (do_phy_reset) {
1851                         err = tg3_bmcr_reset(tp);
1852                         if (err)
1853                                 return err;
1854                         do_phy_reset = 0;
1855                 }
1856
1857                 /* Disable transmitter and interrupt.  */
1858                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1859                         continue;
1860
1861                 reg32 |= 0x3000;
1862                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1863
1864                 /* Set full-duplex, 1000 mbps.  */
1865                 tg3_writephy(tp, MII_BMCR,
1866                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1867
1868                 /* Set to master mode.  */
1869                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1870                         continue;
1871
1872                 tg3_writephy(tp, MII_TG3_CTRL,
1873                              (MII_TG3_CTRL_AS_MASTER |
1874                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1875
1876                 /* Enable SM_DSP_CLOCK and 6dB.  */
1877                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1878
1879                 /* Block the PHY control access.  */
1880                 tg3_phydsp_write(tp, 0x8005, 0x0800);
1881
1882                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1883                 if (!err)
1884                         break;
1885         } while (--retries);
1886
1887         err = tg3_phy_reset_chanpat(tp);
1888         if (err)
1889                 return err;
1890
1891         tg3_phydsp_write(tp, 0x8005, 0x0000);
1892
1893         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1894         tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1895
1896         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1897             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1898                 /* Set Extended packet length bit for jumbo frames */
1899                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1900         } else {
1901                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1902         }
1903
1904         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1905
1906         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1907                 reg32 &= ~0x3000;
1908                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1909         } else if (!err)
1910                 err = -EBUSY;
1911
1912         return err;
1913 }
1914
1915 /* This will reset the tigon3 PHY if there is no valid
1916  * link unless the FORCE argument is non-zero.
1917  */
1918 static int tg3_phy_reset(struct tg3 *tp)
1919 {
1920         u32 cpmuctrl;
1921         u32 phy_status;
1922         int err;
1923
1924         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1925                 u32 val;
1926
1927                 val = tr32(GRC_MISC_CFG);
1928                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1929                 udelay(40);
1930         }
1931         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1932         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1933         if (err != 0)
1934                 return -EBUSY;
1935
1936         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1937                 netif_carrier_off(tp->dev);
1938                 tg3_link_report(tp);
1939         }
1940
1941         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1942             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1943             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1944                 err = tg3_phy_reset_5703_4_5(tp);
1945                 if (err)
1946                         return err;
1947                 goto out;
1948         }
1949
1950         cpmuctrl = 0;
1951         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1952             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1953                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1954                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1955                         tw32(TG3_CPMU_CTRL,
1956                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1957         }
1958
1959         err = tg3_bmcr_reset(tp);
1960         if (err)
1961                 return err;
1962
1963         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1964                 u32 phy;
1965
1966                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1967                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1968
1969                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1970         }
1971
1972         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1973             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1974                 u32 val;
1975
1976                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1977                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1978                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1979                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1980                         udelay(40);
1981                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1982                 }
1983         }
1984
1985         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1986              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1987             (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
1988                 return 0;
1989
1990         tg3_phy_apply_otp(tp);
1991
1992         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
1993                 tg3_phy_toggle_apd(tp, true);
1994         else
1995                 tg3_phy_toggle_apd(tp, false);
1996
1997 out:
1998         if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) {
1999                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2000                 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2001                 tg3_phydsp_write(tp, 0x000a, 0x0323);
2002                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2003         }
2004         if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2005                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2006                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2007         }
2008         if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2009                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2010                 tg3_phydsp_write(tp, 0x000a, 0x310b);
2011                 tg3_phydsp_write(tp, 0x201f, 0x9506);
2012                 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2013                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2014         } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2015                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2016                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2017                 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2018                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2019                         tg3_writephy(tp, MII_TG3_TEST1,
2020                                      MII_TG3_TEST1_TRIM_EN | 0x4);
2021                 } else
2022                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2023                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2024         }
2025         /* Set Extended packet length bit (bit 14) on all chips that */
2026         /* support jumbo frames */
2027         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2028                 /* Cannot do read-modify-write on 5401 */
2029                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2030         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2031                 u32 phy_reg;
2032
2033                 /* Set bit 14 with read-modify-write to preserve other bits */
2034                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2035                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
2036                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
2037         }
2038
2039         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2040          * jumbo frames transmission.
2041          */
2042         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2043                 u32 phy_reg;
2044
2045                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
2046                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2047                                      phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2048         }
2049
2050         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2051                 /* adjust output voltage */
2052                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2053         }
2054
2055         tg3_phy_toggle_automdix(tp, 1);
2056         tg3_phy_set_wirespeed(tp);
2057         return 0;
2058 }
2059
2060 static void tg3_frob_aux_power(struct tg3 *tp)
2061 {
2062         struct tg3 *tp_peer = tp;
2063
2064         /* The GPIOs do something completely different on 57765. */
2065         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2066             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2067             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2068                 return;
2069
2070         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2071             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2072             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2073                 struct net_device *dev_peer;
2074
2075                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2076                 /* remove_one() may have been run on the peer. */
2077                 if (!dev_peer)
2078                         tp_peer = tp;
2079                 else
2080                         tp_peer = netdev_priv(dev_peer);
2081         }
2082
2083         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2084             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2085             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2086             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2087                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2088                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2089                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2090                                     (GRC_LCLCTRL_GPIO_OE0 |
2091                                      GRC_LCLCTRL_GPIO_OE1 |
2092                                      GRC_LCLCTRL_GPIO_OE2 |
2093                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2094                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2095                                     100);
2096                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2097                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2098                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2099                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2100                                              GRC_LCLCTRL_GPIO_OE1 |
2101                                              GRC_LCLCTRL_GPIO_OE2 |
2102                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2103                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2104                                              tp->grc_local_ctrl;
2105                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2106
2107                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2108                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2109
2110                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2111                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2112                 } else {
2113                         u32 no_gpio2;
2114                         u32 grc_local_ctrl = 0;
2115
2116                         if (tp_peer != tp &&
2117                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2118                                 return;
2119
2120                         /* Workaround to prevent overdrawing Amps. */
2121                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2122                             ASIC_REV_5714) {
2123                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2124                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2125                                             grc_local_ctrl, 100);
2126                         }
2127
2128                         /* On 5753 and variants, GPIO2 cannot be used. */
2129                         no_gpio2 = tp->nic_sram_data_cfg &
2130                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2131
2132                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2133                                          GRC_LCLCTRL_GPIO_OE1 |
2134                                          GRC_LCLCTRL_GPIO_OE2 |
2135                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2136                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2137                         if (no_gpio2) {
2138                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2139                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2140                         }
2141                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2142                                                     grc_local_ctrl, 100);
2143
2144                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2145
2146                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2147                                                     grc_local_ctrl, 100);
2148
2149                         if (!no_gpio2) {
2150                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2151                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2152                                             grc_local_ctrl, 100);
2153                         }
2154                 }
2155         } else {
2156                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2157                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2158                         if (tp_peer != tp &&
2159                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2160                                 return;
2161
2162                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2163                                     (GRC_LCLCTRL_GPIO_OE1 |
2164                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2165
2166                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2167                                     GRC_LCLCTRL_GPIO_OE1, 100);
2168
2169                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2170                                     (GRC_LCLCTRL_GPIO_OE1 |
2171                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2172                 }
2173         }
2174 }
2175
2176 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2177 {
2178         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2179                 return 1;
2180         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2181                 if (speed != SPEED_10)
2182                         return 1;
2183         } else if (speed == SPEED_10)
2184                 return 1;
2185
2186         return 0;
2187 }
2188
2189 static int tg3_setup_phy(struct tg3 *, int);
2190
2191 #define RESET_KIND_SHUTDOWN     0
2192 #define RESET_KIND_INIT         1
2193 #define RESET_KIND_SUSPEND      2
2194
2195 static void tg3_write_sig_post_reset(struct tg3 *, int);
2196 static int tg3_halt_cpu(struct tg3 *, u32);
2197
2198 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2199 {
2200         u32 val;
2201
2202         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2203                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2204                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2205                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2206
2207                         sg_dig_ctrl |=
2208                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2209                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2210                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2211                 }
2212                 return;
2213         }
2214
2215         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2216                 tg3_bmcr_reset(tp);
2217                 val = tr32(GRC_MISC_CFG);
2218                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2219                 udelay(40);
2220                 return;
2221         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2222                 u32 phytest;
2223                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2224                         u32 phy;
2225
2226                         tg3_writephy(tp, MII_ADVERTISE, 0);
2227                         tg3_writephy(tp, MII_BMCR,
2228                                      BMCR_ANENABLE | BMCR_ANRESTART);
2229
2230                         tg3_writephy(tp, MII_TG3_FET_TEST,
2231                                      phytest | MII_TG3_FET_SHADOW_EN);
2232                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2233                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2234                                 tg3_writephy(tp,
2235                                              MII_TG3_FET_SHDW_AUXMODE4,
2236                                              phy);
2237                         }
2238                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2239                 }
2240                 return;
2241         } else if (do_low_power) {
2242                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2243                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2244
2245                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2246                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2247                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2248                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2249                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2250         }
2251
2252         /* The PHY should not be powered down on some chips because
2253          * of bugs.
2254          */
2255         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2256             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2257             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2258              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2259                 return;
2260
2261         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2262             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2263                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2264                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2265                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2266                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2267         }
2268
2269         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2270 }
2271
2272 /* tp->lock is held. */
2273 static int tg3_nvram_lock(struct tg3 *tp)
2274 {
2275         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2276                 int i;
2277
2278                 if (tp->nvram_lock_cnt == 0) {
2279                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2280                         for (i = 0; i < 8000; i++) {
2281                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2282                                         break;
2283                                 udelay(20);
2284                         }
2285                         if (i == 8000) {
2286                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2287                                 return -ENODEV;
2288                         }
2289                 }
2290                 tp->nvram_lock_cnt++;
2291         }
2292         return 0;
2293 }
2294
2295 /* tp->lock is held. */
2296 static void tg3_nvram_unlock(struct tg3 *tp)
2297 {
2298         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2299                 if (tp->nvram_lock_cnt > 0)
2300                         tp->nvram_lock_cnt--;
2301                 if (tp->nvram_lock_cnt == 0)
2302                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2303         }
2304 }
2305
2306 /* tp->lock is held. */
2307 static void tg3_enable_nvram_access(struct tg3 *tp)
2308 {
2309         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2310             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2311                 u32 nvaccess = tr32(NVRAM_ACCESS);
2312
2313                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2314         }
2315 }
2316
2317 /* tp->lock is held. */
2318 static void tg3_disable_nvram_access(struct tg3 *tp)
2319 {
2320         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2321             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2322                 u32 nvaccess = tr32(NVRAM_ACCESS);
2323
2324                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2325         }
2326 }
2327
2328 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2329                                         u32 offset, u32 *val)
2330 {
2331         u32 tmp;
2332         int i;
2333
2334         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2335                 return -EINVAL;
2336
2337         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2338                                         EEPROM_ADDR_DEVID_MASK |
2339                                         EEPROM_ADDR_READ);
2340         tw32(GRC_EEPROM_ADDR,
2341              tmp |
2342              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2343              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2344               EEPROM_ADDR_ADDR_MASK) |
2345              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2346
2347         for (i = 0; i < 1000; i++) {
2348                 tmp = tr32(GRC_EEPROM_ADDR);
2349
2350                 if (tmp & EEPROM_ADDR_COMPLETE)
2351                         break;
2352                 msleep(1);
2353         }
2354         if (!(tmp & EEPROM_ADDR_COMPLETE))
2355                 return -EBUSY;
2356
2357         tmp = tr32(GRC_EEPROM_DATA);
2358
2359         /*
2360          * The data will always be opposite the native endian
2361          * format.  Perform a blind byteswap to compensate.
2362          */
2363         *val = swab32(tmp);
2364
2365         return 0;
2366 }
2367
2368 #define NVRAM_CMD_TIMEOUT 10000
2369
2370 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2371 {
2372         int i;
2373
2374         tw32(NVRAM_CMD, nvram_cmd);
2375         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2376                 udelay(10);
2377                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2378                         udelay(10);
2379                         break;
2380                 }
2381         }
2382
2383         if (i == NVRAM_CMD_TIMEOUT)
2384                 return -EBUSY;
2385
2386         return 0;
2387 }
2388
2389 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2390 {
2391         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2392             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2393             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2394            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2395             (tp->nvram_jedecnum == JEDEC_ATMEL))
2396
2397                 addr = ((addr / tp->nvram_pagesize) <<
2398                         ATMEL_AT45DB0X1B_PAGE_POS) +
2399                        (addr % tp->nvram_pagesize);
2400
2401         return addr;
2402 }
2403
2404 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2405 {
2406         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2407             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2408             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2409            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2410             (tp->nvram_jedecnum == JEDEC_ATMEL))
2411
2412                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2413                         tp->nvram_pagesize) +
2414                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2415
2416         return addr;
2417 }
2418
2419 /* NOTE: Data read in from NVRAM is byteswapped according to
2420  * the byteswapping settings for all other register accesses.
2421  * tg3 devices are BE devices, so on a BE machine, the data
2422  * returned will be exactly as it is seen in NVRAM.  On a LE
2423  * machine, the 32-bit value will be byteswapped.
2424  */
2425 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2426 {
2427         int ret;
2428
2429         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2430                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2431
2432         offset = tg3_nvram_phys_addr(tp, offset);
2433
2434         if (offset > NVRAM_ADDR_MSK)
2435                 return -EINVAL;
2436
2437         ret = tg3_nvram_lock(tp);
2438         if (ret)
2439                 return ret;
2440
2441         tg3_enable_nvram_access(tp);
2442
2443         tw32(NVRAM_ADDR, offset);
2444         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2445                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2446
2447         if (ret == 0)
2448                 *val = tr32(NVRAM_RDDATA);
2449
2450         tg3_disable_nvram_access(tp);
2451
2452         tg3_nvram_unlock(tp);
2453
2454         return ret;
2455 }
2456
2457 /* Ensures NVRAM data is in bytestream format. */
2458 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2459 {
2460         u32 v;
2461         int res = tg3_nvram_read(tp, offset, &v);
2462         if (!res)
2463                 *val = cpu_to_be32(v);
2464         return res;
2465 }
2466
2467 /* tp->lock is held. */
2468 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2469 {
2470         u32 addr_high, addr_low;
2471         int i;
2472
2473         addr_high = ((tp->dev->dev_addr[0] << 8) |
2474                      tp->dev->dev_addr[1]);
2475         addr_low = ((tp->dev->dev_addr[2] << 24) |
2476                     (tp->dev->dev_addr[3] << 16) |
2477                     (tp->dev->dev_addr[4] <<  8) |
2478                     (tp->dev->dev_addr[5] <<  0));
2479         for (i = 0; i < 4; i++) {
2480                 if (i == 1 && skip_mac_1)
2481                         continue;
2482                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2483                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2484         }
2485
2486         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2487             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2488                 for (i = 0; i < 12; i++) {
2489                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2490                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2491                 }
2492         }
2493
2494         addr_high = (tp->dev->dev_addr[0] +
2495                      tp->dev->dev_addr[1] +
2496                      tp->dev->dev_addr[2] +
2497                      tp->dev->dev_addr[3] +
2498                      tp->dev->dev_addr[4] +
2499                      tp->dev->dev_addr[5]) &
2500                 TX_BACKOFF_SEED_MASK;
2501         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2502 }
2503
2504 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2505 {
2506         u32 misc_host_ctrl;
2507         bool device_should_wake, do_low_power;
2508
2509         /* Make sure register accesses (indirect or otherwise)
2510          * will function correctly.
2511          */
2512         pci_write_config_dword(tp->pdev,
2513                                TG3PCI_MISC_HOST_CTRL,
2514                                tp->misc_host_ctrl);
2515
2516         switch (state) {
2517         case PCI_D0:
2518                 pci_enable_wake(tp->pdev, state, false);
2519                 pci_set_power_state(tp->pdev, PCI_D0);
2520
2521                 /* Switch out of Vaux if it is a NIC */
2522                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2523                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2524
2525                 return 0;
2526
2527         case PCI_D1:
2528         case PCI_D2:
2529         case PCI_D3hot:
2530                 break;
2531
2532         default:
2533                 netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
2534                            state);
2535                 return -EINVAL;
2536         }
2537
2538         /* Restore the CLKREQ setting. */
2539         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2540                 u16 lnkctl;
2541
2542                 pci_read_config_word(tp->pdev,
2543                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2544                                      &lnkctl);
2545                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2546                 pci_write_config_word(tp->pdev,
2547                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2548                                       lnkctl);
2549         }
2550
2551         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2552         tw32(TG3PCI_MISC_HOST_CTRL,
2553              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2554
2555         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2556                              device_may_wakeup(&tp->pdev->dev) &&
2557                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2558
2559         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2560                 do_low_power = false;
2561                 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
2562                     !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2563                         struct phy_device *phydev;
2564                         u32 phyid, advertising;
2565
2566                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2567
2568                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2569
2570                         tp->link_config.orig_speed = phydev->speed;
2571                         tp->link_config.orig_duplex = phydev->duplex;
2572                         tp->link_config.orig_autoneg = phydev->autoneg;
2573                         tp->link_config.orig_advertising = phydev->advertising;
2574
2575                         advertising = ADVERTISED_TP |
2576                                       ADVERTISED_Pause |
2577                                       ADVERTISED_Autoneg |
2578                                       ADVERTISED_10baseT_Half;
2579
2580                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2581                             device_should_wake) {
2582                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2583                                         advertising |=
2584                                                 ADVERTISED_100baseT_Half |
2585                                                 ADVERTISED_100baseT_Full |
2586                                                 ADVERTISED_10baseT_Full;
2587                                 else
2588                                         advertising |= ADVERTISED_10baseT_Full;
2589                         }
2590
2591                         phydev->advertising = advertising;
2592
2593                         phy_start_aneg(phydev);
2594
2595                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2596                         if (phyid != PHY_ID_BCMAC131) {
2597                                 phyid &= PHY_BCM_OUI_MASK;
2598                                 if (phyid == PHY_BCM_OUI_1 ||
2599                                     phyid == PHY_BCM_OUI_2 ||
2600                                     phyid == PHY_BCM_OUI_3)
2601                                         do_low_power = true;
2602                         }
2603                 }
2604         } else {
2605                 do_low_power = true;
2606
2607                 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2608                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2609                         tp->link_config.orig_speed = tp->link_config.speed;
2610                         tp->link_config.orig_duplex = tp->link_config.duplex;
2611                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2612                 }
2613
2614                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
2615                         tp->link_config.speed = SPEED_10;
2616                         tp->link_config.duplex = DUPLEX_HALF;
2617                         tp->link_config.autoneg = AUTONEG_ENABLE;
2618                         tg3_setup_phy(tp, 0);
2619                 }
2620         }
2621
2622         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2623                 u32 val;
2624
2625                 val = tr32(GRC_VCPU_EXT_CTRL);
2626                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2627         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2628                 int i;
2629                 u32 val;
2630
2631                 for (i = 0; i < 200; i++) {
2632                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2633                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2634                                 break;
2635                         msleep(1);
2636                 }
2637         }
2638         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2639                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2640                                                      WOL_DRV_STATE_SHUTDOWN |
2641                                                      WOL_DRV_WOL |
2642                                                      WOL_SET_MAGIC_PKT);
2643
2644         if (device_should_wake) {
2645                 u32 mac_mode;
2646
2647                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
2648                         if (do_low_power) {
2649                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2650                                 udelay(40);
2651                         }
2652
2653                         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
2654                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2655                         else
2656                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2657
2658                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2659                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2660                             ASIC_REV_5700) {
2661                                 u32 speed = (tp->tg3_flags &
2662                                              TG3_FLAG_WOL_SPEED_100MB) ?
2663                                              SPEED_100 : SPEED_10;
2664                                 if (tg3_5700_link_polarity(tp, speed))
2665                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2666                                 else
2667                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2668                         }
2669                 } else {
2670                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2671                 }
2672
2673                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2674                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2675
2676                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2677                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2678                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2679                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2680                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2681                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2682
2683                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2684                         mac_mode |= tp->mac_mode &
2685                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2686                         if (mac_mode & MAC_MODE_APE_TX_EN)
2687                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2688                 }
2689
2690                 tw32_f(MAC_MODE, mac_mode);
2691                 udelay(100);
2692
2693                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2694                 udelay(10);
2695         }
2696
2697         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2698             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2699              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2700                 u32 base_val;
2701
2702                 base_val = tp->pci_clock_ctrl;
2703                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2704                              CLOCK_CTRL_TXCLK_DISABLE);
2705
2706                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2707                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2708         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2709                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2710                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2711                 /* do nothing */
2712         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2713                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2714                 u32 newbits1, newbits2;
2715
2716                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2717                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2718                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2719                                     CLOCK_CTRL_TXCLK_DISABLE |
2720                                     CLOCK_CTRL_ALTCLK);
2721                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2722                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2723                         newbits1 = CLOCK_CTRL_625_CORE;
2724                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2725                 } else {
2726                         newbits1 = CLOCK_CTRL_ALTCLK;
2727                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2728                 }
2729
2730                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2731                             40);
2732
2733                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2734                             40);
2735
2736                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2737                         u32 newbits3;
2738
2739                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2740                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2741                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2742                                             CLOCK_CTRL_TXCLK_DISABLE |
2743                                             CLOCK_CTRL_44MHZ_CORE);
2744                         } else {
2745                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2746                         }
2747
2748                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2749                                     tp->pci_clock_ctrl | newbits3, 40);
2750                 }
2751         }
2752
2753         if (!(device_should_wake) &&
2754             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2755                 tg3_power_down_phy(tp, do_low_power);
2756
2757         tg3_frob_aux_power(tp);
2758
2759         /* Workaround for unstable PLL clock */
2760         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2761             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2762                 u32 val = tr32(0x7d00);
2763
2764                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2765                 tw32(0x7d00, val);
2766                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2767                         int err;
2768
2769                         err = tg3_nvram_lock(tp);
2770                         tg3_halt_cpu(tp, RX_CPU_BASE);
2771                         if (!err)
2772                                 tg3_nvram_unlock(tp);
2773                 }
2774         }
2775
2776         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2777
2778         if (device_should_wake)
2779                 pci_enable_wake(tp->pdev, state, true);
2780
2781         /* Finally, set the new power state. */
2782         pci_set_power_state(tp->pdev, state);
2783
2784         return 0;
2785 }
2786
2787 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2788 {
2789         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2790         case MII_TG3_AUX_STAT_10HALF:
2791                 *speed = SPEED_10;
2792                 *duplex = DUPLEX_HALF;
2793                 break;
2794
2795         case MII_TG3_AUX_STAT_10FULL:
2796                 *speed = SPEED_10;
2797                 *duplex = DUPLEX_FULL;
2798                 break;
2799
2800         case MII_TG3_AUX_STAT_100HALF:
2801                 *speed = SPEED_100;
2802                 *duplex = DUPLEX_HALF;
2803                 break;
2804
2805         case MII_TG3_AUX_STAT_100FULL:
2806                 *speed = SPEED_100;
2807                 *duplex = DUPLEX_FULL;
2808                 break;
2809
2810         case MII_TG3_AUX_STAT_1000HALF:
2811                 *speed = SPEED_1000;
2812                 *duplex = DUPLEX_HALF;
2813                 break;
2814
2815         case MII_TG3_AUX_STAT_1000FULL:
2816                 *speed = SPEED_1000;
2817                 *duplex = DUPLEX_FULL;
2818                 break;
2819
2820         default:
2821                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2822                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2823                                  SPEED_10;
2824                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2825                                   DUPLEX_HALF;
2826                         break;
2827                 }
2828                 *speed = SPEED_INVALID;
2829                 *duplex = DUPLEX_INVALID;
2830                 break;
2831         }
2832 }
2833
2834 static void tg3_phy_copper_begin(struct tg3 *tp)
2835 {
2836         u32 new_adv;
2837         int i;
2838
2839         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2840                 /* Entering low power mode.  Disable gigabit and
2841                  * 100baseT advertisements.
2842                  */
2843                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2844
2845                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2846                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2847                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2848                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2849
2850                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2851         } else if (tp->link_config.speed == SPEED_INVALID) {
2852                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
2853                         tp->link_config.advertising &=
2854                                 ~(ADVERTISED_1000baseT_Half |
2855                                   ADVERTISED_1000baseT_Full);
2856
2857                 new_adv = ADVERTISE_CSMA;
2858                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2859                         new_adv |= ADVERTISE_10HALF;
2860                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2861                         new_adv |= ADVERTISE_10FULL;
2862                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2863                         new_adv |= ADVERTISE_100HALF;
2864                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2865                         new_adv |= ADVERTISE_100FULL;
2866
2867                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2868
2869                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2870
2871                 if (tp->link_config.advertising &
2872                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2873                         new_adv = 0;
2874                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2875                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2876                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2877                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2878                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) &&
2879                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2880                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2881                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2882                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2883                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2884                 } else {
2885                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2886                 }
2887         } else {
2888                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2889                 new_adv |= ADVERTISE_CSMA;
2890
2891                 /* Asking for a specific link mode. */
2892                 if (tp->link_config.speed == SPEED_1000) {
2893                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2894
2895                         if (tp->link_config.duplex == DUPLEX_FULL)
2896                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2897                         else
2898                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2899                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2900                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2901                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2902                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2903                 } else {
2904                         if (tp->link_config.speed == SPEED_100) {
2905                                 if (tp->link_config.duplex == DUPLEX_FULL)
2906                                         new_adv |= ADVERTISE_100FULL;
2907                                 else
2908                                         new_adv |= ADVERTISE_100HALF;
2909                         } else {
2910                                 if (tp->link_config.duplex == DUPLEX_FULL)
2911                                         new_adv |= ADVERTISE_10FULL;
2912                                 else
2913                                         new_adv |= ADVERTISE_10HALF;
2914                         }
2915                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2916
2917                         new_adv = 0;
2918                 }
2919
2920                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2921         }
2922
2923         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2924             tp->link_config.speed != SPEED_INVALID) {
2925                 u32 bmcr, orig_bmcr;
2926
2927                 tp->link_config.active_speed = tp->link_config.speed;
2928                 tp->link_config.active_duplex = tp->link_config.duplex;
2929
2930                 bmcr = 0;
2931                 switch (tp->link_config.speed) {
2932                 default:
2933                 case SPEED_10:
2934                         break;
2935
2936                 case SPEED_100:
2937                         bmcr |= BMCR_SPEED100;
2938                         break;
2939
2940                 case SPEED_1000:
2941                         bmcr |= TG3_BMCR_SPEED1000;
2942                         break;
2943                 }
2944
2945                 if (tp->link_config.duplex == DUPLEX_FULL)
2946                         bmcr |= BMCR_FULLDPLX;
2947
2948                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2949                     (bmcr != orig_bmcr)) {
2950                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2951                         for (i = 0; i < 1500; i++) {
2952                                 u32 tmp;
2953
2954                                 udelay(10);
2955                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2956                                     tg3_readphy(tp, MII_BMSR, &tmp))
2957                                         continue;
2958                                 if (!(tmp & BMSR_LSTATUS)) {
2959                                         udelay(40);
2960                                         break;
2961                                 }
2962                         }
2963                         tg3_writephy(tp, MII_BMCR, bmcr);
2964                         udelay(40);
2965                 }
2966         } else {
2967                 tg3_writephy(tp, MII_BMCR,
2968                              BMCR_ANENABLE | BMCR_ANRESTART);
2969         }
2970 }
2971
2972 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2973 {
2974         int err;
2975
2976         /* Turn off tap power management. */
2977         /* Set Extended packet length bit */
2978         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2979
2980         err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
2981         err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
2982         err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
2983         err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
2984         err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
2985
2986         udelay(40);
2987
2988         return err;
2989 }
2990
2991 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2992 {
2993         u32 adv_reg, all_mask = 0;
2994
2995         if (mask & ADVERTISED_10baseT_Half)
2996                 all_mask |= ADVERTISE_10HALF;
2997         if (mask & ADVERTISED_10baseT_Full)
2998                 all_mask |= ADVERTISE_10FULL;
2999         if (mask & ADVERTISED_100baseT_Half)
3000                 all_mask |= ADVERTISE_100HALF;
3001         if (mask & ADVERTISED_100baseT_Full)
3002                 all_mask |= ADVERTISE_100FULL;
3003
3004         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3005                 return 0;
3006
3007         if ((adv_reg & all_mask) != all_mask)
3008                 return 0;
3009         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3010                 u32 tg3_ctrl;
3011
3012                 all_mask = 0;
3013                 if (mask & ADVERTISED_1000baseT_Half)
3014                         all_mask |= ADVERTISE_1000HALF;
3015                 if (mask & ADVERTISED_1000baseT_Full)
3016                         all_mask |= ADVERTISE_1000FULL;
3017
3018                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3019                         return 0;
3020
3021                 if ((tg3_ctrl & all_mask) != all_mask)
3022                         return 0;
3023         }
3024         return 1;
3025 }
3026
3027 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3028 {
3029         u32 curadv, reqadv;
3030
3031         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3032                 return 1;
3033
3034         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3035         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3036
3037         if (tp->link_config.active_duplex == DUPLEX_FULL) {
3038                 if (curadv != reqadv)
3039                         return 0;
3040
3041                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3042                         tg3_readphy(tp, MII_LPA, rmtadv);
3043         } else {
3044                 /* Reprogram the advertisement register, even if it
3045                  * does not affect the current link.  If the link
3046                  * gets renegotiated in the future, we can save an
3047                  * additional renegotiation cycle by advertising
3048                  * it correctly in the first place.
3049                  */
3050                 if (curadv != reqadv) {
3051                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3052                                      ADVERTISE_PAUSE_ASYM);
3053                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3054                 }
3055         }
3056
3057         return 1;
3058 }
3059
3060 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3061 {
3062         int current_link_up;
3063         u32 bmsr, dummy;
3064         u32 lcl_adv, rmt_adv;
3065         u16 current_speed;
3066         u8 current_duplex;
3067         int i, err;
3068
3069         tw32(MAC_EVENT, 0);
3070
3071         tw32_f(MAC_STATUS,
3072              (MAC_STATUS_SYNC_CHANGED |
3073               MAC_STATUS_CFG_CHANGED |
3074               MAC_STATUS_MI_COMPLETION |
3075               MAC_STATUS_LNKSTATE_CHANGED));
3076         udelay(40);
3077
3078         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3079                 tw32_f(MAC_MI_MODE,
3080                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3081                 udelay(80);
3082         }
3083
3084         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3085
3086         /* Some third-party PHYs need to be reset on link going
3087          * down.
3088          */
3089         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3090              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3091              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3092             netif_carrier_ok(tp->dev)) {
3093                 tg3_readphy(tp, MII_BMSR, &bmsr);
3094                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3095                     !(bmsr & BMSR_LSTATUS))
3096                         force_reset = 1;
3097         }
3098         if (force_reset)
3099                 tg3_phy_reset(tp);
3100
3101         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3102                 tg3_readphy(tp, MII_BMSR, &bmsr);
3103                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3104                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3105                         bmsr = 0;
3106
3107                 if (!(bmsr & BMSR_LSTATUS)) {
3108                         err = tg3_init_5401phy_dsp(tp);
3109                         if (err)
3110                                 return err;
3111
3112                         tg3_readphy(tp, MII_BMSR, &bmsr);
3113                         for (i = 0; i < 1000; i++) {
3114                                 udelay(10);
3115                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3116                                     (bmsr & BMSR_LSTATUS)) {
3117                                         udelay(40);
3118                                         break;
3119                                 }
3120                         }
3121
3122                         if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3123                             TG3_PHY_REV_BCM5401_B0 &&
3124                             !(bmsr & BMSR_LSTATUS) &&
3125                             tp->link_config.active_speed == SPEED_1000) {
3126                                 err = tg3_phy_reset(tp);
3127                                 if (!err)
3128                                         err = tg3_init_5401phy_dsp(tp);
3129                                 if (err)
3130                                         return err;
3131                         }
3132                 }
3133         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3134                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3135                 /* 5701 {A0,B0} CRC bug workaround */
3136                 tg3_writephy(tp, 0x15, 0x0a75);
3137                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3138                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3139                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3140         }
3141
3142         /* Clear pending interrupts... */
3143         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3144         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3145
3146         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3147                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3148         else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3149                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3150
3151         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3152             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3153                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3154                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3155                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3156                 else
3157                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3158         }
3159
3160         current_link_up = 0;
3161         current_speed = SPEED_INVALID;
3162         current_duplex = DUPLEX_INVALID;
3163
3164         if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3165                 u32 val;
3166
3167                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3168                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3169                 if (!(val & (1 << 10))) {
3170                         val |= (1 << 10);
3171                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3172                         goto relink;
3173                 }
3174         }
3175
3176         bmsr = 0;
3177         for (i = 0; i < 100; i++) {
3178                 tg3_readphy(tp, MII_BMSR, &bmsr);
3179                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3180                     (bmsr & BMSR_LSTATUS))
3181                         break;
3182                 udelay(40);
3183         }
3184
3185         if (bmsr & BMSR_LSTATUS) {
3186                 u32 aux_stat, bmcr;
3187
3188                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3189                 for (i = 0; i < 2000; i++) {
3190                         udelay(10);
3191                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3192                             aux_stat)
3193                                 break;
3194                 }
3195
3196                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3197                                              &current_speed,
3198                                              &current_duplex);
3199
3200                 bmcr = 0;
3201                 for (i = 0; i < 200; i++) {
3202                         tg3_readphy(tp, MII_BMCR, &bmcr);
3203                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3204                                 continue;
3205                         if (bmcr && bmcr != 0x7fff)
3206                                 break;
3207                         udelay(10);
3208                 }
3209
3210                 lcl_adv = 0;
3211                 rmt_adv = 0;
3212
3213                 tp->link_config.active_speed = current_speed;
3214                 tp->link_config.active_duplex = current_duplex;
3215
3216                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3217                         if ((bmcr & BMCR_ANENABLE) &&
3218                             tg3_copper_is_advertising_all(tp,
3219                                                 tp->link_config.advertising)) {
3220                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3221                                                                   &rmt_adv))
3222                                         current_link_up = 1;
3223                         }
3224                 } else {
3225                         if (!(bmcr & BMCR_ANENABLE) &&
3226                             tp->link_config.speed == current_speed &&
3227                             tp->link_config.duplex == current_duplex &&
3228                             tp->link_config.flowctrl ==
3229                             tp->link_config.active_flowctrl) {
3230                                 current_link_up = 1;
3231                         }
3232                 }
3233
3234                 if (current_link_up == 1 &&
3235                     tp->link_config.active_duplex == DUPLEX_FULL)
3236                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3237         }
3238
3239 relink:
3240         if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3241                 u32 tmp;
3242
3243                 tg3_phy_copper_begin(tp);
3244
3245                 tg3_readphy(tp, MII_BMSR, &tmp);
3246                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3247                     (tmp & BMSR_LSTATUS))
3248                         current_link_up = 1;
3249         }
3250
3251         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3252         if (current_link_up == 1) {
3253                 if (tp->link_config.active_speed == SPEED_100 ||
3254                     tp->link_config.active_speed == SPEED_10)
3255                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3256                 else
3257                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3258         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
3259                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3260         else
3261                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3262
3263         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3264         if (tp->link_config.active_duplex == DUPLEX_HALF)
3265                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3266
3267         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3268                 if (current_link_up == 1 &&
3269                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3270                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3271                 else
3272                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3273         }
3274
3275         /* ??? Without this setting Netgear GA302T PHY does not
3276          * ??? send/receive packets...
3277          */
3278         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3279             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3280                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3281                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3282                 udelay(80);
3283         }
3284
3285         tw32_f(MAC_MODE, tp->mac_mode);
3286         udelay(40);
3287
3288         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3289                 /* Polled via timer. */
3290                 tw32_f(MAC_EVENT, 0);
3291         } else {
3292                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3293         }
3294         udelay(40);
3295
3296         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3297             current_link_up == 1 &&
3298             tp->link_config.active_speed == SPEED_1000 &&
3299             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3300              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3301                 udelay(120);
3302                 tw32_f(MAC_STATUS,
3303                      (MAC_STATUS_SYNC_CHANGED |
3304                       MAC_STATUS_CFG_CHANGED));
3305                 udelay(40);
3306                 tg3_write_mem(tp,
3307                               NIC_SRAM_FIRMWARE_MBOX,
3308                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3309         }
3310
3311         /* Prevent send BD corruption. */
3312         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3313                 u16 oldlnkctl, newlnkctl;
3314
3315                 pci_read_config_word(tp->pdev,
3316                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3317                                      &oldlnkctl);
3318                 if (tp->link_config.active_speed == SPEED_100 ||
3319                     tp->link_config.active_speed == SPEED_10)
3320                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3321                 else
3322                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3323                 if (newlnkctl != oldlnkctl)
3324                         pci_write_config_word(tp->pdev,
3325                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3326                                               newlnkctl);
3327         }
3328
3329         if (current_link_up != netif_carrier_ok(tp->dev)) {
3330                 if (current_link_up)
3331                         netif_carrier_on(tp->dev);
3332                 else
3333                         netif_carrier_off(tp->dev);
3334                 tg3_link_report(tp);
3335         }
3336
3337         return 0;
3338 }
3339
3340 struct tg3_fiber_aneginfo {
3341         int state;
3342 #define ANEG_STATE_UNKNOWN              0
3343 #define ANEG_STATE_AN_ENABLE            1
3344 #define ANEG_STATE_RESTART_INIT         2
3345 #define ANEG_STATE_RESTART              3
3346 #define ANEG_STATE_DISABLE_LINK_OK      4
3347 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3348 #define ANEG_STATE_ABILITY_DETECT       6
3349 #define ANEG_STATE_ACK_DETECT_INIT      7
3350 #define ANEG_STATE_ACK_DETECT           8
3351 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3352 #define ANEG_STATE_COMPLETE_ACK         10
3353 #define ANEG_STATE_IDLE_DETECT_INIT     11
3354 #define ANEG_STATE_IDLE_DETECT          12
3355 #define ANEG_STATE_LINK_OK              13
3356 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3357 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3358
3359         u32 flags;
3360 #define MR_AN_ENABLE            0x00000001
3361 #define MR_RESTART_AN           0x00000002
3362 #define MR_AN_COMPLETE          0x00000004
3363 #define MR_PAGE_RX              0x00000008
3364 #define MR_NP_LOADED            0x00000010
3365 #define MR_TOGGLE_TX            0x00000020
3366 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3367 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3368 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3369 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3370 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3371 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3372 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3373 #define MR_TOGGLE_RX            0x00002000
3374 #define MR_NP_RX                0x00004000
3375
3376 #define MR_LINK_OK              0x80000000
3377
3378         unsigned long link_time, cur_time;
3379
3380         u32 ability_match_cfg;
3381         int ability_match_count;
3382
3383         char ability_match, idle_match, ack_match;
3384
3385         u32 txconfig, rxconfig;
3386 #define ANEG_CFG_NP             0x00000080
3387 #define ANEG_CFG_ACK            0x00000040
3388 #define ANEG_CFG_RF2            0x00000020
3389 #define ANEG_CFG_RF1            0x00000010
3390 #define ANEG_CFG_PS2            0x00000001
3391 #define ANEG_CFG_PS1            0x00008000
3392 #define ANEG_CFG_HD             0x00004000
3393 #define ANEG_CFG_FD             0x00002000
3394 #define ANEG_CFG_INVAL          0x00001f06
3395
3396 };
3397 #define ANEG_OK         0
3398 #define ANEG_DONE       1
3399 #define ANEG_TIMER_ENAB 2
3400 #define ANEG_FAILED     -1
3401
3402 #define ANEG_STATE_SETTLE_TIME  10000
3403
3404 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3405                                    struct tg3_fiber_aneginfo *ap)
3406 {
3407         u16 flowctrl;
3408         unsigned long delta;
3409         u32 rx_cfg_reg;
3410         int ret;
3411
3412         if (ap->state == ANEG_STATE_UNKNOWN) {
3413                 ap->rxconfig = 0;
3414                 ap->link_time = 0;
3415                 ap->cur_time = 0;
3416                 ap->ability_match_cfg = 0;
3417                 ap->ability_match_count = 0;
3418                 ap->ability_match = 0;
3419                 ap->idle_match = 0;
3420                 ap->ack_match = 0;
3421         }
3422         ap->cur_time++;
3423
3424         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3425                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3426
3427                 if (rx_cfg_reg != ap->ability_match_cfg) {
3428                         ap->ability_match_cfg = rx_cfg_reg;
3429                         ap->ability_match = 0;
3430                         ap->ability_match_count = 0;
3431                 } else {
3432                         if (++ap->ability_match_count > 1) {
3433                                 ap->ability_match = 1;
3434                                 ap->ability_match_cfg = rx_cfg_reg;
3435                         }
3436                 }
3437                 if (rx_cfg_reg & ANEG_CFG_ACK)
3438                         ap->ack_match = 1;
3439                 else
3440                         ap->ack_match = 0;
3441
3442                 ap->idle_match = 0;
3443         } else {
3444                 ap->idle_match = 1;
3445                 ap->ability_match_cfg = 0;
3446                 ap->ability_match_count = 0;
3447                 ap->ability_match = 0;
3448                 ap->ack_match = 0;
3449
3450                 rx_cfg_reg = 0;
3451         }
3452
3453         ap->rxconfig = rx_cfg_reg;
3454         ret = ANEG_OK;
3455
3456         switch (ap->state) {
3457         case ANEG_STATE_UNKNOWN:
3458                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3459                         ap->state = ANEG_STATE_AN_ENABLE;
3460
3461                 /* fallthru */
3462         case ANEG_STATE_AN_ENABLE:
3463                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3464                 if (ap->flags & MR_AN_ENABLE) {
3465                         ap->link_time = 0;
3466                         ap->cur_time = 0;
3467                         ap->ability_match_cfg = 0;
3468                         ap->ability_match_count = 0;
3469                         ap->ability_match = 0;
3470                         ap->idle_match = 0;
3471                         ap->ack_match = 0;
3472
3473                         ap->state = ANEG_STATE_RESTART_INIT;
3474                 } else {
3475                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3476                 }
3477                 break;
3478
3479         case ANEG_STATE_RESTART_INIT:
3480                 ap->link_time = ap->cur_time;
3481                 ap->flags &= ~(MR_NP_LOADED);
3482                 ap->txconfig = 0;
3483                 tw32(MAC_TX_AUTO_NEG, 0);
3484                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3485                 tw32_f(MAC_MODE, tp->mac_mode);
3486                 udelay(40);
3487
3488                 ret = ANEG_TIMER_ENAB;
3489                 ap->state = ANEG_STATE_RESTART;
3490
3491                 /* fallthru */
3492         case ANEG_STATE_RESTART:
3493                 delta = ap->cur_time - ap->link_time;
3494                 if (delta > ANEG_STATE_SETTLE_TIME)
3495                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3496                 else
3497                         ret = ANEG_TIMER_ENAB;
3498                 break;
3499
3500         case ANEG_STATE_DISABLE_LINK_OK:
3501                 ret = ANEG_DONE;
3502                 break;
3503
3504         case ANEG_STATE_ABILITY_DETECT_INIT:
3505                 ap->flags &= ~(MR_TOGGLE_TX);
3506                 ap->txconfig = ANEG_CFG_FD;
3507                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3508                 if (flowctrl & ADVERTISE_1000XPAUSE)
3509                         ap->txconfig |= ANEG_CFG_PS1;
3510                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3511                         ap->txconfig |= ANEG_CFG_PS2;
3512                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3513                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3514                 tw32_f(MAC_MODE, tp->mac_mode);
3515                 udelay(40);
3516
3517                 ap->state = ANEG_STATE_ABILITY_DETECT;
3518                 break;
3519
3520         case ANEG_STATE_ABILITY_DETECT:
3521                 if (ap->ability_match != 0 && ap->rxconfig != 0)
3522                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3523                 break;
3524
3525         case ANEG_STATE_ACK_DETECT_INIT:
3526                 ap->txconfig |= ANEG_CFG_ACK;
3527                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3528                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3529                 tw32_f(MAC_MODE, tp->mac_mode);
3530                 udelay(40);
3531
3532                 ap->state = ANEG_STATE_ACK_DETECT;
3533
3534                 /* fallthru */
3535         case ANEG_STATE_ACK_DETECT:
3536                 if (ap->ack_match != 0) {
3537                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3538                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3539                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3540                         } else {
3541                                 ap->state = ANEG_STATE_AN_ENABLE;
3542                         }
3543                 } else if (ap->ability_match != 0 &&
3544                            ap->rxconfig == 0) {
3545                         ap->state = ANEG_STATE_AN_ENABLE;
3546                 }
3547                 break;
3548
3549         case ANEG_STATE_COMPLETE_ACK_INIT:
3550                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3551                         ret = ANEG_FAILED;
3552                         break;
3553                 }
3554                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3555                                MR_LP_ADV_HALF_DUPLEX |
3556                                MR_LP_ADV_SYM_PAUSE |
3557                                MR_LP_ADV_ASYM_PAUSE |
3558                                MR_LP_ADV_REMOTE_FAULT1 |
3559                                MR_LP_ADV_REMOTE_FAULT2 |
3560                                MR_LP_ADV_NEXT_PAGE |
3561                                MR_TOGGLE_RX |
3562                                MR_NP_RX);
3563                 if (ap->rxconfig & ANEG_CFG_FD)
3564                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3565                 if (ap->rxconfig & ANEG_CFG_HD)
3566                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3567                 if (ap->rxconfig & ANEG_CFG_PS1)
3568                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3569                 if (ap->rxconfig & ANEG_CFG_PS2)
3570                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3571                 if (ap->rxconfig & ANEG_CFG_RF1)
3572                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3573                 if (ap->rxconfig & ANEG_CFG_RF2)
3574                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3575                 if (ap->rxconfig & ANEG_CFG_NP)
3576                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3577
3578                 ap->link_time = ap->cur_time;
3579
3580                 ap->flags ^= (MR_TOGGLE_TX);
3581                 if (ap->rxconfig & 0x0008)
3582                         ap->flags |= MR_TOGGLE_RX;
3583                 if (ap->rxconfig & ANEG_CFG_NP)
3584                         ap->flags |= MR_NP_RX;
3585                 ap->flags |= MR_PAGE_RX;
3586
3587                 ap->state = ANEG_STATE_COMPLETE_ACK;
3588                 ret = ANEG_TIMER_ENAB;
3589                 break;
3590
3591         case ANEG_STATE_COMPLETE_ACK:
3592                 if (ap->ability_match != 0 &&
3593                     ap->rxconfig == 0) {
3594                         ap->state = ANEG_STATE_AN_ENABLE;
3595                         break;
3596                 }
3597                 delta = ap->cur_time - ap->link_time;
3598                 if (delta > ANEG_STATE_SETTLE_TIME) {
3599                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3600                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3601                         } else {
3602                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3603                                     !(ap->flags & MR_NP_RX)) {
3604                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3605                                 } else {
3606                                         ret = ANEG_FAILED;
3607                                 }
3608                         }
3609                 }
3610                 break;
3611
3612         case ANEG_STATE_IDLE_DETECT_INIT:
3613                 ap->link_time = ap->cur_time;
3614                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3615                 tw32_f(MAC_MODE, tp->mac_mode);
3616                 udelay(40);
3617
3618                 ap->state = ANEG_STATE_IDLE_DETECT;
3619                 ret = ANEG_TIMER_ENAB;
3620                 break;
3621
3622         case ANEG_STATE_IDLE_DETECT:
3623                 if (ap->ability_match != 0 &&
3624                     ap->rxconfig == 0) {
3625                         ap->state = ANEG_STATE_AN_ENABLE;
3626                         break;
3627                 }
3628                 delta = ap->cur_time - ap->link_time;
3629                 if (delta > ANEG_STATE_SETTLE_TIME) {
3630                         /* XXX another gem from the Broadcom driver :( */
3631                         ap->state = ANEG_STATE_LINK_OK;
3632                 }
3633                 break;
3634
3635         case ANEG_STATE_LINK_OK:
3636                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3637                 ret = ANEG_DONE;
3638                 break;
3639
3640         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3641                 /* ??? unimplemented */
3642                 break;
3643
3644         case ANEG_STATE_NEXT_PAGE_WAIT:
3645                 /* ??? unimplemented */
3646                 break;
3647
3648         default:
3649                 ret = ANEG_FAILED;
3650                 break;
3651         }
3652
3653         return ret;
3654 }
3655
3656 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3657 {
3658         int res = 0;
3659         struct tg3_fiber_aneginfo aninfo;
3660         int status = ANEG_FAILED;
3661         unsigned int tick;
3662         u32 tmp;
3663
3664         tw32_f(MAC_TX_AUTO_NEG, 0);
3665
3666         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3667         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3668         udelay(40);
3669
3670         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3671         udelay(40);
3672
3673         memset(&aninfo, 0, sizeof(aninfo));
3674         aninfo.flags |= MR_AN_ENABLE;
3675         aninfo.state = ANEG_STATE_UNKNOWN;
3676         aninfo.cur_time = 0;
3677         tick = 0;
3678         while (++tick < 195000) {
3679                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3680                 if (status == ANEG_DONE || status == ANEG_FAILED)
3681                         break;
3682
3683                 udelay(1);
3684         }
3685
3686         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3687         tw32_f(MAC_MODE, tp->mac_mode);
3688         udelay(40);
3689
3690         *txflags = aninfo.txconfig;
3691         *rxflags = aninfo.flags;
3692
3693         if (status == ANEG_DONE &&
3694             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3695                              MR_LP_ADV_FULL_DUPLEX)))
3696                 res = 1;
3697
3698         return res;
3699 }
3700
3701 static void tg3_init_bcm8002(struct tg3 *tp)
3702 {
3703         u32 mac_status = tr32(MAC_STATUS);
3704         int i;
3705
3706         /* Reset when initting first time or we have a link. */
3707         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3708             !(mac_status & MAC_STATUS_PCS_SYNCED))
3709                 return;
3710
3711         /* Set PLL lock range. */
3712         tg3_writephy(tp, 0x16, 0x8007);
3713
3714         /* SW reset */
3715         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3716
3717         /* Wait for reset to complete. */
3718         /* XXX schedule_timeout() ... */
3719         for (i = 0; i < 500; i++)
3720                 udelay(10);
3721
3722         /* Config mode; select PMA/Ch 1 regs. */
3723         tg3_writephy(tp, 0x10, 0x8411);
3724
3725         /* Enable auto-lock and comdet, select txclk for tx. */
3726         tg3_writephy(tp, 0x11, 0x0a10);
3727
3728         tg3_writephy(tp, 0x18, 0x00a0);
3729         tg3_writephy(tp, 0x16, 0x41ff);
3730
3731         /* Assert and deassert POR. */
3732         tg3_writephy(tp, 0x13, 0x0400);
3733         udelay(40);
3734         tg3_writephy(tp, 0x13, 0x0000);
3735
3736         tg3_writephy(tp, 0x11, 0x0a50);
3737         udelay(40);
3738         tg3_writephy(tp, 0x11, 0x0a10);
3739
3740         /* Wait for signal to stabilize */
3741         /* XXX schedule_timeout() ... */
3742         for (i = 0; i < 15000; i++)
3743                 udelay(10);
3744
3745         /* Deselect the channel register so we can read the PHYID
3746          * later.
3747          */
3748         tg3_writephy(tp, 0x10, 0x8011);
3749 }
3750
3751 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3752 {
3753         u16 flowctrl;
3754         u32 sg_dig_ctrl, sg_dig_status;
3755         u32 serdes_cfg, expected_sg_dig_ctrl;
3756         int workaround, port_a;
3757         int current_link_up;
3758
3759         serdes_cfg = 0;
3760         expected_sg_dig_ctrl = 0;
3761         workaround = 0;
3762         port_a = 1;
3763         current_link_up = 0;
3764
3765         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3766             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3767                 workaround = 1;
3768                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3769                         port_a = 0;
3770
3771                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3772                 /* preserve bits 20-23 for voltage regulator */
3773                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3774         }
3775
3776         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3777
3778         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3779                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3780                         if (workaround) {
3781                                 u32 val = serdes_cfg;
3782
3783                                 if (port_a)
3784                                         val |= 0xc010000;
3785                                 else
3786                                         val |= 0x4010000;
3787                                 tw32_f(MAC_SERDES_CFG, val);
3788                         }
3789
3790                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3791                 }
3792                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3793                         tg3_setup_flow_control(tp, 0, 0);
3794                         current_link_up = 1;
3795                 }
3796                 goto out;
3797         }
3798
3799         /* Want auto-negotiation.  */
3800         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3801
3802         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3803         if (flowctrl & ADVERTISE_1000XPAUSE)
3804                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3805         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3806                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3807
3808         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3809                 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3810                     tp->serdes_counter &&
3811                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3812                                     MAC_STATUS_RCVD_CFG)) ==
3813                      MAC_STATUS_PCS_SYNCED)) {
3814                         tp->serdes_counter--;
3815                         current_link_up = 1;
3816                         goto out;
3817                 }
3818 restart_autoneg:
3819                 if (workaround)
3820                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3821                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3822                 udelay(5);
3823                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3824
3825                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3826                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3827         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3828                                  MAC_STATUS_SIGNAL_DET)) {
3829                 sg_dig_status = tr32(SG_DIG_STATUS);
3830                 mac_status = tr32(MAC_STATUS);
3831
3832                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3833                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3834                         u32 local_adv = 0, remote_adv = 0;
3835
3836                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3837                                 local_adv |= ADVERTISE_1000XPAUSE;
3838                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3839                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3840
3841                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3842                                 remote_adv |= LPA_1000XPAUSE;
3843                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3844                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3845
3846                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3847                         current_link_up = 1;
3848                         tp->serdes_counter = 0;
3849                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3850                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3851                         if (tp->serdes_counter)
3852                                 tp->serdes_counter--;
3853                         else {
3854                                 if (workaround) {
3855                                         u32 val = serdes_cfg;
3856
3857                                         if (port_a)
3858                                                 val |= 0xc010000;
3859                                         else
3860                                                 val |= 0x4010000;
3861
3862                                         tw32_f(MAC_SERDES_CFG, val);
3863                                 }
3864
3865                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3866                                 udelay(40);
3867
3868                                 /* Link parallel detection - link is up */
3869                                 /* only if we have PCS_SYNC and not */
3870                                 /* receiving config code words */
3871                                 mac_status = tr32(MAC_STATUS);
3872                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3873                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3874                                         tg3_setup_flow_control(tp, 0, 0);
3875                                         current_link_up = 1;
3876                                         tp->phy_flags |=
3877                                                 TG3_PHYFLG_PARALLEL_DETECT;
3878                                         tp->serdes_counter =
3879                                                 SERDES_PARALLEL_DET_TIMEOUT;
3880                                 } else
3881                                         goto restart_autoneg;
3882                         }
3883                 }
3884         } else {
3885                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3886                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3887         }
3888
3889 out:
3890         return current_link_up;
3891 }
3892
3893 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3894 {
3895         int current_link_up = 0;
3896
3897         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3898                 goto out;
3899
3900         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3901                 u32 txflags, rxflags;
3902                 int i;
3903
3904                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3905                         u32 local_adv = 0, remote_adv = 0;
3906
3907                         if (txflags & ANEG_CFG_PS1)
3908                                 local_adv |= ADVERTISE_1000XPAUSE;
3909                         if (txflags & ANEG_CFG_PS2)
3910                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3911
3912                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3913                                 remote_adv |= LPA_1000XPAUSE;
3914                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3915                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3916
3917                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3918
3919                         current_link_up = 1;
3920                 }
3921                 for (i = 0; i < 30; i++) {
3922                         udelay(20);
3923                         tw32_f(MAC_STATUS,
3924                                (MAC_STATUS_SYNC_CHANGED |
3925                                 MAC_STATUS_CFG_CHANGED));
3926                         udelay(40);
3927                         if ((tr32(MAC_STATUS) &
3928                              (MAC_STATUS_SYNC_CHANGED |
3929                               MAC_STATUS_CFG_CHANGED)) == 0)
3930                                 break;
3931                 }
3932
3933                 mac_status = tr32(MAC_STATUS);
3934                 if (current_link_up == 0 &&
3935                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3936                     !(mac_status & MAC_STATUS_RCVD_CFG))
3937                         current_link_up = 1;
3938         } else {
3939                 tg3_setup_flow_control(tp, 0, 0);
3940
3941                 /* Forcing 1000FD link up. */
3942                 current_link_up = 1;
3943
3944                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3945                 udelay(40);
3946
3947                 tw32_f(MAC_MODE, tp->mac_mode);
3948                 udelay(40);
3949         }
3950
3951 out:
3952         return current_link_up;
3953 }
3954
3955 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3956 {
3957         u32 orig_pause_cfg;
3958         u16 orig_active_speed;
3959         u8 orig_active_duplex;
3960         u32 mac_status;
3961         int current_link_up;
3962         int i;
3963
3964         orig_pause_cfg = tp->link_config.active_flowctrl;
3965         orig_active_speed = tp->link_config.active_speed;
3966         orig_active_duplex = tp->link_config.active_duplex;
3967
3968         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3969             netif_carrier_ok(tp->dev) &&
3970             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3971                 mac_status = tr32(MAC_STATUS);
3972                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3973                                MAC_STATUS_SIGNAL_DET |
3974                                MAC_STATUS_CFG_CHANGED |
3975                                MAC_STATUS_RCVD_CFG);
3976                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3977                                    MAC_STATUS_SIGNAL_DET)) {
3978                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3979                                             MAC_STATUS_CFG_CHANGED));
3980                         return 0;
3981                 }
3982         }
3983
3984         tw32_f(MAC_TX_AUTO_NEG, 0);
3985
3986         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3987         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3988         tw32_f(MAC_MODE, tp->mac_mode);
3989         udelay(40);
3990
3991         if (tp->phy_id == TG3_PHY_ID_BCM8002)
3992                 tg3_init_bcm8002(tp);
3993
3994         /* Enable link change event even when serdes polling.  */
3995         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3996         udelay(40);
3997
3998         current_link_up = 0;
3999         mac_status = tr32(MAC_STATUS);
4000
4001         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
4002                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4003         else
4004                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4005
4006         tp->napi[0].hw_status->status =
4007                 (SD_STATUS_UPDATED |
4008                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4009
4010         for (i = 0; i < 100; i++) {
4011                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4012                                     MAC_STATUS_CFG_CHANGED));
4013                 udelay(5);
4014                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4015                                          MAC_STATUS_CFG_CHANGED |
4016                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4017                         break;
4018         }
4019
4020         mac_status = tr32(MAC_STATUS);
4021         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4022                 current_link_up = 0;
4023                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4024                     tp->serdes_counter == 0) {
4025                         tw32_f(MAC_MODE, (tp->mac_mode |
4026                                           MAC_MODE_SEND_CONFIGS));
4027                         udelay(1);
4028                         tw32_f(MAC_MODE, tp->mac_mode);
4029                 }
4030         }
4031
4032         if (current_link_up == 1) {
4033                 tp->link_config.active_speed = SPEED_1000;
4034                 tp->link_config.active_duplex = DUPLEX_FULL;
4035                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4036                                     LED_CTRL_LNKLED_OVERRIDE |
4037                                     LED_CTRL_1000MBPS_ON));
4038         } else {
4039                 tp->link_config.active_speed = SPEED_INVALID;
4040                 tp->link_config.active_duplex = DUPLEX_INVALID;
4041                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4042                                     LED_CTRL_LNKLED_OVERRIDE |
4043                                     LED_CTRL_TRAFFIC_OVERRIDE));
4044         }
4045
4046         if (current_link_up != netif_carrier_ok(tp->dev)) {
4047                 if (current_link_up)
4048                         netif_carrier_on(tp->dev);
4049                 else
4050                         netif_carrier_off(tp->dev);
4051                 tg3_link_report(tp);
4052         } else {
4053                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4054                 if (orig_pause_cfg != now_pause_cfg ||
4055                     orig_active_speed != tp->link_config.active_speed ||
4056                     orig_active_duplex != tp->link_config.active_duplex)
4057                         tg3_link_report(tp);
4058         }
4059
4060         return 0;
4061 }
4062
4063 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4064 {
4065         int current_link_up, err = 0;
4066         u32 bmsr, bmcr;
4067         u16 current_speed;
4068         u8 current_duplex;
4069         u32 local_adv, remote_adv;
4070
4071         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4072         tw32_f(MAC_MODE, tp->mac_mode);
4073         udelay(40);
4074
4075         tw32(MAC_EVENT, 0);
4076
4077         tw32_f(MAC_STATUS,
4078              (MAC_STATUS_SYNC_CHANGED |
4079               MAC_STATUS_CFG_CHANGED |
4080               MAC_STATUS_MI_COMPLETION |
4081               MAC_STATUS_LNKSTATE_CHANGED));
4082         udelay(40);
4083
4084         if (force_reset)
4085                 tg3_phy_reset(tp);
4086
4087         current_link_up = 0;
4088         current_speed = SPEED_INVALID;
4089         current_duplex = DUPLEX_INVALID;
4090
4091         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4092         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4093         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4094                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4095                         bmsr |= BMSR_LSTATUS;
4096                 else
4097                         bmsr &= ~BMSR_LSTATUS;
4098         }
4099
4100         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4101
4102         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4103             (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4104                 /* do nothing, just check for link up at the end */
4105         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4106                 u32 adv, new_adv;
4107
4108                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4109                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4110                                   ADVERTISE_1000XPAUSE |
4111                                   ADVERTISE_1000XPSE_ASYM |
4112                                   ADVERTISE_SLCT);
4113
4114                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4115
4116                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4117                         new_adv |= ADVERTISE_1000XHALF;
4118                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4119                         new_adv |= ADVERTISE_1000XFULL;
4120
4121                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4122                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4123                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4124                         tg3_writephy(tp, MII_BMCR, bmcr);
4125
4126                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4127                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4128                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4129
4130                         return err;
4131                 }
4132         } else {
4133                 u32 new_bmcr;
4134
4135                 bmcr &= ~BMCR_SPEED1000;
4136                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4137
4138                 if (tp->link_config.duplex == DUPLEX_FULL)
4139                         new_bmcr |= BMCR_FULLDPLX;
4140
4141                 if (new_bmcr != bmcr) {
4142                         /* BMCR_SPEED1000 is a reserved bit that needs
4143                          * to be set on write.
4144                          */
4145                         new_bmcr |= BMCR_SPEED1000;
4146
4147                         /* Force a linkdown */
4148                         if (netif_carrier_ok(tp->dev)) {
4149                                 u32 adv;
4150
4151                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4152                                 adv &= ~(ADVERTISE_1000XFULL |
4153                                          ADVERTISE_1000XHALF |
4154                                          ADVERTISE_SLCT);
4155                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4156                                 tg3_writephy(tp, MII_BMCR, bmcr |
4157                                                            BMCR_ANRESTART |
4158                                                            BMCR_ANENABLE);
4159                                 udelay(10);
4160                                 netif_carrier_off(tp->dev);
4161                         }
4162                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4163                         bmcr = new_bmcr;
4164                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4165                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4166                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4167                             ASIC_REV_5714) {
4168                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4169                                         bmsr |= BMSR_LSTATUS;
4170                                 else
4171                                         bmsr &= ~BMSR_LSTATUS;
4172                         }
4173                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4174                 }
4175         }
4176
4177         if (bmsr & BMSR_LSTATUS) {
4178                 current_speed = SPEED_1000;
4179                 current_link_up = 1;
4180                 if (bmcr & BMCR_FULLDPLX)
4181                         current_duplex = DUPLEX_FULL;
4182                 else
4183                         current_duplex = DUPLEX_HALF;
4184
4185                 local_adv = 0;
4186                 remote_adv = 0;
4187
4188                 if (bmcr & BMCR_ANENABLE) {
4189                         u32 common;
4190
4191                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4192                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4193                         common = local_adv & remote_adv;
4194                         if (common & (ADVERTISE_1000XHALF |
4195                                       ADVERTISE_1000XFULL)) {
4196                                 if (common & ADVERTISE_1000XFULL)
4197                                         current_duplex = DUPLEX_FULL;
4198                                 else
4199                                         current_duplex = DUPLEX_HALF;
4200                         } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4201                                 /* Link is up via parallel detect */
4202                         } else {
4203                                 current_link_up = 0;
4204                         }
4205                 }
4206         }
4207
4208         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4209                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4210
4211         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4212         if (tp->link_config.active_duplex == DUPLEX_HALF)
4213                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4214
4215         tw32_f(MAC_MODE, tp->mac_mode);
4216         udelay(40);
4217
4218         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4219
4220         tp->link_config.active_speed = current_speed;
4221         tp->link_config.active_duplex = current_duplex;
4222
4223         if (current_link_up != netif_carrier_ok(tp->dev)) {
4224                 if (current_link_up)
4225                         netif_carrier_on(tp->dev);
4226                 else {
4227                         netif_carrier_off(tp->dev);
4228                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4229                 }
4230                 tg3_link_report(tp);
4231         }
4232         return err;
4233 }
4234
4235 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4236 {
4237         if (tp->serdes_counter) {
4238                 /* Give autoneg time to complete. */
4239                 tp->serdes_counter--;
4240                 return;
4241         }
4242
4243         if (!netif_carrier_ok(tp->dev) &&
4244             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4245                 u32 bmcr;
4246
4247                 tg3_readphy(tp, MII_BMCR, &bmcr);
4248                 if (bmcr & BMCR_ANENABLE) {
4249                         u32 phy1, phy2;
4250
4251                         /* Select shadow register 0x1f */
4252                         tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
4253                         tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
4254
4255                         /* Select expansion interrupt status register */
4256                         tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4257                                          MII_TG3_DSP_EXP1_INT_STAT);
4258                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4259                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4260
4261                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4262                                 /* We have signal detect and not receiving
4263                                  * config code words, link is up by parallel
4264                                  * detection.
4265                                  */
4266
4267                                 bmcr &= ~BMCR_ANENABLE;
4268                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4269                                 tg3_writephy(tp, MII_BMCR, bmcr);
4270                                 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
4271                         }
4272                 }
4273         } else if (netif_carrier_ok(tp->dev) &&
4274                    (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4275                    (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4276                 u32 phy2;
4277
4278                 /* Select expansion interrupt status register */
4279                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4280                                  MII_TG3_DSP_EXP1_INT_STAT);
4281                 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4282                 if (phy2 & 0x20) {
4283                         u32 bmcr;
4284
4285                         /* Config code words received, turn on autoneg. */
4286                         tg3_readphy(tp, MII_BMCR, &bmcr);
4287                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4288
4289                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4290
4291                 }
4292         }
4293 }
4294
4295 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4296 {
4297         int err;
4298
4299         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
4300                 err = tg3_setup_fiber_phy(tp, force_reset);
4301         else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4302                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4303         else
4304                 err = tg3_setup_copper_phy(tp, force_reset);
4305
4306         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4307                 u32 val, scale;
4308
4309                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4310                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4311                         scale = 65;
4312                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4313                         scale = 6;
4314                 else
4315                         scale = 12;
4316
4317                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4318                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4319                 tw32(GRC_MISC_CFG, val);
4320         }
4321
4322         if (tp->link_config.active_speed == SPEED_1000 &&
4323             tp->link_config.active_duplex == DUPLEX_HALF)
4324                 tw32(MAC_TX_LENGTHS,
4325                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4326                       (6 << TX_LENGTHS_IPG_SHIFT) |
4327                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4328         else
4329                 tw32(MAC_TX_LENGTHS,
4330                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4331                       (6 << TX_LENGTHS_IPG_SHIFT) |
4332                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4333
4334         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4335                 if (netif_carrier_ok(tp->dev)) {
4336                         tw32(HOSTCC_STAT_COAL_TICKS,
4337                              tp->coal.stats_block_coalesce_usecs);
4338                 } else {
4339                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4340                 }
4341         }
4342
4343         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4344                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4345                 if (!netif_carrier_ok(tp->dev))
4346                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4347                               tp->pwrmgmt_thresh;
4348                 else
4349                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4350                 tw32(PCIE_PWR_MGMT_THRESH, val);
4351         }
4352
4353         return err;
4354 }
4355
4356 /* This is called whenever we suspect that the system chipset is re-
4357  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4358  * is bogus tx completions. We try to recover by setting the
4359  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4360  * in the workqueue.
4361  */
4362 static void tg3_tx_recover(struct tg3 *tp)
4363 {
4364         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4365                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4366
4367         netdev_warn(tp->dev,
4368                     "The system may be re-ordering memory-mapped I/O "
4369                     "cycles to the network device, attempting to recover. "
4370                     "Please report the problem to the driver maintainer "
4371                     "and include system chipset information.\n");
4372
4373         spin_lock(&tp->lock);
4374         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4375         spin_unlock(&tp->lock);
4376 }
4377
4378 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4379 {
4380         /* Tell compiler to fetch tx indices from memory. */
4381         barrier();
4382         return tnapi->tx_pending -
4383                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4384 }
4385
4386 /* Tigon3 never reports partial packet sends.  So we do not
4387  * need special logic to handle SKBs that have not had all
4388  * of their frags sent yet, like SunGEM does.
4389  */
4390 static void tg3_tx(struct tg3_napi *tnapi)
4391 {
4392         struct tg3 *tp = tnapi->tp;
4393         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4394         u32 sw_idx = tnapi->tx_cons;
4395         struct netdev_queue *txq;
4396         int index = tnapi - tp->napi;
4397
4398         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4399                 index--;
4400
4401         txq = netdev_get_tx_queue(tp->dev, index);
4402
4403         while (sw_idx != hw_idx) {
4404                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4405                 struct sk_buff *skb = ri->skb;
4406                 int i, tx_bug = 0;
4407
4408                 if (unlikely(skb == NULL)) {
4409                         tg3_tx_recover(tp);
4410                         return;
4411                 }
4412
4413                 pci_unmap_single(tp->pdev,
4414                                  dma_unmap_addr(ri, mapping),
4415                                  skb_headlen(skb),
4416                                  PCI_DMA_TODEVICE);
4417
4418                 ri->skb = NULL;
4419
4420                 sw_idx = NEXT_TX(sw_idx);
4421
4422                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4423                         ri = &tnapi->tx_buffers[sw_idx];
4424                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4425                                 tx_bug = 1;
4426
4427                         pci_unmap_page(tp->pdev,
4428                                        dma_unmap_addr(ri, mapping),
4429                                        skb_shinfo(skb)->frags[i].size,
4430                                        PCI_DMA_TODEVICE);
4431                         sw_idx = NEXT_TX(sw_idx);
4432                 }
4433
4434                 dev_kfree_skb(skb);
4435
4436                 if (unlikely(tx_bug)) {
4437                         tg3_tx_recover(tp);
4438                         return;
4439                 }
4440         }
4441
4442         tnapi->tx_cons = sw_idx;
4443
4444         /* Need to make the tx_cons update visible to tg3_start_xmit()
4445          * before checking for netif_queue_stopped().  Without the
4446          * memory barrier, there is a small possibility that tg3_start_xmit()
4447          * will miss it and cause the queue to be stopped forever.
4448          */
4449         smp_mb();
4450
4451         if (unlikely(netif_tx_queue_stopped(txq) &&
4452                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4453                 __netif_tx_lock(txq, smp_processor_id());
4454                 if (netif_tx_queue_stopped(txq) &&
4455                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4456                         netif_tx_wake_queue(txq);
4457                 __netif_tx_unlock(txq);
4458         }
4459 }
4460
4461 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4462 {
4463         if (!ri->skb)
4464                 return;
4465
4466         pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4467                          map_sz, PCI_DMA_FROMDEVICE);
4468         dev_kfree_skb_any(ri->skb);
4469         ri->skb = NULL;
4470 }
4471
4472 /* Returns size of skb allocated or < 0 on error.
4473  *
4474  * We only need to fill in the address because the other members
4475  * of the RX descriptor are invariant, see tg3_init_rings.
4476  *
4477  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4478  * posting buffers we only dirty the first cache line of the RX
4479  * descriptor (containing the address).  Whereas for the RX status
4480  * buffers the cpu only reads the last cacheline of the RX descriptor
4481  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4482  */
4483 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4484                             u32 opaque_key, u32 dest_idx_unmasked)
4485 {
4486         struct tg3_rx_buffer_desc *desc;
4487         struct ring_info *map, *src_map;
4488         struct sk_buff *skb;
4489         dma_addr_t mapping;
4490         int skb_size, dest_idx;
4491
4492         src_map = NULL;
4493         switch (opaque_key) {
4494         case RXD_OPAQUE_RING_STD:
4495                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4496                 desc = &tpr->rx_std[dest_idx];
4497                 map = &tpr->rx_std_buffers[dest_idx];
4498                 skb_size = tp->rx_pkt_map_sz;
4499                 break;
4500
4501         case RXD_OPAQUE_RING_JUMBO:
4502                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4503                 desc = &tpr->rx_jmb[dest_idx].std;
4504                 map = &tpr->rx_jmb_buffers[dest_idx];
4505                 skb_size = TG3_RX_JMB_MAP_SZ;
4506                 break;
4507
4508         default:
4509                 return -EINVAL;
4510         }
4511
4512         /* Do not overwrite any of the map or rp information
4513          * until we are sure we can commit to a new buffer.
4514          *
4515          * Callers depend upon this behavior and assume that
4516          * we leave everything unchanged if we fail.
4517          */
4518         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4519         if (skb == NULL)
4520                 return -ENOMEM;
4521
4522         skb_reserve(skb, tp->rx_offset);
4523
4524         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4525                                  PCI_DMA_FROMDEVICE);
4526         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4527                 dev_kfree_skb(skb);
4528                 return -EIO;
4529         }
4530
4531         map->skb = skb;
4532         dma_unmap_addr_set(map, mapping, mapping);
4533
4534         desc->addr_hi = ((u64)mapping >> 32);
4535         desc->addr_lo = ((u64)mapping & 0xffffffff);
4536
4537         return skb_size;
4538 }
4539
4540 /* We only need to move over in the address because the other
4541  * members of the RX descriptor are invariant.  See notes above
4542  * tg3_alloc_rx_skb for full details.
4543  */
4544 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4545                            struct tg3_rx_prodring_set *dpr,
4546                            u32 opaque_key, int src_idx,
4547                            u32 dest_idx_unmasked)
4548 {
4549         struct tg3 *tp = tnapi->tp;
4550         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4551         struct ring_info *src_map, *dest_map;
4552         struct tg3_rx_prodring_set *spr = &tp->prodring[0];
4553         int dest_idx;
4554
4555         switch (opaque_key) {
4556         case RXD_OPAQUE_RING_STD:
4557                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4558                 dest_desc = &dpr->rx_std[dest_idx];
4559                 dest_map = &dpr->rx_std_buffers[dest_idx];
4560                 src_desc = &spr->rx_std[src_idx];
4561                 src_map = &spr->rx_std_buffers[src_idx];
4562                 break;
4563
4564         case RXD_OPAQUE_RING_JUMBO:
4565                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4566                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4567                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4568                 src_desc = &spr->rx_jmb[src_idx].std;
4569                 src_map = &spr->rx_jmb_buffers[src_idx];
4570                 break;
4571
4572         default:
4573                 return;
4574         }
4575
4576         dest_map->skb = src_map->skb;
4577         dma_unmap_addr_set(dest_map, mapping,
4578                            dma_unmap_addr(src_map, mapping));
4579         dest_desc->addr_hi = src_desc->addr_hi;
4580         dest_desc->addr_lo = src_desc->addr_lo;
4581
4582         /* Ensure that the update to the skb happens after the physical
4583          * addresses have been transferred to the new BD location.
4584          */
4585         smp_wmb();
4586
4587         src_map->skb = NULL;
4588 }
4589
4590 /* The RX ring scheme is composed of multiple rings which post fresh
4591  * buffers to the chip, and one special ring the chip uses to report
4592  * status back to the host.
4593  *
4594  * The special ring reports the status of received packets to the
4595  * host.  The chip does not write into the original descriptor the
4596  * RX buffer was obtained from.  The chip simply takes the original
4597  * descriptor as provided by the host, updates the status and length
4598  * field, then writes this into the next status ring entry.
4599  *
4600  * Each ring the host uses to post buffers to the chip is described
4601  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4602  * it is first placed into the on-chip ram.  When the packet's length
4603  * is known, it walks down the TG3_BDINFO entries to select the ring.
4604  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4605  * which is within the range of the new packet's length is chosen.
4606  *
4607  * The "separate ring for rx status" scheme may sound queer, but it makes
4608  * sense from a cache coherency perspective.  If only the host writes
4609  * to the buffer post rings, and only the chip writes to the rx status
4610  * rings, then cache lines never move beyond shared-modified state.
4611  * If both the host and chip were to write into the same ring, cache line
4612  * eviction could occur since both entities want it in an exclusive state.
4613  */
4614 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4615 {
4616         struct tg3 *tp = tnapi->tp;
4617         u32 work_mask, rx_std_posted = 0;
4618         u32 std_prod_idx, jmb_prod_idx;
4619         u32 sw_idx = tnapi->rx_rcb_ptr;
4620         u16 hw_idx;
4621         int received;
4622         struct tg3_rx_prodring_set *tpr = tnapi->prodring;
4623
4624         hw_idx = *(tnapi->rx_rcb_prod_idx);
4625         /*
4626          * We need to order the read of hw_idx and the read of
4627          * the opaque cookie.
4628          */
4629         rmb();
4630         work_mask = 0;
4631         received = 0;
4632         std_prod_idx = tpr->rx_std_prod_idx;
4633         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4634         while (sw_idx != hw_idx && budget > 0) {
4635                 struct ring_info *ri;
4636                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4637                 unsigned int len;
4638                 struct sk_buff *skb;
4639                 dma_addr_t dma_addr;
4640                 u32 opaque_key, desc_idx, *post_ptr;
4641                 bool hw_vlan __maybe_unused = false;
4642                 u16 vtag __maybe_unused = 0;
4643
4644                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4645                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4646                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4647                         ri = &tp->prodring[0].rx_std_buffers[desc_idx];
4648                         dma_addr = dma_unmap_addr(ri, mapping);
4649                         skb = ri->skb;
4650                         post_ptr = &std_prod_idx;
4651                         rx_std_posted++;
4652                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4653                         ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
4654                         dma_addr = dma_unmap_addr(ri, mapping);
4655                         skb = ri->skb;
4656                         post_ptr = &jmb_prod_idx;
4657                 } else
4658                         goto next_pkt_nopost;
4659
4660                 work_mask |= opaque_key;
4661
4662                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4663                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4664                 drop_it:
4665                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4666                                        desc_idx, *post_ptr);
4667                 drop_it_no_recycle:
4668                         /* Other statistics kept track of by card. */
4669                         tp->net_stats.rx_dropped++;
4670                         goto next_pkt;
4671                 }
4672
4673                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4674                       ETH_FCS_LEN;
4675
4676                 if (len > TG3_RX_COPY_THRESH(tp)) {
4677                         int skb_size;
4678
4679                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4680                                                     *post_ptr);
4681                         if (skb_size < 0)
4682                                 goto drop_it;
4683
4684                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4685                                          PCI_DMA_FROMDEVICE);
4686
4687                         /* Ensure that the update to the skb happens
4688                          * after the usage of the old DMA mapping.
4689                          */
4690                         smp_wmb();
4691
4692                         ri->skb = NULL;
4693
4694                         skb_put(skb, len);
4695                 } else {
4696                         struct sk_buff *copy_skb;
4697
4698                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4699                                        desc_idx, *post_ptr);
4700
4701                         copy_skb = netdev_alloc_skb(tp->dev, len + VLAN_HLEN +
4702                                                     TG3_RAW_IP_ALIGN);
4703                         if (copy_skb == NULL)
4704                                 goto drop_it_no_recycle;
4705
4706                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN + VLAN_HLEN);
4707                         skb_put(copy_skb, len);
4708                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4709                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4710                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4711
4712                         /* We'll reuse the original ring buffer. */
4713                         skb = copy_skb;
4714                 }
4715
4716                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4717                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4718                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4719                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4720                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4721                 else
4722                         skb_checksum_none_assert(skb);
4723
4724                 skb->protocol = eth_type_trans(skb, tp->dev);
4725
4726                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4727                     skb->protocol != htons(ETH_P_8021Q)) {
4728                         dev_kfree_skb(skb);
4729                         goto next_pkt;
4730                 }
4731
4732                 if (desc->type_flags & RXD_FLAG_VLAN &&
4733                     !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) {
4734                         vtag = desc->err_vlan & RXD_VLAN_MASK;
4735 #if TG3_VLAN_TAG_USED
4736                         if (tp->vlgrp)
4737                                 hw_vlan = true;
4738                         else
4739 #endif
4740                         {
4741                                 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
4742                                                     __skb_push(skb, VLAN_HLEN);
4743
4744                                 memmove(ve, skb->data + VLAN_HLEN,
4745                                         ETH_ALEN * 2);
4746                                 ve->h_vlan_proto = htons(ETH_P_8021Q);
4747                                 ve->h_vlan_TCI = htons(vtag);
4748                         }
4749                 }
4750
4751 #if TG3_VLAN_TAG_USED
4752                 if (hw_vlan)
4753                         vlan_gro_receive(&tnapi->napi, tp->vlgrp, vtag, skb);
4754                 else
4755 #endif
4756                         napi_gro_receive(&tnapi->napi, skb);
4757
4758                 received++;
4759                 budget--;
4760
4761 next_pkt:
4762                 (*post_ptr)++;
4763
4764                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4765                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4766                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4767                                      tpr->rx_std_prod_idx);
4768                         work_mask &= ~RXD_OPAQUE_RING_STD;
4769                         rx_std_posted = 0;
4770                 }
4771 next_pkt_nopost:
4772                 sw_idx++;
4773                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4774
4775                 /* Refresh hw_idx to see if there is new work */
4776                 if (sw_idx == hw_idx) {
4777                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4778                         rmb();
4779                 }
4780         }
4781
4782         /* ACK the status ring. */
4783         tnapi->rx_rcb_ptr = sw_idx;
4784         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4785
4786         /* Refill RX ring(s). */
4787         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4788                 if (work_mask & RXD_OPAQUE_RING_STD) {
4789                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4790                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4791                                      tpr->rx_std_prod_idx);
4792                 }
4793                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4794                         tpr->rx_jmb_prod_idx = jmb_prod_idx %
4795                                                TG3_RX_JUMBO_RING_SIZE;
4796                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4797                                      tpr->rx_jmb_prod_idx);
4798                 }
4799                 mmiowb();
4800         } else if (work_mask) {
4801                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4802                  * updated before the producer indices can be updated.
4803                  */
4804                 smp_wmb();
4805
4806                 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4807                 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
4808
4809                 if (tnapi != &tp->napi[1])
4810                         napi_schedule(&tp->napi[1].napi);
4811         }
4812
4813         return received;
4814 }
4815
4816 static void tg3_poll_link(struct tg3 *tp)
4817 {
4818         /* handle link change and other phy events */
4819         if (!(tp->tg3_flags &
4820               (TG3_FLAG_USE_LINKCHG_REG |
4821                TG3_FLAG_POLL_SERDES))) {
4822                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4823
4824                 if (sblk->status & SD_STATUS_LINK_CHG) {
4825                         sblk->status = SD_STATUS_UPDATED |
4826                                        (sblk->status & ~SD_STATUS_LINK_CHG);
4827                         spin_lock(&tp->lock);
4828                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4829                                 tw32_f(MAC_STATUS,
4830                                      (MAC_STATUS_SYNC_CHANGED |
4831                                       MAC_STATUS_CFG_CHANGED |
4832                                       MAC_STATUS_MI_COMPLETION |
4833                                       MAC_STATUS_LNKSTATE_CHANGED));
4834                                 udelay(40);
4835                         } else
4836                                 tg3_setup_phy(tp, 0);
4837                         spin_unlock(&tp->lock);
4838                 }
4839         }
4840 }
4841
4842 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4843                                 struct tg3_rx_prodring_set *dpr,
4844                                 struct tg3_rx_prodring_set *spr)
4845 {
4846         u32 si, di, cpycnt, src_prod_idx;
4847         int i, err = 0;
4848
4849         while (1) {
4850                 src_prod_idx = spr->rx_std_prod_idx;
4851
4852                 /* Make sure updates to the rx_std_buffers[] entries and the
4853                  * standard producer index are seen in the correct order.
4854                  */
4855                 smp_rmb();
4856
4857                 if (spr->rx_std_cons_idx == src_prod_idx)
4858                         break;
4859
4860                 if (spr->rx_std_cons_idx < src_prod_idx)
4861                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4862                 else
4863                         cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4864
4865                 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4866
4867                 si = spr->rx_std_cons_idx;
4868                 di = dpr->rx_std_prod_idx;
4869
4870                 for (i = di; i < di + cpycnt; i++) {
4871                         if (dpr->rx_std_buffers[i].skb) {
4872                                 cpycnt = i - di;
4873                                 err = -ENOSPC;
4874                                 break;
4875                         }
4876                 }
4877
4878                 if (!cpycnt)
4879                         break;
4880
4881                 /* Ensure that updates to the rx_std_buffers ring and the
4882                  * shadowed hardware producer ring from tg3_recycle_skb() are
4883                  * ordered correctly WRT the skb check above.
4884                  */
4885                 smp_rmb();
4886
4887                 memcpy(&dpr->rx_std_buffers[di],
4888                        &spr->rx_std_buffers[si],
4889                        cpycnt * sizeof(struct ring_info));
4890
4891                 for (i = 0; i < cpycnt; i++, di++, si++) {
4892                         struct tg3_rx_buffer_desc *sbd, *dbd;
4893                         sbd = &spr->rx_std[si];
4894                         dbd = &dpr->rx_std[di];
4895                         dbd->addr_hi = sbd->addr_hi;
4896                         dbd->addr_lo = sbd->addr_lo;
4897                 }
4898
4899                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4900                                        TG3_RX_RING_SIZE;
4901                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4902                                        TG3_RX_RING_SIZE;
4903         }
4904
4905         while (1) {
4906                 src_prod_idx = spr->rx_jmb_prod_idx;
4907
4908                 /* Make sure updates to the rx_jmb_buffers[] entries and
4909                  * the jumbo producer index are seen in the correct order.
4910                  */
4911                 smp_rmb();
4912
4913                 if (spr->rx_jmb_cons_idx == src_prod_idx)
4914                         break;
4915
4916                 if (spr->rx_jmb_cons_idx < src_prod_idx)
4917                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4918                 else
4919                         cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4920
4921                 cpycnt = min(cpycnt,
4922                              TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4923
4924                 si = spr->rx_jmb_cons_idx;
4925                 di = dpr->rx_jmb_prod_idx;
4926
4927                 for (i = di; i < di + cpycnt; i++) {
4928                         if (dpr->rx_jmb_buffers[i].skb) {
4929                                 cpycnt = i - di;
4930                                 err = -ENOSPC;
4931                                 break;
4932                         }
4933                 }
4934
4935                 if (!cpycnt)
4936                         break;
4937
4938                 /* Ensure that updates to the rx_jmb_buffers ring and the
4939                  * shadowed hardware producer ring from tg3_recycle_skb() are
4940                  * ordered correctly WRT the skb check above.
4941                  */
4942                 smp_rmb();
4943
4944                 memcpy(&dpr->rx_jmb_buffers[di],
4945                        &spr->rx_jmb_buffers[si],
4946                        cpycnt * sizeof(struct ring_info));
4947
4948                 for (i = 0; i < cpycnt; i++, di++, si++) {
4949                         struct tg3_rx_buffer_desc *sbd, *dbd;
4950                         sbd = &spr->rx_jmb[si].std;
4951                         dbd = &dpr->rx_jmb[di].std;
4952                         dbd->addr_hi = sbd->addr_hi;
4953                         dbd->addr_lo = sbd->addr_lo;
4954                 }
4955
4956                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4957                                        TG3_RX_JUMBO_RING_SIZE;
4958                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4959                                        TG3_RX_JUMBO_RING_SIZE;
4960         }
4961
4962         return err;
4963 }
4964
4965 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4966 {
4967         struct tg3 *tp = tnapi->tp;
4968
4969         /* run TX completion thread */
4970         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4971                 tg3_tx(tnapi);
4972                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4973                         return work_done;
4974         }
4975
4976         /* run RX thread, within the bounds set by NAPI.
4977          * All RX "locking" is done by ensuring outside
4978          * code synchronizes with tg3->napi.poll()
4979          */
4980         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4981                 work_done += tg3_rx(tnapi, budget - work_done);
4982
4983         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4984                 struct tg3_rx_prodring_set *dpr = &tp->prodring[0];
4985                 int i, err = 0;
4986                 u32 std_prod_idx = dpr->rx_std_prod_idx;
4987                 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
4988
4989                 for (i = 1; i < tp->irq_cnt; i++)
4990                         err |= tg3_rx_prodring_xfer(tp, dpr,
4991                                                     tp->napi[i].prodring);
4992
4993                 wmb();
4994
4995                 if (std_prod_idx != dpr->rx_std_prod_idx)
4996                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4997                                      dpr->rx_std_prod_idx);
4998
4999                 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5000                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5001                                      dpr->rx_jmb_prod_idx);
5002
5003                 mmiowb();
5004
5005                 if (err)
5006                         tw32_f(HOSTCC_MODE, tp->coal_now);
5007         }
5008
5009         return work_done;
5010 }
5011
5012 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5013 {
5014         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5015         struct tg3 *tp = tnapi->tp;
5016         int work_done = 0;
5017         struct tg3_hw_status *sblk = tnapi->hw_status;
5018
5019         while (1) {
5020                 work_done = tg3_poll_work(tnapi, work_done, budget);
5021
5022                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5023                         goto tx_recovery;
5024
5025                 if (unlikely(work_done >= budget))
5026                         break;
5027
5028                 /* tp->last_tag is used in tg3_int_reenable() below
5029                  * to tell the hw how much work has been processed,
5030                  * so we must read it before checking for more work.
5031                  */
5032                 tnapi->last_tag = sblk->status_tag;
5033                 tnapi->last_irq_tag = tnapi->last_tag;
5034                 rmb();
5035
5036                 /* check for RX/TX work to do */
5037                 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5038                            *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5039                         napi_complete(napi);
5040                         /* Reenable interrupts. */
5041                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5042                         mmiowb();
5043                         break;
5044                 }
5045         }
5046
5047         return work_done;
5048
5049 tx_recovery:
5050         /* work_done is guaranteed to be less than budget. */
5051         napi_complete(napi);
5052         schedule_work(&tp->reset_task);
5053         return work_done;
5054 }
5055
5056 static int tg3_poll(struct napi_struct *napi, int budget)
5057 {
5058         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5059         struct tg3 *tp = tnapi->tp;
5060         int work_done = 0;
5061         struct tg3_hw_status *sblk = tnapi->hw_status;
5062
5063         while (1) {
5064                 tg3_poll_link(tp);
5065
5066                 work_done = tg3_poll_work(tnapi, work_done, budget);
5067
5068                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5069                         goto tx_recovery;
5070
5071                 if (unlikely(work_done >= budget))
5072                         break;
5073
5074                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5075                         /* tp->last_tag is used in tg3_int_reenable() below
5076                          * to tell the hw how much work has been processed,
5077                          * so we must read it before checking for more work.
5078                          */
5079                         tnapi->last_tag = sblk->status_tag;
5080                         tnapi->last_irq_tag = tnapi->last_tag;
5081                         rmb();
5082                 } else
5083                         sblk->status &= ~SD_STATUS_UPDATED;
5084
5085                 if (likely(!tg3_has_work(tnapi))) {
5086                         napi_complete(napi);
5087                         tg3_int_reenable(tnapi);
5088                         break;
5089                 }
5090         }
5091
5092         return work_done;
5093
5094 tx_recovery:
5095         /* work_done is guaranteed to be less than budget. */
5096         napi_complete(napi);
5097         schedule_work(&tp->reset_task);
5098         return work_done;
5099 }
5100
5101 static void tg3_irq_quiesce(struct tg3 *tp)
5102 {
5103         int i;
5104
5105         BUG_ON(tp->irq_sync);
5106
5107         tp->irq_sync = 1;
5108         smp_mb();
5109
5110         for (i = 0; i < tp->irq_cnt; i++)
5111                 synchronize_irq(tp->napi[i].irq_vec);
5112 }
5113
5114 static inline int tg3_irq_sync(struct tg3 *tp)
5115 {
5116         return tp->irq_sync;
5117 }
5118
5119 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5120  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5121  * with as well.  Most of the time, this is not necessary except when
5122  * shutting down the device.
5123  */
5124 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5125 {
5126         spin_lock_bh(&tp->lock);
5127         if (irq_sync)
5128                 tg3_irq_quiesce(tp);
5129 }
5130
5131 static inline void tg3_full_unlock(struct tg3 *tp)
5132 {
5133         spin_unlock_bh(&tp->lock);
5134 }
5135
5136 /* One-shot MSI handler - Chip automatically disables interrupt
5137  * after sending MSI so driver doesn't have to do it.
5138  */
5139 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5140 {
5141         struct tg3_napi *tnapi = dev_id;
5142         struct tg3 *tp = tnapi->tp;
5143
5144         prefetch(tnapi->hw_status);
5145         if (tnapi->rx_rcb)
5146                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5147
5148         if (likely(!tg3_irq_sync(tp)))
5149                 napi_schedule(&tnapi->napi);
5150
5151         return IRQ_HANDLED;
5152 }
5153
5154 /* MSI ISR - No need to check for interrupt sharing and no need to
5155  * flush status block and interrupt mailbox. PCI ordering rules
5156  * guarantee that MSI will arrive after the status block.
5157  */
5158 static irqreturn_t tg3_msi(int irq, void *dev_id)
5159 {
5160         struct tg3_napi *tnapi = dev_id;
5161         struct tg3 *tp = tnapi->tp;
5162
5163         prefetch(tnapi->hw_status);
5164         if (tnapi->rx_rcb)
5165                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5166         /*
5167          * Writing any value to intr-mbox-0 clears PCI INTA# and
5168          * chip-internal interrupt pending events.
5169          * Writing non-zero to intr-mbox-0 additional tells the
5170          * NIC to stop sending us irqs, engaging "in-intr-handler"
5171          * event coalescing.
5172          */
5173         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5174         if (likely(!tg3_irq_sync(tp)))
5175                 napi_schedule(&tnapi->napi);
5176
5177         return IRQ_RETVAL(1);
5178 }
5179
5180 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5181 {
5182         struct tg3_napi *tnapi = dev_id;
5183         struct tg3 *tp = tnapi->tp;
5184         struct tg3_hw_status *sblk = tnapi->hw_status;
5185         unsigned int handled = 1;
5186
5187         /* In INTx mode, it is possible for the interrupt to arrive at
5188          * the CPU before the status block posted prior to the interrupt.
5189          * Reading the PCI State register will confirm whether the
5190          * interrupt is ours and will flush the status block.
5191          */
5192         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5193                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5194                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5195                         handled = 0;
5196                         goto out;
5197                 }
5198         }
5199
5200         /*
5201          * Writing any value to intr-mbox-0 clears PCI INTA# and
5202          * chip-internal interrupt pending events.
5203          * Writing non-zero to intr-mbox-0 additional tells the
5204          * NIC to stop sending us irqs, engaging "in-intr-handler"
5205          * event coalescing.
5206          *
5207          * Flush the mailbox to de-assert the IRQ immediately to prevent
5208          * spurious interrupts.  The flush impacts performance but
5209          * excessive spurious interrupts can be worse in some cases.
5210          */
5211         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5212         if (tg3_irq_sync(tp))
5213                 goto out;
5214         sblk->status &= ~SD_STATUS_UPDATED;
5215         if (likely(tg3_has_work(tnapi))) {
5216                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5217                 napi_schedule(&tnapi->napi);
5218         } else {
5219                 /* No work, shared interrupt perhaps?  re-enable
5220                  * interrupts, and flush that PCI write
5221                  */
5222                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5223                                0x00000000);
5224         }
5225 out:
5226         return IRQ_RETVAL(handled);
5227 }
5228
5229 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5230 {
5231         struct tg3_napi *tnapi = dev_id;
5232         struct tg3 *tp = tnapi->tp;
5233         struct tg3_hw_status *sblk = tnapi->hw_status;
5234         unsigned int handled = 1;
5235
5236         /* In INTx mode, it is possible for the interrupt to arrive at
5237          * the CPU before the status block posted prior to the interrupt.
5238          * Reading the PCI State register will confirm whether the
5239          * interrupt is ours and will flush the status block.
5240          */
5241         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5242                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5243                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5244                         handled = 0;
5245                         goto out;
5246                 }
5247         }
5248
5249         /*
5250          * writing any value to intr-mbox-0 clears PCI INTA# and
5251          * chip-internal interrupt pending events.
5252          * writing non-zero to intr-mbox-0 additional tells the
5253          * NIC to stop sending us irqs, engaging "in-intr-handler"
5254          * event coalescing.
5255          *
5256          * Flush the mailbox to de-assert the IRQ immediately to prevent
5257          * spurious interrupts.  The flush impacts performance but
5258          * excessive spurious interrupts can be worse in some cases.
5259          */
5260         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5261
5262         /*
5263          * In a shared interrupt configuration, sometimes other devices'
5264          * interrupts will scream.  We record the current status tag here
5265          * so that the above check can report that the screaming interrupts
5266          * are unhandled.  Eventually they will be silenced.
5267          */
5268         tnapi->last_irq_tag = sblk->status_tag;
5269
5270         if (tg3_irq_sync(tp))
5271                 goto out;
5272
5273         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5274
5275         napi_schedule(&tnapi->napi);
5276
5277 out:
5278         return IRQ_RETVAL(handled);
5279 }
5280
5281 /* ISR for interrupt test */
5282 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5283 {
5284         struct tg3_napi *tnapi = dev_id;
5285         struct tg3 *tp = tnapi->tp;
5286         struct tg3_hw_status *sblk = tnapi->hw_status;
5287
5288         if ((sblk->status & SD_STATUS_UPDATED) ||
5289             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5290                 tg3_disable_ints(tp);
5291                 return IRQ_RETVAL(1);
5292         }
5293         return IRQ_RETVAL(0);
5294 }
5295
5296 static int tg3_init_hw(struct tg3 *, int);
5297 static int tg3_halt(struct tg3 *, int, int);
5298
5299 /* Restart hardware after configuration changes, self-test, etc.
5300  * Invoked with tp->lock held.
5301  */
5302 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5303         __releases(tp->lock)
5304         __acquires(tp->lock)
5305 {
5306         int err;
5307
5308         err = tg3_init_hw(tp, reset_phy);
5309         if (err) {
5310                 netdev_err(tp->dev,
5311                            "Failed to re-initialize device, aborting\n");
5312                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5313                 tg3_full_unlock(tp);
5314                 del_timer_sync(&tp->timer);
5315                 tp->irq_sync = 0;
5316                 tg3_napi_enable(tp);
5317                 dev_close(tp->dev);
5318                 tg3_full_lock(tp, 0);
5319         }
5320         return err;
5321 }
5322
5323 #ifdef CONFIG_NET_POLL_CONTROLLER
5324 static void tg3_poll_controller(struct net_device *dev)
5325 {
5326         int i;
5327         struct tg3 *tp = netdev_priv(dev);
5328
5329         for (i = 0; i < tp->irq_cnt; i++)
5330                 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5331 }
5332 #endif
5333
5334 static void tg3_reset_task(struct work_struct *work)
5335 {
5336         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5337         int err;
5338         unsigned int restart_timer;
5339
5340         tg3_full_lock(tp, 0);
5341
5342         if (!netif_running(tp->dev)) {
5343                 tg3_full_unlock(tp);
5344                 return;
5345         }
5346
5347         tg3_full_unlock(tp);
5348
5349         tg3_phy_stop(tp);
5350
5351         tg3_netif_stop(tp);
5352
5353         tg3_full_lock(tp, 1);
5354
5355         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5356         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5357
5358         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5359                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5360                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5361                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5362                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5363         }
5364
5365         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5366         err = tg3_init_hw(tp, 1);
5367         if (err)
5368                 goto out;
5369
5370         tg3_netif_start(tp);
5371
5372         if (restart_timer)
5373                 mod_timer(&tp->timer, jiffies + 1);
5374
5375 out:
5376         tg3_full_unlock(tp);
5377
5378         if (!err)
5379                 tg3_phy_start(tp);
5380 }
5381
5382 static void tg3_dump_short_state(struct tg3 *tp)
5383 {
5384         netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5385                    tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5386         netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5387                    tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5388 }
5389
5390 static void tg3_tx_timeout(struct net_device *dev)
5391 {
5392         struct tg3 *tp = netdev_priv(dev);
5393
5394         if (netif_msg_tx_err(tp)) {
5395                 netdev_err(dev, "transmit timed out, resetting\n");
5396                 tg3_dump_short_state(tp);
5397         }
5398
5399         schedule_work(&tp->reset_task);
5400 }
5401
5402 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5403 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5404 {
5405         u32 base = (u32) mapping & 0xffffffff;
5406
5407         return ((base > 0xffffdcc0) &&
5408                 (base + len + 8 < base));
5409 }
5410
5411 /* Test for DMA addresses > 40-bit */
5412 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5413                                           int len)
5414 {
5415 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5416         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5417                 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5418         return 0;
5419 #else
5420         return 0;
5421 #endif
5422 }
5423
5424 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5425
5426 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5427 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5428                                        struct sk_buff *skb, u32 last_plus_one,
5429                                        u32 *start, u32 base_flags, u32 mss)
5430 {
5431         struct tg3 *tp = tnapi->tp;
5432         struct sk_buff *new_skb;
5433         dma_addr_t new_addr = 0;
5434         u32 entry = *start;
5435         int i, ret = 0;
5436
5437         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5438                 new_skb = skb_copy(skb, GFP_ATOMIC);
5439         else {
5440                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5441
5442                 new_skb = skb_copy_expand(skb,
5443                                           skb_headroom(skb) + more_headroom,
5444                                           skb_tailroom(skb), GFP_ATOMIC);
5445         }
5446
5447         if (!new_skb) {
5448                 ret = -1;
5449         } else {
5450                 /* New SKB is guaranteed to be linear. */
5451                 entry = *start;
5452                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5453                                           PCI_DMA_TODEVICE);
5454                 /* Make sure the mapping succeeded */
5455                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5456                         ret = -1;
5457                         dev_kfree_skb(new_skb);
5458                         new_skb = NULL;
5459
5460                 /* Make sure new skb does not cross any 4G boundaries.
5461                  * Drop the packet if it does.
5462                  */
5463                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5464                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5465                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5466                                          PCI_DMA_TODEVICE);
5467                         ret = -1;
5468                         dev_kfree_skb(new_skb);
5469                         new_skb = NULL;
5470                 } else {
5471                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5472                                     base_flags, 1 | (mss << 1));
5473                         *start = NEXT_TX(entry);
5474                 }
5475         }
5476
5477         /* Now clean up the sw ring entries. */
5478         i = 0;
5479         while (entry != last_plus_one) {
5480                 int len;
5481
5482                 if (i == 0)
5483                         len = skb_headlen(skb);
5484                 else
5485                         len = skb_shinfo(skb)->frags[i-1].size;
5486
5487                 pci_unmap_single(tp->pdev,
5488                                  dma_unmap_addr(&tnapi->tx_buffers[entry],
5489                                                 mapping),
5490                                  len, PCI_DMA_TODEVICE);
5491                 if (i == 0) {
5492                         tnapi->tx_buffers[entry].skb = new_skb;
5493                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5494                                            new_addr);
5495                 } else {
5496                         tnapi->tx_buffers[entry].skb = NULL;
5497                 }
5498                 entry = NEXT_TX(entry);
5499                 i++;
5500         }
5501
5502         dev_kfree_skb(skb);
5503
5504         return ret;
5505 }
5506
5507 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5508                         dma_addr_t mapping, int len, u32 flags,
5509                         u32 mss_and_is_end)
5510 {
5511         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5512         int is_end = (mss_and_is_end & 0x1);
5513         u32 mss = (mss_and_is_end >> 1);
5514         u32 vlan_tag = 0;
5515
5516         if (is_end)
5517                 flags |= TXD_FLAG_END;
5518         if (flags & TXD_FLAG_VLAN) {
5519                 vlan_tag = flags >> 16;
5520                 flags &= 0xffff;
5521         }
5522         vlan_tag |= (mss << TXD_MSS_SHIFT);
5523
5524         txd->addr_hi = ((u64) mapping >> 32);
5525         txd->addr_lo = ((u64) mapping & 0xffffffff);
5526         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5527         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5528 }
5529
5530 /* hard_start_xmit for devices that don't have any bugs and
5531  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5532  */
5533 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5534                                   struct net_device *dev)
5535 {
5536         struct tg3 *tp = netdev_priv(dev);
5537         u32 len, entry, base_flags, mss;
5538         dma_addr_t mapping;
5539         struct tg3_napi *tnapi;
5540         struct netdev_queue *txq;
5541         unsigned int i, last;
5542
5543         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5544         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5545         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5546                 tnapi++;
5547
5548         /* We are running in BH disabled context with netif_tx_lock
5549          * and TX reclaim runs via tp->napi.poll inside of a software
5550          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5551          * no IRQ context deadlocks to worry about either.  Rejoice!
5552          */
5553         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5554                 if (!netif_tx_queue_stopped(txq)) {
5555                         netif_tx_stop_queue(txq);
5556
5557                         /* This is a hard error, log it. */
5558                         netdev_err(dev,
5559                                    "BUG! Tx Ring full when queue awake!\n");
5560                 }
5561                 return NETDEV_TX_BUSY;
5562         }
5563
5564         entry = tnapi->tx_prod;
5565         base_flags = 0;
5566         mss = skb_shinfo(skb)->gso_size;
5567         if (mss) {
5568                 int tcp_opt_len, ip_tcp_len;
5569                 u32 hdrlen;
5570
5571                 if (skb_header_cloned(skb) &&
5572                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5573                         dev_kfree_skb(skb);
5574                         goto out_unlock;
5575                 }
5576
5577                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5578                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5579                 else {
5580                         struct iphdr *iph = ip_hdr(skb);
5581
5582                         tcp_opt_len = tcp_optlen(skb);
5583                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5584
5585                         iph->check = 0;
5586                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5587                         hdrlen = ip_tcp_len + tcp_opt_len;
5588                 }
5589
5590                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5591                         mss |= (hdrlen & 0xc) << 12;
5592                         if (hdrlen & 0x10)
5593                                 base_flags |= 0x00000010;
5594                         base_flags |= (hdrlen & 0x3e0) << 5;
5595                 } else
5596                         mss |= hdrlen << 9;
5597
5598                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5599                                TXD_FLAG_CPU_POST_DMA);
5600
5601                 tcp_hdr(skb)->check = 0;
5602
5603         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5604                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5605         }
5606
5607 #if TG3_VLAN_TAG_USED
5608         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5609                 base_flags |= (TXD_FLAG_VLAN |
5610                                (vlan_tx_tag_get(skb) << 16));
5611 #endif
5612
5613         len = skb_headlen(skb);
5614
5615         /* Queue skb data, a.k.a. the main skb fragment. */
5616         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5617         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5618                 dev_kfree_skb(skb);
5619                 goto out_unlock;
5620         }
5621
5622         tnapi->tx_buffers[entry].skb = skb;
5623         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5624
5625         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5626             !mss && skb->len > ETH_DATA_LEN)
5627                 base_flags |= TXD_FLAG_JMB_PKT;
5628
5629         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5630                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5631
5632         entry = NEXT_TX(entry);
5633
5634         /* Now loop through additional data fragments, and queue them. */
5635         if (skb_shinfo(skb)->nr_frags > 0) {
5636                 last = skb_shinfo(skb)->nr_frags - 1;
5637                 for (i = 0; i <= last; i++) {
5638                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5639
5640                         len = frag->size;
5641                         mapping = pci_map_page(tp->pdev,
5642                                                frag->page,
5643                                                frag->page_offset,
5644                                                len, PCI_DMA_TODEVICE);
5645                         if (pci_dma_mapping_error(tp->pdev, mapping))
5646                                 goto dma_error;
5647
5648                         tnapi->tx_buffers[entry].skb = NULL;
5649                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5650                                            mapping);
5651
5652                         tg3_set_txd(tnapi, entry, mapping, len,
5653                                     base_flags, (i == last) | (mss << 1));
5654
5655                         entry = NEXT_TX(entry);
5656                 }
5657         }
5658
5659         /* Packets are ready, update Tx producer idx local and on card. */
5660         tw32_tx_mbox(tnapi->prodmbox, entry);
5661
5662         tnapi->tx_prod = entry;
5663         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5664                 netif_tx_stop_queue(txq);
5665
5666                 /* netif_tx_stop_queue() must be done before checking
5667                  * checking tx index in tg3_tx_avail() below, because in
5668                  * tg3_tx(), we update tx index before checking for
5669                  * netif_tx_queue_stopped().
5670                  */
5671                 smp_mb();
5672                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5673                         netif_tx_wake_queue(txq);
5674         }
5675
5676 out_unlock:
5677         mmiowb();
5678
5679         return NETDEV_TX_OK;
5680
5681 dma_error:
5682         last = i;
5683         entry = tnapi->tx_prod;
5684         tnapi->tx_buffers[entry].skb = NULL;
5685         pci_unmap_single(tp->pdev,
5686                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5687                          skb_headlen(skb),
5688                          PCI_DMA_TODEVICE);
5689         for (i = 0; i <= last; i++) {
5690                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5691                 entry = NEXT_TX(entry);
5692
5693                 pci_unmap_page(tp->pdev,
5694                                dma_unmap_addr(&tnapi->tx_buffers[entry],
5695                                               mapping),
5696                                frag->size, PCI_DMA_TODEVICE);
5697         }
5698
5699         dev_kfree_skb(skb);
5700         return NETDEV_TX_OK;
5701 }
5702
5703 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5704                                           struct net_device *);
5705
5706 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5707  * TSO header is greater than 80 bytes.
5708  */
5709 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5710 {
5711         struct sk_buff *segs, *nskb;
5712         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5713
5714         /* Estimate the number of fragments in the worst case */
5715         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5716                 netif_stop_queue(tp->dev);
5717
5718                 /* netif_tx_stop_queue() must be done before checking
5719                  * checking tx index in tg3_tx_avail() below, because in
5720                  * tg3_tx(), we update tx index before checking for
5721                  * netif_tx_queue_stopped().
5722                  */
5723                 smp_mb();
5724                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5725                         return NETDEV_TX_BUSY;
5726
5727                 netif_wake_queue(tp->dev);
5728         }
5729
5730         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5731         if (IS_ERR(segs))
5732                 goto tg3_tso_bug_end;
5733
5734         do {
5735                 nskb = segs;
5736                 segs = segs->next;
5737                 nskb->next = NULL;
5738                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5739         } while (segs);
5740
5741 tg3_tso_bug_end:
5742         dev_kfree_skb(skb);
5743
5744         return NETDEV_TX_OK;
5745 }
5746
5747 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5748  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5749  */
5750 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5751                                           struct net_device *dev)
5752 {
5753         struct tg3 *tp = netdev_priv(dev);
5754         u32 len, entry, base_flags, mss;
5755         int would_hit_hwbug;
5756         dma_addr_t mapping;
5757         struct tg3_napi *tnapi;
5758         struct netdev_queue *txq;
5759         unsigned int i, last;
5760
5761         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5762         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5763         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5764                 tnapi++;
5765
5766         /* We are running in BH disabled context with netif_tx_lock
5767          * and TX reclaim runs via tp->napi.poll inside of a software
5768          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5769          * no IRQ context deadlocks to worry about either.  Rejoice!
5770          */
5771         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5772                 if (!netif_tx_queue_stopped(txq)) {
5773                         netif_tx_stop_queue(txq);
5774
5775                         /* This is a hard error, log it. */
5776                         netdev_err(dev,
5777                                    "BUG! Tx Ring full when queue awake!\n");
5778                 }
5779                 return NETDEV_TX_BUSY;
5780         }
5781
5782         entry = tnapi->tx_prod;
5783         base_flags = 0;
5784         if (skb->ip_summed == CHECKSUM_PARTIAL)
5785                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5786
5787         mss = skb_shinfo(skb)->gso_size;
5788         if (mss) {
5789                 struct iphdr *iph;
5790                 u32 tcp_opt_len, hdr_len;
5791
5792                 if (skb_header_cloned(skb) &&
5793                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5794                         dev_kfree_skb(skb);
5795                         goto out_unlock;
5796                 }
5797
5798                 iph = ip_hdr(skb);
5799                 tcp_opt_len = tcp_optlen(skb);
5800
5801                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
5802                         hdr_len = skb_headlen(skb) - ETH_HLEN;
5803                 } else {
5804                         u32 ip_tcp_len;
5805
5806                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5807                         hdr_len = ip_tcp_len + tcp_opt_len;
5808
5809                         iph->check = 0;
5810                         iph->tot_len = htons(mss + hdr_len);
5811                 }
5812
5813                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5814                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5815                         return tg3_tso_bug(tp, skb);
5816
5817                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5818                                TXD_FLAG_CPU_POST_DMA);
5819
5820                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5821                         tcp_hdr(skb)->check = 0;
5822                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5823                 } else
5824                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5825                                                                  iph->daddr, 0,
5826                                                                  IPPROTO_TCP,
5827                                                                  0);
5828
5829                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5830                         mss |= (hdr_len & 0xc) << 12;
5831                         if (hdr_len & 0x10)
5832                                 base_flags |= 0x00000010;
5833                         base_flags |= (hdr_len & 0x3e0) << 5;
5834                 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5835                         mss |= hdr_len << 9;
5836                 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5837                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5838                         if (tcp_opt_len || iph->ihl > 5) {
5839                                 int tsflags;
5840
5841                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5842                                 mss |= (tsflags << 11);
5843                         }
5844                 } else {
5845                         if (tcp_opt_len || iph->ihl > 5) {
5846                                 int tsflags;
5847
5848                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5849                                 base_flags |= tsflags << 12;
5850                         }
5851                 }
5852         }
5853 #if TG3_VLAN_TAG_USED
5854         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5855                 base_flags |= (TXD_FLAG_VLAN |
5856                                (vlan_tx_tag_get(skb) << 16));
5857 #endif
5858
5859         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5860             !mss && skb->len > ETH_DATA_LEN)
5861                 base_flags |= TXD_FLAG_JMB_PKT;
5862
5863         len = skb_headlen(skb);
5864
5865         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5866         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5867                 dev_kfree_skb(skb);
5868                 goto out_unlock;
5869         }
5870
5871         tnapi->tx_buffers[entry].skb = skb;
5872         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5873
5874         would_hit_hwbug = 0;
5875
5876         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5877                 would_hit_hwbug = 1;
5878
5879         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5880             tg3_4g_overflow_test(mapping, len))
5881                 would_hit_hwbug = 1;
5882
5883         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5884             tg3_40bit_overflow_test(tp, mapping, len))
5885                 would_hit_hwbug = 1;
5886
5887         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5888                 would_hit_hwbug = 1;
5889
5890         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5891                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5892
5893         entry = NEXT_TX(entry);
5894
5895         /* Now loop through additional data fragments, and queue them. */
5896         if (skb_shinfo(skb)->nr_frags > 0) {
5897                 last = skb_shinfo(skb)->nr_frags - 1;
5898                 for (i = 0; i <= last; i++) {
5899                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5900
5901                         len = frag->size;
5902                         mapping = pci_map_page(tp->pdev,
5903                                                frag->page,
5904                                                frag->page_offset,
5905                                                len, PCI_DMA_TODEVICE);
5906
5907                         tnapi->tx_buffers[entry].skb = NULL;
5908                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5909                                            mapping);
5910                         if (pci_dma_mapping_error(tp->pdev, mapping))
5911                                 goto dma_error;
5912
5913                         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5914                             len <= 8)
5915                                 would_hit_hwbug = 1;
5916
5917                         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5918                             tg3_4g_overflow_test(mapping, len))
5919                                 would_hit_hwbug = 1;
5920
5921                         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5922                             tg3_40bit_overflow_test(tp, mapping, len))
5923                                 would_hit_hwbug = 1;
5924
5925                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5926                                 tg3_set_txd(tnapi, entry, mapping, len,
5927                                             base_flags, (i == last)|(mss << 1));
5928                         else
5929                                 tg3_set_txd(tnapi, entry, mapping, len,
5930                                             base_flags, (i == last));
5931
5932                         entry = NEXT_TX(entry);
5933                 }
5934         }
5935
5936         if (would_hit_hwbug) {
5937                 u32 last_plus_one = entry;
5938                 u32 start;
5939
5940                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5941                 start &= (TG3_TX_RING_SIZE - 1);
5942
5943                 /* If the workaround fails due to memory/mapping
5944                  * failure, silently drop this packet.
5945                  */
5946                 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
5947                                                 &start, base_flags, mss))
5948                         goto out_unlock;
5949
5950                 entry = start;
5951         }
5952
5953         /* Packets are ready, update Tx producer idx local and on card. */
5954         tw32_tx_mbox(tnapi->prodmbox, entry);
5955
5956         tnapi->tx_prod = entry;
5957         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5958                 netif_tx_stop_queue(txq);
5959
5960                 /* netif_tx_stop_queue() must be done before checking
5961                  * checking tx index in tg3_tx_avail() below, because in
5962                  * tg3_tx(), we update tx index before checking for
5963                  * netif_tx_queue_stopped().
5964                  */
5965                 smp_mb();
5966                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5967                         netif_tx_wake_queue(txq);
5968         }
5969
5970 out_unlock:
5971         mmiowb();
5972
5973         return NETDEV_TX_OK;
5974
5975 dma_error:
5976         last = i;
5977         entry = tnapi->tx_prod;
5978         tnapi->tx_buffers[entry].skb = NULL;
5979         pci_unmap_single(tp->pdev,
5980                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5981                          skb_headlen(skb),
5982                          PCI_DMA_TODEVICE);
5983         for (i = 0; i <= last; i++) {
5984                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5985                 entry = NEXT_TX(entry);
5986
5987                 pci_unmap_page(tp->pdev,
5988                                dma_unmap_addr(&tnapi->tx_buffers[entry],
5989                                               mapping),
5990                                frag->size, PCI_DMA_TODEVICE);
5991         }
5992
5993         dev_kfree_skb(skb);
5994         return NETDEV_TX_OK;
5995 }
5996
5997 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5998                                int new_mtu)
5999 {
6000         dev->mtu = new_mtu;
6001
6002         if (new_mtu > ETH_DATA_LEN) {
6003                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6004                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
6005                         ethtool_op_set_tso(dev, 0);
6006                 } else {
6007                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
6008                 }
6009         } else {
6010                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6011                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
6012                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
6013         }
6014 }
6015
6016 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
6017 {
6018         struct tg3 *tp = netdev_priv(dev);
6019         int err;
6020
6021         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
6022                 return -EINVAL;
6023
6024         if (!netif_running(dev)) {
6025                 /* We'll just catch it later when the
6026                  * device is up'd.
6027                  */
6028                 tg3_set_mtu(dev, tp, new_mtu);
6029                 return 0;
6030         }
6031
6032         tg3_phy_stop(tp);
6033
6034         tg3_netif_stop(tp);
6035
6036         tg3_full_lock(tp, 1);
6037
6038         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6039
6040         tg3_set_mtu(dev, tp, new_mtu);
6041
6042         err = tg3_restart_hw(tp, 0);
6043
6044         if (!err)
6045                 tg3_netif_start(tp);
6046
6047         tg3_full_unlock(tp);
6048
6049         if (!err)
6050                 tg3_phy_start(tp);
6051
6052         return err;
6053 }
6054
6055 static void tg3_rx_prodring_free(struct tg3 *tp,
6056                                  struct tg3_rx_prodring_set *tpr)
6057 {
6058         int i;
6059
6060         if (tpr != &tp->prodring[0]) {
6061                 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
6062                      i = (i + 1) % TG3_RX_RING_SIZE)
6063                         tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6064                                         tp->rx_pkt_map_sz);
6065
6066                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6067                         for (i = tpr->rx_jmb_cons_idx;
6068                              i != tpr->rx_jmb_prod_idx;
6069                              i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
6070                                 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6071                                                 TG3_RX_JMB_MAP_SZ);
6072                         }
6073                 }
6074
6075                 return;
6076         }
6077
6078         for (i = 0; i < TG3_RX_RING_SIZE; i++)
6079                 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6080                                 tp->rx_pkt_map_sz);
6081
6082         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6083                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
6084                         tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6085                                         TG3_RX_JMB_MAP_SZ);
6086         }
6087 }
6088
6089 /* Initialize rx rings for packet processing.
6090  *
6091  * The chip has been shut down and the driver detached from
6092  * the networking, so no interrupts or new tx packets will
6093  * end up in the driver.  tp->{tx,}lock are held and thus
6094  * we may not sleep.
6095  */
6096 static int tg3_rx_prodring_alloc(struct tg3 *tp,
6097                                  struct tg3_rx_prodring_set *tpr)
6098 {
6099         u32 i, rx_pkt_dma_sz;
6100
6101         tpr->rx_std_cons_idx = 0;
6102         tpr->rx_std_prod_idx = 0;
6103         tpr->rx_jmb_cons_idx = 0;
6104         tpr->rx_jmb_prod_idx = 0;
6105
6106         if (tpr != &tp->prodring[0]) {
6107                 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
6108                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
6109                         memset(&tpr->rx_jmb_buffers[0], 0,
6110                                TG3_RX_JMB_BUFF_RING_SIZE);
6111                 goto done;
6112         }
6113
6114         /* Zero out all descriptors. */
6115         memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
6116
6117         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6118         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
6119             tp->dev->mtu > ETH_DATA_LEN)
6120                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6121         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6122
6123         /* Initialize invariants of the rings, we only set this
6124          * stuff once.  This works because the card does not
6125          * write into the rx buffer posting rings.
6126          */
6127         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
6128                 struct tg3_rx_buffer_desc *rxd;
6129
6130                 rxd = &tpr->rx_std[i];
6131                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6132                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6133                 rxd->opaque = (RXD_OPAQUE_RING_STD |
6134                                (i << RXD_OPAQUE_INDEX_SHIFT));
6135         }
6136
6137         /* Now allocate fresh SKBs for each rx ring. */
6138         for (i = 0; i < tp->rx_pending; i++) {
6139                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6140                         netdev_warn(tp->dev,
6141                                     "Using a smaller RX standard ring. Only "
6142                                     "%d out of %d buffers were allocated "
6143                                     "successfully\n", i, tp->rx_pending);
6144                         if (i == 0)
6145                                 goto initfail;
6146                         tp->rx_pending = i;
6147                         break;
6148                 }
6149         }
6150
6151         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6152                 goto done;
6153
6154         memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
6155
6156         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
6157                 goto done;
6158
6159         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
6160                 struct tg3_rx_buffer_desc *rxd;
6161
6162                 rxd = &tpr->rx_jmb[i].std;
6163                 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6164                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6165                                   RXD_FLAG_JUMBO;
6166                 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6167                        (i << RXD_OPAQUE_INDEX_SHIFT));
6168         }
6169
6170         for (i = 0; i < tp->rx_jumbo_pending; i++) {
6171                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
6172                         netdev_warn(tp->dev,
6173                                     "Using a smaller RX jumbo ring. Only %d "
6174                                     "out of %d buffers were allocated "
6175                                     "successfully\n", i, tp->rx_jumbo_pending);
6176                         if (i == 0)
6177                                 goto initfail;
6178                         tp->rx_jumbo_pending = i;
6179                         break;
6180                 }
6181         }
6182
6183 done:
6184         return 0;
6185
6186 initfail:
6187         tg3_rx_prodring_free(tp, tpr);
6188         return -ENOMEM;
6189 }
6190
6191 static void tg3_rx_prodring_fini(struct tg3 *tp,
6192                                  struct tg3_rx_prodring_set *tpr)
6193 {
6194         kfree(tpr->rx_std_buffers);
6195         tpr->rx_std_buffers = NULL;
6196         kfree(tpr->rx_jmb_buffers);
6197         tpr->rx_jmb_buffers = NULL;
6198         if (tpr->rx_std) {
6199                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
6200                                     tpr->rx_std, tpr->rx_std_mapping);
6201                 tpr->rx_std = NULL;
6202         }
6203         if (tpr->rx_jmb) {
6204                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
6205                                     tpr->rx_jmb, tpr->rx_jmb_mapping);
6206                 tpr->rx_jmb = NULL;
6207         }
6208 }
6209
6210 static int tg3_rx_prodring_init(struct tg3 *tp,
6211                                 struct tg3_rx_prodring_set *tpr)
6212 {
6213         tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
6214         if (!tpr->rx_std_buffers)
6215                 return -ENOMEM;
6216
6217         tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6218                                            &tpr->rx_std_mapping);
6219         if (!tpr->rx_std)
6220                 goto err_out;
6221
6222         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6223                 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
6224                                               GFP_KERNEL);
6225                 if (!tpr->rx_jmb_buffers)
6226                         goto err_out;
6227
6228                 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6229                                                    TG3_RX_JUMBO_RING_BYTES,
6230                                                    &tpr->rx_jmb_mapping);
6231                 if (!tpr->rx_jmb)
6232                         goto err_out;
6233         }
6234
6235         return 0;
6236
6237 err_out:
6238         tg3_rx_prodring_fini(tp, tpr);
6239         return -ENOMEM;
6240 }
6241
6242 /* Free up pending packets in all rx/tx rings.
6243  *
6244  * The chip has been shut down and the driver detached from
6245  * the networking, so no interrupts or new tx packets will
6246  * end up in the driver.  tp->{tx,}lock is not held and we are not
6247  * in an interrupt context and thus may sleep.
6248  */
6249 static void tg3_free_rings(struct tg3 *tp)
6250 {
6251         int i, j;
6252
6253         for (j = 0; j < tp->irq_cnt; j++) {
6254                 struct tg3_napi *tnapi = &tp->napi[j];
6255
6256                 tg3_rx_prodring_free(tp, &tp->prodring[j]);
6257
6258                 if (!tnapi->tx_buffers)
6259                         continue;
6260
6261                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6262                         struct ring_info *txp;
6263                         struct sk_buff *skb;
6264                         unsigned int k;
6265
6266                         txp = &tnapi->tx_buffers[i];
6267                         skb = txp->skb;
6268
6269                         if (skb == NULL) {
6270                                 i++;
6271                                 continue;
6272                         }
6273
6274                         pci_unmap_single(tp->pdev,
6275                                          dma_unmap_addr(txp, mapping),
6276                                          skb_headlen(skb),
6277                                          PCI_DMA_TODEVICE);
6278                         txp->skb = NULL;
6279
6280                         i++;
6281
6282                         for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6283                                 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6284                                 pci_unmap_page(tp->pdev,
6285                                                dma_unmap_addr(txp, mapping),
6286                                                skb_shinfo(skb)->frags[k].size,
6287                                                PCI_DMA_TODEVICE);
6288                                 i++;
6289                         }
6290
6291                         dev_kfree_skb_any(skb);
6292                 }
6293         }
6294 }
6295
6296 /* Initialize tx/rx rings for packet processing.
6297  *
6298  * The chip has been shut down and the driver detached from
6299  * the networking, so no interrupts or new tx packets will
6300  * end up in the driver.  tp->{tx,}lock are held and thus
6301  * we may not sleep.
6302  */
6303 static int tg3_init_rings(struct tg3 *tp)
6304 {
6305         int i;
6306
6307         /* Free up all the SKBs. */
6308         tg3_free_rings(tp);
6309
6310         for (i = 0; i < tp->irq_cnt; i++) {
6311                 struct tg3_napi *tnapi = &tp->napi[i];
6312
6313                 tnapi->last_tag = 0;
6314                 tnapi->last_irq_tag = 0;
6315                 tnapi->hw_status->status = 0;
6316                 tnapi->hw_status->status_tag = 0;
6317                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6318
6319                 tnapi->tx_prod = 0;
6320                 tnapi->tx_cons = 0;
6321                 if (tnapi->tx_ring)
6322                         memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6323
6324                 tnapi->rx_rcb_ptr = 0;
6325                 if (tnapi->rx_rcb)
6326                         memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6327
6328                 if (tg3_rx_prodring_alloc(tp, &tp->prodring[i])) {
6329                         tg3_free_rings(tp);
6330                         return -ENOMEM;
6331                 }
6332         }
6333
6334         return 0;
6335 }
6336
6337 /*
6338  * Must not be invoked with interrupt sources disabled and
6339  * the hardware shutdown down.
6340  */
6341 static void tg3_free_consistent(struct tg3 *tp)
6342 {
6343         int i;
6344
6345         for (i = 0; i < tp->irq_cnt; i++) {
6346                 struct tg3_napi *tnapi = &tp->napi[i];
6347
6348                 if (tnapi->tx_ring) {
6349                         pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6350                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
6351                         tnapi->tx_ring = NULL;
6352                 }
6353
6354                 kfree(tnapi->tx_buffers);
6355                 tnapi->tx_buffers = NULL;
6356
6357                 if (tnapi->rx_rcb) {
6358                         pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6359                                             tnapi->rx_rcb,
6360                                             tnapi->rx_rcb_mapping);
6361                         tnapi->rx_rcb = NULL;
6362                 }
6363
6364                 if (tnapi->hw_status) {
6365                         pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6366                                             tnapi->hw_status,
6367                                             tnapi->status_mapping);
6368                         tnapi->hw_status = NULL;
6369                 }
6370         }
6371
6372         if (tp->hw_stats) {
6373                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6374                                     tp->hw_stats, tp->stats_mapping);
6375                 tp->hw_stats = NULL;
6376         }
6377
6378         for (i = 0; i < tp->irq_cnt; i++)
6379                 tg3_rx_prodring_fini(tp, &tp->prodring[i]);
6380 }
6381
6382 /*
6383  * Must not be invoked with interrupt sources disabled and
6384  * the hardware shutdown down.  Can sleep.
6385  */
6386 static int tg3_alloc_consistent(struct tg3 *tp)
6387 {
6388         int i;
6389
6390         for (i = 0; i < tp->irq_cnt; i++) {
6391                 if (tg3_rx_prodring_init(tp, &tp->prodring[i]))
6392                         goto err_out;
6393         }
6394
6395         tp->hw_stats = pci_alloc_consistent(tp->pdev,
6396                                             sizeof(struct tg3_hw_stats),
6397                                             &tp->stats_mapping);
6398         if (!tp->hw_stats)
6399                 goto err_out;
6400
6401         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6402
6403         for (i = 0; i < tp->irq_cnt; i++) {
6404                 struct tg3_napi *tnapi = &tp->napi[i];
6405                 struct tg3_hw_status *sblk;
6406
6407                 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6408                                                         TG3_HW_STATUS_SIZE,
6409                                                         &tnapi->status_mapping);
6410                 if (!tnapi->hw_status)
6411                         goto err_out;
6412
6413                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6414                 sblk = tnapi->hw_status;
6415
6416                 /* If multivector TSS is enabled, vector 0 does not handle
6417                  * tx interrupts.  Don't allocate any resources for it.
6418                  */
6419                 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6420                     (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6421                         tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6422                                                     TG3_TX_RING_SIZE,
6423                                                     GFP_KERNEL);
6424                         if (!tnapi->tx_buffers)
6425                                 goto err_out;
6426
6427                         tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6428                                                               TG3_TX_RING_BYTES,
6429                                                        &tnapi->tx_desc_mapping);
6430                         if (!tnapi->tx_ring)
6431                                 goto err_out;
6432                 }
6433
6434                 /*
6435                  * When RSS is enabled, the status block format changes
6436                  * slightly.  The "rx_jumbo_consumer", "reserved",
6437                  * and "rx_mini_consumer" members get mapped to the
6438                  * other three rx return ring producer indexes.
6439                  */
6440                 switch (i) {
6441                 default:
6442                         tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6443                         break;
6444                 case 2:
6445                         tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6446                         break;
6447                 case 3:
6448                         tnapi->rx_rcb_prod_idx = &sblk->reserved;
6449                         break;
6450                 case 4:
6451                         tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6452                         break;
6453                 }
6454
6455                 tnapi->prodring = &tp->prodring[i];
6456
6457                 /*
6458                  * If multivector RSS is enabled, vector 0 does not handle
6459                  * rx or tx interrupts.  Don't allocate any resources for it.
6460                  */
6461                 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6462                         continue;
6463
6464                 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6465                                                      TG3_RX_RCB_RING_BYTES(tp),
6466                                                      &tnapi->rx_rcb_mapping);
6467                 if (!tnapi->rx_rcb)
6468                         goto err_out;
6469
6470                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6471         }
6472
6473         return 0;
6474
6475 err_out:
6476         tg3_free_consistent(tp);
6477         return -ENOMEM;
6478 }
6479
6480 #define MAX_WAIT_CNT 1000
6481
6482 /* To stop a block, clear the enable bit and poll till it
6483  * clears.  tp->lock is held.
6484  */
6485 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6486 {
6487         unsigned int i;
6488         u32 val;
6489
6490         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6491                 switch (ofs) {
6492                 case RCVLSC_MODE:
6493                 case DMAC_MODE:
6494                 case MBFREE_MODE:
6495                 case BUFMGR_MODE:
6496                 case MEMARB_MODE:
6497                         /* We can't enable/disable these bits of the
6498                          * 5705/5750, just say success.
6499                          */
6500                         return 0;
6501
6502                 default:
6503                         break;
6504                 }
6505         }
6506
6507         val = tr32(ofs);
6508         val &= ~enable_bit;
6509         tw32_f(ofs, val);
6510
6511         for (i = 0; i < MAX_WAIT_CNT; i++) {
6512                 udelay(100);
6513                 val = tr32(ofs);
6514                 if ((val & enable_bit) == 0)
6515                         break;
6516         }
6517
6518         if (i == MAX_WAIT_CNT && !silent) {
6519                 dev_err(&tp->pdev->dev,
6520                         "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6521                         ofs, enable_bit);
6522                 return -ENODEV;
6523         }
6524
6525         return 0;
6526 }
6527
6528 /* tp->lock is held. */
6529 static int tg3_abort_hw(struct tg3 *tp, int silent)
6530 {
6531         int i, err;
6532
6533         tg3_disable_ints(tp);
6534
6535         tp->rx_mode &= ~RX_MODE_ENABLE;
6536         tw32_f(MAC_RX_MODE, tp->rx_mode);
6537         udelay(10);
6538
6539         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6540         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6541         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6542         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6543         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6544         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6545
6546         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6547         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6548         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6549         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6550         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6551         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6552         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6553
6554         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6555         tw32_f(MAC_MODE, tp->mac_mode);
6556         udelay(40);
6557
6558         tp->tx_mode &= ~TX_MODE_ENABLE;
6559         tw32_f(MAC_TX_MODE, tp->tx_mode);
6560
6561         for (i = 0; i < MAX_WAIT_CNT; i++) {
6562                 udelay(100);
6563                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6564                         break;
6565         }
6566         if (i >= MAX_WAIT_CNT) {
6567                 dev_err(&tp->pdev->dev,
6568                         "%s timed out, TX_MODE_ENABLE will not clear "
6569                         "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
6570                 err |= -ENODEV;
6571         }
6572
6573         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6574         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6575         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6576
6577         tw32(FTQ_RESET, 0xffffffff);
6578         tw32(FTQ_RESET, 0x00000000);
6579
6580         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6581         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6582
6583         for (i = 0; i < tp->irq_cnt; i++) {
6584                 struct tg3_napi *tnapi = &tp->napi[i];
6585                 if (tnapi->hw_status)
6586                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6587         }
6588         if (tp->hw_stats)
6589                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6590
6591         return err;
6592 }
6593
6594 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6595 {
6596         int i;
6597         u32 apedata;
6598
6599         /* NCSI does not support APE events */
6600         if (tp->tg3_flags3 & TG3_FLG3_APE_HAS_NCSI)
6601                 return;
6602
6603         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6604         if (apedata != APE_SEG_SIG_MAGIC)
6605                 return;
6606
6607         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6608         if (!(apedata & APE_FW_STATUS_READY))
6609                 return;
6610
6611         /* Wait for up to 1 millisecond for APE to service previous event. */
6612         for (i = 0; i < 10; i++) {
6613                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6614                         return;
6615
6616                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6617
6618                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6619                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6620                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6621
6622                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6623
6624                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6625                         break;
6626
6627                 udelay(100);
6628         }
6629
6630         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6631                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6632 }
6633
6634 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6635 {
6636         u32 event;
6637         u32 apedata;
6638
6639         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6640                 return;
6641
6642         switch (kind) {
6643         case RESET_KIND_INIT:
6644                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6645                                 APE_HOST_SEG_SIG_MAGIC);
6646                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6647                                 APE_HOST_SEG_LEN_MAGIC);
6648                 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6649                 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6650                 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6651                         APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
6652                 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6653                                 APE_HOST_BEHAV_NO_PHYLOCK);
6654                 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
6655                                     TG3_APE_HOST_DRVR_STATE_START);
6656
6657                 event = APE_EVENT_STATUS_STATE_START;
6658                 break;
6659         case RESET_KIND_SHUTDOWN:
6660                 /* With the interface we are currently using,
6661                  * APE does not track driver state.  Wiping
6662                  * out the HOST SEGMENT SIGNATURE forces
6663                  * the APE to assume OS absent status.
6664                  */
6665                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6666
6667                 if (device_may_wakeup(&tp->pdev->dev) &&
6668                     (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) {
6669                         tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
6670                                             TG3_APE_HOST_WOL_SPEED_AUTO);
6671                         apedata = TG3_APE_HOST_DRVR_STATE_WOL;
6672                 } else
6673                         apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
6674
6675                 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
6676
6677                 event = APE_EVENT_STATUS_STATE_UNLOAD;
6678                 break;
6679         case RESET_KIND_SUSPEND:
6680                 event = APE_EVENT_STATUS_STATE_SUSPEND;
6681                 break;
6682         default:
6683                 return;
6684         }
6685
6686         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6687
6688         tg3_ape_send_event(tp, event);
6689 }
6690
6691 /* tp->lock is held. */
6692 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6693 {
6694         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6695                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6696
6697         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6698                 switch (kind) {
6699                 case RESET_KIND_INIT:
6700                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6701                                       DRV_STATE_START);
6702                         break;
6703
6704                 case RESET_KIND_SHUTDOWN:
6705                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6706                                       DRV_STATE_UNLOAD);
6707                         break;
6708
6709                 case RESET_KIND_SUSPEND:
6710                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6711                                       DRV_STATE_SUSPEND);
6712                         break;
6713
6714                 default:
6715                         break;
6716                 }
6717         }
6718
6719         if (kind == RESET_KIND_INIT ||
6720             kind == RESET_KIND_SUSPEND)
6721                 tg3_ape_driver_state_change(tp, kind);
6722 }
6723
6724 /* tp->lock is held. */
6725 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6726 {
6727         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6728                 switch (kind) {
6729                 case RESET_KIND_INIT:
6730                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6731                                       DRV_STATE_START_DONE);
6732                         break;
6733
6734                 case RESET_KIND_SHUTDOWN:
6735                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6736                                       DRV_STATE_UNLOAD_DONE);
6737                         break;
6738
6739                 default:
6740                         break;
6741                 }
6742         }
6743
6744         if (kind == RESET_KIND_SHUTDOWN)
6745                 tg3_ape_driver_state_change(tp, kind);
6746 }
6747
6748 /* tp->lock is held. */
6749 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6750 {
6751         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6752                 switch (kind) {
6753                 case RESET_KIND_INIT:
6754                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6755                                       DRV_STATE_START);
6756                         break;
6757
6758                 case RESET_KIND_SHUTDOWN:
6759                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6760                                       DRV_STATE_UNLOAD);
6761                         break;
6762
6763                 case RESET_KIND_SUSPEND:
6764                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6765                                       DRV_STATE_SUSPEND);
6766                         break;
6767
6768                 default:
6769                         break;
6770                 }
6771         }
6772 }
6773
6774 static int tg3_poll_fw(struct tg3 *tp)
6775 {
6776         int i;
6777         u32 val;
6778
6779         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6780                 /* Wait up to 20ms for init done. */
6781                 for (i = 0; i < 200; i++) {
6782                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6783                                 return 0;
6784                         udelay(100);
6785                 }
6786                 return -ENODEV;
6787         }
6788
6789         /* Wait for firmware initialization to complete. */
6790         for (i = 0; i < 100000; i++) {
6791                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6792                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6793                         break;
6794                 udelay(10);
6795         }
6796
6797         /* Chip might not be fitted with firmware.  Some Sun onboard
6798          * parts are configured like that.  So don't signal the timeout
6799          * of the above loop as an error, but do report the lack of
6800          * running firmware once.
6801          */
6802         if (i >= 100000 &&
6803             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6804                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6805
6806                 netdev_info(tp->dev, "No firmware running\n");
6807         }
6808
6809         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6810                 /* The 57765 A0 needs a little more
6811                  * time to do some important work.
6812                  */
6813                 mdelay(10);
6814         }
6815
6816         return 0;
6817 }
6818
6819 /* Save PCI command register before chip reset */
6820 static void tg3_save_pci_state(struct tg3 *tp)
6821 {
6822         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6823 }
6824
6825 /* Restore PCI state after chip reset */
6826 static void tg3_restore_pci_state(struct tg3 *tp)
6827 {
6828         u32 val;
6829
6830         /* Re-enable indirect register accesses. */
6831         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6832                                tp->misc_host_ctrl);
6833
6834         /* Set MAX PCI retry to zero. */
6835         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6836         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6837             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6838                 val |= PCISTATE_RETRY_SAME_DMA;
6839         /* Allow reads and writes to the APE register and memory space. */
6840         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6841                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6842                        PCISTATE_ALLOW_APE_SHMEM_WR |
6843                        PCISTATE_ALLOW_APE_PSPACE_WR;
6844         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6845
6846         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6847
6848         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6849                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6850                         pcie_set_readrq(tp->pdev, 4096);
6851                 else {
6852                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6853                                               tp->pci_cacheline_sz);
6854                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6855                                               tp->pci_lat_timer);
6856                 }
6857         }
6858
6859         /* Make sure PCI-X relaxed ordering bit is clear. */
6860         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6861                 u16 pcix_cmd;
6862
6863                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6864                                      &pcix_cmd);
6865                 pcix_cmd &= ~PCI_X_CMD_ERO;
6866                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6867                                       pcix_cmd);
6868         }
6869
6870         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6871
6872                 /* Chip reset on 5780 will reset MSI enable bit,
6873                  * so need to restore it.
6874                  */
6875                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6876                         u16 ctrl;
6877
6878                         pci_read_config_word(tp->pdev,
6879                                              tp->msi_cap + PCI_MSI_FLAGS,
6880                                              &ctrl);
6881                         pci_write_config_word(tp->pdev,
6882                                               tp->msi_cap + PCI_MSI_FLAGS,
6883                                               ctrl | PCI_MSI_FLAGS_ENABLE);
6884                         val = tr32(MSGINT_MODE);
6885                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6886                 }
6887         }
6888 }
6889
6890 static void tg3_stop_fw(struct tg3 *);
6891
6892 /* tp->lock is held. */
6893 static int tg3_chip_reset(struct tg3 *tp)
6894 {
6895         u32 val;
6896         void (*write_op)(struct tg3 *, u32, u32);
6897         int i, err;
6898
6899         tg3_nvram_lock(tp);
6900
6901         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6902
6903         /* No matching tg3_nvram_unlock() after this because
6904          * chip reset below will undo the nvram lock.
6905          */
6906         tp->nvram_lock_cnt = 0;
6907
6908         /* GRC_MISC_CFG core clock reset will clear the memory
6909          * enable bit in PCI register 4 and the MSI enable bit
6910          * on some chips, so we save relevant registers here.
6911          */
6912         tg3_save_pci_state(tp);
6913
6914         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6915             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6916                 tw32(GRC_FASTBOOT_PC, 0);
6917
6918         /*
6919          * We must avoid the readl() that normally takes place.
6920          * It locks machines, causes machine checks, and other
6921          * fun things.  So, temporarily disable the 5701
6922          * hardware workaround, while we do the reset.
6923          */
6924         write_op = tp->write32;
6925         if (write_op == tg3_write_flush_reg32)
6926                 tp->write32 = tg3_write32;
6927
6928         /* Prevent the irq handler from reading or writing PCI registers
6929          * during chip reset when the memory enable bit in the PCI command
6930          * register may be cleared.  The chip does not generate interrupt
6931          * at this time, but the irq handler may still be called due to irq
6932          * sharing or irqpoll.
6933          */
6934         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6935         for (i = 0; i < tp->irq_cnt; i++) {
6936                 struct tg3_napi *tnapi = &tp->napi[i];
6937                 if (tnapi->hw_status) {
6938                         tnapi->hw_status->status = 0;
6939                         tnapi->hw_status->status_tag = 0;
6940                 }
6941                 tnapi->last_tag = 0;
6942                 tnapi->last_irq_tag = 0;
6943         }
6944         smp_mb();
6945
6946         for (i = 0; i < tp->irq_cnt; i++)
6947                 synchronize_irq(tp->napi[i].irq_vec);
6948
6949         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6950                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6951                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6952         }
6953
6954         /* do the reset */
6955         val = GRC_MISC_CFG_CORECLK_RESET;
6956
6957         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6958                 /* Force PCIe 1.0a mode */
6959                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
6960                     !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
6961                     tr32(TG3_PCIE_PHY_TSTCTL) ==
6962                     (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
6963                         tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
6964
6965                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6966                         tw32(GRC_MISC_CFG, (1 << 29));
6967                         val |= (1 << 29);
6968                 }
6969         }
6970
6971         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6972                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6973                 tw32(GRC_VCPU_EXT_CTRL,
6974                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6975         }
6976
6977         /* Manage gphy power for all CPMU absent PCIe devices. */
6978         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6979             !(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
6980                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6981
6982         tw32(GRC_MISC_CFG, val);
6983
6984         /* restore 5701 hardware bug workaround write method */
6985         tp->write32 = write_op;
6986
6987         /* Unfortunately, we have to delay before the PCI read back.
6988          * Some 575X chips even will not respond to a PCI cfg access
6989          * when the reset command is given to the chip.
6990          *
6991          * How do these hardware designers expect things to work
6992          * properly if the PCI write is posted for a long period
6993          * of time?  It is always necessary to have some method by
6994          * which a register read back can occur to push the write
6995          * out which does the reset.
6996          *
6997          * For most tg3 variants the trick below was working.
6998          * Ho hum...
6999          */
7000         udelay(120);
7001
7002         /* Flush PCI posted writes.  The normal MMIO registers
7003          * are inaccessible at this time so this is the only
7004          * way to make this reliably (actually, this is no longer
7005          * the case, see above).  I tried to use indirect
7006          * register read/write but this upset some 5701 variants.
7007          */
7008         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
7009
7010         udelay(120);
7011
7012         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
7013                 u16 val16;
7014
7015                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
7016                         int i;
7017                         u32 cfg_val;
7018
7019                         /* Wait for link training to complete.  */
7020                         for (i = 0; i < 5000; i++)
7021                                 udelay(100);
7022
7023                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
7024                         pci_write_config_dword(tp->pdev, 0xc4,
7025                                                cfg_val | (1 << 15));
7026                 }
7027
7028                 /* Clear the "no snoop" and "relaxed ordering" bits. */
7029                 pci_read_config_word(tp->pdev,
7030                                      tp->pcie_cap + PCI_EXP_DEVCTL,
7031                                      &val16);
7032                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
7033                            PCI_EXP_DEVCTL_NOSNOOP_EN);
7034                 /*
7035                  * Older PCIe devices only support the 128 byte
7036                  * MPS setting.  Enforce the restriction.
7037                  */
7038                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7039                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
7040                 pci_write_config_word(tp->pdev,
7041                                       tp->pcie_cap + PCI_EXP_DEVCTL,
7042                                       val16);
7043
7044                 pcie_set_readrq(tp->pdev, 4096);
7045
7046                 /* Clear error status */
7047                 pci_write_config_word(tp->pdev,
7048                                       tp->pcie_cap + PCI_EXP_DEVSTA,
7049                                       PCI_EXP_DEVSTA_CED |
7050                                       PCI_EXP_DEVSTA_NFED |
7051                                       PCI_EXP_DEVSTA_FED |
7052                                       PCI_EXP_DEVSTA_URD);
7053         }
7054
7055         tg3_restore_pci_state(tp);
7056
7057         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
7058
7059         val = 0;
7060         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
7061                 val = tr32(MEMARB_MODE);
7062         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7063
7064         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7065                 tg3_stop_fw(tp);
7066                 tw32(0x5000, 0x400);
7067         }
7068
7069         tw32(GRC_MODE, tp->grc_mode);
7070
7071         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
7072                 val = tr32(0xc4);
7073
7074                 tw32(0xc4, val | (1 << 15));
7075         }
7076
7077         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7078             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7079                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7080                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7081                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7082                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7083         }
7084
7085         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
7086                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
7087                 tw32_f(MAC_MODE, tp->mac_mode);
7088         } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
7089                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
7090                 tw32_f(MAC_MODE, tp->mac_mode);
7091         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7092                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
7093                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
7094                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
7095                 tw32_f(MAC_MODE, tp->mac_mode);
7096         } else
7097                 tw32_f(MAC_MODE, 0);
7098         udelay(40);
7099
7100         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7101
7102         err = tg3_poll_fw(tp);
7103         if (err)
7104                 return err;
7105
7106         tg3_mdio_start(tp);
7107
7108         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
7109             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7110             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7111             !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
7112                 val = tr32(0x7c00);
7113
7114                 tw32(0x7c00, val | (1 << 25));
7115         }
7116
7117         /* Reprobe ASF enable state.  */
7118         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7119         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7120         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7121         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7122                 u32 nic_cfg;
7123
7124                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7125                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7126                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7127                         tp->last_event_jiffies = jiffies;
7128                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7129                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7130                 }
7131         }
7132
7133         return 0;
7134 }
7135
7136 /* tp->lock is held. */
7137 static void tg3_stop_fw(struct tg3 *tp)
7138 {
7139         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7140            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7141                 /* Wait for RX cpu to ACK the previous event. */
7142                 tg3_wait_for_event_ack(tp);
7143
7144                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7145
7146                 tg3_generate_fw_event(tp);
7147
7148                 /* Wait for RX cpu to ACK this event. */
7149                 tg3_wait_for_event_ack(tp);
7150         }
7151 }
7152
7153 /* tp->lock is held. */
7154 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7155 {
7156         int err;
7157
7158         tg3_stop_fw(tp);
7159
7160         tg3_write_sig_pre_reset(tp, kind);
7161
7162         tg3_abort_hw(tp, silent);
7163         err = tg3_chip_reset(tp);
7164
7165         __tg3_set_mac_addr(tp, 0);
7166
7167         tg3_write_sig_legacy(tp, kind);
7168         tg3_write_sig_post_reset(tp, kind);
7169
7170         if (err)
7171                 return err;
7172
7173         return 0;
7174 }
7175
7176 #define RX_CPU_SCRATCH_BASE     0x30000
7177 #define RX_CPU_SCRATCH_SIZE     0x04000
7178 #define TX_CPU_SCRATCH_BASE     0x34000
7179 #define TX_CPU_SCRATCH_SIZE     0x04000
7180
7181 /* tp->lock is held. */
7182 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7183 {
7184         int i;
7185
7186         BUG_ON(offset == TX_CPU_BASE &&
7187             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7188
7189         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7190                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7191
7192                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7193                 return 0;
7194         }
7195         if (offset == RX_CPU_BASE) {
7196                 for (i = 0; i < 10000; i++) {
7197                         tw32(offset + CPU_STATE, 0xffffffff);
7198                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7199                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7200                                 break;
7201                 }
7202
7203                 tw32(offset + CPU_STATE, 0xffffffff);
7204                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
7205                 udelay(10);
7206         } else {
7207                 for (i = 0; i < 10000; i++) {
7208                         tw32(offset + CPU_STATE, 0xffffffff);
7209                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7210                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7211                                 break;
7212                 }
7213         }
7214
7215         if (i >= 10000) {
7216                 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7217                            __func__, offset == RX_CPU_BASE ? "RX" : "TX");
7218                 return -ENODEV;
7219         }
7220
7221         /* Clear firmware's nvram arbitration. */
7222         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7223                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7224         return 0;
7225 }
7226
7227 struct fw_info {
7228         unsigned int fw_base;
7229         unsigned int fw_len;
7230         const __be32 *fw_data;
7231 };
7232
7233 /* tp->lock is held. */
7234 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7235                                  int cpu_scratch_size, struct fw_info *info)
7236 {
7237         int err, lock_err, i;
7238         void (*write_op)(struct tg3 *, u32, u32);
7239
7240         if (cpu_base == TX_CPU_BASE &&
7241             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7242                 netdev_err(tp->dev,
7243                            "%s: Trying to load TX cpu firmware which is 5705\n",
7244                            __func__);
7245                 return -EINVAL;
7246         }
7247
7248         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7249                 write_op = tg3_write_mem;
7250         else
7251                 write_op = tg3_write_indirect_reg32;
7252
7253         /* It is possible that bootcode is still loading at this point.
7254          * Get the nvram lock first before halting the cpu.
7255          */
7256         lock_err = tg3_nvram_lock(tp);
7257         err = tg3_halt_cpu(tp, cpu_base);
7258         if (!lock_err)
7259                 tg3_nvram_unlock(tp);
7260         if (err)
7261                 goto out;
7262
7263         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7264                 write_op(tp, cpu_scratch_base + i, 0);
7265         tw32(cpu_base + CPU_STATE, 0xffffffff);
7266         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7267         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7268                 write_op(tp, (cpu_scratch_base +
7269                               (info->fw_base & 0xffff) +
7270                               (i * sizeof(u32))),
7271                               be32_to_cpu(info->fw_data[i]));
7272
7273         err = 0;
7274
7275 out:
7276         return err;
7277 }
7278
7279 /* tp->lock is held. */
7280 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7281 {
7282         struct fw_info info;
7283         const __be32 *fw_data;
7284         int err, i;
7285
7286         fw_data = (void *)tp->fw->data;
7287
7288         /* Firmware blob starts with version numbers, followed by
7289            start address and length. We are setting complete length.
7290            length = end_address_of_bss - start_address_of_text.
7291            Remainder is the blob to be loaded contiguously
7292            from start address. */
7293
7294         info.fw_base = be32_to_cpu(fw_data[1]);
7295         info.fw_len = tp->fw->size - 12;
7296         info.fw_data = &fw_data[3];
7297
7298         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7299                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7300                                     &info);
7301         if (err)
7302                 return err;
7303
7304         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7305                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7306                                     &info);
7307         if (err)
7308                 return err;
7309
7310         /* Now startup only the RX cpu. */
7311         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7312         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7313
7314         for (i = 0; i < 5; i++) {
7315                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7316                         break;
7317                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7318                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
7319                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7320                 udelay(1000);
7321         }
7322         if (i >= 5) {
7323                 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7324                            "should be %08x\n", __func__,
7325                            tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
7326                 return -ENODEV;
7327         }
7328         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7329         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
7330
7331         return 0;
7332 }
7333
7334 /* 5705 needs a special version of the TSO firmware.  */
7335
7336 /* tp->lock is held. */
7337 static int tg3_load_tso_firmware(struct tg3 *tp)
7338 {
7339         struct fw_info info;
7340         const __be32 *fw_data;
7341         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7342         int err, i;
7343
7344         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7345                 return 0;
7346
7347         fw_data = (void *)tp->fw->data;
7348
7349         /* Firmware blob starts with version numbers, followed by
7350            start address and length. We are setting complete length.
7351            length = end_address_of_bss - start_address_of_text.
7352            Remainder is the blob to be loaded contiguously
7353            from start address. */
7354
7355         info.fw_base = be32_to_cpu(fw_data[1]);
7356         cpu_scratch_size = tp->fw_len;
7357         info.fw_len = tp->fw->size - 12;
7358         info.fw_data = &fw_data[3];
7359
7360         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7361                 cpu_base = RX_CPU_BASE;
7362                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7363         } else {
7364                 cpu_base = TX_CPU_BASE;
7365                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7366                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7367         }
7368
7369         err = tg3_load_firmware_cpu(tp, cpu_base,
7370                                     cpu_scratch_base, cpu_scratch_size,
7371                                     &info);
7372         if (err)
7373                 return err;
7374
7375         /* Now startup the cpu. */
7376         tw32(cpu_base + CPU_STATE, 0xffffffff);
7377         tw32_f(cpu_base + CPU_PC, info.fw_base);
7378
7379         for (i = 0; i < 5; i++) {
7380                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7381                         break;
7382                 tw32(cpu_base + CPU_STATE, 0xffffffff);
7383                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
7384                 tw32_f(cpu_base + CPU_PC, info.fw_base);
7385                 udelay(1000);
7386         }
7387         if (i >= 5) {
7388                 netdev_err(tp->dev,
7389                            "%s fails to set CPU PC, is %08x should be %08x\n",
7390                            __func__, tr32(cpu_base + CPU_PC), info.fw_base);
7391                 return -ENODEV;
7392         }
7393         tw32(cpu_base + CPU_STATE, 0xffffffff);
7394         tw32_f(cpu_base + CPU_MODE,  0x00000000);
7395         return 0;
7396 }
7397
7398
7399 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7400 {
7401         struct tg3 *tp = netdev_priv(dev);
7402         struct sockaddr *addr = p;
7403         int err = 0, skip_mac_1 = 0;
7404
7405         if (!is_valid_ether_addr(addr->sa_data))
7406                 return -EINVAL;
7407
7408         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7409
7410         if (!netif_running(dev))
7411                 return 0;
7412
7413         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7414                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7415
7416                 addr0_high = tr32(MAC_ADDR_0_HIGH);
7417                 addr0_low = tr32(MAC_ADDR_0_LOW);
7418                 addr1_high = tr32(MAC_ADDR_1_HIGH);
7419                 addr1_low = tr32(MAC_ADDR_1_LOW);
7420
7421                 /* Skip MAC addr 1 if ASF is using it. */
7422                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7423                     !(addr1_high == 0 && addr1_low == 0))
7424                         skip_mac_1 = 1;
7425         }
7426         spin_lock_bh(&tp->lock);
7427         __tg3_set_mac_addr(tp, skip_mac_1);
7428         spin_unlock_bh(&tp->lock);
7429
7430         return err;
7431 }
7432
7433 /* tp->lock is held. */
7434 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7435                            dma_addr_t mapping, u32 maxlen_flags,
7436                            u32 nic_addr)
7437 {
7438         tg3_write_mem(tp,
7439                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7440                       ((u64) mapping >> 32));
7441         tg3_write_mem(tp,
7442                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7443                       ((u64) mapping & 0xffffffff));
7444         tg3_write_mem(tp,
7445                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7446                        maxlen_flags);
7447
7448         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7449                 tg3_write_mem(tp,
7450                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7451                               nic_addr);
7452 }
7453
7454 static void __tg3_set_rx_mode(struct net_device *);
7455 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7456 {
7457         int i;
7458
7459         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7460                 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7461                 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7462                 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7463         } else {
7464                 tw32(HOSTCC_TXCOL_TICKS, 0);
7465                 tw32(HOSTCC_TXMAX_FRAMES, 0);
7466                 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7467         }
7468
7469         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
7470                 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7471                 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7472                 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7473         } else {
7474                 tw32(HOSTCC_RXCOL_TICKS, 0);
7475                 tw32(HOSTCC_RXMAX_FRAMES, 0);
7476                 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7477         }
7478
7479         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7480                 u32 val = ec->stats_block_coalesce_usecs;
7481
7482                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7483                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7484
7485                 if (!netif_carrier_ok(tp->dev))
7486                         val = 0;
7487
7488                 tw32(HOSTCC_STAT_COAL_TICKS, val);
7489         }
7490
7491         for (i = 0; i < tp->irq_cnt - 1; i++) {
7492                 u32 reg;
7493
7494                 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7495                 tw32(reg, ec->rx_coalesce_usecs);
7496                 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7497                 tw32(reg, ec->rx_max_coalesced_frames);
7498                 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7499                 tw32(reg, ec->rx_max_coalesced_frames_irq);
7500
7501                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7502                         reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7503                         tw32(reg, ec->tx_coalesce_usecs);
7504                         reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7505                         tw32(reg, ec->tx_max_coalesced_frames);
7506                         reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7507                         tw32(reg, ec->tx_max_coalesced_frames_irq);
7508                 }
7509         }
7510
7511         for (; i < tp->irq_max - 1; i++) {
7512                 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7513                 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7514                 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7515
7516                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7517                         tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7518                         tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7519                         tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7520                 }
7521         }
7522 }
7523
7524 /* tp->lock is held. */
7525 static void tg3_rings_reset(struct tg3 *tp)
7526 {
7527         int i;
7528         u32 stblk, txrcb, rxrcb, limit;
7529         struct tg3_napi *tnapi = &tp->napi[0];
7530
7531         /* Disable all transmit rings but the first. */
7532         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7533                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7534         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7535                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7536         else
7537                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7538
7539         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7540              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7541                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7542                               BDINFO_FLAGS_DISABLED);
7543
7544
7545         /* Disable all receive return rings but the first. */
7546         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7547             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7548                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7549         else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7550                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7551         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7552                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7553                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7554         else
7555                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7556
7557         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7558              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7559                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7560                               BDINFO_FLAGS_DISABLED);
7561
7562         /* Disable interrupts */
7563         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7564
7565         /* Zero mailbox registers. */
7566         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7567                 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7568                         tp->napi[i].tx_prod = 0;
7569                         tp->napi[i].tx_cons = 0;
7570                         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7571                                 tw32_mailbox(tp->napi[i].prodmbox, 0);
7572                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
7573                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7574                 }
7575                 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7576                         tw32_mailbox(tp->napi[0].prodmbox, 0);
7577         } else {
7578                 tp->napi[0].tx_prod = 0;
7579                 tp->napi[0].tx_cons = 0;
7580                 tw32_mailbox(tp->napi[0].prodmbox, 0);
7581                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7582         }
7583
7584         /* Make sure the NIC-based send BD rings are disabled. */
7585         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7586                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7587                 for (i = 0; i < 16; i++)
7588                         tw32_tx_mbox(mbox + i * 8, 0);
7589         }
7590
7591         txrcb = NIC_SRAM_SEND_RCB;
7592         rxrcb = NIC_SRAM_RCV_RET_RCB;
7593
7594         /* Clear status block in ram. */
7595         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7596
7597         /* Set status block DMA address */
7598         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7599              ((u64) tnapi->status_mapping >> 32));
7600         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7601              ((u64) tnapi->status_mapping & 0xffffffff));
7602
7603         if (tnapi->tx_ring) {
7604                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7605                                (TG3_TX_RING_SIZE <<
7606                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7607                                NIC_SRAM_TX_BUFFER_DESC);
7608                 txrcb += TG3_BDINFO_SIZE;
7609         }
7610
7611         if (tnapi->rx_rcb) {
7612                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7613                                (TG3_RX_RCB_RING_SIZE(tp) <<
7614                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7615                 rxrcb += TG3_BDINFO_SIZE;
7616         }
7617
7618         stblk = HOSTCC_STATBLCK_RING1;
7619
7620         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7621                 u64 mapping = (u64)tnapi->status_mapping;
7622                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7623                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7624
7625                 /* Clear status block in ram. */
7626                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7627
7628                 if (tnapi->tx_ring) {
7629                         tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7630                                        (TG3_TX_RING_SIZE <<
7631                                         BDINFO_FLAGS_MAXLEN_SHIFT),
7632                                        NIC_SRAM_TX_BUFFER_DESC);
7633                         txrcb += TG3_BDINFO_SIZE;
7634                 }
7635
7636                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7637                                (TG3_RX_RCB_RING_SIZE(tp) <<
7638                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7639
7640                 stblk += 8;
7641                 rxrcb += TG3_BDINFO_SIZE;
7642         }
7643 }
7644
7645 /* tp->lock is held. */
7646 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7647 {
7648         u32 val, rdmac_mode;
7649         int i, err, limit;
7650         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
7651
7652         tg3_disable_ints(tp);
7653
7654         tg3_stop_fw(tp);
7655
7656         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7657
7658         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
7659                 tg3_abort_hw(tp, 1);
7660
7661         if (reset_phy)
7662                 tg3_phy_reset(tp);
7663
7664         err = tg3_chip_reset(tp);
7665         if (err)
7666                 return err;
7667
7668         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7669
7670         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7671                 val = tr32(TG3_CPMU_CTRL);
7672                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7673                 tw32(TG3_CPMU_CTRL, val);
7674
7675                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7676                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7677                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7678                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7679
7680                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7681                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7682                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7683                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7684
7685                 val = tr32(TG3_CPMU_HST_ACC);
7686                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7687                 val |= CPMU_HST_ACC_MACCLK_6_25;
7688                 tw32(TG3_CPMU_HST_ACC, val);
7689         }
7690
7691         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7692                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7693                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7694                        PCIE_PWR_MGMT_L1_THRESH_4MS;
7695                 tw32(PCIE_PWR_MGMT_THRESH, val);
7696
7697                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7698                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7699
7700                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7701
7702                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7703                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7704         }
7705
7706         if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7707                 u32 grc_mode = tr32(GRC_MODE);
7708
7709                 /* Access the lower 1K of PL PCIE block registers. */
7710                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7711                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7712
7713                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7714                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7715                      val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7716
7717                 tw32(GRC_MODE, grc_mode);
7718         }
7719
7720         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
7721                 u32 grc_mode = tr32(GRC_MODE);
7722
7723                 /* Access the lower 1K of PL PCIE block registers. */
7724                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7725                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7726
7727                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5);
7728                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
7729                      val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
7730
7731                 tw32(GRC_MODE, grc_mode);
7732
7733                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7734                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7735                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7736                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7737         }
7738
7739         /* This works around an issue with Athlon chipsets on
7740          * B3 tigon3 silicon.  This bit has no effect on any
7741          * other revision.  But do not set this on PCI Express
7742          * chips and don't even touch the clocks if the CPMU is present.
7743          */
7744         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7745                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7746                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7747                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7748         }
7749
7750         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7751             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7752                 val = tr32(TG3PCI_PCISTATE);
7753                 val |= PCISTATE_RETRY_SAME_DMA;
7754                 tw32(TG3PCI_PCISTATE, val);
7755         }
7756
7757         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7758                 /* Allow reads and writes to the
7759                  * APE register and memory space.
7760                  */
7761                 val = tr32(TG3PCI_PCISTATE);
7762                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7763                        PCISTATE_ALLOW_APE_SHMEM_WR |
7764                        PCISTATE_ALLOW_APE_PSPACE_WR;
7765                 tw32(TG3PCI_PCISTATE, val);
7766         }
7767
7768         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7769                 /* Enable some hw fixes.  */
7770                 val = tr32(TG3PCI_MSI_DATA);
7771                 val |= (1 << 26) | (1 << 28) | (1 << 29);
7772                 tw32(TG3PCI_MSI_DATA, val);
7773         }
7774
7775         /* Descriptor ring init may make accesses to the
7776          * NIC SRAM area to setup the TX descriptors, so we
7777          * can only do this after the hardware has been
7778          * successfully reset.
7779          */
7780         err = tg3_init_rings(tp);
7781         if (err)
7782                 return err;
7783
7784         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
7785                 val = tr32(TG3PCI_DMA_RW_CTRL) &
7786                       ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7787                 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
7788                         val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
7789                 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7790         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7791                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7792                 /* This value is determined during the probe time DMA
7793                  * engine test, tg3_test_dma.
7794                  */
7795                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7796         }
7797
7798         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7799                           GRC_MODE_4X_NIC_SEND_RINGS |
7800                           GRC_MODE_NO_TX_PHDR_CSUM |
7801                           GRC_MODE_NO_RX_PHDR_CSUM);
7802         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7803
7804         /* Pseudo-header checksum is done by hardware logic and not
7805          * the offload processers, so make the chip do the pseudo-
7806          * header checksums on receive.  For transmit it is more
7807          * convenient to do the pseudo-header checksum in software
7808          * as Linux does that on transmit for us in all cases.
7809          */
7810         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7811
7812         tw32(GRC_MODE,
7813              tp->grc_mode |
7814              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7815
7816         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7817         val = tr32(GRC_MISC_CFG);
7818         val &= ~0xff;
7819         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7820         tw32(GRC_MISC_CFG, val);
7821
7822         /* Initialize MBUF/DESC pool. */
7823         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7824                 /* Do nothing.  */
7825         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7826                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7827                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7828                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7829                 else
7830                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7831                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7832                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7833         } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7834                 int fw_len;
7835
7836                 fw_len = tp->fw_len;
7837                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7838                 tw32(BUFMGR_MB_POOL_ADDR,
7839                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7840                 tw32(BUFMGR_MB_POOL_SIZE,
7841                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7842         }
7843
7844         if (tp->dev->mtu <= ETH_DATA_LEN) {
7845                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7846                      tp->bufmgr_config.mbuf_read_dma_low_water);
7847                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7848                      tp->bufmgr_config.mbuf_mac_rx_low_water);
7849                 tw32(BUFMGR_MB_HIGH_WATER,
7850                      tp->bufmgr_config.mbuf_high_water);
7851         } else {
7852                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7853                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7854                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7855                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7856                 tw32(BUFMGR_MB_HIGH_WATER,
7857                      tp->bufmgr_config.mbuf_high_water_jumbo);
7858         }
7859         tw32(BUFMGR_DMA_LOW_WATER,
7860              tp->bufmgr_config.dma_low_water);
7861         tw32(BUFMGR_DMA_HIGH_WATER,
7862              tp->bufmgr_config.dma_high_water);
7863
7864         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7865         for (i = 0; i < 2000; i++) {
7866                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7867                         break;
7868                 udelay(10);
7869         }
7870         if (i >= 2000) {
7871                 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
7872                 return -ENODEV;
7873         }
7874
7875         /* Setup replenish threshold. */
7876         val = tp->rx_pending / 8;
7877         if (val == 0)
7878                 val = 1;
7879         else if (val > tp->rx_std_max_post)
7880                 val = tp->rx_std_max_post;
7881         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7882                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7883                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7884
7885                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7886                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7887         }
7888
7889         tw32(RCVBDI_STD_THRESH, val);
7890
7891         /* Initialize TG3_BDINFO's at:
7892          *  RCVDBDI_STD_BD:     standard eth size rx ring
7893          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
7894          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
7895          *
7896          * like so:
7897          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
7898          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
7899          *                              ring attribute flags
7900          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
7901          *
7902          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7903          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7904          *
7905          * The size of each ring is fixed in the firmware, but the location is
7906          * configurable.
7907          */
7908         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7909              ((u64) tpr->rx_std_mapping >> 32));
7910         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7911              ((u64) tpr->rx_std_mapping & 0xffffffff));
7912         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
7913             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
7914                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7915                      NIC_SRAM_RX_BUFFER_DESC);
7916
7917         /* Disable the mini ring */
7918         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7919                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7920                      BDINFO_FLAGS_DISABLED);
7921
7922         /* Program the jumbo buffer descriptor ring control
7923          * blocks on those devices that have them.
7924          */
7925         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7926             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7927                 /* Setup replenish threshold. */
7928                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7929
7930                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7931                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7932                              ((u64) tpr->rx_jmb_mapping >> 32));
7933                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7934                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7935                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7936                              (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7937                              BDINFO_FLAGS_USE_EXT_RECV);
7938                         if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) ||
7939                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7940                                 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7941                                      NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7942                 } else {
7943                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7944                              BDINFO_FLAGS_DISABLED);
7945                 }
7946
7947                 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
7948                         val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7949                               (TG3_RX_STD_DMA_SZ << 2);
7950                 else
7951                         val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
7952         } else
7953                 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7954
7955         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7956
7957         tpr->rx_std_prod_idx = tp->rx_pending;
7958         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
7959
7960         tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7961                           tp->rx_jumbo_pending : 0;
7962         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
7963
7964         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
7965                 tw32(STD_REPLENISH_LWM, 32);
7966                 tw32(JMB_REPLENISH_LWM, 16);
7967         }
7968
7969         tg3_rings_reset(tp);
7970
7971         /* Initialize MAC address and backoff seed. */
7972         __tg3_set_mac_addr(tp, 0);
7973
7974         /* MTU + ethernet header + FCS + optional VLAN tag */
7975         tw32(MAC_RX_MTU_SIZE,
7976              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7977
7978         /* The slot time is changed by tg3_setup_phy if we
7979          * run at gigabit with half duplex.
7980          */
7981         tw32(MAC_TX_LENGTHS,
7982              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7983              (6 << TX_LENGTHS_IPG_SHIFT) |
7984              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7985
7986         /* Receive rules. */
7987         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7988         tw32(RCVLPC_CONFIG, 0x0181);
7989
7990         /* Calculate RDMAC_MODE setting early, we need it to determine
7991          * the RCVLPC_STATE_ENABLE mask.
7992          */
7993         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7994                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7995                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7996                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7997                       RDMAC_MODE_LNGREAD_ENAB);
7998
7999         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8000             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8001                 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
8002
8003         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8004             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8005             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8006                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
8007                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
8008                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
8009
8010         /* If statement applies to 5705 and 5750 PCI devices only */
8011         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8012              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8013             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
8014                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
8015                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
8016                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
8017                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8018                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
8019                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8020                 }
8021         }
8022
8023         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
8024                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8025
8026         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8027                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8028
8029         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
8030             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8031             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8032                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
8033
8034         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8035             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8036             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8037             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
8038             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
8039                 val = tr32(TG3_RDMA_RSRVCTRL_REG);
8040                 tw32(TG3_RDMA_RSRVCTRL_REG,
8041                      val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
8042         }
8043
8044         /* Receive/send statistics. */
8045         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
8046                 val = tr32(RCVLPC_STATS_ENABLE);
8047                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8048                 tw32(RCVLPC_STATS_ENABLE, val);
8049         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8050                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8051                 val = tr32(RCVLPC_STATS_ENABLE);
8052                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8053                 tw32(RCVLPC_STATS_ENABLE, val);
8054         } else {
8055                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8056         }
8057         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8058         tw32(SNDDATAI_STATSENAB, 0xffffff);
8059         tw32(SNDDATAI_STATSCTRL,
8060              (SNDDATAI_SCTRL_ENABLE |
8061               SNDDATAI_SCTRL_FASTUPD));
8062
8063         /* Setup host coalescing engine. */
8064         tw32(HOSTCC_MODE, 0);
8065         for (i = 0; i < 2000; i++) {
8066                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8067                         break;
8068                 udelay(10);
8069         }
8070
8071         __tg3_set_coalesce(tp, &tp->coal);
8072
8073         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8074                 /* Status/statistics block address.  See tg3_timer,
8075                  * the tg3_periodic_fetch_stats call there, and
8076                  * tg3_get_stats to see how this works for 5705/5750 chips.
8077                  */
8078                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8079                      ((u64) tp->stats_mapping >> 32));
8080                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8081                      ((u64) tp->stats_mapping & 0xffffffff));
8082                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8083
8084                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
8085
8086                 /* Clear statistics and status block memory areas */
8087                 for (i = NIC_SRAM_STATS_BLK;
8088                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8089                      i += sizeof(u32)) {
8090                         tg3_write_mem(tp, i, 0);
8091                         udelay(40);
8092                 }
8093         }
8094
8095         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8096
8097         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8098         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8099         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8100                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8101
8102         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
8103                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
8104                 /* reset to prevent losing 1st rx packet intermittently */
8105                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8106                 udelay(10);
8107         }
8108
8109         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8110                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8111         else
8112                 tp->mac_mode = 0;
8113         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8114                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
8115         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8116             !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8117             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8118                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8119         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8120         udelay(40);
8121
8122         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8123          * If TG3_FLG2_IS_NIC is zero, we should read the
8124          * register to preserve the GPIO settings for LOMs. The GPIOs,
8125          * whether used as inputs or outputs, are set by boot code after
8126          * reset.
8127          */
8128         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
8129                 u32 gpio_mask;
8130
8131                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8132                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8133                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8134
8135                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8136                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8137                                      GRC_LCLCTRL_GPIO_OUTPUT3;
8138
8139                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8140                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8141
8142                 tp->grc_local_ctrl &= ~gpio_mask;
8143                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8144
8145                 /* GPIO1 must be driven high for eeprom write protect */
8146                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8147                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8148                                                GRC_LCLCTRL_GPIO_OUTPUT1);
8149         }
8150         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8151         udelay(100);
8152
8153         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
8154                 val = tr32(MSGINT_MODE);
8155                 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8156                 tw32(MSGINT_MODE, val);
8157         }
8158
8159         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8160                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8161                 udelay(40);
8162         }
8163
8164         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8165                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8166                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8167                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8168                WDMAC_MODE_LNGREAD_ENAB);
8169
8170         /* If statement applies to 5705 and 5750 PCI devices only */
8171         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8172              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8173             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
8174                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8175                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8176                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8177                         /* nothing */
8178                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8179                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8180                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8181                         val |= WDMAC_MODE_RX_ACCEL;
8182                 }
8183         }
8184
8185         /* Enable host coalescing bug fix */
8186         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8187                 val |= WDMAC_MODE_STATUS_TAG_FIX;
8188
8189         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8190                 val |= WDMAC_MODE_BURST_ALL_DATA;
8191
8192         tw32_f(WDMAC_MODE, val);
8193         udelay(40);
8194
8195         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8196                 u16 pcix_cmd;
8197
8198                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8199                                      &pcix_cmd);
8200                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8201                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8202                         pcix_cmd |= PCI_X_CMD_READ_2K;
8203                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8204                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8205                         pcix_cmd |= PCI_X_CMD_READ_2K;
8206                 }
8207                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8208                                       pcix_cmd);
8209         }
8210
8211         tw32_f(RDMAC_MODE, rdmac_mode);
8212         udelay(40);
8213
8214         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8215         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8216                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8217
8218         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8219                 tw32(SNDDATAC_MODE,
8220                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8221         else
8222                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8223
8224         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8225         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8226         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8227         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8228         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8229                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8230         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8231         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8232                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8233         tw32(SNDBDI_MODE, val);
8234         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8235
8236         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8237                 err = tg3_load_5701_a0_firmware_fix(tp);
8238                 if (err)
8239                         return err;
8240         }
8241
8242         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8243                 err = tg3_load_tso_firmware(tp);
8244                 if (err)
8245                         return err;
8246         }
8247
8248         tp->tx_mode = TX_MODE_ENABLE;
8249         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
8250             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8251                 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
8252         tw32_f(MAC_TX_MODE, tp->tx_mode);
8253         udelay(100);
8254
8255         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8256                 u32 reg = MAC_RSS_INDIR_TBL_0;
8257                 u8 *ent = (u8 *)&val;
8258
8259                 /* Setup the indirection table */
8260                 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8261                         int idx = i % sizeof(val);
8262
8263                         ent[idx] = i % (tp->irq_cnt - 1);
8264                         if (idx == sizeof(val) - 1) {
8265                                 tw32(reg, val);
8266                                 reg += 4;
8267                         }
8268                 }
8269
8270                 /* Setup the "secret" hash key. */
8271                 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8272                 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8273                 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8274                 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8275                 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8276                 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8277                 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8278                 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8279                 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8280                 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8281         }
8282
8283         tp->rx_mode = RX_MODE_ENABLE;
8284         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8285                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8286
8287         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8288                 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8289                                RX_MODE_RSS_ITBL_HASH_BITS_7 |
8290                                RX_MODE_RSS_IPV6_HASH_EN |
8291                                RX_MODE_RSS_TCP_IPV6_HASH_EN |
8292                                RX_MODE_RSS_IPV4_HASH_EN |
8293                                RX_MODE_RSS_TCP_IPV4_HASH_EN;
8294
8295         tw32_f(MAC_RX_MODE, tp->rx_mode);
8296         udelay(10);
8297
8298         tw32(MAC_LED_CTRL, tp->led_ctrl);
8299
8300         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8301         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8302                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8303                 udelay(10);
8304         }
8305         tw32_f(MAC_RX_MODE, tp->rx_mode);
8306         udelay(10);
8307
8308         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8309                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8310                         !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
8311                         /* Set drive transmission level to 1.2V  */
8312                         /* only if the signal pre-emphasis bit is not set  */
8313                         val = tr32(MAC_SERDES_CFG);
8314                         val &= 0xfffff000;
8315                         val |= 0x880;
8316                         tw32(MAC_SERDES_CFG, val);
8317                 }
8318                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8319                         tw32(MAC_SERDES_CFG, 0x616000);
8320         }
8321
8322         /* Prevent chip from dropping frames when flow control
8323          * is enabled.
8324          */
8325         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8326                 val = 1;
8327         else
8328                 val = 2;
8329         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8330
8331         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8332             (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
8333                 /* Use hardware link auto-negotiation */
8334                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8335         }
8336
8337         if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8338             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8339                 u32 tmp;
8340
8341                 tmp = tr32(SERDES_RX_CTRL);
8342                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8343                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8344                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8345                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8346         }
8347
8348         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8349                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
8350                         tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
8351                         tp->link_config.speed = tp->link_config.orig_speed;
8352                         tp->link_config.duplex = tp->link_config.orig_duplex;
8353                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
8354                 }
8355
8356                 err = tg3_setup_phy(tp, 0);
8357                 if (err)
8358                         return err;
8359
8360                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8361                     !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8362                         u32 tmp;
8363
8364                         /* Clear CRC stats. */
8365                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8366                                 tg3_writephy(tp, MII_TG3_TEST1,
8367                                              tmp | MII_TG3_TEST1_CRC_EN);
8368                                 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
8369                         }
8370                 }
8371         }
8372
8373         __tg3_set_rx_mode(tp->dev);
8374
8375         /* Initialize receive rules. */
8376         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
8377         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8378         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
8379         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8380
8381         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8382             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8383                 limit = 8;
8384         else
8385                 limit = 16;
8386         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8387                 limit -= 4;
8388         switch (limit) {
8389         case 16:
8390                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
8391         case 15:
8392                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
8393         case 14:
8394                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
8395         case 13:
8396                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
8397         case 12:
8398                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
8399         case 11:
8400                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
8401         case 10:
8402                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
8403         case 9:
8404                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
8405         case 8:
8406                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
8407         case 7:
8408                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
8409         case 6:
8410                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
8411         case 5:
8412                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
8413         case 4:
8414                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
8415         case 3:
8416                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
8417         case 2:
8418         case 1:
8419
8420         default:
8421                 break;
8422         }
8423
8424         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8425                 /* Write our heartbeat update interval to APE. */
8426                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8427                                 APE_HOST_HEARTBEAT_INT_DISABLE);
8428
8429         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8430
8431         return 0;
8432 }
8433
8434 /* Called at device open time to get the chip ready for
8435  * packet processing.  Invoked with tp->lock held.
8436  */
8437 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8438 {
8439         tg3_switch_clocks(tp);
8440
8441         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8442
8443         return tg3_reset_hw(tp, reset_phy);
8444 }
8445
8446 #define TG3_STAT_ADD32(PSTAT, REG) \
8447 do {    u32 __val = tr32(REG); \
8448         (PSTAT)->low += __val; \
8449         if ((PSTAT)->low < __val) \
8450                 (PSTAT)->high += 1; \
8451 } while (0)
8452
8453 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8454 {
8455         struct tg3_hw_stats *sp = tp->hw_stats;
8456
8457         if (!netif_carrier_ok(tp->dev))
8458                 return;
8459
8460         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8461         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8462         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8463         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8464         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8465         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8466         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8467         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8468         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8469         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8470         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8471         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8472         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8473
8474         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8475         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8476         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8477         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8478         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8479         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8480         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8481         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8482         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8483         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8484         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8485         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8486         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8487         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8488
8489         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8490         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8491         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8492 }
8493
8494 static void tg3_timer(unsigned long __opaque)
8495 {
8496         struct tg3 *tp = (struct tg3 *) __opaque;
8497
8498         if (tp->irq_sync)
8499                 goto restart_timer;
8500
8501         spin_lock(&tp->lock);
8502
8503         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8504                 /* All of this garbage is because when using non-tagged
8505                  * IRQ status the mailbox/status_block protocol the chip
8506                  * uses with the cpu is race prone.
8507                  */
8508                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8509                         tw32(GRC_LOCAL_CTRL,
8510                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8511                 } else {
8512                         tw32(HOSTCC_MODE, tp->coalesce_mode |
8513                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8514                 }
8515
8516                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8517                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8518                         spin_unlock(&tp->lock);
8519                         schedule_work(&tp->reset_task);
8520                         return;
8521                 }
8522         }
8523
8524         /* This part only runs once per second. */
8525         if (!--tp->timer_counter) {
8526                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8527                         tg3_periodic_fetch_stats(tp);
8528
8529                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8530                         u32 mac_stat;
8531                         int phy_event;
8532
8533                         mac_stat = tr32(MAC_STATUS);
8534
8535                         phy_event = 0;
8536                         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
8537                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8538                                         phy_event = 1;
8539                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8540                                 phy_event = 1;
8541
8542                         if (phy_event)
8543                                 tg3_setup_phy(tp, 0);
8544                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8545                         u32 mac_stat = tr32(MAC_STATUS);
8546                         int need_setup = 0;
8547
8548                         if (netif_carrier_ok(tp->dev) &&
8549                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8550                                 need_setup = 1;
8551                         }
8552                         if (!netif_carrier_ok(tp->dev) &&
8553                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
8554                                          MAC_STATUS_SIGNAL_DET))) {
8555                                 need_setup = 1;
8556                         }
8557                         if (need_setup) {
8558                                 if (!tp->serdes_counter) {
8559                                         tw32_f(MAC_MODE,
8560                                              (tp->mac_mode &
8561                                               ~MAC_MODE_PORT_MODE_MASK));
8562                                         udelay(40);
8563                                         tw32_f(MAC_MODE, tp->mac_mode);
8564                                         udelay(40);
8565                                 }
8566                                 tg3_setup_phy(tp, 0);
8567                         }
8568                 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8569                            (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8570                         tg3_serdes_parallel_detect(tp);
8571                 }
8572
8573                 tp->timer_counter = tp->timer_multiplier;
8574         }
8575
8576         /* Heartbeat is only sent once every 2 seconds.
8577          *
8578          * The heartbeat is to tell the ASF firmware that the host
8579          * driver is still alive.  In the event that the OS crashes,
8580          * ASF needs to reset the hardware to free up the FIFO space
8581          * that may be filled with rx packets destined for the host.
8582          * If the FIFO is full, ASF will no longer function properly.
8583          *
8584          * Unintended resets have been reported on real time kernels
8585          * where the timer doesn't run on time.  Netpoll will also have
8586          * same problem.
8587          *
8588          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8589          * to check the ring condition when the heartbeat is expiring
8590          * before doing the reset.  This will prevent most unintended
8591          * resets.
8592          */
8593         if (!--tp->asf_counter) {
8594                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8595                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8596                         tg3_wait_for_event_ack(tp);
8597
8598                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8599                                       FWCMD_NICDRV_ALIVE3);
8600                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8601                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
8602                                       TG3_FW_UPDATE_TIMEOUT_SEC);
8603
8604                         tg3_generate_fw_event(tp);
8605                 }
8606                 tp->asf_counter = tp->asf_multiplier;
8607         }
8608
8609         spin_unlock(&tp->lock);
8610
8611 restart_timer:
8612         tp->timer.expires = jiffies + tp->timer_offset;
8613         add_timer(&tp->timer);
8614 }
8615
8616 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8617 {
8618         irq_handler_t fn;
8619         unsigned long flags;
8620         char *name;
8621         struct tg3_napi *tnapi = &tp->napi[irq_num];
8622
8623         if (tp->irq_cnt == 1)
8624                 name = tp->dev->name;
8625         else {
8626                 name = &tnapi->irq_lbl[0];
8627                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8628                 name[IFNAMSIZ-1] = 0;
8629         }
8630
8631         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8632                 fn = tg3_msi;
8633                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8634                         fn = tg3_msi_1shot;
8635                 flags = IRQF_SAMPLE_RANDOM;
8636         } else {
8637                 fn = tg3_interrupt;
8638                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8639                         fn = tg3_interrupt_tagged;
8640                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8641         }
8642
8643         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8644 }
8645
8646 static int tg3_test_interrupt(struct tg3 *tp)
8647 {
8648         struct tg3_napi *tnapi = &tp->napi[0];
8649         struct net_device *dev = tp->dev;
8650         int err, i, intr_ok = 0;
8651         u32 val;
8652
8653         if (!netif_running(dev))
8654                 return -ENODEV;
8655
8656         tg3_disable_ints(tp);
8657
8658         free_irq(tnapi->irq_vec, tnapi);
8659
8660         /*
8661          * Turn off MSI one shot mode.  Otherwise this test has no
8662          * observable way to know whether the interrupt was delivered.
8663          */
8664         if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8665             (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8666                 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8667                 tw32(MSGINT_MODE, val);
8668         }
8669
8670         err = request_irq(tnapi->irq_vec, tg3_test_isr,
8671                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8672         if (err)
8673                 return err;
8674
8675         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8676         tg3_enable_ints(tp);
8677
8678         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8679                tnapi->coal_now);
8680
8681         for (i = 0; i < 5; i++) {
8682                 u32 int_mbox, misc_host_ctrl;
8683
8684                 int_mbox = tr32_mailbox(tnapi->int_mbox);
8685                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8686
8687                 if ((int_mbox != 0) ||
8688                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8689                         intr_ok = 1;
8690                         break;
8691                 }
8692
8693                 msleep(10);
8694         }
8695
8696         tg3_disable_ints(tp);
8697
8698         free_irq(tnapi->irq_vec, tnapi);
8699
8700         err = tg3_request_irq(tp, 0);
8701
8702         if (err)
8703                 return err;
8704
8705         if (intr_ok) {
8706                 /* Reenable MSI one shot mode. */
8707                 if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8708                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8709                         val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8710                         tw32(MSGINT_MODE, val);
8711                 }
8712                 return 0;
8713         }
8714
8715         return -EIO;
8716 }
8717
8718 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8719  * successfully restored
8720  */
8721 static int tg3_test_msi(struct tg3 *tp)
8722 {
8723         int err;
8724         u16 pci_cmd;
8725
8726         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8727                 return 0;
8728
8729         /* Turn off SERR reporting in case MSI terminates with Master
8730          * Abort.
8731          */
8732         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8733         pci_write_config_word(tp->pdev, PCI_COMMAND,
8734                               pci_cmd & ~PCI_COMMAND_SERR);
8735
8736         err = tg3_test_interrupt(tp);
8737
8738         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8739
8740         if (!err)
8741                 return 0;
8742
8743         /* other failures */
8744         if (err != -EIO)
8745                 return err;
8746
8747         /* MSI test failed, go back to INTx mode */
8748         netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
8749                     "to INTx mode. Please report this failure to the PCI "
8750                     "maintainer and include system chipset information\n");
8751
8752         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8753
8754         pci_disable_msi(tp->pdev);
8755
8756         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8757         tp->napi[0].irq_vec = tp->pdev->irq;
8758
8759         err = tg3_request_irq(tp, 0);
8760         if (err)
8761                 return err;
8762
8763         /* Need to reset the chip because the MSI cycle may have terminated
8764          * with Master Abort.
8765          */
8766         tg3_full_lock(tp, 1);
8767
8768         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8769         err = tg3_init_hw(tp, 1);
8770
8771         tg3_full_unlock(tp);
8772
8773         if (err)
8774                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8775
8776         return err;
8777 }
8778
8779 static int tg3_request_firmware(struct tg3 *tp)
8780 {
8781         const __be32 *fw_data;
8782
8783         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8784                 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
8785                            tp->fw_needed);
8786                 return -ENOENT;
8787         }
8788
8789         fw_data = (void *)tp->fw->data;
8790
8791         /* Firmware blob starts with version numbers, followed by
8792          * start address and _full_ length including BSS sections
8793          * (which must be longer than the actual data, of course
8794          */
8795
8796         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
8797         if (tp->fw_len < (tp->fw->size - 12)) {
8798                 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
8799                            tp->fw_len, tp->fw_needed);
8800                 release_firmware(tp->fw);
8801                 tp->fw = NULL;
8802                 return -EINVAL;
8803         }
8804
8805         /* We no longer need firmware; we have it. */
8806         tp->fw_needed = NULL;
8807         return 0;
8808 }
8809
8810 static bool tg3_enable_msix(struct tg3 *tp)
8811 {
8812         int i, rc, cpus = num_online_cpus();
8813         struct msix_entry msix_ent[tp->irq_max];
8814
8815         if (cpus == 1)
8816                 /* Just fallback to the simpler MSI mode. */
8817                 return false;
8818
8819         /*
8820          * We want as many rx rings enabled as there are cpus.
8821          * The first MSIX vector only deals with link interrupts, etc,
8822          * so we add one to the number of vectors we are requesting.
8823          */
8824         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8825
8826         for (i = 0; i < tp->irq_max; i++) {
8827                 msix_ent[i].entry  = i;
8828                 msix_ent[i].vector = 0;
8829         }
8830
8831         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8832         if (rc < 0) {
8833                 return false;
8834         } else if (rc != 0) {
8835                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8836                         return false;
8837                 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
8838                               tp->irq_cnt, rc);
8839                 tp->irq_cnt = rc;
8840         }
8841
8842         for (i = 0; i < tp->irq_max; i++)
8843                 tp->napi[i].irq_vec = msix_ent[i].vector;
8844
8845         tp->dev->real_num_tx_queues = 1;
8846         if (tp->irq_cnt > 1)
8847                 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8848
8849         return true;
8850 }
8851
8852 static void tg3_ints_init(struct tg3 *tp)
8853 {
8854         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8855             !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8856                 /* All MSI supporting chips should support tagged
8857                  * status.  Assert that this is the case.
8858                  */
8859                 netdev_warn(tp->dev,
8860                             "MSI without TAGGED_STATUS? Not using MSI\n");
8861                 goto defcfg;
8862         }
8863
8864         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8865                 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8866         else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8867                  pci_enable_msi(tp->pdev) == 0)
8868                 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8869
8870         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8871                 u32 msi_mode = tr32(MSGINT_MODE);
8872                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8873                         msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8874                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8875         }
8876 defcfg:
8877         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8878                 tp->irq_cnt = 1;
8879                 tp->napi[0].irq_vec = tp->pdev->irq;
8880                 tp->dev->real_num_tx_queues = 1;
8881         }
8882 }
8883
8884 static void tg3_ints_fini(struct tg3 *tp)
8885 {
8886         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8887                 pci_disable_msix(tp->pdev);
8888         else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8889                 pci_disable_msi(tp->pdev);
8890         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8891         tp->tg3_flags3 &= ~(TG3_FLG3_ENABLE_RSS | TG3_FLG3_ENABLE_TSS);
8892 }
8893
8894 static int tg3_open(struct net_device *dev)
8895 {
8896         struct tg3 *tp = netdev_priv(dev);
8897         int i, err;
8898
8899         if (tp->fw_needed) {
8900                 err = tg3_request_firmware(tp);
8901                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8902                         if (err)
8903                                 return err;
8904                 } else if (err) {
8905                         netdev_warn(tp->dev, "TSO capability disabled\n");
8906                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8907                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8908                         netdev_notice(tp->dev, "TSO capability restored\n");
8909                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8910                 }
8911         }
8912
8913         netif_carrier_off(tp->dev);
8914
8915         err = tg3_set_power_state(tp, PCI_D0);
8916         if (err)
8917                 return err;
8918
8919         tg3_full_lock(tp, 0);
8920
8921         tg3_disable_ints(tp);
8922         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8923
8924         tg3_full_unlock(tp);
8925
8926         /*
8927          * Setup interrupts first so we know how
8928          * many NAPI resources to allocate
8929          */
8930         tg3_ints_init(tp);
8931
8932         /* The placement of this call is tied
8933          * to the setup and use of Host TX descriptors.
8934          */
8935         err = tg3_alloc_consistent(tp);
8936         if (err)
8937                 goto err_out1;
8938
8939         tg3_napi_enable(tp);
8940
8941         for (i = 0; i < tp->irq_cnt; i++) {
8942                 struct tg3_napi *tnapi = &tp->napi[i];
8943                 err = tg3_request_irq(tp, i);
8944                 if (err) {
8945                         for (i--; i >= 0; i--)
8946                                 free_irq(tnapi->irq_vec, tnapi);
8947                         break;
8948                 }
8949         }
8950
8951         if (err)
8952                 goto err_out2;
8953
8954         tg3_full_lock(tp, 0);
8955
8956         err = tg3_init_hw(tp, 1);
8957         if (err) {
8958                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8959                 tg3_free_rings(tp);
8960         } else {
8961                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8962                         tp->timer_offset = HZ;
8963                 else
8964                         tp->timer_offset = HZ / 10;
8965
8966                 BUG_ON(tp->timer_offset > HZ);
8967                 tp->timer_counter = tp->timer_multiplier =
8968                         (HZ / tp->timer_offset);
8969                 tp->asf_counter = tp->asf_multiplier =
8970                         ((HZ / tp->timer_offset) * 2);
8971
8972                 init_timer(&tp->timer);
8973                 tp->timer.expires = jiffies + tp->timer_offset;
8974                 tp->timer.data = (unsigned long) tp;
8975                 tp->timer.function = tg3_timer;
8976         }
8977
8978         tg3_full_unlock(tp);
8979
8980         if (err)
8981                 goto err_out3;
8982
8983         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8984                 err = tg3_test_msi(tp);
8985
8986                 if (err) {
8987                         tg3_full_lock(tp, 0);
8988                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8989                         tg3_free_rings(tp);
8990                         tg3_full_unlock(tp);
8991
8992                         goto err_out2;
8993                 }
8994
8995                 if (!(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8996                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8997                         u32 val = tr32(PCIE_TRANSACTION_CFG);
8998
8999                         tw32(PCIE_TRANSACTION_CFG,
9000                              val | PCIE_TRANS_CFG_1SHOT_MSI);
9001                 }
9002         }
9003
9004         tg3_phy_start(tp);
9005
9006         tg3_full_lock(tp, 0);
9007
9008         add_timer(&tp->timer);
9009         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9010         tg3_enable_ints(tp);
9011
9012         tg3_full_unlock(tp);
9013
9014         netif_tx_start_all_queues(dev);
9015
9016         return 0;
9017
9018 err_out3:
9019         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9020                 struct tg3_napi *tnapi = &tp->napi[i];
9021                 free_irq(tnapi->irq_vec, tnapi);
9022         }
9023
9024 err_out2:
9025         tg3_napi_disable(tp);
9026         tg3_free_consistent(tp);
9027
9028 err_out1:
9029         tg3_ints_fini(tp);
9030         return err;
9031 }
9032
9033 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
9034                                                  struct rtnl_link_stats64 *);
9035 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9036
9037 static int tg3_close(struct net_device *dev)
9038 {
9039         int i;
9040         struct tg3 *tp = netdev_priv(dev);
9041
9042         tg3_napi_disable(tp);
9043         cancel_work_sync(&tp->reset_task);
9044
9045         netif_tx_stop_all_queues(dev);
9046
9047         del_timer_sync(&tp->timer);
9048
9049         tg3_phy_stop(tp);
9050
9051         tg3_full_lock(tp, 1);
9052
9053         tg3_disable_ints(tp);
9054
9055         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9056         tg3_free_rings(tp);
9057         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9058
9059         tg3_full_unlock(tp);
9060
9061         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9062                 struct tg3_napi *tnapi = &tp->napi[i];
9063                 free_irq(tnapi->irq_vec, tnapi);
9064         }
9065
9066         tg3_ints_fini(tp);
9067
9068         tg3_get_stats64(tp->dev, &tp->net_stats_prev);
9069
9070         memcpy(&tp->estats_prev, tg3_get_estats(tp),
9071                sizeof(tp->estats_prev));
9072
9073         tg3_free_consistent(tp);
9074
9075         tg3_set_power_state(tp, PCI_D3hot);
9076
9077         netif_carrier_off(tp->dev);
9078
9079         return 0;
9080 }
9081
9082 static inline u64 get_stat64(tg3_stat64_t *val)
9083 {
9084        return ((u64)val->high << 32) | ((u64)val->low);
9085 }
9086
9087 static u64 calc_crc_errors(struct tg3 *tp)
9088 {
9089         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9090
9091         if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9092             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9093              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9094                 u32 val;
9095
9096                 spin_lock_bh(&tp->lock);
9097                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9098                         tg3_writephy(tp, MII_TG3_TEST1,
9099                                      val | MII_TG3_TEST1_CRC_EN);
9100                         tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
9101                 } else
9102                         val = 0;
9103                 spin_unlock_bh(&tp->lock);
9104
9105                 tp->phy_crc_errors += val;
9106
9107                 return tp->phy_crc_errors;
9108         }
9109
9110         return get_stat64(&hw_stats->rx_fcs_errors);
9111 }
9112
9113 #define ESTAT_ADD(member) \
9114         estats->member =        old_estats->member + \
9115                                 get_stat64(&hw_stats->member)
9116
9117 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9118 {
9119         struct tg3_ethtool_stats *estats = &tp->estats;
9120         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9121         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9122
9123         if (!hw_stats)
9124                 return old_estats;
9125
9126         ESTAT_ADD(rx_octets);
9127         ESTAT_ADD(rx_fragments);
9128         ESTAT_ADD(rx_ucast_packets);
9129         ESTAT_ADD(rx_mcast_packets);
9130         ESTAT_ADD(rx_bcast_packets);
9131         ESTAT_ADD(rx_fcs_errors);
9132         ESTAT_ADD(rx_align_errors);
9133         ESTAT_ADD(rx_xon_pause_rcvd);
9134         ESTAT_ADD(rx_xoff_pause_rcvd);
9135         ESTAT_ADD(rx_mac_ctrl_rcvd);
9136         ESTAT_ADD(rx_xoff_entered);
9137         ESTAT_ADD(rx_frame_too_long_errors);
9138         ESTAT_ADD(rx_jabbers);
9139         ESTAT_ADD(rx_undersize_packets);
9140         ESTAT_ADD(rx_in_length_errors);
9141         ESTAT_ADD(rx_out_length_errors);
9142         ESTAT_ADD(rx_64_or_less_octet_packets);
9143         ESTAT_ADD(rx_65_to_127_octet_packets);
9144         ESTAT_ADD(rx_128_to_255_octet_packets);
9145         ESTAT_ADD(rx_256_to_511_octet_packets);
9146         ESTAT_ADD(rx_512_to_1023_octet_packets);
9147         ESTAT_ADD(rx_1024_to_1522_octet_packets);
9148         ESTAT_ADD(rx_1523_to_2047_octet_packets);
9149         ESTAT_ADD(rx_2048_to_4095_octet_packets);
9150         ESTAT_ADD(rx_4096_to_8191_octet_packets);
9151         ESTAT_ADD(rx_8192_to_9022_octet_packets);
9152
9153         ESTAT_ADD(tx_octets);
9154         ESTAT_ADD(tx_collisions);
9155         ESTAT_ADD(tx_xon_sent);
9156         ESTAT_ADD(tx_xoff_sent);
9157         ESTAT_ADD(tx_flow_control);
9158         ESTAT_ADD(tx_mac_errors);
9159         ESTAT_ADD(tx_single_collisions);
9160         ESTAT_ADD(tx_mult_collisions);
9161         ESTAT_ADD(tx_deferred);
9162         ESTAT_ADD(tx_excessive_collisions);
9163         ESTAT_ADD(tx_late_collisions);
9164         ESTAT_ADD(tx_collide_2times);
9165         ESTAT_ADD(tx_collide_3times);
9166         ESTAT_ADD(tx_collide_4times);
9167         ESTAT_ADD(tx_collide_5times);
9168         ESTAT_ADD(tx_collide_6times);
9169         ESTAT_ADD(tx_collide_7times);
9170         ESTAT_ADD(tx_collide_8times);
9171         ESTAT_ADD(tx_collide_9times);
9172         ESTAT_ADD(tx_collide_10times);
9173         ESTAT_ADD(tx_collide_11times);
9174         ESTAT_ADD(tx_collide_12times);
9175         ESTAT_ADD(tx_collide_13times);
9176         ESTAT_ADD(tx_collide_14times);
9177         ESTAT_ADD(tx_collide_15times);
9178         ESTAT_ADD(tx_ucast_packets);
9179         ESTAT_ADD(tx_mcast_packets);
9180         ESTAT_ADD(tx_bcast_packets);
9181         ESTAT_ADD(tx_carrier_sense_errors);
9182         ESTAT_ADD(tx_discards);
9183         ESTAT_ADD(tx_errors);
9184
9185         ESTAT_ADD(dma_writeq_full);
9186         ESTAT_ADD(dma_write_prioq_full);
9187         ESTAT_ADD(rxbds_empty);
9188         ESTAT_ADD(rx_discards);
9189         ESTAT_ADD(rx_errors);
9190         ESTAT_ADD(rx_threshold_hit);
9191
9192         ESTAT_ADD(dma_readq_full);
9193         ESTAT_ADD(dma_read_prioq_full);
9194         ESTAT_ADD(tx_comp_queue_full);
9195
9196         ESTAT_ADD(ring_set_send_prod_index);
9197         ESTAT_ADD(ring_status_update);
9198         ESTAT_ADD(nic_irqs);
9199         ESTAT_ADD(nic_avoided_irqs);
9200         ESTAT_ADD(nic_tx_threshold_hit);
9201
9202         return estats;
9203 }
9204
9205 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
9206                                                  struct rtnl_link_stats64 *stats)
9207 {
9208         struct tg3 *tp = netdev_priv(dev);
9209         struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
9210         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9211
9212         if (!hw_stats)
9213                 return old_stats;
9214
9215         stats->rx_packets = old_stats->rx_packets +
9216                 get_stat64(&hw_stats->rx_ucast_packets) +
9217                 get_stat64(&hw_stats->rx_mcast_packets) +
9218                 get_stat64(&hw_stats->rx_bcast_packets);
9219
9220         stats->tx_packets = old_stats->tx_packets +
9221                 get_stat64(&hw_stats->tx_ucast_packets) +
9222                 get_stat64(&hw_stats->tx_mcast_packets) +
9223                 get_stat64(&hw_stats->tx_bcast_packets);
9224
9225         stats->rx_bytes = old_stats->rx_bytes +
9226                 get_stat64(&hw_stats->rx_octets);
9227         stats->tx_bytes = old_stats->tx_bytes +
9228                 get_stat64(&hw_stats->tx_octets);
9229
9230         stats->rx_errors = old_stats->rx_errors +
9231                 get_stat64(&hw_stats->rx_errors);
9232         stats->tx_errors = old_stats->tx_errors +
9233                 get_stat64(&hw_stats->tx_errors) +
9234                 get_stat64(&hw_stats->tx_mac_errors) +
9235                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9236                 get_stat64(&hw_stats->tx_discards);
9237
9238         stats->multicast = old_stats->multicast +
9239                 get_stat64(&hw_stats->rx_mcast_packets);
9240         stats->collisions = old_stats->collisions +
9241                 get_stat64(&hw_stats->tx_collisions);
9242
9243         stats->rx_length_errors = old_stats->rx_length_errors +
9244                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9245                 get_stat64(&hw_stats->rx_undersize_packets);
9246
9247         stats->rx_over_errors = old_stats->rx_over_errors +
9248                 get_stat64(&hw_stats->rxbds_empty);
9249         stats->rx_frame_errors = old_stats->rx_frame_errors +
9250                 get_stat64(&hw_stats->rx_align_errors);
9251         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9252                 get_stat64(&hw_stats->tx_discards);
9253         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9254                 get_stat64(&hw_stats->tx_carrier_sense_errors);
9255
9256         stats->rx_crc_errors = old_stats->rx_crc_errors +
9257                 calc_crc_errors(tp);
9258
9259         stats->rx_missed_errors = old_stats->rx_missed_errors +
9260                 get_stat64(&hw_stats->rx_discards);
9261
9262         return stats;
9263 }
9264
9265 static inline u32 calc_crc(unsigned char *buf, int len)
9266 {
9267         u32 reg;
9268         u32 tmp;
9269         int j, k;
9270
9271         reg = 0xffffffff;
9272
9273         for (j = 0; j < len; j++) {
9274                 reg ^= buf[j];
9275
9276                 for (k = 0; k < 8; k++) {
9277                         tmp = reg & 0x01;
9278
9279                         reg >>= 1;
9280
9281                         if (tmp)
9282                                 reg ^= 0xedb88320;
9283                 }
9284         }
9285
9286         return ~reg;
9287 }
9288
9289 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9290 {
9291         /* accept or reject all multicast frames */
9292         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9293         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9294         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9295         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9296 }
9297
9298 static void __tg3_set_rx_mode(struct net_device *dev)
9299 {
9300         struct tg3 *tp = netdev_priv(dev);
9301         u32 rx_mode;
9302
9303         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9304                                   RX_MODE_KEEP_VLAN_TAG);
9305
9306         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9307          * flag clear.
9308          */
9309 #if TG3_VLAN_TAG_USED
9310         if (!tp->vlgrp &&
9311             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9312                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9313 #else
9314         /* By definition, VLAN is disabled always in this
9315          * case.
9316          */
9317         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9318                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9319 #endif
9320
9321         if (dev->flags & IFF_PROMISC) {
9322                 /* Promiscuous mode. */
9323                 rx_mode |= RX_MODE_PROMISC;
9324         } else if (dev->flags & IFF_ALLMULTI) {
9325                 /* Accept all multicast. */
9326                 tg3_set_multi(tp, 1);
9327         } else if (netdev_mc_empty(dev)) {
9328                 /* Reject all multicast. */
9329                 tg3_set_multi(tp, 0);
9330         } else {
9331                 /* Accept one or more multicast(s). */
9332                 struct netdev_hw_addr *ha;
9333                 u32 mc_filter[4] = { 0, };
9334                 u32 regidx;
9335                 u32 bit;
9336                 u32 crc;
9337
9338                 netdev_for_each_mc_addr(ha, dev) {
9339                         crc = calc_crc(ha->addr, ETH_ALEN);
9340                         bit = ~crc & 0x7f;
9341                         regidx = (bit & 0x60) >> 5;
9342                         bit &= 0x1f;
9343                         mc_filter[regidx] |= (1 << bit);
9344                 }
9345
9346                 tw32(MAC_HASH_REG_0, mc_filter[0]);
9347                 tw32(MAC_HASH_REG_1, mc_filter[1]);
9348                 tw32(MAC_HASH_REG_2, mc_filter[2]);
9349                 tw32(MAC_HASH_REG_3, mc_filter[3]);
9350         }
9351
9352         if (rx_mode != tp->rx_mode) {
9353                 tp->rx_mode = rx_mode;
9354                 tw32_f(MAC_RX_MODE, rx_mode);
9355                 udelay(10);
9356         }
9357 }
9358
9359 static void tg3_set_rx_mode(struct net_device *dev)
9360 {
9361         struct tg3 *tp = netdev_priv(dev);
9362
9363         if (!netif_running(dev))
9364                 return;
9365
9366         tg3_full_lock(tp, 0);
9367         __tg3_set_rx_mode(dev);
9368         tg3_full_unlock(tp);
9369 }
9370
9371 #define TG3_REGDUMP_LEN         (32 * 1024)
9372
9373 static int tg3_get_regs_len(struct net_device *dev)
9374 {
9375         return TG3_REGDUMP_LEN;
9376 }
9377
9378 static void tg3_get_regs(struct net_device *dev,
9379                 struct ethtool_regs *regs, void *_p)
9380 {
9381         u32 *p = _p;
9382         struct tg3 *tp = netdev_priv(dev);
9383         u8 *orig_p = _p;
9384         int i;
9385
9386         regs->version = 0;
9387
9388         memset(p, 0, TG3_REGDUMP_LEN);
9389
9390         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9391                 return;
9392
9393         tg3_full_lock(tp, 0);
9394
9395 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
9396 #define GET_REG32_LOOP(base, len)               \
9397 do {    p = (u32 *)(orig_p + (base));           \
9398         for (i = 0; i < len; i += 4)            \
9399                 __GET_REG32((base) + i);        \
9400 } while (0)
9401 #define GET_REG32_1(reg)                        \
9402 do {    p = (u32 *)(orig_p + (reg));            \
9403         __GET_REG32((reg));                     \
9404 } while (0)
9405
9406         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9407         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9408         GET_REG32_LOOP(MAC_MODE, 0x4f0);
9409         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9410         GET_REG32_1(SNDDATAC_MODE);
9411         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9412         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9413         GET_REG32_1(SNDBDC_MODE);
9414         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9415         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9416         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9417         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9418         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9419         GET_REG32_1(RCVDCC_MODE);
9420         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9421         GET_REG32_LOOP(RCVCC_MODE, 0x14);
9422         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9423         GET_REG32_1(MBFREE_MODE);
9424         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9425         GET_REG32_LOOP(MEMARB_MODE, 0x10);
9426         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9427         GET_REG32_LOOP(RDMAC_MODE, 0x08);
9428         GET_REG32_LOOP(WDMAC_MODE, 0x08);
9429         GET_REG32_1(RX_CPU_MODE);
9430         GET_REG32_1(RX_CPU_STATE);
9431         GET_REG32_1(RX_CPU_PGMCTR);
9432         GET_REG32_1(RX_CPU_HWBKPT);
9433         GET_REG32_1(TX_CPU_MODE);
9434         GET_REG32_1(TX_CPU_STATE);
9435         GET_REG32_1(TX_CPU_PGMCTR);
9436         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9437         GET_REG32_LOOP(FTQ_RESET, 0x120);
9438         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9439         GET_REG32_1(DMAC_MODE);
9440         GET_REG32_LOOP(GRC_MODE, 0x4c);
9441         if (tp->tg3_flags & TG3_FLAG_NVRAM)
9442                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9443
9444 #undef __GET_REG32
9445 #undef GET_REG32_LOOP
9446 #undef GET_REG32_1
9447
9448         tg3_full_unlock(tp);
9449 }
9450
9451 static int tg3_get_eeprom_len(struct net_device *dev)
9452 {
9453         struct tg3 *tp = netdev_priv(dev);
9454
9455         return tp->nvram_size;
9456 }
9457
9458 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9459 {
9460         struct tg3 *tp = netdev_priv(dev);
9461         int ret;
9462         u8  *pd;
9463         u32 i, offset, len, b_offset, b_count;
9464         __be32 val;
9465
9466         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9467                 return -EINVAL;
9468
9469         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9470                 return -EAGAIN;
9471
9472         offset = eeprom->offset;
9473         len = eeprom->len;
9474         eeprom->len = 0;
9475
9476         eeprom->magic = TG3_EEPROM_MAGIC;
9477
9478         if (offset & 3) {
9479                 /* adjustments to start on required 4 byte boundary */
9480                 b_offset = offset & 3;
9481                 b_count = 4 - b_offset;
9482                 if (b_count > len) {
9483                         /* i.e. offset=1 len=2 */
9484                         b_count = len;
9485                 }
9486                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9487                 if (ret)
9488                         return ret;
9489                 memcpy(data, ((char *)&val) + b_offset, b_count);
9490                 len -= b_count;
9491                 offset += b_count;
9492                 eeprom->len += b_count;
9493         }
9494
9495         /* read bytes upto the last 4 byte boundary */
9496         pd = &data[eeprom->len];
9497         for (i = 0; i < (len - (len & 3)); i += 4) {
9498                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9499                 if (ret) {
9500                         eeprom->len += i;
9501                         return ret;
9502                 }
9503                 memcpy(pd + i, &val, 4);
9504         }
9505         eeprom->len += i;
9506
9507         if (len & 3) {
9508                 /* read last bytes not ending on 4 byte boundary */
9509                 pd = &data[eeprom->len];
9510                 b_count = len & 3;
9511                 b_offset = offset + len - b_count;
9512                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9513                 if (ret)
9514                         return ret;
9515                 memcpy(pd, &val, b_count);
9516                 eeprom->len += b_count;
9517         }
9518         return 0;
9519 }
9520
9521 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9522
9523 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9524 {
9525         struct tg3 *tp = netdev_priv(dev);
9526         int ret;
9527         u32 offset, len, b_offset, odd_len;
9528         u8 *buf;
9529         __be32 start, end;
9530
9531         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9532                 return -EAGAIN;
9533
9534         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9535             eeprom->magic != TG3_EEPROM_MAGIC)
9536                 return -EINVAL;
9537
9538         offset = eeprom->offset;
9539         len = eeprom->len;
9540
9541         if ((b_offset = (offset & 3))) {
9542                 /* adjustments to start on required 4 byte boundary */
9543                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9544                 if (ret)
9545                         return ret;
9546                 len += b_offset;
9547                 offset &= ~3;
9548                 if (len < 4)
9549                         len = 4;
9550         }
9551
9552         odd_len = 0;
9553         if (len & 3) {
9554                 /* adjustments to end on required 4 byte boundary */
9555                 odd_len = 1;
9556                 len = (len + 3) & ~3;
9557                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9558                 if (ret)
9559                         return ret;
9560         }
9561
9562         buf = data;
9563         if (b_offset || odd_len) {
9564                 buf = kmalloc(len, GFP_KERNEL);
9565                 if (!buf)
9566                         return -ENOMEM;
9567                 if (b_offset)
9568                         memcpy(buf, &start, 4);
9569                 if (odd_len)
9570                         memcpy(buf+len-4, &end, 4);
9571                 memcpy(buf + b_offset, data, eeprom->len);
9572         }
9573
9574         ret = tg3_nvram_write_block(tp, offset, len, buf);
9575
9576         if (buf != data)
9577                 kfree(buf);
9578
9579         return ret;
9580 }
9581
9582 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9583 {
9584         struct tg3 *tp = netdev_priv(dev);
9585
9586         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9587                 struct phy_device *phydev;
9588                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9589                         return -EAGAIN;
9590                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9591                 return phy_ethtool_gset(phydev, cmd);
9592         }
9593
9594         cmd->supported = (SUPPORTED_Autoneg);
9595
9596         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9597                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9598                                    SUPPORTED_1000baseT_Full);
9599
9600         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
9601                 cmd->supported |= (SUPPORTED_100baseT_Half |
9602                                   SUPPORTED_100baseT_Full |
9603                                   SUPPORTED_10baseT_Half |
9604                                   SUPPORTED_10baseT_Full |
9605                                   SUPPORTED_TP);
9606                 cmd->port = PORT_TP;
9607         } else {
9608                 cmd->supported |= SUPPORTED_FIBRE;
9609                 cmd->port = PORT_FIBRE;
9610         }
9611
9612         cmd->advertising = tp->link_config.advertising;
9613         if (netif_running(dev)) {
9614                 cmd->speed = tp->link_config.active_speed;
9615                 cmd->duplex = tp->link_config.active_duplex;
9616         }
9617         cmd->phy_address = tp->phy_addr;
9618         cmd->transceiver = XCVR_INTERNAL;
9619         cmd->autoneg = tp->link_config.autoneg;
9620         cmd->maxtxpkt = 0;
9621         cmd->maxrxpkt = 0;
9622         return 0;
9623 }
9624
9625 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9626 {
9627         struct tg3 *tp = netdev_priv(dev);
9628
9629         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9630                 struct phy_device *phydev;
9631                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9632                         return -EAGAIN;
9633                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9634                 return phy_ethtool_sset(phydev, cmd);
9635         }
9636
9637         if (cmd->autoneg != AUTONEG_ENABLE &&
9638             cmd->autoneg != AUTONEG_DISABLE)
9639                 return -EINVAL;
9640
9641         if (cmd->autoneg == AUTONEG_DISABLE &&
9642             cmd->duplex != DUPLEX_FULL &&
9643             cmd->duplex != DUPLEX_HALF)
9644                 return -EINVAL;
9645
9646         if (cmd->autoneg == AUTONEG_ENABLE) {
9647                 u32 mask = ADVERTISED_Autoneg |
9648                            ADVERTISED_Pause |
9649                            ADVERTISED_Asym_Pause;
9650
9651                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9652                         mask |= ADVERTISED_1000baseT_Half |
9653                                 ADVERTISED_1000baseT_Full;
9654
9655                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
9656                         mask |= ADVERTISED_100baseT_Half |
9657                                 ADVERTISED_100baseT_Full |
9658                                 ADVERTISED_10baseT_Half |
9659                                 ADVERTISED_10baseT_Full |
9660                                 ADVERTISED_TP;
9661                 else
9662                         mask |= ADVERTISED_FIBRE;
9663
9664                 if (cmd->advertising & ~mask)
9665                         return -EINVAL;
9666
9667                 mask &= (ADVERTISED_1000baseT_Half |
9668                          ADVERTISED_1000baseT_Full |
9669                          ADVERTISED_100baseT_Half |
9670                          ADVERTISED_100baseT_Full |
9671                          ADVERTISED_10baseT_Half |
9672                          ADVERTISED_10baseT_Full);
9673
9674                 cmd->advertising &= mask;
9675         } else {
9676                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
9677                         if (cmd->speed != SPEED_1000)
9678                                 return -EINVAL;
9679
9680                         if (cmd->duplex != DUPLEX_FULL)
9681                                 return -EINVAL;
9682                 } else {
9683                         if (cmd->speed != SPEED_100 &&
9684                             cmd->speed != SPEED_10)
9685                                 return -EINVAL;
9686                 }
9687         }
9688
9689         tg3_full_lock(tp, 0);
9690
9691         tp->link_config.autoneg = cmd->autoneg;
9692         if (cmd->autoneg == AUTONEG_ENABLE) {
9693                 tp->link_config.advertising = (cmd->advertising |
9694                                               ADVERTISED_Autoneg);
9695                 tp->link_config.speed = SPEED_INVALID;
9696                 tp->link_config.duplex = DUPLEX_INVALID;
9697         } else {
9698                 tp->link_config.advertising = 0;
9699                 tp->link_config.speed = cmd->speed;
9700                 tp->link_config.duplex = cmd->duplex;
9701         }
9702
9703         tp->link_config.orig_speed = tp->link_config.speed;
9704         tp->link_config.orig_duplex = tp->link_config.duplex;
9705         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9706
9707         if (netif_running(dev))
9708                 tg3_setup_phy(tp, 1);
9709
9710         tg3_full_unlock(tp);
9711
9712         return 0;
9713 }
9714
9715 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9716 {
9717         struct tg3 *tp = netdev_priv(dev);
9718
9719         strcpy(info->driver, DRV_MODULE_NAME);
9720         strcpy(info->version, DRV_MODULE_VERSION);
9721         strcpy(info->fw_version, tp->fw_ver);
9722         strcpy(info->bus_info, pci_name(tp->pdev));
9723 }
9724
9725 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9726 {
9727         struct tg3 *tp = netdev_priv(dev);
9728
9729         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9730             device_can_wakeup(&tp->pdev->dev))
9731                 wol->supported = WAKE_MAGIC;
9732         else
9733                 wol->supported = 0;
9734         wol->wolopts = 0;
9735         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9736             device_can_wakeup(&tp->pdev->dev))
9737                 wol->wolopts = WAKE_MAGIC;
9738         memset(&wol->sopass, 0, sizeof(wol->sopass));
9739 }
9740
9741 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9742 {
9743         struct tg3 *tp = netdev_priv(dev);
9744         struct device *dp = &tp->pdev->dev;
9745
9746         if (wol->wolopts & ~WAKE_MAGIC)
9747                 return -EINVAL;
9748         if ((wol->wolopts & WAKE_MAGIC) &&
9749             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9750                 return -EINVAL;
9751
9752         spin_lock_bh(&tp->lock);
9753         if (wol->wolopts & WAKE_MAGIC) {
9754                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9755                 device_set_wakeup_enable(dp, true);
9756         } else {
9757                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9758                 device_set_wakeup_enable(dp, false);
9759         }
9760         spin_unlock_bh(&tp->lock);
9761
9762         return 0;
9763 }
9764
9765 static u32 tg3_get_msglevel(struct net_device *dev)
9766 {
9767         struct tg3 *tp = netdev_priv(dev);
9768         return tp->msg_enable;
9769 }
9770
9771 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9772 {
9773         struct tg3 *tp = netdev_priv(dev);
9774         tp->msg_enable = value;
9775 }
9776
9777 static int tg3_set_tso(struct net_device *dev, u32 value)
9778 {
9779         struct tg3 *tp = netdev_priv(dev);
9780
9781         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9782                 if (value)
9783                         return -EINVAL;
9784                 return 0;
9785         }
9786         if ((dev->features & NETIF_F_IPV6_CSUM) &&
9787             ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9788              (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9789                 if (value) {
9790                         dev->features |= NETIF_F_TSO6;
9791                         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9792                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9793                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9794                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9795                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9796                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9797                                 dev->features |= NETIF_F_TSO_ECN;
9798                 } else
9799                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9800         }
9801         return ethtool_op_set_tso(dev, value);
9802 }
9803
9804 static int tg3_nway_reset(struct net_device *dev)
9805 {
9806         struct tg3 *tp = netdev_priv(dev);
9807         int r;
9808
9809         if (!netif_running(dev))
9810                 return -EAGAIN;
9811
9812         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
9813                 return -EINVAL;
9814
9815         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9816                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9817                         return -EAGAIN;
9818                 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9819         } else {
9820                 u32 bmcr;
9821
9822                 spin_lock_bh(&tp->lock);
9823                 r = -EINVAL;
9824                 tg3_readphy(tp, MII_BMCR, &bmcr);
9825                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9826                     ((bmcr & BMCR_ANENABLE) ||
9827                      (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
9828                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9829                                                    BMCR_ANENABLE);
9830                         r = 0;
9831                 }
9832                 spin_unlock_bh(&tp->lock);
9833         }
9834
9835         return r;
9836 }
9837
9838 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9839 {
9840         struct tg3 *tp = netdev_priv(dev);
9841
9842         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9843         ering->rx_mini_max_pending = 0;
9844         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9845                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9846         else
9847                 ering->rx_jumbo_max_pending = 0;
9848
9849         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9850
9851         ering->rx_pending = tp->rx_pending;
9852         ering->rx_mini_pending = 0;
9853         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9854                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9855         else
9856                 ering->rx_jumbo_pending = 0;
9857
9858         ering->tx_pending = tp->napi[0].tx_pending;
9859 }
9860
9861 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9862 {
9863         struct tg3 *tp = netdev_priv(dev);
9864         int i, irq_sync = 0, err = 0;
9865
9866         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9867             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9868             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9869             (ering->tx_pending <= MAX_SKB_FRAGS) ||
9870             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9871              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9872                 return -EINVAL;
9873
9874         if (netif_running(dev)) {
9875                 tg3_phy_stop(tp);
9876                 tg3_netif_stop(tp);
9877                 irq_sync = 1;
9878         }
9879
9880         tg3_full_lock(tp, irq_sync);
9881
9882         tp->rx_pending = ering->rx_pending;
9883
9884         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9885             tp->rx_pending > 63)
9886                 tp->rx_pending = 63;
9887         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9888
9889         for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9890                 tp->napi[i].tx_pending = ering->tx_pending;
9891
9892         if (netif_running(dev)) {
9893                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9894                 err = tg3_restart_hw(tp, 1);
9895                 if (!err)
9896                         tg3_netif_start(tp);
9897         }
9898
9899         tg3_full_unlock(tp);
9900
9901         if (irq_sync && !err)
9902                 tg3_phy_start(tp);
9903
9904         return err;
9905 }
9906
9907 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9908 {
9909         struct tg3 *tp = netdev_priv(dev);
9910
9911         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9912
9913         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9914                 epause->rx_pause = 1;
9915         else
9916                 epause->rx_pause = 0;
9917
9918         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9919                 epause->tx_pause = 1;
9920         else
9921                 epause->tx_pause = 0;
9922 }
9923
9924 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9925 {
9926         struct tg3 *tp = netdev_priv(dev);
9927         int err = 0;
9928
9929         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9930                 u32 newadv;
9931                 struct phy_device *phydev;
9932
9933                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9934
9935                 if (!(phydev->supported & SUPPORTED_Pause) ||
9936                     (!(phydev->supported & SUPPORTED_Asym_Pause) &&
9937                      ((epause->rx_pause && !epause->tx_pause) ||
9938                       (!epause->rx_pause && epause->tx_pause))))
9939                         return -EINVAL;
9940
9941                 tp->link_config.flowctrl = 0;
9942                 if (epause->rx_pause) {
9943                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
9944
9945                         if (epause->tx_pause) {
9946                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9947                                 newadv = ADVERTISED_Pause;
9948                         } else
9949                                 newadv = ADVERTISED_Pause |
9950                                          ADVERTISED_Asym_Pause;
9951                 } else if (epause->tx_pause) {
9952                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
9953                         newadv = ADVERTISED_Asym_Pause;
9954                 } else
9955                         newadv = 0;
9956
9957                 if (epause->autoneg)
9958                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9959                 else
9960                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9961
9962                 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
9963                         u32 oldadv = phydev->advertising &
9964                                      (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
9965                         if (oldadv != newadv) {
9966                                 phydev->advertising &=
9967                                         ~(ADVERTISED_Pause |
9968                                           ADVERTISED_Asym_Pause);
9969                                 phydev->advertising |= newadv;
9970                                 if (phydev->autoneg) {
9971                                         /*
9972                                          * Always renegotiate the link to
9973                                          * inform our link partner of our
9974                                          * flow control settings, even if the
9975                                          * flow control is forced.  Let
9976                                          * tg3_adjust_link() do the final
9977                                          * flow control setup.
9978                                          */
9979                                         return phy_start_aneg(phydev);
9980                                 }
9981                         }
9982
9983                         if (!epause->autoneg)
9984                                 tg3_setup_flow_control(tp, 0, 0);
9985                 } else {
9986                         tp->link_config.orig_advertising &=
9987                                         ~(ADVERTISED_Pause |
9988                                           ADVERTISED_Asym_Pause);
9989                         tp->link_config.orig_advertising |= newadv;
9990                 }
9991         } else {
9992                 int irq_sync = 0;
9993
9994                 if (netif_running(dev)) {
9995                         tg3_netif_stop(tp);
9996                         irq_sync = 1;
9997                 }
9998
9999                 tg3_full_lock(tp, irq_sync);
10000
10001                 if (epause->autoneg)
10002                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10003                 else
10004                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10005                 if (epause->rx_pause)
10006                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
10007                 else
10008                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10009                 if (epause->tx_pause)
10010                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
10011                 else
10012                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10013
10014                 if (netif_running(dev)) {
10015                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10016                         err = tg3_restart_hw(tp, 1);
10017                         if (!err)
10018                                 tg3_netif_start(tp);
10019                 }
10020
10021                 tg3_full_unlock(tp);
10022         }
10023
10024         return err;
10025 }
10026
10027 static u32 tg3_get_rx_csum(struct net_device *dev)
10028 {
10029         struct tg3 *tp = netdev_priv(dev);
10030         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10031 }
10032
10033 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10034 {
10035         struct tg3 *tp = netdev_priv(dev);
10036
10037         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10038                 if (data != 0)
10039                         return -EINVAL;
10040                 return 0;
10041         }
10042
10043         spin_lock_bh(&tp->lock);
10044         if (data)
10045                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10046         else
10047                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10048         spin_unlock_bh(&tp->lock);
10049
10050         return 0;
10051 }
10052
10053 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10054 {
10055         struct tg3 *tp = netdev_priv(dev);
10056
10057         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10058                 if (data != 0)
10059                         return -EINVAL;
10060                 return 0;
10061         }
10062
10063         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10064                 ethtool_op_set_tx_ipv6_csum(dev, data);
10065         else
10066                 ethtool_op_set_tx_csum(dev, data);
10067
10068         return 0;
10069 }
10070
10071 static int tg3_get_sset_count(struct net_device *dev, int sset)
10072 {
10073         switch (sset) {
10074         case ETH_SS_TEST:
10075                 return TG3_NUM_TEST;
10076         case ETH_SS_STATS:
10077                 return TG3_NUM_STATS;
10078         default:
10079                 return -EOPNOTSUPP;
10080         }
10081 }
10082
10083 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
10084 {
10085         switch (stringset) {
10086         case ETH_SS_STATS:
10087                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10088                 break;
10089         case ETH_SS_TEST:
10090                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10091                 break;
10092         default:
10093                 WARN_ON(1);     /* we need a WARN() */
10094                 break;
10095         }
10096 }
10097
10098 static int tg3_phys_id(struct net_device *dev, u32 data)
10099 {
10100         struct tg3 *tp = netdev_priv(dev);
10101         int i;
10102
10103         if (!netif_running(tp->dev))
10104                 return -EAGAIN;
10105
10106         if (data == 0)
10107                 data = UINT_MAX / 2;
10108
10109         for (i = 0; i < (data * 2); i++) {
10110                 if ((i % 2) == 0)
10111                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10112                                            LED_CTRL_1000MBPS_ON |
10113                                            LED_CTRL_100MBPS_ON |
10114                                            LED_CTRL_10MBPS_ON |
10115                                            LED_CTRL_TRAFFIC_OVERRIDE |
10116                                            LED_CTRL_TRAFFIC_BLINK |
10117                                            LED_CTRL_TRAFFIC_LED);
10118
10119                 else
10120                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10121                                            LED_CTRL_TRAFFIC_OVERRIDE);
10122
10123                 if (msleep_interruptible(500))
10124                         break;
10125         }
10126         tw32(MAC_LED_CTRL, tp->led_ctrl);
10127         return 0;
10128 }
10129
10130 static void tg3_get_ethtool_stats(struct net_device *dev,
10131                                    struct ethtool_stats *estats, u64 *tmp_stats)
10132 {
10133         struct tg3 *tp = netdev_priv(dev);
10134         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10135 }
10136
10137 #define NVRAM_TEST_SIZE 0x100
10138 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
10139 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
10140 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
10141 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10142 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10143
10144 static int tg3_test_nvram(struct tg3 *tp)
10145 {
10146         u32 csum, magic;
10147         __be32 *buf;
10148         int i, j, k, err = 0, size;
10149
10150         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10151                 return 0;
10152
10153         if (tg3_nvram_read(tp, 0, &magic) != 0)
10154                 return -EIO;
10155
10156         if (magic == TG3_EEPROM_MAGIC)
10157                 size = NVRAM_TEST_SIZE;
10158         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10159                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10160                     TG3_EEPROM_SB_FORMAT_1) {
10161                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10162                         case TG3_EEPROM_SB_REVISION_0:
10163                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10164                                 break;
10165                         case TG3_EEPROM_SB_REVISION_2:
10166                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10167                                 break;
10168                         case TG3_EEPROM_SB_REVISION_3:
10169                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10170                                 break;
10171                         default:
10172                                 return 0;
10173                         }
10174                 } else
10175                         return 0;
10176         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10177                 size = NVRAM_SELFBOOT_HW_SIZE;
10178         else
10179                 return -EIO;
10180
10181         buf = kmalloc(size, GFP_KERNEL);
10182         if (buf == NULL)
10183                 return -ENOMEM;
10184
10185         err = -EIO;
10186         for (i = 0, j = 0; i < size; i += 4, j++) {
10187                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10188                 if (err)
10189                         break;
10190         }
10191         if (i < size)
10192                 goto out;
10193
10194         /* Selfboot format */
10195         magic = be32_to_cpu(buf[0]);
10196         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10197             TG3_EEPROM_MAGIC_FW) {
10198                 u8 *buf8 = (u8 *) buf, csum8 = 0;
10199
10200                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10201                     TG3_EEPROM_SB_REVISION_2) {
10202                         /* For rev 2, the csum doesn't include the MBA. */
10203                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10204                                 csum8 += buf8[i];
10205                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10206                                 csum8 += buf8[i];
10207                 } else {
10208                         for (i = 0; i < size; i++)
10209                                 csum8 += buf8[i];
10210                 }
10211
10212                 if (csum8 == 0) {
10213                         err = 0;
10214                         goto out;
10215                 }
10216
10217                 err = -EIO;
10218                 goto out;
10219         }
10220
10221         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10222             TG3_EEPROM_MAGIC_HW) {
10223                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10224                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10225                 u8 *buf8 = (u8 *) buf;
10226
10227                 /* Separate the parity bits and the data bytes.  */
10228                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10229                         if ((i == 0) || (i == 8)) {
10230                                 int l;
10231                                 u8 msk;
10232
10233                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10234                                         parity[k++] = buf8[i] & msk;
10235                                 i++;
10236                         } else if (i == 16) {
10237                                 int l;
10238                                 u8 msk;
10239
10240                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10241                                         parity[k++] = buf8[i] & msk;
10242                                 i++;
10243
10244                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10245                                         parity[k++] = buf8[i] & msk;
10246                                 i++;
10247                         }
10248                         data[j++] = buf8[i];
10249                 }
10250
10251                 err = -EIO;
10252                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10253                         u8 hw8 = hweight8(data[i]);
10254
10255                         if ((hw8 & 0x1) && parity[i])
10256                                 goto out;
10257                         else if (!(hw8 & 0x1) && !parity[i])
10258                                 goto out;
10259                 }
10260                 err = 0;
10261                 goto out;
10262         }
10263
10264         /* Bootstrap checksum at offset 0x10 */
10265         csum = calc_crc((unsigned char *) buf, 0x10);
10266         if (csum != be32_to_cpu(buf[0x10/4]))
10267                 goto out;
10268
10269         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10270         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10271         if (csum != be32_to_cpu(buf[0xfc/4]))
10272                 goto out;
10273
10274         err = 0;
10275
10276 out:
10277         kfree(buf);
10278         return err;
10279 }
10280
10281 #define TG3_SERDES_TIMEOUT_SEC  2
10282 #define TG3_COPPER_TIMEOUT_SEC  6
10283
10284 static int tg3_test_link(struct tg3 *tp)
10285 {
10286         int i, max;
10287
10288         if (!netif_running(tp->dev))
10289                 return -ENODEV;
10290
10291         if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
10292                 max = TG3_SERDES_TIMEOUT_SEC;
10293         else
10294                 max = TG3_COPPER_TIMEOUT_SEC;
10295
10296         for (i = 0; i < max; i++) {
10297                 if (netif_carrier_ok(tp->dev))
10298                         return 0;
10299
10300                 if (msleep_interruptible(1000))
10301                         break;
10302         }
10303
10304         return -EIO;
10305 }
10306
10307 /* Only test the commonly used registers */
10308 static int tg3_test_registers(struct tg3 *tp)
10309 {
10310         int i, is_5705, is_5750;
10311         u32 offset, read_mask, write_mask, val, save_val, read_val;
10312         static struct {
10313                 u16 offset;
10314                 u16 flags;
10315 #define TG3_FL_5705     0x1
10316 #define TG3_FL_NOT_5705 0x2
10317 #define TG3_FL_NOT_5788 0x4
10318 #define TG3_FL_NOT_5750 0x8
10319                 u32 read_mask;
10320                 u32 write_mask;
10321         } reg_tbl[] = {
10322                 /* MAC Control Registers */
10323                 { MAC_MODE, TG3_FL_NOT_5705,
10324                         0x00000000, 0x00ef6f8c },
10325                 { MAC_MODE, TG3_FL_5705,
10326                         0x00000000, 0x01ef6b8c },
10327                 { MAC_STATUS, TG3_FL_NOT_5705,
10328                         0x03800107, 0x00000000 },
10329                 { MAC_STATUS, TG3_FL_5705,
10330                         0x03800100, 0x00000000 },
10331                 { MAC_ADDR_0_HIGH, 0x0000,
10332                         0x00000000, 0x0000ffff },
10333                 { MAC_ADDR_0_LOW, 0x0000,
10334                         0x00000000, 0xffffffff },
10335                 { MAC_RX_MTU_SIZE, 0x0000,
10336                         0x00000000, 0x0000ffff },
10337                 { MAC_TX_MODE, 0x0000,
10338                         0x00000000, 0x00000070 },
10339                 { MAC_TX_LENGTHS, 0x0000,
10340                         0x00000000, 0x00003fff },
10341                 { MAC_RX_MODE, TG3_FL_NOT_5705,
10342                         0x00000000, 0x000007fc },
10343                 { MAC_RX_MODE, TG3_FL_5705,
10344                         0x00000000, 0x000007dc },
10345                 { MAC_HASH_REG_0, 0x0000,
10346                         0x00000000, 0xffffffff },
10347                 { MAC_HASH_REG_1, 0x0000,
10348                         0x00000000, 0xffffffff },
10349                 { MAC_HASH_REG_2, 0x0000,
10350                         0x00000000, 0xffffffff },
10351                 { MAC_HASH_REG_3, 0x0000,
10352                         0x00000000, 0xffffffff },
10353
10354                 /* Receive Data and Receive BD Initiator Control Registers. */
10355                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10356                         0x00000000, 0xffffffff },
10357                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10358                         0x00000000, 0xffffffff },
10359                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10360                         0x00000000, 0x00000003 },
10361                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10362                         0x00000000, 0xffffffff },
10363                 { RCVDBDI_STD_BD+0, 0x0000,
10364                         0x00000000, 0xffffffff },
10365                 { RCVDBDI_STD_BD+4, 0x0000,
10366                         0x00000000, 0xffffffff },
10367                 { RCVDBDI_STD_BD+8, 0x0000,
10368                         0x00000000, 0xffff0002 },
10369                 { RCVDBDI_STD_BD+0xc, 0x0000,
10370                         0x00000000, 0xffffffff },
10371
10372                 /* Receive BD Initiator Control Registers. */
10373                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10374                         0x00000000, 0xffffffff },
10375                 { RCVBDI_STD_THRESH, TG3_FL_5705,
10376                         0x00000000, 0x000003ff },
10377                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10378                         0x00000000, 0xffffffff },
10379
10380                 /* Host Coalescing Control Registers. */
10381                 { HOSTCC_MODE, TG3_FL_NOT_5705,
10382                         0x00000000, 0x00000004 },
10383                 { HOSTCC_MODE, TG3_FL_5705,
10384                         0x00000000, 0x000000f6 },
10385                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10386                         0x00000000, 0xffffffff },
10387                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10388                         0x00000000, 0x000003ff },
10389                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10390                         0x00000000, 0xffffffff },
10391                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10392                         0x00000000, 0x000003ff },
10393                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10394                         0x00000000, 0xffffffff },
10395                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10396                         0x00000000, 0x000000ff },
10397                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10398                         0x00000000, 0xffffffff },
10399                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10400                         0x00000000, 0x000000ff },
10401                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10402                         0x00000000, 0xffffffff },
10403                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10404                         0x00000000, 0xffffffff },
10405                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10406                         0x00000000, 0xffffffff },
10407                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10408                         0x00000000, 0x000000ff },
10409                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10410                         0x00000000, 0xffffffff },
10411                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10412                         0x00000000, 0x000000ff },
10413                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10414                         0x00000000, 0xffffffff },
10415                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10416                         0x00000000, 0xffffffff },
10417                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10418                         0x00000000, 0xffffffff },
10419                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10420                         0x00000000, 0xffffffff },
10421                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10422                         0x00000000, 0xffffffff },
10423                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10424                         0xffffffff, 0x00000000 },
10425                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10426                         0xffffffff, 0x00000000 },
10427
10428                 /* Buffer Manager Control Registers. */
10429                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10430                         0x00000000, 0x007fff80 },
10431                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10432                         0x00000000, 0x007fffff },
10433                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10434                         0x00000000, 0x0000003f },
10435                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10436                         0x00000000, 0x000001ff },
10437                 { BUFMGR_MB_HIGH_WATER, 0x0000,
10438                         0x00000000, 0x000001ff },
10439                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10440                         0xffffffff, 0x00000000 },
10441                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10442                         0xffffffff, 0x00000000 },
10443
10444                 /* Mailbox Registers */
10445                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10446                         0x00000000, 0x000001ff },
10447                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10448                         0x00000000, 0x000001ff },
10449                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10450                         0x00000000, 0x000007ff },
10451                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10452                         0x00000000, 0x000001ff },
10453
10454                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10455         };
10456
10457         is_5705 = is_5750 = 0;
10458         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10459                 is_5705 = 1;
10460                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10461                         is_5750 = 1;
10462         }
10463
10464         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10465                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10466                         continue;
10467
10468                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10469                         continue;
10470
10471                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10472                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
10473                         continue;
10474
10475                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10476                         continue;
10477
10478                 offset = (u32) reg_tbl[i].offset;
10479                 read_mask = reg_tbl[i].read_mask;
10480                 write_mask = reg_tbl[i].write_mask;
10481
10482                 /* Save the original register content */
10483                 save_val = tr32(offset);
10484
10485                 /* Determine the read-only value. */
10486                 read_val = save_val & read_mask;
10487
10488                 /* Write zero to the register, then make sure the read-only bits
10489                  * are not changed and the read/write bits are all zeros.
10490                  */
10491                 tw32(offset, 0);
10492
10493                 val = tr32(offset);
10494
10495                 /* Test the read-only and read/write bits. */
10496                 if (((val & read_mask) != read_val) || (val & write_mask))
10497                         goto out;
10498
10499                 /* Write ones to all the bits defined by RdMask and WrMask, then
10500                  * make sure the read-only bits are not changed and the
10501                  * read/write bits are all ones.
10502                  */
10503                 tw32(offset, read_mask | write_mask);
10504
10505                 val = tr32(offset);
10506
10507                 /* Test the read-only bits. */
10508                 if ((val & read_mask) != read_val)
10509                         goto out;
10510
10511                 /* Test the read/write bits. */
10512                 if ((val & write_mask) != write_mask)
10513                         goto out;
10514
10515                 tw32(offset, save_val);
10516         }
10517
10518         return 0;
10519
10520 out:
10521         if (netif_msg_hw(tp))
10522                 netdev_err(tp->dev,
10523                            "Register test failed at offset %x\n", offset);
10524         tw32(offset, save_val);
10525         return -EIO;
10526 }
10527
10528 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10529 {
10530         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10531         int i;
10532         u32 j;
10533
10534         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10535                 for (j = 0; j < len; j += 4) {
10536                         u32 val;
10537
10538                         tg3_write_mem(tp, offset + j, test_pattern[i]);
10539                         tg3_read_mem(tp, offset + j, &val);
10540                         if (val != test_pattern[i])
10541                                 return -EIO;
10542                 }
10543         }
10544         return 0;
10545 }
10546
10547 static int tg3_test_memory(struct tg3 *tp)
10548 {
10549         static struct mem_entry {
10550                 u32 offset;
10551                 u32 len;
10552         } mem_tbl_570x[] = {
10553                 { 0x00000000, 0x00b50},
10554                 { 0x00002000, 0x1c000},
10555                 { 0xffffffff, 0x00000}
10556         }, mem_tbl_5705[] = {
10557                 { 0x00000100, 0x0000c},
10558                 { 0x00000200, 0x00008},
10559                 { 0x00004000, 0x00800},
10560                 { 0x00006000, 0x01000},
10561                 { 0x00008000, 0x02000},
10562                 { 0x00010000, 0x0e000},
10563                 { 0xffffffff, 0x00000}
10564         }, mem_tbl_5755[] = {
10565                 { 0x00000200, 0x00008},
10566                 { 0x00004000, 0x00800},
10567                 { 0x00006000, 0x00800},
10568                 { 0x00008000, 0x02000},
10569                 { 0x00010000, 0x0c000},
10570                 { 0xffffffff, 0x00000}
10571         }, mem_tbl_5906[] = {
10572                 { 0x00000200, 0x00008},
10573                 { 0x00004000, 0x00400},
10574                 { 0x00006000, 0x00400},
10575                 { 0x00008000, 0x01000},
10576                 { 0x00010000, 0x01000},
10577                 { 0xffffffff, 0x00000}
10578         }, mem_tbl_5717[] = {
10579                 { 0x00000200, 0x00008},
10580                 { 0x00010000, 0x0a000},
10581                 { 0x00020000, 0x13c00},
10582                 { 0xffffffff, 0x00000}
10583         }, mem_tbl_57765[] = {
10584                 { 0x00000200, 0x00008},
10585                 { 0x00004000, 0x00800},
10586                 { 0x00006000, 0x09800},
10587                 { 0x00010000, 0x0a000},
10588                 { 0xffffffff, 0x00000}
10589         };
10590         struct mem_entry *mem_tbl;
10591         int err = 0;
10592         int i;
10593
10594         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
10595             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
10596                 mem_tbl = mem_tbl_5717;
10597         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10598                 mem_tbl = mem_tbl_57765;
10599         else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10600                 mem_tbl = mem_tbl_5755;
10601         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10602                 mem_tbl = mem_tbl_5906;
10603         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10604                 mem_tbl = mem_tbl_5705;
10605         else
10606                 mem_tbl = mem_tbl_570x;
10607
10608         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10609                 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
10610                 if (err)
10611                         break;
10612         }
10613
10614         return err;
10615 }
10616
10617 #define TG3_MAC_LOOPBACK        0
10618 #define TG3_PHY_LOOPBACK        1
10619
10620 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10621 {
10622         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10623         u32 desc_idx, coal_now;
10624         struct sk_buff *skb, *rx_skb;
10625         u8 *tx_data;
10626         dma_addr_t map;
10627         int num_pkts, tx_len, rx_len, i, err;
10628         struct tg3_rx_buffer_desc *desc;
10629         struct tg3_napi *tnapi, *rnapi;
10630         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
10631
10632         tnapi = &tp->napi[0];
10633         rnapi = &tp->napi[0];
10634         if (tp->irq_cnt > 1) {
10635                 rnapi = &tp->napi[1];
10636                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
10637                         tnapi = &tp->napi[1];
10638         }
10639         coal_now = tnapi->coal_now | rnapi->coal_now;
10640
10641         if (loopback_mode == TG3_MAC_LOOPBACK) {
10642                 /* HW errata - mac loopback fails in some cases on 5780.
10643                  * Normal traffic and PHY loopback are not affected by
10644                  * errata.
10645                  */
10646                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10647                         return 0;
10648
10649                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10650                            MAC_MODE_PORT_INT_LPBACK;
10651                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10652                         mac_mode |= MAC_MODE_LINK_POLARITY;
10653                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
10654                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10655                 else
10656                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10657                 tw32(MAC_MODE, mac_mode);
10658         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10659                 u32 val;
10660
10661                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10662                         tg3_phy_fet_toggle_apd(tp, false);
10663                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10664                 } else
10665                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10666
10667                 tg3_phy_toggle_automdix(tp, 0);
10668
10669                 tg3_writephy(tp, MII_BMCR, val);
10670                 udelay(40);
10671
10672                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10673                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10674                         tg3_writephy(tp, MII_TG3_FET_PTEST,
10675                                      MII_TG3_FET_PTEST_FRC_TX_LINK |
10676                                      MII_TG3_FET_PTEST_FRC_TX_LOCK);
10677                         /* The write needs to be flushed for the AC131 */
10678                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10679                                 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
10680                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10681                 } else
10682                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10683
10684                 /* reset to prevent losing 1st rx packet intermittently */
10685                 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10686                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10687                         udelay(10);
10688                         tw32_f(MAC_RX_MODE, tp->rx_mode);
10689                 }
10690                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10691                         u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
10692                         if (masked_phy_id == TG3_PHY_ID_BCM5401)
10693                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10694                         else if (masked_phy_id == TG3_PHY_ID_BCM5411)
10695                                 mac_mode |= MAC_MODE_LINK_POLARITY;
10696                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
10697                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10698                 }
10699                 tw32(MAC_MODE, mac_mode);
10700         } else {
10701                 return -EINVAL;
10702         }
10703
10704         err = -EIO;
10705
10706         tx_len = 1514;
10707         skb = netdev_alloc_skb(tp->dev, tx_len);
10708         if (!skb)
10709                 return -ENOMEM;
10710
10711         tx_data = skb_put(skb, tx_len);
10712         memcpy(tx_data, tp->dev->dev_addr, 6);
10713         memset(tx_data + 6, 0x0, 8);
10714
10715         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10716
10717         for (i = 14; i < tx_len; i++)
10718                 tx_data[i] = (u8) (i & 0xff);
10719
10720         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10721         if (pci_dma_mapping_error(tp->pdev, map)) {
10722                 dev_kfree_skb(skb);
10723                 return -EIO;
10724         }
10725
10726         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10727                rnapi->coal_now);
10728
10729         udelay(10);
10730
10731         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10732
10733         num_pkts = 0;
10734
10735         tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10736
10737         tnapi->tx_prod++;
10738         num_pkts++;
10739
10740         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10741         tr32_mailbox(tnapi->prodmbox);
10742
10743         udelay(10);
10744
10745         /* 350 usec to allow enough time on some 10/100 Mbps devices.  */
10746         for (i = 0; i < 35; i++) {
10747                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10748                        coal_now);
10749
10750                 udelay(10);
10751
10752                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10753                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10754                 if ((tx_idx == tnapi->tx_prod) &&
10755                     (rx_idx == (rx_start_idx + num_pkts)))
10756                         break;
10757         }
10758
10759         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10760         dev_kfree_skb(skb);
10761
10762         if (tx_idx != tnapi->tx_prod)
10763                 goto out;
10764
10765         if (rx_idx != rx_start_idx + num_pkts)
10766                 goto out;
10767
10768         desc = &rnapi->rx_rcb[rx_start_idx];
10769         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10770         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10771         if (opaque_key != RXD_OPAQUE_RING_STD)
10772                 goto out;
10773
10774         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10775             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10776                 goto out;
10777
10778         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10779         if (rx_len != tx_len)
10780                 goto out;
10781
10782         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10783
10784         map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10785         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10786
10787         for (i = 14; i < tx_len; i++) {
10788                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10789                         goto out;
10790         }
10791         err = 0;
10792
10793         /* tg3_free_rings will unmap and free the rx_skb */
10794 out:
10795         return err;
10796 }
10797
10798 #define TG3_MAC_LOOPBACK_FAILED         1
10799 #define TG3_PHY_LOOPBACK_FAILED         2
10800 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
10801                                          TG3_PHY_LOOPBACK_FAILED)
10802
10803 static int tg3_test_loopback(struct tg3 *tp)
10804 {
10805         int err = 0;
10806         u32 cpmuctrl = 0;
10807
10808         if (!netif_running(tp->dev))
10809                 return TG3_LOOPBACK_FAILED;
10810
10811         err = tg3_reset_hw(tp, 1);
10812         if (err)
10813                 return TG3_LOOPBACK_FAILED;
10814
10815         /* Turn off gphy autopowerdown. */
10816         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
10817                 tg3_phy_toggle_apd(tp, false);
10818
10819         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10820                 int i;
10821                 u32 status;
10822
10823                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10824
10825                 /* Wait for up to 40 microseconds to acquire lock. */
10826                 for (i = 0; i < 4; i++) {
10827                         status = tr32(TG3_CPMU_MUTEX_GNT);
10828                         if (status == CPMU_MUTEX_GNT_DRIVER)
10829                                 break;
10830                         udelay(10);
10831                 }
10832
10833                 if (status != CPMU_MUTEX_GNT_DRIVER)
10834                         return TG3_LOOPBACK_FAILED;
10835
10836                 /* Turn off link-based power management. */
10837                 cpmuctrl = tr32(TG3_CPMU_CTRL);
10838                 tw32(TG3_CPMU_CTRL,
10839                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10840                                   CPMU_CTRL_LINK_AWARE_MODE));
10841         }
10842
10843         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10844                 err |= TG3_MAC_LOOPBACK_FAILED;
10845
10846         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10847                 tw32(TG3_CPMU_CTRL, cpmuctrl);
10848
10849                 /* Release the mutex */
10850                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10851         }
10852
10853         if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10854             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10855                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10856                         err |= TG3_PHY_LOOPBACK_FAILED;
10857         }
10858
10859         /* Re-enable gphy autopowerdown. */
10860         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
10861                 tg3_phy_toggle_apd(tp, true);
10862
10863         return err;
10864 }
10865
10866 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10867                           u64 *data)
10868 {
10869         struct tg3 *tp = netdev_priv(dev);
10870
10871         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10872                 tg3_set_power_state(tp, PCI_D0);
10873
10874         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10875
10876         if (tg3_test_nvram(tp) != 0) {
10877                 etest->flags |= ETH_TEST_FL_FAILED;
10878                 data[0] = 1;
10879         }
10880         if (tg3_test_link(tp) != 0) {
10881                 etest->flags |= ETH_TEST_FL_FAILED;
10882                 data[1] = 1;
10883         }
10884         if (etest->flags & ETH_TEST_FL_OFFLINE) {
10885                 int err, err2 = 0, irq_sync = 0;
10886
10887                 if (netif_running(dev)) {
10888                         tg3_phy_stop(tp);
10889                         tg3_netif_stop(tp);
10890                         irq_sync = 1;
10891                 }
10892
10893                 tg3_full_lock(tp, irq_sync);
10894
10895                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10896                 err = tg3_nvram_lock(tp);
10897                 tg3_halt_cpu(tp, RX_CPU_BASE);
10898                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10899                         tg3_halt_cpu(tp, TX_CPU_BASE);
10900                 if (!err)
10901                         tg3_nvram_unlock(tp);
10902
10903                 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
10904                         tg3_phy_reset(tp);
10905
10906                 if (tg3_test_registers(tp) != 0) {
10907                         etest->flags |= ETH_TEST_FL_FAILED;
10908                         data[2] = 1;
10909                 }
10910                 if (tg3_test_memory(tp) != 0) {
10911                         etest->flags |= ETH_TEST_FL_FAILED;
10912                         data[3] = 1;
10913                 }
10914                 if ((data[4] = tg3_test_loopback(tp)) != 0)
10915                         etest->flags |= ETH_TEST_FL_FAILED;
10916
10917                 tg3_full_unlock(tp);
10918
10919                 if (tg3_test_interrupt(tp) != 0) {
10920                         etest->flags |= ETH_TEST_FL_FAILED;
10921                         data[5] = 1;
10922                 }
10923
10924                 tg3_full_lock(tp, 0);
10925
10926                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10927                 if (netif_running(dev)) {
10928                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10929                         err2 = tg3_restart_hw(tp, 1);
10930                         if (!err2)
10931                                 tg3_netif_start(tp);
10932                 }
10933
10934                 tg3_full_unlock(tp);
10935
10936                 if (irq_sync && !err2)
10937                         tg3_phy_start(tp);
10938         }
10939         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10940                 tg3_set_power_state(tp, PCI_D3hot);
10941
10942 }
10943
10944 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10945 {
10946         struct mii_ioctl_data *data = if_mii(ifr);
10947         struct tg3 *tp = netdev_priv(dev);
10948         int err;
10949
10950         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10951                 struct phy_device *phydev;
10952                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10953                         return -EAGAIN;
10954                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10955                 return phy_mii_ioctl(phydev, ifr, cmd);
10956         }
10957
10958         switch (cmd) {
10959         case SIOCGMIIPHY:
10960                 data->phy_id = tp->phy_addr;
10961
10962                 /* fallthru */
10963         case SIOCGMIIREG: {
10964                 u32 mii_regval;
10965
10966                 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
10967                         break;                  /* We have no PHY */
10968
10969                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10970                         return -EAGAIN;
10971
10972                 spin_lock_bh(&tp->lock);
10973                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10974                 spin_unlock_bh(&tp->lock);
10975
10976                 data->val_out = mii_regval;
10977
10978                 return err;
10979         }
10980
10981         case SIOCSMIIREG:
10982                 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
10983                         break;                  /* We have no PHY */
10984
10985                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10986                         return -EAGAIN;
10987
10988                 spin_lock_bh(&tp->lock);
10989                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10990                 spin_unlock_bh(&tp->lock);
10991
10992                 return err;
10993
10994         default:
10995                 /* do nothing */
10996                 break;
10997         }
10998         return -EOPNOTSUPP;
10999 }
11000
11001 #if TG3_VLAN_TAG_USED
11002 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
11003 {
11004         struct tg3 *tp = netdev_priv(dev);
11005
11006         if (!netif_running(dev)) {
11007                 tp->vlgrp = grp;
11008                 return;
11009         }
11010
11011         tg3_netif_stop(tp);
11012
11013         tg3_full_lock(tp, 0);
11014
11015         tp->vlgrp = grp;
11016
11017         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11018         __tg3_set_rx_mode(dev);
11019
11020         tg3_netif_start(tp);
11021
11022         tg3_full_unlock(tp);
11023 }
11024 #endif
11025
11026 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11027 {
11028         struct tg3 *tp = netdev_priv(dev);
11029
11030         memcpy(ec, &tp->coal, sizeof(*ec));
11031         return 0;
11032 }
11033
11034 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11035 {
11036         struct tg3 *tp = netdev_priv(dev);
11037         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11038         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11039
11040         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11041                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11042                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11043                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11044                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11045         }
11046
11047         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11048             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11049             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11050             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11051             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11052             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11053             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11054             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11055             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11056             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11057                 return -EINVAL;
11058
11059         /* No rx interrupts will be generated if both are zero */
11060         if ((ec->rx_coalesce_usecs == 0) &&
11061             (ec->rx_max_coalesced_frames == 0))
11062                 return -EINVAL;
11063
11064         /* No tx interrupts will be generated if both are zero */
11065         if ((ec->tx_coalesce_usecs == 0) &&
11066             (ec->tx_max_coalesced_frames == 0))
11067                 return -EINVAL;
11068
11069         /* Only copy relevant parameters, ignore all others. */
11070         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11071         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11072         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11073         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11074         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11075         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11076         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11077         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11078         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11079
11080         if (netif_running(dev)) {
11081                 tg3_full_lock(tp, 0);
11082                 __tg3_set_coalesce(tp, &tp->coal);
11083                 tg3_full_unlock(tp);
11084         }
11085         return 0;
11086 }
11087
11088 static const struct ethtool_ops tg3_ethtool_ops = {
11089         .get_settings           = tg3_get_settings,
11090         .set_settings           = tg3_set_settings,
11091         .get_drvinfo            = tg3_get_drvinfo,
11092         .get_regs_len           = tg3_get_regs_len,
11093         .get_regs               = tg3_get_regs,
11094         .get_wol                = tg3_get_wol,
11095         .set_wol                = tg3_set_wol,
11096         .get_msglevel           = tg3_get_msglevel,
11097         .set_msglevel           = tg3_set_msglevel,
11098         .nway_reset             = tg3_nway_reset,
11099         .get_link               = ethtool_op_get_link,
11100         .get_eeprom_len         = tg3_get_eeprom_len,
11101         .get_eeprom             = tg3_get_eeprom,
11102         .set_eeprom             = tg3_set_eeprom,
11103         .get_ringparam          = tg3_get_ringparam,
11104         .set_ringparam          = tg3_set_ringparam,
11105         .get_pauseparam         = tg3_get_pauseparam,
11106         .set_pauseparam         = tg3_set_pauseparam,
11107         .get_rx_csum            = tg3_get_rx_csum,
11108         .set_rx_csum            = tg3_set_rx_csum,
11109         .set_tx_csum            = tg3_set_tx_csum,
11110         .set_sg                 = ethtool_op_set_sg,
11111         .set_tso                = tg3_set_tso,
11112         .self_test              = tg3_self_test,
11113         .get_strings            = tg3_get_strings,
11114         .phys_id                = tg3_phys_id,
11115         .get_ethtool_stats      = tg3_get_ethtool_stats,
11116         .get_coalesce           = tg3_get_coalesce,
11117         .set_coalesce           = tg3_set_coalesce,
11118         .get_sset_count         = tg3_get_sset_count,
11119 };
11120
11121 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11122 {
11123         u32 cursize, val, magic;
11124
11125         tp->nvram_size = EEPROM_CHIP_SIZE;
11126
11127         if (tg3_nvram_read(tp, 0, &magic) != 0)
11128                 return;
11129
11130         if ((magic != TG3_EEPROM_MAGIC) &&
11131             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11132             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11133                 return;
11134
11135         /*
11136          * Size the chip by reading offsets at increasing powers of two.
11137          * When we encounter our validation signature, we know the addressing
11138          * has wrapped around, and thus have our chip size.
11139          */
11140         cursize = 0x10;
11141
11142         while (cursize < tp->nvram_size) {
11143                 if (tg3_nvram_read(tp, cursize, &val) != 0)
11144                         return;
11145
11146                 if (val == magic)
11147                         break;
11148
11149                 cursize <<= 1;
11150         }
11151
11152         tp->nvram_size = cursize;
11153 }
11154
11155 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11156 {
11157         u32 val;
11158
11159         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11160             tg3_nvram_read(tp, 0, &val) != 0)
11161                 return;
11162
11163         /* Selfboot format */
11164         if (val != TG3_EEPROM_MAGIC) {
11165                 tg3_get_eeprom_size(tp);
11166                 return;
11167         }
11168
11169         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11170                 if (val != 0) {
11171                         /* This is confusing.  We want to operate on the
11172                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
11173                          * call will read from NVRAM and byteswap the data
11174                          * according to the byteswapping settings for all
11175                          * other register accesses.  This ensures the data we
11176                          * want will always reside in the lower 16-bits.
11177                          * However, the data in NVRAM is in LE format, which
11178                          * means the data from the NVRAM read will always be
11179                          * opposite the endianness of the CPU.  The 16-bit
11180                          * byteswap then brings the data to CPU endianness.
11181                          */
11182                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11183                         return;
11184                 }
11185         }
11186         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11187 }
11188
11189 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11190 {
11191         u32 nvcfg1;
11192
11193         nvcfg1 = tr32(NVRAM_CFG1);
11194         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11195                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11196         } else {
11197                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11198                 tw32(NVRAM_CFG1, nvcfg1);
11199         }
11200
11201         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11202             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11203                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11204                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11205                         tp->nvram_jedecnum = JEDEC_ATMEL;
11206                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11207                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11208                         break;
11209                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11210                         tp->nvram_jedecnum = JEDEC_ATMEL;
11211                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11212                         break;
11213                 case FLASH_VENDOR_ATMEL_EEPROM:
11214                         tp->nvram_jedecnum = JEDEC_ATMEL;
11215                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11216                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11217                         break;
11218                 case FLASH_VENDOR_ST:
11219                         tp->nvram_jedecnum = JEDEC_ST;
11220                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11221                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11222                         break;
11223                 case FLASH_VENDOR_SAIFUN:
11224                         tp->nvram_jedecnum = JEDEC_SAIFUN;
11225                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11226                         break;
11227                 case FLASH_VENDOR_SST_SMALL:
11228                 case FLASH_VENDOR_SST_LARGE:
11229                         tp->nvram_jedecnum = JEDEC_SST;
11230                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11231                         break;
11232                 }
11233         } else {
11234                 tp->nvram_jedecnum = JEDEC_ATMEL;
11235                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11236                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11237         }
11238 }
11239
11240 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11241 {
11242         switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11243         case FLASH_5752PAGE_SIZE_256:
11244                 tp->nvram_pagesize = 256;
11245                 break;
11246         case FLASH_5752PAGE_SIZE_512:
11247                 tp->nvram_pagesize = 512;
11248                 break;
11249         case FLASH_5752PAGE_SIZE_1K:
11250                 tp->nvram_pagesize = 1024;
11251                 break;
11252         case FLASH_5752PAGE_SIZE_2K:
11253                 tp->nvram_pagesize = 2048;
11254                 break;
11255         case FLASH_5752PAGE_SIZE_4K:
11256                 tp->nvram_pagesize = 4096;
11257                 break;
11258         case FLASH_5752PAGE_SIZE_264:
11259                 tp->nvram_pagesize = 264;
11260                 break;
11261         case FLASH_5752PAGE_SIZE_528:
11262                 tp->nvram_pagesize = 528;
11263                 break;
11264         }
11265 }
11266
11267 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11268 {
11269         u32 nvcfg1;
11270
11271         nvcfg1 = tr32(NVRAM_CFG1);
11272
11273         /* NVRAM protection for TPM */
11274         if (nvcfg1 & (1 << 27))
11275                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11276
11277         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11278         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11279         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11280                 tp->nvram_jedecnum = JEDEC_ATMEL;
11281                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11282                 break;
11283         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11284                 tp->nvram_jedecnum = JEDEC_ATMEL;
11285                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11286                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11287                 break;
11288         case FLASH_5752VENDOR_ST_M45PE10:
11289         case FLASH_5752VENDOR_ST_M45PE20:
11290         case FLASH_5752VENDOR_ST_M45PE40:
11291                 tp->nvram_jedecnum = JEDEC_ST;
11292                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11293                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11294                 break;
11295         }
11296
11297         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11298                 tg3_nvram_get_pagesize(tp, nvcfg1);
11299         } else {
11300                 /* For eeprom, set pagesize to maximum eeprom size */
11301                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11302
11303                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11304                 tw32(NVRAM_CFG1, nvcfg1);
11305         }
11306 }
11307
11308 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11309 {
11310         u32 nvcfg1, protect = 0;
11311
11312         nvcfg1 = tr32(NVRAM_CFG1);
11313
11314         /* NVRAM protection for TPM */
11315         if (nvcfg1 & (1 << 27)) {
11316                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11317                 protect = 1;
11318         }
11319
11320         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11321         switch (nvcfg1) {
11322         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11323         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11324         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11325         case FLASH_5755VENDOR_ATMEL_FLASH_5:
11326                 tp->nvram_jedecnum = JEDEC_ATMEL;
11327                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11328                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11329                 tp->nvram_pagesize = 264;
11330                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11331                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11332                         tp->nvram_size = (protect ? 0x3e200 :
11333                                           TG3_NVRAM_SIZE_512KB);
11334                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11335                         tp->nvram_size = (protect ? 0x1f200 :
11336                                           TG3_NVRAM_SIZE_256KB);
11337                 else
11338                         tp->nvram_size = (protect ? 0x1f200 :
11339                                           TG3_NVRAM_SIZE_128KB);
11340                 break;
11341         case FLASH_5752VENDOR_ST_M45PE10:
11342         case FLASH_5752VENDOR_ST_M45PE20:
11343         case FLASH_5752VENDOR_ST_M45PE40:
11344                 tp->nvram_jedecnum = JEDEC_ST;
11345                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11346                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11347                 tp->nvram_pagesize = 256;
11348                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11349                         tp->nvram_size = (protect ?
11350                                           TG3_NVRAM_SIZE_64KB :
11351                                           TG3_NVRAM_SIZE_128KB);
11352                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11353                         tp->nvram_size = (protect ?
11354                                           TG3_NVRAM_SIZE_64KB :
11355                                           TG3_NVRAM_SIZE_256KB);
11356                 else
11357                         tp->nvram_size = (protect ?
11358                                           TG3_NVRAM_SIZE_128KB :
11359                                           TG3_NVRAM_SIZE_512KB);
11360                 break;
11361         }
11362 }
11363
11364 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11365 {
11366         u32 nvcfg1;
11367
11368         nvcfg1 = tr32(NVRAM_CFG1);
11369
11370         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11371         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11372         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11373         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11374         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11375                 tp->nvram_jedecnum = JEDEC_ATMEL;
11376                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11377                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11378
11379                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11380                 tw32(NVRAM_CFG1, nvcfg1);
11381                 break;
11382         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11383         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11384         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11385         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11386                 tp->nvram_jedecnum = JEDEC_ATMEL;
11387                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11388                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11389                 tp->nvram_pagesize = 264;
11390                 break;
11391         case FLASH_5752VENDOR_ST_M45PE10:
11392         case FLASH_5752VENDOR_ST_M45PE20:
11393         case FLASH_5752VENDOR_ST_M45PE40:
11394                 tp->nvram_jedecnum = JEDEC_ST;
11395                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11396                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11397                 tp->nvram_pagesize = 256;
11398                 break;
11399         }
11400 }
11401
11402 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11403 {
11404         u32 nvcfg1, protect = 0;
11405
11406         nvcfg1 = tr32(NVRAM_CFG1);
11407
11408         /* NVRAM protection for TPM */
11409         if (nvcfg1 & (1 << 27)) {
11410                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11411                 protect = 1;
11412         }
11413
11414         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11415         switch (nvcfg1) {
11416         case FLASH_5761VENDOR_ATMEL_ADB021D:
11417         case FLASH_5761VENDOR_ATMEL_ADB041D:
11418         case FLASH_5761VENDOR_ATMEL_ADB081D:
11419         case FLASH_5761VENDOR_ATMEL_ADB161D:
11420         case FLASH_5761VENDOR_ATMEL_MDB021D:
11421         case FLASH_5761VENDOR_ATMEL_MDB041D:
11422         case FLASH_5761VENDOR_ATMEL_MDB081D:
11423         case FLASH_5761VENDOR_ATMEL_MDB161D:
11424                 tp->nvram_jedecnum = JEDEC_ATMEL;
11425                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11426                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11427                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11428                 tp->nvram_pagesize = 256;
11429                 break;
11430         case FLASH_5761VENDOR_ST_A_M45PE20:
11431         case FLASH_5761VENDOR_ST_A_M45PE40:
11432         case FLASH_5761VENDOR_ST_A_M45PE80:
11433         case FLASH_5761VENDOR_ST_A_M45PE16:
11434         case FLASH_5761VENDOR_ST_M_M45PE20:
11435         case FLASH_5761VENDOR_ST_M_M45PE40:
11436         case FLASH_5761VENDOR_ST_M_M45PE80:
11437         case FLASH_5761VENDOR_ST_M_M45PE16:
11438                 tp->nvram_jedecnum = JEDEC_ST;
11439                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11440                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11441                 tp->nvram_pagesize = 256;
11442                 break;
11443         }
11444
11445         if (protect) {
11446                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11447         } else {
11448                 switch (nvcfg1) {
11449                 case FLASH_5761VENDOR_ATMEL_ADB161D:
11450                 case FLASH_5761VENDOR_ATMEL_MDB161D:
11451                 case FLASH_5761VENDOR_ST_A_M45PE16:
11452                 case FLASH_5761VENDOR_ST_M_M45PE16:
11453                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11454                         break;
11455                 case FLASH_5761VENDOR_ATMEL_ADB081D:
11456                 case FLASH_5761VENDOR_ATMEL_MDB081D:
11457                 case FLASH_5761VENDOR_ST_A_M45PE80:
11458                 case FLASH_5761VENDOR_ST_M_M45PE80:
11459                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11460                         break;
11461                 case FLASH_5761VENDOR_ATMEL_ADB041D:
11462                 case FLASH_5761VENDOR_ATMEL_MDB041D:
11463                 case FLASH_5761VENDOR_ST_A_M45PE40:
11464                 case FLASH_5761VENDOR_ST_M_M45PE40:
11465                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11466                         break;
11467                 case FLASH_5761VENDOR_ATMEL_ADB021D:
11468                 case FLASH_5761VENDOR_ATMEL_MDB021D:
11469                 case FLASH_5761VENDOR_ST_A_M45PE20:
11470                 case FLASH_5761VENDOR_ST_M_M45PE20:
11471                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11472                         break;
11473                 }
11474         }
11475 }
11476
11477 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11478 {
11479         tp->nvram_jedecnum = JEDEC_ATMEL;
11480         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11481         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11482 }
11483
11484 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11485 {
11486         u32 nvcfg1;
11487
11488         nvcfg1 = tr32(NVRAM_CFG1);
11489
11490         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11491         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11492         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11493                 tp->nvram_jedecnum = JEDEC_ATMEL;
11494                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11495                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11496
11497                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11498                 tw32(NVRAM_CFG1, nvcfg1);
11499                 return;
11500         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11501         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11502         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11503         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11504         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11505         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11506         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11507                 tp->nvram_jedecnum = JEDEC_ATMEL;
11508                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11509                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11510
11511                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11512                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11513                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11514                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11515                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11516                         break;
11517                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11518                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11519                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11520                         break;
11521                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11522                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11523                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11524                         break;
11525                 }
11526                 break;
11527         case FLASH_5752VENDOR_ST_M45PE10:
11528         case FLASH_5752VENDOR_ST_M45PE20:
11529         case FLASH_5752VENDOR_ST_M45PE40:
11530                 tp->nvram_jedecnum = JEDEC_ST;
11531                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11532                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11533
11534                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11535                 case FLASH_5752VENDOR_ST_M45PE10:
11536                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11537                         break;
11538                 case FLASH_5752VENDOR_ST_M45PE20:
11539                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11540                         break;
11541                 case FLASH_5752VENDOR_ST_M45PE40:
11542                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11543                         break;
11544                 }
11545                 break;
11546         default:
11547                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11548                 return;
11549         }
11550
11551         tg3_nvram_get_pagesize(tp, nvcfg1);
11552         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11553                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11554 }
11555
11556
11557 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11558 {
11559         u32 nvcfg1;
11560
11561         nvcfg1 = tr32(NVRAM_CFG1);
11562
11563         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11564         case FLASH_5717VENDOR_ATMEL_EEPROM:
11565         case FLASH_5717VENDOR_MICRO_EEPROM:
11566                 tp->nvram_jedecnum = JEDEC_ATMEL;
11567                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11568                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11569
11570                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11571                 tw32(NVRAM_CFG1, nvcfg1);
11572                 return;
11573         case FLASH_5717VENDOR_ATMEL_MDB011D:
11574         case FLASH_5717VENDOR_ATMEL_ADB011B:
11575         case FLASH_5717VENDOR_ATMEL_ADB011D:
11576         case FLASH_5717VENDOR_ATMEL_MDB021D:
11577         case FLASH_5717VENDOR_ATMEL_ADB021B:
11578         case FLASH_5717VENDOR_ATMEL_ADB021D:
11579         case FLASH_5717VENDOR_ATMEL_45USPT:
11580                 tp->nvram_jedecnum = JEDEC_ATMEL;
11581                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11582                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11583
11584                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11585                 case FLASH_5717VENDOR_ATMEL_MDB021D:
11586                 case FLASH_5717VENDOR_ATMEL_ADB021B:
11587                 case FLASH_5717VENDOR_ATMEL_ADB021D:
11588                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11589                         break;
11590                 default:
11591                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11592                         break;
11593                 }
11594                 break;
11595         case FLASH_5717VENDOR_ST_M_M25PE10:
11596         case FLASH_5717VENDOR_ST_A_M25PE10:
11597         case FLASH_5717VENDOR_ST_M_M45PE10:
11598         case FLASH_5717VENDOR_ST_A_M45PE10:
11599         case FLASH_5717VENDOR_ST_M_M25PE20:
11600         case FLASH_5717VENDOR_ST_A_M25PE20:
11601         case FLASH_5717VENDOR_ST_M_M45PE20:
11602         case FLASH_5717VENDOR_ST_A_M45PE20:
11603         case FLASH_5717VENDOR_ST_25USPT:
11604         case FLASH_5717VENDOR_ST_45USPT:
11605                 tp->nvram_jedecnum = JEDEC_ST;
11606                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11607                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11608
11609                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11610                 case FLASH_5717VENDOR_ST_M_M25PE20:
11611                 case FLASH_5717VENDOR_ST_A_M25PE20:
11612                 case FLASH_5717VENDOR_ST_M_M45PE20:
11613                 case FLASH_5717VENDOR_ST_A_M45PE20:
11614                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11615                         break;
11616                 default:
11617                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11618                         break;
11619                 }
11620                 break;
11621         default:
11622                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11623                 return;
11624         }
11625
11626         tg3_nvram_get_pagesize(tp, nvcfg1);
11627         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11628                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11629 }
11630
11631 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11632 static void __devinit tg3_nvram_init(struct tg3 *tp)
11633 {
11634         tw32_f(GRC_EEPROM_ADDR,
11635              (EEPROM_ADDR_FSM_RESET |
11636               (EEPROM_DEFAULT_CLOCK_PERIOD <<
11637                EEPROM_ADDR_CLKPERD_SHIFT)));
11638
11639         msleep(1);
11640
11641         /* Enable seeprom accesses. */
11642         tw32_f(GRC_LOCAL_CTRL,
11643              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11644         udelay(100);
11645
11646         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11647             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11648                 tp->tg3_flags |= TG3_FLAG_NVRAM;
11649
11650                 if (tg3_nvram_lock(tp)) {
11651                         netdev_warn(tp->dev,
11652                                     "Cannot get nvram lock, %s failed\n",
11653                                     __func__);
11654                         return;
11655                 }
11656                 tg3_enable_nvram_access(tp);
11657
11658                 tp->nvram_size = 0;
11659
11660                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11661                         tg3_get_5752_nvram_info(tp);
11662                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11663                         tg3_get_5755_nvram_info(tp);
11664                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11665                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11666                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11667                         tg3_get_5787_nvram_info(tp);
11668                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11669                         tg3_get_5761_nvram_info(tp);
11670                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11671                         tg3_get_5906_nvram_info(tp);
11672                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11673                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11674                         tg3_get_57780_nvram_info(tp);
11675                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
11676                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
11677                         tg3_get_5717_nvram_info(tp);
11678                 else
11679                         tg3_get_nvram_info(tp);
11680
11681                 if (tp->nvram_size == 0)
11682                         tg3_get_nvram_size(tp);
11683
11684                 tg3_disable_nvram_access(tp);
11685                 tg3_nvram_unlock(tp);
11686
11687         } else {
11688                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11689
11690                 tg3_get_eeprom_size(tp);
11691         }
11692 }
11693
11694 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11695                                     u32 offset, u32 len, u8 *buf)
11696 {
11697         int i, j, rc = 0;
11698         u32 val;
11699
11700         for (i = 0; i < len; i += 4) {
11701                 u32 addr;
11702                 __be32 data;
11703
11704                 addr = offset + i;
11705
11706                 memcpy(&data, buf + i, 4);
11707
11708                 /*
11709                  * The SEEPROM interface expects the data to always be opposite
11710                  * the native endian format.  We accomplish this by reversing
11711                  * all the operations that would have been performed on the
11712                  * data from a call to tg3_nvram_read_be32().
11713                  */
11714                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11715
11716                 val = tr32(GRC_EEPROM_ADDR);
11717                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11718
11719                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11720                         EEPROM_ADDR_READ);
11721                 tw32(GRC_EEPROM_ADDR, val |
11722                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
11723                         (addr & EEPROM_ADDR_ADDR_MASK) |
11724                         EEPROM_ADDR_START |
11725                         EEPROM_ADDR_WRITE);
11726
11727                 for (j = 0; j < 1000; j++) {
11728                         val = tr32(GRC_EEPROM_ADDR);
11729
11730                         if (val & EEPROM_ADDR_COMPLETE)
11731                                 break;
11732                         msleep(1);
11733                 }
11734                 if (!(val & EEPROM_ADDR_COMPLETE)) {
11735                         rc = -EBUSY;
11736                         break;
11737                 }
11738         }
11739
11740         return rc;
11741 }
11742
11743 /* offset and length are dword aligned */
11744 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11745                 u8 *buf)
11746 {
11747         int ret = 0;
11748         u32 pagesize = tp->nvram_pagesize;
11749         u32 pagemask = pagesize - 1;
11750         u32 nvram_cmd;
11751         u8 *tmp;
11752
11753         tmp = kmalloc(pagesize, GFP_KERNEL);
11754         if (tmp == NULL)
11755                 return -ENOMEM;
11756
11757         while (len) {
11758                 int j;
11759                 u32 phy_addr, page_off, size;
11760
11761                 phy_addr = offset & ~pagemask;
11762
11763                 for (j = 0; j < pagesize; j += 4) {
11764                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
11765                                                   (__be32 *) (tmp + j));
11766                         if (ret)
11767                                 break;
11768                 }
11769                 if (ret)
11770                         break;
11771
11772                 page_off = offset & pagemask;
11773                 size = pagesize;
11774                 if (len < size)
11775                         size = len;
11776
11777                 len -= size;
11778
11779                 memcpy(tmp + page_off, buf, size);
11780
11781                 offset = offset + (pagesize - page_off);
11782
11783                 tg3_enable_nvram_access(tp);
11784
11785                 /*
11786                  * Before we can erase the flash page, we need
11787                  * to issue a special "write enable" command.
11788                  */
11789                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11790
11791                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11792                         break;
11793
11794                 /* Erase the target page */
11795                 tw32(NVRAM_ADDR, phy_addr);
11796
11797                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11798                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11799
11800                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11801                         break;
11802
11803                 /* Issue another write enable to start the write. */
11804                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11805
11806                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11807                         break;
11808
11809                 for (j = 0; j < pagesize; j += 4) {
11810                         __be32 data;
11811
11812                         data = *((__be32 *) (tmp + j));
11813
11814                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
11815
11816                         tw32(NVRAM_ADDR, phy_addr + j);
11817
11818                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11819                                 NVRAM_CMD_WR;
11820
11821                         if (j == 0)
11822                                 nvram_cmd |= NVRAM_CMD_FIRST;
11823                         else if (j == (pagesize - 4))
11824                                 nvram_cmd |= NVRAM_CMD_LAST;
11825
11826                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11827                                 break;
11828                 }
11829                 if (ret)
11830                         break;
11831         }
11832
11833         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11834         tg3_nvram_exec_cmd(tp, nvram_cmd);
11835
11836         kfree(tmp);
11837
11838         return ret;
11839 }
11840
11841 /* offset and length are dword aligned */
11842 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11843                 u8 *buf)
11844 {
11845         int i, ret = 0;
11846
11847         for (i = 0; i < len; i += 4, offset += 4) {
11848                 u32 page_off, phy_addr, nvram_cmd;
11849                 __be32 data;
11850
11851                 memcpy(&data, buf + i, 4);
11852                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11853
11854                 page_off = offset % tp->nvram_pagesize;
11855
11856                 phy_addr = tg3_nvram_phys_addr(tp, offset);
11857
11858                 tw32(NVRAM_ADDR, phy_addr);
11859
11860                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11861
11862                 if (page_off == 0 || i == 0)
11863                         nvram_cmd |= NVRAM_CMD_FIRST;
11864                 if (page_off == (tp->nvram_pagesize - 4))
11865                         nvram_cmd |= NVRAM_CMD_LAST;
11866
11867                 if (i == (len - 4))
11868                         nvram_cmd |= NVRAM_CMD_LAST;
11869
11870                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11871                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11872                     (tp->nvram_jedecnum == JEDEC_ST) &&
11873                     (nvram_cmd & NVRAM_CMD_FIRST)) {
11874
11875                         if ((ret = tg3_nvram_exec_cmd(tp,
11876                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11877                                 NVRAM_CMD_DONE)))
11878
11879                                 break;
11880                 }
11881                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11882                         /* We always do complete word writes to eeprom. */
11883                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11884                 }
11885
11886                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11887                         break;
11888         }
11889         return ret;
11890 }
11891
11892 /* offset and length are dword aligned */
11893 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11894 {
11895         int ret;
11896
11897         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11898                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11899                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
11900                 udelay(40);
11901         }
11902
11903         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11904                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11905         } else {
11906                 u32 grc_mode;
11907
11908                 ret = tg3_nvram_lock(tp);
11909                 if (ret)
11910                         return ret;
11911
11912                 tg3_enable_nvram_access(tp);
11913                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11914                     !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
11915                         tw32(NVRAM_WRITE1, 0x406);
11916
11917                 grc_mode = tr32(GRC_MODE);
11918                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11919
11920                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11921                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11922
11923                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
11924                                 buf);
11925                 } else {
11926                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11927                                 buf);
11928                 }
11929
11930                 grc_mode = tr32(GRC_MODE);
11931                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11932
11933                 tg3_disable_nvram_access(tp);
11934                 tg3_nvram_unlock(tp);
11935         }
11936
11937         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11938                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11939                 udelay(40);
11940         }
11941
11942         return ret;
11943 }
11944
11945 struct subsys_tbl_ent {
11946         u16 subsys_vendor, subsys_devid;
11947         u32 phy_id;
11948 };
11949
11950 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
11951         /* Broadcom boards. */
11952         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11953           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
11954         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11955           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
11956         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11957           TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
11958         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11959           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
11960         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11961           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
11962         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11963           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
11964         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11965           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
11966         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11967           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
11968         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11969           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
11970         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11971           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
11972         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11973           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
11974
11975         /* 3com boards. */
11976         { TG3PCI_SUBVENDOR_ID_3COM,
11977           TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
11978         { TG3PCI_SUBVENDOR_ID_3COM,
11979           TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
11980         { TG3PCI_SUBVENDOR_ID_3COM,
11981           TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
11982         { TG3PCI_SUBVENDOR_ID_3COM,
11983           TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
11984         { TG3PCI_SUBVENDOR_ID_3COM,
11985           TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
11986
11987         /* DELL boards. */
11988         { TG3PCI_SUBVENDOR_ID_DELL,
11989           TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
11990         { TG3PCI_SUBVENDOR_ID_DELL,
11991           TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
11992         { TG3PCI_SUBVENDOR_ID_DELL,
11993           TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
11994         { TG3PCI_SUBVENDOR_ID_DELL,
11995           TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
11996
11997         /* Compaq boards. */
11998         { TG3PCI_SUBVENDOR_ID_COMPAQ,
11999           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
12000         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12001           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
12002         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12003           TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
12004         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12005           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
12006         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12007           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
12008
12009         /* IBM boards. */
12010         { TG3PCI_SUBVENDOR_ID_IBM,
12011           TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
12012 };
12013
12014 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
12015 {
12016         int i;
12017
12018         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12019                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12020                      tp->pdev->subsystem_vendor) &&
12021                     (subsys_id_to_phy_id[i].subsys_devid ==
12022                      tp->pdev->subsystem_device))
12023                         return &subsys_id_to_phy_id[i];
12024         }
12025         return NULL;
12026 }
12027
12028 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12029 {
12030         u32 val;
12031         u16 pmcsr;
12032
12033         /* On some early chips the SRAM cannot be accessed in D3hot state,
12034          * so need make sure we're in D0.
12035          */
12036         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12037         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12038         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12039         msleep(1);
12040
12041         /* Make sure register accesses (indirect or otherwise)
12042          * will function correctly.
12043          */
12044         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12045                                tp->misc_host_ctrl);
12046
12047         /* The memory arbiter has to be enabled in order for SRAM accesses
12048          * to succeed.  Normally on powerup the tg3 chip firmware will make
12049          * sure it is enabled, but other entities such as system netboot
12050          * code might disable it.
12051          */
12052         val = tr32(MEMARB_MODE);
12053         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12054
12055         tp->phy_id = TG3_PHY_ID_INVALID;
12056         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12057
12058         /* Assume an onboard device and WOL capable by default.  */
12059         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12060
12061         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12062                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12063                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12064                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12065                 }
12066                 val = tr32(VCPU_CFGSHDW);
12067                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12068                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12069                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12070                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
12071                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12072                 goto done;
12073         }
12074
12075         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12076         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12077                 u32 nic_cfg, led_cfg;
12078                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12079                 int eeprom_phy_serdes = 0;
12080
12081                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12082                 tp->nic_sram_data_cfg = nic_cfg;
12083
12084                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12085                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12086                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12087                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12088                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12089                     (ver > 0) && (ver < 0x100))
12090                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12091
12092                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12093                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12094
12095                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12096                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12097                         eeprom_phy_serdes = 1;
12098
12099                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12100                 if (nic_phy_id != 0) {
12101                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12102                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12103
12104                         eeprom_phy_id  = (id1 >> 16) << 10;
12105                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
12106                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
12107                 } else
12108                         eeprom_phy_id = 0;
12109
12110                 tp->phy_id = eeprom_phy_id;
12111                 if (eeprom_phy_serdes) {
12112                         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12113                                 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12114                         else
12115                                 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
12116                 }
12117
12118                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12119                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12120                                     SHASTA_EXT_LED_MODE_MASK);
12121                 else
12122                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12123
12124                 switch (led_cfg) {
12125                 default:
12126                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12127                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12128                         break;
12129
12130                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12131                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12132                         break;
12133
12134                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12135                         tp->led_ctrl = LED_CTRL_MODE_MAC;
12136
12137                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12138                          * read on some older 5700/5701 bootcode.
12139                          */
12140                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12141                             ASIC_REV_5700 ||
12142                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
12143                             ASIC_REV_5701)
12144                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12145
12146                         break;
12147
12148                 case SHASTA_EXT_LED_SHARED:
12149                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
12150                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12151                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12152                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12153                                                  LED_CTRL_MODE_PHY_2);
12154                         break;
12155
12156                 case SHASTA_EXT_LED_MAC:
12157                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12158                         break;
12159
12160                 case SHASTA_EXT_LED_COMBO:
12161                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
12162                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12163                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12164                                                  LED_CTRL_MODE_PHY_2);
12165                         break;
12166
12167                 }
12168
12169                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12170                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12171                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12172                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12173
12174                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12175                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12176
12177                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12178                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12179                         if ((tp->pdev->subsystem_vendor ==
12180                              PCI_VENDOR_ID_ARIMA) &&
12181                             (tp->pdev->subsystem_device == 0x205a ||
12182                              tp->pdev->subsystem_device == 0x2063))
12183                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12184                 } else {
12185                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12186                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12187                 }
12188
12189                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12190                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12191                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12192                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12193                 }
12194
12195                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12196                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12197                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12198
12199                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
12200                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12201                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12202
12203                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12204                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12205                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12206
12207                 if (cfg2 & (1 << 17))
12208                         tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
12209
12210                 /* serdes signal pre-emphasis in register 0x590 set by */
12211                 /* bootcode if bit 18 is set */
12212                 if (cfg2 & (1 << 18))
12213                         tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
12214
12215                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12216                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
12217                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12218                         tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
12219
12220                 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12221                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12222                     !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
12223                         u32 cfg3;
12224
12225                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12226                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12227                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12228                 }
12229
12230                 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12231                         tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
12232                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12233                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12234                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12235                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12236         }
12237 done:
12238         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12239         device_set_wakeup_enable(&tp->pdev->dev,
12240                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12241 }
12242
12243 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12244 {
12245         int i;
12246         u32 val;
12247
12248         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12249         tw32(OTP_CTRL, cmd);
12250
12251         /* Wait for up to 1 ms for command to execute. */
12252         for (i = 0; i < 100; i++) {
12253                 val = tr32(OTP_STATUS);
12254                 if (val & OTP_STATUS_CMD_DONE)
12255                         break;
12256                 udelay(10);
12257         }
12258
12259         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12260 }
12261
12262 /* Read the gphy configuration from the OTP region of the chip.  The gphy
12263  * configuration is a 32-bit value that straddles the alignment boundary.
12264  * We do two 32-bit reads and then shift and merge the results.
12265  */
12266 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12267 {
12268         u32 bhalf_otp, thalf_otp;
12269
12270         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12271
12272         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12273                 return 0;
12274
12275         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12276
12277         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12278                 return 0;
12279
12280         thalf_otp = tr32(OTP_READ_DATA);
12281
12282         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12283
12284         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12285                 return 0;
12286
12287         bhalf_otp = tr32(OTP_READ_DATA);
12288
12289         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12290 }
12291
12292 static int __devinit tg3_phy_probe(struct tg3 *tp)
12293 {
12294         u32 hw_phy_id_1, hw_phy_id_2;
12295         u32 hw_phy_id, hw_phy_id_masked;
12296         int err;
12297
12298         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12299                 return tg3_phy_init(tp);
12300
12301         /* Reading the PHY ID register can conflict with ASF
12302          * firmware access to the PHY hardware.
12303          */
12304         err = 0;
12305         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12306             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12307                 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
12308         } else {
12309                 /* Now read the physical PHY_ID from the chip and verify
12310                  * that it is sane.  If it doesn't look good, we fall back
12311                  * to either the hard-coded table based PHY_ID and failing
12312                  * that the value found in the eeprom area.
12313                  */
12314                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12315                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12316
12317                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
12318                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12319                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
12320
12321                 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
12322         }
12323
12324         if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
12325                 tp->phy_id = hw_phy_id;
12326                 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
12327                         tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12328                 else
12329                         tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
12330         } else {
12331                 if (tp->phy_id != TG3_PHY_ID_INVALID) {
12332                         /* Do nothing, phy ID already set up in
12333                          * tg3_get_eeprom_hw_cfg().
12334                          */
12335                 } else {
12336                         struct subsys_tbl_ent *p;
12337
12338                         /* No eeprom signature?  Try the hardcoded
12339                          * subsys device table.
12340                          */
12341                         p = tg3_lookup_by_subsys(tp);
12342                         if (!p)
12343                                 return -ENODEV;
12344
12345                         tp->phy_id = p->phy_id;
12346                         if (!tp->phy_id ||
12347                             tp->phy_id == TG3_PHY_ID_BCM8002)
12348                                 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12349                 }
12350         }
12351
12352         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
12353             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12354             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12355                 u32 bmsr, adv_reg, tg3_ctrl, mask;
12356
12357                 tg3_readphy(tp, MII_BMSR, &bmsr);
12358                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12359                     (bmsr & BMSR_LSTATUS))
12360                         goto skip_phy_reset;
12361
12362                 err = tg3_phy_reset(tp);
12363                 if (err)
12364                         return err;
12365
12366                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12367                            ADVERTISE_100HALF | ADVERTISE_100FULL |
12368                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12369                 tg3_ctrl = 0;
12370                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
12371                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12372                                     MII_TG3_CTRL_ADV_1000_FULL);
12373                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12374                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12375                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12376                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
12377                 }
12378
12379                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12380                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12381                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12382                 if (!tg3_copper_is_advertising_all(tp, mask)) {
12383                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12384
12385                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12386                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12387
12388                         tg3_writephy(tp, MII_BMCR,
12389                                      BMCR_ANENABLE | BMCR_ANRESTART);
12390                 }
12391                 tg3_phy_set_wirespeed(tp);
12392
12393                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12394                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12395                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12396         }
12397
12398 skip_phy_reset:
12399         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
12400                 err = tg3_init_5401phy_dsp(tp);
12401                 if (err)
12402                         return err;
12403
12404                 err = tg3_init_5401phy_dsp(tp);
12405         }
12406
12407         if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
12408                 tp->link_config.advertising =
12409                         (ADVERTISED_1000baseT_Half |
12410                          ADVERTISED_1000baseT_Full |
12411                          ADVERTISED_Autoneg |
12412                          ADVERTISED_FIBRE);
12413         if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
12414                 tp->link_config.advertising &=
12415                         ~(ADVERTISED_1000baseT_Half |
12416                           ADVERTISED_1000baseT_Full);
12417
12418         return err;
12419 }
12420
12421 static void __devinit tg3_read_vpd(struct tg3 *tp)
12422 {
12423         u8 vpd_data[TG3_NVM_VPD_LEN];
12424         unsigned int block_end, rosize, len;
12425         int j, i = 0;
12426         u32 magic;
12427
12428         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12429             tg3_nvram_read(tp, 0x0, &magic))
12430                 goto out_not_found;
12431
12432         if (magic == TG3_EEPROM_MAGIC) {
12433                 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12434                         u32 tmp;
12435
12436                         /* The data is in little-endian format in NVRAM.
12437                          * Use the big-endian read routines to preserve
12438                          * the byte order as it exists in NVRAM.
12439                          */
12440                         if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12441                                 goto out_not_found;
12442
12443                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12444                 }
12445         } else {
12446                 ssize_t cnt;
12447                 unsigned int pos = 0;
12448
12449                 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12450                         cnt = pci_read_vpd(tp->pdev, pos,
12451                                            TG3_NVM_VPD_LEN - pos,
12452                                            &vpd_data[pos]);
12453                         if (cnt == -ETIMEDOUT || -EINTR)
12454                                 cnt = 0;
12455                         else if (cnt < 0)
12456                                 goto out_not_found;
12457                 }
12458                 if (pos != TG3_NVM_VPD_LEN)
12459                         goto out_not_found;
12460         }
12461
12462         i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
12463                              PCI_VPD_LRDT_RO_DATA);
12464         if (i < 0)
12465                 goto out_not_found;
12466
12467         rosize = pci_vpd_lrdt_size(&vpd_data[i]);
12468         block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
12469         i += PCI_VPD_LRDT_TAG_SIZE;
12470
12471         if (block_end > TG3_NVM_VPD_LEN)
12472                 goto out_not_found;
12473
12474         j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12475                                       PCI_VPD_RO_KEYWORD_MFR_ID);
12476         if (j > 0) {
12477                 len = pci_vpd_info_field_size(&vpd_data[j]);
12478
12479                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12480                 if (j + len > block_end || len != 4 ||
12481                     memcmp(&vpd_data[j], "1028", 4))
12482                         goto partno;
12483
12484                 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12485                                               PCI_VPD_RO_KEYWORD_VENDOR0);
12486                 if (j < 0)
12487                         goto partno;
12488
12489                 len = pci_vpd_info_field_size(&vpd_data[j]);
12490
12491                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12492                 if (j + len > block_end)
12493                         goto partno;
12494
12495                 memcpy(tp->fw_ver, &vpd_data[j], len);
12496                 strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
12497         }
12498
12499 partno:
12500         i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12501                                       PCI_VPD_RO_KEYWORD_PARTNO);
12502         if (i < 0)
12503                 goto out_not_found;
12504
12505         len = pci_vpd_info_field_size(&vpd_data[i]);
12506
12507         i += PCI_VPD_INFO_FLD_HDR_SIZE;
12508         if (len > TG3_BPN_SIZE ||
12509             (len + i) > TG3_NVM_VPD_LEN)
12510                 goto out_not_found;
12511
12512         memcpy(tp->board_part_number, &vpd_data[i], len);
12513
12514         return;
12515
12516 out_not_found:
12517         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12518                 strcpy(tp->board_part_number, "BCM95906");
12519         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12520                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12521                 strcpy(tp->board_part_number, "BCM57780");
12522         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12523                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12524                 strcpy(tp->board_part_number, "BCM57760");
12525         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12526                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12527                 strcpy(tp->board_part_number, "BCM57790");
12528         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12529                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12530                 strcpy(tp->board_part_number, "BCM57788");
12531         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12532                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
12533                 strcpy(tp->board_part_number, "BCM57761");
12534         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12535                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
12536                 strcpy(tp->board_part_number, "BCM57765");
12537         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12538                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
12539                 strcpy(tp->board_part_number, "BCM57781");
12540         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12541                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
12542                 strcpy(tp->board_part_number, "BCM57785");
12543         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12544                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
12545                 strcpy(tp->board_part_number, "BCM57791");
12546         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12547                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12548                 strcpy(tp->board_part_number, "BCM57795");
12549         else
12550                 strcpy(tp->board_part_number, "none");
12551 }
12552
12553 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12554 {
12555         u32 val;
12556
12557         if (tg3_nvram_read(tp, offset, &val) ||
12558             (val & 0xfc000000) != 0x0c000000 ||
12559             tg3_nvram_read(tp, offset + 4, &val) ||
12560             val != 0)
12561                 return 0;
12562
12563         return 1;
12564 }
12565
12566 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12567 {
12568         u32 val, offset, start, ver_offset;
12569         int i, dst_off;
12570         bool newver = false;
12571
12572         if (tg3_nvram_read(tp, 0xc, &offset) ||
12573             tg3_nvram_read(tp, 0x4, &start))
12574                 return;
12575
12576         offset = tg3_nvram_logical_addr(tp, offset);
12577
12578         if (tg3_nvram_read(tp, offset, &val))
12579                 return;
12580
12581         if ((val & 0xfc000000) == 0x0c000000) {
12582                 if (tg3_nvram_read(tp, offset + 4, &val))
12583                         return;
12584
12585                 if (val == 0)
12586                         newver = true;
12587         }
12588
12589         dst_off = strlen(tp->fw_ver);
12590
12591         if (newver) {
12592                 if (TG3_VER_SIZE - dst_off < 16 ||
12593                     tg3_nvram_read(tp, offset + 8, &ver_offset))
12594                         return;
12595
12596                 offset = offset + ver_offset - start;
12597                 for (i = 0; i < 16; i += 4) {
12598                         __be32 v;
12599                         if (tg3_nvram_read_be32(tp, offset + i, &v))
12600                                 return;
12601
12602                         memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
12603                 }
12604         } else {
12605                 u32 major, minor;
12606
12607                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12608                         return;
12609
12610                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12611                         TG3_NVM_BCVER_MAJSFT;
12612                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12613                 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
12614                          "v%d.%02d", major, minor);
12615         }
12616 }
12617
12618 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12619 {
12620         u32 val, major, minor;
12621
12622         /* Use native endian representation */
12623         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12624                 return;
12625
12626         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12627                 TG3_NVM_HWSB_CFG1_MAJSFT;
12628         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12629                 TG3_NVM_HWSB_CFG1_MINSFT;
12630
12631         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12632 }
12633
12634 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12635 {
12636         u32 offset, major, minor, build;
12637
12638         strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
12639
12640         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12641                 return;
12642
12643         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12644         case TG3_EEPROM_SB_REVISION_0:
12645                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12646                 break;
12647         case TG3_EEPROM_SB_REVISION_2:
12648                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12649                 break;
12650         case TG3_EEPROM_SB_REVISION_3:
12651                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12652                 break;
12653         case TG3_EEPROM_SB_REVISION_4:
12654                 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
12655                 break;
12656         case TG3_EEPROM_SB_REVISION_5:
12657                 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
12658                 break;
12659         default:
12660                 return;
12661         }
12662
12663         if (tg3_nvram_read(tp, offset, &val))
12664                 return;
12665
12666         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12667                 TG3_EEPROM_SB_EDH_BLD_SHFT;
12668         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12669                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12670         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
12671
12672         if (minor > 99 || build > 26)
12673                 return;
12674
12675         offset = strlen(tp->fw_ver);
12676         snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
12677                  " v%d.%02d", major, minor);
12678
12679         if (build > 0) {
12680                 offset = strlen(tp->fw_ver);
12681                 if (offset < TG3_VER_SIZE - 1)
12682                         tp->fw_ver[offset] = 'a' + build - 1;
12683         }
12684 }
12685
12686 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12687 {
12688         u32 val, offset, start;
12689         int i, vlen;
12690
12691         for (offset = TG3_NVM_DIR_START;
12692              offset < TG3_NVM_DIR_END;
12693              offset += TG3_NVM_DIRENT_SIZE) {
12694                 if (tg3_nvram_read(tp, offset, &val))
12695                         return;
12696
12697                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12698                         break;
12699         }
12700
12701         if (offset == TG3_NVM_DIR_END)
12702                 return;
12703
12704         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12705                 start = 0x08000000;
12706         else if (tg3_nvram_read(tp, offset - 4, &start))
12707                 return;
12708
12709         if (tg3_nvram_read(tp, offset + 4, &offset) ||
12710             !tg3_fw_img_is_valid(tp, offset) ||
12711             tg3_nvram_read(tp, offset + 8, &val))
12712                 return;
12713
12714         offset += val - start;
12715
12716         vlen = strlen(tp->fw_ver);
12717
12718         tp->fw_ver[vlen++] = ',';
12719         tp->fw_ver[vlen++] = ' ';
12720
12721         for (i = 0; i < 4; i++) {
12722                 __be32 v;
12723                 if (tg3_nvram_read_be32(tp, offset, &v))
12724                         return;
12725
12726                 offset += sizeof(v);
12727
12728                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12729                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12730                         break;
12731                 }
12732
12733                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12734                 vlen += sizeof(v);
12735         }
12736 }
12737
12738 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12739 {
12740         int vlen;
12741         u32 apedata;
12742         char *fwtype;
12743
12744         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12745             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
12746                 return;
12747
12748         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12749         if (apedata != APE_SEG_SIG_MAGIC)
12750                 return;
12751
12752         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12753         if (!(apedata & APE_FW_STATUS_READY))
12754                 return;
12755
12756         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12757
12758         if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) {
12759                 tp->tg3_flags3 |= TG3_FLG3_APE_HAS_NCSI;
12760                 fwtype = "NCSI";
12761         } else {
12762                 fwtype = "DASH";
12763         }
12764
12765         vlen = strlen(tp->fw_ver);
12766
12767         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
12768                  fwtype,
12769                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12770                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12771                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12772                  (apedata & APE_FW_VERSION_BLDMSK));
12773 }
12774
12775 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12776 {
12777         u32 val;
12778         bool vpd_vers = false;
12779
12780         if (tp->fw_ver[0] != 0)
12781                 vpd_vers = true;
12782
12783         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12784                 strcat(tp->fw_ver, "sb");
12785                 return;
12786         }
12787
12788         if (tg3_nvram_read(tp, 0, &val))
12789                 return;
12790
12791         if (val == TG3_EEPROM_MAGIC)
12792                 tg3_read_bc_ver(tp);
12793         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12794                 tg3_read_sb_ver(tp, val);
12795         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12796                 tg3_read_hwsb_ver(tp);
12797         else
12798                 return;
12799
12800         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12801              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
12802                 goto done;
12803
12804         tg3_read_mgmtfw_ver(tp);
12805
12806 done:
12807         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12808 }
12809
12810 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12811
12812 static void inline vlan_features_add(struct net_device *dev, unsigned long flags)
12813 {
12814 #if TG3_VLAN_TAG_USED
12815         dev->vlan_features |= flags;
12816 #endif
12817 }
12818
12819 static int __devinit tg3_get_invariants(struct tg3 *tp)
12820 {
12821         static struct pci_device_id write_reorder_chipsets[] = {
12822                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12823                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12824                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12825                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12826                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12827                              PCI_DEVICE_ID_VIA_8385_0) },
12828                 { },
12829         };
12830         u32 misc_ctrl_reg;
12831         u32 pci_state_reg, grc_misc_cfg;
12832         u32 val;
12833         u16 pci_cmd;
12834         int err;
12835
12836         /* Force memory write invalidate off.  If we leave it on,
12837          * then on 5700_BX chips we have to enable a workaround.
12838          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12839          * to match the cacheline size.  The Broadcom driver have this
12840          * workaround but turns MWI off all the times so never uses
12841          * it.  This seems to suggest that the workaround is insufficient.
12842          */
12843         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12844         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12845         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12846
12847         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12848          * has the register indirect write enable bit set before
12849          * we try to access any of the MMIO registers.  It is also
12850          * critical that the PCI-X hw workaround situation is decided
12851          * before that as well.
12852          */
12853         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12854                               &misc_ctrl_reg);
12855
12856         tp->pci_chip_rev_id = (misc_ctrl_reg >>
12857                                MISC_HOST_CTRL_CHIPREV_SHIFT);
12858         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12859                 u32 prod_id_asic_rev;
12860
12861                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12862                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12863                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724 ||
12864                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719)
12865                         pci_read_config_dword(tp->pdev,
12866                                               TG3PCI_GEN2_PRODID_ASICREV,
12867                                               &prod_id_asic_rev);
12868                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
12869                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
12870                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
12871                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
12872                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
12873                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12874                         pci_read_config_dword(tp->pdev,
12875                                               TG3PCI_GEN15_PRODID_ASICREV,
12876                                               &prod_id_asic_rev);
12877                 else
12878                         pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12879                                               &prod_id_asic_rev);
12880
12881                 tp->pci_chip_rev_id = prod_id_asic_rev;
12882         }
12883
12884         /* Wrong chip ID in 5752 A0. This code can be removed later
12885          * as A0 is not in production.
12886          */
12887         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12888                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12889
12890         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12891          * we need to disable memory and use config. cycles
12892          * only to access all registers. The 5702/03 chips
12893          * can mistakenly decode the special cycles from the
12894          * ICH chipsets as memory write cycles, causing corruption
12895          * of register and memory space. Only certain ICH bridges
12896          * will drive special cycles with non-zero data during the
12897          * address phase which can fall within the 5703's address
12898          * range. This is not an ICH bug as the PCI spec allows
12899          * non-zero address during special cycles. However, only
12900          * these ICH bridges are known to drive non-zero addresses
12901          * during special cycles.
12902          *
12903          * Since special cycles do not cross PCI bridges, we only
12904          * enable this workaround if the 5703 is on the secondary
12905          * bus of these ICH bridges.
12906          */
12907         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12908             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12909                 static struct tg3_dev_id {
12910                         u32     vendor;
12911                         u32     device;
12912                         u32     rev;
12913                 } ich_chipsets[] = {
12914                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12915                           PCI_ANY_ID },
12916                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12917                           PCI_ANY_ID },
12918                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12919                           0xa },
12920                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12921                           PCI_ANY_ID },
12922                         { },
12923                 };
12924                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12925                 struct pci_dev *bridge = NULL;
12926
12927                 while (pci_id->vendor != 0) {
12928                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
12929                                                 bridge);
12930                         if (!bridge) {
12931                                 pci_id++;
12932                                 continue;
12933                         }
12934                         if (pci_id->rev != PCI_ANY_ID) {
12935                                 if (bridge->revision > pci_id->rev)
12936                                         continue;
12937                         }
12938                         if (bridge->subordinate &&
12939                             (bridge->subordinate->number ==
12940                              tp->pdev->bus->number)) {
12941
12942                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12943                                 pci_dev_put(bridge);
12944                                 break;
12945                         }
12946                 }
12947         }
12948
12949         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12950                 static struct tg3_dev_id {
12951                         u32     vendor;
12952                         u32     device;
12953                 } bridge_chipsets[] = {
12954                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12955                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12956                         { },
12957                 };
12958                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12959                 struct pci_dev *bridge = NULL;
12960
12961                 while (pci_id->vendor != 0) {
12962                         bridge = pci_get_device(pci_id->vendor,
12963                                                 pci_id->device,
12964                                                 bridge);
12965                         if (!bridge) {
12966                                 pci_id++;
12967                                 continue;
12968                         }
12969                         if (bridge->subordinate &&
12970                             (bridge->subordinate->number <=
12971                              tp->pdev->bus->number) &&
12972                             (bridge->subordinate->subordinate >=
12973                              tp->pdev->bus->number)) {
12974                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12975                                 pci_dev_put(bridge);
12976                                 break;
12977                         }
12978                 }
12979         }
12980
12981         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12982          * DMA addresses > 40-bit. This bridge may have other additional
12983          * 57xx devices behind it in some 4-port NIC designs for example.
12984          * Any tg3 device found behind the bridge will also need the 40-bit
12985          * DMA workaround.
12986          */
12987         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12988             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12989                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
12990                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12991                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
12992         } else {
12993                 struct pci_dev *bridge = NULL;
12994
12995                 do {
12996                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12997                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
12998                                                 bridge);
12999                         if (bridge && bridge->subordinate &&
13000                             (bridge->subordinate->number <=
13001                              tp->pdev->bus->number) &&
13002                             (bridge->subordinate->subordinate >=
13003                              tp->pdev->bus->number)) {
13004                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13005                                 pci_dev_put(bridge);
13006                                 break;
13007                         }
13008                 } while (bridge);
13009         }
13010
13011         /* Initialize misc host control in PCI block. */
13012         tp->misc_host_ctrl |= (misc_ctrl_reg &
13013                                MISC_HOST_CTRL_CHIPREV);
13014         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13015                                tp->misc_host_ctrl);
13016
13017         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13018             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13019             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13020                 tp->pdev_peer = tg3_find_peer(tp);
13021
13022         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13023             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13024             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13025                 tp->tg3_flags3 |= TG3_FLG3_5717_PLUS;
13026
13027         /* Intentionally exclude ASIC_REV_5906 */
13028         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13029             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13030             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13031             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13032             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13033             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13034             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13035                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13036
13037         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13038             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13039             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13040             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13041             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13042                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13043
13044         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13045             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13046                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13047
13048         /* 5700 B0 chips do not support checksumming correctly due
13049          * to hardware bugs.
13050          */
13051         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13052                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13053         else {
13054                 unsigned long features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_GRO;
13055
13056                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13057                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13058                         features |= NETIF_F_IPV6_CSUM;
13059                 tp->dev->features |= features;
13060                 vlan_features_add(tp->dev, features);
13061         }
13062
13063         /* Determine TSO capabilities */
13064         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13065                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13066         else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13067                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13068                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13069         else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13070                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13071                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13072                     tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13073                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13074         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13075                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13076                    tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13077                 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13078                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13079                         tp->fw_needed = FIRMWARE_TG3TSO5;
13080                 else
13081                         tp->fw_needed = FIRMWARE_TG3TSO;
13082         }
13083
13084         tp->irq_max = 1;
13085
13086         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13087                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13088                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13089                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13090                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13091                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13092                      tp->pdev_peer == tp->pdev))
13093                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13094
13095                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13096                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13097                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13098                 }
13099
13100                 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
13101                         tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13102                         tp->irq_max = TG3_IRQ_MAX_VECS;
13103                 }
13104         }
13105
13106         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13107             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13108             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13109                 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13110         else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13111                 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13112                 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13113         }
13114
13115         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13116                 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13117
13118         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13119             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13120             (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13121                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13122
13123         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13124                               &pci_state_reg);
13125
13126         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13127         if (tp->pcie_cap != 0) {
13128                 u16 lnkctl;
13129
13130                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13131
13132                 pcie_set_readrq(tp->pdev, 4096);
13133
13134                 pci_read_config_word(tp->pdev,
13135                                      tp->pcie_cap + PCI_EXP_LNKCTL,
13136                                      &lnkctl);
13137                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13138                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13139                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13140                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13141                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13142                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13143                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13144                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13145                 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13146                         tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13147                 }
13148         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13149                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13150         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13151                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13152                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13153                 if (!tp->pcix_cap) {
13154                         dev_err(&tp->pdev->dev,
13155                                 "Cannot find PCI-X capability, aborting\n");
13156                         return -EIO;
13157                 }
13158
13159                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13160                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13161         }
13162
13163         /* If we have an AMD 762 or VIA K8T800 chipset, write
13164          * reordering to the mailbox registers done by the host
13165          * controller can cause major troubles.  We read back from
13166          * every mailbox register write to force the writes to be
13167          * posted to the chip in order.
13168          */
13169         if (pci_dev_present(write_reorder_chipsets) &&
13170             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13171                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13172
13173         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13174                              &tp->pci_cacheline_sz);
13175         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13176                              &tp->pci_lat_timer);
13177         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13178             tp->pci_lat_timer < 64) {
13179                 tp->pci_lat_timer = 64;
13180                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13181                                       tp->pci_lat_timer);
13182         }
13183
13184         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13185                 /* 5700 BX chips need to have their TX producer index
13186                  * mailboxes written twice to workaround a bug.
13187                  */
13188                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13189
13190                 /* If we are in PCI-X mode, enable register write workaround.
13191                  *
13192                  * The workaround is to use indirect register accesses
13193                  * for all chip writes not to mailbox registers.
13194                  */
13195                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13196                         u32 pm_reg;
13197
13198                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13199
13200                         /* The chip can have it's power management PCI config
13201                          * space registers clobbered due to this bug.
13202                          * So explicitly force the chip into D0 here.
13203                          */
13204                         pci_read_config_dword(tp->pdev,
13205                                               tp->pm_cap + PCI_PM_CTRL,
13206                                               &pm_reg);
13207                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13208                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13209                         pci_write_config_dword(tp->pdev,
13210                                                tp->pm_cap + PCI_PM_CTRL,
13211                                                pm_reg);
13212
13213                         /* Also, force SERR#/PERR# in PCI command. */
13214                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13215                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13216                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13217                 }
13218         }
13219
13220         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13221                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13222         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13223                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13224
13225         /* Chip-specific fixup from Broadcom driver */
13226         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13227             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13228                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13229                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13230         }
13231
13232         /* Default fast path register access methods */
13233         tp->read32 = tg3_read32;
13234         tp->write32 = tg3_write32;
13235         tp->read32_mbox = tg3_read32;
13236         tp->write32_mbox = tg3_write32;
13237         tp->write32_tx_mbox = tg3_write32;
13238         tp->write32_rx_mbox = tg3_write32;
13239
13240         /* Various workaround register access methods */
13241         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13242                 tp->write32 = tg3_write_indirect_reg32;
13243         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13244                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13245                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13246                 /*
13247                  * Back to back register writes can cause problems on these
13248                  * chips, the workaround is to read back all reg writes
13249                  * except those to mailbox regs.
13250                  *
13251                  * See tg3_write_indirect_reg32().
13252                  */
13253                 tp->write32 = tg3_write_flush_reg32;
13254         }
13255
13256         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13257             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13258                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13259                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13260                         tp->write32_rx_mbox = tg3_write_flush_reg32;
13261         }
13262
13263         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13264                 tp->read32 = tg3_read_indirect_reg32;
13265                 tp->write32 = tg3_write_indirect_reg32;
13266                 tp->read32_mbox = tg3_read_indirect_mbox;
13267                 tp->write32_mbox = tg3_write_indirect_mbox;
13268                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13269                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13270
13271                 iounmap(tp->regs);
13272                 tp->regs = NULL;
13273
13274                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13275                 pci_cmd &= ~PCI_COMMAND_MEMORY;
13276                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13277         }
13278         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13279                 tp->read32_mbox = tg3_read32_mbox_5906;
13280                 tp->write32_mbox = tg3_write32_mbox_5906;
13281                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13282                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13283         }
13284
13285         if (tp->write32 == tg3_write_indirect_reg32 ||
13286             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13287              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13288               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13289                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13290
13291         /* Get eeprom hw config before calling tg3_set_power_state().
13292          * In particular, the TG3_FLG2_IS_NIC flag must be
13293          * determined before calling tg3_set_power_state() so that
13294          * we know whether or not to switch out of Vaux power.
13295          * When the flag is set, it means that GPIO1 is used for eeprom
13296          * write protect and also implies that it is a LOM where GPIOs
13297          * are not used to switch power.
13298          */
13299         tg3_get_eeprom_hw_cfg(tp);
13300
13301         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13302                 /* Allow reads and writes to the
13303                  * APE register and memory space.
13304                  */
13305                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13306                                  PCISTATE_ALLOW_APE_SHMEM_WR |
13307                                  PCISTATE_ALLOW_APE_PSPACE_WR;
13308                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13309                                        pci_state_reg);
13310         }
13311
13312         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13313             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13314             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13315             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13316             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13317                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13318
13319         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13320          * GPIO1 driven high will bring 5700's external PHY out of reset.
13321          * It is also used as eeprom write protect on LOMs.
13322          */
13323         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13324         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13325             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13326                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13327                                        GRC_LCLCTRL_GPIO_OUTPUT1);
13328         /* Unused GPIO3 must be driven as output on 5752 because there
13329          * are no pull-up resistors on unused GPIO pins.
13330          */
13331         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13332                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13333
13334         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13335             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13336             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13337                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13338
13339         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13340             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13341                 /* Turn off the debug UART. */
13342                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13343                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13344                         /* Keep VMain power. */
13345                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13346                                               GRC_LCLCTRL_GPIO_OUTPUT0;
13347         }
13348
13349         /* Force the chip into D0. */
13350         err = tg3_set_power_state(tp, PCI_D0);
13351         if (err) {
13352                 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
13353                 return err;
13354         }
13355
13356         /* Derive initial jumbo mode from MTU assigned in
13357          * ether_setup() via the alloc_etherdev() call
13358          */
13359         if (tp->dev->mtu > ETH_DATA_LEN &&
13360             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13361                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13362
13363         /* Determine WakeOnLan speed to use. */
13364         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13365             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13366             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13367             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13368                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13369         } else {
13370                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13371         }
13372
13373         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13374                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
13375
13376         /* A few boards don't want Ethernet@WireSpeed phy feature */
13377         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13378             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13379              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13380              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13381             (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
13382             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
13383                 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
13384
13385         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13386             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13387                 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
13388         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13389                 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
13390
13391         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13392             !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
13393             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13394             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13395             !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
13396                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13397                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13398                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13399                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13400                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13401                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13402                                 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
13403                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13404                                 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
13405                 } else
13406                         tp->phy_flags |= TG3_PHYFLG_BER_BUG;
13407         }
13408
13409         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13410             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13411                 tp->phy_otp = tg3_read_otp_phycfg(tp);
13412                 if (tp->phy_otp == 0)
13413                         tp->phy_otp = TG3_OTP_DEFAULT;
13414         }
13415
13416         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13417                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13418         else
13419                 tp->mi_mode = MAC_MI_MODE_BASE;
13420
13421         tp->coalesce_mode = 0;
13422         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13423             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13424                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13425
13426         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13427             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13428                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13429
13430         err = tg3_mdio_init(tp);
13431         if (err)
13432                 return err;
13433
13434         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
13435             tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
13436                 return -ENOTSUPP;
13437
13438         /* Initialize data/descriptor byte/word swapping. */
13439         val = tr32(GRC_MODE);
13440         val &= GRC_MODE_HOST_STACKUP;
13441         tw32(GRC_MODE, val | tp->grc_mode);
13442
13443         tg3_switch_clocks(tp);
13444
13445         /* Clear this out for sanity. */
13446         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13447
13448         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13449                               &pci_state_reg);
13450         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13451             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13452                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13453
13454                 if (chiprevid == CHIPREV_ID_5701_A0 ||
13455                     chiprevid == CHIPREV_ID_5701_B0 ||
13456                     chiprevid == CHIPREV_ID_5701_B2 ||
13457                     chiprevid == CHIPREV_ID_5701_B5) {
13458                         void __iomem *sram_base;
13459
13460                         /* Write some dummy words into the SRAM status block
13461                          * area, see if it reads back correctly.  If the return
13462                          * value is bad, force enable the PCIX workaround.
13463                          */
13464                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13465
13466                         writel(0x00000000, sram_base);
13467                         writel(0x00000000, sram_base + 4);
13468                         writel(0xffffffff, sram_base + 4);
13469                         if (readl(sram_base) != 0x00000000)
13470                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13471                 }
13472         }
13473
13474         udelay(50);
13475         tg3_nvram_init(tp);
13476
13477         grc_misc_cfg = tr32(GRC_MISC_CFG);
13478         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13479
13480         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13481             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13482              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13483                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13484
13485         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13486             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13487                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13488         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13489                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13490                                       HOSTCC_MODE_CLRTICK_TXBD);
13491
13492                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13493                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13494                                        tp->misc_host_ctrl);
13495         }
13496
13497         /* Preserve the APE MAC_MODE bits */
13498         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13499                 tp->mac_mode = tr32(MAC_MODE) |
13500                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13501         else
13502                 tp->mac_mode = TG3_DEF_MAC_MODE;
13503
13504         /* these are limited to 10/100 only */
13505         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13506              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13507             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13508              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13509              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13510               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13511               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13512             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13513              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13514               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13515               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13516             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13517             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13518             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
13519             (tp->phy_flags & TG3_PHYFLG_IS_FET))
13520                 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
13521
13522         err = tg3_phy_probe(tp);
13523         if (err) {
13524                 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
13525                 /* ... but do not return immediately ... */
13526                 tg3_mdio_fini(tp);
13527         }
13528
13529         tg3_read_vpd(tp);
13530         tg3_read_fw_ver(tp);
13531
13532         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
13533                 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
13534         } else {
13535                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13536                         tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
13537                 else
13538                         tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
13539         }
13540
13541         /* 5700 {AX,BX} chips have a broken status block link
13542          * change bit implementation, so we must use the
13543          * status register in those cases.
13544          */
13545         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13546                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13547         else
13548                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13549
13550         /* The led_ctrl is set during tg3_phy_probe, here we might
13551          * have to force the link status polling mechanism based
13552          * upon subsystem IDs.
13553          */
13554         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13555             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13556             !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
13557                 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
13558                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13559         }
13560
13561         /* For all SERDES we poll the MAC status register. */
13562         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
13563                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13564         else
13565                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13566
13567         tp->rx_offset = NET_IP_ALIGN + TG3_RX_HEADROOM;
13568         tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
13569         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13570             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
13571                 tp->rx_offset -= NET_IP_ALIGN;
13572 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
13573                 tp->rx_copy_thresh = ~(u16)0;
13574 #endif
13575         }
13576
13577         tp->rx_std_max_post = TG3_RX_RING_SIZE;
13578
13579         /* Increment the rx prod index on the rx std ring by at most
13580          * 8 for these chips to workaround hw errata.
13581          */
13582         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13583             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13584             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13585                 tp->rx_std_max_post = 8;
13586
13587         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13588                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13589                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
13590
13591         return err;
13592 }
13593
13594 #ifdef CONFIG_SPARC
13595 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13596 {
13597         struct net_device *dev = tp->dev;
13598         struct pci_dev *pdev = tp->pdev;
13599         struct device_node *dp = pci_device_to_OF_node(pdev);
13600         const unsigned char *addr;
13601         int len;
13602
13603         addr = of_get_property(dp, "local-mac-address", &len);
13604         if (addr && len == 6) {
13605                 memcpy(dev->dev_addr, addr, 6);
13606                 memcpy(dev->perm_addr, dev->dev_addr, 6);
13607                 return 0;
13608         }
13609         return -ENODEV;
13610 }
13611
13612 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13613 {
13614         struct net_device *dev = tp->dev;
13615
13616         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13617         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13618         return 0;
13619 }
13620 #endif
13621
13622 static int __devinit tg3_get_device_address(struct tg3 *tp)
13623 {
13624         struct net_device *dev = tp->dev;
13625         u32 hi, lo, mac_offset;
13626         int addr_ok = 0;
13627
13628 #ifdef CONFIG_SPARC
13629         if (!tg3_get_macaddr_sparc(tp))
13630                 return 0;
13631 #endif
13632
13633         mac_offset = 0x7c;
13634         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13635             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13636                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13637                         mac_offset = 0xcc;
13638                 if (tg3_nvram_lock(tp))
13639                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13640                 else
13641                         tg3_nvram_unlock(tp);
13642         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13643                    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
13644                 if (PCI_FUNC(tp->pdev->devfn) & 1)
13645                         mac_offset = 0xcc;
13646                 if (PCI_FUNC(tp->pdev->devfn) > 1)
13647                         mac_offset += 0x18c;
13648         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13649                 mac_offset = 0x10;
13650
13651         /* First try to get it from MAC address mailbox. */
13652         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13653         if ((hi >> 16) == 0x484b) {
13654                 dev->dev_addr[0] = (hi >>  8) & 0xff;
13655                 dev->dev_addr[1] = (hi >>  0) & 0xff;
13656
13657                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13658                 dev->dev_addr[2] = (lo >> 24) & 0xff;
13659                 dev->dev_addr[3] = (lo >> 16) & 0xff;
13660                 dev->dev_addr[4] = (lo >>  8) & 0xff;
13661                 dev->dev_addr[5] = (lo >>  0) & 0xff;
13662
13663                 /* Some old bootcode may report a 0 MAC address in SRAM */
13664                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13665         }
13666         if (!addr_ok) {
13667                 /* Next, try NVRAM. */
13668                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13669                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13670                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13671                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13672                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13673                 }
13674                 /* Finally just fetch it out of the MAC control regs. */
13675                 else {
13676                         hi = tr32(MAC_ADDR_0_HIGH);
13677                         lo = tr32(MAC_ADDR_0_LOW);
13678
13679                         dev->dev_addr[5] = lo & 0xff;
13680                         dev->dev_addr[4] = (lo >> 8) & 0xff;
13681                         dev->dev_addr[3] = (lo >> 16) & 0xff;
13682                         dev->dev_addr[2] = (lo >> 24) & 0xff;
13683                         dev->dev_addr[1] = hi & 0xff;
13684                         dev->dev_addr[0] = (hi >> 8) & 0xff;
13685                 }
13686         }
13687
13688         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13689 #ifdef CONFIG_SPARC
13690                 if (!tg3_get_default_macaddr_sparc(tp))
13691                         return 0;
13692 #endif
13693                 return -EINVAL;
13694         }
13695         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13696         return 0;
13697 }
13698
13699 #define BOUNDARY_SINGLE_CACHELINE       1
13700 #define BOUNDARY_MULTI_CACHELINE        2
13701
13702 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13703 {
13704         int cacheline_size;
13705         u8 byte;
13706         int goal;
13707
13708         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13709         if (byte == 0)
13710                 cacheline_size = 1024;
13711         else
13712                 cacheline_size = (int) byte * 4;
13713
13714         /* On 5703 and later chips, the boundary bits have no
13715          * effect.
13716          */
13717         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13718             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13719             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13720                 goto out;
13721
13722 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13723         goal = BOUNDARY_MULTI_CACHELINE;
13724 #else
13725 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13726         goal = BOUNDARY_SINGLE_CACHELINE;
13727 #else
13728         goal = 0;
13729 #endif
13730 #endif
13731
13732         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
13733                 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13734                 goto out;
13735         }
13736
13737         if (!goal)
13738                 goto out;
13739
13740         /* PCI controllers on most RISC systems tend to disconnect
13741          * when a device tries to burst across a cache-line boundary.
13742          * Therefore, letting tg3 do so just wastes PCI bandwidth.
13743          *
13744          * Unfortunately, for PCI-E there are only limited
13745          * write-side controls for this, and thus for reads
13746          * we will still get the disconnects.  We'll also waste
13747          * these PCI cycles for both read and write for chips
13748          * other than 5700 and 5701 which do not implement the
13749          * boundary bits.
13750          */
13751         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13752             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13753                 switch (cacheline_size) {
13754                 case 16:
13755                 case 32:
13756                 case 64:
13757                 case 128:
13758                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13759                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13760                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13761                         } else {
13762                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13763                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13764                         }
13765                         break;
13766
13767                 case 256:
13768                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13769                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13770                         break;
13771
13772                 default:
13773                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13774                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13775                         break;
13776                 }
13777         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13778                 switch (cacheline_size) {
13779                 case 16:
13780                 case 32:
13781                 case 64:
13782                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13783                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13784                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13785                                 break;
13786                         }
13787                         /* fallthrough */
13788                 case 128:
13789                 default:
13790                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13791                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13792                         break;
13793                 }
13794         } else {
13795                 switch (cacheline_size) {
13796                 case 16:
13797                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13798                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13799                                         DMA_RWCTRL_WRITE_BNDRY_16);
13800                                 break;
13801                         }
13802                         /* fallthrough */
13803                 case 32:
13804                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13805                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13806                                         DMA_RWCTRL_WRITE_BNDRY_32);
13807                                 break;
13808                         }
13809                         /* fallthrough */
13810                 case 64:
13811                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13812                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13813                                         DMA_RWCTRL_WRITE_BNDRY_64);
13814                                 break;
13815                         }
13816                         /* fallthrough */
13817                 case 128:
13818                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13819                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13820                                         DMA_RWCTRL_WRITE_BNDRY_128);
13821                                 break;
13822                         }
13823                         /* fallthrough */
13824                 case 256:
13825                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
13826                                 DMA_RWCTRL_WRITE_BNDRY_256);
13827                         break;
13828                 case 512:
13829                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
13830                                 DMA_RWCTRL_WRITE_BNDRY_512);
13831                         break;
13832                 case 1024:
13833                 default:
13834                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13835                                 DMA_RWCTRL_WRITE_BNDRY_1024);
13836                         break;
13837                 }
13838         }
13839
13840 out:
13841         return val;
13842 }
13843
13844 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13845 {
13846         struct tg3_internal_buffer_desc test_desc;
13847         u32 sram_dma_descs;
13848         int i, ret;
13849
13850         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13851
13852         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13853         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13854         tw32(RDMAC_STATUS, 0);
13855         tw32(WDMAC_STATUS, 0);
13856
13857         tw32(BUFMGR_MODE, 0);
13858         tw32(FTQ_RESET, 0);
13859
13860         test_desc.addr_hi = ((u64) buf_dma) >> 32;
13861         test_desc.addr_lo = buf_dma & 0xffffffff;
13862         test_desc.nic_mbuf = 0x00002100;
13863         test_desc.len = size;
13864
13865         /*
13866          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13867          * the *second* time the tg3 driver was getting loaded after an
13868          * initial scan.
13869          *
13870          * Broadcom tells me:
13871          *   ...the DMA engine is connected to the GRC block and a DMA
13872          *   reset may affect the GRC block in some unpredictable way...
13873          *   The behavior of resets to individual blocks has not been tested.
13874          *
13875          * Broadcom noted the GRC reset will also reset all sub-components.
13876          */
13877         if (to_device) {
13878                 test_desc.cqid_sqid = (13 << 8) | 2;
13879
13880                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13881                 udelay(40);
13882         } else {
13883                 test_desc.cqid_sqid = (16 << 8) | 7;
13884
13885                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13886                 udelay(40);
13887         }
13888         test_desc.flags = 0x00000005;
13889
13890         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13891                 u32 val;
13892
13893                 val = *(((u32 *)&test_desc) + i);
13894                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13895                                        sram_dma_descs + (i * sizeof(u32)));
13896                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13897         }
13898         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13899
13900         if (to_device)
13901                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13902         else
13903                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13904
13905         ret = -ENODEV;
13906         for (i = 0; i < 40; i++) {
13907                 u32 val;
13908
13909                 if (to_device)
13910                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13911                 else
13912                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13913                 if ((val & 0xffff) == sram_dma_descs) {
13914                         ret = 0;
13915                         break;
13916                 }
13917
13918                 udelay(100);
13919         }
13920
13921         return ret;
13922 }
13923
13924 #define TEST_BUFFER_SIZE        0x2000
13925
13926 static int __devinit tg3_test_dma(struct tg3 *tp)
13927 {
13928         dma_addr_t buf_dma;
13929         u32 *buf, saved_dma_rwctrl;
13930         int ret = 0;
13931
13932         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13933         if (!buf) {
13934                 ret = -ENOMEM;
13935                 goto out_nofree;
13936         }
13937
13938         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13939                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13940
13941         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13942
13943         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13944                 goto out;
13945
13946         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13947                 /* DMA read watermark not used on PCIE */
13948                 tp->dma_rwctrl |= 0x00180000;
13949         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
13950                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13951                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
13952                         tp->dma_rwctrl |= 0x003f0000;
13953                 else
13954                         tp->dma_rwctrl |= 0x003f000f;
13955         } else {
13956                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13957                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13958                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
13959                         u32 read_water = 0x7;
13960
13961                         /* If the 5704 is behind the EPB bridge, we can
13962                          * do the less restrictive ONE_DMA workaround for
13963                          * better performance.
13964                          */
13965                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13966                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13967                                 tp->dma_rwctrl |= 0x8000;
13968                         else if (ccval == 0x6 || ccval == 0x7)
13969                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13970
13971                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13972                                 read_water = 4;
13973                         /* Set bit 23 to enable PCIX hw bug fix */
13974                         tp->dma_rwctrl |=
13975                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13976                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13977                                 (1 << 23);
13978                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13979                         /* 5780 always in PCIX mode */
13980                         tp->dma_rwctrl |= 0x00144000;
13981                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13982                         /* 5714 always in PCIX mode */
13983                         tp->dma_rwctrl |= 0x00148000;
13984                 } else {
13985                         tp->dma_rwctrl |= 0x001b000f;
13986                 }
13987         }
13988
13989         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13990             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13991                 tp->dma_rwctrl &= 0xfffffff0;
13992
13993         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13994             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13995                 /* Remove this if it causes problems for some boards. */
13996                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13997
13998                 /* On 5700/5701 chips, we need to set this bit.
13999                  * Otherwise the chip will issue cacheline transactions
14000                  * to streamable DMA memory with not all the byte
14001                  * enables turned on.  This is an error on several
14002                  * RISC PCI controllers, in particular sparc64.
14003                  *
14004                  * On 5703/5704 chips, this bit has been reassigned
14005                  * a different meaning.  In particular, it is used
14006                  * on those chips to enable a PCI-X workaround.
14007                  */
14008                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
14009         }
14010
14011         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14012
14013 #if 0
14014         /* Unneeded, already done by tg3_get_invariants.  */
14015         tg3_switch_clocks(tp);
14016 #endif
14017
14018         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14019             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14020                 goto out;
14021
14022         /* It is best to perform DMA test with maximum write burst size
14023          * to expose the 5700/5701 write DMA bug.
14024          */
14025         saved_dma_rwctrl = tp->dma_rwctrl;
14026         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14027         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14028
14029         while (1) {
14030                 u32 *p = buf, i;
14031
14032                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14033                         p[i] = i;
14034
14035                 /* Send the buffer to the chip. */
14036                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14037                 if (ret) {
14038                         dev_err(&tp->pdev->dev,
14039                                 "%s: Buffer write failed. err = %d\n",
14040                                 __func__, ret);
14041                         break;
14042                 }
14043
14044 #if 0
14045                 /* validate data reached card RAM correctly. */
14046                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14047                         u32 val;
14048                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
14049                         if (le32_to_cpu(val) != p[i]) {
14050                                 dev_err(&tp->pdev->dev,
14051                                         "%s: Buffer corrupted on device! "
14052                                         "(%d != %d)\n", __func__, val, i);
14053                                 /* ret = -ENODEV here? */
14054                         }
14055                         p[i] = 0;
14056                 }
14057 #endif
14058                 /* Now read it back. */
14059                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14060                 if (ret) {
14061                         dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
14062                                 "err = %d\n", __func__, ret);
14063                         break;
14064                 }
14065
14066                 /* Verify it. */
14067                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14068                         if (p[i] == i)
14069                                 continue;
14070
14071                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14072                             DMA_RWCTRL_WRITE_BNDRY_16) {
14073                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14074                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14075                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14076                                 break;
14077                         } else {
14078                                 dev_err(&tp->pdev->dev,
14079                                         "%s: Buffer corrupted on read back! "
14080                                         "(%d != %d)\n", __func__, p[i], i);
14081                                 ret = -ENODEV;
14082                                 goto out;
14083                         }
14084                 }
14085
14086                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14087                         /* Success. */
14088                         ret = 0;
14089                         break;
14090                 }
14091         }
14092         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14093             DMA_RWCTRL_WRITE_BNDRY_16) {
14094                 static struct pci_device_id dma_wait_state_chipsets[] = {
14095                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14096                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14097                         { },
14098                 };
14099
14100                 /* DMA test passed without adjusting DMA boundary,
14101                  * now look for chipsets that are known to expose the
14102                  * DMA bug without failing the test.
14103                  */
14104                 if (pci_dev_present(dma_wait_state_chipsets)) {
14105                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14106                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14107                 } else {
14108                         /* Safe to use the calculated DMA boundary. */
14109                         tp->dma_rwctrl = saved_dma_rwctrl;
14110                 }
14111
14112                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14113         }
14114
14115 out:
14116         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14117 out_nofree:
14118         return ret;
14119 }
14120
14121 static void __devinit tg3_init_link_config(struct tg3 *tp)
14122 {
14123         tp->link_config.advertising =
14124                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14125                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14126                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14127                  ADVERTISED_Autoneg | ADVERTISED_MII);
14128         tp->link_config.speed = SPEED_INVALID;
14129         tp->link_config.duplex = DUPLEX_INVALID;
14130         tp->link_config.autoneg = AUTONEG_ENABLE;
14131         tp->link_config.active_speed = SPEED_INVALID;
14132         tp->link_config.active_duplex = DUPLEX_INVALID;
14133         tp->link_config.orig_speed = SPEED_INVALID;
14134         tp->link_config.orig_duplex = DUPLEX_INVALID;
14135         tp->link_config.orig_autoneg = AUTONEG_INVALID;
14136 }
14137
14138 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14139 {
14140         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
14141                 tp->bufmgr_config.mbuf_read_dma_low_water =
14142                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14143                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14144                         DEFAULT_MB_MACRX_LOW_WATER_57765;
14145                 tp->bufmgr_config.mbuf_high_water =
14146                         DEFAULT_MB_HIGH_WATER_57765;
14147
14148                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14149                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14150                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14151                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14152                 tp->bufmgr_config.mbuf_high_water_jumbo =
14153                         DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14154         } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14155                 tp->bufmgr_config.mbuf_read_dma_low_water =
14156                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14157                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14158                         DEFAULT_MB_MACRX_LOW_WATER_5705;
14159                 tp->bufmgr_config.mbuf_high_water =
14160                         DEFAULT_MB_HIGH_WATER_5705;
14161                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14162                         tp->bufmgr_config.mbuf_mac_rx_low_water =
14163                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
14164                         tp->bufmgr_config.mbuf_high_water =
14165                                 DEFAULT_MB_HIGH_WATER_5906;
14166                 }
14167
14168                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14169                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14170                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14171                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14172                 tp->bufmgr_config.mbuf_high_water_jumbo =
14173                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14174         } else {
14175                 tp->bufmgr_config.mbuf_read_dma_low_water =
14176                         DEFAULT_MB_RDMA_LOW_WATER;
14177                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14178                         DEFAULT_MB_MACRX_LOW_WATER;
14179                 tp->bufmgr_config.mbuf_high_water =
14180                         DEFAULT_MB_HIGH_WATER;
14181
14182                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14183                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14184                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14185                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14186                 tp->bufmgr_config.mbuf_high_water_jumbo =
14187                         DEFAULT_MB_HIGH_WATER_JUMBO;
14188         }
14189
14190         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14191         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14192 }
14193
14194 static char * __devinit tg3_phy_string(struct tg3 *tp)
14195 {
14196         switch (tp->phy_id & TG3_PHY_ID_MASK) {
14197         case TG3_PHY_ID_BCM5400:        return "5400";
14198         case TG3_PHY_ID_BCM5401:        return "5401";
14199         case TG3_PHY_ID_BCM5411:        return "5411";
14200         case TG3_PHY_ID_BCM5701:        return "5701";
14201         case TG3_PHY_ID_BCM5703:        return "5703";
14202         case TG3_PHY_ID_BCM5704:        return "5704";
14203         case TG3_PHY_ID_BCM5705:        return "5705";
14204         case TG3_PHY_ID_BCM5750:        return "5750";
14205         case TG3_PHY_ID_BCM5752:        return "5752";
14206         case TG3_PHY_ID_BCM5714:        return "5714";
14207         case TG3_PHY_ID_BCM5780:        return "5780";
14208         case TG3_PHY_ID_BCM5755:        return "5755";
14209         case TG3_PHY_ID_BCM5787:        return "5787";
14210         case TG3_PHY_ID_BCM5784:        return "5784";
14211         case TG3_PHY_ID_BCM5756:        return "5722/5756";
14212         case TG3_PHY_ID_BCM5906:        return "5906";
14213         case TG3_PHY_ID_BCM5761:        return "5761";
14214         case TG3_PHY_ID_BCM5718C:       return "5718C";
14215         case TG3_PHY_ID_BCM5718S:       return "5718S";
14216         case TG3_PHY_ID_BCM57765:       return "57765";
14217         case TG3_PHY_ID_BCM5719C:       return "5719C";
14218         case TG3_PHY_ID_BCM8002:        return "8002/serdes";
14219         case 0:                 return "serdes";
14220         default:                return "unknown";
14221         }
14222 }
14223
14224 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14225 {
14226         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14227                 strcpy(str, "PCI Express");
14228                 return str;
14229         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14230                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14231
14232                 strcpy(str, "PCIX:");
14233
14234                 if ((clock_ctrl == 7) ||
14235                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14236                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14237                         strcat(str, "133MHz");
14238                 else if (clock_ctrl == 0)
14239                         strcat(str, "33MHz");
14240                 else if (clock_ctrl == 2)
14241                         strcat(str, "50MHz");
14242                 else if (clock_ctrl == 4)
14243                         strcat(str, "66MHz");
14244                 else if (clock_ctrl == 6)
14245                         strcat(str, "100MHz");
14246         } else {
14247                 strcpy(str, "PCI:");
14248                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14249                         strcat(str, "66MHz");
14250                 else
14251                         strcat(str, "33MHz");
14252         }
14253         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14254                 strcat(str, ":32-bit");
14255         else
14256                 strcat(str, ":64-bit");
14257         return str;
14258 }
14259
14260 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14261 {
14262         struct pci_dev *peer;
14263         unsigned int func, devnr = tp->pdev->devfn & ~7;
14264
14265         for (func = 0; func < 8; func++) {
14266                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14267                 if (peer && peer != tp->pdev)
14268                         break;
14269                 pci_dev_put(peer);
14270         }
14271         /* 5704 can be configured in single-port mode, set peer to
14272          * tp->pdev in that case.
14273          */
14274         if (!peer) {
14275                 peer = tp->pdev;
14276                 return peer;
14277         }
14278
14279         /*
14280          * We don't need to keep the refcount elevated; there's no way
14281          * to remove one half of this device without removing the other
14282          */
14283         pci_dev_put(peer);
14284
14285         return peer;
14286 }
14287
14288 static void __devinit tg3_init_coal(struct tg3 *tp)
14289 {
14290         struct ethtool_coalesce *ec = &tp->coal;
14291
14292         memset(ec, 0, sizeof(*ec));
14293         ec->cmd = ETHTOOL_GCOALESCE;
14294         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14295         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14296         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14297         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14298         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14299         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14300         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14301         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14302         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14303
14304         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14305                                  HOSTCC_MODE_CLRTICK_TXBD)) {
14306                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14307                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14308                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14309                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14310         }
14311
14312         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14313                 ec->rx_coalesce_usecs_irq = 0;
14314                 ec->tx_coalesce_usecs_irq = 0;
14315                 ec->stats_block_coalesce_usecs = 0;
14316         }
14317 }
14318
14319 static const struct net_device_ops tg3_netdev_ops = {
14320         .ndo_open               = tg3_open,
14321         .ndo_stop               = tg3_close,
14322         .ndo_start_xmit         = tg3_start_xmit,
14323         .ndo_get_stats64        = tg3_get_stats64,
14324         .ndo_validate_addr      = eth_validate_addr,
14325         .ndo_set_multicast_list = tg3_set_rx_mode,
14326         .ndo_set_mac_address    = tg3_set_mac_addr,
14327         .ndo_do_ioctl           = tg3_ioctl,
14328         .ndo_tx_timeout         = tg3_tx_timeout,
14329         .ndo_change_mtu         = tg3_change_mtu,
14330 #if TG3_VLAN_TAG_USED
14331         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14332 #endif
14333 #ifdef CONFIG_NET_POLL_CONTROLLER
14334         .ndo_poll_controller    = tg3_poll_controller,
14335 #endif
14336 };
14337
14338 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14339         .ndo_open               = tg3_open,
14340         .ndo_stop               = tg3_close,
14341         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
14342         .ndo_get_stats64        = tg3_get_stats64,
14343         .ndo_validate_addr      = eth_validate_addr,
14344         .ndo_set_multicast_list = tg3_set_rx_mode,
14345         .ndo_set_mac_address    = tg3_set_mac_addr,
14346         .ndo_do_ioctl           = tg3_ioctl,
14347         .ndo_tx_timeout         = tg3_tx_timeout,
14348         .ndo_change_mtu         = tg3_change_mtu,
14349 #if TG3_VLAN_TAG_USED
14350         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14351 #endif
14352 #ifdef CONFIG_NET_POLL_CONTROLLER
14353         .ndo_poll_controller    = tg3_poll_controller,
14354 #endif
14355 };
14356
14357 static int __devinit tg3_init_one(struct pci_dev *pdev,
14358                                   const struct pci_device_id *ent)
14359 {
14360         struct net_device *dev;
14361         struct tg3 *tp;
14362         int i, err, pm_cap;
14363         u32 sndmbx, rcvmbx, intmbx;
14364         char str[40];
14365         u64 dma_mask, persist_dma_mask;
14366
14367         printk_once(KERN_INFO "%s\n", version);
14368
14369         err = pci_enable_device(pdev);
14370         if (err) {
14371                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
14372                 return err;
14373         }
14374
14375         err = pci_request_regions(pdev, DRV_MODULE_NAME);
14376         if (err) {
14377                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
14378                 goto err_out_disable_pdev;
14379         }
14380
14381         pci_set_master(pdev);
14382
14383         /* Find power-management capability. */
14384         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14385         if (pm_cap == 0) {
14386                 dev_err(&pdev->dev,
14387                         "Cannot find Power Management capability, aborting\n");
14388                 err = -EIO;
14389                 goto err_out_free_res;
14390         }
14391
14392         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14393         if (!dev) {
14394                 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
14395                 err = -ENOMEM;
14396                 goto err_out_free_res;
14397         }
14398
14399         SET_NETDEV_DEV(dev, &pdev->dev);
14400
14401 #if TG3_VLAN_TAG_USED
14402         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14403 #endif
14404
14405         tp = netdev_priv(dev);
14406         tp->pdev = pdev;
14407         tp->dev = dev;
14408         tp->pm_cap = pm_cap;
14409         tp->rx_mode = TG3_DEF_RX_MODE;
14410         tp->tx_mode = TG3_DEF_TX_MODE;
14411
14412         if (tg3_debug > 0)
14413                 tp->msg_enable = tg3_debug;
14414         else
14415                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14416
14417         /* The word/byte swap controls here control register access byte
14418          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
14419          * setting below.
14420          */
14421         tp->misc_host_ctrl =
14422                 MISC_HOST_CTRL_MASK_PCI_INT |
14423                 MISC_HOST_CTRL_WORD_SWAP |
14424                 MISC_HOST_CTRL_INDIR_ACCESS |
14425                 MISC_HOST_CTRL_PCISTATE_RW;
14426
14427         /* The NONFRM (non-frame) byte/word swap controls take effect
14428          * on descriptor entries, anything which isn't packet data.
14429          *
14430          * The StrongARM chips on the board (one for tx, one for rx)
14431          * are running in big-endian mode.
14432          */
14433         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14434                         GRC_MODE_WSWAP_NONFRM_DATA);
14435 #ifdef __BIG_ENDIAN
14436         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14437 #endif
14438         spin_lock_init(&tp->lock);
14439         spin_lock_init(&tp->indirect_lock);
14440         INIT_WORK(&tp->reset_task, tg3_reset_task);
14441
14442         tp->regs = pci_ioremap_bar(pdev, BAR_0);
14443         if (!tp->regs) {
14444                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
14445                 err = -ENOMEM;
14446                 goto err_out_free_dev;
14447         }
14448
14449         tg3_init_link_config(tp);
14450
14451         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14452         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14453
14454         dev->ethtool_ops = &tg3_ethtool_ops;
14455         dev->watchdog_timeo = TG3_TX_TIMEOUT;
14456         dev->irq = pdev->irq;
14457
14458         err = tg3_get_invariants(tp);
14459         if (err) {
14460                 dev_err(&pdev->dev,
14461                         "Problem fetching invariants of chip, aborting\n");
14462                 goto err_out_iounmap;
14463         }
14464
14465         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14466             tp->pci_chip_rev_id != CHIPREV_ID_5717_A0 &&
14467             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
14468                 dev->netdev_ops = &tg3_netdev_ops;
14469         else
14470                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14471
14472
14473         /* The EPB bridge inside 5714, 5715, and 5780 and any
14474          * device behind the EPB cannot support DMA addresses > 40-bit.
14475          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14476          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14477          * do DMA address check in tg3_start_xmit().
14478          */
14479         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14480                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14481         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14482                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14483 #ifdef CONFIG_HIGHMEM
14484                 dma_mask = DMA_BIT_MASK(64);
14485 #endif
14486         } else
14487                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14488
14489         /* Configure DMA attributes. */
14490         if (dma_mask > DMA_BIT_MASK(32)) {
14491                 err = pci_set_dma_mask(pdev, dma_mask);
14492                 if (!err) {
14493                         dev->features |= NETIF_F_HIGHDMA;
14494                         err = pci_set_consistent_dma_mask(pdev,
14495                                                           persist_dma_mask);
14496                         if (err < 0) {
14497                                 dev_err(&pdev->dev, "Unable to obtain 64 bit "
14498                                         "DMA for consistent allocations\n");
14499                                 goto err_out_iounmap;
14500                         }
14501                 }
14502         }
14503         if (err || dma_mask == DMA_BIT_MASK(32)) {
14504                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14505                 if (err) {
14506                         dev_err(&pdev->dev,
14507                                 "No usable DMA configuration, aborting\n");
14508                         goto err_out_iounmap;
14509                 }
14510         }
14511
14512         tg3_init_bufmgr_config(tp);
14513
14514         /* Selectively allow TSO based on operating conditions */
14515         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14516             (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14517                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14518         else {
14519                 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14520                 tp->fw_needed = NULL;
14521         }
14522
14523         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14524                 tp->fw_needed = FIRMWARE_TG3;
14525
14526         /* TSO is on by default on chips that support hardware TSO.
14527          * Firmware TSO on older chips gives lower performance, so it
14528          * is off by default, but can be enabled using ethtool.
14529          */
14530         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14531             (dev->features & NETIF_F_IP_CSUM)) {
14532                 dev->features |= NETIF_F_TSO;
14533                 vlan_features_add(dev, NETIF_F_TSO);
14534         }
14535         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14536             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14537                 if (dev->features & NETIF_F_IPV6_CSUM) {
14538                         dev->features |= NETIF_F_TSO6;
14539                         vlan_features_add(dev, NETIF_F_TSO6);
14540                 }
14541                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14542                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14543                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14544                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14545                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14546                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
14547                         dev->features |= NETIF_F_TSO_ECN;
14548                         vlan_features_add(dev, NETIF_F_TSO_ECN);
14549                 }
14550         }
14551
14552         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14553             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14554             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14555                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14556                 tp->rx_pending = 63;
14557         }
14558
14559         err = tg3_get_device_address(tp);
14560         if (err) {
14561                 dev_err(&pdev->dev,
14562                         "Could not obtain valid ethernet address, aborting\n");
14563                 goto err_out_iounmap;
14564         }
14565
14566         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14567                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14568                 if (!tp->aperegs) {
14569                         dev_err(&pdev->dev,
14570                                 "Cannot map APE registers, aborting\n");
14571                         err = -ENOMEM;
14572                         goto err_out_iounmap;
14573                 }
14574
14575                 tg3_ape_lock_init(tp);
14576
14577                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14578                         tg3_read_dash_ver(tp);
14579         }
14580
14581         /*
14582          * Reset chip in case UNDI or EFI driver did not shutdown
14583          * DMA self test will enable WDMAC and we'll see (spurious)
14584          * pending DMA on the PCI bus at that point.
14585          */
14586         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14587             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14588                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14589                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14590         }
14591
14592         err = tg3_test_dma(tp);
14593         if (err) {
14594                 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
14595                 goto err_out_apeunmap;
14596         }
14597
14598         /* flow control autonegotiation is default behavior */
14599         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14600         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14601
14602         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14603         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14604         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14605         for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14606                 struct tg3_napi *tnapi = &tp->napi[i];
14607
14608                 tnapi->tp = tp;
14609                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14610
14611                 tnapi->int_mbox = intmbx;
14612                 if (i < 4)
14613                         intmbx += 0x8;
14614                 else
14615                         intmbx += 0x4;
14616
14617                 tnapi->consmbox = rcvmbx;
14618                 tnapi->prodmbox = sndmbx;
14619
14620                 if (i) {
14621                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14622                         netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14623                 } else {
14624                         tnapi->coal_now = HOSTCC_MODE_NOW;
14625                         netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14626                 }
14627
14628                 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14629                         break;
14630
14631                 /*
14632                  * If we support MSIX, we'll be using RSS.  If we're using
14633                  * RSS, the first vector only handles link interrupts and the
14634                  * remaining vectors handle rx and tx interrupts.  Reuse the
14635                  * mailbox values for the next iteration.  The values we setup
14636                  * above are still useful for the single vectored mode.
14637                  */
14638                 if (!i)
14639                         continue;
14640
14641                 rcvmbx += 0x8;
14642
14643                 if (sndmbx & 0x4)
14644                         sndmbx -= 0x4;
14645                 else
14646                         sndmbx += 0xc;
14647         }
14648
14649         tg3_init_coal(tp);
14650
14651         pci_set_drvdata(pdev, dev);
14652
14653         err = register_netdev(dev);
14654         if (err) {
14655                 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
14656                 goto err_out_apeunmap;
14657         }
14658
14659         netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14660                     tp->board_part_number,
14661                     tp->pci_chip_rev_id,
14662                     tg3_bus_string(tp, str),
14663                     dev->dev_addr);
14664
14665         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
14666                 struct phy_device *phydev;
14667                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14668                 netdev_info(dev,
14669                             "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14670                             phydev->drv->name, dev_name(&phydev->dev));
14671         } else {
14672                 char *ethtype;
14673
14674                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
14675                         ethtype = "10/100Base-TX";
14676                 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
14677                         ethtype = "1000Base-SX";
14678                 else
14679                         ethtype = "10/100/1000Base-T";
14680
14681                 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
14682                             "(WireSpeed[%d])\n", tg3_phy_string(tp), ethtype,
14683                           (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0);
14684         }
14685
14686         netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14687                     (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14688                     (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14689                     (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
14690                     (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14691                     (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14692         netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14693                     tp->dma_rwctrl,
14694                     pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
14695                     ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
14696
14697         return 0;
14698
14699 err_out_apeunmap:
14700         if (tp->aperegs) {
14701                 iounmap(tp->aperegs);
14702                 tp->aperegs = NULL;
14703         }
14704
14705 err_out_iounmap:
14706         if (tp->regs) {
14707                 iounmap(tp->regs);
14708                 tp->regs = NULL;
14709         }
14710
14711 err_out_free_dev:
14712         free_netdev(dev);
14713
14714 err_out_free_res:
14715         pci_release_regions(pdev);
14716
14717 err_out_disable_pdev:
14718         pci_disable_device(pdev);
14719         pci_set_drvdata(pdev, NULL);
14720         return err;
14721 }
14722
14723 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14724 {
14725         struct net_device *dev = pci_get_drvdata(pdev);
14726
14727         if (dev) {
14728                 struct tg3 *tp = netdev_priv(dev);
14729
14730                 if (tp->fw)
14731                         release_firmware(tp->fw);
14732
14733                 flush_scheduled_work();
14734
14735                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14736                         tg3_phy_fini(tp);
14737                         tg3_mdio_fini(tp);
14738                 }
14739
14740                 unregister_netdev(dev);
14741                 if (tp->aperegs) {
14742                         iounmap(tp->aperegs);
14743                         tp->aperegs = NULL;
14744                 }
14745                 if (tp->regs) {
14746                         iounmap(tp->regs);
14747                         tp->regs = NULL;
14748                 }
14749                 free_netdev(dev);
14750                 pci_release_regions(pdev);
14751                 pci_disable_device(pdev);
14752                 pci_set_drvdata(pdev, NULL);
14753         }
14754 }
14755
14756 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14757 {
14758         struct net_device *dev = pci_get_drvdata(pdev);
14759         struct tg3 *tp = netdev_priv(dev);
14760         pci_power_t target_state;
14761         int err;
14762
14763         /* PCI register 4 needs to be saved whether netif_running() or not.
14764          * MSI address and data need to be saved if using MSI and
14765          * netif_running().
14766          */
14767         pci_save_state(pdev);
14768
14769         if (!netif_running(dev))
14770                 return 0;
14771
14772         flush_scheduled_work();
14773         tg3_phy_stop(tp);
14774         tg3_netif_stop(tp);
14775
14776         del_timer_sync(&tp->timer);
14777
14778         tg3_full_lock(tp, 1);
14779         tg3_disable_ints(tp);
14780         tg3_full_unlock(tp);
14781
14782         netif_device_detach(dev);
14783
14784         tg3_full_lock(tp, 0);
14785         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14786         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14787         tg3_full_unlock(tp);
14788
14789         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14790
14791         err = tg3_set_power_state(tp, target_state);
14792         if (err) {
14793                 int err2;
14794
14795                 tg3_full_lock(tp, 0);
14796
14797                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14798                 err2 = tg3_restart_hw(tp, 1);
14799                 if (err2)
14800                         goto out;
14801
14802                 tp->timer.expires = jiffies + tp->timer_offset;
14803                 add_timer(&tp->timer);
14804
14805                 netif_device_attach(dev);
14806                 tg3_netif_start(tp);
14807
14808 out:
14809                 tg3_full_unlock(tp);
14810
14811                 if (!err2)
14812                         tg3_phy_start(tp);
14813         }
14814
14815         return err;
14816 }
14817
14818 static int tg3_resume(struct pci_dev *pdev)
14819 {
14820         struct net_device *dev = pci_get_drvdata(pdev);
14821         struct tg3 *tp = netdev_priv(dev);
14822         int err;
14823
14824         pci_restore_state(tp->pdev);
14825
14826         if (!netif_running(dev))
14827                 return 0;
14828
14829         err = tg3_set_power_state(tp, PCI_D0);
14830         if (err)
14831                 return err;
14832
14833         netif_device_attach(dev);
14834
14835         tg3_full_lock(tp, 0);
14836
14837         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14838         err = tg3_restart_hw(tp, 1);
14839         if (err)
14840                 goto out;
14841
14842         tp->timer.expires = jiffies + tp->timer_offset;
14843         add_timer(&tp->timer);
14844
14845         tg3_netif_start(tp);
14846
14847 out:
14848         tg3_full_unlock(tp);
14849
14850         if (!err)
14851                 tg3_phy_start(tp);
14852
14853         return err;
14854 }
14855
14856 static struct pci_driver tg3_driver = {
14857         .name           = DRV_MODULE_NAME,
14858         .id_table       = tg3_pci_tbl,
14859         .probe          = tg3_init_one,
14860         .remove         = __devexit_p(tg3_remove_one),
14861         .suspend        = tg3_suspend,
14862         .resume         = tg3_resume
14863 };
14864
14865 static int __init tg3_init(void)
14866 {
14867         return pci_register_driver(&tg3_driver);
14868 }
14869
14870 static void __exit tg3_cleanup(void)
14871 {
14872         pci_unregister_driver(&tg3_driver);
14873 }
14874
14875 module_init(tg3_init);
14876 module_exit(tg3_cleanup);