drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2010 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/stringify.h>
  22 #include <linux/kernel.h>
  23 #include <linux/types.h>
  24 #include <linux/compiler.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/in.h>
  28 #include <linux/init.h>
  29 #include <linux/ioport.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/ethtool.h>
  35 #include <linux/mii.h>
  36 #include <linux/phy.h>
  37 #include <linux/brcmphy.h>
  38 #include <linux/if_vlan.h>
  39 #include <linux/ip.h>
  40 #include <linux/tcp.h>
  41 #include <linux/workqueue.h>
  42 #include <linux/prefetch.h>
  43 #include <linux/dma-mapping.h>
  44 #include <linux/firmware.h>
  45
  46 #include <net/checksum.h>
  47 #include <net/ip.h>
  48
  49 #include <asm/system.h>
  50 #include <asm/io.h>
  51 #include <asm/byteorder.h>
  52 #include <asm/uaccess.h>
  53
  54 #ifdef CONFIG_SPARC
  55 #include <asm/idprom.h>
  56 #include <asm/prom.h>
  57 #endif
  58
  59 #define BAR_0   0
  60 #define BAR_2   2
  61
  62 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  63 #define TG3_VLAN_TAG_USED 1
  64 #else
  65 #define TG3_VLAN_TAG_USED 0
  66 #endif
  67
  68 #include "tg3.h"
  69
  70 #define DRV_MODULE_NAME         "tg3"
  71 #define TG3_MAJ_NUM                     3
  72 #define TG3_MIN_NUM                     111
  73 #define DRV_MODULE_VERSION      \
  74         __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
  75 #define DRV_MODULE_RELDATE      "June 5, 2010"
  76
  77 #define TG3_DEF_MAC_MODE        0
  78 #define TG3_DEF_RX_MODE         0
  79 #define TG3_DEF_TX_MODE         0
  80 #define TG3_DEF_MSG_ENABLE        \
  81         (NETIF_MSG_DRV          | \
  82          NETIF_MSG_PROBE        | \
  83          NETIF_MSG_LINK         | \
  84          NETIF_MSG_TIMER        | \
  85          NETIF_MSG_IFDOWN       | \
  86          NETIF_MSG_IFUP         | \
  87          NETIF_MSG_RX_ERR       | \
  88          NETIF_MSG_TX_ERR)
  89
  90 /* length of time before we decide the hardware is borked,
  91  * and dev->tx_timeout() should be called to fix the problem
  92  */
  93 #define TG3_TX_TIMEOUT                  (5 * HZ)
  94
  95 /* hardware minimum and maximum for a single frame's data payload */
  96 #define TG3_MIN_MTU                     60
  97 #define TG3_MAX_MTU(tp) \
  98         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  99
 100 /* These numbers seem to be hard coded in the NIC firmware somehow.
 101  * You can't change the ring sizes, but you can change where you place
 102  * them in the NIC onboard memory.
 103  */
 104 #define TG3_RX_RING_SIZE                512
 105 #define TG3_DEF_RX_RING_PENDING         200
 106 #define TG3_RX_JUMBO_RING_SIZE          256
 107 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 108 #define TG3_RSS_INDIR_TBL_SIZE          128
 109
 110 /* Do not place this n-ring entries value into the tp struct itself,
 111  * we really want to expose these constants to GCC so that modulo et
 112  * al.  operations are done with shifts and masks instead of with
 113  * hw multiply/modulo instructions.  Another solution would be to
 114  * replace things like '% foo' with '& (foo - 1)'.
 115  */
 116 #define TG3_RX_RCB_RING_SIZE(tp)        \
 117         (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
 118           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
 119
 120 #define TG3_TX_RING_SIZE                512
 121 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 122
 123 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 124                                  TG3_RX_RING_SIZE)
 125 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
 126                                  TG3_RX_JUMBO_RING_SIZE)
 127 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 128                                  TG3_RX_RCB_RING_SIZE(tp))
 129 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 130                                  TG3_TX_RING_SIZE)
 131 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 132
 133 #define TG3_RX_DMA_ALIGN                16
 134 #define TG3_RX_HEADROOM                 ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
 135
 136 #define TG3_DMA_BYTE_ENAB               64
 137
 138 #define TG3_RX_STD_DMA_SZ               1536
 139 #define TG3_RX_JMB_DMA_SZ               9046
 140
 141 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 142
 143 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 144 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 145
 146 #define TG3_RX_STD_BUFF_RING_SIZE \
 147         (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
 148
 149 #define TG3_RX_JMB_BUFF_RING_SIZE \
 150         (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
 151
 152 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
 153  * that are at least dword aligned when used in PCIX mode.  The driver
 154  * works around this bug by double copying the packet.  This workaround
 155  * is built into the normal double copy length check for efficiency.
 156  *
 157  * However, the double copy is only necessary on those architectures
 158  * where unaligned memory accesses are inefficient.  For those architectures
 159  * where unaligned memory accesses incur little penalty, we can reintegrate
 160  * the 5701 in the normal rx path.  Doing so saves a device structure
 161  * dereference by hardcoding the double copy threshold in place.
 162  */
 163 #define TG3_RX_COPY_THRESHOLD           256
 164 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
 165         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
 166 #else
 167         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
 168 #endif
 169
 170 /* minimum number of free TX descriptors required to wake up TX process */
 171 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 172
 173 #define TG3_RAW_IP_ALIGN 2
 174
 175 /* number of ETHTOOL_GSTATS u64's */
 176 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 177
 178 #define TG3_NUM_TEST            6
 179
 180 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
 181
 182 #define FIRMWARE_TG3            "tigon/tg3.bin"
 183 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 184 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 185
 186 static char version[] __devinitdata =
 187         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
 188
 189 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 190 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 191 MODULE_LICENSE("GPL");
 192 MODULE_VERSION(DRV_MODULE_VERSION);
 193 MODULE_FIRMWARE(FIRMWARE_TG3);
 194 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 195 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 196
 197 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 198 module_param(tg3_debug, int, 0);
 199 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 200
 201 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 255         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 256         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 257         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 258         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 259         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 260         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 261         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 262         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 263         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 264         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 265         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 266         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 267         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 268         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
 269         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
 270         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
 271         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
 272         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
 273         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
 274         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
 275         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
 276         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
 277         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
 278         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 279         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 280         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 281         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 282         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 283         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 284         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 285         {}
 286 };
 287
 288 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 289
 290 static const struct {
 291         const char string[ETH_GSTRING_LEN];
 292 } ethtool_stats_keys[TG3_NUM_STATS] = {
 293         { "rx_octets" },
 294         { "rx_fragments" },
 295         { "rx_ucast_packets" },
 296         { "rx_mcast_packets" },
 297         { "rx_bcast_packets" },
 298         { "rx_fcs_errors" },
 299         { "rx_align_errors" },
 300         { "rx_xon_pause_rcvd" },
 301         { "rx_xoff_pause_rcvd" },
 302         { "rx_mac_ctrl_rcvd" },
 303         { "rx_xoff_entered" },
 304         { "rx_frame_too_long_errors" },
 305         { "rx_jabbers" },
 306         { "rx_undersize_packets" },
 307         { "rx_in_length_errors" },
 308         { "rx_out_length_errors" },
 309         { "rx_64_or_less_octet_packets" },
 310         { "rx_65_to_127_octet_packets" },
 311         { "rx_128_to_255_octet_packets" },
 312         { "rx_256_to_511_octet_packets" },
 313         { "rx_512_to_1023_octet_packets" },
 314         { "rx_1024_to_1522_octet_packets" },
 315         { "rx_1523_to_2047_octet_packets" },
 316         { "rx_2048_to_4095_octet_packets" },
 317         { "rx_4096_to_8191_octet_packets" },
 318         { "rx_8192_to_9022_octet_packets" },
 319
 320         { "tx_octets" },
 321         { "tx_collisions" },
 322
 323         { "tx_xon_sent" },
 324         { "tx_xoff_sent" },
 325         { "tx_flow_control" },
 326         { "tx_mac_errors" },
 327         { "tx_single_collisions" },
 328         { "tx_mult_collisions" },
 329         { "tx_deferred" },
 330         { "tx_excessive_collisions" },
 331         { "tx_late_collisions" },
 332         { "tx_collide_2times" },
 333         { "tx_collide_3times" },
 334         { "tx_collide_4times" },
 335         { "tx_collide_5times" },
 336         { "tx_collide_6times" },
 337         { "tx_collide_7times" },
 338         { "tx_collide_8times" },
 339         { "tx_collide_9times" },
 340         { "tx_collide_10times" },
 341         { "tx_collide_11times" },
 342         { "tx_collide_12times" },
 343         { "tx_collide_13times" },
 344         { "tx_collide_14times" },
 345         { "tx_collide_15times" },
 346         { "tx_ucast_packets" },
 347         { "tx_mcast_packets" },
 348         { "tx_bcast_packets" },
 349         { "tx_carrier_sense_errors" },
 350         { "tx_discards" },
 351         { "tx_errors" },
 352
 353         { "dma_writeq_full" },
 354         { "dma_write_prioq_full" },
 355         { "rxbds_empty" },
 356         { "rx_discards" },
 357         { "rx_errors" },
 358         { "rx_threshold_hit" },
 359
 360         { "dma_readq_full" },
 361         { "dma_read_prioq_full" },
 362         { "tx_comp_queue_full" },
 363
 364         { "ring_set_send_prod_index" },
 365         { "ring_status_update" },
 366         { "nic_irqs" },
 367         { "nic_avoided_irqs" },
 368         { "nic_tx_threshold_hit" }
 369 };
 370
 371 static const struct {
 372         const char string[ETH_GSTRING_LEN];
 373 } ethtool_test_keys[TG3_NUM_TEST] = {
 374         { "nvram test     (online) " },
 375         { "link test      (online) " },
 376         { "register test  (offline)" },
 377         { "memory test    (offline)" },
 378         { "loopback test  (offline)" },
 379         { "interrupt test (offline)" },
 380 };
 381
 382 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 383 {
 384         writel(val, tp->regs + off);
 385 }
 386
 387 static u32 tg3_read32(struct tg3 *tp, u32 off)
 388 {
 389         return readl(tp->regs + off);
 390 }
 391
 392 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 393 {
 394         writel(val, tp->aperegs + off);
 395 }
 396
 397 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 398 {
 399         return readl(tp->aperegs + off);
 400 }
 401
 402 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 403 {
 404         unsigned long flags;
 405
 406         spin_lock_irqsave(&tp->indirect_lock, flags);
 407         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 408         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 409         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 410 }
 411
 412 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 413 {
 414         writel(val, tp->regs + off);
 415         readl(tp->regs + off);
 416 }
 417
 418 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 419 {
 420         unsigned long flags;
 421         u32 val;
 422
 423         spin_lock_irqsave(&tp->indirect_lock, flags);
 424         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 425         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 426         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 427         return val;
 428 }
 429
 430 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 431 {
 432         unsigned long flags;
 433
 434         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 435                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 436                                        TG3_64BIT_REG_LOW, val);
 437                 return;
 438         }
 439         if (off == TG3_RX_STD_PROD_IDX_REG) {
 440                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 441                                        TG3_64BIT_REG_LOW, val);
 442                 return;
 443         }
 444
 445         spin_lock_irqsave(&tp->indirect_lock, flags);
 446         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 447         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 448         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 449
 450         /* In indirect mode when disabling interrupts, we also need
 451          * to clear the interrupt bit in the GRC local ctrl register.
 452          */
 453         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 454             (val == 0x1)) {
 455                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 456                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 457         }
 458 }
 459
 460 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 461 {
 462         unsigned long flags;
 463         u32 val;
 464
 465         spin_lock_irqsave(&tp->indirect_lock, flags);
 466         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 467         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 468         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 469         return val;
 470 }
 471
 472 /* usec_wait specifies the wait time in usec when writing to certain registers
 473  * where it is unsafe to read back the register without some delay.
 474  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 475  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 476  */
 477 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 478 {
 479         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 480             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 481                 /* Non-posted methods */
 482                 tp->write32(tp, off, val);
 483         else {
 484                 /* Posted method */
 485                 tg3_write32(tp, off, val);
 486                 if (usec_wait)
 487                         udelay(usec_wait);
 488                 tp->read32(tp, off);
 489         }
 490         /* Wait again after the read for the posted method to guarantee that
 491          * the wait time is met.
 492          */
 493         if (usec_wait)
 494                 udelay(usec_wait);
 495 }
 496
 497 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 498 {
 499         tp->write32_mbox(tp, off, val);
 500         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 501             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 502                 tp->read32_mbox(tp, off);
 503 }
 504
 505 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 506 {
 507         void __iomem *mbox = tp->regs + off;
 508         writel(val, mbox);
 509         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 510                 writel(val, mbox);
 511         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 512                 readl(mbox);
 513 }
 514
 515 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 516 {
 517         return readl(tp->regs + off + GRCMBOX_BASE);
 518 }
 519
 520 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 521 {
 522         writel(val, tp->regs + off + GRCMBOX_BASE);
 523 }
 524
 525 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
 526 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 527 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
 528 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
 529 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
 530
 531 #define tw32(reg, val)                  tp->write32(tp, reg, val)
 532 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
 533 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
 534 #define tr32(reg)                       tp->read32(tp, reg)
 535
 536 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 537 {
 538         unsigned long flags;
 539
 540         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 541             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 542                 return;
 543
 544         spin_lock_irqsave(&tp->indirect_lock, flags);
 545         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 546                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 547                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 548
 549                 /* Always leave this as zero. */
 550                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 551         } else {
 552                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 553                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 554
 555                 /* Always leave this as zero. */
 556                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 557         }
 558         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 559 }
 560
 561 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 562 {
 563         unsigned long flags;
 564
 565         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 566             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 567                 *val = 0;
 568                 return;
 569         }
 570
 571         spin_lock_irqsave(&tp->indirect_lock, flags);
 572         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 573                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 574                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 575
 576                 /* Always leave this as zero. */
 577                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 578         } else {
 579                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 580                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 581
 582                 /* Always leave this as zero. */
 583                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 584         }
 585         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 586 }
 587
 588 static void tg3_ape_lock_init(struct tg3 *tp)
 589 {
 590         int i;
 591         u32 regbase;
 592
 593         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 594                 regbase = TG3_APE_LOCK_GRANT;
 595         else
 596                 regbase = TG3_APE_PER_LOCK_GRANT;
 597
 598         /* Make sure the driver hasn't any stale locks. */
 599         for (i = 0; i < 8; i++)
 600                 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
 601 }
 602
 603 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 604 {
 605         int i, off;
 606         int ret = 0;
 607         u32 status, req, gnt;
 608
 609         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 610                 return 0;
 611
 612         switch (locknum) {
 613         case TG3_APE_LOCK_GRC:
 614         case TG3_APE_LOCK_MEM:
 615                 break;
 616         default:
 617                 return -EINVAL;
 618         }
 619
 620         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
 621                 req = TG3_APE_LOCK_REQ;
 622                 gnt = TG3_APE_LOCK_GRANT;
 623         } else {
 624                 req = TG3_APE_PER_LOCK_REQ;
 625                 gnt = TG3_APE_PER_LOCK_GRANT;
 626         }
 627
 628         off = 4 * locknum;
 629
 630         tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
 631
 632         /* Wait for up to 1 millisecond to acquire lock. */
 633         for (i = 0; i < 100; i++) {
 634                 status = tg3_ape_read32(tp, gnt + off);
 635                 if (status == APE_LOCK_GRANT_DRIVER)
 636                         break;
 637                 udelay(10);
 638         }
 639
 640         if (status != APE_LOCK_GRANT_DRIVER) {
 641                 /* Revoke the lock request. */
 642                 tg3_ape_write32(tp, gnt + off,
 643                                 APE_LOCK_GRANT_DRIVER);
 644
 645                 ret = -EBUSY;
 646         }
 647
 648         return ret;
 649 }
 650
 651 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 652 {
 653         u32 gnt;
 654
 655         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 656                 return;
 657
 658         switch (locknum) {
 659         case TG3_APE_LOCK_GRC:
 660         case TG3_APE_LOCK_MEM:
 661                 break;
 662         default:
 663                 return;
 664         }
 665
 666         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 667                 gnt = TG3_APE_LOCK_GRANT;
 668         else
 669                 gnt = TG3_APE_PER_LOCK_GRANT;
 670
 671         tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
 672 }
 673
 674 static void tg3_disable_ints(struct tg3 *tp)
 675 {
 676         int i;
 677
 678         tw32(TG3PCI_MISC_HOST_CTRL,
 679              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 680         for (i = 0; i < tp->irq_max; i++)
 681                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 682 }
 683
 684 static void tg3_enable_ints(struct tg3 *tp)
 685 {
 686         int i;
 687
 688         tp->irq_sync = 0;
 689         wmb();
 690
 691         tw32(TG3PCI_MISC_HOST_CTRL,
 692              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 693
 694         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
 695         for (i = 0; i < tp->irq_cnt; i++) {
 696                 struct tg3_napi *tnapi = &tp->napi[i];
 697
 698                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 699                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 700                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 701
 702                 tp->coal_now |= tnapi->coal_now;
 703         }
 704
 705         /* Force an initial interrupt */
 706         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 707             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 708                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 709         else
 710                 tw32(HOSTCC_MODE, tp->coal_now);
 711
 712         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
 713 }
 714
 715 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 716 {
 717         struct tg3 *tp = tnapi->tp;
 718         struct tg3_hw_status *sblk = tnapi->hw_status;
 719         unsigned int work_exists = 0;
 720
 721         /* check for phy events */
 722         if (!(tp->tg3_flags &
 723               (TG3_FLAG_USE_LINKCHG_REG |
 724                TG3_FLAG_POLL_SERDES))) {
 725                 if (sblk->status & SD_STATUS_LINK_CHG)
 726                         work_exists = 1;
 727         }
 728         /* check for RX/TX work to do */
 729         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 730             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
 731                 work_exists = 1;
 732
 733         return work_exists;
 734 }
 735
 736 /* tg3_int_reenable
 737  *  similar to tg3_enable_ints, but it accurately determines whether there
 738  *  is new work pending and can return without flushing the PIO write
 739  *  which reenables interrupts
 740  */
 741 static void tg3_int_reenable(struct tg3_napi *tnapi)
 742 {
 743         struct tg3 *tp = tnapi->tp;
 744
 745         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 746         mmiowb();
 747
 748         /* When doing tagged status, this work check is unnecessary.
 749          * The last_tag we write above tells the chip which piece of
 750          * work we've completed.
 751          */
 752         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 753             tg3_has_work(tnapi))
 754                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 755                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 756 }
 757
 758 static void tg3_napi_disable(struct tg3 *tp)
 759 {
 760         int i;
 761
 762         for (i = tp->irq_cnt - 1; i >= 0; i--)
 763                 napi_disable(&tp->napi[i].napi);
 764 }
 765
 766 static void tg3_napi_enable(struct tg3 *tp)
 767 {
 768         int i;
 769
 770         for (i = 0; i < tp->irq_cnt; i++)
 771                 napi_enable(&tp->napi[i].napi);
 772 }
 773
 774 static inline void tg3_netif_stop(struct tg3 *tp)
 775 {
 776         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 777         tg3_napi_disable(tp);
 778         netif_tx_disable(tp->dev);
 779 }
 780
 781 static inline void tg3_netif_start(struct tg3 *tp)
 782 {
 783         /* NOTE: unconditional netif_tx_wake_all_queues is only
 784          * appropriate so long as all callers are assured to
 785          * have free tx slots (such as after tg3_init_hw)
 786          */
 787         netif_tx_wake_all_queues(tp->dev);
 788
 789         tg3_napi_enable(tp);
 790         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
 791         tg3_enable_ints(tp);
 792 }
 793
 794 static void tg3_switch_clocks(struct tg3 *tp)
 795 {
 796         u32 clock_ctrl;
 797         u32 orig_clock_ctrl;
 798
 799         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 800             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 801                 return;
 802
 803         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 804
 805         orig_clock_ctrl = clock_ctrl;
 806         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 807                        CLOCK_CTRL_CLKRUN_OENABLE |
 808                        0x1f);
 809         tp->pci_clock_ctrl = clock_ctrl;
 810
 811         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 812                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 813                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 814                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 815                 }
 816         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 817                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 818                             clock_ctrl |
 819                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 820                             40);
 821                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 822                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 823                             40);
 824         }
 825         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 826 }
 827
 828 #define PHY_BUSY_LOOPS  5000
 829
 830 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 831 {
 832         u32 frame_val;
 833         unsigned int loops;
 834         int ret;
 835
 836         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 837                 tw32_f(MAC_MI_MODE,
 838                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 839                 udelay(80);
 840         }
 841
 842         *val = 0x0;
 843
 844         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 845                       MI_COM_PHY_ADDR_MASK);
 846         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 847                       MI_COM_REG_ADDR_MASK);
 848         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 849
 850         tw32_f(MAC_MI_COM, frame_val);
 851
 852         loops = PHY_BUSY_LOOPS;
 853         while (loops != 0) {
 854                 udelay(10);
 855                 frame_val = tr32(MAC_MI_COM);
 856
 857                 if ((frame_val & MI_COM_BUSY) == 0) {
 858                         udelay(5);
 859                         frame_val = tr32(MAC_MI_COM);
 860                         break;
 861                 }
 862                 loops -= 1;
 863         }
 864
 865         ret = -EBUSY;
 866         if (loops != 0) {
 867                 *val = frame_val & MI_COM_DATA_MASK;
 868                 ret = 0;
 869         }
 870
 871         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 872                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 873                 udelay(80);
 874         }
 875
 876         return ret;
 877 }
 878
 879 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 880 {
 881         u32 frame_val;
 882         unsigned int loops;
 883         int ret;
 884
 885         if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
 886             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 887                 return 0;
 888
 889         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 890                 tw32_f(MAC_MI_MODE,
 891                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 892                 udelay(80);
 893         }
 894
 895         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 896                       MI_COM_PHY_ADDR_MASK);
 897         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 898                       MI_COM_REG_ADDR_MASK);
 899         frame_val |= (val & MI_COM_DATA_MASK);
 900         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 901
 902         tw32_f(MAC_MI_COM, frame_val);
 903
 904         loops = PHY_BUSY_LOOPS;
 905         while (loops != 0) {
 906                 udelay(10);
 907                 frame_val = tr32(MAC_MI_COM);
 908                 if ((frame_val & MI_COM_BUSY) == 0) {
 909                         udelay(5);
 910                         frame_val = tr32(MAC_MI_COM);
 911                         break;
 912                 }
 913                 loops -= 1;
 914         }
 915
 916         ret = -EBUSY;
 917         if (loops != 0)
 918                 ret = 0;
 919
 920         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 921                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 922                 udelay(80);
 923         }
 924
 925         return ret;
 926 }
 927
 928 static int tg3_bmcr_reset(struct tg3 *tp)
 929 {
 930         u32 phy_control;
 931         int limit, err;
 932
 933         /* OK, reset it, and poll the BMCR_RESET bit until it
 934          * clears or we time out.
 935          */
 936         phy_control = BMCR_RESET;
 937         err = tg3_writephy(tp, MII_BMCR, phy_control);
 938         if (err != 0)
 939                 return -EBUSY;
 940
 941         limit = 5000;
 942         while (limit--) {
 943                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 944                 if (err != 0)
 945                         return -EBUSY;
 946
 947                 if ((phy_control & BMCR_RESET) == 0) {
 948                         udelay(40);
 949                         break;
 950                 }
 951                 udelay(10);
 952         }
 953         if (limit < 0)
 954                 return -EBUSY;
 955
 956         return 0;
 957 }
 958
 959 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 960 {
 961         struct tg3 *tp = bp->priv;
 962         u32 val;
 963
 964         spin_lock_bh(&tp->lock);
 965
 966         if (tg3_readphy(tp, reg, &val))
 967                 val = -EIO;
 968
 969         spin_unlock_bh(&tp->lock);
 970
 971         return val;
 972 }
 973
 974 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 975 {
 976         struct tg3 *tp = bp->priv;
 977         u32 ret = 0;
 978
 979         spin_lock_bh(&tp->lock);
 980
 981         if (tg3_writephy(tp, reg, val))
 982                 ret = -EIO;
 983
 984         spin_unlock_bh(&tp->lock);
 985
 986         return ret;
 987 }
 988
 989 static int tg3_mdio_reset(struct mii_bus *bp)
 990 {
 991         return 0;
 992 }
 993
 994 static void tg3_mdio_config_5785(struct tg3 *tp)
 995 {
 996         u32 val;
 997         struct phy_device *phydev;
 998
 999         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1000         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1001         case PHY_ID_BCM50610:
1002         case PHY_ID_BCM50610M:
1003                 val = MAC_PHYCFG2_50610_LED_MODES;
1004                 break;
1005         case PHY_ID_BCMAC131:
1006                 val = MAC_PHYCFG2_AC131_LED_MODES;
1007                 break;
1008         case PHY_ID_RTL8211C:
1009                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1010                 break;
1011         case PHY_ID_RTL8201E:
1012                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1013                 break;
1014         default:
1015                 return;
1016         }
1017
1018         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1019                 tw32(MAC_PHYCFG2, val);
1020
1021                 val = tr32(MAC_PHYCFG1);
1022                 val &= ~(MAC_PHYCFG1_RGMII_INT |
1023                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1024                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1025                 tw32(MAC_PHYCFG1, val);
1026
1027                 return;
1028         }
1029
1030         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
1031                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1032                        MAC_PHYCFG2_FMODE_MASK_MASK |
1033                        MAC_PHYCFG2_GMODE_MASK_MASK |
1034                        MAC_PHYCFG2_ACT_MASK_MASK   |
1035                        MAC_PHYCFG2_QUAL_MASK_MASK |
1036                        MAC_PHYCFG2_INBAND_ENABLE;
1037
1038         tw32(MAC_PHYCFG2, val);
1039
1040         val = tr32(MAC_PHYCFG1);
1041         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1042                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1043         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1044                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1045                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1046                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1047                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1048         }
1049         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1050                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1051         tw32(MAC_PHYCFG1, val);
1052
1053         val = tr32(MAC_EXT_RGMII_MODE);
1054         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1055                  MAC_RGMII_MODE_RX_QUALITY |
1056                  MAC_RGMII_MODE_RX_ACTIVITY |
1057                  MAC_RGMII_MODE_RX_ENG_DET |
1058                  MAC_RGMII_MODE_TX_ENABLE |
1059                  MAC_RGMII_MODE_TX_LOWPWR |
1060                  MAC_RGMII_MODE_TX_RESET);
1061         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1062                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1063                         val |= MAC_RGMII_MODE_RX_INT_B |
1064                                MAC_RGMII_MODE_RX_QUALITY |
1065                                MAC_RGMII_MODE_RX_ACTIVITY |
1066                                MAC_RGMII_MODE_RX_ENG_DET;
1067                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1068                         val |= MAC_RGMII_MODE_TX_ENABLE |
1069                                MAC_RGMII_MODE_TX_LOWPWR |
1070                                MAC_RGMII_MODE_TX_RESET;
1071         }
1072         tw32(MAC_EXT_RGMII_MODE, val);
1073 }
1074
1075 static void tg3_mdio_start(struct tg3 *tp)
1076 {
1077         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1078         tw32_f(MAC_MI_MODE, tp->mi_mode);
1079         udelay(80);
1080
1081         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1082             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1083                 tg3_mdio_config_5785(tp);
1084 }
1085
1086 static int tg3_mdio_init(struct tg3 *tp)
1087 {
1088         int i;
1089         u32 reg;
1090         struct phy_device *phydev;
1091
1092         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1093             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
1094                 u32 is_serdes;
1095
1096                 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1097
1098                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1099                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1100                 else
1101                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1102                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1103                 if (is_serdes)
1104                         tp->phy_addr += 7;
1105         } else
1106                 tp->phy_addr = TG3_PHY_MII_ADDR;
1107
1108         tg3_mdio_start(tp);
1109
1110         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1111             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1112                 return 0;
1113
1114         tp->mdio_bus = mdiobus_alloc();
1115         if (tp->mdio_bus == NULL)
1116                 return -ENOMEM;
1117
1118         tp->mdio_bus->name     = "tg3 mdio bus";
1119         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1120                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1121         tp->mdio_bus->priv     = tp;
1122         tp->mdio_bus->parent   = &tp->pdev->dev;
1123         tp->mdio_bus->read     = &tg3_mdio_read;
1124         tp->mdio_bus->write    = &tg3_mdio_write;
1125         tp->mdio_bus->reset    = &tg3_mdio_reset;
1126         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1127         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1128
1129         for (i = 0; i < PHY_MAX_ADDR; i++)
1130                 tp->mdio_bus->irq[i] = PHY_POLL;
1131
1132         /* The bus registration will look for all the PHYs on the mdio bus.
1133          * Unfortunately, it does not ensure the PHY is powered up before
1134          * accessing the PHY ID registers.  A chip reset is the
1135          * quickest way to bring the device back to an operational state..
1136          */
1137         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1138                 tg3_bmcr_reset(tp);
1139
1140         i = mdiobus_register(tp->mdio_bus);
1141         if (i) {
1142                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1143                 mdiobus_free(tp->mdio_bus);
1144                 return i;
1145         }
1146
1147         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1148
1149         if (!phydev || !phydev->drv) {
1150                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1151                 mdiobus_unregister(tp->mdio_bus);
1152                 mdiobus_free(tp->mdio_bus);
1153                 return -ENODEV;
1154         }
1155
1156         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1157         case PHY_ID_BCM57780:
1158                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1159                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1160                 break;
1161         case PHY_ID_BCM50610:
1162         case PHY_ID_BCM50610M:
1163                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1164                                      PHY_BRCM_RX_REFCLK_UNUSED |
1165                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1166                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1167                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1168                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1169                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1170                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1171                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1172                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1173                 /* fallthru */
1174         case PHY_ID_RTL8211C:
1175                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1176                 break;
1177         case PHY_ID_RTL8201E:
1178         case PHY_ID_BCMAC131:
1179                 phydev->interface = PHY_INTERFACE_MODE_MII;
1180                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1181                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1182                 break;
1183         }
1184
1185         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1186
1187         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1188                 tg3_mdio_config_5785(tp);
1189
1190         return 0;
1191 }
1192
1193 static void tg3_mdio_fini(struct tg3 *tp)
1194 {
1195         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1196                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1197                 mdiobus_unregister(tp->mdio_bus);
1198                 mdiobus_free(tp->mdio_bus);
1199         }
1200 }
1201
1202 /* tp->lock is held. */
1203 static inline void tg3_generate_fw_event(struct tg3 *tp)
1204 {
1205         u32 val;
1206
1207         val = tr32(GRC_RX_CPU_EVENT);
1208         val |= GRC_RX_CPU_DRIVER_EVENT;
1209         tw32_f(GRC_RX_CPU_EVENT, val);
1210
1211         tp->last_event_jiffies = jiffies;
1212 }
1213
1214 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1215
1216 /* tp->lock is held. */
1217 static void tg3_wait_for_event_ack(struct tg3 *tp)
1218 {
1219         int i;
1220         unsigned int delay_cnt;
1221         long time_remain;
1222
1223         /* If enough time has passed, no wait is necessary. */
1224         time_remain = (long)(tp->last_event_jiffies + 1 +
1225                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1226                       (long)jiffies;
1227         if (time_remain < 0)
1228                 return;
1229
1230         /* Check if we can shorten the wait time. */
1231         delay_cnt = jiffies_to_usecs(time_remain);
1232         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1233                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1234         delay_cnt = (delay_cnt >> 3) + 1;
1235
1236         for (i = 0; i < delay_cnt; i++) {
1237                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1238                         break;
1239                 udelay(8);
1240         }
1241 }
1242
1243 /* tp->lock is held. */
1244 static void tg3_ump_link_report(struct tg3 *tp)
1245 {
1246         u32 reg;
1247         u32 val;
1248
1249         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1250             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1251                 return;
1252
1253         tg3_wait_for_event_ack(tp);
1254
1255         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1256
1257         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1258
1259         val = 0;
1260         if (!tg3_readphy(tp, MII_BMCR, &reg))
1261                 val = reg << 16;
1262         if (!tg3_readphy(tp, MII_BMSR, &reg))
1263                 val |= (reg & 0xffff);
1264         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1265
1266         val = 0;
1267         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1268                 val = reg << 16;
1269         if (!tg3_readphy(tp, MII_LPA, &reg))
1270                 val |= (reg & 0xffff);
1271         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1272
1273         val = 0;
1274         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1275                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1276                         val = reg << 16;
1277                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1278                         val |= (reg & 0xffff);
1279         }
1280         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1281
1282         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1283                 val = reg << 16;
1284         else
1285                 val = 0;
1286         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1287
1288         tg3_generate_fw_event(tp);
1289 }
1290
1291 static void tg3_link_report(struct tg3 *tp)
1292 {
1293         if (!netif_carrier_ok(tp->dev)) {
1294                 netif_info(tp, link, tp->dev, "Link is down\n");
1295                 tg3_ump_link_report(tp);
1296         } else if (netif_msg_link(tp)) {
1297                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1298                             (tp->link_config.active_speed == SPEED_1000 ?
1299                              1000 :
1300                              (tp->link_config.active_speed == SPEED_100 ?
1301                               100 : 10)),
1302                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1303                              "full" : "half"));
1304
1305                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1306                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1307                             "on" : "off",
1308                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1309                             "on" : "off");
1310                 tg3_ump_link_report(tp);
1311         }
1312 }
1313
1314 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1315 {
1316         u16 miireg;
1317
1318         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1319                 miireg = ADVERTISE_PAUSE_CAP;
1320         else if (flow_ctrl & FLOW_CTRL_TX)
1321                 miireg = ADVERTISE_PAUSE_ASYM;
1322         else if (flow_ctrl & FLOW_CTRL_RX)
1323                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1324         else
1325                 miireg = 0;
1326
1327         return miireg;
1328 }
1329
1330 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1331 {
1332         u16 miireg;
1333
1334         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1335                 miireg = ADVERTISE_1000XPAUSE;
1336         else if (flow_ctrl & FLOW_CTRL_TX)
1337                 miireg = ADVERTISE_1000XPSE_ASYM;
1338         else if (flow_ctrl & FLOW_CTRL_RX)
1339                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1340         else
1341                 miireg = 0;
1342
1343         return miireg;
1344 }
1345
1346 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1347 {
1348         u8 cap = 0;
1349
1350         if (lcladv & ADVERTISE_1000XPAUSE) {
1351                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1352                         if (rmtadv & LPA_1000XPAUSE)
1353                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1354                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1355                                 cap = FLOW_CTRL_RX;
1356                 } else {
1357                         if (rmtadv & LPA_1000XPAUSE)
1358                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1359                 }
1360         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1361                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1362                         cap = FLOW_CTRL_TX;
1363         }
1364
1365         return cap;
1366 }
1367
1368 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1369 {
1370         u8 autoneg;
1371         u8 flowctrl = 0;
1372         u32 old_rx_mode = tp->rx_mode;
1373         u32 old_tx_mode = tp->tx_mode;
1374
1375         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1376                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1377         else
1378                 autoneg = tp->link_config.autoneg;
1379
1380         if (autoneg == AUTONEG_ENABLE &&
1381             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1382                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1383                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1384                 else
1385                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1386         } else
1387                 flowctrl = tp->link_config.flowctrl;
1388
1389         tp->link_config.active_flowctrl = flowctrl;
1390
1391         if (flowctrl & FLOW_CTRL_RX)
1392                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1393         else
1394                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1395
1396         if (old_rx_mode != tp->rx_mode)
1397                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1398
1399         if (flowctrl & FLOW_CTRL_TX)
1400                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1401         else
1402                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1403
1404         if (old_tx_mode != tp->tx_mode)
1405                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1406 }
1407
1408 static void tg3_adjust_link(struct net_device *dev)
1409 {
1410         u8 oldflowctrl, linkmesg = 0;
1411         u32 mac_mode, lcl_adv, rmt_adv;
1412         struct tg3 *tp = netdev_priv(dev);
1413         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1414
1415         spin_lock_bh(&tp->lock);
1416
1417         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1418                                     MAC_MODE_HALF_DUPLEX);
1419
1420         oldflowctrl = tp->link_config.active_flowctrl;
1421
1422         if (phydev->link) {
1423                 lcl_adv = 0;
1424                 rmt_adv = 0;
1425
1426                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1427                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1428                 else if (phydev->speed == SPEED_1000 ||
1429                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1430                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1431                 else
1432                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1433
1434                 if (phydev->duplex == DUPLEX_HALF)
1435                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1436                 else {
1437                         lcl_adv = tg3_advert_flowctrl_1000T(
1438                                   tp->link_config.flowctrl);
1439
1440                         if (phydev->pause)
1441                                 rmt_adv = LPA_PAUSE_CAP;
1442                         if (phydev->asym_pause)
1443                                 rmt_adv |= LPA_PAUSE_ASYM;
1444                 }
1445
1446                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1447         } else
1448                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1449
1450         if (mac_mode != tp->mac_mode) {
1451                 tp->mac_mode = mac_mode;
1452                 tw32_f(MAC_MODE, tp->mac_mode);
1453                 udelay(40);
1454         }
1455
1456         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1457                 if (phydev->speed == SPEED_10)
1458                         tw32(MAC_MI_STAT,
1459                              MAC_MI_STAT_10MBPS_MODE |
1460                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1461                 else
1462                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1463         }
1464
1465         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1466                 tw32(MAC_TX_LENGTHS,
1467                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1468                       (6 << TX_LENGTHS_IPG_SHIFT) |
1469                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1470         else
1471                 tw32(MAC_TX_LENGTHS,
1472                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1473                       (6 << TX_LENGTHS_IPG_SHIFT) |
1474                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1475
1476         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1477             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1478             phydev->speed != tp->link_config.active_speed ||
1479             phydev->duplex != tp->link_config.active_duplex ||
1480             oldflowctrl != tp->link_config.active_flowctrl)
1481                 linkmesg = 1;
1482
1483         tp->link_config.active_speed = phydev->speed;
1484         tp->link_config.active_duplex = phydev->duplex;
1485
1486         spin_unlock_bh(&tp->lock);
1487
1488         if (linkmesg)
1489                 tg3_link_report(tp);
1490 }
1491
1492 static int tg3_phy_init(struct tg3 *tp)
1493 {
1494         struct phy_device *phydev;
1495
1496         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1497                 return 0;
1498
1499         /* Bring the PHY back to a known state. */
1500         tg3_bmcr_reset(tp);
1501
1502         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1503
1504         /* Attach the MAC to the PHY. */
1505         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1506                              phydev->dev_flags, phydev->interface);
1507         if (IS_ERR(phydev)) {
1508                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1509                 return PTR_ERR(phydev);
1510         }
1511
1512         /* Mask with MAC supported features. */
1513         switch (phydev->interface) {
1514         case PHY_INTERFACE_MODE_GMII:
1515         case PHY_INTERFACE_MODE_RGMII:
1516                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1517                         phydev->supported &= (PHY_GBIT_FEATURES |
1518                                               SUPPORTED_Pause |
1519                                               SUPPORTED_Asym_Pause);
1520                         break;
1521                 }
1522                 /* fallthru */
1523         case PHY_INTERFACE_MODE_MII:
1524                 phydev->supported &= (PHY_BASIC_FEATURES |
1525                                       SUPPORTED_Pause |
1526                                       SUPPORTED_Asym_Pause);
1527                 break;
1528         default:
1529                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1530                 return -EINVAL;
1531         }
1532
1533         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1534
1535         phydev->advertising = phydev->supported;
1536
1537         return 0;
1538 }
1539
1540 static void tg3_phy_start(struct tg3 *tp)
1541 {
1542         struct phy_device *phydev;
1543
1544         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1545                 return;
1546
1547         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1548
1549         if (tp->link_config.phy_is_low_power) {
1550                 tp->link_config.phy_is_low_power = 0;
1551                 phydev->speed = tp->link_config.orig_speed;
1552                 phydev->duplex = tp->link_config.orig_duplex;
1553                 phydev->autoneg = tp->link_config.orig_autoneg;
1554                 phydev->advertising = tp->link_config.orig_advertising;
1555         }
1556
1557         phy_start(phydev);
1558
1559         phy_start_aneg(phydev);
1560 }
1561
1562 static void tg3_phy_stop(struct tg3 *tp)
1563 {
1564         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1565                 return;
1566
1567         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1568 }
1569
1570 static void tg3_phy_fini(struct tg3 *tp)
1571 {
1572         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1573                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1574                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1575         }
1576 }
1577
1578 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1579 {
1580         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1581         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1582 }
1583
1584 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1585 {
1586         u32 phytest;
1587
1588         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1589                 u32 phy;
1590
1591                 tg3_writephy(tp, MII_TG3_FET_TEST,
1592                              phytest | MII_TG3_FET_SHADOW_EN);
1593                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1594                         if (enable)
1595                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1596                         else
1597                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1598                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1599                 }
1600                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1601         }
1602 }
1603
1604 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1605 {
1606         u32 reg;
1607
1608         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1609             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1610               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1611              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1612                 return;
1613
1614         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1615                 tg3_phy_fet_toggle_apd(tp, enable);
1616                 return;
1617         }
1618
1619         reg = MII_TG3_MISC_SHDW_WREN |
1620               MII_TG3_MISC_SHDW_SCR5_SEL |
1621               MII_TG3_MISC_SHDW_SCR5_LPED |
1622               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1623               MII_TG3_MISC_SHDW_SCR5_SDTL |
1624               MII_TG3_MISC_SHDW_SCR5_C125OE;
1625         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1626                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1627
1628         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1629
1630
1631         reg = MII_TG3_MISC_SHDW_WREN |
1632               MII_TG3_MISC_SHDW_APD_SEL |
1633               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1634         if (enable)
1635                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1636
1637         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1638 }
1639
1640 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1641 {
1642         u32 phy;
1643
1644         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1645             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1646                 return;
1647
1648         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1649                 u32 ephy;
1650
1651                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1652                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1653
1654                         tg3_writephy(tp, MII_TG3_FET_TEST,
1655                                      ephy | MII_TG3_FET_SHADOW_EN);
1656                         if (!tg3_readphy(tp, reg, &phy)) {
1657                                 if (enable)
1658                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1659                                 else
1660                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1661                                 tg3_writephy(tp, reg, phy);
1662                         }
1663                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1664                 }
1665         } else {
1666                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1667                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1668                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1669                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1670                         if (enable)
1671                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1672                         else
1673                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1674                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1675                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1676                 }
1677         }
1678 }
1679
1680 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1681 {
1682         u32 val;
1683
1684         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1685                 return;
1686
1687         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1688             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1689                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1690                              (val | (1 << 15) | (1 << 4)));
1691 }
1692
1693 static void tg3_phy_apply_otp(struct tg3 *tp)
1694 {
1695         u32 otp, phy;
1696
1697         if (!tp->phy_otp)
1698                 return;
1699
1700         otp = tp->phy_otp;
1701
1702         /* Enable SM_DSP clock and tx 6dB coding. */
1703         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1704               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1705               MII_TG3_AUXCTL_ACTL_TX_6DB;
1706         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1707
1708         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1709         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1710         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1711
1712         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1713               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1714         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1715
1716         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1717         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1718         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1719
1720         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1721         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1722
1723         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1724         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1725
1726         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1727               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1728         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1729
1730         /* Turn off SM_DSP clock. */
1731         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1732               MII_TG3_AUXCTL_ACTL_TX_6DB;
1733         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1734 }
1735
1736 static int tg3_wait_macro_done(struct tg3 *tp)
1737 {
1738         int limit = 100;
1739
1740         while (limit--) {
1741                 u32 tmp32;
1742
1743                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1744                         if ((tmp32 & 0x1000) == 0)
1745                                 break;
1746                 }
1747         }
1748         if (limit < 0)
1749                 return -EBUSY;
1750
1751         return 0;
1752 }
1753
1754 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1755 {
1756         static const u32 test_pat[4][6] = {
1757         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1758         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1759         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1760         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1761         };
1762         int chan;
1763
1764         for (chan = 0; chan < 4; chan++) {
1765                 int i;
1766
1767                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1768                              (chan * 0x2000) | 0x0200);
1769                 tg3_writephy(tp, 0x16, 0x0002);
1770
1771                 for (i = 0; i < 6; i++)
1772                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1773                                      test_pat[chan][i]);
1774
1775                 tg3_writephy(tp, 0x16, 0x0202);
1776                 if (tg3_wait_macro_done(tp)) {
1777                         *resetp = 1;
1778                         return -EBUSY;
1779                 }
1780
1781                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1782                              (chan * 0x2000) | 0x0200);
1783                 tg3_writephy(tp, 0x16, 0x0082);
1784                 if (tg3_wait_macro_done(tp)) {
1785                         *resetp = 1;
1786                         return -EBUSY;
1787                 }
1788
1789                 tg3_writephy(tp, 0x16, 0x0802);
1790                 if (tg3_wait_macro_done(tp)) {
1791                         *resetp = 1;
1792                         return -EBUSY;
1793                 }
1794
1795                 for (i = 0; i < 6; i += 2) {
1796                         u32 low, high;
1797
1798                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1799                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1800                             tg3_wait_macro_done(tp)) {
1801                                 *resetp = 1;
1802                                 return -EBUSY;
1803                         }
1804                         low &= 0x7fff;
1805                         high &= 0x000f;
1806                         if (low != test_pat[chan][i] ||
1807                             high != test_pat[chan][i+1]) {
1808                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1809                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1810                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1811
1812                                 return -EBUSY;
1813                         }
1814                 }
1815         }
1816
1817         return 0;
1818 }
1819
1820 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1821 {
1822         int chan;
1823
1824         for (chan = 0; chan < 4; chan++) {
1825                 int i;
1826
1827                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1828                              (chan * 0x2000) | 0x0200);
1829                 tg3_writephy(tp, 0x16, 0x0002);
1830                 for (i = 0; i < 6; i++)
1831                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1832                 tg3_writephy(tp, 0x16, 0x0202);
1833                 if (tg3_wait_macro_done(tp))
1834                         return -EBUSY;
1835         }
1836
1837         return 0;
1838 }
1839
1840 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1841 {
1842         u32 reg32, phy9_orig;
1843         int retries, do_phy_reset, err;
1844
1845         retries = 10;
1846         do_phy_reset = 1;
1847         do {
1848                 if (do_phy_reset) {
1849                         err = tg3_bmcr_reset(tp);
1850                         if (err)
1851                                 return err;
1852                         do_phy_reset = 0;
1853                 }
1854
1855                 /* Disable transmitter and interrupt.  */
1856                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1857                         continue;
1858
1859                 reg32 |= 0x3000;
1860                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1861
1862                 /* Set full-duplex, 1000 mbps.  */
1863                 tg3_writephy(tp, MII_BMCR,
1864                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1865
1866                 /* Set to master mode.  */
1867                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1868                         continue;
1869
1870                 tg3_writephy(tp, MII_TG3_CTRL,
1871                              (MII_TG3_CTRL_AS_MASTER |
1872                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1873
1874                 /* Enable SM_DSP_CLOCK and 6dB.  */
1875                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1876
1877                 /* Block the PHY control access.  */
1878                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1879                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1880
1881                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1882                 if (!err)
1883                         break;
1884         } while (--retries);
1885
1886         err = tg3_phy_reset_chanpat(tp);
1887         if (err)
1888                 return err;
1889
1890         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1891         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1892
1893         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1894         tg3_writephy(tp, 0x16, 0x0000);
1895
1896         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1897             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1898                 /* Set Extended packet length bit for jumbo frames */
1899                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1900         } else {
1901                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1902         }
1903
1904         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1905
1906         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1907                 reg32 &= ~0x3000;
1908                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1909         } else if (!err)
1910                 err = -EBUSY;
1911
1912         return err;
1913 }
1914
1915 /* This will reset the tigon3 PHY if there is no valid
1916  * link unless the FORCE argument is non-zero.
1917  */
1918 static int tg3_phy_reset(struct tg3 *tp)
1919 {
1920         u32 cpmuctrl;
1921         u32 phy_status;
1922         int err;
1923
1924         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1925                 u32 val;
1926
1927                 val = tr32(GRC_MISC_CFG);
1928                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1929                 udelay(40);
1930         }
1931         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1932         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1933         if (err != 0)
1934                 return -EBUSY;
1935
1936         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1937                 netif_carrier_off(tp->dev);
1938                 tg3_link_report(tp);
1939         }
1940
1941         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1942             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1943             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1944                 err = tg3_phy_reset_5703_4_5(tp);
1945                 if (err)
1946                         return err;
1947                 goto out;
1948         }
1949
1950         cpmuctrl = 0;
1951         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1952             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1953                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1954                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1955                         tw32(TG3_CPMU_CTRL,
1956                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1957         }
1958
1959         err = tg3_bmcr_reset(tp);
1960         if (err)
1961                 return err;
1962
1963         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1964                 u32 phy;
1965
1966                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1967                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1968
1969                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1970         }
1971
1972         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1973             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1974                 u32 val;
1975
1976                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1977                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1978                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1979                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1980                         udelay(40);
1981                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1982                 }
1983         }
1984
1985         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1986              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1987             (tp->tg3_flags2 & TG3_FLG2_MII_SERDES))
1988                 return 0;
1989
1990         tg3_phy_apply_otp(tp);
1991
1992         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1993                 tg3_phy_toggle_apd(tp, true);
1994         else
1995                 tg3_phy_toggle_apd(tp, false);
1996
1997 out:
1998         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1999                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2000                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2001                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
2002                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2003                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
2004                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2005         }
2006         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
2007                 tg3_writephy(tp, 0x1c, 0x8d68);
2008                 tg3_writephy(tp, 0x1c, 0x8d68);
2009         }
2010         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
2011                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2012                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2013                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
2014                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2015                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
2016                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
2017                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
2018                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2019         } else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
2020                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2021                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2022                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
2023                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2024                         tg3_writephy(tp, MII_TG3_TEST1,
2025                                      MII_TG3_TEST1_TRIM_EN | 0x4);
2026                 } else
2027                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2028                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2029         }
2030         /* Set Extended packet length bit (bit 14) on all chips that */
2031         /* support jumbo frames */
2032         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2033                 /* Cannot do read-modify-write on 5401 */
2034                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2035         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2036                 u32 phy_reg;
2037
2038                 /* Set bit 14 with read-modify-write to preserve other bits */
2039                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2040                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
2041                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
2042         }
2043
2044         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2045          * jumbo frames transmission.
2046          */
2047         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2048                 u32 phy_reg;
2049
2050                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
2051                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2052                                      phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2053         }
2054
2055         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2056                 /* adjust output voltage */
2057                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2058         }
2059
2060         tg3_phy_toggle_automdix(tp, 1);
2061         tg3_phy_set_wirespeed(tp);
2062         return 0;
2063 }
2064
2065 static void tg3_frob_aux_power(struct tg3 *tp)
2066 {
2067         struct tg3 *tp_peer = tp;
2068
2069         /* The GPIOs do something completely different on 57765. */
2070         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2071             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2072             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2073                 return;
2074
2075         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2076             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2077             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2078                 struct net_device *dev_peer;
2079
2080                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2081                 /* remove_one() may have been run on the peer. */
2082                 if (!dev_peer)
2083                         tp_peer = tp;
2084                 else
2085                         tp_peer = netdev_priv(dev_peer);
2086         }
2087
2088         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2089             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2090             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2091             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2092                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2093                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2094                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2095                                     (GRC_LCLCTRL_GPIO_OE0 |
2096                                      GRC_LCLCTRL_GPIO_OE1 |
2097                                      GRC_LCLCTRL_GPIO_OE2 |
2098                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2099                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2100                                     100);
2101                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2102                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2103                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2104                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2105                                              GRC_LCLCTRL_GPIO_OE1 |
2106                                              GRC_LCLCTRL_GPIO_OE2 |
2107                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2108                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2109                                              tp->grc_local_ctrl;
2110                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2111
2112                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2113                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2114
2115                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2116                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2117                 } else {
2118                         u32 no_gpio2;
2119                         u32 grc_local_ctrl = 0;
2120
2121                         if (tp_peer != tp &&
2122                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2123                                 return;
2124
2125                         /* Workaround to prevent overdrawing Amps. */
2126                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2127                             ASIC_REV_5714) {
2128                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2129                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2130                                             grc_local_ctrl, 100);
2131                         }
2132
2133                         /* On 5753 and variants, GPIO2 cannot be used. */
2134                         no_gpio2 = tp->nic_sram_data_cfg &
2135                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2136
2137                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2138                                          GRC_LCLCTRL_GPIO_OE1 |
2139                                          GRC_LCLCTRL_GPIO_OE2 |
2140                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2141                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2142                         if (no_gpio2) {
2143                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2144                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2145                         }
2146                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2147                                                     grc_local_ctrl, 100);
2148
2149                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2150
2151                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2152                                                     grc_local_ctrl, 100);
2153
2154                         if (!no_gpio2) {
2155                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2156                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2157                                             grc_local_ctrl, 100);
2158                         }
2159                 }
2160         } else {
2161                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2162                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2163                         if (tp_peer != tp &&
2164                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2165                                 return;
2166
2167                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2168                                     (GRC_LCLCTRL_GPIO_OE1 |
2169                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2170
2171                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2172                                     GRC_LCLCTRL_GPIO_OE1, 100);
2173
2174                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2175                                     (GRC_LCLCTRL_GPIO_OE1 |
2176                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2177                 }
2178         }
2179 }
2180
2181 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2182 {
2183         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2184                 return 1;
2185         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2186                 if (speed != SPEED_10)
2187                         return 1;
2188         } else if (speed == SPEED_10)
2189                 return 1;
2190
2191         return 0;
2192 }
2193
2194 static int tg3_setup_phy(struct tg3 *, int);
2195
2196 #define RESET_KIND_SHUTDOWN     0
2197 #define RESET_KIND_INIT         1
2198 #define RESET_KIND_SUSPEND      2
2199
2200 static void tg3_write_sig_post_reset(struct tg3 *, int);
2201 static int tg3_halt_cpu(struct tg3 *, u32);
2202
2203 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2204 {
2205         u32 val;
2206
2207         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2208                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2209                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2210                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2211
2212                         sg_dig_ctrl |=
2213                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2214                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2215                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2216                 }
2217                 return;
2218         }
2219
2220         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2221                 tg3_bmcr_reset(tp);
2222                 val = tr32(GRC_MISC_CFG);
2223                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2224                 udelay(40);
2225                 return;
2226         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2227                 u32 phytest;
2228                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2229                         u32 phy;
2230
2231                         tg3_writephy(tp, MII_ADVERTISE, 0);
2232                         tg3_writephy(tp, MII_BMCR,
2233                                      BMCR_ANENABLE | BMCR_ANRESTART);
2234
2235                         tg3_writephy(tp, MII_TG3_FET_TEST,
2236                                      phytest | MII_TG3_FET_SHADOW_EN);
2237                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2238                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2239                                 tg3_writephy(tp,
2240                                              MII_TG3_FET_SHDW_AUXMODE4,
2241                                              phy);
2242                         }
2243                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2244                 }
2245                 return;
2246         } else if (do_low_power) {
2247                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2248                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2249
2250                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2251                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2252                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2253                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2254                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2255         }
2256
2257         /* The PHY should not be powered down on some chips because
2258          * of bugs.
2259          */
2260         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2261             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2262             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2263              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2264                 return;
2265
2266         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2267             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2268                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2269                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2270                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2271                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2272         }
2273
2274         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2275 }
2276
2277 /* tp->lock is held. */
2278 static int tg3_nvram_lock(struct tg3 *tp)
2279 {
2280         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2281                 int i;
2282
2283                 if (tp->nvram_lock_cnt == 0) {
2284                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2285                         for (i = 0; i < 8000; i++) {
2286                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2287                                         break;
2288                                 udelay(20);
2289                         }
2290                         if (i == 8000) {
2291                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2292                                 return -ENODEV;
2293                         }
2294                 }
2295                 tp->nvram_lock_cnt++;
2296         }
2297         return 0;
2298 }
2299
2300 /* tp->lock is held. */
2301 static void tg3_nvram_unlock(struct tg3 *tp)
2302 {
2303         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2304                 if (tp->nvram_lock_cnt > 0)
2305                         tp->nvram_lock_cnt--;
2306                 if (tp->nvram_lock_cnt == 0)
2307                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2308         }
2309 }
2310
2311 /* tp->lock is held. */
2312 static void tg3_enable_nvram_access(struct tg3 *tp)
2313 {
2314         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2315             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2316                 u32 nvaccess = tr32(NVRAM_ACCESS);
2317
2318                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2319         }
2320 }
2321
2322 /* tp->lock is held. */
2323 static void tg3_disable_nvram_access(struct tg3 *tp)
2324 {
2325         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2326             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2327                 u32 nvaccess = tr32(NVRAM_ACCESS);
2328
2329                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2330         }
2331 }
2332
2333 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2334                                         u32 offset, u32 *val)
2335 {
2336         u32 tmp;
2337         int i;
2338
2339         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2340                 return -EINVAL;
2341
2342         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2343                                         EEPROM_ADDR_DEVID_MASK |
2344                                         EEPROM_ADDR_READ);
2345         tw32(GRC_EEPROM_ADDR,
2346              tmp |
2347              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2348              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2349               EEPROM_ADDR_ADDR_MASK) |
2350              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2351
2352         for (i = 0; i < 1000; i++) {
2353                 tmp = tr32(GRC_EEPROM_ADDR);
2354
2355                 if (tmp & EEPROM_ADDR_COMPLETE)
2356                         break;
2357                 msleep(1);
2358         }
2359         if (!(tmp & EEPROM_ADDR_COMPLETE))
2360                 return -EBUSY;
2361
2362         tmp = tr32(GRC_EEPROM_DATA);
2363
2364         /*
2365          * The data will always be opposite the native endian
2366          * format.  Perform a blind byteswap to compensate.
2367          */
2368         *val = swab32(tmp);
2369
2370         return 0;
2371 }
2372
2373 #define NVRAM_CMD_TIMEOUT 10000
2374
2375 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2376 {
2377         int i;
2378
2379         tw32(NVRAM_CMD, nvram_cmd);
2380         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2381                 udelay(10);
2382                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2383                         udelay(10);
2384                         break;
2385                 }
2386         }
2387
2388         if (i == NVRAM_CMD_TIMEOUT)
2389                 return -EBUSY;
2390
2391         return 0;
2392 }
2393
2394 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2395 {
2396         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2397             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2398             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2399            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2400             (tp->nvram_jedecnum == JEDEC_ATMEL))
2401
2402                 addr = ((addr / tp->nvram_pagesize) <<
2403                         ATMEL_AT45DB0X1B_PAGE_POS) +
2404                        (addr % tp->nvram_pagesize);
2405
2406         return addr;
2407 }
2408
2409 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2410 {
2411         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2412             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2413             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2414            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2415             (tp->nvram_jedecnum == JEDEC_ATMEL))
2416
2417                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2418                         tp->nvram_pagesize) +
2419                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2420
2421         return addr;
2422 }
2423
2424 /* NOTE: Data read in from NVRAM is byteswapped according to
2425  * the byteswapping settings for all other register accesses.
2426  * tg3 devices are BE devices, so on a BE machine, the data
2427  * returned will be exactly as it is seen in NVRAM.  On a LE
2428  * machine, the 32-bit value will be byteswapped.
2429  */
2430 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2431 {
2432         int ret;
2433
2434         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2435                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2436
2437         offset = tg3_nvram_phys_addr(tp, offset);
2438
2439         if (offset > NVRAM_ADDR_MSK)
2440                 return -EINVAL;
2441
2442         ret = tg3_nvram_lock(tp);
2443         if (ret)
2444                 return ret;
2445
2446         tg3_enable_nvram_access(tp);
2447
2448         tw32(NVRAM_ADDR, offset);
2449         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2450                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2451
2452         if (ret == 0)
2453                 *val = tr32(NVRAM_RDDATA);
2454
2455         tg3_disable_nvram_access(tp);
2456
2457         tg3_nvram_unlock(tp);
2458
2459         return ret;
2460 }
2461
2462 /* Ensures NVRAM data is in bytestream format. */
2463 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2464 {
2465         u32 v;
2466         int res = tg3_nvram_read(tp, offset, &v);
2467         if (!res)
2468                 *val = cpu_to_be32(v);
2469         return res;
2470 }
2471
2472 /* tp->lock is held. */
2473 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2474 {
2475         u32 addr_high, addr_low;
2476         int i;
2477
2478         addr_high = ((tp->dev->dev_addr[0] << 8) |
2479                      tp->dev->dev_addr[1]);
2480         addr_low = ((tp->dev->dev_addr[2] << 24) |
2481                     (tp->dev->dev_addr[3] << 16) |
2482                     (tp->dev->dev_addr[4] <<  8) |
2483                     (tp->dev->dev_addr[5] <<  0));
2484         for (i = 0; i < 4; i++) {
2485                 if (i == 1 && skip_mac_1)
2486                         continue;
2487                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2488                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2489         }
2490
2491         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2492             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2493                 for (i = 0; i < 12; i++) {
2494                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2495                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2496                 }
2497         }
2498
2499         addr_high = (tp->dev->dev_addr[0] +
2500                      tp->dev->dev_addr[1] +
2501                      tp->dev->dev_addr[2] +
2502                      tp->dev->dev_addr[3] +
2503                      tp->dev->dev_addr[4] +
2504                      tp->dev->dev_addr[5]) &
2505                 TX_BACKOFF_SEED_MASK;
2506         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2507 }
2508
2509 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2510 {
2511         u32 misc_host_ctrl;
2512         bool device_should_wake, do_low_power;
2513
2514         /* Make sure register accesses (indirect or otherwise)
2515          * will function correctly.
2516          */
2517         pci_write_config_dword(tp->pdev,
2518                                TG3PCI_MISC_HOST_CTRL,
2519                                tp->misc_host_ctrl);
2520
2521         switch (state) {
2522         case PCI_D0:
2523                 pci_enable_wake(tp->pdev, state, false);
2524                 pci_set_power_state(tp->pdev, PCI_D0);
2525
2526                 /* Switch out of Vaux if it is a NIC */
2527                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2528                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2529
2530                 return 0;
2531
2532         case PCI_D1:
2533         case PCI_D2:
2534         case PCI_D3hot:
2535                 break;
2536
2537         default:
2538                 netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
2539                            state);
2540                 return -EINVAL;
2541         }
2542
2543         /* Restore the CLKREQ setting. */
2544         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2545                 u16 lnkctl;
2546
2547                 pci_read_config_word(tp->pdev,
2548                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2549                                      &lnkctl);
2550                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2551                 pci_write_config_word(tp->pdev,
2552                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2553                                       lnkctl);
2554         }
2555
2556         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2557         tw32(TG3PCI_MISC_HOST_CTRL,
2558              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2559
2560         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2561                              device_may_wakeup(&tp->pdev->dev) &&
2562                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2563
2564         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2565                 do_low_power = false;
2566                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2567                     !tp->link_config.phy_is_low_power) {
2568                         struct phy_device *phydev;
2569                         u32 phyid, advertising;
2570
2571                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2572
2573                         tp->link_config.phy_is_low_power = 1;
2574
2575                         tp->link_config.orig_speed = phydev->speed;
2576                         tp->link_config.orig_duplex = phydev->duplex;
2577                         tp->link_config.orig_autoneg = phydev->autoneg;
2578                         tp->link_config.orig_advertising = phydev->advertising;
2579
2580                         advertising = ADVERTISED_TP |
2581                                       ADVERTISED_Pause |
2582                                       ADVERTISED_Autoneg |
2583                                       ADVERTISED_10baseT_Half;
2584
2585                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2586                             device_should_wake) {
2587                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2588                                         advertising |=
2589                                                 ADVERTISED_100baseT_Half |
2590                                                 ADVERTISED_100baseT_Full |
2591                                                 ADVERTISED_10baseT_Full;
2592                                 else
2593                                         advertising |= ADVERTISED_10baseT_Full;
2594                         }
2595
2596                         phydev->advertising = advertising;
2597
2598                         phy_start_aneg(phydev);
2599
2600                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2601                         if (phyid != PHY_ID_BCMAC131) {
2602                                 phyid &= PHY_BCM_OUI_MASK;
2603                                 if (phyid == PHY_BCM_OUI_1 ||
2604                                     phyid == PHY_BCM_OUI_2 ||
2605                                     phyid == PHY_BCM_OUI_3)
2606                                         do_low_power = true;
2607                         }
2608                 }
2609         } else {
2610                 do_low_power = true;
2611
2612                 if (tp->link_config.phy_is_low_power == 0) {
2613                         tp->link_config.phy_is_low_power = 1;
2614                         tp->link_config.orig_speed = tp->link_config.speed;
2615                         tp->link_config.orig_duplex = tp->link_config.duplex;
2616                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2617                 }
2618
2619                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2620                         tp->link_config.speed = SPEED_10;
2621                         tp->link_config.duplex = DUPLEX_HALF;
2622                         tp->link_config.autoneg = AUTONEG_ENABLE;
2623                         tg3_setup_phy(tp, 0);
2624                 }
2625         }
2626
2627         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2628                 u32 val;
2629
2630                 val = tr32(GRC_VCPU_EXT_CTRL);
2631                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2632         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2633                 int i;
2634                 u32 val;
2635
2636                 for (i = 0; i < 200; i++) {
2637                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2638                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2639                                 break;
2640                         msleep(1);
2641                 }
2642         }
2643         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2644                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2645                                                      WOL_DRV_STATE_SHUTDOWN |
2646                                                      WOL_DRV_WOL |
2647                                                      WOL_SET_MAGIC_PKT);
2648
2649         if (device_should_wake) {
2650                 u32 mac_mode;
2651
2652                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2653                         if (do_low_power) {
2654                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2655                                 udelay(40);
2656                         }
2657
2658                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2659                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2660                         else
2661                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2662
2663                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2664                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2665                             ASIC_REV_5700) {
2666                                 u32 speed = (tp->tg3_flags &
2667                                              TG3_FLAG_WOL_SPEED_100MB) ?
2668                                              SPEED_100 : SPEED_10;
2669                                 if (tg3_5700_link_polarity(tp, speed))
2670                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2671                                 else
2672                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2673                         }
2674                 } else {
2675                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2676                 }
2677
2678                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2679                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2680
2681                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2682                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2683                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2684                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2685                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2686                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2687
2688                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2689                         mac_mode |= tp->mac_mode &
2690                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2691                         if (mac_mode & MAC_MODE_APE_TX_EN)
2692                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2693                 }
2694
2695                 tw32_f(MAC_MODE, mac_mode);
2696                 udelay(100);
2697
2698                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2699                 udelay(10);
2700         }
2701
2702         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2703             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2704              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2705                 u32 base_val;
2706
2707                 base_val = tp->pci_clock_ctrl;
2708                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2709                              CLOCK_CTRL_TXCLK_DISABLE);
2710
2711                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2712                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2713         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2714                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2715                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2716                 /* do nothing */
2717         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2718                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2719                 u32 newbits1, newbits2;
2720
2721                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2722                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2723                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2724                                     CLOCK_CTRL_TXCLK_DISABLE |
2725                                     CLOCK_CTRL_ALTCLK);
2726                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2727                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2728                         newbits1 = CLOCK_CTRL_625_CORE;
2729                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2730                 } else {
2731                         newbits1 = CLOCK_CTRL_ALTCLK;
2732                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2733                 }
2734
2735                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2736                             40);
2737
2738                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2739                             40);
2740
2741                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2742                         u32 newbits3;
2743
2744                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2745                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2746                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2747                                             CLOCK_CTRL_TXCLK_DISABLE |
2748                                             CLOCK_CTRL_44MHZ_CORE);
2749                         } else {
2750                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2751                         }
2752
2753                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2754                                     tp->pci_clock_ctrl | newbits3, 40);
2755                 }
2756         }
2757
2758         if (!(device_should_wake) &&
2759             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2760                 tg3_power_down_phy(tp, do_low_power);
2761
2762         tg3_frob_aux_power(tp);
2763
2764         /* Workaround for unstable PLL clock */
2765         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2766             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2767                 u32 val = tr32(0x7d00);
2768
2769                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2770                 tw32(0x7d00, val);
2771                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2772                         int err;
2773
2774                         err = tg3_nvram_lock(tp);
2775                         tg3_halt_cpu(tp, RX_CPU_BASE);
2776                         if (!err)
2777                                 tg3_nvram_unlock(tp);
2778                 }
2779         }
2780
2781         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2782
2783         if (device_should_wake)
2784                 pci_enable_wake(tp->pdev, state, true);
2785
2786         /* Finally, set the new power state. */
2787         pci_set_power_state(tp->pdev, state);
2788
2789         return 0;
2790 }
2791
2792 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2793 {
2794         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2795         case MII_TG3_AUX_STAT_10HALF:
2796                 *speed = SPEED_10;
2797                 *duplex = DUPLEX_HALF;
2798                 break;
2799
2800         case MII_TG3_AUX_STAT_10FULL:
2801                 *speed = SPEED_10;
2802                 *duplex = DUPLEX_FULL;
2803                 break;
2804
2805         case MII_TG3_AUX_STAT_100HALF:
2806                 *speed = SPEED_100;
2807                 *duplex = DUPLEX_HALF;
2808                 break;
2809
2810         case MII_TG3_AUX_STAT_100FULL:
2811                 *speed = SPEED_100;
2812                 *duplex = DUPLEX_FULL;
2813                 break;
2814
2815         case MII_TG3_AUX_STAT_1000HALF:
2816                 *speed = SPEED_1000;
2817                 *duplex = DUPLEX_HALF;
2818                 break;
2819
2820         case MII_TG3_AUX_STAT_1000FULL:
2821                 *speed = SPEED_1000;
2822                 *duplex = DUPLEX_FULL;
2823                 break;
2824
2825         default:
2826                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2827                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2828                                  SPEED_10;
2829                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2830                                   DUPLEX_HALF;
2831                         break;
2832                 }
2833                 *speed = SPEED_INVALID;
2834                 *duplex = DUPLEX_INVALID;
2835                 break;
2836         }
2837 }
2838
2839 static void tg3_phy_copper_begin(struct tg3 *tp)
2840 {
2841         u32 new_adv;
2842         int i;
2843
2844         if (tp->link_config.phy_is_low_power) {
2845                 /* Entering low power mode.  Disable gigabit and
2846                  * 100baseT advertisements.
2847                  */
2848                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2849
2850                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2851                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2852                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2853                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2854
2855                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2856         } else if (tp->link_config.speed == SPEED_INVALID) {
2857                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2858                         tp->link_config.advertising &=
2859                                 ~(ADVERTISED_1000baseT_Half |
2860                                   ADVERTISED_1000baseT_Full);
2861
2862                 new_adv = ADVERTISE_CSMA;
2863                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2864                         new_adv |= ADVERTISE_10HALF;
2865                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2866                         new_adv |= ADVERTISE_10FULL;
2867                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2868                         new_adv |= ADVERTISE_100HALF;
2869                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2870                         new_adv |= ADVERTISE_100FULL;
2871
2872                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2873
2874                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2875
2876                 if (tp->link_config.advertising &
2877                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2878                         new_adv = 0;
2879                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2880                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2881                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2882                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2883                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2884                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2885                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2886                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2887                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2888                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2889                 } else {
2890                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2891                 }
2892         } else {
2893                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2894                 new_adv |= ADVERTISE_CSMA;
2895
2896                 /* Asking for a specific link mode. */
2897                 if (tp->link_config.speed == SPEED_1000) {
2898                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2899
2900                         if (tp->link_config.duplex == DUPLEX_FULL)
2901                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2902                         else
2903                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2904                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2905                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2906                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2907                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2908                 } else {
2909                         if (tp->link_config.speed == SPEED_100) {
2910                                 if (tp->link_config.duplex == DUPLEX_FULL)
2911                                         new_adv |= ADVERTISE_100FULL;
2912                                 else
2913                                         new_adv |= ADVERTISE_100HALF;
2914                         } else {
2915                                 if (tp->link_config.duplex == DUPLEX_FULL)
2916                                         new_adv |= ADVERTISE_10FULL;
2917                                 else
2918                                         new_adv |= ADVERTISE_10HALF;
2919                         }
2920                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2921
2922                         new_adv = 0;
2923                 }
2924
2925                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2926         }
2927
2928         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2929             tp->link_config.speed != SPEED_INVALID) {
2930                 u32 bmcr, orig_bmcr;
2931
2932                 tp->link_config.active_speed = tp->link_config.speed;
2933                 tp->link_config.active_duplex = tp->link_config.duplex;
2934
2935                 bmcr = 0;
2936                 switch (tp->link_config.speed) {
2937                 default:
2938                 case SPEED_10:
2939                         break;
2940
2941                 case SPEED_100:
2942                         bmcr |= BMCR_SPEED100;
2943                         break;
2944
2945                 case SPEED_1000:
2946                         bmcr |= TG3_BMCR_SPEED1000;
2947                         break;
2948                 }
2949
2950                 if (tp->link_config.duplex == DUPLEX_FULL)
2951                         bmcr |= BMCR_FULLDPLX;
2952
2953                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2954                     (bmcr != orig_bmcr)) {
2955                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2956                         for (i = 0; i < 1500; i++) {
2957                                 u32 tmp;
2958
2959                                 udelay(10);
2960                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2961                                     tg3_readphy(tp, MII_BMSR, &tmp))
2962                                         continue;
2963                                 if (!(tmp & BMSR_LSTATUS)) {
2964                                         udelay(40);
2965                                         break;
2966                                 }
2967                         }
2968                         tg3_writephy(tp, MII_BMCR, bmcr);
2969                         udelay(40);
2970                 }
2971         } else {
2972                 tg3_writephy(tp, MII_BMCR,
2973                              BMCR_ANENABLE | BMCR_ANRESTART);
2974         }
2975 }
2976
2977 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2978 {
2979         int err;
2980
2981         /* Turn off tap power management. */
2982         /* Set Extended packet length bit */
2983         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2984
2985         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2986         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2987
2988         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2989         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2990
2991         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2992         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2993
2994         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2995         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2996
2997         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2998         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2999
3000         udelay(40);
3001
3002         return err;
3003 }
3004
3005 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
3006 {
3007         u32 adv_reg, all_mask = 0;
3008
3009         if (mask & ADVERTISED_10baseT_Half)
3010                 all_mask |= ADVERTISE_10HALF;
3011         if (mask & ADVERTISED_10baseT_Full)
3012                 all_mask |= ADVERTISE_10FULL;
3013         if (mask & ADVERTISED_100baseT_Half)
3014                 all_mask |= ADVERTISE_100HALF;
3015         if (mask & ADVERTISED_100baseT_Full)
3016                 all_mask |= ADVERTISE_100FULL;
3017
3018         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3019                 return 0;
3020
3021         if ((adv_reg & all_mask) != all_mask)
3022                 return 0;
3023         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
3024                 u32 tg3_ctrl;
3025
3026                 all_mask = 0;
3027                 if (mask & ADVERTISED_1000baseT_Half)
3028                         all_mask |= ADVERTISE_1000HALF;
3029                 if (mask & ADVERTISED_1000baseT_Full)
3030                         all_mask |= ADVERTISE_1000FULL;
3031
3032                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3033                         return 0;
3034
3035                 if ((tg3_ctrl & all_mask) != all_mask)
3036                         return 0;
3037         }
3038         return 1;
3039 }
3040
3041 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3042 {
3043         u32 curadv, reqadv;
3044
3045         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3046                 return 1;
3047
3048         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3049         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3050
3051         if (tp->link_config.active_duplex == DUPLEX_FULL) {
3052                 if (curadv != reqadv)
3053                         return 0;
3054
3055                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3056                         tg3_readphy(tp, MII_LPA, rmtadv);
3057         } else {
3058                 /* Reprogram the advertisement register, even if it
3059                  * does not affect the current link.  If the link
3060                  * gets renegotiated in the future, we can save an
3061                  * additional renegotiation cycle by advertising
3062                  * it correctly in the first place.
3063                  */
3064                 if (curadv != reqadv) {
3065                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3066                                      ADVERTISE_PAUSE_ASYM);
3067                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3068                 }
3069         }
3070
3071         return 1;
3072 }
3073
3074 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3075 {
3076         int current_link_up;
3077         u32 bmsr, dummy;
3078         u32 lcl_adv, rmt_adv;
3079         u16 current_speed;
3080         u8 current_duplex;
3081         int i, err;
3082
3083         tw32(MAC_EVENT, 0);
3084
3085         tw32_f(MAC_STATUS,
3086              (MAC_STATUS_SYNC_CHANGED |
3087               MAC_STATUS_CFG_CHANGED |
3088               MAC_STATUS_MI_COMPLETION |
3089               MAC_STATUS_LNKSTATE_CHANGED));
3090         udelay(40);
3091
3092         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3093                 tw32_f(MAC_MI_MODE,
3094                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3095                 udelay(80);
3096         }
3097
3098         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3099
3100         /* Some third-party PHYs need to be reset on link going
3101          * down.
3102          */
3103         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3104              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3105              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3106             netif_carrier_ok(tp->dev)) {
3107                 tg3_readphy(tp, MII_BMSR, &bmsr);
3108                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3109                     !(bmsr & BMSR_LSTATUS))
3110                         force_reset = 1;
3111         }
3112         if (force_reset)
3113                 tg3_phy_reset(tp);
3114
3115         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3116                 tg3_readphy(tp, MII_BMSR, &bmsr);
3117                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3118                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3119                         bmsr = 0;
3120
3121                 if (!(bmsr & BMSR_LSTATUS)) {
3122                         err = tg3_init_5401phy_dsp(tp);
3123                         if (err)
3124                                 return err;
3125
3126                         tg3_readphy(tp, MII_BMSR, &bmsr);
3127                         for (i = 0; i < 1000; i++) {
3128                                 udelay(10);
3129                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3130                                     (bmsr & BMSR_LSTATUS)) {
3131                                         udelay(40);
3132                                         break;
3133                                 }
3134                         }
3135
3136                         if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3137                             TG3_PHY_REV_BCM5401_B0 &&
3138                             !(bmsr & BMSR_LSTATUS) &&
3139                             tp->link_config.active_speed == SPEED_1000) {
3140                                 err = tg3_phy_reset(tp);
3141                                 if (!err)
3142                                         err = tg3_init_5401phy_dsp(tp);
3143                                 if (err)
3144                                         return err;
3145                         }
3146                 }
3147         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3148                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3149                 /* 5701 {A0,B0} CRC bug workaround */
3150                 tg3_writephy(tp, 0x15, 0x0a75);
3151                 tg3_writephy(tp, 0x1c, 0x8c68);
3152                 tg3_writephy(tp, 0x1c, 0x8d68);
3153                 tg3_writephy(tp, 0x1c, 0x8c68);
3154         }
3155
3156         /* Clear pending interrupts... */
3157         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3158         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3159
3160         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3161                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3162         else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3163                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3164
3165         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3166             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3167                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3168                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3169                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3170                 else
3171                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3172         }
3173
3174         current_link_up = 0;
3175         current_speed = SPEED_INVALID;
3176         current_duplex = DUPLEX_INVALID;
3177
3178         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3179                 u32 val;
3180
3181                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3182                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3183                 if (!(val & (1 << 10))) {
3184                         val |= (1 << 10);
3185                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3186                         goto relink;
3187                 }
3188         }
3189
3190         bmsr = 0;
3191         for (i = 0; i < 100; i++) {
3192                 tg3_readphy(tp, MII_BMSR, &bmsr);
3193                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3194                     (bmsr & BMSR_LSTATUS))
3195                         break;
3196                 udelay(40);
3197         }
3198
3199         if (bmsr & BMSR_LSTATUS) {
3200                 u32 aux_stat, bmcr;
3201
3202                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3203                 for (i = 0; i < 2000; i++) {
3204                         udelay(10);
3205                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3206                             aux_stat)
3207                                 break;
3208                 }
3209
3210                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3211                                              &current_speed,
3212                                              &current_duplex);
3213
3214                 bmcr = 0;
3215                 for (i = 0; i < 200; i++) {
3216                         tg3_readphy(tp, MII_BMCR, &bmcr);
3217                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3218                                 continue;
3219                         if (bmcr && bmcr != 0x7fff)
3220                                 break;
3221                         udelay(10);
3222                 }
3223
3224                 lcl_adv = 0;
3225                 rmt_adv = 0;
3226
3227                 tp->link_config.active_speed = current_speed;
3228                 tp->link_config.active_duplex = current_duplex;
3229
3230                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3231                         if ((bmcr & BMCR_ANENABLE) &&
3232                             tg3_copper_is_advertising_all(tp,
3233                                                 tp->link_config.advertising)) {
3234                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3235                                                                   &rmt_adv))
3236                                         current_link_up = 1;
3237                         }
3238                 } else {
3239                         if (!(bmcr & BMCR_ANENABLE) &&
3240                             tp->link_config.speed == current_speed &&
3241                             tp->link_config.duplex == current_duplex &&
3242                             tp->link_config.flowctrl ==
3243                             tp->link_config.active_flowctrl) {
3244                                 current_link_up = 1;
3245                         }
3246                 }
3247
3248                 if (current_link_up == 1 &&
3249                     tp->link_config.active_duplex == DUPLEX_FULL)
3250                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3251         }
3252
3253 relink:
3254         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3255                 u32 tmp;
3256
3257                 tg3_phy_copper_begin(tp);
3258
3259                 tg3_readphy(tp, MII_BMSR, &tmp);
3260                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3261                     (tmp & BMSR_LSTATUS))
3262                         current_link_up = 1;
3263         }
3264
3265         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3266         if (current_link_up == 1) {
3267                 if (tp->link_config.active_speed == SPEED_100 ||
3268                     tp->link_config.active_speed == SPEED_10)
3269                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3270                 else
3271                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3272         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3273                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3274         else
3275                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3276
3277         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3278         if (tp->link_config.active_duplex == DUPLEX_HALF)
3279                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3280
3281         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3282                 if (current_link_up == 1 &&
3283                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3284                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3285                 else
3286                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3287         }
3288
3289         /* ??? Without this setting Netgear GA302T PHY does not
3290          * ??? send/receive packets...
3291          */
3292         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3293             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3294                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3295                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3296                 udelay(80);
3297         }
3298
3299         tw32_f(MAC_MODE, tp->mac_mode);
3300         udelay(40);
3301
3302         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3303                 /* Polled via timer. */
3304                 tw32_f(MAC_EVENT, 0);
3305         } else {
3306                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3307         }
3308         udelay(40);
3309
3310         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3311             current_link_up == 1 &&
3312             tp->link_config.active_speed == SPEED_1000 &&
3313             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3314              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3315                 udelay(120);
3316                 tw32_f(MAC_STATUS,
3317                      (MAC_STATUS_SYNC_CHANGED |
3318                       MAC_STATUS_CFG_CHANGED));
3319                 udelay(40);
3320                 tg3_write_mem(tp,
3321                               NIC_SRAM_FIRMWARE_MBOX,
3322                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3323         }
3324
3325         /* Prevent send BD corruption. */
3326         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3327                 u16 oldlnkctl, newlnkctl;
3328
3329                 pci_read_config_word(tp->pdev,
3330                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3331                                      &oldlnkctl);
3332                 if (tp->link_config.active_speed == SPEED_100 ||
3333                     tp->link_config.active_speed == SPEED_10)
3334                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3335                 else
3336                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3337                 if (newlnkctl != oldlnkctl)
3338                         pci_write_config_word(tp->pdev,
3339                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3340                                               newlnkctl);
3341         }
3342
3343         if (current_link_up != netif_carrier_ok(tp->dev)) {
3344                 if (current_link_up)
3345                         netif_carrier_on(tp->dev);
3346                 else
3347                         netif_carrier_off(tp->dev);
3348                 tg3_link_report(tp);
3349         }
3350
3351         return 0;
3352 }
3353
3354 struct tg3_fiber_aneginfo {
3355         int state;
3356 #define ANEG_STATE_UNKNOWN              0
3357 #define ANEG_STATE_AN_ENABLE            1
3358 #define ANEG_STATE_RESTART_INIT         2
3359 #define ANEG_STATE_RESTART              3
3360 #define ANEG_STATE_DISABLE_LINK_OK      4
3361 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3362 #define ANEG_STATE_ABILITY_DETECT       6
3363 #define ANEG_STATE_ACK_DETECT_INIT      7
3364 #define ANEG_STATE_ACK_DETECT           8
3365 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3366 #define ANEG_STATE_COMPLETE_ACK         10
3367 #define ANEG_STATE_IDLE_DETECT_INIT     11
3368 #define ANEG_STATE_IDLE_DETECT          12
3369 #define ANEG_STATE_LINK_OK              13
3370 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3371 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3372
3373         u32 flags;
3374 #define MR_AN_ENABLE            0x00000001
3375 #define MR_RESTART_AN           0x00000002
3376 #define MR_AN_COMPLETE          0x00000004
3377 #define MR_PAGE_RX              0x00000008
3378 #define MR_NP_LOADED            0x00000010
3379 #define MR_TOGGLE_TX            0x00000020
3380 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3381 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3382 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3383 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3384 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3385 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3386 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3387 #define MR_TOGGLE_RX            0x00002000
3388 #define MR_NP_RX                0x00004000
3389
3390 #define MR_LINK_OK              0x80000000
3391
3392         unsigned long link_time, cur_time;
3393
3394         u32 ability_match_cfg;
3395         int ability_match_count;
3396
3397         char ability_match, idle_match, ack_match;
3398
3399         u32 txconfig, rxconfig;
3400 #define ANEG_CFG_NP             0x00000080
3401 #define ANEG_CFG_ACK            0x00000040
3402 #define ANEG_CFG_RF2            0x00000020
3403 #define ANEG_CFG_RF1            0x00000010
3404 #define ANEG_CFG_PS2            0x00000001
3405 #define ANEG_CFG_PS1            0x00008000
3406 #define ANEG_CFG_HD             0x00004000
3407 #define ANEG_CFG_FD             0x00002000
3408 #define ANEG_CFG_INVAL          0x00001f06
3409
3410 };
3411 #define ANEG_OK         0
3412 #define ANEG_DONE       1
3413 #define ANEG_TIMER_ENAB 2
3414 #define ANEG_FAILED     -1
3415
3416 #define ANEG_STATE_SETTLE_TIME  10000
3417
3418 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3419                                    struct tg3_fiber_aneginfo *ap)
3420 {
3421         u16 flowctrl;
3422         unsigned long delta;
3423         u32 rx_cfg_reg;
3424         int ret;
3425
3426         if (ap->state == ANEG_STATE_UNKNOWN) {
3427                 ap->rxconfig = 0;
3428                 ap->link_time = 0;
3429                 ap->cur_time = 0;
3430                 ap->ability_match_cfg = 0;
3431                 ap->ability_match_count = 0;
3432                 ap->ability_match = 0;
3433                 ap->idle_match = 0;
3434                 ap->ack_match = 0;
3435         }
3436         ap->cur_time++;
3437
3438         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3439                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3440
3441                 if (rx_cfg_reg != ap->ability_match_cfg) {
3442                         ap->ability_match_cfg = rx_cfg_reg;
3443                         ap->ability_match = 0;
3444                         ap->ability_match_count = 0;
3445                 } else {
3446                         if (++ap->ability_match_count > 1) {
3447                                 ap->ability_match = 1;
3448                                 ap->ability_match_cfg = rx_cfg_reg;
3449                         }
3450                 }
3451                 if (rx_cfg_reg & ANEG_CFG_ACK)
3452                         ap->ack_match = 1;
3453                 else
3454                         ap->ack_match = 0;
3455
3456                 ap->idle_match = 0;
3457         } else {
3458                 ap->idle_match = 1;
3459                 ap->ability_match_cfg = 0;
3460                 ap->ability_match_count = 0;
3461                 ap->ability_match = 0;
3462                 ap->ack_match = 0;
3463
3464                 rx_cfg_reg = 0;
3465         }
3466
3467         ap->rxconfig = rx_cfg_reg;
3468         ret = ANEG_OK;
3469
3470         switch (ap->state) {
3471         case ANEG_STATE_UNKNOWN:
3472                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3473                         ap->state = ANEG_STATE_AN_ENABLE;
3474
3475                 /* fallthru */
3476         case ANEG_STATE_AN_ENABLE:
3477                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3478                 if (ap->flags & MR_AN_ENABLE) {
3479                         ap->link_time = 0;
3480                         ap->cur_time = 0;
3481                         ap->ability_match_cfg = 0;
3482                         ap->ability_match_count = 0;
3483                         ap->ability_match = 0;
3484                         ap->idle_match = 0;
3485                         ap->ack_match = 0;
3486
3487                         ap->state = ANEG_STATE_RESTART_INIT;
3488                 } else {
3489                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3490                 }
3491                 break;
3492
3493         case ANEG_STATE_RESTART_INIT:
3494                 ap->link_time = ap->cur_time;
3495                 ap->flags &= ~(MR_NP_LOADED);
3496                 ap->txconfig = 0;
3497                 tw32(MAC_TX_AUTO_NEG, 0);
3498                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3499                 tw32_f(MAC_MODE, tp->mac_mode);
3500                 udelay(40);
3501
3502                 ret = ANEG_TIMER_ENAB;
3503                 ap->state = ANEG_STATE_RESTART;
3504
3505                 /* fallthru */
3506         case ANEG_STATE_RESTART:
3507                 delta = ap->cur_time - ap->link_time;
3508                 if (delta > ANEG_STATE_SETTLE_TIME)
3509                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3510                 else
3511                         ret = ANEG_TIMER_ENAB;
3512                 break;
3513
3514         case ANEG_STATE_DISABLE_LINK_OK:
3515                 ret = ANEG_DONE;
3516                 break;
3517
3518         case ANEG_STATE_ABILITY_DETECT_INIT:
3519                 ap->flags &= ~(MR_TOGGLE_TX);
3520                 ap->txconfig = ANEG_CFG_FD;
3521                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3522                 if (flowctrl & ADVERTISE_1000XPAUSE)
3523                         ap->txconfig |= ANEG_CFG_PS1;
3524                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3525                         ap->txconfig |= ANEG_CFG_PS2;
3526                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3527                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3528                 tw32_f(MAC_MODE, tp->mac_mode);
3529                 udelay(40);
3530
3531                 ap->state = ANEG_STATE_ABILITY_DETECT;
3532                 break;
3533
3534         case ANEG_STATE_ABILITY_DETECT:
3535                 if (ap->ability_match != 0 && ap->rxconfig != 0)
3536                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3537                 break;
3538
3539         case ANEG_STATE_ACK_DETECT_INIT:
3540                 ap->txconfig |= ANEG_CFG_ACK;
3541                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3542                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3543                 tw32_f(MAC_MODE, tp->mac_mode);
3544                 udelay(40);
3545
3546                 ap->state = ANEG_STATE_ACK_DETECT;
3547
3548                 /* fallthru */
3549         case ANEG_STATE_ACK_DETECT:
3550                 if (ap->ack_match != 0) {
3551                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3552                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3553                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3554                         } else {
3555                                 ap->state = ANEG_STATE_AN_ENABLE;
3556                         }
3557                 } else if (ap->ability_match != 0 &&
3558                            ap->rxconfig == 0) {
3559                         ap->state = ANEG_STATE_AN_ENABLE;
3560                 }
3561                 break;
3562
3563         case ANEG_STATE_COMPLETE_ACK_INIT:
3564                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3565                         ret = ANEG_FAILED;
3566                         break;
3567                 }
3568                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3569                                MR_LP_ADV_HALF_DUPLEX |
3570                                MR_LP_ADV_SYM_PAUSE |
3571                                MR_LP_ADV_ASYM_PAUSE |
3572                                MR_LP_ADV_REMOTE_FAULT1 |
3573                                MR_LP_ADV_REMOTE_FAULT2 |
3574                                MR_LP_ADV_NEXT_PAGE |
3575                                MR_TOGGLE_RX |
3576                                MR_NP_RX);
3577                 if (ap->rxconfig & ANEG_CFG_FD)
3578                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3579                 if (ap->rxconfig & ANEG_CFG_HD)
3580                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3581                 if (ap->rxconfig & ANEG_CFG_PS1)
3582                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3583                 if (ap->rxconfig & ANEG_CFG_PS2)
3584                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3585                 if (ap->rxconfig & ANEG_CFG_RF1)
3586                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3587                 if (ap->rxconfig & ANEG_CFG_RF2)
3588                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3589                 if (ap->rxconfig & ANEG_CFG_NP)
3590                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3591
3592                 ap->link_time = ap->cur_time;
3593
3594                 ap->flags ^= (MR_TOGGLE_TX);
3595                 if (ap->rxconfig & 0x0008)
3596                         ap->flags |= MR_TOGGLE_RX;
3597                 if (ap->rxconfig & ANEG_CFG_NP)
3598                         ap->flags |= MR_NP_RX;
3599                 ap->flags |= MR_PAGE_RX;
3600
3601                 ap->state = ANEG_STATE_COMPLETE_ACK;
3602                 ret = ANEG_TIMER_ENAB;
3603                 break;
3604
3605         case ANEG_STATE_COMPLETE_ACK:
3606                 if (ap->ability_match != 0 &&
3607                     ap->rxconfig == 0) {
3608                         ap->state = ANEG_STATE_AN_ENABLE;
3609                         break;
3610                 }
3611                 delta = ap->cur_time - ap->link_time;
3612                 if (delta > ANEG_STATE_SETTLE_TIME) {
3613                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3614                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3615                         } else {
3616                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3617                                     !(ap->flags & MR_NP_RX)) {
3618                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3619                                 } else {
3620                                         ret = ANEG_FAILED;
3621                                 }
3622                         }
3623                 }
3624                 break;
3625
3626         case ANEG_STATE_IDLE_DETECT_INIT:
3627                 ap->link_time = ap->cur_time;
3628                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3629                 tw32_f(MAC_MODE, tp->mac_mode);
3630                 udelay(40);
3631
3632                 ap->state = ANEG_STATE_IDLE_DETECT;
3633                 ret = ANEG_TIMER_ENAB;
3634                 break;
3635
3636         case ANEG_STATE_IDLE_DETECT:
3637                 if (ap->ability_match != 0 &&
3638                     ap->rxconfig == 0) {
3639                         ap->state = ANEG_STATE_AN_ENABLE;
3640                         break;
3641                 }
3642                 delta = ap->cur_time - ap->link_time;
3643                 if (delta > ANEG_STATE_SETTLE_TIME) {
3644                         /* XXX another gem from the Broadcom driver :( */
3645                         ap->state = ANEG_STATE_LINK_OK;
3646                 }
3647                 break;
3648
3649         case ANEG_STATE_LINK_OK:
3650                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3651                 ret = ANEG_DONE;
3652                 break;
3653
3654         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3655                 /* ??? unimplemented */
3656                 break;
3657
3658         case ANEG_STATE_NEXT_PAGE_WAIT:
3659                 /* ??? unimplemented */
3660                 break;
3661
3662         default:
3663                 ret = ANEG_FAILED;
3664                 break;
3665         }
3666
3667         return ret;
3668 }
3669
3670 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3671 {
3672         int res = 0;
3673         struct tg3_fiber_aneginfo aninfo;
3674         int status = ANEG_FAILED;
3675         unsigned int tick;
3676         u32 tmp;
3677
3678         tw32_f(MAC_TX_AUTO_NEG, 0);
3679
3680         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3681         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3682         udelay(40);
3683
3684         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3685         udelay(40);
3686
3687         memset(&aninfo, 0, sizeof(aninfo));
3688         aninfo.flags |= MR_AN_ENABLE;
3689         aninfo.state = ANEG_STATE_UNKNOWN;
3690         aninfo.cur_time = 0;
3691         tick = 0;
3692         while (++tick < 195000) {
3693                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3694                 if (status == ANEG_DONE || status == ANEG_FAILED)
3695                         break;
3696
3697                 udelay(1);
3698         }
3699
3700         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3701         tw32_f(MAC_MODE, tp->mac_mode);
3702         udelay(40);
3703
3704         *txflags = aninfo.txconfig;
3705         *rxflags = aninfo.flags;
3706
3707         if (status == ANEG_DONE &&
3708             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3709                              MR_LP_ADV_FULL_DUPLEX)))
3710                 res = 1;
3711
3712         return res;
3713 }
3714
3715 static void tg3_init_bcm8002(struct tg3 *tp)
3716 {
3717         u32 mac_status = tr32(MAC_STATUS);
3718         int i;
3719
3720         /* Reset when initting first time or we have a link. */
3721         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3722             !(mac_status & MAC_STATUS_PCS_SYNCED))
3723                 return;
3724
3725         /* Set PLL lock range. */
3726         tg3_writephy(tp, 0x16, 0x8007);
3727
3728         /* SW reset */
3729         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3730
3731         /* Wait for reset to complete. */
3732         /* XXX schedule_timeout() ... */
3733         for (i = 0; i < 500; i++)
3734                 udelay(10);
3735
3736         /* Config mode; select PMA/Ch 1 regs. */
3737         tg3_writephy(tp, 0x10, 0x8411);
3738
3739         /* Enable auto-lock and comdet, select txclk for tx. */
3740         tg3_writephy(tp, 0x11, 0x0a10);
3741
3742         tg3_writephy(tp, 0x18, 0x00a0);
3743         tg3_writephy(tp, 0x16, 0x41ff);
3744
3745         /* Assert and deassert POR. */
3746         tg3_writephy(tp, 0x13, 0x0400);
3747         udelay(40);
3748         tg3_writephy(tp, 0x13, 0x0000);
3749
3750         tg3_writephy(tp, 0x11, 0x0a50);
3751         udelay(40);
3752         tg3_writephy(tp, 0x11, 0x0a10);
3753
3754         /* Wait for signal to stabilize */
3755         /* XXX schedule_timeout() ... */
3756         for (i = 0; i < 15000; i++)
3757                 udelay(10);
3758
3759         /* Deselect the channel register so we can read the PHYID
3760          * later.
3761          */
3762         tg3_writephy(tp, 0x10, 0x8011);
3763 }
3764
3765 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3766 {
3767         u16 flowctrl;
3768         u32 sg_dig_ctrl, sg_dig_status;
3769         u32 serdes_cfg, expected_sg_dig_ctrl;
3770         int workaround, port_a;
3771         int current_link_up;
3772
3773         serdes_cfg = 0;
3774         expected_sg_dig_ctrl = 0;
3775         workaround = 0;
3776         port_a = 1;
3777         current_link_up = 0;
3778
3779         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3780             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3781                 workaround = 1;
3782                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3783                         port_a = 0;
3784
3785                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3786                 /* preserve bits 20-23 for voltage regulator */
3787                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3788         }
3789
3790         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3791
3792         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3793                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3794                         if (workaround) {
3795                                 u32 val = serdes_cfg;
3796
3797                                 if (port_a)
3798                                         val |= 0xc010000;
3799                                 else
3800                                         val |= 0x4010000;
3801                                 tw32_f(MAC_SERDES_CFG, val);
3802                         }
3803
3804                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3805                 }
3806                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3807                         tg3_setup_flow_control(tp, 0, 0);
3808                         current_link_up = 1;
3809                 }
3810                 goto out;
3811         }
3812
3813         /* Want auto-negotiation.  */
3814         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3815
3816         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3817         if (flowctrl & ADVERTISE_1000XPAUSE)
3818                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3819         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3820                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3821
3822         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3823                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3824                     tp->serdes_counter &&
3825                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3826                                     MAC_STATUS_RCVD_CFG)) ==
3827                      MAC_STATUS_PCS_SYNCED)) {
3828                         tp->serdes_counter--;
3829                         current_link_up = 1;
3830                         goto out;
3831                 }
3832 restart_autoneg:
3833                 if (workaround)
3834                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3835                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3836                 udelay(5);
3837                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3838
3839                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3840                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3841         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3842                                  MAC_STATUS_SIGNAL_DET)) {
3843                 sg_dig_status = tr32(SG_DIG_STATUS);
3844                 mac_status = tr32(MAC_STATUS);
3845
3846                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3847                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3848                         u32 local_adv = 0, remote_adv = 0;
3849
3850                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3851                                 local_adv |= ADVERTISE_1000XPAUSE;
3852                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3853                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3854
3855                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3856                                 remote_adv |= LPA_1000XPAUSE;
3857                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3858                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3859
3860                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3861                         current_link_up = 1;
3862                         tp->serdes_counter = 0;
3863                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3864                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3865                         if (tp->serdes_counter)
3866                                 tp->serdes_counter--;
3867                         else {
3868                                 if (workaround) {
3869                                         u32 val = serdes_cfg;
3870
3871                                         if (port_a)
3872                                                 val |= 0xc010000;
3873                                         else
3874                                                 val |= 0x4010000;
3875
3876                                         tw32_f(MAC_SERDES_CFG, val);
3877                                 }
3878
3879                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3880                                 udelay(40);
3881
3882                                 /* Link parallel detection - link is up */
3883                                 /* only if we have PCS_SYNC and not */
3884                                 /* receiving config code words */
3885                                 mac_status = tr32(MAC_STATUS);
3886                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3887                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3888                                         tg3_setup_flow_control(tp, 0, 0);
3889                                         current_link_up = 1;
3890                                         tp->tg3_flags2 |=
3891                                                 TG3_FLG2_PARALLEL_DETECT;
3892                                         tp->serdes_counter =
3893                                                 SERDES_PARALLEL_DET_TIMEOUT;
3894                                 } else
3895                                         goto restart_autoneg;
3896                         }
3897                 }
3898         } else {
3899                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3900                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3901         }
3902
3903 out:
3904         return current_link_up;
3905 }
3906
3907 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3908 {
3909         int current_link_up = 0;
3910
3911         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3912                 goto out;
3913
3914         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3915                 u32 txflags, rxflags;
3916                 int i;
3917
3918                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3919                         u32 local_adv = 0, remote_adv = 0;
3920
3921                         if (txflags & ANEG_CFG_PS1)
3922                                 local_adv |= ADVERTISE_1000XPAUSE;
3923                         if (txflags & ANEG_CFG_PS2)
3924                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3925
3926                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3927                                 remote_adv |= LPA_1000XPAUSE;
3928                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3929                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3930
3931                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3932
3933                         current_link_up = 1;
3934                 }
3935                 for (i = 0; i < 30; i++) {
3936                         udelay(20);
3937                         tw32_f(MAC_STATUS,
3938                                (MAC_STATUS_SYNC_CHANGED |
3939                                 MAC_STATUS_CFG_CHANGED));
3940                         udelay(40);
3941                         if ((tr32(MAC_STATUS) &
3942                              (MAC_STATUS_SYNC_CHANGED |
3943                               MAC_STATUS_CFG_CHANGED)) == 0)
3944                                 break;
3945                 }
3946
3947                 mac_status = tr32(MAC_STATUS);
3948                 if (current_link_up == 0 &&
3949                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3950                     !(mac_status & MAC_STATUS_RCVD_CFG))
3951                         current_link_up = 1;
3952         } else {
3953                 tg3_setup_flow_control(tp, 0, 0);
3954
3955                 /* Forcing 1000FD link up. */
3956                 current_link_up = 1;
3957
3958                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3959                 udelay(40);
3960
3961                 tw32_f(MAC_MODE, tp->mac_mode);
3962                 udelay(40);
3963         }
3964
3965 out:
3966         return current_link_up;
3967 }
3968
3969 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3970 {
3971         u32 orig_pause_cfg;
3972         u16 orig_active_speed;
3973         u8 orig_active_duplex;
3974         u32 mac_status;
3975         int current_link_up;
3976         int i;
3977
3978         orig_pause_cfg = tp->link_config.active_flowctrl;
3979         orig_active_speed = tp->link_config.active_speed;
3980         orig_active_duplex = tp->link_config.active_duplex;
3981
3982         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3983             netif_carrier_ok(tp->dev) &&
3984             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3985                 mac_status = tr32(MAC_STATUS);
3986                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3987                                MAC_STATUS_SIGNAL_DET |
3988                                MAC_STATUS_CFG_CHANGED |
3989                                MAC_STATUS_RCVD_CFG);
3990                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3991                                    MAC_STATUS_SIGNAL_DET)) {
3992                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3993                                             MAC_STATUS_CFG_CHANGED));
3994                         return 0;
3995                 }
3996         }
3997
3998         tw32_f(MAC_TX_AUTO_NEG, 0);
3999
4000         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
4001         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
4002         tw32_f(MAC_MODE, tp->mac_mode);
4003         udelay(40);
4004
4005         if (tp->phy_id == TG3_PHY_ID_BCM8002)
4006                 tg3_init_bcm8002(tp);
4007
4008         /* Enable link change event even when serdes polling.  */
4009         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4010         udelay(40);
4011
4012         current_link_up = 0;
4013         mac_status = tr32(MAC_STATUS);
4014
4015         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
4016                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4017         else
4018                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4019
4020         tp->napi[0].hw_status->status =
4021                 (SD_STATUS_UPDATED |
4022                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4023
4024         for (i = 0; i < 100; i++) {
4025                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4026                                     MAC_STATUS_CFG_CHANGED));
4027                 udelay(5);
4028                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4029                                          MAC_STATUS_CFG_CHANGED |
4030                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4031                         break;
4032         }
4033
4034         mac_status = tr32(MAC_STATUS);
4035         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4036                 current_link_up = 0;
4037                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4038                     tp->serdes_counter == 0) {
4039                         tw32_f(MAC_MODE, (tp->mac_mode |
4040                                           MAC_MODE_SEND_CONFIGS));
4041                         udelay(1);
4042                         tw32_f(MAC_MODE, tp->mac_mode);
4043                 }
4044         }
4045
4046         if (current_link_up == 1) {
4047                 tp->link_config.active_speed = SPEED_1000;
4048                 tp->link_config.active_duplex = DUPLEX_FULL;
4049                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4050                                     LED_CTRL_LNKLED_OVERRIDE |
4051                                     LED_CTRL_1000MBPS_ON));
4052         } else {
4053                 tp->link_config.active_speed = SPEED_INVALID;
4054                 tp->link_config.active_duplex = DUPLEX_INVALID;
4055                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4056                                     LED_CTRL_LNKLED_OVERRIDE |
4057                                     LED_CTRL_TRAFFIC_OVERRIDE));
4058         }
4059
4060         if (current_link_up != netif_carrier_ok(tp->dev)) {
4061                 if (current_link_up)
4062                         netif_carrier_on(tp->dev);
4063                 else
4064                         netif_carrier_off(tp->dev);
4065                 tg3_link_report(tp);
4066         } else {
4067                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4068                 if (orig_pause_cfg != now_pause_cfg ||
4069                     orig_active_speed != tp->link_config.active_speed ||
4070                     orig_active_duplex != tp->link_config.active_duplex)
4071                         tg3_link_report(tp);
4072         }
4073
4074         return 0;
4075 }
4076
4077 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4078 {
4079         int current_link_up, err = 0;
4080         u32 bmsr, bmcr;
4081         u16 current_speed;
4082         u8 current_duplex;
4083         u32 local_adv, remote_adv;
4084
4085         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4086         tw32_f(MAC_MODE, tp->mac_mode);
4087         udelay(40);
4088
4089         tw32(MAC_EVENT, 0);
4090
4091         tw32_f(MAC_STATUS,
4092              (MAC_STATUS_SYNC_CHANGED |
4093               MAC_STATUS_CFG_CHANGED |
4094               MAC_STATUS_MI_COMPLETION |
4095               MAC_STATUS_LNKSTATE_CHANGED));
4096         udelay(40);
4097
4098         if (force_reset)
4099                 tg3_phy_reset(tp);
4100
4101         current_link_up = 0;
4102         current_speed = SPEED_INVALID;
4103         current_duplex = DUPLEX_INVALID;
4104
4105         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4106         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4107         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4108                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4109                         bmsr |= BMSR_LSTATUS;
4110                 else
4111                         bmsr &= ~BMSR_LSTATUS;
4112         }
4113
4114         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4115
4116         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4117             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4118                 /* do nothing, just check for link up at the end */
4119         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4120                 u32 adv, new_adv;
4121
4122                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4123                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4124                                   ADVERTISE_1000XPAUSE |
4125                                   ADVERTISE_1000XPSE_ASYM |
4126                                   ADVERTISE_SLCT);
4127
4128                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4129
4130                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4131                         new_adv |= ADVERTISE_1000XHALF;
4132                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4133                         new_adv |= ADVERTISE_1000XFULL;
4134
4135                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4136                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4137                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4138                         tg3_writephy(tp, MII_BMCR, bmcr);
4139
4140                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4141                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4142                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4143
4144                         return err;
4145                 }
4146         } else {
4147                 u32 new_bmcr;
4148
4149                 bmcr &= ~BMCR_SPEED1000;
4150                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4151
4152                 if (tp->link_config.duplex == DUPLEX_FULL)
4153                         new_bmcr |= BMCR_FULLDPLX;
4154
4155                 if (new_bmcr != bmcr) {
4156                         /* BMCR_SPEED1000 is a reserved bit that needs
4157                          * to be set on write.
4158                          */
4159                         new_bmcr |= BMCR_SPEED1000;
4160
4161                         /* Force a linkdown */
4162                         if (netif_carrier_ok(tp->dev)) {
4163                                 u32 adv;
4164
4165                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4166                                 adv &= ~(ADVERTISE_1000XFULL |
4167                                          ADVERTISE_1000XHALF |
4168                                          ADVERTISE_SLCT);
4169                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4170                                 tg3_writephy(tp, MII_BMCR, bmcr |
4171                                                            BMCR_ANRESTART |
4172                                                            BMCR_ANENABLE);
4173                                 udelay(10);
4174                                 netif_carrier_off(tp->dev);
4175                         }
4176                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4177                         bmcr = new_bmcr;
4178                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4179                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4180                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4181                             ASIC_REV_5714) {
4182                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4183                                         bmsr |= BMSR_LSTATUS;
4184                                 else
4185                                         bmsr &= ~BMSR_LSTATUS;
4186                         }
4187                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4188                 }
4189         }
4190
4191         if (bmsr & BMSR_LSTATUS) {
4192                 current_speed = SPEED_1000;
4193                 current_link_up = 1;
4194                 if (bmcr & BMCR_FULLDPLX)
4195                         current_duplex = DUPLEX_FULL;
4196                 else
4197                         current_duplex = DUPLEX_HALF;
4198
4199                 local_adv = 0;
4200                 remote_adv = 0;
4201
4202                 if (bmcr & BMCR_ANENABLE) {
4203                         u32 common;
4204
4205                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4206                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4207                         common = local_adv & remote_adv;
4208                         if (common & (ADVERTISE_1000XHALF |
4209                                       ADVERTISE_1000XFULL)) {
4210                                 if (common & ADVERTISE_1000XFULL)
4211                                         current_duplex = DUPLEX_FULL;
4212                                 else
4213                                         current_duplex = DUPLEX_HALF;
4214                         } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4215                                 /* Link is up via parallel detect */
4216                         } else {
4217                                 current_link_up = 0;
4218                         }
4219                 }
4220         }
4221
4222         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4223                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4224
4225         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4226         if (tp->link_config.active_duplex == DUPLEX_HALF)
4227                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4228
4229         tw32_f(MAC_MODE, tp->mac_mode);
4230         udelay(40);
4231
4232         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4233
4234         tp->link_config.active_speed = current_speed;
4235         tp->link_config.active_duplex = current_duplex;
4236
4237         if (current_link_up != netif_carrier_ok(tp->dev)) {
4238                 if (current_link_up)
4239                         netif_carrier_on(tp->dev);
4240                 else {
4241                         netif_carrier_off(tp->dev);
4242                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4243                 }
4244                 tg3_link_report(tp);
4245         }
4246         return err;
4247 }
4248
4249 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4250 {
4251         if (tp->serdes_counter) {
4252                 /* Give autoneg time to complete. */
4253                 tp->serdes_counter--;
4254                 return;
4255         }
4256
4257         if (!netif_carrier_ok(tp->dev) &&
4258             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4259                 u32 bmcr;
4260
4261                 tg3_readphy(tp, MII_BMCR, &bmcr);
4262                 if (bmcr & BMCR_ANENABLE) {
4263                         u32 phy1, phy2;
4264
4265                         /* Select shadow register 0x1f */
4266                         tg3_writephy(tp, 0x1c, 0x7c00);
4267                         tg3_readphy(tp, 0x1c, &phy1);
4268
4269                         /* Select expansion interrupt status register */
4270                         tg3_writephy(tp, 0x17, 0x0f01);
4271                         tg3_readphy(tp, 0x15, &phy2);
4272                         tg3_readphy(tp, 0x15, &phy2);
4273
4274                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4275                                 /* We have signal detect and not receiving
4276                                  * config code words, link is up by parallel
4277                                  * detection.
4278                                  */
4279
4280                                 bmcr &= ~BMCR_ANENABLE;
4281                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4282                                 tg3_writephy(tp, MII_BMCR, bmcr);
4283                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4284                         }
4285                 }
4286         } else if (netif_carrier_ok(tp->dev) &&
4287                    (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4288                    (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4289                 u32 phy2;
4290
4291                 /* Select expansion interrupt status register */
4292                 tg3_writephy(tp, 0x17, 0x0f01);
4293                 tg3_readphy(tp, 0x15, &phy2);
4294                 if (phy2 & 0x20) {
4295                         u32 bmcr;
4296
4297                         /* Config code words received, turn on autoneg. */
4298                         tg3_readphy(tp, MII_BMCR, &bmcr);
4299                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4300
4301                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4302
4303                 }
4304         }
4305 }
4306
4307 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4308 {
4309         int err;
4310
4311         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
4312                 err = tg3_setup_fiber_phy(tp, force_reset);
4313         else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
4314                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4315         else
4316                 err = tg3_setup_copper_phy(tp, force_reset);
4317
4318         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4319                 u32 val, scale;
4320
4321                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4322                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4323                         scale = 65;
4324                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4325                         scale = 6;
4326                 else
4327                         scale = 12;
4328
4329                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4330                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4331                 tw32(GRC_MISC_CFG, val);
4332         }
4333
4334         if (tp->link_config.active_speed == SPEED_1000 &&
4335             tp->link_config.active_duplex == DUPLEX_HALF)
4336                 tw32(MAC_TX_LENGTHS,
4337                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4338                       (6 << TX_LENGTHS_IPG_SHIFT) |
4339                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4340         else
4341                 tw32(MAC_TX_LENGTHS,
4342                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4343                       (6 << TX_LENGTHS_IPG_SHIFT) |
4344                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4345
4346         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4347                 if (netif_carrier_ok(tp->dev)) {
4348                         tw32(HOSTCC_STAT_COAL_TICKS,
4349                              tp->coal.stats_block_coalesce_usecs);
4350                 } else {
4351                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4352                 }
4353         }
4354
4355         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4356                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4357                 if (!netif_carrier_ok(tp->dev))
4358                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4359                               tp->pwrmgmt_thresh;
4360                 else
4361                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4362                 tw32(PCIE_PWR_MGMT_THRESH, val);
4363         }
4364
4365         return err;
4366 }
4367
4368 /* This is called whenever we suspect that the system chipset is re-
4369  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4370  * is bogus tx completions. We try to recover by setting the
4371  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4372  * in the workqueue.
4373  */
4374 static void tg3_tx_recover(struct tg3 *tp)
4375 {
4376         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4377                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4378
4379         netdev_warn(tp->dev,
4380                     "The system may be re-ordering memory-mapped I/O "
4381                     "cycles to the network device, attempting to recover. "
4382                     "Please report the problem to the driver maintainer "
4383                     "and include system chipset information.\n");
4384
4385         spin_lock(&tp->lock);
4386         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4387         spin_unlock(&tp->lock);
4388 }
4389
4390 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4391 {
4392         smp_mb();
4393         return tnapi->tx_pending -
4394                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4395 }
4396
4397 /* Tigon3 never reports partial packet sends.  So we do not
4398  * need special logic to handle SKBs that have not had all
4399  * of their frags sent yet, like SunGEM does.
4400  */
4401 static void tg3_tx(struct tg3_napi *tnapi)
4402 {
4403         struct tg3 *tp = tnapi->tp;
4404         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4405         u32 sw_idx = tnapi->tx_cons;
4406         struct netdev_queue *txq;
4407         int index = tnapi - tp->napi;
4408
4409         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4410                 index--;
4411
4412         txq = netdev_get_tx_queue(tp->dev, index);
4413
4414         while (sw_idx != hw_idx) {
4415                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4416                 struct sk_buff *skb = ri->skb;
4417                 int i, tx_bug = 0;
4418
4419                 if (unlikely(skb == NULL)) {
4420                         tg3_tx_recover(tp);
4421                         return;
4422                 }
4423
4424                 pci_unmap_single(tp->pdev,
4425                                  dma_unmap_addr(ri, mapping),
4426                                  skb_headlen(skb),
4427                                  PCI_DMA_TODEVICE);
4428
4429                 ri->skb = NULL;
4430
4431                 sw_idx = NEXT_TX(sw_idx);
4432
4433                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4434                         ri = &tnapi->tx_buffers[sw_idx];
4435                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4436                                 tx_bug = 1;
4437
4438                         pci_unmap_page(tp->pdev,
4439                                        dma_unmap_addr(ri, mapping),
4440                                        skb_shinfo(skb)->frags[i].size,
4441                                        PCI_DMA_TODEVICE);
4442                         sw_idx = NEXT_TX(sw_idx);
4443                 }
4444
4445                 dev_kfree_skb(skb);
4446
4447                 if (unlikely(tx_bug)) {
4448                         tg3_tx_recover(tp);
4449                         return;
4450                 }
4451         }
4452
4453         tnapi->tx_cons = sw_idx;
4454
4455         /* Need to make the tx_cons update visible to tg3_start_xmit()
4456          * before checking for netif_queue_stopped().  Without the
4457          * memory barrier, there is a small possibility that tg3_start_xmit()
4458          * will miss it and cause the queue to be stopped forever.
4459          */
4460         smp_mb();
4461
4462         if (unlikely(netif_tx_queue_stopped(txq) &&
4463                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4464                 __netif_tx_lock(txq, smp_processor_id());
4465                 if (netif_tx_queue_stopped(txq) &&
4466                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4467                         netif_tx_wake_queue(txq);
4468                 __netif_tx_unlock(txq);
4469         }
4470 }
4471
4472 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4473 {
4474         if (!ri->skb)
4475                 return;
4476
4477         pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4478                          map_sz, PCI_DMA_FROMDEVICE);
4479         dev_kfree_skb_any(ri->skb);
4480         ri->skb = NULL;
4481 }
4482
4483 /* Returns size of skb allocated or < 0 on error.
4484  *
4485  * We only need to fill in the address because the other members
4486  * of the RX descriptor are invariant, see tg3_init_rings.
4487  *
4488  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4489  * posting buffers we only dirty the first cache line of the RX
4490  * descriptor (containing the address).  Whereas for the RX status
4491  * buffers the cpu only reads the last cacheline of the RX descriptor
4492  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4493  */
4494 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4495                             u32 opaque_key, u32 dest_idx_unmasked)
4496 {
4497         struct tg3_rx_buffer_desc *desc;
4498         struct ring_info *map, *src_map;
4499         struct sk_buff *skb;
4500         dma_addr_t mapping;
4501         int skb_size, dest_idx;
4502
4503         src_map = NULL;
4504         switch (opaque_key) {
4505         case RXD_OPAQUE_RING_STD:
4506                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4507                 desc = &tpr->rx_std[dest_idx];
4508                 map = &tpr->rx_std_buffers[dest_idx];
4509                 skb_size = tp->rx_pkt_map_sz;
4510                 break;
4511
4512         case RXD_OPAQUE_RING_JUMBO:
4513                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4514                 desc = &tpr->rx_jmb[dest_idx].std;
4515                 map = &tpr->rx_jmb_buffers[dest_idx];
4516                 skb_size = TG3_RX_JMB_MAP_SZ;
4517                 break;
4518
4519         default:
4520                 return -EINVAL;
4521         }
4522
4523         /* Do not overwrite any of the map or rp information
4524          * until we are sure we can commit to a new buffer.
4525          *
4526          * Callers depend upon this behavior and assume that
4527          * we leave everything unchanged if we fail.
4528          */
4529         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4530         if (skb == NULL)
4531                 return -ENOMEM;
4532
4533         skb_reserve(skb, tp->rx_offset);
4534
4535         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4536                                  PCI_DMA_FROMDEVICE);
4537         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4538                 dev_kfree_skb(skb);
4539                 return -EIO;
4540         }
4541
4542         map->skb = skb;
4543         dma_unmap_addr_set(map, mapping, mapping);
4544
4545         desc->addr_hi = ((u64)mapping >> 32);
4546         desc->addr_lo = ((u64)mapping & 0xffffffff);
4547
4548         return skb_size;
4549 }
4550
4551 /* We only need to move over in the address because the other
4552  * members of the RX descriptor are invariant.  See notes above
4553  * tg3_alloc_rx_skb for full details.
4554  */
4555 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4556                            struct tg3_rx_prodring_set *dpr,
4557                            u32 opaque_key, int src_idx,
4558                            u32 dest_idx_unmasked)
4559 {
4560         struct tg3 *tp = tnapi->tp;
4561         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4562         struct ring_info *src_map, *dest_map;
4563         struct tg3_rx_prodring_set *spr = &tp->prodring[0];
4564         int dest_idx;
4565
4566         switch (opaque_key) {
4567         case RXD_OPAQUE_RING_STD:
4568                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4569                 dest_desc = &dpr->rx_std[dest_idx];
4570                 dest_map = &dpr->rx_std_buffers[dest_idx];
4571                 src_desc = &spr->rx_std[src_idx];
4572                 src_map = &spr->rx_std_buffers[src_idx];
4573                 break;
4574
4575         case RXD_OPAQUE_RING_JUMBO:
4576                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4577                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4578                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4579                 src_desc = &spr->rx_jmb[src_idx].std;
4580                 src_map = &spr->rx_jmb_buffers[src_idx];
4581                 break;
4582
4583         default:
4584                 return;
4585         }
4586
4587         dest_map->skb = src_map->skb;
4588         dma_unmap_addr_set(dest_map, mapping,
4589                            dma_unmap_addr(src_map, mapping));
4590         dest_desc->addr_hi = src_desc->addr_hi;
4591         dest_desc->addr_lo = src_desc->addr_lo;
4592
4593         /* Ensure that the update to the skb happens after the physical
4594          * addresses have been transferred to the new BD location.
4595          */
4596         smp_wmb();
4597
4598         src_map->skb = NULL;
4599 }
4600
4601 /* The RX ring scheme is composed of multiple rings which post fresh
4602  * buffers to the chip, and one special ring the chip uses to report
4603  * status back to the host.
4604  *
4605  * The special ring reports the status of received packets to the
4606  * host.  The chip does not write into the original descriptor the
4607  * RX buffer was obtained from.  The chip simply takes the original
4608  * descriptor as provided by the host, updates the status and length
4609  * field, then writes this into the next status ring entry.
4610  *
4611  * Each ring the host uses to post buffers to the chip is described
4612  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4613  * it is first placed into the on-chip ram.  When the packet's length
4614  * is known, it walks down the TG3_BDINFO entries to select the ring.
4615  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4616  * which is within the range of the new packet's length is chosen.
4617  *
4618  * The "separate ring for rx status" scheme may sound queer, but it makes
4619  * sense from a cache coherency perspective.  If only the host writes
4620  * to the buffer post rings, and only the chip writes to the rx status
4621  * rings, then cache lines never move beyond shared-modified state.
4622  * If both the host and chip were to write into the same ring, cache line
4623  * eviction could occur since both entities want it in an exclusive state.
4624  */
4625 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4626 {
4627         struct tg3 *tp = tnapi->tp;
4628         u32 work_mask, rx_std_posted = 0;
4629         u32 std_prod_idx, jmb_prod_idx;
4630         u32 sw_idx = tnapi->rx_rcb_ptr;
4631         u16 hw_idx;
4632         int received;
4633         struct tg3_rx_prodring_set *tpr = tnapi->prodring;
4634
4635         hw_idx = *(tnapi->rx_rcb_prod_idx);
4636         /*
4637          * We need to order the read of hw_idx and the read of
4638          * the opaque cookie.
4639          */
4640         rmb();
4641         work_mask = 0;
4642         received = 0;
4643         std_prod_idx = tpr->rx_std_prod_idx;
4644         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4645         while (sw_idx != hw_idx && budget > 0) {
4646                 struct ring_info *ri;
4647                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4648                 unsigned int len;
4649                 struct sk_buff *skb;
4650                 dma_addr_t dma_addr;
4651                 u32 opaque_key, desc_idx, *post_ptr;
4652                 bool hw_vlan __maybe_unused = false;
4653                 u16 vtag __maybe_unused = 0;
4654
4655                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4656                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4657                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4658                         ri = &tp->prodring[0].rx_std_buffers[desc_idx];
4659                         dma_addr = dma_unmap_addr(ri, mapping);
4660                         skb = ri->skb;
4661                         post_ptr = &std_prod_idx;
4662                         rx_std_posted++;
4663                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4664                         ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
4665                         dma_addr = dma_unmap_addr(ri, mapping);
4666                         skb = ri->skb;
4667                         post_ptr = &jmb_prod_idx;
4668                 } else
4669                         goto next_pkt_nopost;
4670
4671                 work_mask |= opaque_key;
4672
4673                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4674                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4675                 drop_it:
4676                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4677                                        desc_idx, *post_ptr);
4678                 drop_it_no_recycle:
4679                         /* Other statistics kept track of by card. */
4680                         tp->net_stats.rx_dropped++;
4681                         goto next_pkt;
4682                 }
4683
4684                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4685                       ETH_FCS_LEN;
4686
4687                 if (len > TG3_RX_COPY_THRESH(tp)) {
4688                         int skb_size;
4689
4690                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4691                                                     *post_ptr);
4692                         if (skb_size < 0)
4693                                 goto drop_it;
4694
4695                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4696                                          PCI_DMA_FROMDEVICE);
4697
4698                         /* Ensure that the update to the skb happens
4699                          * after the usage of the old DMA mapping.
4700                          */
4701                         smp_wmb();
4702
4703                         ri->skb = NULL;
4704
4705                         skb_put(skb, len);
4706                 } else {
4707                         struct sk_buff *copy_skb;
4708
4709                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4710                                        desc_idx, *post_ptr);
4711
4712                         copy_skb = netdev_alloc_skb(tp->dev, len + VLAN_HLEN +
4713                                                     TG3_RAW_IP_ALIGN);
4714                         if (copy_skb == NULL)
4715                                 goto drop_it_no_recycle;
4716
4717                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN + VLAN_HLEN);
4718                         skb_put(copy_skb, len);
4719                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4720                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4721                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4722
4723                         /* We'll reuse the original ring buffer. */
4724                         skb = copy_skb;
4725                 }
4726
4727                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4728                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4729                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4730                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4731                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4732                 else
4733                         skb->ip_summed = CHECKSUM_NONE;
4734
4735                 skb->protocol = eth_type_trans(skb, tp->dev);
4736
4737                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4738                     skb->protocol != htons(ETH_P_8021Q)) {
4739                         dev_kfree_skb(skb);
4740                         goto next_pkt;
4741                 }
4742
4743                 if (desc->type_flags & RXD_FLAG_VLAN &&
4744                     !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) {
4745                         vtag = desc->err_vlan & RXD_VLAN_MASK;
4746 #if TG3_VLAN_TAG_USED
4747                         if (tp->vlgrp)
4748                                 hw_vlan = true;
4749                         else
4750 #endif
4751                         {
4752                                 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
4753                                                     __skb_push(skb, VLAN_HLEN);
4754
4755                                 memmove(ve, skb->data + VLAN_HLEN,
4756                                         ETH_ALEN * 2);
4757                                 ve->h_vlan_proto = htons(ETH_P_8021Q);
4758                                 ve->h_vlan_TCI = htons(vtag);
4759                         }
4760                 }
4761
4762 #if TG3_VLAN_TAG_USED
4763                 if (hw_vlan)
4764                         vlan_gro_receive(&tnapi->napi, tp->vlgrp, vtag, skb);
4765                 else
4766 #endif
4767                         napi_gro_receive(&tnapi->napi, skb);
4768
4769                 received++;
4770                 budget--;
4771
4772 next_pkt:
4773                 (*post_ptr)++;
4774
4775                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4776                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4777                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4778                                      tpr->rx_std_prod_idx);
4779                         work_mask &= ~RXD_OPAQUE_RING_STD;
4780                         rx_std_posted = 0;
4781                 }
4782 next_pkt_nopost:
4783                 sw_idx++;
4784                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4785
4786                 /* Refresh hw_idx to see if there is new work */
4787                 if (sw_idx == hw_idx) {
4788                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4789                         rmb();
4790                 }
4791         }
4792
4793         /* ACK the status ring. */
4794         tnapi->rx_rcb_ptr = sw_idx;
4795         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4796
4797         /* Refill RX ring(s). */
4798         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4799                 if (work_mask & RXD_OPAQUE_RING_STD) {
4800                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4801                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4802                                      tpr->rx_std_prod_idx);
4803                 }
4804                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4805                         tpr->rx_jmb_prod_idx = jmb_prod_idx %
4806                                                TG3_RX_JUMBO_RING_SIZE;
4807                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4808                                      tpr->rx_jmb_prod_idx);
4809                 }
4810                 mmiowb();
4811         } else if (work_mask) {
4812                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4813                  * updated before the producer indices can be updated.
4814                  */
4815                 smp_wmb();
4816
4817                 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4818                 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
4819
4820                 if (tnapi != &tp->napi[1])
4821                         napi_schedule(&tp->napi[1].napi);
4822         }
4823
4824         return received;
4825 }
4826
4827 static void tg3_poll_link(struct tg3 *tp)
4828 {
4829         /* handle link change and other phy events */
4830         if (!(tp->tg3_flags &
4831               (TG3_FLAG_USE_LINKCHG_REG |
4832                TG3_FLAG_POLL_SERDES))) {
4833                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4834
4835                 if (sblk->status & SD_STATUS_LINK_CHG) {
4836                         sblk->status = SD_STATUS_UPDATED |
4837                                        (sblk->status & ~SD_STATUS_LINK_CHG);
4838                         spin_lock(&tp->lock);
4839                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4840                                 tw32_f(MAC_STATUS,
4841                                      (MAC_STATUS_SYNC_CHANGED |
4842                                       MAC_STATUS_CFG_CHANGED |
4843                                       MAC_STATUS_MI_COMPLETION |
4844                                       MAC_STATUS_LNKSTATE_CHANGED));
4845                                 udelay(40);
4846                         } else
4847                                 tg3_setup_phy(tp, 0);
4848                         spin_unlock(&tp->lock);
4849                 }
4850         }
4851 }
4852
4853 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4854                                 struct tg3_rx_prodring_set *dpr,
4855                                 struct tg3_rx_prodring_set *spr)
4856 {
4857         u32 si, di, cpycnt, src_prod_idx;
4858         int i, err = 0;
4859
4860         while (1) {
4861                 src_prod_idx = spr->rx_std_prod_idx;
4862
4863                 /* Make sure updates to the rx_std_buffers[] entries and the
4864                  * standard producer index are seen in the correct order.
4865                  */
4866                 smp_rmb();
4867
4868                 if (spr->rx_std_cons_idx == src_prod_idx)
4869                         break;
4870
4871                 if (spr->rx_std_cons_idx < src_prod_idx)
4872                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4873                 else
4874                         cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4875
4876                 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4877
4878                 si = spr->rx_std_cons_idx;
4879                 di = dpr->rx_std_prod_idx;
4880
4881                 for (i = di; i < di + cpycnt; i++) {
4882                         if (dpr->rx_std_buffers[i].skb) {
4883                                 cpycnt = i - di;
4884                                 err = -ENOSPC;
4885                                 break;
4886                         }
4887                 }
4888
4889                 if (!cpycnt)
4890                         break;
4891
4892                 /* Ensure that updates to the rx_std_buffers ring and the
4893                  * shadowed hardware producer ring from tg3_recycle_skb() are
4894                  * ordered correctly WRT the skb check above.
4895                  */
4896                 smp_rmb();
4897
4898                 memcpy(&dpr->rx_std_buffers[di],
4899                        &spr->rx_std_buffers[si],
4900                        cpycnt * sizeof(struct ring_info));
4901
4902                 for (i = 0; i < cpycnt; i++, di++, si++) {
4903                         struct tg3_rx_buffer_desc *sbd, *dbd;
4904                         sbd = &spr->rx_std[si];
4905                         dbd = &dpr->rx_std[di];
4906                         dbd->addr_hi = sbd->addr_hi;
4907                         dbd->addr_lo = sbd->addr_lo;
4908                 }
4909
4910                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4911                                        TG3_RX_RING_SIZE;
4912                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4913                                        TG3_RX_RING_SIZE;
4914         }
4915
4916         while (1) {
4917                 src_prod_idx = spr->rx_jmb_prod_idx;
4918
4919                 /* Make sure updates to the rx_jmb_buffers[] entries and
4920                  * the jumbo producer index are seen in the correct order.
4921                  */
4922                 smp_rmb();
4923
4924                 if (spr->rx_jmb_cons_idx == src_prod_idx)
4925                         break;
4926
4927                 if (spr->rx_jmb_cons_idx < src_prod_idx)
4928                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4929                 else
4930                         cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4931
4932                 cpycnt = min(cpycnt,
4933                              TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4934
4935                 si = spr->rx_jmb_cons_idx;
4936                 di = dpr->rx_jmb_prod_idx;
4937
4938                 for (i = di; i < di + cpycnt; i++) {
4939                         if (dpr->rx_jmb_buffers[i].skb) {
4940                                 cpycnt = i - di;
4941                                 err = -ENOSPC;
4942                                 break;
4943                         }
4944                 }
4945
4946                 if (!cpycnt)
4947                         break;
4948
4949                 /* Ensure that updates to the rx_jmb_buffers ring and the
4950                  * shadowed hardware producer ring from tg3_recycle_skb() are
4951                  * ordered correctly WRT the skb check above.
4952                  */
4953                 smp_rmb();
4954
4955                 memcpy(&dpr->rx_jmb_buffers[di],
4956                        &spr->rx_jmb_buffers[si],
4957                        cpycnt * sizeof(struct ring_info));
4958
4959                 for (i = 0; i < cpycnt; i++, di++, si++) {
4960                         struct tg3_rx_buffer_desc *sbd, *dbd;
4961                         sbd = &spr->rx_jmb[si].std;
4962                         dbd = &dpr->rx_jmb[di].std;
4963                         dbd->addr_hi = sbd->addr_hi;
4964                         dbd->addr_lo = sbd->addr_lo;
4965                 }
4966
4967                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4968                                        TG3_RX_JUMBO_RING_SIZE;
4969                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4970                                        TG3_RX_JUMBO_RING_SIZE;
4971         }
4972
4973         return err;
4974 }
4975
4976 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4977 {
4978         struct tg3 *tp = tnapi->tp;
4979
4980         /* run TX completion thread */
4981         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4982                 tg3_tx(tnapi);
4983                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4984                         return work_done;
4985         }
4986
4987         /* run RX thread, within the bounds set by NAPI.
4988          * All RX "locking" is done by ensuring outside
4989          * code synchronizes with tg3->napi.poll()
4990          */
4991         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4992                 work_done += tg3_rx(tnapi, budget - work_done);
4993
4994         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4995                 struct tg3_rx_prodring_set *dpr = &tp->prodring[0];
4996                 int i, err = 0;
4997                 u32 std_prod_idx = dpr->rx_std_prod_idx;
4998                 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
4999
5000                 for (i = 1; i < tp->irq_cnt; i++)
5001                         err |= tg3_rx_prodring_xfer(tp, dpr,
5002                                                     tp->napi[i].prodring);
5003
5004                 wmb();
5005
5006                 if (std_prod_idx != dpr->rx_std_prod_idx)
5007                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5008                                      dpr->rx_std_prod_idx);
5009
5010                 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5011                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5012                                      dpr->rx_jmb_prod_idx);
5013
5014                 mmiowb();
5015
5016                 if (err)
5017                         tw32_f(HOSTCC_MODE, tp->coal_now);
5018         }
5019
5020         return work_done;
5021 }
5022
5023 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5024 {
5025         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5026         struct tg3 *tp = tnapi->tp;
5027         int work_done = 0;
5028         struct tg3_hw_status *sblk = tnapi->hw_status;
5029
5030         while (1) {
5031                 work_done = tg3_poll_work(tnapi, work_done, budget);
5032
5033                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5034                         goto tx_recovery;
5035
5036                 if (unlikely(work_done >= budget))
5037                         break;
5038
5039                 /* tp->last_tag is used in tg3_int_reenable() below
5040                  * to tell the hw how much work has been processed,
5041                  * so we must read it before checking for more work.
5042                  */
5043                 tnapi->last_tag = sblk->status_tag;
5044                 tnapi->last_irq_tag = tnapi->last_tag;
5045                 rmb();
5046
5047                 /* check for RX/TX work to do */
5048                 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5049                            *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5050                         napi_complete(napi);
5051                         /* Reenable interrupts. */
5052                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5053                         mmiowb();
5054                         break;
5055                 }
5056         }
5057
5058         return work_done;
5059
5060 tx_recovery:
5061         /* work_done is guaranteed to be less than budget. */
5062         napi_complete(napi);
5063         schedule_work(&tp->reset_task);
5064         return work_done;
5065 }
5066
5067 static int tg3_poll(struct napi_struct *napi, int budget)
5068 {
5069         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5070         struct tg3 *tp = tnapi->tp;
5071         int work_done = 0;
5072         struct tg3_hw_status *sblk = tnapi->hw_status;
5073
5074         while (1) {
5075                 tg3_poll_link(tp);
5076
5077                 work_done = tg3_poll_work(tnapi, work_done, budget);
5078
5079                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5080                         goto tx_recovery;
5081
5082                 if (unlikely(work_done >= budget))
5083                         break;
5084
5085                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5086                         /* tp->last_tag is used in tg3_int_reenable() below
5087                          * to tell the hw how much work has been processed,
5088                          * so we must read it before checking for more work.
5089                          */
5090                         tnapi->last_tag = sblk->status_tag;
5091                         tnapi->last_irq_tag = tnapi->last_tag;
5092                         rmb();
5093                 } else
5094                         sblk->status &= ~SD_STATUS_UPDATED;
5095
5096                 if (likely(!tg3_has_work(tnapi))) {
5097                         napi_complete(napi);
5098                         tg3_int_reenable(tnapi);
5099                         break;
5100                 }
5101         }
5102
5103         return work_done;
5104
5105 tx_recovery:
5106         /* work_done is guaranteed to be less than budget. */
5107         napi_complete(napi);
5108         schedule_work(&tp->reset_task);
5109         return work_done;
5110 }
5111
5112 static void tg3_irq_quiesce(struct tg3 *tp)
5113 {
5114         int i;
5115
5116         BUG_ON(tp->irq_sync);
5117
5118         tp->irq_sync = 1;
5119         smp_mb();
5120
5121         for (i = 0; i < tp->irq_cnt; i++)
5122                 synchronize_irq(tp->napi[i].irq_vec);
5123 }
5124
5125 static inline int tg3_irq_sync(struct tg3 *tp)
5126 {
5127         return tp->irq_sync;
5128 }
5129
5130 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5131  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5132  * with as well.  Most of the time, this is not necessary except when
5133  * shutting down the device.
5134  */
5135 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5136 {
5137         spin_lock_bh(&tp->lock);
5138         if (irq_sync)
5139                 tg3_irq_quiesce(tp);
5140 }
5141
5142 static inline void tg3_full_unlock(struct tg3 *tp)
5143 {
5144         spin_unlock_bh(&tp->lock);
5145 }
5146
5147 /* One-shot MSI handler - Chip automatically disables interrupt
5148  * after sending MSI so driver doesn't have to do it.
5149  */
5150 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5151 {
5152         struct tg3_napi *tnapi = dev_id;
5153         struct tg3 *tp = tnapi->tp;
5154
5155         prefetch(tnapi->hw_status);
5156         if (tnapi->rx_rcb)
5157                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5158
5159         if (likely(!tg3_irq_sync(tp)))
5160                 napi_schedule(&tnapi->napi);
5161
5162         return IRQ_HANDLED;
5163 }
5164
5165 /* MSI ISR - No need to check for interrupt sharing and no need to
5166  * flush status block and interrupt mailbox. PCI ordering rules
5167  * guarantee that MSI will arrive after the status block.
5168  */
5169 static irqreturn_t tg3_msi(int irq, void *dev_id)
5170 {
5171         struct tg3_napi *tnapi = dev_id;
5172         struct tg3 *tp = tnapi->tp;
5173
5174         prefetch(tnapi->hw_status);
5175         if (tnapi->rx_rcb)
5176                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5177         /*
5178          * Writing any value to intr-mbox-0 clears PCI INTA# and
5179          * chip-internal interrupt pending events.
5180          * Writing non-zero to intr-mbox-0 additional tells the
5181          * NIC to stop sending us irqs, engaging "in-intr-handler"
5182          * event coalescing.
5183          */
5184         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5185         if (likely(!tg3_irq_sync(tp)))
5186                 napi_schedule(&tnapi->napi);
5187
5188         return IRQ_RETVAL(1);
5189 }
5190
5191 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5192 {
5193         struct tg3_napi *tnapi = dev_id;
5194         struct tg3 *tp = tnapi->tp;
5195         struct tg3_hw_status *sblk = tnapi->hw_status;
5196         unsigned int handled = 1;
5197
5198         /* In INTx mode, it is possible for the interrupt to arrive at
5199          * the CPU before the status block posted prior to the interrupt.
5200          * Reading the PCI State register will confirm whether the
5201          * interrupt is ours and will flush the status block.
5202          */
5203         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5204                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5205                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5206                         handled = 0;
5207                         goto out;
5208                 }
5209         }
5210
5211         /*
5212          * Writing any value to intr-mbox-0 clears PCI INTA# and
5213          * chip-internal interrupt pending events.
5214          * Writing non-zero to intr-mbox-0 additional tells the
5215          * NIC to stop sending us irqs, engaging "in-intr-handler"
5216          * event coalescing.
5217          *
5218          * Flush the mailbox to de-assert the IRQ immediately to prevent
5219          * spurious interrupts.  The flush impacts performance but
5220          * excessive spurious interrupts can be worse in some cases.
5221          */
5222         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5223         if (tg3_irq_sync(tp))
5224                 goto out;
5225         sblk->status &= ~SD_STATUS_UPDATED;
5226         if (likely(tg3_has_work(tnapi))) {
5227                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5228                 napi_schedule(&tnapi->napi);
5229         } else {
5230                 /* No work, shared interrupt perhaps?  re-enable
5231                  * interrupts, and flush that PCI write
5232                  */
5233                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5234                                0x00000000);
5235         }
5236 out:
5237         return IRQ_RETVAL(handled);
5238 }
5239
5240 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5241 {
5242         struct tg3_napi *tnapi = dev_id;
5243         struct tg3 *tp = tnapi->tp;
5244         struct tg3_hw_status *sblk = tnapi->hw_status;
5245         unsigned int handled = 1;
5246
5247         /* In INTx mode, it is possible for the interrupt to arrive at
5248          * the CPU before the status block posted prior to the interrupt.
5249          * Reading the PCI State register will confirm whether the
5250          * interrupt is ours and will flush the status block.
5251          */
5252         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5253                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5254                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5255                         handled = 0;
5256                         goto out;
5257                 }
5258         }
5259
5260         /*
5261          * writing any value to intr-mbox-0 clears PCI INTA# and
5262          * chip-internal interrupt pending events.
5263          * writing non-zero to intr-mbox-0 additional tells the
5264          * NIC to stop sending us irqs, engaging "in-intr-handler"
5265          * event coalescing.
5266          *
5267          * Flush the mailbox to de-assert the IRQ immediately to prevent
5268          * spurious interrupts.  The flush impacts performance but
5269          * excessive spurious interrupts can be worse in some cases.
5270          */
5271         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5272
5273         /*
5274          * In a shared interrupt configuration, sometimes other devices'
5275          * interrupts will scream.  We record the current status tag here
5276          * so that the above check can report that the screaming interrupts
5277          * are unhandled.  Eventually they will be silenced.
5278          */
5279         tnapi->last_irq_tag = sblk->status_tag;
5280
5281         if (tg3_irq_sync(tp))
5282                 goto out;
5283
5284         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5285
5286         napi_schedule(&tnapi->napi);
5287
5288 out:
5289         return IRQ_RETVAL(handled);
5290 }
5291
5292 /* ISR for interrupt test */
5293 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5294 {
5295         struct tg3_napi *tnapi = dev_id;
5296         struct tg3 *tp = tnapi->tp;
5297         struct tg3_hw_status *sblk = tnapi->hw_status;
5298
5299         if ((sblk->status & SD_STATUS_UPDATED) ||
5300             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5301                 tg3_disable_ints(tp);
5302                 return IRQ_RETVAL(1);
5303         }
5304         return IRQ_RETVAL(0);
5305 }
5306
5307 static int tg3_init_hw(struct tg3 *, int);
5308 static int tg3_halt(struct tg3 *, int, int);
5309
5310 /* Restart hardware after configuration changes, self-test, etc.
5311  * Invoked with tp->lock held.
5312  */
5313 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5314         __releases(tp->lock)
5315         __acquires(tp->lock)
5316 {
5317         int err;
5318
5319         err = tg3_init_hw(tp, reset_phy);
5320         if (err) {
5321                 netdev_err(tp->dev,
5322                            "Failed to re-initialize device, aborting\n");
5323                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5324                 tg3_full_unlock(tp);
5325                 del_timer_sync(&tp->timer);
5326                 tp->irq_sync = 0;
5327                 tg3_napi_enable(tp);
5328                 dev_close(tp->dev);
5329                 tg3_full_lock(tp, 0);
5330         }
5331         return err;
5332 }
5333
5334 #ifdef CONFIG_NET_POLL_CONTROLLER
5335 static void tg3_poll_controller(struct net_device *dev)
5336 {
5337         int i;
5338         struct tg3 *tp = netdev_priv(dev);
5339
5340         for (i = 0; i < tp->irq_cnt; i++)
5341                 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5342 }
5343 #endif
5344
5345 static void tg3_reset_task(struct work_struct *work)
5346 {
5347         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5348         int err;
5349         unsigned int restart_timer;
5350
5351         tg3_full_lock(tp, 0);
5352
5353         if (!netif_running(tp->dev)) {
5354                 tg3_full_unlock(tp);
5355                 return;
5356         }
5357
5358         tg3_full_unlock(tp);
5359
5360         tg3_phy_stop(tp);
5361
5362         tg3_netif_stop(tp);
5363
5364         tg3_full_lock(tp, 1);
5365
5366         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5367         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5368
5369         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5370                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5371                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5372                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5373                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5374         }
5375
5376         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5377         err = tg3_init_hw(tp, 1);
5378         if (err)
5379                 goto out;
5380
5381         tg3_netif_start(tp);
5382
5383         if (restart_timer)
5384                 mod_timer(&tp->timer, jiffies + 1);
5385
5386 out:
5387         tg3_full_unlock(tp);
5388
5389         if (!err)
5390                 tg3_phy_start(tp);
5391 }
5392
5393 static void tg3_dump_short_state(struct tg3 *tp)
5394 {
5395         netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5396                    tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5397         netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5398                    tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5399 }
5400
5401 static void tg3_tx_timeout(struct net_device *dev)
5402 {
5403         struct tg3 *tp = netdev_priv(dev);
5404
5405         if (netif_msg_tx_err(tp)) {
5406                 netdev_err(dev, "transmit timed out, resetting\n");
5407                 tg3_dump_short_state(tp);
5408         }
5409
5410         schedule_work(&tp->reset_task);
5411 }
5412
5413 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5414 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5415 {
5416         u32 base = (u32) mapping & 0xffffffff;
5417
5418         return ((base > 0xffffdcc0) &&
5419                 (base + len + 8 < base));
5420 }
5421
5422 /* Test for DMA addresses > 40-bit */
5423 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5424                                           int len)
5425 {
5426 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5427         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5428                 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5429         return 0;
5430 #else
5431         return 0;
5432 #endif
5433 }
5434
5435 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5436
5437 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5438 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5439                                        struct sk_buff *skb, u32 last_plus_one,
5440                                        u32 *start, u32 base_flags, u32 mss)
5441 {
5442         struct tg3 *tp = tnapi->tp;
5443         struct sk_buff *new_skb;
5444         dma_addr_t new_addr = 0;
5445         u32 entry = *start;
5446         int i, ret = 0;
5447
5448         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5449                 new_skb = skb_copy(skb, GFP_ATOMIC);
5450         else {
5451                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5452
5453                 new_skb = skb_copy_expand(skb,
5454                                           skb_headroom(skb) + more_headroom,
5455                                           skb_tailroom(skb), GFP_ATOMIC);
5456         }
5457
5458         if (!new_skb) {
5459                 ret = -1;
5460         } else {
5461                 /* New SKB is guaranteed to be linear. */
5462                 entry = *start;
5463                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5464                                           PCI_DMA_TODEVICE);
5465                 /* Make sure the mapping succeeded */
5466                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5467                         ret = -1;
5468                         dev_kfree_skb(new_skb);
5469                         new_skb = NULL;
5470
5471                 /* Make sure new skb does not cross any 4G boundaries.
5472                  * Drop the packet if it does.
5473                  */
5474                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5475                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5476                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5477                                          PCI_DMA_TODEVICE);
5478                         ret = -1;
5479                         dev_kfree_skb(new_skb);
5480                         new_skb = NULL;
5481                 } else {
5482                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5483                                     base_flags, 1 | (mss << 1));
5484                         *start = NEXT_TX(entry);
5485                 }
5486         }
5487
5488         /* Now clean up the sw ring entries. */
5489         i = 0;
5490         while (entry != last_plus_one) {
5491                 int len;
5492
5493                 if (i == 0)
5494                         len = skb_headlen(skb);
5495                 else
5496                         len = skb_shinfo(skb)->frags[i-1].size;
5497
5498                 pci_unmap_single(tp->pdev,
5499                                  dma_unmap_addr(&tnapi->tx_buffers[entry],
5500                                                 mapping),
5501                                  len, PCI_DMA_TODEVICE);
5502                 if (i == 0) {
5503                         tnapi->tx_buffers[entry].skb = new_skb;
5504                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5505                                            new_addr);
5506                 } else {
5507                         tnapi->tx_buffers[entry].skb = NULL;
5508                 }
5509                 entry = NEXT_TX(entry);
5510                 i++;
5511         }
5512
5513         dev_kfree_skb(skb);
5514
5515         return ret;
5516 }
5517
5518 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5519                         dma_addr_t mapping, int len, u32 flags,
5520                         u32 mss_and_is_end)
5521 {
5522         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5523         int is_end = (mss_and_is_end & 0x1);
5524         u32 mss = (mss_and_is_end >> 1);
5525         u32 vlan_tag = 0;
5526
5527         if (is_end)
5528                 flags |= TXD_FLAG_END;
5529         if (flags & TXD_FLAG_VLAN) {
5530                 vlan_tag = flags >> 16;
5531                 flags &= 0xffff;
5532         }
5533         vlan_tag |= (mss << TXD_MSS_SHIFT);
5534
5535         txd->addr_hi = ((u64) mapping >> 32);
5536         txd->addr_lo = ((u64) mapping & 0xffffffff);
5537         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5538         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5539 }
5540
5541 /* hard_start_xmit for devices that don't have any bugs and
5542  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5543  */
5544 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5545                                   struct net_device *dev)
5546 {
5547         struct tg3 *tp = netdev_priv(dev);
5548         u32 len, entry, base_flags, mss;
5549         dma_addr_t mapping;
5550         struct tg3_napi *tnapi;
5551         struct netdev_queue *txq;
5552         unsigned int i, last;
5553
5554         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5555         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5556         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5557                 tnapi++;
5558
5559         /* We are running in BH disabled context with netif_tx_lock
5560          * and TX reclaim runs via tp->napi.poll inside of a software
5561          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5562          * no IRQ context deadlocks to worry about either.  Rejoice!
5563          */
5564         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5565                 if (!netif_tx_queue_stopped(txq)) {
5566                         netif_tx_stop_queue(txq);
5567
5568                         /* This is a hard error, log it. */
5569                         netdev_err(dev,
5570                                    "BUG! Tx Ring full when queue awake!\n");
5571                 }
5572                 return NETDEV_TX_BUSY;
5573         }
5574
5575         entry = tnapi->tx_prod;
5576         base_flags = 0;
5577         mss = 0;
5578         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5579                 int tcp_opt_len, ip_tcp_len;
5580                 u32 hdrlen;
5581
5582                 if (skb_header_cloned(skb) &&
5583                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5584                         dev_kfree_skb(skb);
5585                         goto out_unlock;
5586                 }
5587
5588                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5589                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5590                 else {
5591                         struct iphdr *iph = ip_hdr(skb);
5592
5593                         tcp_opt_len = tcp_optlen(skb);
5594                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5595
5596                         iph->check = 0;
5597                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5598                         hdrlen = ip_tcp_len + tcp_opt_len;
5599                 }
5600
5601                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5602                         mss |= (hdrlen & 0xc) << 12;
5603                         if (hdrlen & 0x10)
5604                                 base_flags |= 0x00000010;
5605                         base_flags |= (hdrlen & 0x3e0) << 5;
5606                 } else
5607                         mss |= hdrlen << 9;
5608
5609                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5610                                TXD_FLAG_CPU_POST_DMA);
5611
5612                 tcp_hdr(skb)->check = 0;
5613
5614         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5615                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5616         }
5617
5618 #if TG3_VLAN_TAG_USED
5619         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5620                 base_flags |= (TXD_FLAG_VLAN |
5621                                (vlan_tx_tag_get(skb) << 16));
5622 #endif
5623
5624         len = skb_headlen(skb);
5625
5626         /* Queue skb data, a.k.a. the main skb fragment. */
5627         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5628         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5629                 dev_kfree_skb(skb);
5630                 goto out_unlock;
5631         }
5632
5633         tnapi->tx_buffers[entry].skb = skb;
5634         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5635
5636         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5637             !mss && skb->len > ETH_DATA_LEN)
5638                 base_flags |= TXD_FLAG_JMB_PKT;
5639
5640         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5641                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5642
5643         entry = NEXT_TX(entry);
5644
5645         /* Now loop through additional data fragments, and queue them. */
5646         if (skb_shinfo(skb)->nr_frags > 0) {
5647                 last = skb_shinfo(skb)->nr_frags - 1;
5648                 for (i = 0; i <= last; i++) {
5649                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5650
5651                         len = frag->size;
5652                         mapping = pci_map_page(tp->pdev,
5653                                                frag->page,
5654                                                frag->page_offset,
5655                                                len, PCI_DMA_TODEVICE);
5656                         if (pci_dma_mapping_error(tp->pdev, mapping))
5657                                 goto dma_error;
5658
5659                         tnapi->tx_buffers[entry].skb = NULL;
5660                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5661                                            mapping);
5662
5663                         tg3_set_txd(tnapi, entry, mapping, len,
5664                                     base_flags, (i == last) | (mss << 1));
5665
5666                         entry = NEXT_TX(entry);
5667                 }
5668         }
5669
5670         /* Packets are ready, update Tx producer idx local and on card. */
5671         tw32_tx_mbox(tnapi->prodmbox, entry);
5672
5673         tnapi->tx_prod = entry;
5674         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5675                 netif_tx_stop_queue(txq);
5676                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5677                         netif_tx_wake_queue(txq);
5678         }
5679
5680 out_unlock:
5681         mmiowb();
5682
5683         return NETDEV_TX_OK;
5684
5685 dma_error:
5686         last = i;
5687         entry = tnapi->tx_prod;
5688         tnapi->tx_buffers[entry].skb = NULL;
5689         pci_unmap_single(tp->pdev,
5690                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5691                          skb_headlen(skb),
5692                          PCI_DMA_TODEVICE);
5693         for (i = 0; i <= last; i++) {
5694                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5695                 entry = NEXT_TX(entry);
5696
5697                 pci_unmap_page(tp->pdev,
5698                                dma_unmap_addr(&tnapi->tx_buffers[entry],
5699                                               mapping),
5700                                frag->size, PCI_DMA_TODEVICE);
5701         }
5702
5703         dev_kfree_skb(skb);
5704         return NETDEV_TX_OK;
5705 }
5706
5707 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5708                                           struct net_device *);
5709
5710 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5711  * TSO header is greater than 80 bytes.
5712  */
5713 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5714 {
5715         struct sk_buff *segs, *nskb;
5716         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5717
5718         /* Estimate the number of fragments in the worst case */
5719         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5720                 netif_stop_queue(tp->dev);
5721                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5722                         return NETDEV_TX_BUSY;
5723
5724                 netif_wake_queue(tp->dev);
5725         }
5726
5727         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5728         if (IS_ERR(segs))
5729                 goto tg3_tso_bug_end;
5730
5731         do {
5732                 nskb = segs;
5733                 segs = segs->next;
5734                 nskb->next = NULL;
5735                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5736         } while (segs);
5737
5738 tg3_tso_bug_end:
5739         dev_kfree_skb(skb);
5740
5741         return NETDEV_TX_OK;
5742 }
5743
5744 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5745  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5746  */
5747 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5748                                           struct net_device *dev)
5749 {
5750         struct tg3 *tp = netdev_priv(dev);
5751         u32 len, entry, base_flags, mss;
5752         int would_hit_hwbug;
5753         dma_addr_t mapping;
5754         struct tg3_napi *tnapi;
5755         struct netdev_queue *txq;
5756         unsigned int i, last;
5757
5758         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5759         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5760         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5761                 tnapi++;
5762
5763         /* We are running in BH disabled context with netif_tx_lock
5764          * and TX reclaim runs via tp->napi.poll inside of a software
5765          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5766          * no IRQ context deadlocks to worry about either.  Rejoice!
5767          */
5768         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5769                 if (!netif_tx_queue_stopped(txq)) {
5770                         netif_tx_stop_queue(txq);
5771
5772                         /* This is a hard error, log it. */
5773                         netdev_err(dev,
5774                                    "BUG! Tx Ring full when queue awake!\n");
5775                 }
5776                 return NETDEV_TX_BUSY;
5777         }
5778
5779         entry = tnapi->tx_prod;
5780         base_flags = 0;
5781         if (skb->ip_summed == CHECKSUM_PARTIAL)
5782                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5783
5784         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5785                 struct iphdr *iph;
5786                 u32 tcp_opt_len, hdr_len;
5787
5788                 if (skb_header_cloned(skb) &&
5789                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5790                         dev_kfree_skb(skb);
5791                         goto out_unlock;
5792                 }
5793
5794                 iph = ip_hdr(skb);
5795                 tcp_opt_len = tcp_optlen(skb);
5796
5797                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
5798                         hdr_len = skb_headlen(skb) - ETH_HLEN;
5799                 } else {
5800                         u32 ip_tcp_len;
5801
5802                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5803                         hdr_len = ip_tcp_len + tcp_opt_len;
5804
5805                         iph->check = 0;
5806                         iph->tot_len = htons(mss + hdr_len);
5807                 }
5808
5809                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5810                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5811                         return tg3_tso_bug(tp, skb);
5812
5813                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5814                                TXD_FLAG_CPU_POST_DMA);
5815
5816                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5817                         tcp_hdr(skb)->check = 0;
5818                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5819                 } else
5820                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5821                                                                  iph->daddr, 0,
5822                                                                  IPPROTO_TCP,
5823                                                                  0);
5824
5825                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5826                         mss |= (hdr_len & 0xc) << 12;
5827                         if (hdr_len & 0x10)
5828                                 base_flags |= 0x00000010;
5829                         base_flags |= (hdr_len & 0x3e0) << 5;
5830                 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5831                         mss |= hdr_len << 9;
5832                 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5833                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5834                         if (tcp_opt_len || iph->ihl > 5) {
5835                                 int tsflags;
5836
5837                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5838                                 mss |= (tsflags << 11);
5839                         }
5840                 } else {
5841                         if (tcp_opt_len || iph->ihl > 5) {
5842                                 int tsflags;
5843
5844                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5845                                 base_flags |= tsflags << 12;
5846                         }
5847                 }
5848         }
5849 #if TG3_VLAN_TAG_USED
5850         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5851                 base_flags |= (TXD_FLAG_VLAN |
5852                                (vlan_tx_tag_get(skb) << 16));
5853 #endif
5854
5855         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5856             !mss && skb->len > ETH_DATA_LEN)
5857                 base_flags |= TXD_FLAG_JMB_PKT;
5858
5859         len = skb_headlen(skb);
5860
5861         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5862         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5863                 dev_kfree_skb(skb);
5864                 goto out_unlock;
5865         }
5866
5867         tnapi->tx_buffers[entry].skb = skb;
5868         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5869
5870         would_hit_hwbug = 0;
5871
5872         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5873                 would_hit_hwbug = 1;
5874
5875         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5876             tg3_4g_overflow_test(mapping, len))
5877                 would_hit_hwbug = 1;
5878
5879         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5880             tg3_40bit_overflow_test(tp, mapping, len))
5881                 would_hit_hwbug = 1;
5882
5883         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5884                 would_hit_hwbug = 1;
5885
5886         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5887                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5888
5889         entry = NEXT_TX(entry);
5890
5891         /* Now loop through additional data fragments, and queue them. */
5892         if (skb_shinfo(skb)->nr_frags > 0) {
5893                 last = skb_shinfo(skb)->nr_frags - 1;
5894                 for (i = 0; i <= last; i++) {
5895                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5896
5897                         len = frag->size;
5898                         mapping = pci_map_page(tp->pdev,
5899                                                frag->page,
5900                                                frag->page_offset,
5901                                                len, PCI_DMA_TODEVICE);
5902
5903                         tnapi->tx_buffers[entry].skb = NULL;
5904                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5905                                            mapping);
5906                         if (pci_dma_mapping_error(tp->pdev, mapping))
5907                                 goto dma_error;
5908
5909                         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5910                             len <= 8)
5911                                 would_hit_hwbug = 1;
5912
5913                         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5914                             tg3_4g_overflow_test(mapping, len))
5915                                 would_hit_hwbug = 1;
5916
5917                         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5918                             tg3_40bit_overflow_test(tp, mapping, len))
5919                                 would_hit_hwbug = 1;
5920
5921                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5922                                 tg3_set_txd(tnapi, entry, mapping, len,
5923                                             base_flags, (i == last)|(mss << 1));
5924                         else
5925                                 tg3_set_txd(tnapi, entry, mapping, len,
5926                                             base_flags, (i == last));
5927
5928                         entry = NEXT_TX(entry);
5929                 }
5930         }
5931
5932         if (would_hit_hwbug) {
5933                 u32 last_plus_one = entry;
5934                 u32 start;
5935
5936                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5937                 start &= (TG3_TX_RING_SIZE - 1);
5938
5939                 /* If the workaround fails due to memory/mapping
5940                  * failure, silently drop this packet.
5941                  */
5942                 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
5943                                                 &start, base_flags, mss))
5944                         goto out_unlock;
5945
5946                 entry = start;
5947         }
5948
5949         /* Packets are ready, update Tx producer idx local and on card. */
5950         tw32_tx_mbox(tnapi->prodmbox, entry);
5951
5952         tnapi->tx_prod = entry;
5953         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5954                 netif_tx_stop_queue(txq);
5955                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5956                         netif_tx_wake_queue(txq);
5957         }
5958
5959 out_unlock:
5960         mmiowb();
5961
5962         return NETDEV_TX_OK;
5963
5964 dma_error:
5965         last = i;
5966         entry = tnapi->tx_prod;
5967         tnapi->tx_buffers[entry].skb = NULL;
5968         pci_unmap_single(tp->pdev,
5969                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5970                          skb_headlen(skb),
5971                          PCI_DMA_TODEVICE);
5972         for (i = 0; i <= last; i++) {
5973                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5974                 entry = NEXT_TX(entry);
5975
5976                 pci_unmap_page(tp->pdev,
5977                                dma_unmap_addr(&tnapi->tx_buffers[entry],
5978                                               mapping),
5979                                frag->size, PCI_DMA_TODEVICE);
5980         }
5981
5982         dev_kfree_skb(skb);
5983         return NETDEV_TX_OK;
5984 }
5985
5986 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5987                                int new_mtu)
5988 {
5989         dev->mtu = new_mtu;
5990
5991         if (new_mtu > ETH_DATA_LEN) {
5992                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5993                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5994                         ethtool_op_set_tso(dev, 0);
5995                 } else {
5996                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5997                 }
5998         } else {
5999                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6000                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
6001                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
6002         }
6003 }
6004
6005 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
6006 {
6007         struct tg3 *tp = netdev_priv(dev);
6008         int err;
6009
6010         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
6011                 return -EINVAL;
6012
6013         if (!netif_running(dev)) {
6014                 /* We'll just catch it later when the
6015                  * device is up'd.
6016                  */
6017                 tg3_set_mtu(dev, tp, new_mtu);
6018                 return 0;
6019         }
6020
6021         tg3_phy_stop(tp);
6022
6023         tg3_netif_stop(tp);
6024
6025         tg3_full_lock(tp, 1);
6026
6027         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6028
6029         tg3_set_mtu(dev, tp, new_mtu);
6030
6031         err = tg3_restart_hw(tp, 0);
6032
6033         if (!err)
6034                 tg3_netif_start(tp);
6035
6036         tg3_full_unlock(tp);
6037
6038         if (!err)
6039                 tg3_phy_start(tp);
6040
6041         return err;
6042 }
6043
6044 static void tg3_rx_prodring_free(struct tg3 *tp,
6045                                  struct tg3_rx_prodring_set *tpr)
6046 {
6047         int i;
6048
6049         if (tpr != &tp->prodring[0]) {
6050                 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
6051                      i = (i + 1) % TG3_RX_RING_SIZE)
6052                         tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6053                                         tp->rx_pkt_map_sz);
6054
6055                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6056                         for (i = tpr->rx_jmb_cons_idx;
6057                              i != tpr->rx_jmb_prod_idx;
6058                              i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
6059                                 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6060                                                 TG3_RX_JMB_MAP_SZ);
6061                         }
6062                 }
6063
6064                 return;
6065         }
6066
6067         for (i = 0; i < TG3_RX_RING_SIZE; i++)
6068                 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6069                                 tp->rx_pkt_map_sz);
6070
6071         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6072                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
6073                         tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6074                                         TG3_RX_JMB_MAP_SZ);
6075         }
6076 }
6077
6078 /* Initialize rx rings for packet processing.
6079  *
6080  * The chip has been shut down and the driver detached from
6081  * the networking, so no interrupts or new tx packets will
6082  * end up in the driver.  tp->{tx,}lock are held and thus
6083  * we may not sleep.
6084  */
6085 static int tg3_rx_prodring_alloc(struct tg3 *tp,
6086                                  struct tg3_rx_prodring_set *tpr)
6087 {
6088         u32 i, rx_pkt_dma_sz;
6089
6090         tpr->rx_std_cons_idx = 0;
6091         tpr->rx_std_prod_idx = 0;
6092         tpr->rx_jmb_cons_idx = 0;
6093         tpr->rx_jmb_prod_idx = 0;
6094
6095         if (tpr != &tp->prodring[0]) {
6096                 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
6097                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
6098                         memset(&tpr->rx_jmb_buffers[0], 0,
6099                                TG3_RX_JMB_BUFF_RING_SIZE);
6100                 goto done;
6101         }
6102
6103         /* Zero out all descriptors. */
6104         memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
6105
6106         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6107         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
6108             tp->dev->mtu > ETH_DATA_LEN)
6109                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6110         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6111
6112         /* Initialize invariants of the rings, we only set this
6113          * stuff once.  This works because the card does not
6114          * write into the rx buffer posting rings.
6115          */
6116         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
6117                 struct tg3_rx_buffer_desc *rxd;
6118
6119                 rxd = &tpr->rx_std[i];
6120                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6121                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6122                 rxd->opaque = (RXD_OPAQUE_RING_STD |
6123                                (i << RXD_OPAQUE_INDEX_SHIFT));
6124         }
6125
6126         /* Now allocate fresh SKBs for each rx ring. */
6127         for (i = 0; i < tp->rx_pending; i++) {
6128                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6129                         netdev_warn(tp->dev,
6130                                     "Using a smaller RX standard ring. Only "
6131                                     "%d out of %d buffers were allocated "
6132                                     "successfully\n", i, tp->rx_pending);
6133                         if (i == 0)
6134                                 goto initfail;
6135                         tp->rx_pending = i;
6136                         break;
6137                 }
6138         }
6139
6140         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6141                 goto done;
6142
6143         memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
6144
6145         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
6146                 goto done;
6147
6148         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
6149                 struct tg3_rx_buffer_desc *rxd;
6150
6151                 rxd = &tpr->rx_jmb[i].std;
6152                 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6153                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6154                                   RXD_FLAG_JUMBO;
6155                 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6156                        (i << RXD_OPAQUE_INDEX_SHIFT));
6157         }
6158
6159         for (i = 0; i < tp->rx_jumbo_pending; i++) {
6160                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
6161                         netdev_warn(tp->dev,
6162                                     "Using a smaller RX jumbo ring. Only %d "
6163                                     "out of %d buffers were allocated "
6164                                     "successfully\n", i, tp->rx_jumbo_pending);
6165                         if (i == 0)
6166                                 goto initfail;
6167                         tp->rx_jumbo_pending = i;
6168                         break;
6169                 }
6170         }
6171
6172 done:
6173         return 0;
6174
6175 initfail:
6176         tg3_rx_prodring_free(tp, tpr);
6177         return -ENOMEM;
6178 }
6179
6180 static void tg3_rx_prodring_fini(struct tg3 *tp,
6181                                  struct tg3_rx_prodring_set *tpr)
6182 {
6183         kfree(tpr->rx_std_buffers);
6184         tpr->rx_std_buffers = NULL;
6185         kfree(tpr->rx_jmb_buffers);
6186         tpr->rx_jmb_buffers = NULL;
6187         if (tpr->rx_std) {
6188                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
6189                                     tpr->rx_std, tpr->rx_std_mapping);
6190                 tpr->rx_std = NULL;
6191         }
6192         if (tpr->rx_jmb) {
6193                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
6194                                     tpr->rx_jmb, tpr->rx_jmb_mapping);
6195                 tpr->rx_jmb = NULL;
6196         }
6197 }
6198
6199 static int tg3_rx_prodring_init(struct tg3 *tp,
6200                                 struct tg3_rx_prodring_set *tpr)
6201 {
6202         tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
6203         if (!tpr->rx_std_buffers)
6204                 return -ENOMEM;
6205
6206         tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6207                                            &tpr->rx_std_mapping);
6208         if (!tpr->rx_std)
6209                 goto err_out;
6210
6211         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6212                 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
6213                                               GFP_KERNEL);
6214                 if (!tpr->rx_jmb_buffers)
6215                         goto err_out;
6216
6217                 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6218                                                    TG3_RX_JUMBO_RING_BYTES,
6219                                                    &tpr->rx_jmb_mapping);
6220                 if (!tpr->rx_jmb)
6221                         goto err_out;
6222         }
6223
6224         return 0;
6225
6226 err_out:
6227         tg3_rx_prodring_fini(tp, tpr);
6228         return -ENOMEM;
6229 }
6230
6231 /* Free up pending packets in all rx/tx rings.
6232  *
6233  * The chip has been shut down and the driver detached from
6234  * the networking, so no interrupts or new tx packets will
6235  * end up in the driver.  tp->{tx,}lock is not held and we are not
6236  * in an interrupt context and thus may sleep.
6237  */
6238 static void tg3_free_rings(struct tg3 *tp)
6239 {
6240         int i, j;
6241
6242         for (j = 0; j < tp->irq_cnt; j++) {
6243                 struct tg3_napi *tnapi = &tp->napi[j];
6244
6245                 tg3_rx_prodring_free(tp, &tp->prodring[j]);
6246
6247                 if (!tnapi->tx_buffers)
6248                         continue;
6249
6250                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6251                         struct ring_info *txp;
6252                         struct sk_buff *skb;
6253                         unsigned int k;
6254
6255                         txp = &tnapi->tx_buffers[i];
6256                         skb = txp->skb;
6257
6258                         if (skb == NULL) {
6259                                 i++;
6260                                 continue;
6261                         }
6262
6263                         pci_unmap_single(tp->pdev,
6264                                          dma_unmap_addr(txp, mapping),
6265                                          skb_headlen(skb),
6266                                          PCI_DMA_TODEVICE);
6267                         txp->skb = NULL;
6268
6269                         i++;
6270
6271                         for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6272                                 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6273                                 pci_unmap_page(tp->pdev,
6274                                                dma_unmap_addr(txp, mapping),
6275                                                skb_shinfo(skb)->frags[k].size,
6276                                                PCI_DMA_TODEVICE);
6277                                 i++;
6278                         }
6279
6280                         dev_kfree_skb_any(skb);
6281                 }
6282         }
6283 }
6284
6285 /* Initialize tx/rx rings for packet processing.
6286  *
6287  * The chip has been shut down and the driver detached from
6288  * the networking, so no interrupts or new tx packets will
6289  * end up in the driver.  tp->{tx,}lock are held and thus
6290  * we may not sleep.
6291  */
6292 static int tg3_init_rings(struct tg3 *tp)
6293 {
6294         int i;
6295
6296         /* Free up all the SKBs. */
6297         tg3_free_rings(tp);
6298
6299         for (i = 0; i < tp->irq_cnt; i++) {
6300                 struct tg3_napi *tnapi = &tp->napi[i];
6301
6302                 tnapi->last_tag = 0;
6303                 tnapi->last_irq_tag = 0;
6304                 tnapi->hw_status->status = 0;
6305                 tnapi->hw_status->status_tag = 0;
6306                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6307
6308                 tnapi->tx_prod = 0;
6309                 tnapi->tx_cons = 0;
6310                 if (tnapi->tx_ring)
6311                         memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6312
6313                 tnapi->rx_rcb_ptr = 0;
6314                 if (tnapi->rx_rcb)
6315                         memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6316
6317                 if (tg3_rx_prodring_alloc(tp, &tp->prodring[i])) {
6318                         tg3_free_rings(tp);
6319                         return -ENOMEM;
6320                 }
6321         }
6322
6323         return 0;
6324 }
6325
6326 /*
6327  * Must not be invoked with interrupt sources disabled and
6328  * the hardware shutdown down.
6329  */
6330 static void tg3_free_consistent(struct tg3 *tp)
6331 {
6332         int i;
6333
6334         for (i = 0; i < tp->irq_cnt; i++) {
6335                 struct tg3_napi *tnapi = &tp->napi[i];
6336
6337                 if (tnapi->tx_ring) {
6338                         pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6339                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
6340                         tnapi->tx_ring = NULL;
6341                 }
6342
6343                 kfree(tnapi->tx_buffers);
6344                 tnapi->tx_buffers = NULL;
6345
6346                 if (tnapi->rx_rcb) {
6347                         pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6348                                             tnapi->rx_rcb,
6349                                             tnapi->rx_rcb_mapping);
6350                         tnapi->rx_rcb = NULL;
6351                 }
6352
6353                 if (tnapi->hw_status) {
6354                         pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6355                                             tnapi->hw_status,
6356                                             tnapi->status_mapping);
6357                         tnapi->hw_status = NULL;
6358                 }
6359         }
6360
6361         if (tp->hw_stats) {
6362                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6363                                     tp->hw_stats, tp->stats_mapping);
6364                 tp->hw_stats = NULL;
6365         }
6366
6367         for (i = 0; i < tp->irq_cnt; i++)
6368                 tg3_rx_prodring_fini(tp, &tp->prodring[i]);
6369 }
6370
6371 /*
6372  * Must not be invoked with interrupt sources disabled and
6373  * the hardware shutdown down.  Can sleep.
6374  */
6375 static int tg3_alloc_consistent(struct tg3 *tp)
6376 {
6377         int i;
6378
6379         for (i = 0; i < tp->irq_cnt; i++) {
6380                 if (tg3_rx_prodring_init(tp, &tp->prodring[i]))
6381                         goto err_out;
6382         }
6383
6384         tp->hw_stats = pci_alloc_consistent(tp->pdev,
6385                                             sizeof(struct tg3_hw_stats),
6386                                             &tp->stats_mapping);
6387         if (!tp->hw_stats)
6388                 goto err_out;
6389
6390         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6391
6392         for (i = 0; i < tp->irq_cnt; i++) {
6393                 struct tg3_napi *tnapi = &tp->napi[i];
6394                 struct tg3_hw_status *sblk;
6395
6396                 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6397                                                         TG3_HW_STATUS_SIZE,
6398                                                         &tnapi->status_mapping);
6399                 if (!tnapi->hw_status)
6400                         goto err_out;
6401
6402                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6403                 sblk = tnapi->hw_status;
6404
6405                 /* If multivector TSS is enabled, vector 0 does not handle
6406                  * tx interrupts.  Don't allocate any resources for it.
6407                  */
6408                 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6409                     (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6410                         tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6411                                                     TG3_TX_RING_SIZE,
6412                                                     GFP_KERNEL);
6413                         if (!tnapi->tx_buffers)
6414                                 goto err_out;
6415
6416                         tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6417                                                               TG3_TX_RING_BYTES,
6418                                                        &tnapi->tx_desc_mapping);
6419                         if (!tnapi->tx_ring)
6420                                 goto err_out;
6421                 }
6422
6423                 /*
6424                  * When RSS is enabled, the status block format changes
6425                  * slightly.  The "rx_jumbo_consumer", "reserved",
6426                  * and "rx_mini_consumer" members get mapped to the
6427                  * other three rx return ring producer indexes.
6428                  */
6429                 switch (i) {
6430                 default:
6431                         tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6432                         break;
6433                 case 2:
6434                         tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6435                         break;
6436                 case 3:
6437                         tnapi->rx_rcb_prod_idx = &sblk->reserved;
6438                         break;
6439                 case 4:
6440                         tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6441                         break;
6442                 }
6443
6444                 tnapi->prodring = &tp->prodring[i];
6445
6446                 /*
6447                  * If multivector RSS is enabled, vector 0 does not handle
6448                  * rx or tx interrupts.  Don't allocate any resources for it.
6449                  */
6450                 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6451                         continue;
6452
6453                 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6454                                                      TG3_RX_RCB_RING_BYTES(tp),
6455                                                      &tnapi->rx_rcb_mapping);
6456                 if (!tnapi->rx_rcb)
6457                         goto err_out;
6458
6459                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6460         }
6461
6462         return 0;
6463
6464 err_out:
6465         tg3_free_consistent(tp);
6466         return -ENOMEM;
6467 }
6468
6469 #define MAX_WAIT_CNT 1000
6470
6471 /* To stop a block, clear the enable bit and poll till it
6472  * clears.  tp->lock is held.
6473  */
6474 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6475 {
6476         unsigned int i;
6477         u32 val;
6478
6479         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6480                 switch (ofs) {
6481                 case RCVLSC_MODE:
6482                 case DMAC_MODE:
6483                 case MBFREE_MODE:
6484                 case BUFMGR_MODE:
6485                 case MEMARB_MODE:
6486                         /* We can't enable/disable these bits of the
6487                          * 5705/5750, just say success.
6488                          */
6489                         return 0;
6490
6491                 default:
6492                         break;
6493                 }
6494         }
6495
6496         val = tr32(ofs);
6497         val &= ~enable_bit;
6498         tw32_f(ofs, val);
6499
6500         for (i = 0; i < MAX_WAIT_CNT; i++) {
6501                 udelay(100);
6502                 val = tr32(ofs);
6503                 if ((val & enable_bit) == 0)
6504                         break;
6505         }
6506
6507         if (i == MAX_WAIT_CNT && !silent) {
6508                 dev_err(&tp->pdev->dev,
6509                         "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6510                         ofs, enable_bit);
6511                 return -ENODEV;
6512         }
6513
6514         return 0;
6515 }
6516
6517 /* tp->lock is held. */
6518 static int tg3_abort_hw(struct tg3 *tp, int silent)
6519 {
6520         int i, err;
6521
6522         tg3_disable_ints(tp);
6523
6524         tp->rx_mode &= ~RX_MODE_ENABLE;
6525         tw32_f(MAC_RX_MODE, tp->rx_mode);
6526         udelay(10);
6527
6528         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6529         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6530         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6531         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6532         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6533         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6534
6535         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6536         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6537         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6538         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6539         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6540         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6541         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6542
6543         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6544         tw32_f(MAC_MODE, tp->mac_mode);
6545         udelay(40);
6546
6547         tp->tx_mode &= ~TX_MODE_ENABLE;
6548         tw32_f(MAC_TX_MODE, tp->tx_mode);
6549
6550         for (i = 0; i < MAX_WAIT_CNT; i++) {
6551                 udelay(100);
6552                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6553                         break;
6554         }
6555         if (i >= MAX_WAIT_CNT) {
6556                 dev_err(&tp->pdev->dev,
6557                         "%s timed out, TX_MODE_ENABLE will not clear "
6558                         "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
6559                 err |= -ENODEV;
6560         }
6561
6562         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6563         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6564         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6565
6566         tw32(FTQ_RESET, 0xffffffff);
6567         tw32(FTQ_RESET, 0x00000000);
6568
6569         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6570         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6571
6572         for (i = 0; i < tp->irq_cnt; i++) {
6573                 struct tg3_napi *tnapi = &tp->napi[i];
6574                 if (tnapi->hw_status)
6575                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6576         }
6577         if (tp->hw_stats)
6578                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6579
6580         return err;
6581 }
6582
6583 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6584 {
6585         int i;
6586         u32 apedata;
6587
6588         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6589         if (apedata != APE_SEG_SIG_MAGIC)
6590                 return;
6591
6592         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6593         if (!(apedata & APE_FW_STATUS_READY))
6594                 return;
6595
6596         /* Wait for up to 1 millisecond for APE to service previous event. */
6597         for (i = 0; i < 10; i++) {
6598                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6599                         return;
6600
6601                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6602
6603                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6604                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6605                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6606
6607                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6608
6609                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6610                         break;
6611
6612                 udelay(100);
6613         }
6614
6615         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6616                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6617 }
6618
6619 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6620 {
6621         u32 event;
6622         u32 apedata;
6623
6624         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6625                 return;
6626
6627         switch (kind) {
6628         case RESET_KIND_INIT:
6629                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6630                                 APE_HOST_SEG_SIG_MAGIC);
6631                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6632                                 APE_HOST_SEG_LEN_MAGIC);
6633                 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6634                 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6635                 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6636                         APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
6637                 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6638                                 APE_HOST_BEHAV_NO_PHYLOCK);
6639
6640                 event = APE_EVENT_STATUS_STATE_START;
6641                 break;
6642         case RESET_KIND_SHUTDOWN:
6643                 /* With the interface we are currently using,
6644                  * APE does not track driver state.  Wiping
6645                  * out the HOST SEGMENT SIGNATURE forces
6646                  * the APE to assume OS absent status.
6647                  */
6648                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6649
6650                 event = APE_EVENT_STATUS_STATE_UNLOAD;
6651                 break;
6652         case RESET_KIND_SUSPEND:
6653                 event = APE_EVENT_STATUS_STATE_SUSPEND;
6654                 break;
6655         default:
6656                 return;
6657         }
6658
6659         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6660
6661         tg3_ape_send_event(tp, event);
6662 }
6663
6664 /* tp->lock is held. */
6665 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6666 {
6667         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6668                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6669
6670         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6671                 switch (kind) {
6672                 case RESET_KIND_INIT:
6673                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6674                                       DRV_STATE_START);
6675                         break;
6676
6677                 case RESET_KIND_SHUTDOWN:
6678                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6679                                       DRV_STATE_UNLOAD);
6680                         break;
6681
6682                 case RESET_KIND_SUSPEND:
6683                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6684                                       DRV_STATE_SUSPEND);
6685                         break;
6686
6687                 default:
6688                         break;
6689                 }
6690         }
6691
6692         if (kind == RESET_KIND_INIT ||
6693             kind == RESET_KIND_SUSPEND)
6694                 tg3_ape_driver_state_change(tp, kind);
6695 }
6696
6697 /* tp->lock is held. */
6698 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6699 {
6700         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6701                 switch (kind) {
6702                 case RESET_KIND_INIT:
6703                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6704                                       DRV_STATE_START_DONE);
6705                         break;
6706
6707                 case RESET_KIND_SHUTDOWN:
6708                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6709                                       DRV_STATE_UNLOAD_DONE);
6710                         break;
6711
6712                 default:
6713                         break;
6714                 }
6715         }
6716
6717         if (kind == RESET_KIND_SHUTDOWN)
6718                 tg3_ape_driver_state_change(tp, kind);
6719 }
6720
6721 /* tp->lock is held. */
6722 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6723 {
6724         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6725                 switch (kind) {
6726                 case RESET_KIND_INIT:
6727                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6728                                       DRV_STATE_START);
6729                         break;
6730
6731                 case RESET_KIND_SHUTDOWN:
6732                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6733                                       DRV_STATE_UNLOAD);
6734                         break;
6735
6736                 case RESET_KIND_SUSPEND:
6737                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6738                                       DRV_STATE_SUSPEND);
6739                         break;
6740
6741                 default:
6742                         break;
6743                 }
6744         }
6745 }
6746
6747 static int tg3_poll_fw(struct tg3 *tp)
6748 {
6749         int i;
6750         u32 val;
6751
6752         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6753                 /* Wait up to 20ms for init done. */
6754                 for (i = 0; i < 200; i++) {
6755                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6756                                 return 0;
6757                         udelay(100);
6758                 }
6759                 return -ENODEV;
6760         }
6761
6762         /* Wait for firmware initialization to complete. */
6763         for (i = 0; i < 100000; i++) {
6764                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6765                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6766                         break;
6767                 udelay(10);
6768         }
6769
6770         /* Chip might not be fitted with firmware.  Some Sun onboard
6771          * parts are configured like that.  So don't signal the timeout
6772          * of the above loop as an error, but do report the lack of
6773          * running firmware once.
6774          */
6775         if (i >= 100000 &&
6776             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6777                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6778
6779                 netdev_info(tp->dev, "No firmware running\n");
6780         }
6781
6782         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6783                 /* The 57765 A0 needs a little more
6784                  * time to do some important work.
6785                  */
6786                 mdelay(10);
6787         }
6788
6789         return 0;
6790 }
6791
6792 /* Save PCI command register before chip reset */
6793 static void tg3_save_pci_state(struct tg3 *tp)
6794 {
6795         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6796 }
6797
6798 /* Restore PCI state after chip reset */
6799 static void tg3_restore_pci_state(struct tg3 *tp)
6800 {
6801         u32 val;
6802
6803         /* Re-enable indirect register accesses. */
6804         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6805                                tp->misc_host_ctrl);
6806
6807         /* Set MAX PCI retry to zero. */
6808         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6809         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6810             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6811                 val |= PCISTATE_RETRY_SAME_DMA;
6812         /* Allow reads and writes to the APE register and memory space. */
6813         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6814                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6815                        PCISTATE_ALLOW_APE_SHMEM_WR |
6816                        PCISTATE_ALLOW_APE_PSPACE_WR;
6817         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6818
6819         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6820
6821         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6822                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6823                         pcie_set_readrq(tp->pdev, 4096);
6824                 else {
6825                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6826                                               tp->pci_cacheline_sz);
6827                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6828                                               tp->pci_lat_timer);
6829                 }
6830         }
6831
6832         /* Make sure PCI-X relaxed ordering bit is clear. */
6833         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6834                 u16 pcix_cmd;
6835
6836                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6837                                      &pcix_cmd);
6838                 pcix_cmd &= ~PCI_X_CMD_ERO;
6839                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6840                                       pcix_cmd);
6841         }
6842
6843         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6844
6845                 /* Chip reset on 5780 will reset MSI enable bit,
6846                  * so need to restore it.
6847                  */
6848                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6849                         u16 ctrl;
6850
6851                         pci_read_config_word(tp->pdev,
6852                                              tp->msi_cap + PCI_MSI_FLAGS,
6853                                              &ctrl);
6854                         pci_write_config_word(tp->pdev,
6855                                               tp->msi_cap + PCI_MSI_FLAGS,
6856                                               ctrl | PCI_MSI_FLAGS_ENABLE);
6857                         val = tr32(MSGINT_MODE);
6858                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6859                 }
6860         }
6861 }
6862
6863 static void tg3_stop_fw(struct tg3 *);
6864
6865 /* tp->lock is held. */
6866 static int tg3_chip_reset(struct tg3 *tp)
6867 {
6868         u32 val;
6869         void (*write_op)(struct tg3 *, u32, u32);
6870         int i, err;
6871
6872         tg3_nvram_lock(tp);
6873
6874         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6875
6876         /* No matching tg3_nvram_unlock() after this because
6877          * chip reset below will undo the nvram lock.
6878          */
6879         tp->nvram_lock_cnt = 0;
6880
6881         /* GRC_MISC_CFG core clock reset will clear the memory
6882          * enable bit in PCI register 4 and the MSI enable bit
6883          * on some chips, so we save relevant registers here.
6884          */
6885         tg3_save_pci_state(tp);
6886
6887         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6888             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6889                 tw32(GRC_FASTBOOT_PC, 0);
6890
6891         /*
6892          * We must avoid the readl() that normally takes place.
6893          * It locks machines, causes machine checks, and other
6894          * fun things.  So, temporarily disable the 5701
6895          * hardware workaround, while we do the reset.
6896          */
6897         write_op = tp->write32;
6898         if (write_op == tg3_write_flush_reg32)
6899                 tp->write32 = tg3_write32;
6900
6901         /* Prevent the irq handler from reading or writing PCI registers
6902          * during chip reset when the memory enable bit in the PCI command
6903          * register may be cleared.  The chip does not generate interrupt
6904          * at this time, but the irq handler may still be called due to irq
6905          * sharing or irqpoll.
6906          */
6907         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6908         for (i = 0; i < tp->irq_cnt; i++) {
6909                 struct tg3_napi *tnapi = &tp->napi[i];
6910                 if (tnapi->hw_status) {
6911                         tnapi->hw_status->status = 0;
6912                         tnapi->hw_status->status_tag = 0;
6913                 }
6914                 tnapi->last_tag = 0;
6915                 tnapi->last_irq_tag = 0;
6916         }
6917         smp_mb();
6918
6919         for (i = 0; i < tp->irq_cnt; i++)
6920                 synchronize_irq(tp->napi[i].irq_vec);
6921
6922         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6923                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6924                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6925         }
6926
6927         /* do the reset */
6928         val = GRC_MISC_CFG_CORECLK_RESET;
6929
6930         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6931                 if (tr32(0x7e2c) == 0x60) {
6932                         tw32(0x7e2c, 0x20);
6933                 }
6934                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6935                         tw32(GRC_MISC_CFG, (1 << 29));
6936                         val |= (1 << 29);
6937                 }
6938         }
6939
6940         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6941                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6942                 tw32(GRC_VCPU_EXT_CTRL,
6943                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6944         }
6945
6946         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6947                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6948         tw32(GRC_MISC_CFG, val);
6949
6950         /* restore 5701 hardware bug workaround write method */
6951         tp->write32 = write_op;
6952
6953         /* Unfortunately, we have to delay before the PCI read back.
6954          * Some 575X chips even will not respond to a PCI cfg access
6955          * when the reset command is given to the chip.
6956          *
6957          * How do these hardware designers expect things to work
6958          * properly if the PCI write is posted for a long period
6959          * of time?  It is always necessary to have some method by
6960          * which a register read back can occur to push the write
6961          * out which does the reset.
6962          *
6963          * For most tg3 variants the trick below was working.
6964          * Ho hum...
6965          */
6966         udelay(120);
6967
6968         /* Flush PCI posted writes.  The normal MMIO registers
6969          * are inaccessible at this time so this is the only
6970          * way to make this reliably (actually, this is no longer
6971          * the case, see above).  I tried to use indirect
6972          * register read/write but this upset some 5701 variants.
6973          */
6974         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6975
6976         udelay(120);
6977
6978         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6979                 u16 val16;
6980
6981                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6982                         int i;
6983                         u32 cfg_val;
6984
6985                         /* Wait for link training to complete.  */
6986                         for (i = 0; i < 5000; i++)
6987                                 udelay(100);
6988
6989                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6990                         pci_write_config_dword(tp->pdev, 0xc4,
6991                                                cfg_val | (1 << 15));
6992                 }
6993
6994                 /* Clear the "no snoop" and "relaxed ordering" bits. */
6995                 pci_read_config_word(tp->pdev,
6996                                      tp->pcie_cap + PCI_EXP_DEVCTL,
6997                                      &val16);
6998                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6999                            PCI_EXP_DEVCTL_NOSNOOP_EN);
7000                 /*
7001                  * Older PCIe devices only support the 128 byte
7002                  * MPS setting.  Enforce the restriction.
7003                  */
7004                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
7005                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
7006                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
7007                 pci_write_config_word(tp->pdev,
7008                                       tp->pcie_cap + PCI_EXP_DEVCTL,
7009                                       val16);
7010
7011                 pcie_set_readrq(tp->pdev, 4096);
7012
7013                 /* Clear error status */
7014                 pci_write_config_word(tp->pdev,
7015                                       tp->pcie_cap + PCI_EXP_DEVSTA,
7016                                       PCI_EXP_DEVSTA_CED |
7017                                       PCI_EXP_DEVSTA_NFED |
7018                                       PCI_EXP_DEVSTA_FED |
7019                                       PCI_EXP_DEVSTA_URD);
7020         }
7021
7022         tg3_restore_pci_state(tp);
7023
7024         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
7025
7026         val = 0;
7027         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
7028                 val = tr32(MEMARB_MODE);
7029         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7030
7031         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7032                 tg3_stop_fw(tp);
7033                 tw32(0x5000, 0x400);
7034         }
7035
7036         tw32(GRC_MODE, tp->grc_mode);
7037
7038         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
7039                 val = tr32(0xc4);
7040
7041                 tw32(0xc4, val | (1 << 15));
7042         }
7043
7044         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7045             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7046                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7047                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7048                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7049                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7050         }
7051
7052         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7053                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
7054                 tw32_f(MAC_MODE, tp->mac_mode);
7055         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7056                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
7057                 tw32_f(MAC_MODE, tp->mac_mode);
7058         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7059                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
7060                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
7061                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
7062                 tw32_f(MAC_MODE, tp->mac_mode);
7063         } else
7064                 tw32_f(MAC_MODE, 0);
7065         udelay(40);
7066
7067         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7068
7069         err = tg3_poll_fw(tp);
7070         if (err)
7071                 return err;
7072
7073         tg3_mdio_start(tp);
7074
7075         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7076                 u8 phy_addr;
7077
7078                 phy_addr = tp->phy_addr;
7079                 tp->phy_addr = TG3_PHY_PCIE_ADDR;
7080
7081                 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
7082                              TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
7083                 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
7084                       TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
7085                       TG3_PCIEPHY_TX0CTRL1_NB_EN;
7086                 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
7087                 udelay(10);
7088
7089                 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
7090                              TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
7091                 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
7092                       TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
7093                 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
7094                 udelay(10);
7095
7096                 tp->phy_addr = phy_addr;
7097         }
7098
7099         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
7100             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7101             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7102             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
7103             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719 &&
7104             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
7105                 val = tr32(0x7c00);
7106
7107                 tw32(0x7c00, val | (1 << 25));
7108         }
7109
7110         /* Reprobe ASF enable state.  */
7111         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7112         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7113         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7114         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7115                 u32 nic_cfg;
7116
7117                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7118                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7119                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7120                         tp->last_event_jiffies = jiffies;
7121                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7122                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7123                 }
7124         }
7125
7126         return 0;
7127 }
7128
7129 /* tp->lock is held. */
7130 static void tg3_stop_fw(struct tg3 *tp)
7131 {
7132         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7133            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7134                 /* Wait for RX cpu to ACK the previous event. */
7135                 tg3_wait_for_event_ack(tp);
7136
7137                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7138
7139                 tg3_generate_fw_event(tp);
7140
7141                 /* Wait for RX cpu to ACK this event. */
7142                 tg3_wait_for_event_ack(tp);
7143         }
7144 }
7145
7146 /* tp->lock is held. */
7147 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7148 {
7149         int err;
7150
7151         tg3_stop_fw(tp);
7152
7153         tg3_write_sig_pre_reset(tp, kind);
7154
7155         tg3_abort_hw(tp, silent);
7156         err = tg3_chip_reset(tp);
7157
7158         __tg3_set_mac_addr(tp, 0);
7159
7160         tg3_write_sig_legacy(tp, kind);
7161         tg3_write_sig_post_reset(tp, kind);
7162
7163         if (err)
7164                 return err;
7165
7166         return 0;
7167 }
7168
7169 #define RX_CPU_SCRATCH_BASE     0x30000
7170 #define RX_CPU_SCRATCH_SIZE     0x04000
7171 #define TX_CPU_SCRATCH_BASE     0x34000
7172 #define TX_CPU_SCRATCH_SIZE     0x04000
7173
7174 /* tp->lock is held. */
7175 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7176 {
7177         int i;
7178
7179         BUG_ON(offset == TX_CPU_BASE &&
7180             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7181
7182         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7183                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7184
7185                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7186                 return 0;
7187         }
7188         if (offset == RX_CPU_BASE) {
7189                 for (i = 0; i < 10000; i++) {
7190                         tw32(offset + CPU_STATE, 0xffffffff);
7191                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7192                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7193                                 break;
7194                 }
7195
7196                 tw32(offset + CPU_STATE, 0xffffffff);
7197                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
7198                 udelay(10);
7199         } else {
7200                 for (i = 0; i < 10000; i++) {
7201                         tw32(offset + CPU_STATE, 0xffffffff);
7202                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7203                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7204                                 break;
7205                 }
7206         }
7207
7208         if (i >= 10000) {
7209                 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7210                            __func__, offset == RX_CPU_BASE ? "RX" : "TX");
7211                 return -ENODEV;
7212         }
7213
7214         /* Clear firmware's nvram arbitration. */
7215         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7216                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7217         return 0;
7218 }
7219
7220 struct fw_info {
7221         unsigned int fw_base;
7222         unsigned int fw_len;
7223         const __be32 *fw_data;
7224 };
7225
7226 /* tp->lock is held. */
7227 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7228                                  int cpu_scratch_size, struct fw_info *info)
7229 {
7230         int err, lock_err, i;
7231         void (*write_op)(struct tg3 *, u32, u32);
7232
7233         if (cpu_base == TX_CPU_BASE &&
7234             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7235                 netdev_err(tp->dev,
7236                            "%s: Trying to load TX cpu firmware which is 5705\n",
7237                            __func__);
7238                 return -EINVAL;
7239         }
7240
7241         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7242                 write_op = tg3_write_mem;
7243         else
7244                 write_op = tg3_write_indirect_reg32;
7245
7246         /* It is possible that bootcode is still loading at this point.
7247          * Get the nvram lock first before halting the cpu.
7248          */
7249         lock_err = tg3_nvram_lock(tp);
7250         err = tg3_halt_cpu(tp, cpu_base);
7251         if (!lock_err)
7252                 tg3_nvram_unlock(tp);
7253         if (err)
7254                 goto out;
7255
7256         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7257                 write_op(tp, cpu_scratch_base + i, 0);
7258         tw32(cpu_base + CPU_STATE, 0xffffffff);
7259         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7260         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7261                 write_op(tp, (cpu_scratch_base +
7262                               (info->fw_base & 0xffff) +
7263                               (i * sizeof(u32))),
7264                               be32_to_cpu(info->fw_data[i]));
7265
7266         err = 0;
7267
7268 out:
7269         return err;
7270 }
7271
7272 /* tp->lock is held. */
7273 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7274 {
7275         struct fw_info info;
7276         const __be32 *fw_data;
7277         int err, i;
7278
7279         fw_data = (void *)tp->fw->data;
7280
7281         /* Firmware blob starts with version numbers, followed by
7282            start address and length. We are setting complete length.
7283            length = end_address_of_bss - start_address_of_text.
7284            Remainder is the blob to be loaded contiguously
7285            from start address. */
7286
7287         info.fw_base = be32_to_cpu(fw_data[1]);
7288         info.fw_len = tp->fw->size - 12;
7289         info.fw_data = &fw_data[3];
7290
7291         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7292                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7293                                     &info);
7294         if (err)
7295                 return err;
7296
7297         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7298                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7299                                     &info);
7300         if (err)
7301                 return err;
7302
7303         /* Now startup only the RX cpu. */
7304         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7305         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7306
7307         for (i = 0; i < 5; i++) {
7308                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7309                         break;
7310                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7311                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
7312                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7313                 udelay(1000);
7314         }
7315         if (i >= 5) {
7316                 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7317                            "should be %08x\n", __func__,
7318                            tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
7319                 return -ENODEV;
7320         }
7321         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7322         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
7323
7324         return 0;
7325 }
7326
7327 /* 5705 needs a special version of the TSO firmware.  */
7328
7329 /* tp->lock is held. */
7330 static int tg3_load_tso_firmware(struct tg3 *tp)
7331 {
7332         struct fw_info info;
7333         const __be32 *fw_data;
7334         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7335         int err, i;
7336
7337         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7338                 return 0;
7339
7340         fw_data = (void *)tp->fw->data;
7341
7342         /* Firmware blob starts with version numbers, followed by
7343            start address and length. We are setting complete length.
7344            length = end_address_of_bss - start_address_of_text.
7345            Remainder is the blob to be loaded contiguously
7346            from start address. */
7347
7348         info.fw_base = be32_to_cpu(fw_data[1]);
7349         cpu_scratch_size = tp->fw_len;
7350         info.fw_len = tp->fw->size - 12;
7351         info.fw_data = &fw_data[3];
7352
7353         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7354                 cpu_base = RX_CPU_BASE;
7355                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7356         } else {
7357                 cpu_base = TX_CPU_BASE;
7358                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7359                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7360         }
7361
7362         err = tg3_load_firmware_cpu(tp, cpu_base,
7363                                     cpu_scratch_base, cpu_scratch_size,
7364                                     &info);
7365         if (err)
7366                 return err;
7367
7368         /* Now startup the cpu. */
7369         tw32(cpu_base + CPU_STATE, 0xffffffff);
7370         tw32_f(cpu_base + CPU_PC, info.fw_base);
7371
7372         for (i = 0; i < 5; i++) {
7373                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7374                         break;
7375                 tw32(cpu_base + CPU_STATE, 0xffffffff);
7376                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
7377                 tw32_f(cpu_base + CPU_PC, info.fw_base);
7378                 udelay(1000);
7379         }
7380         if (i >= 5) {
7381                 netdev_err(tp->dev,
7382                            "%s fails to set CPU PC, is %08x should be %08x\n",
7383                            __func__, tr32(cpu_base + CPU_PC), info.fw_base);
7384                 return -ENODEV;
7385         }
7386         tw32(cpu_base + CPU_STATE, 0xffffffff);
7387         tw32_f(cpu_base + CPU_MODE,  0x00000000);
7388         return 0;
7389 }
7390
7391
7392 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7393 {
7394         struct tg3 *tp = netdev_priv(dev);
7395         struct sockaddr *addr = p;
7396         int err = 0, skip_mac_1 = 0;
7397
7398         if (!is_valid_ether_addr(addr->sa_data))
7399                 return -EINVAL;
7400
7401         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7402
7403         if (!netif_running(dev))
7404                 return 0;
7405
7406         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7407                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7408
7409                 addr0_high = tr32(MAC_ADDR_0_HIGH);
7410                 addr0_low = tr32(MAC_ADDR_0_LOW);
7411                 addr1_high = tr32(MAC_ADDR_1_HIGH);
7412                 addr1_low = tr32(MAC_ADDR_1_LOW);
7413
7414                 /* Skip MAC addr 1 if ASF is using it. */
7415                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7416                     !(addr1_high == 0 && addr1_low == 0))
7417                         skip_mac_1 = 1;
7418         }
7419         spin_lock_bh(&tp->lock);
7420         __tg3_set_mac_addr(tp, skip_mac_1);
7421         spin_unlock_bh(&tp->lock);
7422
7423         return err;
7424 }
7425
7426 /* tp->lock is held. */
7427 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7428                            dma_addr_t mapping, u32 maxlen_flags,
7429                            u32 nic_addr)
7430 {
7431         tg3_write_mem(tp,
7432                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7433                       ((u64) mapping >> 32));
7434         tg3_write_mem(tp,
7435                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7436                       ((u64) mapping & 0xffffffff));
7437         tg3_write_mem(tp,
7438                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7439                        maxlen_flags);
7440
7441         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7442                 tg3_write_mem(tp,
7443                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7444                               nic_addr);
7445 }
7446
7447 static void __tg3_set_rx_mode(struct net_device *);
7448 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7449 {
7450         int i;
7451
7452         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7453                 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7454                 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7455                 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7456         } else {
7457                 tw32(HOSTCC_TXCOL_TICKS, 0);
7458                 tw32(HOSTCC_TXMAX_FRAMES, 0);
7459                 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7460         }
7461
7462         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
7463                 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7464                 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7465                 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7466         } else {
7467                 tw32(HOSTCC_RXCOL_TICKS, 0);
7468                 tw32(HOSTCC_RXMAX_FRAMES, 0);
7469                 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7470         }
7471
7472         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7473                 u32 val = ec->stats_block_coalesce_usecs;
7474
7475                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7476                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7477
7478                 if (!netif_carrier_ok(tp->dev))
7479                         val = 0;
7480
7481                 tw32(HOSTCC_STAT_COAL_TICKS, val);
7482         }
7483
7484         for (i = 0; i < tp->irq_cnt - 1; i++) {
7485                 u32 reg;
7486
7487                 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7488                 tw32(reg, ec->rx_coalesce_usecs);
7489                 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7490                 tw32(reg, ec->rx_max_coalesced_frames);
7491                 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7492                 tw32(reg, ec->rx_max_coalesced_frames_irq);
7493
7494                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7495                         reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7496                         tw32(reg, ec->tx_coalesce_usecs);
7497                         reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7498                         tw32(reg, ec->tx_max_coalesced_frames);
7499                         reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7500                         tw32(reg, ec->tx_max_coalesced_frames_irq);
7501                 }
7502         }
7503
7504         for (; i < tp->irq_max - 1; i++) {
7505                 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7506                 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7507                 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7508
7509                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7510                         tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7511                         tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7512                         tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7513                 }
7514         }
7515 }
7516
7517 /* tp->lock is held. */
7518 static void tg3_rings_reset(struct tg3 *tp)
7519 {
7520         int i;
7521         u32 stblk, txrcb, rxrcb, limit;
7522         struct tg3_napi *tnapi = &tp->napi[0];
7523
7524         /* Disable all transmit rings but the first. */
7525         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7526                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7527         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7528                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7529         else
7530                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7531
7532         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7533              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7534                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7535                               BDINFO_FLAGS_DISABLED);
7536
7537
7538         /* Disable all receive return rings but the first. */
7539         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7540             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7541                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7542         else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7543                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7544         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7545                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7546                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7547         else
7548                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7549
7550         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7551              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7552                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7553                               BDINFO_FLAGS_DISABLED);
7554
7555         /* Disable interrupts */
7556         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7557
7558         /* Zero mailbox registers. */
7559         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7560                 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7561                         tp->napi[i].tx_prod = 0;
7562                         tp->napi[i].tx_cons = 0;
7563                         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7564                                 tw32_mailbox(tp->napi[i].prodmbox, 0);
7565                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
7566                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7567                 }
7568                 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7569                         tw32_mailbox(tp->napi[0].prodmbox, 0);
7570         } else {
7571                 tp->napi[0].tx_prod = 0;
7572                 tp->napi[0].tx_cons = 0;
7573                 tw32_mailbox(tp->napi[0].prodmbox, 0);
7574                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7575         }
7576
7577         /* Make sure the NIC-based send BD rings are disabled. */
7578         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7579                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7580                 for (i = 0; i < 16; i++)
7581                         tw32_tx_mbox(mbox + i * 8, 0);
7582         }
7583
7584         txrcb = NIC_SRAM_SEND_RCB;
7585         rxrcb = NIC_SRAM_RCV_RET_RCB;
7586
7587         /* Clear status block in ram. */
7588         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7589
7590         /* Set status block DMA address */
7591         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7592              ((u64) tnapi->status_mapping >> 32));
7593         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7594              ((u64) tnapi->status_mapping & 0xffffffff));
7595
7596         if (tnapi->tx_ring) {
7597                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7598                                (TG3_TX_RING_SIZE <<
7599                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7600                                NIC_SRAM_TX_BUFFER_DESC);
7601                 txrcb += TG3_BDINFO_SIZE;
7602         }
7603
7604         if (tnapi->rx_rcb) {
7605                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7606                                (TG3_RX_RCB_RING_SIZE(tp) <<
7607                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7608                 rxrcb += TG3_BDINFO_SIZE;
7609         }
7610
7611         stblk = HOSTCC_STATBLCK_RING1;
7612
7613         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7614                 u64 mapping = (u64)tnapi->status_mapping;
7615                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7616                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7617
7618                 /* Clear status block in ram. */
7619                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7620
7621                 if (tnapi->tx_ring) {
7622                         tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7623                                        (TG3_TX_RING_SIZE <<
7624                                         BDINFO_FLAGS_MAXLEN_SHIFT),
7625                                        NIC_SRAM_TX_BUFFER_DESC);
7626                         txrcb += TG3_BDINFO_SIZE;
7627                 }
7628
7629                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7630                                (TG3_RX_RCB_RING_SIZE(tp) <<
7631                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7632
7633                 stblk += 8;
7634                 rxrcb += TG3_BDINFO_SIZE;
7635         }
7636 }
7637
7638 /* tp->lock is held. */
7639 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7640 {
7641         u32 val, rdmac_mode;
7642         int i, err, limit;
7643         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
7644
7645         tg3_disable_ints(tp);
7646
7647         tg3_stop_fw(tp);
7648
7649         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7650
7651         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
7652                 tg3_abort_hw(tp, 1);
7653
7654         if (reset_phy)
7655                 tg3_phy_reset(tp);
7656
7657         err = tg3_chip_reset(tp);
7658         if (err)
7659                 return err;
7660
7661         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7662
7663         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7664                 val = tr32(TG3_CPMU_CTRL);
7665                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7666                 tw32(TG3_CPMU_CTRL, val);
7667
7668                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7669                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7670                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7671                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7672
7673                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7674                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7675                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7676                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7677
7678                 val = tr32(TG3_CPMU_HST_ACC);
7679                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7680                 val |= CPMU_HST_ACC_MACCLK_6_25;
7681                 tw32(TG3_CPMU_HST_ACC, val);
7682         }
7683
7684         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7685                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7686                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7687                        PCIE_PWR_MGMT_L1_THRESH_4MS;
7688                 tw32(PCIE_PWR_MGMT_THRESH, val);
7689
7690                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7691                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7692
7693                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7694
7695                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7696                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7697         }
7698
7699         if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7700                 u32 grc_mode = tr32(GRC_MODE);
7701
7702                 /* Access the lower 1K of PL PCIE block registers. */
7703                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7704                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7705
7706                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7707                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7708                      val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7709
7710                 tw32(GRC_MODE, grc_mode);
7711         }
7712
7713         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
7714                 u32 grc_mode = tr32(GRC_MODE);
7715
7716                 /* Access the lower 1K of PL PCIE block registers. */
7717                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7718                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7719
7720                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5);
7721                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
7722                      val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
7723
7724                 tw32(GRC_MODE, grc_mode);
7725
7726                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7727                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7728                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7729                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7730         }
7731
7732         /* This works around an issue with Athlon chipsets on
7733          * B3 tigon3 silicon.  This bit has no effect on any
7734          * other revision.  But do not set this on PCI Express
7735          * chips and don't even touch the clocks if the CPMU is present.
7736          */
7737         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7738                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7739                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7740                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7741         }
7742
7743         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7744             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7745                 val = tr32(TG3PCI_PCISTATE);
7746                 val |= PCISTATE_RETRY_SAME_DMA;
7747                 tw32(TG3PCI_PCISTATE, val);
7748         }
7749
7750         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7751                 /* Allow reads and writes to the
7752                  * APE register and memory space.
7753                  */
7754                 val = tr32(TG3PCI_PCISTATE);
7755                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7756                        PCISTATE_ALLOW_APE_SHMEM_WR |
7757                        PCISTATE_ALLOW_APE_PSPACE_WR;
7758                 tw32(TG3PCI_PCISTATE, val);
7759         }
7760
7761         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7762                 /* Enable some hw fixes.  */
7763                 val = tr32(TG3PCI_MSI_DATA);
7764                 val |= (1 << 26) | (1 << 28) | (1 << 29);
7765                 tw32(TG3PCI_MSI_DATA, val);
7766         }
7767
7768         /* Descriptor ring init may make accesses to the
7769          * NIC SRAM area to setup the TX descriptors, so we
7770          * can only do this after the hardware has been
7771          * successfully reset.
7772          */
7773         err = tg3_init_rings(tp);
7774         if (err)
7775                 return err;
7776
7777         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7778             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
7779             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7780                 val = tr32(TG3PCI_DMA_RW_CTRL) &
7781                       ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7782                 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
7783                         val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
7784                 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7785         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7786                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7787                 /* This value is determined during the probe time DMA
7788                  * engine test, tg3_test_dma.
7789                  */
7790                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7791         }
7792
7793         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7794                           GRC_MODE_4X_NIC_SEND_RINGS |
7795                           GRC_MODE_NO_TX_PHDR_CSUM |
7796                           GRC_MODE_NO_RX_PHDR_CSUM);
7797         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7798
7799         /* Pseudo-header checksum is done by hardware logic and not
7800          * the offload processers, so make the chip do the pseudo-
7801          * header checksums on receive.  For transmit it is more
7802          * convenient to do the pseudo-header checksum in software
7803          * as Linux does that on transmit for us in all cases.
7804          */
7805         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7806
7807         tw32(GRC_MODE,
7808              tp->grc_mode |
7809              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7810
7811         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7812         val = tr32(GRC_MISC_CFG);
7813         val &= ~0xff;
7814         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7815         tw32(GRC_MISC_CFG, val);
7816
7817         /* Initialize MBUF/DESC pool. */
7818         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7819                 /* Do nothing.  */
7820         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7821                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7822                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7823                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7824                 else
7825                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7826                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7827                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7828         } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7829                 int fw_len;
7830
7831                 fw_len = tp->fw_len;
7832                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7833                 tw32(BUFMGR_MB_POOL_ADDR,
7834                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7835                 tw32(BUFMGR_MB_POOL_SIZE,
7836                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7837         }
7838
7839         if (tp->dev->mtu <= ETH_DATA_LEN) {
7840                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7841                      tp->bufmgr_config.mbuf_read_dma_low_water);
7842                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7843                      tp->bufmgr_config.mbuf_mac_rx_low_water);
7844                 tw32(BUFMGR_MB_HIGH_WATER,
7845                      tp->bufmgr_config.mbuf_high_water);
7846         } else {
7847                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7848                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7849                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7850                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7851                 tw32(BUFMGR_MB_HIGH_WATER,
7852                      tp->bufmgr_config.mbuf_high_water_jumbo);
7853         }
7854         tw32(BUFMGR_DMA_LOW_WATER,
7855              tp->bufmgr_config.dma_low_water);
7856         tw32(BUFMGR_DMA_HIGH_WATER,
7857              tp->bufmgr_config.dma_high_water);
7858
7859         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7860         for (i = 0; i < 2000; i++) {
7861                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7862                         break;
7863                 udelay(10);
7864         }
7865         if (i >= 2000) {
7866                 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
7867                 return -ENODEV;
7868         }
7869
7870         /* Setup replenish threshold. */
7871         val = tp->rx_pending / 8;
7872         if (val == 0)
7873                 val = 1;
7874         else if (val > tp->rx_std_max_post)
7875                 val = tp->rx_std_max_post;
7876         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7877                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7878                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7879
7880                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7881                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7882         }
7883
7884         tw32(RCVBDI_STD_THRESH, val);
7885
7886         /* Initialize TG3_BDINFO's at:
7887          *  RCVDBDI_STD_BD:     standard eth size rx ring
7888          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
7889          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
7890          *
7891          * like so:
7892          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
7893          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
7894          *                              ring attribute flags
7895          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
7896          *
7897          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7898          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7899          *
7900          * The size of each ring is fixed in the firmware, but the location is
7901          * configurable.
7902          */
7903         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7904              ((u64) tpr->rx_std_mapping >> 32));
7905         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7906              ((u64) tpr->rx_std_mapping & 0xffffffff));
7907         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
7908             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
7909                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7910                      NIC_SRAM_RX_BUFFER_DESC);
7911
7912         /* Disable the mini ring */
7913         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7914                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7915                      BDINFO_FLAGS_DISABLED);
7916
7917         /* Program the jumbo buffer descriptor ring control
7918          * blocks on those devices that have them.
7919          */
7920         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7921             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7922                 /* Setup replenish threshold. */
7923                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7924
7925                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7926                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7927                              ((u64) tpr->rx_jmb_mapping >> 32));
7928                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7929                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7930                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7931                              (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7932                              BDINFO_FLAGS_USE_EXT_RECV);
7933                         if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) ||
7934                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7935                                 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7936                                      NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7937                 } else {
7938                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7939                              BDINFO_FLAGS_DISABLED);
7940                 }
7941
7942                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7943                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
7944                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7945                         val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7946                               (TG3_RX_STD_DMA_SZ << 2);
7947                 else
7948                         val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
7949         } else
7950                 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7951
7952         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7953
7954         tpr->rx_std_prod_idx = tp->rx_pending;
7955         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
7956
7957         tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7958                           tp->rx_jumbo_pending : 0;
7959         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
7960
7961         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7962             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
7963             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7964                 tw32(STD_REPLENISH_LWM, 32);
7965                 tw32(JMB_REPLENISH_LWM, 16);
7966         }
7967
7968         tg3_rings_reset(tp);
7969
7970         /* Initialize MAC address and backoff seed. */
7971         __tg3_set_mac_addr(tp, 0);
7972
7973         /* MTU + ethernet header + FCS + optional VLAN tag */
7974         tw32(MAC_RX_MTU_SIZE,
7975              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7976
7977         /* The slot time is changed by tg3_setup_phy if we
7978          * run at gigabit with half duplex.
7979          */
7980         tw32(MAC_TX_LENGTHS,
7981              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7982              (6 << TX_LENGTHS_IPG_SHIFT) |
7983              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7984
7985         /* Receive rules. */
7986         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7987         tw32(RCVLPC_CONFIG, 0x0181);
7988
7989         /* Calculate RDMAC_MODE setting early, we need it to determine
7990          * the RCVLPC_STATE_ENABLE mask.
7991          */
7992         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7993                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7994                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7995                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7996                       RDMAC_MODE_LNGREAD_ENAB);
7997
7998         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7999             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8000                 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
8001
8002         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8003             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8004             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8005                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
8006                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
8007                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
8008
8009         /* If statement applies to 5705 and 5750 PCI devices only */
8010         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8011              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8012             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
8013                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
8014                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
8015                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
8016                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8017                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
8018                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8019                 }
8020         }
8021
8022         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
8023                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8024
8025         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8026                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8027
8028         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
8029             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8030             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8031                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
8032
8033         /* Receive/send statistics. */
8034         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
8035                 val = tr32(RCVLPC_STATS_ENABLE);
8036                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8037                 tw32(RCVLPC_STATS_ENABLE, val);
8038         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8039                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8040                 val = tr32(RCVLPC_STATS_ENABLE);
8041                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8042                 tw32(RCVLPC_STATS_ENABLE, val);
8043         } else {
8044                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8045         }
8046         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8047         tw32(SNDDATAI_STATSENAB, 0xffffff);
8048         tw32(SNDDATAI_STATSCTRL,
8049              (SNDDATAI_SCTRL_ENABLE |
8050               SNDDATAI_SCTRL_FASTUPD));
8051
8052         /* Setup host coalescing engine. */
8053         tw32(HOSTCC_MODE, 0);
8054         for (i = 0; i < 2000; i++) {
8055                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8056                         break;
8057                 udelay(10);
8058         }
8059
8060         __tg3_set_coalesce(tp, &tp->coal);
8061
8062         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8063                 /* Status/statistics block address.  See tg3_timer,
8064                  * the tg3_periodic_fetch_stats call there, and
8065                  * tg3_get_stats to see how this works for 5705/5750 chips.
8066                  */
8067                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8068                      ((u64) tp->stats_mapping >> 32));
8069                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8070                      ((u64) tp->stats_mapping & 0xffffffff));
8071                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8072
8073                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
8074
8075                 /* Clear statistics and status block memory areas */
8076                 for (i = NIC_SRAM_STATS_BLK;
8077                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8078                      i += sizeof(u32)) {
8079                         tg3_write_mem(tp, i, 0);
8080                         udelay(40);
8081                 }
8082         }
8083
8084         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8085
8086         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8087         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8088         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8089                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8090
8091         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8092                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
8093                 /* reset to prevent losing 1st rx packet intermittently */
8094                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8095                 udelay(10);
8096         }
8097
8098         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8099                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8100         else
8101                 tp->mac_mode = 0;
8102         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8103                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
8104         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8105             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8106             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8107                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8108         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8109         udelay(40);
8110
8111         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8112          * If TG3_FLG2_IS_NIC is zero, we should read the
8113          * register to preserve the GPIO settings for LOMs. The GPIOs,
8114          * whether used as inputs or outputs, are set by boot code after
8115          * reset.
8116          */
8117         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
8118                 u32 gpio_mask;
8119
8120                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8121                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8122                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8123
8124                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8125                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8126                                      GRC_LCLCTRL_GPIO_OUTPUT3;
8127
8128                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8129                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8130
8131                 tp->grc_local_ctrl &= ~gpio_mask;
8132                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8133
8134                 /* GPIO1 must be driven high for eeprom write protect */
8135                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8136                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8137                                                GRC_LCLCTRL_GPIO_OUTPUT1);
8138         }
8139         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8140         udelay(100);
8141
8142         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
8143                 val = tr32(MSGINT_MODE);
8144                 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8145                 tw32(MSGINT_MODE, val);
8146         }
8147
8148         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8149                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8150                 udelay(40);
8151         }
8152
8153         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8154                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8155                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8156                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8157                WDMAC_MODE_LNGREAD_ENAB);
8158
8159         /* If statement applies to 5705 and 5750 PCI devices only */
8160         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8161              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8162             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
8163                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8164                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8165                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8166                         /* nothing */
8167                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8168                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8169                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8170                         val |= WDMAC_MODE_RX_ACCEL;
8171                 }
8172         }
8173
8174         /* Enable host coalescing bug fix */
8175         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8176                 val |= WDMAC_MODE_STATUS_TAG_FIX;
8177
8178         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8179                 val |= WDMAC_MODE_BURST_ALL_DATA;
8180
8181         tw32_f(WDMAC_MODE, val);
8182         udelay(40);
8183
8184         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8185                 u16 pcix_cmd;
8186
8187                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8188                                      &pcix_cmd);
8189                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8190                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8191                         pcix_cmd |= PCI_X_CMD_READ_2K;
8192                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8193                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8194                         pcix_cmd |= PCI_X_CMD_READ_2K;
8195                 }
8196                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8197                                       pcix_cmd);
8198         }
8199
8200         tw32_f(RDMAC_MODE, rdmac_mode);
8201         udelay(40);
8202
8203         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8204         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8205                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8206
8207         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8208                 tw32(SNDDATAC_MODE,
8209                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8210         else
8211                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8212
8213         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8214         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8215         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8216         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8217         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8218                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8219         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8220         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8221                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8222         tw32(SNDBDI_MODE, val);
8223         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8224
8225         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8226                 err = tg3_load_5701_a0_firmware_fix(tp);
8227                 if (err)
8228                         return err;
8229         }
8230
8231         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8232                 err = tg3_load_tso_firmware(tp);
8233                 if (err)
8234                         return err;
8235         }
8236
8237         tp->tx_mode = TX_MODE_ENABLE;
8238         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
8239             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8240                 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
8241         tw32_f(MAC_TX_MODE, tp->tx_mode);
8242         udelay(100);
8243
8244         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8245                 u32 reg = MAC_RSS_INDIR_TBL_0;
8246                 u8 *ent = (u8 *)&val;
8247
8248                 /* Setup the indirection table */
8249                 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8250                         int idx = i % sizeof(val);
8251
8252                         ent[idx] = i % (tp->irq_cnt - 1);
8253                         if (idx == sizeof(val) - 1) {
8254                                 tw32(reg, val);
8255                                 reg += 4;
8256                         }
8257                 }
8258
8259                 /* Setup the "secret" hash key. */
8260                 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8261                 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8262                 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8263                 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8264                 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8265                 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8266                 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8267                 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8268                 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8269                 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8270         }
8271
8272         tp->rx_mode = RX_MODE_ENABLE;
8273         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8274                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8275
8276         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8277                 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8278                                RX_MODE_RSS_ITBL_HASH_BITS_7 |
8279                                RX_MODE_RSS_IPV6_HASH_EN |
8280                                RX_MODE_RSS_TCP_IPV6_HASH_EN |
8281                                RX_MODE_RSS_IPV4_HASH_EN |
8282                                RX_MODE_RSS_TCP_IPV4_HASH_EN;
8283
8284         tw32_f(MAC_RX_MODE, tp->rx_mode);
8285         udelay(10);
8286
8287         tw32(MAC_LED_CTRL, tp->led_ctrl);
8288
8289         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8290         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8291                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8292                 udelay(10);
8293         }
8294         tw32_f(MAC_RX_MODE, tp->rx_mode);
8295         udelay(10);
8296
8297         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8298                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8299                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
8300                         /* Set drive transmission level to 1.2V  */
8301                         /* only if the signal pre-emphasis bit is not set  */
8302                         val = tr32(MAC_SERDES_CFG);
8303                         val &= 0xfffff000;
8304                         val |= 0x880;
8305                         tw32(MAC_SERDES_CFG, val);
8306                 }
8307                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8308                         tw32(MAC_SERDES_CFG, 0x616000);
8309         }
8310
8311         /* Prevent chip from dropping frames when flow control
8312          * is enabled.
8313          */
8314         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8315                 val = 1;
8316         else
8317                 val = 2;
8318         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8319
8320         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8321             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8322                 /* Use hardware link auto-negotiation */
8323                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8324         }
8325
8326         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8327             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8328                 u32 tmp;
8329
8330                 tmp = tr32(SERDES_RX_CTRL);
8331                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8332                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8333                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8334                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8335         }
8336
8337         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8338                 if (tp->link_config.phy_is_low_power) {
8339                         tp->link_config.phy_is_low_power = 0;
8340                         tp->link_config.speed = tp->link_config.orig_speed;
8341                         tp->link_config.duplex = tp->link_config.orig_duplex;
8342                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
8343                 }
8344
8345                 err = tg3_setup_phy(tp, 0);
8346                 if (err)
8347                         return err;
8348
8349                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8350                     !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
8351                         u32 tmp;
8352
8353                         /* Clear CRC stats. */
8354                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8355                                 tg3_writephy(tp, MII_TG3_TEST1,
8356                                              tmp | MII_TG3_TEST1_CRC_EN);
8357                                 tg3_readphy(tp, 0x14, &tmp);
8358                         }
8359                 }
8360         }
8361
8362         __tg3_set_rx_mode(tp->dev);
8363
8364         /* Initialize receive rules. */
8365         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
8366         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8367         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
8368         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8369
8370         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8371             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8372                 limit = 8;
8373         else
8374                 limit = 16;
8375         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8376                 limit -= 4;
8377         switch (limit) {
8378         case 16:
8379                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
8380         case 15:
8381                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
8382         case 14:
8383                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
8384         case 13:
8385                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
8386         case 12:
8387                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
8388         case 11:
8389                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
8390         case 10:
8391                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
8392         case 9:
8393                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
8394         case 8:
8395                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
8396         case 7:
8397                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
8398         case 6:
8399                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
8400         case 5:
8401                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
8402         case 4:
8403                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
8404         case 3:
8405                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
8406         case 2:
8407         case 1:
8408
8409         default:
8410                 break;
8411         }
8412
8413         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8414                 /* Write our heartbeat update interval to APE. */
8415                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8416                                 APE_HOST_HEARTBEAT_INT_DISABLE);
8417
8418         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8419
8420         return 0;
8421 }
8422
8423 /* Called at device open time to get the chip ready for
8424  * packet processing.  Invoked with tp->lock held.
8425  */
8426 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8427 {
8428         tg3_switch_clocks(tp);
8429
8430         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8431
8432         return tg3_reset_hw(tp, reset_phy);
8433 }
8434
8435 #define TG3_STAT_ADD32(PSTAT, REG) \
8436 do {    u32 __val = tr32(REG); \
8437         (PSTAT)->low += __val; \
8438         if ((PSTAT)->low < __val) \
8439                 (PSTAT)->high += 1; \
8440 } while (0)
8441
8442 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8443 {
8444         struct tg3_hw_stats *sp = tp->hw_stats;
8445
8446         if (!netif_carrier_ok(tp->dev))
8447                 return;
8448
8449         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8450         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8451         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8452         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8453         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8454         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8455         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8456         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8457         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8458         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8459         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8460         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8461         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8462
8463         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8464         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8465         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8466         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8467         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8468         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8469         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8470         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8471         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8472         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8473         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8474         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8475         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8476         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8477
8478         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8479         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8480         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8481 }
8482
8483 static void tg3_timer(unsigned long __opaque)
8484 {
8485         struct tg3 *tp = (struct tg3 *) __opaque;
8486
8487         if (tp->irq_sync)
8488                 goto restart_timer;
8489
8490         spin_lock(&tp->lock);
8491
8492         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8493                 /* All of this garbage is because when using non-tagged
8494                  * IRQ status the mailbox/status_block protocol the chip
8495                  * uses with the cpu is race prone.
8496                  */
8497                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8498                         tw32(GRC_LOCAL_CTRL,
8499                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8500                 } else {
8501                         tw32(HOSTCC_MODE, tp->coalesce_mode |
8502                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8503                 }
8504
8505                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8506                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8507                         spin_unlock(&tp->lock);
8508                         schedule_work(&tp->reset_task);
8509                         return;
8510                 }
8511         }
8512
8513         /* This part only runs once per second. */
8514         if (!--tp->timer_counter) {
8515                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8516                         tg3_periodic_fetch_stats(tp);
8517
8518                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8519                         u32 mac_stat;
8520                         int phy_event;
8521
8522                         mac_stat = tr32(MAC_STATUS);
8523
8524                         phy_event = 0;
8525                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8526                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8527                                         phy_event = 1;
8528                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8529                                 phy_event = 1;
8530
8531                         if (phy_event)
8532                                 tg3_setup_phy(tp, 0);
8533                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8534                         u32 mac_stat = tr32(MAC_STATUS);
8535                         int need_setup = 0;
8536
8537                         if (netif_carrier_ok(tp->dev) &&
8538                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8539                                 need_setup = 1;
8540                         }
8541                         if (! netif_carrier_ok(tp->dev) &&
8542                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
8543                                          MAC_STATUS_SIGNAL_DET))) {
8544                                 need_setup = 1;
8545                         }
8546                         if (need_setup) {
8547                                 if (!tp->serdes_counter) {
8548                                         tw32_f(MAC_MODE,
8549                                              (tp->mac_mode &
8550                                               ~MAC_MODE_PORT_MODE_MASK));
8551                                         udelay(40);
8552                                         tw32_f(MAC_MODE, tp->mac_mode);
8553                                         udelay(40);
8554                                 }
8555                                 tg3_setup_phy(tp, 0);
8556                         }
8557                 } else if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8558                            (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8559                         tg3_serdes_parallel_detect(tp);
8560                 }
8561
8562                 tp->timer_counter = tp->timer_multiplier;
8563         }
8564
8565         /* Heartbeat is only sent once every 2 seconds.
8566          *
8567          * The heartbeat is to tell the ASF firmware that the host
8568          * driver is still alive.  In the event that the OS crashes,
8569          * ASF needs to reset the hardware to free up the FIFO space
8570          * that may be filled with rx packets destined for the host.
8571          * If the FIFO is full, ASF will no longer function properly.
8572          *
8573          * Unintended resets have been reported on real time kernels
8574          * where the timer doesn't run on time.  Netpoll will also have
8575          * same problem.
8576          *
8577          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8578          * to check the ring condition when the heartbeat is expiring
8579          * before doing the reset.  This will prevent most unintended
8580          * resets.
8581          */
8582         if (!--tp->asf_counter) {
8583                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8584                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8585                         tg3_wait_for_event_ack(tp);
8586
8587                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8588                                       FWCMD_NICDRV_ALIVE3);
8589                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8590                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
8591                                       TG3_FW_UPDATE_TIMEOUT_SEC);
8592
8593                         tg3_generate_fw_event(tp);
8594                 }
8595                 tp->asf_counter = tp->asf_multiplier;
8596         }
8597
8598         spin_unlock(&tp->lock);
8599
8600 restart_timer:
8601         tp->timer.expires = jiffies + tp->timer_offset;
8602         add_timer(&tp->timer);
8603 }
8604
8605 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8606 {
8607         irq_handler_t fn;
8608         unsigned long flags;
8609         char *name;
8610         struct tg3_napi *tnapi = &tp->napi[irq_num];
8611
8612         if (tp->irq_cnt == 1)
8613                 name = tp->dev->name;
8614         else {
8615                 name = &tnapi->irq_lbl[0];
8616                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8617                 name[IFNAMSIZ-1] = 0;
8618         }
8619
8620         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8621                 fn = tg3_msi;
8622                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8623                         fn = tg3_msi_1shot;
8624                 flags = IRQF_SAMPLE_RANDOM;
8625         } else {
8626                 fn = tg3_interrupt;
8627                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8628                         fn = tg3_interrupt_tagged;
8629                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8630         }
8631
8632         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8633 }
8634
8635 static int tg3_test_interrupt(struct tg3 *tp)
8636 {
8637         struct tg3_napi *tnapi = &tp->napi[0];
8638         struct net_device *dev = tp->dev;
8639         int err, i, intr_ok = 0;
8640         u32 val;
8641
8642         if (!netif_running(dev))
8643                 return -ENODEV;
8644
8645         tg3_disable_ints(tp);
8646
8647         free_irq(tnapi->irq_vec, tnapi);
8648
8649         /*
8650          * Turn off MSI one shot mode.  Otherwise this test has no
8651          * observable way to know whether the interrupt was delivered.
8652          */
8653         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8654              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8655              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
8656             (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8657                 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8658                 tw32(MSGINT_MODE, val);
8659         }
8660
8661         err = request_irq(tnapi->irq_vec, tg3_test_isr,
8662                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8663         if (err)
8664                 return err;
8665
8666         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8667         tg3_enable_ints(tp);
8668
8669         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8670                tnapi->coal_now);
8671
8672         for (i = 0; i < 5; i++) {
8673                 u32 int_mbox, misc_host_ctrl;
8674
8675                 int_mbox = tr32_mailbox(tnapi->int_mbox);
8676                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8677
8678                 if ((int_mbox != 0) ||
8679                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8680                         intr_ok = 1;
8681                         break;
8682                 }
8683
8684                 msleep(10);
8685         }
8686
8687         tg3_disable_ints(tp);
8688
8689         free_irq(tnapi->irq_vec, tnapi);
8690
8691         err = tg3_request_irq(tp, 0);
8692
8693         if (err)
8694                 return err;
8695
8696         if (intr_ok) {
8697                 /* Reenable MSI one shot mode. */
8698                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8699                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8700                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
8701                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8702                         val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8703                         tw32(MSGINT_MODE, val);
8704                 }
8705                 return 0;
8706         }
8707
8708         return -EIO;
8709 }
8710
8711 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8712  * successfully restored
8713  */
8714 static int tg3_test_msi(struct tg3 *tp)
8715 {
8716         int err;
8717         u16 pci_cmd;
8718
8719         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8720                 return 0;
8721
8722         /* Turn off SERR reporting in case MSI terminates with Master
8723          * Abort.
8724          */
8725         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8726         pci_write_config_word(tp->pdev, PCI_COMMAND,
8727                               pci_cmd & ~PCI_COMMAND_SERR);
8728
8729         err = tg3_test_interrupt(tp);
8730
8731         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8732
8733         if (!err)
8734                 return 0;
8735
8736         /* other failures */
8737         if (err != -EIO)
8738                 return err;
8739
8740         /* MSI test failed, go back to INTx mode */
8741         netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
8742                     "to INTx mode. Please report this failure to the PCI "
8743                     "maintainer and include system chipset information\n");
8744
8745         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8746
8747         pci_disable_msi(tp->pdev);
8748
8749         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8750         tp->napi[0].irq_vec = tp->pdev->irq;
8751
8752         err = tg3_request_irq(tp, 0);
8753         if (err)
8754                 return err;
8755
8756         /* Need to reset the chip because the MSI cycle may have terminated
8757          * with Master Abort.
8758          */
8759         tg3_full_lock(tp, 1);
8760
8761         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8762         err = tg3_init_hw(tp, 1);
8763
8764         tg3_full_unlock(tp);
8765
8766         if (err)
8767                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8768
8769         return err;
8770 }
8771
8772 static int tg3_request_firmware(struct tg3 *tp)
8773 {
8774         const __be32 *fw_data;
8775
8776         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8777                 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
8778                            tp->fw_needed);
8779                 return -ENOENT;
8780         }
8781
8782         fw_data = (void *)tp->fw->data;
8783
8784         /* Firmware blob starts with version numbers, followed by
8785          * start address and _full_ length including BSS sections
8786          * (which must be longer than the actual data, of course
8787          */
8788
8789         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
8790         if (tp->fw_len < (tp->fw->size - 12)) {
8791                 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
8792                            tp->fw_len, tp->fw_needed);
8793                 release_firmware(tp->fw);
8794                 tp->fw = NULL;
8795                 return -EINVAL;
8796         }
8797
8798         /* We no longer need firmware; we have it. */
8799         tp->fw_needed = NULL;
8800         return 0;
8801 }
8802
8803 static bool tg3_enable_msix(struct tg3 *tp)
8804 {
8805         int i, rc, cpus = num_online_cpus();
8806         struct msix_entry msix_ent[tp->irq_max];
8807
8808         if (cpus == 1)
8809                 /* Just fallback to the simpler MSI mode. */
8810                 return false;
8811
8812         /*
8813          * We want as many rx rings enabled as there are cpus.
8814          * The first MSIX vector only deals with link interrupts, etc,
8815          * so we add one to the number of vectors we are requesting.
8816          */
8817         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8818
8819         for (i = 0; i < tp->irq_max; i++) {
8820                 msix_ent[i].entry  = i;
8821                 msix_ent[i].vector = 0;
8822         }
8823
8824         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8825         if (rc < 0) {
8826                 return false;
8827         } else if (rc != 0) {
8828                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8829                         return false;
8830                 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
8831                               tp->irq_cnt, rc);
8832                 tp->irq_cnt = rc;
8833         }
8834
8835         for (i = 0; i < tp->irq_max; i++)
8836                 tp->napi[i].irq_vec = msix_ent[i].vector;
8837
8838         tp->dev->real_num_tx_queues = 1;
8839         if (tp->irq_cnt > 1) {
8840                 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8841
8842                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8843                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
8844                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
8845                         tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8846                 }
8847         }
8848
8849         return true;
8850 }
8851
8852 static void tg3_ints_init(struct tg3 *tp)
8853 {
8854         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8855             !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8856                 /* All MSI supporting chips should support tagged
8857                  * status.  Assert that this is the case.
8858                  */
8859                 netdev_warn(tp->dev,
8860                             "MSI without TAGGED_STATUS? Not using MSI\n");
8861                 goto defcfg;
8862         }
8863
8864         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8865                 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8866         else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8867                  pci_enable_msi(tp->pdev) == 0)
8868                 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8869
8870         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8871                 u32 msi_mode = tr32(MSGINT_MODE);
8872                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8873                         msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8874                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8875         }
8876 defcfg:
8877         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8878                 tp->irq_cnt = 1;
8879                 tp->napi[0].irq_vec = tp->pdev->irq;
8880                 tp->dev->real_num_tx_queues = 1;
8881         }
8882 }
8883
8884 static void tg3_ints_fini(struct tg3 *tp)
8885 {
8886         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8887                 pci_disable_msix(tp->pdev);
8888         else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8889                 pci_disable_msi(tp->pdev);
8890         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8891         tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
8892 }
8893
8894 static int tg3_open(struct net_device *dev)
8895 {
8896         struct tg3 *tp = netdev_priv(dev);
8897         int i, err;
8898
8899         if (tp->fw_needed) {
8900                 err = tg3_request_firmware(tp);
8901                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8902                         if (err)
8903                                 return err;
8904                 } else if (err) {
8905                         netdev_warn(tp->dev, "TSO capability disabled\n");
8906                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8907                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8908                         netdev_notice(tp->dev, "TSO capability restored\n");
8909                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8910                 }
8911         }
8912
8913         netif_carrier_off(tp->dev);
8914
8915         err = tg3_set_power_state(tp, PCI_D0);
8916         if (err)
8917                 return err;
8918
8919         tg3_full_lock(tp, 0);
8920
8921         tg3_disable_ints(tp);
8922         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8923
8924         tg3_full_unlock(tp);
8925
8926         /*
8927          * Setup interrupts first so we know how
8928          * many NAPI resources to allocate
8929          */
8930         tg3_ints_init(tp);
8931
8932         /* The placement of this call is tied
8933          * to the setup and use of Host TX descriptors.
8934          */
8935         err = tg3_alloc_consistent(tp);
8936         if (err)
8937                 goto err_out1;
8938
8939         tg3_napi_enable(tp);
8940
8941         for (i = 0; i < tp->irq_cnt; i++) {
8942                 struct tg3_napi *tnapi = &tp->napi[i];
8943                 err = tg3_request_irq(tp, i);
8944                 if (err) {
8945                         for (i--; i >= 0; i--)
8946                                 free_irq(tnapi->irq_vec, tnapi);
8947                         break;
8948                 }
8949         }
8950
8951         if (err)
8952                 goto err_out2;
8953
8954         tg3_full_lock(tp, 0);
8955
8956         err = tg3_init_hw(tp, 1);
8957         if (err) {
8958                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8959                 tg3_free_rings(tp);
8960         } else {
8961                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8962                         tp->timer_offset = HZ;
8963                 else
8964                         tp->timer_offset = HZ / 10;
8965
8966                 BUG_ON(tp->timer_offset > HZ);
8967                 tp->timer_counter = tp->timer_multiplier =
8968                         (HZ / tp->timer_offset);
8969                 tp->asf_counter = tp->asf_multiplier =
8970                         ((HZ / tp->timer_offset) * 2);
8971
8972                 init_timer(&tp->timer);
8973                 tp->timer.expires = jiffies + tp->timer_offset;
8974                 tp->timer.data = (unsigned long) tp;
8975                 tp->timer.function = tg3_timer;
8976         }
8977
8978         tg3_full_unlock(tp);
8979
8980         if (err)
8981                 goto err_out3;
8982
8983         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8984                 err = tg3_test_msi(tp);
8985
8986                 if (err) {
8987                         tg3_full_lock(tp, 0);
8988                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8989                         tg3_free_rings(tp);
8990                         tg3_full_unlock(tp);
8991
8992                         goto err_out2;
8993                 }
8994
8995                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8996                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719 &&
8997                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 &&
8998                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8999                     (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
9000                         u32 val = tr32(PCIE_TRANSACTION_CFG);
9001
9002                         tw32(PCIE_TRANSACTION_CFG,
9003                              val | PCIE_TRANS_CFG_1SHOT_MSI);
9004                 }
9005         }
9006
9007         tg3_phy_start(tp);
9008
9009         tg3_full_lock(tp, 0);
9010
9011         add_timer(&tp->timer);
9012         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9013         tg3_enable_ints(tp);
9014
9015         tg3_full_unlock(tp);
9016
9017         netif_tx_start_all_queues(dev);
9018
9019         return 0;
9020
9021 err_out3:
9022         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9023                 struct tg3_napi *tnapi = &tp->napi[i];
9024                 free_irq(tnapi->irq_vec, tnapi);
9025         }
9026
9027 err_out2:
9028         tg3_napi_disable(tp);
9029         tg3_free_consistent(tp);
9030
9031 err_out1:
9032         tg3_ints_fini(tp);
9033         return err;
9034 }
9035
9036 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
9037                                                  struct rtnl_link_stats64 *);
9038 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9039
9040 static int tg3_close(struct net_device *dev)
9041 {
9042         int i;
9043         struct tg3 *tp = netdev_priv(dev);
9044
9045         tg3_napi_disable(tp);
9046         cancel_work_sync(&tp->reset_task);
9047
9048         netif_tx_stop_all_queues(dev);
9049
9050         del_timer_sync(&tp->timer);
9051
9052         tg3_phy_stop(tp);
9053
9054         tg3_full_lock(tp, 1);
9055
9056         tg3_disable_ints(tp);
9057
9058         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9059         tg3_free_rings(tp);
9060         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9061
9062         tg3_full_unlock(tp);
9063
9064         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9065                 struct tg3_napi *tnapi = &tp->napi[i];
9066                 free_irq(tnapi->irq_vec, tnapi);
9067         }
9068
9069         tg3_ints_fini(tp);
9070
9071         tg3_get_stats64(tp->dev, &tp->net_stats_prev);
9072
9073         memcpy(&tp->estats_prev, tg3_get_estats(tp),
9074                sizeof(tp->estats_prev));
9075
9076         tg3_free_consistent(tp);
9077
9078         tg3_set_power_state(tp, PCI_D3hot);
9079
9080         netif_carrier_off(tp->dev);
9081
9082         return 0;
9083 }
9084
9085 static inline u64 get_stat64(tg3_stat64_t *val)
9086 {
9087        return ((u64)val->high << 32) | ((u64)val->low);
9088 }
9089
9090 static u64 calc_crc_errors(struct tg3 *tp)
9091 {
9092         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9093
9094         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9095             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9096              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9097                 u32 val;
9098
9099                 spin_lock_bh(&tp->lock);
9100                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9101                         tg3_writephy(tp, MII_TG3_TEST1,
9102                                      val | MII_TG3_TEST1_CRC_EN);
9103                         tg3_readphy(tp, 0x14, &val);
9104                 } else
9105                         val = 0;
9106                 spin_unlock_bh(&tp->lock);
9107
9108                 tp->phy_crc_errors += val;
9109
9110                 return tp->phy_crc_errors;
9111         }
9112
9113         return get_stat64(&hw_stats->rx_fcs_errors);
9114 }
9115
9116 #define ESTAT_ADD(member) \
9117         estats->member =        old_estats->member + \
9118                                 get_stat64(&hw_stats->member)
9119
9120 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9121 {
9122         struct tg3_ethtool_stats *estats = &tp->estats;
9123         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9124         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9125
9126         if (!hw_stats)
9127                 return old_estats;
9128
9129         ESTAT_ADD(rx_octets);
9130         ESTAT_ADD(rx_fragments);
9131         ESTAT_ADD(rx_ucast_packets);
9132         ESTAT_ADD(rx_mcast_packets);
9133         ESTAT_ADD(rx_bcast_packets);
9134         ESTAT_ADD(rx_fcs_errors);
9135         ESTAT_ADD(rx_align_errors);
9136         ESTAT_ADD(rx_xon_pause_rcvd);
9137         ESTAT_ADD(rx_xoff_pause_rcvd);
9138         ESTAT_ADD(rx_mac_ctrl_rcvd);
9139         ESTAT_ADD(rx_xoff_entered);
9140         ESTAT_ADD(rx_frame_too_long_errors);
9141         ESTAT_ADD(rx_jabbers);
9142         ESTAT_ADD(rx_undersize_packets);
9143         ESTAT_ADD(rx_in_length_errors);
9144         ESTAT_ADD(rx_out_length_errors);
9145         ESTAT_ADD(rx_64_or_less_octet_packets);
9146         ESTAT_ADD(rx_65_to_127_octet_packets);
9147         ESTAT_ADD(rx_128_to_255_octet_packets);
9148         ESTAT_ADD(rx_256_to_511_octet_packets);
9149         ESTAT_ADD(rx_512_to_1023_octet_packets);
9150         ESTAT_ADD(rx_1024_to_1522_octet_packets);
9151         ESTAT_ADD(rx_1523_to_2047_octet_packets);
9152         ESTAT_ADD(rx_2048_to_4095_octet_packets);
9153         ESTAT_ADD(rx_4096_to_8191_octet_packets);
9154         ESTAT_ADD(rx_8192_to_9022_octet_packets);
9155
9156         ESTAT_ADD(tx_octets);
9157         ESTAT_ADD(tx_collisions);
9158         ESTAT_ADD(tx_xon_sent);
9159         ESTAT_ADD(tx_xoff_sent);
9160         ESTAT_ADD(tx_flow_control);
9161         ESTAT_ADD(tx_mac_errors);
9162         ESTAT_ADD(tx_single_collisions);
9163         ESTAT_ADD(tx_mult_collisions);
9164         ESTAT_ADD(tx_deferred);
9165         ESTAT_ADD(tx_excessive_collisions);
9166         ESTAT_ADD(tx_late_collisions);
9167         ESTAT_ADD(tx_collide_2times);
9168         ESTAT_ADD(tx_collide_3times);
9169         ESTAT_ADD(tx_collide_4times);
9170         ESTAT_ADD(tx_collide_5times);
9171         ESTAT_ADD(tx_collide_6times);
9172         ESTAT_ADD(tx_collide_7times);
9173         ESTAT_ADD(tx_collide_8times);
9174         ESTAT_ADD(tx_collide_9times);
9175         ESTAT_ADD(tx_collide_10times);
9176         ESTAT_ADD(tx_collide_11times);
9177         ESTAT_ADD(tx_collide_12times);
9178         ESTAT_ADD(tx_collide_13times);
9179         ESTAT_ADD(tx_collide_14times);
9180         ESTAT_ADD(tx_collide_15times);
9181         ESTAT_ADD(tx_ucast_packets);
9182         ESTAT_ADD(tx_mcast_packets);
9183         ESTAT_ADD(tx_bcast_packets);
9184         ESTAT_ADD(tx_carrier_sense_errors);
9185         ESTAT_ADD(tx_discards);
9186         ESTAT_ADD(tx_errors);
9187
9188         ESTAT_ADD(dma_writeq_full);
9189         ESTAT_ADD(dma_write_prioq_full);
9190         ESTAT_ADD(rxbds_empty);
9191         ESTAT_ADD(rx_discards);
9192         ESTAT_ADD(rx_errors);
9193         ESTAT_ADD(rx_threshold_hit);
9194
9195         ESTAT_ADD(dma_readq_full);
9196         ESTAT_ADD(dma_read_prioq_full);
9197         ESTAT_ADD(tx_comp_queue_full);
9198
9199         ESTAT_ADD(ring_set_send_prod_index);
9200         ESTAT_ADD(ring_status_update);
9201         ESTAT_ADD(nic_irqs);
9202         ESTAT_ADD(nic_avoided_irqs);
9203         ESTAT_ADD(nic_tx_threshold_hit);
9204
9205         return estats;
9206 }
9207
9208 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
9209                                                  struct rtnl_link_stats64 *stats)
9210 {
9211         struct tg3 *tp = netdev_priv(dev);
9212         struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
9213         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9214
9215         if (!hw_stats)
9216                 return old_stats;
9217
9218         stats->rx_packets = old_stats->rx_packets +
9219                 get_stat64(&hw_stats->rx_ucast_packets) +
9220                 get_stat64(&hw_stats->rx_mcast_packets) +
9221                 get_stat64(&hw_stats->rx_bcast_packets);
9222
9223         stats->tx_packets = old_stats->tx_packets +
9224                 get_stat64(&hw_stats->tx_ucast_packets) +
9225                 get_stat64(&hw_stats->tx_mcast_packets) +
9226                 get_stat64(&hw_stats->tx_bcast_packets);
9227
9228         stats->rx_bytes = old_stats->rx_bytes +
9229                 get_stat64(&hw_stats->rx_octets);
9230         stats->tx_bytes = old_stats->tx_bytes +
9231                 get_stat64(&hw_stats->tx_octets);
9232
9233         stats->rx_errors = old_stats->rx_errors +
9234                 get_stat64(&hw_stats->rx_errors);
9235         stats->tx_errors = old_stats->tx_errors +
9236                 get_stat64(&hw_stats->tx_errors) +
9237                 get_stat64(&hw_stats->tx_mac_errors) +
9238                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9239                 get_stat64(&hw_stats->tx_discards);
9240
9241         stats->multicast = old_stats->multicast +
9242                 get_stat64(&hw_stats->rx_mcast_packets);
9243         stats->collisions = old_stats->collisions +
9244                 get_stat64(&hw_stats->tx_collisions);
9245
9246         stats->rx_length_errors = old_stats->rx_length_errors +
9247                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9248                 get_stat64(&hw_stats->rx_undersize_packets);
9249
9250         stats->rx_over_errors = old_stats->rx_over_errors +
9251                 get_stat64(&hw_stats->rxbds_empty);
9252         stats->rx_frame_errors = old_stats->rx_frame_errors +
9253                 get_stat64(&hw_stats->rx_align_errors);
9254         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9255                 get_stat64(&hw_stats->tx_discards);
9256         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9257                 get_stat64(&hw_stats->tx_carrier_sense_errors);
9258
9259         stats->rx_crc_errors = old_stats->rx_crc_errors +
9260                 calc_crc_errors(tp);
9261
9262         stats->rx_missed_errors = old_stats->rx_missed_errors +
9263                 get_stat64(&hw_stats->rx_discards);
9264
9265         return stats;
9266 }
9267
9268 static inline u32 calc_crc(unsigned char *buf, int len)
9269 {
9270         u32 reg;
9271         u32 tmp;
9272         int j, k;
9273
9274         reg = 0xffffffff;
9275
9276         for (j = 0; j < len; j++) {
9277                 reg ^= buf[j];
9278
9279                 for (k = 0; k < 8; k++) {
9280                         tmp = reg & 0x01;
9281
9282                         reg >>= 1;
9283
9284                         if (tmp)
9285                                 reg ^= 0xedb88320;
9286                 }
9287         }
9288
9289         return ~reg;
9290 }
9291
9292 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9293 {
9294         /* accept or reject all multicast frames */
9295         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9296         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9297         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9298         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9299 }
9300
9301 static void __tg3_set_rx_mode(struct net_device *dev)
9302 {
9303         struct tg3 *tp = netdev_priv(dev);
9304         u32 rx_mode;
9305
9306         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9307                                   RX_MODE_KEEP_VLAN_TAG);
9308
9309         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9310          * flag clear.
9311          */
9312 #if TG3_VLAN_TAG_USED
9313         if (!tp->vlgrp &&
9314             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9315                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9316 #else
9317         /* By definition, VLAN is disabled always in this
9318          * case.
9319          */
9320         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9321                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9322 #endif
9323
9324         if (dev->flags & IFF_PROMISC) {
9325                 /* Promiscuous mode. */
9326                 rx_mode |= RX_MODE_PROMISC;
9327         } else if (dev->flags & IFF_ALLMULTI) {
9328                 /* Accept all multicast. */
9329                 tg3_set_multi(tp, 1);
9330         } else if (netdev_mc_empty(dev)) {
9331                 /* Reject all multicast. */
9332                 tg3_set_multi(tp, 0);
9333         } else {
9334                 /* Accept one or more multicast(s). */
9335                 struct netdev_hw_addr *ha;
9336                 u32 mc_filter[4] = { 0, };
9337                 u32 regidx;
9338                 u32 bit;
9339                 u32 crc;
9340
9341                 netdev_for_each_mc_addr(ha, dev) {
9342                         crc = calc_crc(ha->addr, ETH_ALEN);
9343                         bit = ~crc & 0x7f;
9344                         regidx = (bit & 0x60) >> 5;
9345                         bit &= 0x1f;
9346                         mc_filter[regidx] |= (1 << bit);
9347                 }
9348
9349                 tw32(MAC_HASH_REG_0, mc_filter[0]);
9350                 tw32(MAC_HASH_REG_1, mc_filter[1]);
9351                 tw32(MAC_HASH_REG_2, mc_filter[2]);
9352                 tw32(MAC_HASH_REG_3, mc_filter[3]);
9353         }
9354
9355         if (rx_mode != tp->rx_mode) {
9356                 tp->rx_mode = rx_mode;
9357                 tw32_f(MAC_RX_MODE, rx_mode);
9358                 udelay(10);
9359         }
9360 }
9361
9362 static void tg3_set_rx_mode(struct net_device *dev)
9363 {
9364         struct tg3 *tp = netdev_priv(dev);
9365
9366         if (!netif_running(dev))
9367                 return;
9368
9369         tg3_full_lock(tp, 0);
9370         __tg3_set_rx_mode(dev);
9371         tg3_full_unlock(tp);
9372 }
9373
9374 #define TG3_REGDUMP_LEN         (32 * 1024)
9375
9376 static int tg3_get_regs_len(struct net_device *dev)
9377 {
9378         return TG3_REGDUMP_LEN;
9379 }
9380
9381 static void tg3_get_regs(struct net_device *dev,
9382                 struct ethtool_regs *regs, void *_p)
9383 {
9384         u32 *p = _p;
9385         struct tg3 *tp = netdev_priv(dev);
9386         u8 *orig_p = _p;
9387         int i;
9388
9389         regs->version = 0;
9390
9391         memset(p, 0, TG3_REGDUMP_LEN);
9392
9393         if (tp->link_config.phy_is_low_power)
9394                 return;
9395
9396         tg3_full_lock(tp, 0);
9397
9398 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
9399 #define GET_REG32_LOOP(base,len)                \
9400 do {    p = (u32 *)(orig_p + (base));           \
9401         for (i = 0; i < len; i += 4)            \
9402                 __GET_REG32((base) + i);        \
9403 } while (0)
9404 #define GET_REG32_1(reg)                        \
9405 do {    p = (u32 *)(orig_p + (reg));            \
9406         __GET_REG32((reg));                     \
9407 } while (0)
9408
9409         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9410         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9411         GET_REG32_LOOP(MAC_MODE, 0x4f0);
9412         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9413         GET_REG32_1(SNDDATAC_MODE);
9414         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9415         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9416         GET_REG32_1(SNDBDC_MODE);
9417         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9418         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9419         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9420         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9421         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9422         GET_REG32_1(RCVDCC_MODE);
9423         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9424         GET_REG32_LOOP(RCVCC_MODE, 0x14);
9425         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9426         GET_REG32_1(MBFREE_MODE);
9427         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9428         GET_REG32_LOOP(MEMARB_MODE, 0x10);
9429         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9430         GET_REG32_LOOP(RDMAC_MODE, 0x08);
9431         GET_REG32_LOOP(WDMAC_MODE, 0x08);
9432         GET_REG32_1(RX_CPU_MODE);
9433         GET_REG32_1(RX_CPU_STATE);
9434         GET_REG32_1(RX_CPU_PGMCTR);
9435         GET_REG32_1(RX_CPU_HWBKPT);
9436         GET_REG32_1(TX_CPU_MODE);
9437         GET_REG32_1(TX_CPU_STATE);
9438         GET_REG32_1(TX_CPU_PGMCTR);
9439         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9440         GET_REG32_LOOP(FTQ_RESET, 0x120);
9441         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9442         GET_REG32_1(DMAC_MODE);
9443         GET_REG32_LOOP(GRC_MODE, 0x4c);
9444         if (tp->tg3_flags & TG3_FLAG_NVRAM)
9445                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9446
9447 #undef __GET_REG32
9448 #undef GET_REG32_LOOP
9449 #undef GET_REG32_1
9450
9451         tg3_full_unlock(tp);
9452 }
9453
9454 static int tg3_get_eeprom_len(struct net_device *dev)
9455 {
9456         struct tg3 *tp = netdev_priv(dev);
9457
9458         return tp->nvram_size;
9459 }
9460
9461 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9462 {
9463         struct tg3 *tp = netdev_priv(dev);
9464         int ret;
9465         u8  *pd;
9466         u32 i, offset, len, b_offset, b_count;
9467         __be32 val;
9468
9469         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9470                 return -EINVAL;
9471
9472         if (tp->link_config.phy_is_low_power)
9473                 return -EAGAIN;
9474
9475         offset = eeprom->offset;
9476         len = eeprom->len;
9477         eeprom->len = 0;
9478
9479         eeprom->magic = TG3_EEPROM_MAGIC;
9480
9481         if (offset & 3) {
9482                 /* adjustments to start on required 4 byte boundary */
9483                 b_offset = offset & 3;
9484                 b_count = 4 - b_offset;
9485                 if (b_count > len) {
9486                         /* i.e. offset=1 len=2 */
9487                         b_count = len;
9488                 }
9489                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9490                 if (ret)
9491                         return ret;
9492                 memcpy(data, ((char*)&val) + b_offset, b_count);
9493                 len -= b_count;
9494                 offset += b_count;
9495                 eeprom->len += b_count;
9496         }
9497
9498         /* read bytes upto the last 4 byte boundary */
9499         pd = &data[eeprom->len];
9500         for (i = 0; i < (len - (len & 3)); i += 4) {
9501                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9502                 if (ret) {
9503                         eeprom->len += i;
9504                         return ret;
9505                 }
9506                 memcpy(pd + i, &val, 4);
9507         }
9508         eeprom->len += i;
9509
9510         if (len & 3) {
9511                 /* read last bytes not ending on 4 byte boundary */
9512                 pd = &data[eeprom->len];
9513                 b_count = len & 3;
9514                 b_offset = offset + len - b_count;
9515                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9516                 if (ret)
9517                         return ret;
9518                 memcpy(pd, &val, b_count);
9519                 eeprom->len += b_count;
9520         }
9521         return 0;
9522 }
9523
9524 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9525
9526 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9527 {
9528         struct tg3 *tp = netdev_priv(dev);
9529         int ret;
9530         u32 offset, len, b_offset, odd_len;
9531         u8 *buf;
9532         __be32 start, end;
9533
9534         if (tp->link_config.phy_is_low_power)
9535                 return -EAGAIN;
9536
9537         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9538             eeprom->magic != TG3_EEPROM_MAGIC)
9539                 return -EINVAL;
9540
9541         offset = eeprom->offset;
9542         len = eeprom->len;
9543
9544         if ((b_offset = (offset & 3))) {
9545                 /* adjustments to start on required 4 byte boundary */
9546                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9547                 if (ret)
9548                         return ret;
9549                 len += b_offset;
9550                 offset &= ~3;
9551                 if (len < 4)
9552                         len = 4;
9553         }
9554
9555         odd_len = 0;
9556         if (len & 3) {
9557                 /* adjustments to end on required 4 byte boundary */
9558                 odd_len = 1;
9559                 len = (len + 3) & ~3;
9560                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9561                 if (ret)
9562                         return ret;
9563         }
9564
9565         buf = data;
9566         if (b_offset || odd_len) {
9567                 buf = kmalloc(len, GFP_KERNEL);
9568                 if (!buf)
9569                         return -ENOMEM;
9570                 if (b_offset)
9571                         memcpy(buf, &start, 4);
9572                 if (odd_len)
9573                         memcpy(buf+len-4, &end, 4);
9574                 memcpy(buf + b_offset, data, eeprom->len);
9575         }
9576
9577         ret = tg3_nvram_write_block(tp, offset, len, buf);
9578
9579         if (buf != data)
9580                 kfree(buf);
9581
9582         return ret;
9583 }
9584
9585 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9586 {
9587         struct tg3 *tp = netdev_priv(dev);
9588
9589         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9590                 struct phy_device *phydev;
9591                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9592                         return -EAGAIN;
9593                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9594                 return phy_ethtool_gset(phydev, cmd);
9595         }
9596
9597         cmd->supported = (SUPPORTED_Autoneg);
9598
9599         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9600                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9601                                    SUPPORTED_1000baseT_Full);
9602
9603         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
9604                 cmd->supported |= (SUPPORTED_100baseT_Half |
9605                                   SUPPORTED_100baseT_Full |
9606                                   SUPPORTED_10baseT_Half |
9607                                   SUPPORTED_10baseT_Full |
9608                                   SUPPORTED_TP);
9609                 cmd->port = PORT_TP;
9610         } else {
9611                 cmd->supported |= SUPPORTED_FIBRE;
9612                 cmd->port = PORT_FIBRE;
9613         }
9614
9615         cmd->advertising = tp->link_config.advertising;
9616         if (netif_running(dev)) {
9617                 cmd->speed = tp->link_config.active_speed;
9618                 cmd->duplex = tp->link_config.active_duplex;
9619         }
9620         cmd->phy_address = tp->phy_addr;
9621         cmd->transceiver = XCVR_INTERNAL;
9622         cmd->autoneg = tp->link_config.autoneg;
9623         cmd->maxtxpkt = 0;
9624         cmd->maxrxpkt = 0;
9625         return 0;
9626 }
9627
9628 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9629 {
9630         struct tg3 *tp = netdev_priv(dev);
9631
9632         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9633                 struct phy_device *phydev;
9634                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9635                         return -EAGAIN;
9636                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9637                 return phy_ethtool_sset(phydev, cmd);
9638         }
9639
9640         if (cmd->autoneg != AUTONEG_ENABLE &&
9641             cmd->autoneg != AUTONEG_DISABLE)
9642                 return -EINVAL;
9643
9644         if (cmd->autoneg == AUTONEG_DISABLE &&
9645             cmd->duplex != DUPLEX_FULL &&
9646             cmd->duplex != DUPLEX_HALF)
9647                 return -EINVAL;
9648
9649         if (cmd->autoneg == AUTONEG_ENABLE) {
9650                 u32 mask = ADVERTISED_Autoneg |
9651                            ADVERTISED_Pause |
9652                            ADVERTISED_Asym_Pause;
9653
9654                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9655                         mask |= ADVERTISED_1000baseT_Half |
9656                                 ADVERTISED_1000baseT_Full;
9657
9658                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9659                         mask |= ADVERTISED_100baseT_Half |
9660                                 ADVERTISED_100baseT_Full |
9661                                 ADVERTISED_10baseT_Half |
9662                                 ADVERTISED_10baseT_Full |
9663                                 ADVERTISED_TP;
9664                 else
9665                         mask |= ADVERTISED_FIBRE;
9666
9667                 if (cmd->advertising & ~mask)
9668                         return -EINVAL;
9669
9670                 mask &= (ADVERTISED_1000baseT_Half |
9671                          ADVERTISED_1000baseT_Full |
9672                          ADVERTISED_100baseT_Half |
9673                          ADVERTISED_100baseT_Full |
9674                          ADVERTISED_10baseT_Half |
9675                          ADVERTISED_10baseT_Full);
9676
9677                 cmd->advertising &= mask;
9678         } else {
9679                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9680                         if (cmd->speed != SPEED_1000)
9681                                 return -EINVAL;
9682
9683                         if (cmd->duplex != DUPLEX_FULL)
9684                                 return -EINVAL;
9685                 } else {
9686                         if (cmd->speed != SPEED_100 &&
9687                             cmd->speed != SPEED_10)
9688                                 return -EINVAL;
9689                 }
9690         }
9691
9692         tg3_full_lock(tp, 0);
9693
9694         tp->link_config.autoneg = cmd->autoneg;
9695         if (cmd->autoneg == AUTONEG_ENABLE) {
9696                 tp->link_config.advertising = (cmd->advertising |
9697                                               ADVERTISED_Autoneg);
9698                 tp->link_config.speed = SPEED_INVALID;
9699                 tp->link_config.duplex = DUPLEX_INVALID;
9700         } else {
9701                 tp->link_config.advertising = 0;
9702                 tp->link_config.speed = cmd->speed;
9703                 tp->link_config.duplex = cmd->duplex;
9704         }
9705
9706         tp->link_config.orig_speed = tp->link_config.speed;
9707         tp->link_config.orig_duplex = tp->link_config.duplex;
9708         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9709
9710         if (netif_running(dev))
9711                 tg3_setup_phy(tp, 1);
9712
9713         tg3_full_unlock(tp);
9714
9715         return 0;
9716 }
9717
9718 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9719 {
9720         struct tg3 *tp = netdev_priv(dev);
9721
9722         strcpy(info->driver, DRV_MODULE_NAME);
9723         strcpy(info->version, DRV_MODULE_VERSION);
9724         strcpy(info->fw_version, tp->fw_ver);
9725         strcpy(info->bus_info, pci_name(tp->pdev));
9726 }
9727
9728 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9729 {
9730         struct tg3 *tp = netdev_priv(dev);
9731
9732         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9733             device_can_wakeup(&tp->pdev->dev))
9734                 wol->supported = WAKE_MAGIC;
9735         else
9736                 wol->supported = 0;
9737         wol->wolopts = 0;
9738         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9739             device_can_wakeup(&tp->pdev->dev))
9740                 wol->wolopts = WAKE_MAGIC;
9741         memset(&wol->sopass, 0, sizeof(wol->sopass));
9742 }
9743
9744 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9745 {
9746         struct tg3 *tp = netdev_priv(dev);
9747         struct device *dp = &tp->pdev->dev;
9748
9749         if (wol->wolopts & ~WAKE_MAGIC)
9750                 return -EINVAL;
9751         if ((wol->wolopts & WAKE_MAGIC) &&
9752             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9753                 return -EINVAL;
9754
9755         spin_lock_bh(&tp->lock);
9756         if (wol->wolopts & WAKE_MAGIC) {
9757                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9758                 device_set_wakeup_enable(dp, true);
9759         } else {
9760                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9761                 device_set_wakeup_enable(dp, false);
9762         }
9763         spin_unlock_bh(&tp->lock);
9764
9765         return 0;
9766 }
9767
9768 static u32 tg3_get_msglevel(struct net_device *dev)
9769 {
9770         struct tg3 *tp = netdev_priv(dev);
9771         return tp->msg_enable;
9772 }
9773
9774 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9775 {
9776         struct tg3 *tp = netdev_priv(dev);
9777         tp->msg_enable = value;
9778 }
9779
9780 static int tg3_set_tso(struct net_device *dev, u32 value)
9781 {
9782         struct tg3 *tp = netdev_priv(dev);
9783
9784         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9785                 if (value)
9786                         return -EINVAL;
9787                 return 0;
9788         }
9789         if ((dev->features & NETIF_F_IPV6_CSUM) &&
9790             ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9791              (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9792                 if (value) {
9793                         dev->features |= NETIF_F_TSO6;
9794                         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9795                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9796                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9797                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9798                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9799                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9800                                 dev->features |= NETIF_F_TSO_ECN;
9801                 } else
9802                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9803         }
9804         return ethtool_op_set_tso(dev, value);
9805 }
9806
9807 static int tg3_nway_reset(struct net_device *dev)
9808 {
9809         struct tg3 *tp = netdev_priv(dev);
9810         int r;
9811
9812         if (!netif_running(dev))
9813                 return -EAGAIN;
9814
9815         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9816                 return -EINVAL;
9817
9818         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9819                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9820                         return -EAGAIN;
9821                 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9822         } else {
9823                 u32 bmcr;
9824
9825                 spin_lock_bh(&tp->lock);
9826                 r = -EINVAL;
9827                 tg3_readphy(tp, MII_BMCR, &bmcr);
9828                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9829                     ((bmcr & BMCR_ANENABLE) ||
9830                      (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9831                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9832                                                    BMCR_ANENABLE);
9833                         r = 0;
9834                 }
9835                 spin_unlock_bh(&tp->lock);
9836         }
9837
9838         return r;
9839 }
9840
9841 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9842 {
9843         struct tg3 *tp = netdev_priv(dev);
9844
9845         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9846         ering->rx_mini_max_pending = 0;
9847         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9848                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9849         else
9850                 ering->rx_jumbo_max_pending = 0;
9851
9852         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9853
9854         ering->rx_pending = tp->rx_pending;
9855         ering->rx_mini_pending = 0;
9856         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9857                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9858         else
9859                 ering->rx_jumbo_pending = 0;
9860
9861         ering->tx_pending = tp->napi[0].tx_pending;
9862 }
9863
9864 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9865 {
9866         struct tg3 *tp = netdev_priv(dev);
9867         int i, irq_sync = 0, err = 0;
9868
9869         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9870             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9871             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9872             (ering->tx_pending <= MAX_SKB_FRAGS) ||
9873             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9874              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9875                 return -EINVAL;
9876
9877         if (netif_running(dev)) {
9878                 tg3_phy_stop(tp);
9879                 tg3_netif_stop(tp);
9880                 irq_sync = 1;
9881         }
9882
9883         tg3_full_lock(tp, irq_sync);
9884
9885         tp->rx_pending = ering->rx_pending;
9886
9887         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9888             tp->rx_pending > 63)
9889                 tp->rx_pending = 63;
9890         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9891
9892         for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9893                 tp->napi[i].tx_pending = ering->tx_pending;
9894
9895         if (netif_running(dev)) {
9896                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9897                 err = tg3_restart_hw(tp, 1);
9898                 if (!err)
9899                         tg3_netif_start(tp);
9900         }
9901
9902         tg3_full_unlock(tp);
9903
9904         if (irq_sync && !err)
9905                 tg3_phy_start(tp);
9906
9907         return err;
9908 }
9909
9910 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9911 {
9912         struct tg3 *tp = netdev_priv(dev);
9913
9914         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9915
9916         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9917                 epause->rx_pause = 1;
9918         else
9919                 epause->rx_pause = 0;
9920
9921         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9922                 epause->tx_pause = 1;
9923         else
9924                 epause->tx_pause = 0;
9925 }
9926
9927 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9928 {
9929         struct tg3 *tp = netdev_priv(dev);
9930         int err = 0;
9931
9932         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9933                 u32 newadv;
9934                 struct phy_device *phydev;
9935
9936                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9937
9938                 if (!(phydev->supported & SUPPORTED_Pause) ||
9939                     (!(phydev->supported & SUPPORTED_Asym_Pause) &&
9940                      ((epause->rx_pause && !epause->tx_pause) ||
9941                       (!epause->rx_pause && epause->tx_pause))))
9942                         return -EINVAL;
9943
9944                 tp->link_config.flowctrl = 0;
9945                 if (epause->rx_pause) {
9946                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
9947
9948                         if (epause->tx_pause) {
9949                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9950                                 newadv = ADVERTISED_Pause;
9951                         } else
9952                                 newadv = ADVERTISED_Pause |
9953                                          ADVERTISED_Asym_Pause;
9954                 } else if (epause->tx_pause) {
9955                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
9956                         newadv = ADVERTISED_Asym_Pause;
9957                 } else
9958                         newadv = 0;
9959
9960                 if (epause->autoneg)
9961                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9962                 else
9963                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9964
9965                 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9966                         u32 oldadv = phydev->advertising &
9967                                      (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
9968                         if (oldadv != newadv) {
9969                                 phydev->advertising &=
9970                                         ~(ADVERTISED_Pause |
9971                                           ADVERTISED_Asym_Pause);
9972                                 phydev->advertising |= newadv;
9973                                 if (phydev->autoneg) {
9974                                         /*
9975                                          * Always renegotiate the link to
9976                                          * inform our link partner of our
9977                                          * flow control settings, even if the
9978                                          * flow control is forced.  Let
9979                                          * tg3_adjust_link() do the final
9980                                          * flow control setup.
9981                                          */
9982                                         return phy_start_aneg(phydev);
9983                                 }
9984                         }
9985
9986                         if (!epause->autoneg)
9987                                 tg3_setup_flow_control(tp, 0, 0);
9988                 } else {
9989                         tp->link_config.orig_advertising &=
9990                                         ~(ADVERTISED_Pause |
9991                                           ADVERTISED_Asym_Pause);
9992                         tp->link_config.orig_advertising |= newadv;
9993                 }
9994         } else {
9995                 int irq_sync = 0;
9996
9997                 if (netif_running(dev)) {
9998                         tg3_netif_stop(tp);
9999                         irq_sync = 1;
10000                 }
10001
10002                 tg3_full_lock(tp, irq_sync);
10003
10004                 if (epause->autoneg)
10005                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10006                 else
10007                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10008                 if (epause->rx_pause)
10009                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
10010                 else
10011                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10012                 if (epause->tx_pause)
10013                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
10014                 else
10015                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10016
10017                 if (netif_running(dev)) {
10018                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10019                         err = tg3_restart_hw(tp, 1);
10020                         if (!err)
10021                                 tg3_netif_start(tp);
10022                 }
10023
10024                 tg3_full_unlock(tp);
10025         }
10026
10027         return err;
10028 }
10029
10030 static u32 tg3_get_rx_csum(struct net_device *dev)
10031 {
10032         struct tg3 *tp = netdev_priv(dev);
10033         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10034 }
10035
10036 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10037 {
10038         struct tg3 *tp = netdev_priv(dev);
10039
10040         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10041                 if (data != 0)
10042                         return -EINVAL;
10043                 return 0;
10044         }
10045
10046         spin_lock_bh(&tp->lock);
10047         if (data)
10048                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10049         else
10050                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10051         spin_unlock_bh(&tp->lock);
10052
10053         return 0;
10054 }
10055
10056 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10057 {
10058         struct tg3 *tp = netdev_priv(dev);
10059
10060         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10061                 if (data != 0)
10062                         return -EINVAL;
10063                 return 0;
10064         }
10065
10066         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10067                 ethtool_op_set_tx_ipv6_csum(dev, data);
10068         else
10069                 ethtool_op_set_tx_csum(dev, data);
10070
10071         return 0;
10072 }
10073
10074 static int tg3_get_sset_count(struct net_device *dev, int sset)
10075 {
10076         switch (sset) {
10077         case ETH_SS_TEST:
10078                 return TG3_NUM_TEST;
10079         case ETH_SS_STATS:
10080                 return TG3_NUM_STATS;
10081         default:
10082                 return -EOPNOTSUPP;
10083         }
10084 }
10085
10086 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
10087 {
10088         switch (stringset) {
10089         case ETH_SS_STATS:
10090                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10091                 break;
10092         case ETH_SS_TEST:
10093                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10094                 break;
10095         default:
10096                 WARN_ON(1);     /* we need a WARN() */
10097                 break;
10098         }
10099 }
10100
10101 static int tg3_phys_id(struct net_device *dev, u32 data)
10102 {
10103         struct tg3 *tp = netdev_priv(dev);
10104         int i;
10105
10106         if (!netif_running(tp->dev))
10107                 return -EAGAIN;
10108
10109         if (data == 0)
10110                 data = UINT_MAX / 2;
10111
10112         for (i = 0; i < (data * 2); i++) {
10113                 if ((i % 2) == 0)
10114                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10115                                            LED_CTRL_1000MBPS_ON |
10116                                            LED_CTRL_100MBPS_ON |
10117                                            LED_CTRL_10MBPS_ON |
10118                                            LED_CTRL_TRAFFIC_OVERRIDE |
10119                                            LED_CTRL_TRAFFIC_BLINK |
10120                                            LED_CTRL_TRAFFIC_LED);
10121
10122                 else
10123                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10124                                            LED_CTRL_TRAFFIC_OVERRIDE);
10125
10126                 if (msleep_interruptible(500))
10127                         break;
10128         }
10129         tw32(MAC_LED_CTRL, tp->led_ctrl);
10130         return 0;
10131 }
10132
10133 static void tg3_get_ethtool_stats(struct net_device *dev,
10134                                    struct ethtool_stats *estats, u64 *tmp_stats)
10135 {
10136         struct tg3 *tp = netdev_priv(dev);
10137         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10138 }
10139
10140 #define NVRAM_TEST_SIZE 0x100
10141 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
10142 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
10143 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
10144 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10145 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10146
10147 static int tg3_test_nvram(struct tg3 *tp)
10148 {
10149         u32 csum, magic;
10150         __be32 *buf;
10151         int i, j, k, err = 0, size;
10152
10153         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10154                 return 0;
10155
10156         if (tg3_nvram_read(tp, 0, &magic) != 0)
10157                 return -EIO;
10158
10159         if (magic == TG3_EEPROM_MAGIC)
10160                 size = NVRAM_TEST_SIZE;
10161         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10162                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10163                     TG3_EEPROM_SB_FORMAT_1) {
10164                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10165                         case TG3_EEPROM_SB_REVISION_0:
10166                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10167                                 break;
10168                         case TG3_EEPROM_SB_REVISION_2:
10169                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10170                                 break;
10171                         case TG3_EEPROM_SB_REVISION_3:
10172                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10173                                 break;
10174                         default:
10175                                 return 0;
10176                         }
10177                 } else
10178                         return 0;
10179         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10180                 size = NVRAM_SELFBOOT_HW_SIZE;
10181         else
10182                 return -EIO;
10183
10184         buf = kmalloc(size, GFP_KERNEL);
10185         if (buf == NULL)
10186                 return -ENOMEM;
10187
10188         err = -EIO;
10189         for (i = 0, j = 0; i < size; i += 4, j++) {
10190                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10191                 if (err)
10192                         break;
10193         }
10194         if (i < size)
10195                 goto out;
10196
10197         /* Selfboot format */
10198         magic = be32_to_cpu(buf[0]);
10199         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10200             TG3_EEPROM_MAGIC_FW) {
10201                 u8 *buf8 = (u8 *) buf, csum8 = 0;
10202
10203                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10204                     TG3_EEPROM_SB_REVISION_2) {
10205                         /* For rev 2, the csum doesn't include the MBA. */
10206                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10207                                 csum8 += buf8[i];
10208                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10209                                 csum8 += buf8[i];
10210                 } else {
10211                         for (i = 0; i < size; i++)
10212                                 csum8 += buf8[i];
10213                 }
10214
10215                 if (csum8 == 0) {
10216                         err = 0;
10217                         goto out;
10218                 }
10219
10220                 err = -EIO;
10221                 goto out;
10222         }
10223
10224         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10225             TG3_EEPROM_MAGIC_HW) {
10226                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10227                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10228                 u8 *buf8 = (u8 *) buf;
10229
10230                 /* Separate the parity bits and the data bytes.  */
10231                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10232                         if ((i == 0) || (i == 8)) {
10233                                 int l;
10234                                 u8 msk;
10235
10236                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10237                                         parity[k++] = buf8[i] & msk;
10238                                 i++;
10239                         } else if (i == 16) {
10240                                 int l;
10241                                 u8 msk;
10242
10243                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10244                                         parity[k++] = buf8[i] & msk;
10245                                 i++;
10246
10247                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10248                                         parity[k++] = buf8[i] & msk;
10249                                 i++;
10250                         }
10251                         data[j++] = buf8[i];
10252                 }
10253
10254                 err = -EIO;
10255                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10256                         u8 hw8 = hweight8(data[i]);
10257
10258                         if ((hw8 & 0x1) && parity[i])
10259                                 goto out;
10260                         else if (!(hw8 & 0x1) && !parity[i])
10261                                 goto out;
10262                 }
10263                 err = 0;
10264                 goto out;
10265         }
10266
10267         /* Bootstrap checksum at offset 0x10 */
10268         csum = calc_crc((unsigned char *) buf, 0x10);
10269         if (csum != be32_to_cpu(buf[0x10/4]))
10270                 goto out;
10271
10272         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10273         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10274         if (csum != be32_to_cpu(buf[0xfc/4]))
10275                 goto out;
10276
10277         err = 0;
10278
10279 out:
10280         kfree(buf);
10281         return err;
10282 }
10283
10284 #define TG3_SERDES_TIMEOUT_SEC  2
10285 #define TG3_COPPER_TIMEOUT_SEC  6
10286
10287 static int tg3_test_link(struct tg3 *tp)
10288 {
10289         int i, max;
10290
10291         if (!netif_running(tp->dev))
10292                 return -ENODEV;
10293
10294         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10295                 max = TG3_SERDES_TIMEOUT_SEC;
10296         else
10297                 max = TG3_COPPER_TIMEOUT_SEC;
10298
10299         for (i = 0; i < max; i++) {
10300                 if (netif_carrier_ok(tp->dev))
10301                         return 0;
10302
10303                 if (msleep_interruptible(1000))
10304                         break;
10305         }
10306
10307         return -EIO;
10308 }
10309
10310 /* Only test the commonly used registers */
10311 static int tg3_test_registers(struct tg3 *tp)
10312 {
10313         int i, is_5705, is_5750;
10314         u32 offset, read_mask, write_mask, val, save_val, read_val;
10315         static struct {
10316                 u16 offset;
10317                 u16 flags;
10318 #define TG3_FL_5705     0x1
10319 #define TG3_FL_NOT_5705 0x2
10320 #define TG3_FL_NOT_5788 0x4
10321 #define TG3_FL_NOT_5750 0x8
10322                 u32 read_mask;
10323                 u32 write_mask;
10324         } reg_tbl[] = {
10325                 /* MAC Control Registers */
10326                 { MAC_MODE, TG3_FL_NOT_5705,
10327                         0x00000000, 0x00ef6f8c },
10328                 { MAC_MODE, TG3_FL_5705,
10329                         0x00000000, 0x01ef6b8c },
10330                 { MAC_STATUS, TG3_FL_NOT_5705,
10331                         0x03800107, 0x00000000 },
10332                 { MAC_STATUS, TG3_FL_5705,
10333                         0x03800100, 0x00000000 },
10334                 { MAC_ADDR_0_HIGH, 0x0000,
10335                         0x00000000, 0x0000ffff },
10336                 { MAC_ADDR_0_LOW, 0x0000,
10337                         0x00000000, 0xffffffff },
10338                 { MAC_RX_MTU_SIZE, 0x0000,
10339                         0x00000000, 0x0000ffff },
10340                 { MAC_TX_MODE, 0x0000,
10341                         0x00000000, 0x00000070 },
10342                 { MAC_TX_LENGTHS, 0x0000,
10343                         0x00000000, 0x00003fff },
10344                 { MAC_RX_MODE, TG3_FL_NOT_5705,
10345                         0x00000000, 0x000007fc },
10346                 { MAC_RX_MODE, TG3_FL_5705,
10347                         0x00000000, 0x000007dc },
10348                 { MAC_HASH_REG_0, 0x0000,
10349                         0x00000000, 0xffffffff },
10350                 { MAC_HASH_REG_1, 0x0000,
10351                         0x00000000, 0xffffffff },
10352                 { MAC_HASH_REG_2, 0x0000,
10353                         0x00000000, 0xffffffff },
10354                 { MAC_HASH_REG_3, 0x0000,
10355                         0x00000000, 0xffffffff },
10356
10357                 /* Receive Data and Receive BD Initiator Control Registers. */
10358                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10359                         0x00000000, 0xffffffff },
10360                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10361                         0x00000000, 0xffffffff },
10362                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10363                         0x00000000, 0x00000003 },
10364                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10365                         0x00000000, 0xffffffff },
10366                 { RCVDBDI_STD_BD+0, 0x0000,
10367                         0x00000000, 0xffffffff },
10368                 { RCVDBDI_STD_BD+4, 0x0000,
10369                         0x00000000, 0xffffffff },
10370                 { RCVDBDI_STD_BD+8, 0x0000,
10371                         0x00000000, 0xffff0002 },
10372                 { RCVDBDI_STD_BD+0xc, 0x0000,
10373                         0x00000000, 0xffffffff },
10374
10375                 /* Receive BD Initiator Control Registers. */
10376                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10377                         0x00000000, 0xffffffff },
10378                 { RCVBDI_STD_THRESH, TG3_FL_5705,
10379                         0x00000000, 0x000003ff },
10380                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10381                         0x00000000, 0xffffffff },
10382
10383                 /* Host Coalescing Control Registers. */
10384                 { HOSTCC_MODE, TG3_FL_NOT_5705,
10385                         0x00000000, 0x00000004 },
10386                 { HOSTCC_MODE, TG3_FL_5705,
10387                         0x00000000, 0x000000f6 },
10388                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10389                         0x00000000, 0xffffffff },
10390                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10391                         0x00000000, 0x000003ff },
10392                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10393                         0x00000000, 0xffffffff },
10394                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10395                         0x00000000, 0x000003ff },
10396                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10397                         0x00000000, 0xffffffff },
10398                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10399                         0x00000000, 0x000000ff },
10400                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10401                         0x00000000, 0xffffffff },
10402                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10403                         0x00000000, 0x000000ff },
10404                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10405                         0x00000000, 0xffffffff },
10406                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10407                         0x00000000, 0xffffffff },
10408                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10409                         0x00000000, 0xffffffff },
10410                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10411                         0x00000000, 0x000000ff },
10412                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10413                         0x00000000, 0xffffffff },
10414                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10415                         0x00000000, 0x000000ff },
10416                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10417                         0x00000000, 0xffffffff },
10418                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10419                         0x00000000, 0xffffffff },
10420                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10421                         0x00000000, 0xffffffff },
10422                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10423                         0x00000000, 0xffffffff },
10424                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10425                         0x00000000, 0xffffffff },
10426                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10427                         0xffffffff, 0x00000000 },
10428                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10429                         0xffffffff, 0x00000000 },
10430
10431                 /* Buffer Manager Control Registers. */
10432                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10433                         0x00000000, 0x007fff80 },
10434                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10435                         0x00000000, 0x007fffff },
10436                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10437                         0x00000000, 0x0000003f },
10438                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10439                         0x00000000, 0x000001ff },
10440                 { BUFMGR_MB_HIGH_WATER, 0x0000,
10441                         0x00000000, 0x000001ff },
10442                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10443                         0xffffffff, 0x00000000 },
10444                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10445                         0xffffffff, 0x00000000 },
10446
10447                 /* Mailbox Registers */
10448                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10449                         0x00000000, 0x000001ff },
10450                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10451                         0x00000000, 0x000001ff },
10452                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10453                         0x00000000, 0x000007ff },
10454                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10455                         0x00000000, 0x000001ff },
10456
10457                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10458         };
10459
10460         is_5705 = is_5750 = 0;
10461         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10462                 is_5705 = 1;
10463                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10464                         is_5750 = 1;
10465         }
10466
10467         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10468                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10469                         continue;
10470
10471                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10472                         continue;
10473
10474                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10475                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
10476                         continue;
10477
10478                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10479                         continue;
10480
10481                 offset = (u32) reg_tbl[i].offset;
10482                 read_mask = reg_tbl[i].read_mask;
10483                 write_mask = reg_tbl[i].write_mask;
10484
10485                 /* Save the original register content */
10486                 save_val = tr32(offset);
10487
10488                 /* Determine the read-only value. */
10489                 read_val = save_val & read_mask;
10490
10491                 /* Write zero to the register, then make sure the read-only bits
10492                  * are not changed and the read/write bits are all zeros.
10493                  */
10494                 tw32(offset, 0);
10495
10496                 val = tr32(offset);
10497
10498                 /* Test the read-only and read/write bits. */
10499                 if (((val & read_mask) != read_val) || (val & write_mask))
10500                         goto out;
10501
10502                 /* Write ones to all the bits defined by RdMask and WrMask, then
10503                  * make sure the read-only bits are not changed and the
10504                  * read/write bits are all ones.
10505                  */
10506                 tw32(offset, read_mask | write_mask);
10507
10508                 val = tr32(offset);
10509
10510                 /* Test the read-only bits. */
10511                 if ((val & read_mask) != read_val)
10512                         goto out;
10513
10514                 /* Test the read/write bits. */
10515                 if ((val & write_mask) != write_mask)
10516                         goto out;
10517
10518                 tw32(offset, save_val);
10519         }
10520
10521         return 0;
10522
10523 out:
10524         if (netif_msg_hw(tp))
10525                 netdev_err(tp->dev,
10526                            "Register test failed at offset %x\n", offset);
10527         tw32(offset, save_val);
10528         return -EIO;
10529 }
10530
10531 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10532 {
10533         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10534         int i;
10535         u32 j;
10536
10537         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10538                 for (j = 0; j < len; j += 4) {
10539                         u32 val;
10540
10541                         tg3_write_mem(tp, offset + j, test_pattern[i]);
10542                         tg3_read_mem(tp, offset + j, &val);
10543                         if (val != test_pattern[i])
10544                                 return -EIO;
10545                 }
10546         }
10547         return 0;
10548 }
10549
10550 static int tg3_test_memory(struct tg3 *tp)
10551 {
10552         static struct mem_entry {
10553                 u32 offset;
10554                 u32 len;
10555         } mem_tbl_570x[] = {
10556                 { 0x00000000, 0x00b50},
10557                 { 0x00002000, 0x1c000},
10558                 { 0xffffffff, 0x00000}
10559         }, mem_tbl_5705[] = {
10560                 { 0x00000100, 0x0000c},
10561                 { 0x00000200, 0x00008},
10562                 { 0x00004000, 0x00800},
10563                 { 0x00006000, 0x01000},
10564                 { 0x00008000, 0x02000},
10565                 { 0x00010000, 0x0e000},
10566                 { 0xffffffff, 0x00000}
10567         }, mem_tbl_5755[] = {
10568                 { 0x00000200, 0x00008},
10569                 { 0x00004000, 0x00800},
10570                 { 0x00006000, 0x00800},
10571                 { 0x00008000, 0x02000},
10572                 { 0x00010000, 0x0c000},
10573                 { 0xffffffff, 0x00000}
10574         }, mem_tbl_5906[] = {
10575                 { 0x00000200, 0x00008},
10576                 { 0x00004000, 0x00400},
10577                 { 0x00006000, 0x00400},
10578                 { 0x00008000, 0x01000},
10579                 { 0x00010000, 0x01000},
10580                 { 0xffffffff, 0x00000}
10581         }, mem_tbl_5717[] = {
10582                 { 0x00000200, 0x00008},
10583                 { 0x00010000, 0x0a000},
10584                 { 0x00020000, 0x13c00},
10585                 { 0xffffffff, 0x00000}
10586         }, mem_tbl_57765[] = {
10587                 { 0x00000200, 0x00008},
10588                 { 0x00004000, 0x00800},
10589                 { 0x00006000, 0x09800},
10590                 { 0x00010000, 0x0a000},
10591                 { 0xffffffff, 0x00000}
10592         };
10593         struct mem_entry *mem_tbl;
10594         int err = 0;
10595         int i;
10596
10597         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
10598             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
10599                 mem_tbl = mem_tbl_5717;
10600         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10601                 mem_tbl = mem_tbl_57765;
10602         else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10603                 mem_tbl = mem_tbl_5755;
10604         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10605                 mem_tbl = mem_tbl_5906;
10606         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10607                 mem_tbl = mem_tbl_5705;
10608         else
10609                 mem_tbl = mem_tbl_570x;
10610
10611         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10612                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10613                     mem_tbl[i].len)) != 0)
10614                         break;
10615         }
10616
10617         return err;
10618 }
10619
10620 #define TG3_MAC_LOOPBACK        0
10621 #define TG3_PHY_LOOPBACK        1
10622
10623 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10624 {
10625         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10626         u32 desc_idx, coal_now;
10627         struct sk_buff *skb, *rx_skb;
10628         u8 *tx_data;
10629         dma_addr_t map;
10630         int num_pkts, tx_len, rx_len, i, err;
10631         struct tg3_rx_buffer_desc *desc;
10632         struct tg3_napi *tnapi, *rnapi;
10633         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
10634
10635         tnapi = &tp->napi[0];
10636         rnapi = &tp->napi[0];
10637         if (tp->irq_cnt > 1) {
10638                 rnapi = &tp->napi[1];
10639                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
10640                         tnapi = &tp->napi[1];
10641         }
10642         coal_now = tnapi->coal_now | rnapi->coal_now;
10643
10644         if (loopback_mode == TG3_MAC_LOOPBACK) {
10645                 /* HW errata - mac loopback fails in some cases on 5780.
10646                  * Normal traffic and PHY loopback are not affected by
10647                  * errata.
10648                  */
10649                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10650                         return 0;
10651
10652                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10653                            MAC_MODE_PORT_INT_LPBACK;
10654                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10655                         mac_mode |= MAC_MODE_LINK_POLARITY;
10656                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10657                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10658                 else
10659                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10660                 tw32(MAC_MODE, mac_mode);
10661         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10662                 u32 val;
10663
10664                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10665                         tg3_phy_fet_toggle_apd(tp, false);
10666                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10667                 } else
10668                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10669
10670                 tg3_phy_toggle_automdix(tp, 0);
10671
10672                 tg3_writephy(tp, MII_BMCR, val);
10673                 udelay(40);
10674
10675                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10676                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10677                         tg3_writephy(tp, MII_TG3_FET_PTEST,
10678                                      MII_TG3_FET_PTEST_FRC_TX_LINK |
10679                                      MII_TG3_FET_PTEST_FRC_TX_LOCK);
10680                         /* The write needs to be flushed for the AC131 */
10681                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10682                                 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
10683                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10684                 } else
10685                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10686
10687                 /* reset to prevent losing 1st rx packet intermittently */
10688                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10689                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10690                         udelay(10);
10691                         tw32_f(MAC_RX_MODE, tp->rx_mode);
10692                 }
10693                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10694                         u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
10695                         if (masked_phy_id == TG3_PHY_ID_BCM5401)
10696                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10697                         else if (masked_phy_id == TG3_PHY_ID_BCM5411)
10698                                 mac_mode |= MAC_MODE_LINK_POLARITY;
10699                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
10700                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10701                 }
10702                 tw32(MAC_MODE, mac_mode);
10703         } else {
10704                 return -EINVAL;
10705         }
10706
10707         err = -EIO;
10708
10709         tx_len = 1514;
10710         skb = netdev_alloc_skb(tp->dev, tx_len);
10711         if (!skb)
10712                 return -ENOMEM;
10713
10714         tx_data = skb_put(skb, tx_len);
10715         memcpy(tx_data, tp->dev->dev_addr, 6);
10716         memset(tx_data + 6, 0x0, 8);
10717
10718         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10719
10720         for (i = 14; i < tx_len; i++)
10721                 tx_data[i] = (u8) (i & 0xff);
10722
10723         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10724         if (pci_dma_mapping_error(tp->pdev, map)) {
10725                 dev_kfree_skb(skb);
10726                 return -EIO;
10727         }
10728
10729         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10730                rnapi->coal_now);
10731
10732         udelay(10);
10733
10734         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10735
10736         num_pkts = 0;
10737
10738         tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10739
10740         tnapi->tx_prod++;
10741         num_pkts++;
10742
10743         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10744         tr32_mailbox(tnapi->prodmbox);
10745
10746         udelay(10);
10747
10748         /* 350 usec to allow enough time on some 10/100 Mbps devices.  */
10749         for (i = 0; i < 35; i++) {
10750                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10751                        coal_now);
10752
10753                 udelay(10);
10754
10755                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10756                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10757                 if ((tx_idx == tnapi->tx_prod) &&
10758                     (rx_idx == (rx_start_idx + num_pkts)))
10759                         break;
10760         }
10761
10762         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10763         dev_kfree_skb(skb);
10764
10765         if (tx_idx != tnapi->tx_prod)
10766                 goto out;
10767
10768         if (rx_idx != rx_start_idx + num_pkts)
10769                 goto out;
10770
10771         desc = &rnapi->rx_rcb[rx_start_idx];
10772         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10773         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10774         if (opaque_key != RXD_OPAQUE_RING_STD)
10775                 goto out;
10776
10777         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10778             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10779                 goto out;
10780
10781         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10782         if (rx_len != tx_len)
10783                 goto out;
10784
10785         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10786
10787         map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10788         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10789
10790         for (i = 14; i < tx_len; i++) {
10791                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10792                         goto out;
10793         }
10794         err = 0;
10795
10796         /* tg3_free_rings will unmap and free the rx_skb */
10797 out:
10798         return err;
10799 }
10800
10801 #define TG3_MAC_LOOPBACK_FAILED         1
10802 #define TG3_PHY_LOOPBACK_FAILED         2
10803 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
10804                                          TG3_PHY_LOOPBACK_FAILED)
10805
10806 static int tg3_test_loopback(struct tg3 *tp)
10807 {
10808         int err = 0;
10809         u32 cpmuctrl = 0;
10810
10811         if (!netif_running(tp->dev))
10812                 return TG3_LOOPBACK_FAILED;
10813
10814         err = tg3_reset_hw(tp, 1);
10815         if (err)
10816                 return TG3_LOOPBACK_FAILED;
10817
10818         /* Turn off gphy autopowerdown. */
10819         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10820                 tg3_phy_toggle_apd(tp, false);
10821
10822         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10823                 int i;
10824                 u32 status;
10825
10826                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10827
10828                 /* Wait for up to 40 microseconds to acquire lock. */
10829                 for (i = 0; i < 4; i++) {
10830                         status = tr32(TG3_CPMU_MUTEX_GNT);
10831                         if (status == CPMU_MUTEX_GNT_DRIVER)
10832                                 break;
10833                         udelay(10);
10834                 }
10835
10836                 if (status != CPMU_MUTEX_GNT_DRIVER)
10837                         return TG3_LOOPBACK_FAILED;
10838
10839                 /* Turn off link-based power management. */
10840                 cpmuctrl = tr32(TG3_CPMU_CTRL);
10841                 tw32(TG3_CPMU_CTRL,
10842                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10843                                   CPMU_CTRL_LINK_AWARE_MODE));
10844         }
10845
10846         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10847                 err |= TG3_MAC_LOOPBACK_FAILED;
10848
10849         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10850                 tw32(TG3_CPMU_CTRL, cpmuctrl);
10851
10852                 /* Release the mutex */
10853                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10854         }
10855
10856         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10857             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10858                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10859                         err |= TG3_PHY_LOOPBACK_FAILED;
10860         }
10861
10862         /* Re-enable gphy autopowerdown. */
10863         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10864                 tg3_phy_toggle_apd(tp, true);
10865
10866         return err;
10867 }
10868
10869 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10870                           u64 *data)
10871 {
10872         struct tg3 *tp = netdev_priv(dev);
10873
10874         if (tp->link_config.phy_is_low_power)
10875                 tg3_set_power_state(tp, PCI_D0);
10876
10877         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10878
10879         if (tg3_test_nvram(tp) != 0) {
10880                 etest->flags |= ETH_TEST_FL_FAILED;
10881                 data[0] = 1;
10882         }
10883         if (tg3_test_link(tp) != 0) {
10884                 etest->flags |= ETH_TEST_FL_FAILED;
10885                 data[1] = 1;
10886         }
10887         if (etest->flags & ETH_TEST_FL_OFFLINE) {
10888                 int err, err2 = 0, irq_sync = 0;
10889
10890                 if (netif_running(dev)) {
10891                         tg3_phy_stop(tp);
10892                         tg3_netif_stop(tp);
10893                         irq_sync = 1;
10894                 }
10895
10896                 tg3_full_lock(tp, irq_sync);
10897
10898                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10899                 err = tg3_nvram_lock(tp);
10900                 tg3_halt_cpu(tp, RX_CPU_BASE);
10901                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10902                         tg3_halt_cpu(tp, TX_CPU_BASE);
10903                 if (!err)
10904                         tg3_nvram_unlock(tp);
10905
10906                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10907                         tg3_phy_reset(tp);
10908
10909                 if (tg3_test_registers(tp) != 0) {
10910                         etest->flags |= ETH_TEST_FL_FAILED;
10911                         data[2] = 1;
10912                 }
10913                 if (tg3_test_memory(tp) != 0) {
10914                         etest->flags |= ETH_TEST_FL_FAILED;
10915                         data[3] = 1;
10916                 }
10917                 if ((data[4] = tg3_test_loopback(tp)) != 0)
10918                         etest->flags |= ETH_TEST_FL_FAILED;
10919
10920                 tg3_full_unlock(tp);
10921
10922                 if (tg3_test_interrupt(tp) != 0) {
10923                         etest->flags |= ETH_TEST_FL_FAILED;
10924                         data[5] = 1;
10925                 }
10926
10927                 tg3_full_lock(tp, 0);
10928
10929                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10930                 if (netif_running(dev)) {
10931                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10932                         err2 = tg3_restart_hw(tp, 1);
10933                         if (!err2)
10934                                 tg3_netif_start(tp);
10935                 }
10936
10937                 tg3_full_unlock(tp);
10938
10939                 if (irq_sync && !err2)
10940                         tg3_phy_start(tp);
10941         }
10942         if (tp->link_config.phy_is_low_power)
10943                 tg3_set_power_state(tp, PCI_D3hot);
10944
10945 }
10946
10947 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10948 {
10949         struct mii_ioctl_data *data = if_mii(ifr);
10950         struct tg3 *tp = netdev_priv(dev);
10951         int err;
10952
10953         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10954                 struct phy_device *phydev;
10955                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10956                         return -EAGAIN;
10957                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10958                 return phy_mii_ioctl(phydev, data, cmd);
10959         }
10960
10961         switch (cmd) {
10962         case SIOCGMIIPHY:
10963                 data->phy_id = tp->phy_addr;
10964
10965                 /* fallthru */
10966         case SIOCGMIIREG: {
10967                 u32 mii_regval;
10968
10969                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10970                         break;                  /* We have no PHY */
10971
10972                 if (tp->link_config.phy_is_low_power)
10973                         return -EAGAIN;
10974
10975                 spin_lock_bh(&tp->lock);
10976                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10977                 spin_unlock_bh(&tp->lock);
10978
10979                 data->val_out = mii_regval;
10980
10981                 return err;
10982         }
10983
10984         case SIOCSMIIREG:
10985                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10986                         break;                  /* We have no PHY */
10987
10988                 if (tp->link_config.phy_is_low_power)
10989                         return -EAGAIN;
10990
10991                 spin_lock_bh(&tp->lock);
10992                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10993                 spin_unlock_bh(&tp->lock);
10994
10995                 return err;
10996
10997         default:
10998                 /* do nothing */
10999                 break;
11000         }
11001         return -EOPNOTSUPP;
11002 }
11003
11004 #if TG3_VLAN_TAG_USED
11005 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
11006 {
11007         struct tg3 *tp = netdev_priv(dev);
11008
11009         if (!netif_running(dev)) {
11010                 tp->vlgrp = grp;
11011                 return;
11012         }
11013
11014         tg3_netif_stop(tp);
11015
11016         tg3_full_lock(tp, 0);
11017
11018         tp->vlgrp = grp;
11019
11020         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11021         __tg3_set_rx_mode(dev);
11022
11023         tg3_netif_start(tp);
11024
11025         tg3_full_unlock(tp);
11026 }
11027 #endif
11028
11029 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11030 {
11031         struct tg3 *tp = netdev_priv(dev);
11032
11033         memcpy(ec, &tp->coal, sizeof(*ec));
11034         return 0;
11035 }
11036
11037 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11038 {
11039         struct tg3 *tp = netdev_priv(dev);
11040         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11041         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11042
11043         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11044                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11045                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11046                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11047                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11048         }
11049
11050         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11051             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11052             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11053             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11054             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11055             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11056             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11057             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11058             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11059             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11060                 return -EINVAL;
11061
11062         /* No rx interrupts will be generated if both are zero */
11063         if ((ec->rx_coalesce_usecs == 0) &&
11064             (ec->rx_max_coalesced_frames == 0))
11065                 return -EINVAL;
11066
11067         /* No tx interrupts will be generated if both are zero */
11068         if ((ec->tx_coalesce_usecs == 0) &&
11069             (ec->tx_max_coalesced_frames == 0))
11070                 return -EINVAL;
11071
11072         /* Only copy relevant parameters, ignore all others. */
11073         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11074         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11075         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11076         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11077         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11078         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11079         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11080         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11081         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11082
11083         if (netif_running(dev)) {
11084                 tg3_full_lock(tp, 0);
11085                 __tg3_set_coalesce(tp, &tp->coal);
11086                 tg3_full_unlock(tp);
11087         }
11088         return 0;
11089 }
11090
11091 static const struct ethtool_ops tg3_ethtool_ops = {
11092         .get_settings           = tg3_get_settings,
11093         .set_settings           = tg3_set_settings,
11094         .get_drvinfo            = tg3_get_drvinfo,
11095         .get_regs_len           = tg3_get_regs_len,
11096         .get_regs               = tg3_get_regs,
11097         .get_wol                = tg3_get_wol,
11098         .set_wol                = tg3_set_wol,
11099         .get_msglevel           = tg3_get_msglevel,
11100         .set_msglevel           = tg3_set_msglevel,
11101         .nway_reset             = tg3_nway_reset,
11102         .get_link               = ethtool_op_get_link,
11103         .get_eeprom_len         = tg3_get_eeprom_len,
11104         .get_eeprom             = tg3_get_eeprom,
11105         .set_eeprom             = tg3_set_eeprom,
11106         .get_ringparam          = tg3_get_ringparam,
11107         .set_ringparam          = tg3_set_ringparam,
11108         .get_pauseparam         = tg3_get_pauseparam,
11109         .set_pauseparam         = tg3_set_pauseparam,
11110         .get_rx_csum            = tg3_get_rx_csum,
11111         .set_rx_csum            = tg3_set_rx_csum,
11112         .set_tx_csum            = tg3_set_tx_csum,
11113         .set_sg                 = ethtool_op_set_sg,
11114         .set_tso                = tg3_set_tso,
11115         .self_test              = tg3_self_test,
11116         .get_strings            = tg3_get_strings,
11117         .phys_id                = tg3_phys_id,
11118         .get_ethtool_stats      = tg3_get_ethtool_stats,
11119         .get_coalesce           = tg3_get_coalesce,
11120         .set_coalesce           = tg3_set_coalesce,
11121         .get_sset_count         = tg3_get_sset_count,
11122 };
11123
11124 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11125 {
11126         u32 cursize, val, magic;
11127
11128         tp->nvram_size = EEPROM_CHIP_SIZE;
11129
11130         if (tg3_nvram_read(tp, 0, &magic) != 0)
11131                 return;
11132
11133         if ((magic != TG3_EEPROM_MAGIC) &&
11134             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11135             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11136                 return;
11137
11138         /*
11139          * Size the chip by reading offsets at increasing powers of two.
11140          * When we encounter our validation signature, we know the addressing
11141          * has wrapped around, and thus have our chip size.
11142          */
11143         cursize = 0x10;
11144
11145         while (cursize < tp->nvram_size) {
11146                 if (tg3_nvram_read(tp, cursize, &val) != 0)
11147                         return;
11148
11149                 if (val == magic)
11150                         break;
11151
11152                 cursize <<= 1;
11153         }
11154
11155         tp->nvram_size = cursize;
11156 }
11157
11158 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11159 {
11160         u32 val;
11161
11162         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11163             tg3_nvram_read(tp, 0, &val) != 0)
11164                 return;
11165
11166         /* Selfboot format */
11167         if (val != TG3_EEPROM_MAGIC) {
11168                 tg3_get_eeprom_size(tp);
11169                 return;
11170         }
11171
11172         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11173                 if (val != 0) {
11174                         /* This is confusing.  We want to operate on the
11175                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
11176                          * call will read from NVRAM and byteswap the data
11177                          * according to the byteswapping settings for all
11178                          * other register accesses.  This ensures the data we
11179                          * want will always reside in the lower 16-bits.
11180                          * However, the data in NVRAM is in LE format, which
11181                          * means the data from the NVRAM read will always be
11182                          * opposite the endianness of the CPU.  The 16-bit
11183                          * byteswap then brings the data to CPU endianness.
11184                          */
11185                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11186                         return;
11187                 }
11188         }
11189         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11190 }
11191
11192 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11193 {
11194         u32 nvcfg1;
11195
11196         nvcfg1 = tr32(NVRAM_CFG1);
11197         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11198                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11199         } else {
11200                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11201                 tw32(NVRAM_CFG1, nvcfg1);
11202         }
11203
11204         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11205             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11206                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11207                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11208                         tp->nvram_jedecnum = JEDEC_ATMEL;
11209                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11210                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11211                         break;
11212                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11213                         tp->nvram_jedecnum = JEDEC_ATMEL;
11214                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11215                         break;
11216                 case FLASH_VENDOR_ATMEL_EEPROM:
11217                         tp->nvram_jedecnum = JEDEC_ATMEL;
11218                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11219                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11220                         break;
11221                 case FLASH_VENDOR_ST:
11222                         tp->nvram_jedecnum = JEDEC_ST;
11223                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11224                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11225                         break;
11226                 case FLASH_VENDOR_SAIFUN:
11227                         tp->nvram_jedecnum = JEDEC_SAIFUN;
11228                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11229                         break;
11230                 case FLASH_VENDOR_SST_SMALL:
11231                 case FLASH_VENDOR_SST_LARGE:
11232                         tp->nvram_jedecnum = JEDEC_SST;
11233                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11234                         break;
11235                 }
11236         } else {
11237                 tp->nvram_jedecnum = JEDEC_ATMEL;
11238                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11239                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11240         }
11241 }
11242
11243 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11244 {
11245         switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11246         case FLASH_5752PAGE_SIZE_256:
11247                 tp->nvram_pagesize = 256;
11248                 break;
11249         case FLASH_5752PAGE_SIZE_512:
11250                 tp->nvram_pagesize = 512;
11251                 break;
11252         case FLASH_5752PAGE_SIZE_1K:
11253                 tp->nvram_pagesize = 1024;
11254                 break;
11255         case FLASH_5752PAGE_SIZE_2K:
11256                 tp->nvram_pagesize = 2048;
11257                 break;
11258         case FLASH_5752PAGE_SIZE_4K:
11259                 tp->nvram_pagesize = 4096;
11260                 break;
11261         case FLASH_5752PAGE_SIZE_264:
11262                 tp->nvram_pagesize = 264;
11263                 break;
11264         case FLASH_5752PAGE_SIZE_528:
11265                 tp->nvram_pagesize = 528;
11266                 break;
11267         }
11268 }
11269
11270 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11271 {
11272         u32 nvcfg1;
11273
11274         nvcfg1 = tr32(NVRAM_CFG1);
11275
11276         /* NVRAM protection for TPM */
11277         if (nvcfg1 & (1 << 27))
11278                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11279
11280         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11281         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11282         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11283                 tp->nvram_jedecnum = JEDEC_ATMEL;
11284                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11285                 break;
11286         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11287                 tp->nvram_jedecnum = JEDEC_ATMEL;
11288                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11289                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11290                 break;
11291         case FLASH_5752VENDOR_ST_M45PE10:
11292         case FLASH_5752VENDOR_ST_M45PE20:
11293         case FLASH_5752VENDOR_ST_M45PE40:
11294                 tp->nvram_jedecnum = JEDEC_ST;
11295                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11296                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11297                 break;
11298         }
11299
11300         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11301                 tg3_nvram_get_pagesize(tp, nvcfg1);
11302         } else {
11303                 /* For eeprom, set pagesize to maximum eeprom size */
11304                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11305
11306                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11307                 tw32(NVRAM_CFG1, nvcfg1);
11308         }
11309 }
11310
11311 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11312 {
11313         u32 nvcfg1, protect = 0;
11314
11315         nvcfg1 = tr32(NVRAM_CFG1);
11316
11317         /* NVRAM protection for TPM */
11318         if (nvcfg1 & (1 << 27)) {
11319                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11320                 protect = 1;
11321         }
11322
11323         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11324         switch (nvcfg1) {
11325         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11326         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11327         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11328         case FLASH_5755VENDOR_ATMEL_FLASH_5:
11329                 tp->nvram_jedecnum = JEDEC_ATMEL;
11330                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11331                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11332                 tp->nvram_pagesize = 264;
11333                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11334                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11335                         tp->nvram_size = (protect ? 0x3e200 :
11336                                           TG3_NVRAM_SIZE_512KB);
11337                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11338                         tp->nvram_size = (protect ? 0x1f200 :
11339                                           TG3_NVRAM_SIZE_256KB);
11340                 else
11341                         tp->nvram_size = (protect ? 0x1f200 :
11342                                           TG3_NVRAM_SIZE_128KB);
11343                 break;
11344         case FLASH_5752VENDOR_ST_M45PE10:
11345         case FLASH_5752VENDOR_ST_M45PE20:
11346         case FLASH_5752VENDOR_ST_M45PE40:
11347                 tp->nvram_jedecnum = JEDEC_ST;
11348                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11349                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11350                 tp->nvram_pagesize = 256;
11351                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11352                         tp->nvram_size = (protect ?
11353                                           TG3_NVRAM_SIZE_64KB :
11354                                           TG3_NVRAM_SIZE_128KB);
11355                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11356                         tp->nvram_size = (protect ?
11357                                           TG3_NVRAM_SIZE_64KB :
11358                                           TG3_NVRAM_SIZE_256KB);
11359                 else
11360                         tp->nvram_size = (protect ?
11361                                           TG3_NVRAM_SIZE_128KB :
11362                                           TG3_NVRAM_SIZE_512KB);
11363                 break;
11364         }
11365 }
11366
11367 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11368 {
11369         u32 nvcfg1;
11370
11371         nvcfg1 = tr32(NVRAM_CFG1);
11372
11373         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11374         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11375         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11376         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11377         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11378                 tp->nvram_jedecnum = JEDEC_ATMEL;
11379                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11380                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11381
11382                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11383                 tw32(NVRAM_CFG1, nvcfg1);
11384                 break;
11385         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11386         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11387         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11388         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11389                 tp->nvram_jedecnum = JEDEC_ATMEL;
11390                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11391                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11392                 tp->nvram_pagesize = 264;
11393                 break;
11394         case FLASH_5752VENDOR_ST_M45PE10:
11395         case FLASH_5752VENDOR_ST_M45PE20:
11396         case FLASH_5752VENDOR_ST_M45PE40:
11397                 tp->nvram_jedecnum = JEDEC_ST;
11398                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11399                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11400                 tp->nvram_pagesize = 256;
11401                 break;
11402         }
11403 }
11404
11405 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11406 {
11407         u32 nvcfg1, protect = 0;
11408
11409         nvcfg1 = tr32(NVRAM_CFG1);
11410
11411         /* NVRAM protection for TPM */
11412         if (nvcfg1 & (1 << 27)) {
11413                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11414                 protect = 1;
11415         }
11416
11417         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11418         switch (nvcfg1) {
11419         case FLASH_5761VENDOR_ATMEL_ADB021D:
11420         case FLASH_5761VENDOR_ATMEL_ADB041D:
11421         case FLASH_5761VENDOR_ATMEL_ADB081D:
11422         case FLASH_5761VENDOR_ATMEL_ADB161D:
11423         case FLASH_5761VENDOR_ATMEL_MDB021D:
11424         case FLASH_5761VENDOR_ATMEL_MDB041D:
11425         case FLASH_5761VENDOR_ATMEL_MDB081D:
11426         case FLASH_5761VENDOR_ATMEL_MDB161D:
11427                 tp->nvram_jedecnum = JEDEC_ATMEL;
11428                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11429                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11430                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11431                 tp->nvram_pagesize = 256;
11432                 break;
11433         case FLASH_5761VENDOR_ST_A_M45PE20:
11434         case FLASH_5761VENDOR_ST_A_M45PE40:
11435         case FLASH_5761VENDOR_ST_A_M45PE80:
11436         case FLASH_5761VENDOR_ST_A_M45PE16:
11437         case FLASH_5761VENDOR_ST_M_M45PE20:
11438         case FLASH_5761VENDOR_ST_M_M45PE40:
11439         case FLASH_5761VENDOR_ST_M_M45PE80:
11440         case FLASH_5761VENDOR_ST_M_M45PE16:
11441                 tp->nvram_jedecnum = JEDEC_ST;
11442                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11443                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11444                 tp->nvram_pagesize = 256;
11445                 break;
11446         }
11447
11448         if (protect) {
11449                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11450         } else {
11451                 switch (nvcfg1) {
11452                 case FLASH_5761VENDOR_ATMEL_ADB161D:
11453                 case FLASH_5761VENDOR_ATMEL_MDB161D:
11454                 case FLASH_5761VENDOR_ST_A_M45PE16:
11455                 case FLASH_5761VENDOR_ST_M_M45PE16:
11456                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11457                         break;
11458                 case FLASH_5761VENDOR_ATMEL_ADB081D:
11459                 case FLASH_5761VENDOR_ATMEL_MDB081D:
11460                 case FLASH_5761VENDOR_ST_A_M45PE80:
11461                 case FLASH_5761VENDOR_ST_M_M45PE80:
11462                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11463                         break;
11464                 case FLASH_5761VENDOR_ATMEL_ADB041D:
11465                 case FLASH_5761VENDOR_ATMEL_MDB041D:
11466                 case FLASH_5761VENDOR_ST_A_M45PE40:
11467                 case FLASH_5761VENDOR_ST_M_M45PE40:
11468                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11469                         break;
11470                 case FLASH_5761VENDOR_ATMEL_ADB021D:
11471                 case FLASH_5761VENDOR_ATMEL_MDB021D:
11472                 case FLASH_5761VENDOR_ST_A_M45PE20:
11473                 case FLASH_5761VENDOR_ST_M_M45PE20:
11474                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11475                         break;
11476                 }
11477         }
11478 }
11479
11480 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11481 {
11482         tp->nvram_jedecnum = JEDEC_ATMEL;
11483         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11484         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11485 }
11486
11487 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11488 {
11489         u32 nvcfg1;
11490
11491         nvcfg1 = tr32(NVRAM_CFG1);
11492
11493         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11494         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11495         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11496                 tp->nvram_jedecnum = JEDEC_ATMEL;
11497                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11498                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11499
11500                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11501                 tw32(NVRAM_CFG1, nvcfg1);
11502                 return;
11503         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11504         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11505         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11506         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11507         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11508         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11509         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11510                 tp->nvram_jedecnum = JEDEC_ATMEL;
11511                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11512                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11513
11514                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11515                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11516                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11517                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11518                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11519                         break;
11520                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11521                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11522                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11523                         break;
11524                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11525                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11526                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11527                         break;
11528                 }
11529                 break;
11530         case FLASH_5752VENDOR_ST_M45PE10:
11531         case FLASH_5752VENDOR_ST_M45PE20:
11532         case FLASH_5752VENDOR_ST_M45PE40:
11533                 tp->nvram_jedecnum = JEDEC_ST;
11534                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11535                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11536
11537                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11538                 case FLASH_5752VENDOR_ST_M45PE10:
11539                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11540                         break;
11541                 case FLASH_5752VENDOR_ST_M45PE20:
11542                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11543                         break;
11544                 case FLASH_5752VENDOR_ST_M45PE40:
11545                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11546                         break;
11547                 }
11548                 break;
11549         default:
11550                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11551                 return;
11552         }
11553
11554         tg3_nvram_get_pagesize(tp, nvcfg1);
11555         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11556                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11557 }
11558
11559
11560 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11561 {
11562         u32 nvcfg1;
11563
11564         nvcfg1 = tr32(NVRAM_CFG1);
11565
11566         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11567         case FLASH_5717VENDOR_ATMEL_EEPROM:
11568         case FLASH_5717VENDOR_MICRO_EEPROM:
11569                 tp->nvram_jedecnum = JEDEC_ATMEL;
11570                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11571                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11572
11573                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11574                 tw32(NVRAM_CFG1, nvcfg1);
11575                 return;
11576         case FLASH_5717VENDOR_ATMEL_MDB011D:
11577         case FLASH_5717VENDOR_ATMEL_ADB011B:
11578         case FLASH_5717VENDOR_ATMEL_ADB011D:
11579         case FLASH_5717VENDOR_ATMEL_MDB021D:
11580         case FLASH_5717VENDOR_ATMEL_ADB021B:
11581         case FLASH_5717VENDOR_ATMEL_ADB021D:
11582         case FLASH_5717VENDOR_ATMEL_45USPT:
11583                 tp->nvram_jedecnum = JEDEC_ATMEL;
11584                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11585                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11586
11587                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11588                 case FLASH_5717VENDOR_ATMEL_MDB021D:
11589                 case FLASH_5717VENDOR_ATMEL_ADB021B:
11590                 case FLASH_5717VENDOR_ATMEL_ADB021D:
11591                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11592                         break;
11593                 default:
11594                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11595                         break;
11596                 }
11597                 break;
11598         case FLASH_5717VENDOR_ST_M_M25PE10:
11599         case FLASH_5717VENDOR_ST_A_M25PE10:
11600         case FLASH_5717VENDOR_ST_M_M45PE10:
11601         case FLASH_5717VENDOR_ST_A_M45PE10:
11602         case FLASH_5717VENDOR_ST_M_M25PE20:
11603         case FLASH_5717VENDOR_ST_A_M25PE20:
11604         case FLASH_5717VENDOR_ST_M_M45PE20:
11605         case FLASH_5717VENDOR_ST_A_M45PE20:
11606         case FLASH_5717VENDOR_ST_25USPT:
11607         case FLASH_5717VENDOR_ST_45USPT:
11608                 tp->nvram_jedecnum = JEDEC_ST;
11609                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11610                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11611
11612                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11613                 case FLASH_5717VENDOR_ST_M_M25PE20:
11614                 case FLASH_5717VENDOR_ST_A_M25PE20:
11615                 case FLASH_5717VENDOR_ST_M_M45PE20:
11616                 case FLASH_5717VENDOR_ST_A_M45PE20:
11617                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11618                         break;
11619                 default:
11620                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11621                         break;
11622                 }
11623                 break;
11624         default:
11625                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11626                 return;
11627         }
11628
11629         tg3_nvram_get_pagesize(tp, nvcfg1);
11630         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11631                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11632 }
11633
11634 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11635 static void __devinit tg3_nvram_init(struct tg3 *tp)
11636 {
11637         tw32_f(GRC_EEPROM_ADDR,
11638              (EEPROM_ADDR_FSM_RESET |
11639               (EEPROM_DEFAULT_CLOCK_PERIOD <<
11640                EEPROM_ADDR_CLKPERD_SHIFT)));
11641
11642         msleep(1);
11643
11644         /* Enable seeprom accesses. */
11645         tw32_f(GRC_LOCAL_CTRL,
11646              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11647         udelay(100);
11648
11649         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11650             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11651                 tp->tg3_flags |= TG3_FLAG_NVRAM;
11652
11653                 if (tg3_nvram_lock(tp)) {
11654                         netdev_warn(tp->dev,
11655                                     "Cannot get nvram lock, %s failed\n",
11656                                     __func__);
11657                         return;
11658                 }
11659                 tg3_enable_nvram_access(tp);
11660
11661                 tp->nvram_size = 0;
11662
11663                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11664                         tg3_get_5752_nvram_info(tp);
11665                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11666                         tg3_get_5755_nvram_info(tp);
11667                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11668                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11669                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11670                         tg3_get_5787_nvram_info(tp);
11671                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11672                         tg3_get_5761_nvram_info(tp);
11673                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11674                         tg3_get_5906_nvram_info(tp);
11675                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11676                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11677                         tg3_get_57780_nvram_info(tp);
11678                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
11679                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
11680                         tg3_get_5717_nvram_info(tp);
11681                 else
11682                         tg3_get_nvram_info(tp);
11683
11684                 if (tp->nvram_size == 0)
11685                         tg3_get_nvram_size(tp);
11686
11687                 tg3_disable_nvram_access(tp);
11688                 tg3_nvram_unlock(tp);
11689
11690         } else {
11691                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11692
11693                 tg3_get_eeprom_size(tp);
11694         }
11695 }
11696
11697 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11698                                     u32 offset, u32 len, u8 *buf)
11699 {
11700         int i, j, rc = 0;
11701         u32 val;
11702
11703         for (i = 0; i < len; i += 4) {
11704                 u32 addr;
11705                 __be32 data;
11706
11707                 addr = offset + i;
11708
11709                 memcpy(&data, buf + i, 4);
11710
11711                 /*
11712                  * The SEEPROM interface expects the data to always be opposite
11713                  * the native endian format.  We accomplish this by reversing
11714                  * all the operations that would have been performed on the
11715                  * data from a call to tg3_nvram_read_be32().
11716                  */
11717                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11718
11719                 val = tr32(GRC_EEPROM_ADDR);
11720                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11721
11722                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11723                         EEPROM_ADDR_READ);
11724                 tw32(GRC_EEPROM_ADDR, val |
11725                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
11726                         (addr & EEPROM_ADDR_ADDR_MASK) |
11727                         EEPROM_ADDR_START |
11728                         EEPROM_ADDR_WRITE);
11729
11730                 for (j = 0; j < 1000; j++) {
11731                         val = tr32(GRC_EEPROM_ADDR);
11732
11733                         if (val & EEPROM_ADDR_COMPLETE)
11734                                 break;
11735                         msleep(1);
11736                 }
11737                 if (!(val & EEPROM_ADDR_COMPLETE)) {
11738                         rc = -EBUSY;
11739                         break;
11740                 }
11741         }
11742
11743         return rc;
11744 }
11745
11746 /* offset and length are dword aligned */
11747 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11748                 u8 *buf)
11749 {
11750         int ret = 0;
11751         u32 pagesize = tp->nvram_pagesize;
11752         u32 pagemask = pagesize - 1;
11753         u32 nvram_cmd;
11754         u8 *tmp;
11755
11756         tmp = kmalloc(pagesize, GFP_KERNEL);
11757         if (tmp == NULL)
11758                 return -ENOMEM;
11759
11760         while (len) {
11761                 int j;
11762                 u32 phy_addr, page_off, size;
11763
11764                 phy_addr = offset & ~pagemask;
11765
11766                 for (j = 0; j < pagesize; j += 4) {
11767                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
11768                                                   (__be32 *) (tmp + j));
11769                         if (ret)
11770                                 break;
11771                 }
11772                 if (ret)
11773                         break;
11774
11775                 page_off = offset & pagemask;
11776                 size = pagesize;
11777                 if (len < size)
11778                         size = len;
11779
11780                 len -= size;
11781
11782                 memcpy(tmp + page_off, buf, size);
11783
11784                 offset = offset + (pagesize - page_off);
11785
11786                 tg3_enable_nvram_access(tp);
11787
11788                 /*
11789                  * Before we can erase the flash page, we need
11790                  * to issue a special "write enable" command.
11791                  */
11792                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11793
11794                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11795                         break;
11796
11797                 /* Erase the target page */
11798                 tw32(NVRAM_ADDR, phy_addr);
11799
11800                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11801                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11802
11803                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11804                         break;
11805
11806                 /* Issue another write enable to start the write. */
11807                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11808
11809                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11810                         break;
11811
11812                 for (j = 0; j < pagesize; j += 4) {
11813                         __be32 data;
11814
11815                         data = *((__be32 *) (tmp + j));
11816
11817                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
11818
11819                         tw32(NVRAM_ADDR, phy_addr + j);
11820
11821                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11822                                 NVRAM_CMD_WR;
11823
11824                         if (j == 0)
11825                                 nvram_cmd |= NVRAM_CMD_FIRST;
11826                         else if (j == (pagesize - 4))
11827                                 nvram_cmd |= NVRAM_CMD_LAST;
11828
11829                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11830                                 break;
11831                 }
11832                 if (ret)
11833                         break;
11834         }
11835
11836         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11837         tg3_nvram_exec_cmd(tp, nvram_cmd);
11838
11839         kfree(tmp);
11840
11841         return ret;
11842 }
11843
11844 /* offset and length are dword aligned */
11845 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11846                 u8 *buf)
11847 {
11848         int i, ret = 0;
11849
11850         for (i = 0; i < len; i += 4, offset += 4) {
11851                 u32 page_off, phy_addr, nvram_cmd;
11852                 __be32 data;
11853
11854                 memcpy(&data, buf + i, 4);
11855                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11856
11857                 page_off = offset % tp->nvram_pagesize;
11858
11859                 phy_addr = tg3_nvram_phys_addr(tp, offset);
11860
11861                 tw32(NVRAM_ADDR, phy_addr);
11862
11863                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11864
11865                 if (page_off == 0 || i == 0)
11866                         nvram_cmd |= NVRAM_CMD_FIRST;
11867                 if (page_off == (tp->nvram_pagesize - 4))
11868                         nvram_cmd |= NVRAM_CMD_LAST;
11869
11870                 if (i == (len - 4))
11871                         nvram_cmd |= NVRAM_CMD_LAST;
11872
11873                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11874                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11875                     (tp->nvram_jedecnum == JEDEC_ST) &&
11876                     (nvram_cmd & NVRAM_CMD_FIRST)) {
11877
11878                         if ((ret = tg3_nvram_exec_cmd(tp,
11879                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11880                                 NVRAM_CMD_DONE)))
11881
11882                                 break;
11883                 }
11884                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11885                         /* We always do complete word writes to eeprom. */
11886                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11887                 }
11888
11889                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11890                         break;
11891         }
11892         return ret;
11893 }
11894
11895 /* offset and length are dword aligned */
11896 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11897 {
11898         int ret;
11899
11900         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11901                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11902                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
11903                 udelay(40);
11904         }
11905
11906         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11907                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11908         } else {
11909                 u32 grc_mode;
11910
11911                 ret = tg3_nvram_lock(tp);
11912                 if (ret)
11913                         return ret;
11914
11915                 tg3_enable_nvram_access(tp);
11916                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11917                     !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
11918                         tw32(NVRAM_WRITE1, 0x406);
11919
11920                 grc_mode = tr32(GRC_MODE);
11921                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11922
11923                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11924                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11925
11926                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
11927                                 buf);
11928                 } else {
11929                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11930                                 buf);
11931                 }
11932
11933                 grc_mode = tr32(GRC_MODE);
11934                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11935
11936                 tg3_disable_nvram_access(tp);
11937                 tg3_nvram_unlock(tp);
11938         }
11939
11940         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11941                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11942                 udelay(40);
11943         }
11944
11945         return ret;
11946 }
11947
11948 struct subsys_tbl_ent {
11949         u16 subsys_vendor, subsys_devid;
11950         u32 phy_id;
11951 };
11952
11953 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
11954         /* Broadcom boards. */
11955         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11956           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
11957         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11958           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
11959         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11960           TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
11961         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11962           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
11963         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11964           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
11965         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11966           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
11967         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11968           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
11969         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11970           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
11971         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11972           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
11973         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11974           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
11975         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11976           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
11977
11978         /* 3com boards. */
11979         { TG3PCI_SUBVENDOR_ID_3COM,
11980           TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
11981         { TG3PCI_SUBVENDOR_ID_3COM,
11982           TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
11983         { TG3PCI_SUBVENDOR_ID_3COM,
11984           TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
11985         { TG3PCI_SUBVENDOR_ID_3COM,
11986           TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
11987         { TG3PCI_SUBVENDOR_ID_3COM,
11988           TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
11989
11990         /* DELL boards. */
11991         { TG3PCI_SUBVENDOR_ID_DELL,
11992           TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
11993         { TG3PCI_SUBVENDOR_ID_DELL,
11994           TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
11995         { TG3PCI_SUBVENDOR_ID_DELL,
11996           TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
11997         { TG3PCI_SUBVENDOR_ID_DELL,
11998           TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
11999
12000         /* Compaq boards. */
12001         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12002           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
12003         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12004           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
12005         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12006           TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
12007         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12008           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
12009         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12010           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
12011
12012         /* IBM boards. */
12013         { TG3PCI_SUBVENDOR_ID_IBM,
12014           TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
12015 };
12016
12017 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
12018 {
12019         int i;
12020
12021         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12022                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12023                      tp->pdev->subsystem_vendor) &&
12024                     (subsys_id_to_phy_id[i].subsys_devid ==
12025                      tp->pdev->subsystem_device))
12026                         return &subsys_id_to_phy_id[i];
12027         }
12028         return NULL;
12029 }
12030
12031 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12032 {
12033         u32 val;
12034         u16 pmcsr;
12035
12036         /* On some early chips the SRAM cannot be accessed in D3hot state,
12037          * so need make sure we're in D0.
12038          */
12039         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12040         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12041         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12042         msleep(1);
12043
12044         /* Make sure register accesses (indirect or otherwise)
12045          * will function correctly.
12046          */
12047         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12048                                tp->misc_host_ctrl);
12049
12050         /* The memory arbiter has to be enabled in order for SRAM accesses
12051          * to succeed.  Normally on powerup the tg3 chip firmware will make
12052          * sure it is enabled, but other entities such as system netboot
12053          * code might disable it.
12054          */
12055         val = tr32(MEMARB_MODE);
12056         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12057
12058         tp->phy_id = TG3_PHY_ID_INVALID;
12059         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12060
12061         /* Assume an onboard device and WOL capable by default.  */
12062         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12063
12064         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12065                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12066                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12067                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12068                 }
12069                 val = tr32(VCPU_CFGSHDW);
12070                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12071                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12072                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12073                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
12074                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12075                 goto done;
12076         }
12077
12078         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12079         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12080                 u32 nic_cfg, led_cfg;
12081                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12082                 int eeprom_phy_serdes = 0;
12083
12084                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12085                 tp->nic_sram_data_cfg = nic_cfg;
12086
12087                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12088                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12089                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12090                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12091                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12092                     (ver > 0) && (ver < 0x100))
12093                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12094
12095                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12096                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12097
12098                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12099                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12100                         eeprom_phy_serdes = 1;
12101
12102                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12103                 if (nic_phy_id != 0) {
12104                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12105                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12106
12107                         eeprom_phy_id  = (id1 >> 16) << 10;
12108                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
12109                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
12110                 } else
12111                         eeprom_phy_id = 0;
12112
12113                 tp->phy_id = eeprom_phy_id;
12114                 if (eeprom_phy_serdes) {
12115                         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12116                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12117                         else
12118                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
12119                 }
12120
12121                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12122                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12123                                     SHASTA_EXT_LED_MODE_MASK);
12124                 else
12125                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12126
12127                 switch (led_cfg) {
12128                 default:
12129                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12130                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12131                         break;
12132
12133                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12134                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12135                         break;
12136
12137                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12138                         tp->led_ctrl = LED_CTRL_MODE_MAC;
12139
12140                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12141                          * read on some older 5700/5701 bootcode.
12142                          */
12143                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12144                             ASIC_REV_5700 ||
12145                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
12146                             ASIC_REV_5701)
12147                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12148
12149                         break;
12150
12151                 case SHASTA_EXT_LED_SHARED:
12152                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
12153                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12154                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12155                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12156                                                  LED_CTRL_MODE_PHY_2);
12157                         break;
12158
12159                 case SHASTA_EXT_LED_MAC:
12160                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12161                         break;
12162
12163                 case SHASTA_EXT_LED_COMBO:
12164                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
12165                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12166                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12167                                                  LED_CTRL_MODE_PHY_2);
12168                         break;
12169
12170                 }
12171
12172                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12173                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12174                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12175                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12176
12177                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12178                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12179
12180                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12181                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12182                         if ((tp->pdev->subsystem_vendor ==
12183                              PCI_VENDOR_ID_ARIMA) &&
12184                             (tp->pdev->subsystem_device == 0x205a ||
12185                              tp->pdev->subsystem_device == 0x2063))
12186                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12187                 } else {
12188                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12189                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12190                 }
12191
12192                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12193                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12194                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12195                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12196                 }
12197
12198                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12199                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12200                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12201
12202                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
12203                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12204                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12205
12206                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12207                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12208                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12209
12210                 if (cfg2 & (1 << 17))
12211                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
12212
12213                 /* serdes signal pre-emphasis in register 0x590 set by */
12214                 /* bootcode if bit 18 is set */
12215                 if (cfg2 & (1 << 18))
12216                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
12217
12218                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12219                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
12220                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12221                         tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
12222
12223                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12224                         u32 cfg3;
12225
12226                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12227                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12228                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12229                 }
12230
12231                 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12232                         tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
12233                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12234                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12235                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12236                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12237         }
12238 done:
12239         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12240         device_set_wakeup_enable(&tp->pdev->dev,
12241                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12242 }
12243
12244 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12245 {
12246         int i;
12247         u32 val;
12248
12249         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12250         tw32(OTP_CTRL, cmd);
12251
12252         /* Wait for up to 1 ms for command to execute. */
12253         for (i = 0; i < 100; i++) {
12254                 val = tr32(OTP_STATUS);
12255                 if (val & OTP_STATUS_CMD_DONE)
12256                         break;
12257                 udelay(10);
12258         }
12259
12260         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12261 }
12262
12263 /* Read the gphy configuration from the OTP region of the chip.  The gphy
12264  * configuration is a 32-bit value that straddles the alignment boundary.
12265  * We do two 32-bit reads and then shift and merge the results.
12266  */
12267 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12268 {
12269         u32 bhalf_otp, thalf_otp;
12270
12271         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12272
12273         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12274                 return 0;
12275
12276         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12277
12278         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12279                 return 0;
12280
12281         thalf_otp = tr32(OTP_READ_DATA);
12282
12283         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12284
12285         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12286                 return 0;
12287
12288         bhalf_otp = tr32(OTP_READ_DATA);
12289
12290         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12291 }
12292
12293 static int __devinit tg3_phy_probe(struct tg3 *tp)
12294 {
12295         u32 hw_phy_id_1, hw_phy_id_2;
12296         u32 hw_phy_id, hw_phy_id_masked;
12297         int err;
12298
12299         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12300                 return tg3_phy_init(tp);
12301
12302         /* Reading the PHY ID register can conflict with ASF
12303          * firmware access to the PHY hardware.
12304          */
12305         err = 0;
12306         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12307             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12308                 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
12309         } else {
12310                 /* Now read the physical PHY_ID from the chip and verify
12311                  * that it is sane.  If it doesn't look good, we fall back
12312                  * to either the hard-coded table based PHY_ID and failing
12313                  * that the value found in the eeprom area.
12314                  */
12315                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12316                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12317
12318                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
12319                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12320                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
12321
12322                 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
12323         }
12324
12325         if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
12326                 tp->phy_id = hw_phy_id;
12327                 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
12328                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12329                 else
12330                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
12331         } else {
12332                 if (tp->phy_id != TG3_PHY_ID_INVALID) {
12333                         /* Do nothing, phy ID already set up in
12334                          * tg3_get_eeprom_hw_cfg().
12335                          */
12336                 } else {
12337                         struct subsys_tbl_ent *p;
12338
12339                         /* No eeprom signature?  Try the hardcoded
12340                          * subsys device table.
12341                          */
12342                         p = tg3_lookup_by_subsys(tp);
12343                         if (!p)
12344                                 return -ENODEV;
12345
12346                         tp->phy_id = p->phy_id;
12347                         if (!tp->phy_id ||
12348                             tp->phy_id == TG3_PHY_ID_BCM8002)
12349                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12350                 }
12351         }
12352
12353         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
12354             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12355             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12356                 u32 bmsr, adv_reg, tg3_ctrl, mask;
12357
12358                 tg3_readphy(tp, MII_BMSR, &bmsr);
12359                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12360                     (bmsr & BMSR_LSTATUS))
12361                         goto skip_phy_reset;
12362
12363                 err = tg3_phy_reset(tp);
12364                 if (err)
12365                         return err;
12366
12367                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12368                            ADVERTISE_100HALF | ADVERTISE_100FULL |
12369                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12370                 tg3_ctrl = 0;
12371                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12372                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12373                                     MII_TG3_CTRL_ADV_1000_FULL);
12374                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12375                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12376                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12377                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
12378                 }
12379
12380                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12381                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12382                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12383                 if (!tg3_copper_is_advertising_all(tp, mask)) {
12384                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12385
12386                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12387                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12388
12389                         tg3_writephy(tp, MII_BMCR,
12390                                      BMCR_ANENABLE | BMCR_ANRESTART);
12391                 }
12392                 tg3_phy_set_wirespeed(tp);
12393
12394                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12395                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12396                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12397         }
12398
12399 skip_phy_reset:
12400         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
12401                 err = tg3_init_5401phy_dsp(tp);
12402                 if (err)
12403                         return err;
12404
12405                 err = tg3_init_5401phy_dsp(tp);
12406         }
12407
12408         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
12409                 tp->link_config.advertising =
12410                         (ADVERTISED_1000baseT_Half |
12411                          ADVERTISED_1000baseT_Full |
12412                          ADVERTISED_Autoneg |
12413                          ADVERTISED_FIBRE);
12414         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12415                 tp->link_config.advertising &=
12416                         ~(ADVERTISED_1000baseT_Half |
12417                           ADVERTISED_1000baseT_Full);
12418
12419         return err;
12420 }
12421
12422 static void __devinit tg3_read_vpd(struct tg3 *tp)
12423 {
12424         u8 vpd_data[TG3_NVM_VPD_LEN];
12425         unsigned int block_end, rosize, len;
12426         int j, i = 0;
12427         u32 magic;
12428
12429         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12430             tg3_nvram_read(tp, 0x0, &magic))
12431                 goto out_not_found;
12432
12433         if (magic == TG3_EEPROM_MAGIC) {
12434                 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12435                         u32 tmp;
12436
12437                         /* The data is in little-endian format in NVRAM.
12438                          * Use the big-endian read routines to preserve
12439                          * the byte order as it exists in NVRAM.
12440                          */
12441                         if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12442                                 goto out_not_found;
12443
12444                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12445                 }
12446         } else {
12447                 ssize_t cnt;
12448                 unsigned int pos = 0;
12449
12450                 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12451                         cnt = pci_read_vpd(tp->pdev, pos,
12452                                            TG3_NVM_VPD_LEN - pos,
12453                                            &vpd_data[pos]);
12454                         if (cnt == -ETIMEDOUT || -EINTR)
12455                                 cnt = 0;
12456                         else if (cnt < 0)
12457                                 goto out_not_found;
12458                 }
12459                 if (pos != TG3_NVM_VPD_LEN)
12460                         goto out_not_found;
12461         }
12462
12463         i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
12464                              PCI_VPD_LRDT_RO_DATA);
12465         if (i < 0)
12466                 goto out_not_found;
12467
12468         rosize = pci_vpd_lrdt_size(&vpd_data[i]);
12469         block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
12470         i += PCI_VPD_LRDT_TAG_SIZE;
12471
12472         if (block_end > TG3_NVM_VPD_LEN)
12473                 goto out_not_found;
12474
12475         j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12476                                       PCI_VPD_RO_KEYWORD_MFR_ID);
12477         if (j > 0) {
12478                 len = pci_vpd_info_field_size(&vpd_data[j]);
12479
12480                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12481                 if (j + len > block_end || len != 4 ||
12482                     memcmp(&vpd_data[j], "1028", 4))
12483                         goto partno;
12484
12485                 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12486                                               PCI_VPD_RO_KEYWORD_VENDOR0);
12487                 if (j < 0)
12488                         goto partno;
12489
12490                 len = pci_vpd_info_field_size(&vpd_data[j]);
12491
12492                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12493                 if (j + len > block_end)
12494                         goto partno;
12495
12496                 memcpy(tp->fw_ver, &vpd_data[j], len);
12497                 strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
12498         }
12499
12500 partno:
12501         i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12502                                       PCI_VPD_RO_KEYWORD_PARTNO);
12503         if (i < 0)
12504                 goto out_not_found;
12505
12506         len = pci_vpd_info_field_size(&vpd_data[i]);
12507
12508         i += PCI_VPD_INFO_FLD_HDR_SIZE;
12509         if (len > TG3_BPN_SIZE ||
12510             (len + i) > TG3_NVM_VPD_LEN)
12511                 goto out_not_found;
12512
12513         memcpy(tp->board_part_number, &vpd_data[i], len);
12514
12515         return;
12516
12517 out_not_found:
12518         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12519                 strcpy(tp->board_part_number, "BCM95906");
12520         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12521                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12522                 strcpy(tp->board_part_number, "BCM57780");
12523         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12524                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12525                 strcpy(tp->board_part_number, "BCM57760");
12526         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12527                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12528                 strcpy(tp->board_part_number, "BCM57790");
12529         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12530                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12531                 strcpy(tp->board_part_number, "BCM57788");
12532         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12533                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
12534                 strcpy(tp->board_part_number, "BCM57761");
12535         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12536                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
12537                 strcpy(tp->board_part_number, "BCM57765");
12538         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12539                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
12540                 strcpy(tp->board_part_number, "BCM57781");
12541         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12542                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
12543                 strcpy(tp->board_part_number, "BCM57785");
12544         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12545                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
12546                 strcpy(tp->board_part_number, "BCM57791");
12547         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12548                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12549                 strcpy(tp->board_part_number, "BCM57795");
12550         else
12551                 strcpy(tp->board_part_number, "none");
12552 }
12553
12554 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12555 {
12556         u32 val;
12557
12558         if (tg3_nvram_read(tp, offset, &val) ||
12559             (val & 0xfc000000) != 0x0c000000 ||
12560             tg3_nvram_read(tp, offset + 4, &val) ||
12561             val != 0)
12562                 return 0;
12563
12564         return 1;
12565 }
12566
12567 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12568 {
12569         u32 val, offset, start, ver_offset;
12570         int i, dst_off;
12571         bool newver = false;
12572
12573         if (tg3_nvram_read(tp, 0xc, &offset) ||
12574             tg3_nvram_read(tp, 0x4, &start))
12575                 return;
12576
12577         offset = tg3_nvram_logical_addr(tp, offset);
12578
12579         if (tg3_nvram_read(tp, offset, &val))
12580                 return;
12581
12582         if ((val & 0xfc000000) == 0x0c000000) {
12583                 if (tg3_nvram_read(tp, offset + 4, &val))
12584                         return;
12585
12586                 if (val == 0)
12587                         newver = true;
12588         }
12589
12590         dst_off = strlen(tp->fw_ver);
12591
12592         if (newver) {
12593                 if (TG3_VER_SIZE - dst_off < 16 ||
12594                     tg3_nvram_read(tp, offset + 8, &ver_offset))
12595                         return;
12596
12597                 offset = offset + ver_offset - start;
12598                 for (i = 0; i < 16; i += 4) {
12599                         __be32 v;
12600                         if (tg3_nvram_read_be32(tp, offset + i, &v))
12601                                 return;
12602
12603                         memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
12604                 }
12605         } else {
12606                 u32 major, minor;
12607
12608                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12609                         return;
12610
12611                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12612                         TG3_NVM_BCVER_MAJSFT;
12613                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12614                 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
12615                          "v%d.%02d", major, minor);
12616         }
12617 }
12618
12619 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12620 {
12621         u32 val, major, minor;
12622
12623         /* Use native endian representation */
12624         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12625                 return;
12626
12627         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12628                 TG3_NVM_HWSB_CFG1_MAJSFT;
12629         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12630                 TG3_NVM_HWSB_CFG1_MINSFT;
12631
12632         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12633 }
12634
12635 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12636 {
12637         u32 offset, major, minor, build;
12638
12639         strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
12640
12641         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12642                 return;
12643
12644         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12645         case TG3_EEPROM_SB_REVISION_0:
12646                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12647                 break;
12648         case TG3_EEPROM_SB_REVISION_2:
12649                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12650                 break;
12651         case TG3_EEPROM_SB_REVISION_3:
12652                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12653                 break;
12654         case TG3_EEPROM_SB_REVISION_4:
12655                 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
12656                 break;
12657         case TG3_EEPROM_SB_REVISION_5:
12658                 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
12659                 break;
12660         default:
12661                 return;
12662         }
12663
12664         if (tg3_nvram_read(tp, offset, &val))
12665                 return;
12666
12667         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12668                 TG3_EEPROM_SB_EDH_BLD_SHFT;
12669         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12670                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12671         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
12672
12673         if (minor > 99 || build > 26)
12674                 return;
12675
12676         offset = strlen(tp->fw_ver);
12677         snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
12678                  " v%d.%02d", major, minor);
12679
12680         if (build > 0) {
12681                 offset = strlen(tp->fw_ver);
12682                 if (offset < TG3_VER_SIZE - 1)
12683                         tp->fw_ver[offset] = 'a' + build - 1;
12684         }
12685 }
12686
12687 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12688 {
12689         u32 val, offset, start;
12690         int i, vlen;
12691
12692         for (offset = TG3_NVM_DIR_START;
12693              offset < TG3_NVM_DIR_END;
12694              offset += TG3_NVM_DIRENT_SIZE) {
12695                 if (tg3_nvram_read(tp, offset, &val))
12696                         return;
12697
12698                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12699                         break;
12700         }
12701
12702         if (offset == TG3_NVM_DIR_END)
12703                 return;
12704
12705         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12706                 start = 0x08000000;
12707         else if (tg3_nvram_read(tp, offset - 4, &start))
12708                 return;
12709
12710         if (tg3_nvram_read(tp, offset + 4, &offset) ||
12711             !tg3_fw_img_is_valid(tp, offset) ||
12712             tg3_nvram_read(tp, offset + 8, &val))
12713                 return;
12714
12715         offset += val - start;
12716
12717         vlen = strlen(tp->fw_ver);
12718
12719         tp->fw_ver[vlen++] = ',';
12720         tp->fw_ver[vlen++] = ' ';
12721
12722         for (i = 0; i < 4; i++) {
12723                 __be32 v;
12724                 if (tg3_nvram_read_be32(tp, offset, &v))
12725                         return;
12726
12727                 offset += sizeof(v);
12728
12729                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12730                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12731                         break;
12732                 }
12733
12734                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12735                 vlen += sizeof(v);
12736         }
12737 }
12738
12739 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12740 {
12741         int vlen;
12742         u32 apedata;
12743
12744         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12745             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
12746                 return;
12747
12748         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12749         if (apedata != APE_SEG_SIG_MAGIC)
12750                 return;
12751
12752         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12753         if (!(apedata & APE_FW_STATUS_READY))
12754                 return;
12755
12756         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12757
12758         vlen = strlen(tp->fw_ver);
12759
12760         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12761                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12762                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12763                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12764                  (apedata & APE_FW_VERSION_BLDMSK));
12765 }
12766
12767 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12768 {
12769         u32 val;
12770         bool vpd_vers = false;
12771
12772         if (tp->fw_ver[0] != 0)
12773                 vpd_vers = true;
12774
12775         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12776                 strcat(tp->fw_ver, "sb");
12777                 return;
12778         }
12779
12780         if (tg3_nvram_read(tp, 0, &val))
12781                 return;
12782
12783         if (val == TG3_EEPROM_MAGIC)
12784                 tg3_read_bc_ver(tp);
12785         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12786                 tg3_read_sb_ver(tp, val);
12787         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12788                 tg3_read_hwsb_ver(tp);
12789         else
12790                 return;
12791
12792         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12793              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
12794                 goto done;
12795
12796         tg3_read_mgmtfw_ver(tp);
12797
12798 done:
12799         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12800 }
12801
12802 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12803
12804 static void inline vlan_features_add(struct net_device *dev, unsigned long flags)
12805 {
12806 #if TG3_VLAN_TAG_USED
12807         dev->vlan_features |= flags;
12808 #endif
12809 }
12810
12811 static int __devinit tg3_get_invariants(struct tg3 *tp)
12812 {
12813         static struct pci_device_id write_reorder_chipsets[] = {
12814                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12815                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12816                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12817                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12818                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12819                              PCI_DEVICE_ID_VIA_8385_0) },
12820                 { },
12821         };
12822         u32 misc_ctrl_reg;
12823         u32 pci_state_reg, grc_misc_cfg;
12824         u32 val;
12825         u16 pci_cmd;
12826         int err;
12827
12828         /* Force memory write invalidate off.  If we leave it on,
12829          * then on 5700_BX chips we have to enable a workaround.
12830          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12831          * to match the cacheline size.  The Broadcom driver have this
12832          * workaround but turns MWI off all the times so never uses
12833          * it.  This seems to suggest that the workaround is insufficient.
12834          */
12835         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12836         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12837         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12838
12839         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12840          * has the register indirect write enable bit set before
12841          * we try to access any of the MMIO registers.  It is also
12842          * critical that the PCI-X hw workaround situation is decided
12843          * before that as well.
12844          */
12845         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12846                               &misc_ctrl_reg);
12847
12848         tp->pci_chip_rev_id = (misc_ctrl_reg >>
12849                                MISC_HOST_CTRL_CHIPREV_SHIFT);
12850         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12851                 u32 prod_id_asic_rev;
12852
12853                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12854                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12855                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724 ||
12856                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719)
12857                         pci_read_config_dword(tp->pdev,
12858                                               TG3PCI_GEN2_PRODID_ASICREV,
12859                                               &prod_id_asic_rev);
12860                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
12861                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
12862                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
12863                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
12864                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
12865                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12866                         pci_read_config_dword(tp->pdev,
12867                                               TG3PCI_GEN15_PRODID_ASICREV,
12868                                               &prod_id_asic_rev);
12869                 else
12870                         pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12871                                               &prod_id_asic_rev);
12872
12873                 tp->pci_chip_rev_id = prod_id_asic_rev;
12874         }
12875
12876         /* Wrong chip ID in 5752 A0. This code can be removed later
12877          * as A0 is not in production.
12878          */
12879         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12880                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12881
12882         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12883          * we need to disable memory and use config. cycles
12884          * only to access all registers. The 5702/03 chips
12885          * can mistakenly decode the special cycles from the
12886          * ICH chipsets as memory write cycles, causing corruption
12887          * of register and memory space. Only certain ICH bridges
12888          * will drive special cycles with non-zero data during the
12889          * address phase which can fall within the 5703's address
12890          * range. This is not an ICH bug as the PCI spec allows
12891          * non-zero address during special cycles. However, only
12892          * these ICH bridges are known to drive non-zero addresses
12893          * during special cycles.
12894          *
12895          * Since special cycles do not cross PCI bridges, we only
12896          * enable this workaround if the 5703 is on the secondary
12897          * bus of these ICH bridges.
12898          */
12899         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12900             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12901                 static struct tg3_dev_id {
12902                         u32     vendor;
12903                         u32     device;
12904                         u32     rev;
12905                 } ich_chipsets[] = {
12906                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12907                           PCI_ANY_ID },
12908                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12909                           PCI_ANY_ID },
12910                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12911                           0xa },
12912                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12913                           PCI_ANY_ID },
12914                         { },
12915                 };
12916                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12917                 struct pci_dev *bridge = NULL;
12918
12919                 while (pci_id->vendor != 0) {
12920                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
12921                                                 bridge);
12922                         if (!bridge) {
12923                                 pci_id++;
12924                                 continue;
12925                         }
12926                         if (pci_id->rev != PCI_ANY_ID) {
12927                                 if (bridge->revision > pci_id->rev)
12928                                         continue;
12929                         }
12930                         if (bridge->subordinate &&
12931                             (bridge->subordinate->number ==
12932                              tp->pdev->bus->number)) {
12933
12934                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12935                                 pci_dev_put(bridge);
12936                                 break;
12937                         }
12938                 }
12939         }
12940
12941         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12942                 static struct tg3_dev_id {
12943                         u32     vendor;
12944                         u32     device;
12945                 } bridge_chipsets[] = {
12946                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12947                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12948                         { },
12949                 };
12950                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12951                 struct pci_dev *bridge = NULL;
12952
12953                 while (pci_id->vendor != 0) {
12954                         bridge = pci_get_device(pci_id->vendor,
12955                                                 pci_id->device,
12956                                                 bridge);
12957                         if (!bridge) {
12958                                 pci_id++;
12959                                 continue;
12960                         }
12961                         if (bridge->subordinate &&
12962                             (bridge->subordinate->number <=
12963                              tp->pdev->bus->number) &&
12964                             (bridge->subordinate->subordinate >=
12965                              tp->pdev->bus->number)) {
12966                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12967                                 pci_dev_put(bridge);
12968                                 break;
12969                         }
12970                 }
12971         }
12972
12973         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12974          * DMA addresses > 40-bit. This bridge may have other additional
12975          * 57xx devices behind it in some 4-port NIC designs for example.
12976          * Any tg3 device found behind the bridge will also need the 40-bit
12977          * DMA workaround.
12978          */
12979         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12980             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12981                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
12982                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12983                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
12984         } else {
12985                 struct pci_dev *bridge = NULL;
12986
12987                 do {
12988                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12989                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
12990                                                 bridge);
12991                         if (bridge && bridge->subordinate &&
12992                             (bridge->subordinate->number <=
12993                              tp->pdev->bus->number) &&
12994                             (bridge->subordinate->subordinate >=
12995                              tp->pdev->bus->number)) {
12996                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12997                                 pci_dev_put(bridge);
12998                                 break;
12999                         }
13000                 } while (bridge);
13001         }
13002
13003         /* Initialize misc host control in PCI block. */
13004         tp->misc_host_ctrl |= (misc_ctrl_reg &
13005                                MISC_HOST_CTRL_CHIPREV);
13006         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13007                                tp->misc_host_ctrl);
13008
13009         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13010             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13011             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13012                 tp->pdev_peer = tg3_find_peer(tp);
13013
13014         /* Intentionally exclude ASIC_REV_5906 */
13015         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13016             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13017             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13018             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13019             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13020             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13021             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13022             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13023             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13024                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13025
13026         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13027             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13028             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13029             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13030             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13031                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13032
13033         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13034             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13035                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13036
13037         /* 5700 B0 chips do not support checksumming correctly due
13038          * to hardware bugs.
13039          */
13040         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13041                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13042         else {
13043                 unsigned long features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_GRO;
13044
13045                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13046                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13047                         features |= NETIF_F_IPV6_CSUM;
13048                 tp->dev->features |= features;
13049                 vlan_features_add(tp->dev, features);
13050         }
13051
13052         /* Determine TSO capabilities */
13053         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13054             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13055             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13056                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13057         else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13058                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13059                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13060         else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13061                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13062                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13063                     tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13064                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13065         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13066                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13067                    tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13068                 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13069                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13070                         tp->fw_needed = FIRMWARE_TG3TSO5;
13071                 else
13072                         tp->fw_needed = FIRMWARE_TG3TSO;
13073         }
13074
13075         tp->irq_max = 1;
13076
13077         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13078                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13079                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13080                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13081                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13082                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13083                      tp->pdev_peer == tp->pdev))
13084                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13085
13086                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13087                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13088                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13089                 }
13090
13091                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13092                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13093                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13094                         tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13095                         tp->irq_max = TG3_IRQ_MAX_VECS;
13096                 }
13097         }
13098
13099         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13100             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13101             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13102                 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13103         else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13104                 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13105                 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13106         }
13107
13108         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13109             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13110             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13111                 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13112
13113         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13114             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13115             (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13116                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13117
13118         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13119                               &pci_state_reg);
13120
13121         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13122         if (tp->pcie_cap != 0) {
13123                 u16 lnkctl;
13124
13125                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13126
13127                 pcie_set_readrq(tp->pdev, 4096);
13128
13129                 pci_read_config_word(tp->pdev,
13130                                      tp->pcie_cap + PCI_EXP_LNKCTL,
13131                                      &lnkctl);
13132                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13133                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13134                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13135                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13136                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13137                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13138                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13139                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13140                 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13141                         tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13142                 }
13143         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13144                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13145         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13146                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13147                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13148                 if (!tp->pcix_cap) {
13149                         dev_err(&tp->pdev->dev,
13150                                 "Cannot find PCI-X capability, aborting\n");
13151                         return -EIO;
13152                 }
13153
13154                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13155                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13156         }
13157
13158         /* If we have an AMD 762 or VIA K8T800 chipset, write
13159          * reordering to the mailbox registers done by the host
13160          * controller can cause major troubles.  We read back from
13161          * every mailbox register write to force the writes to be
13162          * posted to the chip in order.
13163          */
13164         if (pci_dev_present(write_reorder_chipsets) &&
13165             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13166                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13167
13168         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13169                              &tp->pci_cacheline_sz);
13170         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13171                              &tp->pci_lat_timer);
13172         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13173             tp->pci_lat_timer < 64) {
13174                 tp->pci_lat_timer = 64;
13175                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13176                                       tp->pci_lat_timer);
13177         }
13178
13179         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13180                 /* 5700 BX chips need to have their TX producer index
13181                  * mailboxes written twice to workaround a bug.
13182                  */
13183                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13184
13185                 /* If we are in PCI-X mode, enable register write workaround.
13186                  *
13187                  * The workaround is to use indirect register accesses
13188                  * for all chip writes not to mailbox registers.
13189                  */
13190                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13191                         u32 pm_reg;
13192
13193                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13194
13195                         /* The chip can have it's power management PCI config
13196                          * space registers clobbered due to this bug.
13197                          * So explicitly force the chip into D0 here.
13198                          */
13199                         pci_read_config_dword(tp->pdev,
13200                                               tp->pm_cap + PCI_PM_CTRL,
13201                                               &pm_reg);
13202                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13203                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13204                         pci_write_config_dword(tp->pdev,
13205                                                tp->pm_cap + PCI_PM_CTRL,
13206                                                pm_reg);
13207
13208                         /* Also, force SERR#/PERR# in PCI command. */
13209                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13210                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13211                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13212                 }
13213         }
13214
13215         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13216                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13217         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13218                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13219
13220         /* Chip-specific fixup from Broadcom driver */
13221         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13222             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13223                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13224                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13225         }
13226
13227         /* Default fast path register access methods */
13228         tp->read32 = tg3_read32;
13229         tp->write32 = tg3_write32;
13230         tp->read32_mbox = tg3_read32;
13231         tp->write32_mbox = tg3_write32;
13232         tp->write32_tx_mbox = tg3_write32;
13233         tp->write32_rx_mbox = tg3_write32;
13234
13235         /* Various workaround register access methods */
13236         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13237                 tp->write32 = tg3_write_indirect_reg32;
13238         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13239                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13240                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13241                 /*
13242                  * Back to back register writes can cause problems on these
13243                  * chips, the workaround is to read back all reg writes
13244                  * except those to mailbox regs.
13245                  *
13246                  * See tg3_write_indirect_reg32().
13247                  */
13248                 tp->write32 = tg3_write_flush_reg32;
13249         }
13250
13251         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13252             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13253                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13254                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13255                         tp->write32_rx_mbox = tg3_write_flush_reg32;
13256         }
13257
13258         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13259                 tp->read32 = tg3_read_indirect_reg32;
13260                 tp->write32 = tg3_write_indirect_reg32;
13261                 tp->read32_mbox = tg3_read_indirect_mbox;
13262                 tp->write32_mbox = tg3_write_indirect_mbox;
13263                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13264                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13265
13266                 iounmap(tp->regs);
13267                 tp->regs = NULL;
13268
13269                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13270                 pci_cmd &= ~PCI_COMMAND_MEMORY;
13271                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13272         }
13273         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13274                 tp->read32_mbox = tg3_read32_mbox_5906;
13275                 tp->write32_mbox = tg3_write32_mbox_5906;
13276                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13277                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13278         }
13279
13280         if (tp->write32 == tg3_write_indirect_reg32 ||
13281             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13282              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13283               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13284                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13285
13286         /* Get eeprom hw config before calling tg3_set_power_state().
13287          * In particular, the TG3_FLG2_IS_NIC flag must be
13288          * determined before calling tg3_set_power_state() so that
13289          * we know whether or not to switch out of Vaux power.
13290          * When the flag is set, it means that GPIO1 is used for eeprom
13291          * write protect and also implies that it is a LOM where GPIOs
13292          * are not used to switch power.
13293          */
13294         tg3_get_eeprom_hw_cfg(tp);
13295
13296         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13297                 /* Allow reads and writes to the
13298                  * APE register and memory space.
13299                  */
13300                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13301                                  PCISTATE_ALLOW_APE_SHMEM_WR |
13302                                  PCISTATE_ALLOW_APE_PSPACE_WR;
13303                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13304                                        pci_state_reg);
13305         }
13306
13307         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13308             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13309             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13310             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13311             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13312             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13313             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13314                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13315
13316         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13317          * GPIO1 driven high will bring 5700's external PHY out of reset.
13318          * It is also used as eeprom write protect on LOMs.
13319          */
13320         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13321         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13322             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13323                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13324                                        GRC_LCLCTRL_GPIO_OUTPUT1);
13325         /* Unused GPIO3 must be driven as output on 5752 because there
13326          * are no pull-up resistors on unused GPIO pins.
13327          */
13328         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13329                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13330
13331         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13332             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13333             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13334                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13335
13336         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13337             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13338                 /* Turn off the debug UART. */
13339                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13340                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13341                         /* Keep VMain power. */
13342                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13343                                               GRC_LCLCTRL_GPIO_OUTPUT0;
13344         }
13345
13346         /* Force the chip into D0. */
13347         err = tg3_set_power_state(tp, PCI_D0);
13348         if (err) {
13349                 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
13350                 return err;
13351         }
13352
13353         /* Derive initial jumbo mode from MTU assigned in
13354          * ether_setup() via the alloc_etherdev() call
13355          */
13356         if (tp->dev->mtu > ETH_DATA_LEN &&
13357             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13358                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13359
13360         /* Determine WakeOnLan speed to use. */
13361         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13362             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13363             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13364             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13365                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13366         } else {
13367                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13368         }
13369
13370         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13371                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
13372
13373         /* A few boards don't want Ethernet@WireSpeed phy feature */
13374         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13375             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13376              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13377              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13378             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
13379             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
13380                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
13381
13382         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13383             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13384                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
13385         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13386                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
13387
13388         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13389             !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
13390             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13391             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13392             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
13393             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719 &&
13394             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
13395                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13396                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13397                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13398                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13399                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13400                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13401                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
13402                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13403                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
13404                 } else
13405                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
13406         }
13407
13408         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13409             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13410                 tp->phy_otp = tg3_read_otp_phycfg(tp);
13411                 if (tp->phy_otp == 0)
13412                         tp->phy_otp = TG3_OTP_DEFAULT;
13413         }
13414
13415         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13416                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13417         else
13418                 tp->mi_mode = MAC_MI_MODE_BASE;
13419
13420         tp->coalesce_mode = 0;
13421         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13422             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13423                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13424
13425         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13426             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13427                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13428
13429         err = tg3_mdio_init(tp);
13430         if (err)
13431                 return err;
13432
13433         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
13434             tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
13435                 return -ENOTSUPP;
13436
13437         /* Initialize data/descriptor byte/word swapping. */
13438         val = tr32(GRC_MODE);
13439         val &= GRC_MODE_HOST_STACKUP;
13440         tw32(GRC_MODE, val | tp->grc_mode);
13441
13442         tg3_switch_clocks(tp);
13443
13444         /* Clear this out for sanity. */
13445         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13446
13447         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13448                               &pci_state_reg);
13449         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13450             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13451                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13452
13453                 if (chiprevid == CHIPREV_ID_5701_A0 ||
13454                     chiprevid == CHIPREV_ID_5701_B0 ||
13455                     chiprevid == CHIPREV_ID_5701_B2 ||
13456                     chiprevid == CHIPREV_ID_5701_B5) {
13457                         void __iomem *sram_base;
13458
13459                         /* Write some dummy words into the SRAM status block
13460                          * area, see if it reads back correctly.  If the return
13461                          * value is bad, force enable the PCIX workaround.
13462                          */
13463                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13464
13465                         writel(0x00000000, sram_base);
13466                         writel(0x00000000, sram_base + 4);
13467                         writel(0xffffffff, sram_base + 4);
13468                         if (readl(sram_base) != 0x00000000)
13469                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13470                 }
13471         }
13472
13473         udelay(50);
13474         tg3_nvram_init(tp);
13475
13476         grc_misc_cfg = tr32(GRC_MISC_CFG);
13477         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13478
13479         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13480             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13481              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13482                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13483
13484         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13485             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13486                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13487         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13488                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13489                                       HOSTCC_MODE_CLRTICK_TXBD);
13490
13491                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13492                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13493                                        tp->misc_host_ctrl);
13494         }
13495
13496         /* Preserve the APE MAC_MODE bits */
13497         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13498                 tp->mac_mode = tr32(MAC_MODE) |
13499                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13500         else
13501                 tp->mac_mode = TG3_DEF_MAC_MODE;
13502
13503         /* these are limited to 10/100 only */
13504         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13505              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13506             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13507              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13508              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13509               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13510               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13511             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13512              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13513               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13514               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13515             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13516             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13517             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
13518             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
13519                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13520
13521         err = tg3_phy_probe(tp);
13522         if (err) {
13523                 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
13524                 /* ... but do not return immediately ... */
13525                 tg3_mdio_fini(tp);
13526         }
13527
13528         tg3_read_vpd(tp);
13529         tg3_read_fw_ver(tp);
13530
13531         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13532                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13533         } else {
13534                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13535                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13536                 else
13537                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13538         }
13539
13540         /* 5700 {AX,BX} chips have a broken status block link
13541          * change bit implementation, so we must use the
13542          * status register in those cases.
13543          */
13544         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13545                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13546         else
13547                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13548
13549         /* The led_ctrl is set during tg3_phy_probe, here we might
13550          * have to force the link status polling mechanism based
13551          * upon subsystem IDs.
13552          */
13553         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13554             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13555             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13556                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13557                                   TG3_FLAG_USE_LINKCHG_REG);
13558         }
13559
13560         /* For all SERDES we poll the MAC status register. */
13561         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13562                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13563         else
13564                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13565
13566         tp->rx_offset = NET_IP_ALIGN + TG3_RX_HEADROOM;
13567         tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
13568         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13569             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
13570                 tp->rx_offset -= NET_IP_ALIGN;
13571 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
13572                 tp->rx_copy_thresh = ~(u16)0;
13573 #endif
13574         }
13575
13576         tp->rx_std_max_post = TG3_RX_RING_SIZE;
13577
13578         /* Increment the rx prod index on the rx std ring by at most
13579          * 8 for these chips to workaround hw errata.
13580          */
13581         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13582             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13583             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13584                 tp->rx_std_max_post = 8;
13585
13586         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13587                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13588                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
13589
13590         return err;
13591 }
13592
13593 #ifdef CONFIG_SPARC
13594 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13595 {
13596         struct net_device *dev = tp->dev;
13597         struct pci_dev *pdev = tp->pdev;
13598         struct device_node *dp = pci_device_to_OF_node(pdev);
13599         const unsigned char *addr;
13600         int len;
13601
13602         addr = of_get_property(dp, "local-mac-address", &len);
13603         if (addr && len == 6) {
13604                 memcpy(dev->dev_addr, addr, 6);
13605                 memcpy(dev->perm_addr, dev->dev_addr, 6);
13606                 return 0;
13607         }
13608         return -ENODEV;
13609 }
13610
13611 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13612 {
13613         struct net_device *dev = tp->dev;
13614
13615         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13616         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13617         return 0;
13618 }
13619 #endif
13620
13621 static int __devinit tg3_get_device_address(struct tg3 *tp)
13622 {
13623         struct net_device *dev = tp->dev;
13624         u32 hi, lo, mac_offset;
13625         int addr_ok = 0;
13626
13627 #ifdef CONFIG_SPARC
13628         if (!tg3_get_macaddr_sparc(tp))
13629                 return 0;
13630 #endif
13631
13632         mac_offset = 0x7c;
13633         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13634             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13635                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13636                         mac_offset = 0xcc;
13637                 if (tg3_nvram_lock(tp))
13638                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13639                 else
13640                         tg3_nvram_unlock(tp);
13641         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13642                    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
13643                 if (PCI_FUNC(tp->pdev->devfn) & 1)
13644                         mac_offset = 0xcc;
13645                 if (PCI_FUNC(tp->pdev->devfn) > 1)
13646                         mac_offset += 0x18c;
13647         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13648                 mac_offset = 0x10;
13649
13650         /* First try to get it from MAC address mailbox. */
13651         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13652         if ((hi >> 16) == 0x484b) {
13653                 dev->dev_addr[0] = (hi >>  8) & 0xff;
13654                 dev->dev_addr[1] = (hi >>  0) & 0xff;
13655
13656                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13657                 dev->dev_addr[2] = (lo >> 24) & 0xff;
13658                 dev->dev_addr[3] = (lo >> 16) & 0xff;
13659                 dev->dev_addr[4] = (lo >>  8) & 0xff;
13660                 dev->dev_addr[5] = (lo >>  0) & 0xff;
13661
13662                 /* Some old bootcode may report a 0 MAC address in SRAM */
13663                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13664         }
13665         if (!addr_ok) {
13666                 /* Next, try NVRAM. */
13667                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13668                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13669                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13670                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13671                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13672                 }
13673                 /* Finally just fetch it out of the MAC control regs. */
13674                 else {
13675                         hi = tr32(MAC_ADDR_0_HIGH);
13676                         lo = tr32(MAC_ADDR_0_LOW);
13677
13678                         dev->dev_addr[5] = lo & 0xff;
13679                         dev->dev_addr[4] = (lo >> 8) & 0xff;
13680                         dev->dev_addr[3] = (lo >> 16) & 0xff;
13681                         dev->dev_addr[2] = (lo >> 24) & 0xff;
13682                         dev->dev_addr[1] = hi & 0xff;
13683                         dev->dev_addr[0] = (hi >> 8) & 0xff;
13684                 }
13685         }
13686
13687         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13688 #ifdef CONFIG_SPARC
13689                 if (!tg3_get_default_macaddr_sparc(tp))
13690                         return 0;
13691 #endif
13692                 return -EINVAL;
13693         }
13694         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13695         return 0;
13696 }
13697
13698 #define BOUNDARY_SINGLE_CACHELINE       1
13699 #define BOUNDARY_MULTI_CACHELINE        2
13700
13701 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13702 {
13703         int cacheline_size;
13704         u8 byte;
13705         int goal;
13706
13707         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13708         if (byte == 0)
13709                 cacheline_size = 1024;
13710         else
13711                 cacheline_size = (int) byte * 4;
13712
13713         /* On 5703 and later chips, the boundary bits have no
13714          * effect.
13715          */
13716         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13717             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13718             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13719                 goto out;
13720
13721 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13722         goal = BOUNDARY_MULTI_CACHELINE;
13723 #else
13724 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13725         goal = BOUNDARY_SINGLE_CACHELINE;
13726 #else
13727         goal = 0;
13728 #endif
13729 #endif
13730
13731         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13732             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13733             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13734                 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13735                 goto out;
13736         }
13737
13738         if (!goal)
13739                 goto out;
13740
13741         /* PCI controllers on most RISC systems tend to disconnect
13742          * when a device tries to burst across a cache-line boundary.
13743          * Therefore, letting tg3 do so just wastes PCI bandwidth.
13744          *
13745          * Unfortunately, for PCI-E there are only limited
13746          * write-side controls for this, and thus for reads
13747          * we will still get the disconnects.  We'll also waste
13748          * these PCI cycles for both read and write for chips
13749          * other than 5700 and 5701 which do not implement the
13750          * boundary bits.
13751          */
13752         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13753             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13754                 switch (cacheline_size) {
13755                 case 16:
13756                 case 32:
13757                 case 64:
13758                 case 128:
13759                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13760                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13761                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13762                         } else {
13763                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13764                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13765                         }
13766                         break;
13767
13768                 case 256:
13769                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13770                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13771                         break;
13772
13773                 default:
13774                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13775                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13776                         break;
13777                 }
13778         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13779                 switch (cacheline_size) {
13780                 case 16:
13781                 case 32:
13782                 case 64:
13783                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13784                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13785                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13786                                 break;
13787                         }
13788                         /* fallthrough */
13789                 case 128:
13790                 default:
13791                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13792                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13793                         break;
13794                 }
13795         } else {
13796                 switch (cacheline_size) {
13797                 case 16:
13798                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13799                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13800                                         DMA_RWCTRL_WRITE_BNDRY_16);
13801                                 break;
13802                         }
13803                         /* fallthrough */
13804                 case 32:
13805                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13806                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13807                                         DMA_RWCTRL_WRITE_BNDRY_32);
13808                                 break;
13809                         }
13810                         /* fallthrough */
13811                 case 64:
13812                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13813                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13814                                         DMA_RWCTRL_WRITE_BNDRY_64);
13815                                 break;
13816                         }
13817                         /* fallthrough */
13818                 case 128:
13819                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13820                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13821                                         DMA_RWCTRL_WRITE_BNDRY_128);
13822                                 break;
13823                         }
13824                         /* fallthrough */
13825                 case 256:
13826                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
13827                                 DMA_RWCTRL_WRITE_BNDRY_256);
13828                         break;
13829                 case 512:
13830                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
13831                                 DMA_RWCTRL_WRITE_BNDRY_512);
13832                         break;
13833                 case 1024:
13834                 default:
13835                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13836                                 DMA_RWCTRL_WRITE_BNDRY_1024);
13837                         break;
13838                 }
13839         }
13840
13841 out:
13842         return val;
13843 }
13844
13845 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13846 {
13847         struct tg3_internal_buffer_desc test_desc;
13848         u32 sram_dma_descs;
13849         int i, ret;
13850
13851         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13852
13853         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13854         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13855         tw32(RDMAC_STATUS, 0);
13856         tw32(WDMAC_STATUS, 0);
13857
13858         tw32(BUFMGR_MODE, 0);
13859         tw32(FTQ_RESET, 0);
13860
13861         test_desc.addr_hi = ((u64) buf_dma) >> 32;
13862         test_desc.addr_lo = buf_dma & 0xffffffff;
13863         test_desc.nic_mbuf = 0x00002100;
13864         test_desc.len = size;
13865
13866         /*
13867          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13868          * the *second* time the tg3 driver was getting loaded after an
13869          * initial scan.
13870          *
13871          * Broadcom tells me:
13872          *   ...the DMA engine is connected to the GRC block and a DMA
13873          *   reset may affect the GRC block in some unpredictable way...
13874          *   The behavior of resets to individual blocks has not been tested.
13875          *
13876          * Broadcom noted the GRC reset will also reset all sub-components.
13877          */
13878         if (to_device) {
13879                 test_desc.cqid_sqid = (13 << 8) | 2;
13880
13881                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13882                 udelay(40);
13883         } else {
13884                 test_desc.cqid_sqid = (16 << 8) | 7;
13885
13886                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13887                 udelay(40);
13888         }
13889         test_desc.flags = 0x00000005;
13890
13891         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13892                 u32 val;
13893
13894                 val = *(((u32 *)&test_desc) + i);
13895                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13896                                        sram_dma_descs + (i * sizeof(u32)));
13897                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13898         }
13899         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13900
13901         if (to_device)
13902                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13903         else
13904                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13905
13906         ret = -ENODEV;
13907         for (i = 0; i < 40; i++) {
13908                 u32 val;
13909
13910                 if (to_device)
13911                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13912                 else
13913                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13914                 if ((val & 0xffff) == sram_dma_descs) {
13915                         ret = 0;
13916                         break;
13917                 }
13918
13919                 udelay(100);
13920         }
13921
13922         return ret;
13923 }
13924
13925 #define TEST_BUFFER_SIZE        0x2000
13926
13927 static int __devinit tg3_test_dma(struct tg3 *tp)
13928 {
13929         dma_addr_t buf_dma;
13930         u32 *buf, saved_dma_rwctrl;
13931         int ret = 0;
13932
13933         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13934         if (!buf) {
13935                 ret = -ENOMEM;
13936                 goto out_nofree;
13937         }
13938
13939         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13940                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13941
13942         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13943
13944         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13945             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13946             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13947                 goto out;
13948
13949         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13950                 /* DMA read watermark not used on PCIE */
13951                 tp->dma_rwctrl |= 0x00180000;
13952         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
13953                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13954                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
13955                         tp->dma_rwctrl |= 0x003f0000;
13956                 else
13957                         tp->dma_rwctrl |= 0x003f000f;
13958         } else {
13959                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13960                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13961                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
13962                         u32 read_water = 0x7;
13963
13964                         /* If the 5704 is behind the EPB bridge, we can
13965                          * do the less restrictive ONE_DMA workaround for
13966                          * better performance.
13967                          */
13968                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13969                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13970                                 tp->dma_rwctrl |= 0x8000;
13971                         else if (ccval == 0x6 || ccval == 0x7)
13972                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13973
13974                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13975                                 read_water = 4;
13976                         /* Set bit 23 to enable PCIX hw bug fix */
13977                         tp->dma_rwctrl |=
13978                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13979                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13980                                 (1 << 23);
13981                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13982                         /* 5780 always in PCIX mode */
13983                         tp->dma_rwctrl |= 0x00144000;
13984                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13985                         /* 5714 always in PCIX mode */
13986                         tp->dma_rwctrl |= 0x00148000;
13987                 } else {
13988                         tp->dma_rwctrl |= 0x001b000f;
13989                 }
13990         }
13991
13992         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13993             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13994                 tp->dma_rwctrl &= 0xfffffff0;
13995
13996         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13997             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13998                 /* Remove this if it causes problems for some boards. */
13999                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
14000
14001                 /* On 5700/5701 chips, we need to set this bit.
14002                  * Otherwise the chip will issue cacheline transactions
14003                  * to streamable DMA memory with not all the byte
14004                  * enables turned on.  This is an error on several
14005                  * RISC PCI controllers, in particular sparc64.
14006                  *
14007                  * On 5703/5704 chips, this bit has been reassigned
14008                  * a different meaning.  In particular, it is used
14009                  * on those chips to enable a PCI-X workaround.
14010                  */
14011                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
14012         }
14013
14014         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14015
14016 #if 0
14017         /* Unneeded, already done by tg3_get_invariants.  */
14018         tg3_switch_clocks(tp);
14019 #endif
14020
14021         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14022             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14023                 goto out;
14024
14025         /* It is best to perform DMA test with maximum write burst size
14026          * to expose the 5700/5701 write DMA bug.
14027          */
14028         saved_dma_rwctrl = tp->dma_rwctrl;
14029         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14030         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14031
14032         while (1) {
14033                 u32 *p = buf, i;
14034
14035                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14036                         p[i] = i;
14037
14038                 /* Send the buffer to the chip. */
14039                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14040                 if (ret) {
14041                         dev_err(&tp->pdev->dev,
14042                                 "%s: Buffer write failed. err = %d\n",
14043                                 __func__, ret);
14044                         break;
14045                 }
14046
14047 #if 0
14048                 /* validate data reached card RAM correctly. */
14049                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14050                         u32 val;
14051                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
14052                         if (le32_to_cpu(val) != p[i]) {
14053                                 dev_err(&tp->pdev->dev,
14054                                         "%s: Buffer corrupted on device! "
14055                                         "(%d != %d)\n", __func__, val, i);
14056                                 /* ret = -ENODEV here? */
14057                         }
14058                         p[i] = 0;
14059                 }
14060 #endif
14061                 /* Now read it back. */
14062                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14063                 if (ret) {
14064                         dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
14065                                 "err = %d\n", __func__, ret);
14066                         break;
14067                 }
14068
14069                 /* Verify it. */
14070                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14071                         if (p[i] == i)
14072                                 continue;
14073
14074                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14075                             DMA_RWCTRL_WRITE_BNDRY_16) {
14076                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14077                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14078                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14079                                 break;
14080                         } else {
14081                                 dev_err(&tp->pdev->dev,
14082                                         "%s: Buffer corrupted on read back! "
14083                                         "(%d != %d)\n", __func__, p[i], i);
14084                                 ret = -ENODEV;
14085                                 goto out;
14086                         }
14087                 }
14088
14089                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14090                         /* Success. */
14091                         ret = 0;
14092                         break;
14093                 }
14094         }
14095         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14096             DMA_RWCTRL_WRITE_BNDRY_16) {
14097                 static struct pci_device_id dma_wait_state_chipsets[] = {
14098                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14099                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14100                         { },
14101                 };
14102
14103                 /* DMA test passed without adjusting DMA boundary,
14104                  * now look for chipsets that are known to expose the
14105                  * DMA bug without failing the test.
14106                  */
14107                 if (pci_dev_present(dma_wait_state_chipsets)) {
14108                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14109                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14110                 } else {
14111                         /* Safe to use the calculated DMA boundary. */
14112                         tp->dma_rwctrl = saved_dma_rwctrl;
14113                 }
14114
14115                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14116         }
14117
14118 out:
14119         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14120 out_nofree:
14121         return ret;
14122 }
14123
14124 static void __devinit tg3_init_link_config(struct tg3 *tp)
14125 {
14126         tp->link_config.advertising =
14127                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14128                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14129                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14130                  ADVERTISED_Autoneg | ADVERTISED_MII);
14131         tp->link_config.speed = SPEED_INVALID;
14132         tp->link_config.duplex = DUPLEX_INVALID;
14133         tp->link_config.autoneg = AUTONEG_ENABLE;
14134         tp->link_config.active_speed = SPEED_INVALID;
14135         tp->link_config.active_duplex = DUPLEX_INVALID;
14136         tp->link_config.phy_is_low_power = 0;
14137         tp->link_config.orig_speed = SPEED_INVALID;
14138         tp->link_config.orig_duplex = DUPLEX_INVALID;
14139         tp->link_config.orig_autoneg = AUTONEG_INVALID;
14140 }
14141
14142 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14143 {
14144         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14145             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
14146             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
14147                 tp->bufmgr_config.mbuf_read_dma_low_water =
14148                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14149                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14150                         DEFAULT_MB_MACRX_LOW_WATER_57765;
14151                 tp->bufmgr_config.mbuf_high_water =
14152                         DEFAULT_MB_HIGH_WATER_57765;
14153
14154                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14155                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14156                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14157                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14158                 tp->bufmgr_config.mbuf_high_water_jumbo =
14159                         DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14160         } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14161                 tp->bufmgr_config.mbuf_read_dma_low_water =
14162                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14163                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14164                         DEFAULT_MB_MACRX_LOW_WATER_5705;
14165                 tp->bufmgr_config.mbuf_high_water =
14166                         DEFAULT_MB_HIGH_WATER_5705;
14167                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14168                         tp->bufmgr_config.mbuf_mac_rx_low_water =
14169                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
14170                         tp->bufmgr_config.mbuf_high_water =
14171                                 DEFAULT_MB_HIGH_WATER_5906;
14172                 }
14173
14174                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14175                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14176                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14177                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14178                 tp->bufmgr_config.mbuf_high_water_jumbo =
14179                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14180         } else {
14181                 tp->bufmgr_config.mbuf_read_dma_low_water =
14182                         DEFAULT_MB_RDMA_LOW_WATER;
14183                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14184                         DEFAULT_MB_MACRX_LOW_WATER;
14185                 tp->bufmgr_config.mbuf_high_water =
14186                         DEFAULT_MB_HIGH_WATER;
14187
14188                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14189                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14190                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14191                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14192                 tp->bufmgr_config.mbuf_high_water_jumbo =
14193                         DEFAULT_MB_HIGH_WATER_JUMBO;
14194         }
14195
14196         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14197         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14198 }
14199
14200 static char * __devinit tg3_phy_string(struct tg3 *tp)
14201 {
14202         switch (tp->phy_id & TG3_PHY_ID_MASK) {
14203         case TG3_PHY_ID_BCM5400:        return "5400";
14204         case TG3_PHY_ID_BCM5401:        return "5401";
14205         case TG3_PHY_ID_BCM5411:        return "5411";
14206         case TG3_PHY_ID_BCM5701:        return "5701";
14207         case TG3_PHY_ID_BCM5703:        return "5703";
14208         case TG3_PHY_ID_BCM5704:        return "5704";
14209         case TG3_PHY_ID_BCM5705:        return "5705";
14210         case TG3_PHY_ID_BCM5750:        return "5750";
14211         case TG3_PHY_ID_BCM5752:        return "5752";
14212         case TG3_PHY_ID_BCM5714:        return "5714";
14213         case TG3_PHY_ID_BCM5780:        return "5780";
14214         case TG3_PHY_ID_BCM5755:        return "5755";
14215         case TG3_PHY_ID_BCM5787:        return "5787";
14216         case TG3_PHY_ID_BCM5784:        return "5784";
14217         case TG3_PHY_ID_BCM5756:        return "5722/5756";
14218         case TG3_PHY_ID_BCM5906:        return "5906";
14219         case TG3_PHY_ID_BCM5761:        return "5761";
14220         case TG3_PHY_ID_BCM5718C:       return "5718C";
14221         case TG3_PHY_ID_BCM5718S:       return "5718S";
14222         case TG3_PHY_ID_BCM57765:       return "57765";
14223         case TG3_PHY_ID_BCM5719C:       return "5719C";
14224         case TG3_PHY_ID_BCM8002:        return "8002/serdes";
14225         case 0:                 return "serdes";
14226         default:                return "unknown";
14227         }
14228 }
14229
14230 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14231 {
14232         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14233                 strcpy(str, "PCI Express");
14234                 return str;
14235         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14236                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14237
14238                 strcpy(str, "PCIX:");
14239
14240                 if ((clock_ctrl == 7) ||
14241                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14242                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14243                         strcat(str, "133MHz");
14244                 else if (clock_ctrl == 0)
14245                         strcat(str, "33MHz");
14246                 else if (clock_ctrl == 2)
14247                         strcat(str, "50MHz");
14248                 else if (clock_ctrl == 4)
14249                         strcat(str, "66MHz");
14250                 else if (clock_ctrl == 6)
14251                         strcat(str, "100MHz");
14252         } else {
14253                 strcpy(str, "PCI:");
14254                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14255                         strcat(str, "66MHz");
14256                 else
14257                         strcat(str, "33MHz");
14258         }
14259         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14260                 strcat(str, ":32-bit");
14261         else
14262                 strcat(str, ":64-bit");
14263         return str;
14264 }
14265
14266 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14267 {
14268         struct pci_dev *peer;
14269         unsigned int func, devnr = tp->pdev->devfn & ~7;
14270
14271         for (func = 0; func < 8; func++) {
14272                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14273                 if (peer && peer != tp->pdev)
14274                         break;
14275                 pci_dev_put(peer);
14276         }
14277         /* 5704 can be configured in single-port mode, set peer to
14278          * tp->pdev in that case.
14279          */
14280         if (!peer) {
14281                 peer = tp->pdev;
14282                 return peer;
14283         }
14284
14285         /*
14286          * We don't need to keep the refcount elevated; there's no way
14287          * to remove one half of this device without removing the other
14288          */
14289         pci_dev_put(peer);
14290
14291         return peer;
14292 }
14293
14294 static void __devinit tg3_init_coal(struct tg3 *tp)
14295 {
14296         struct ethtool_coalesce *ec = &tp->coal;
14297
14298         memset(ec, 0, sizeof(*ec));
14299         ec->cmd = ETHTOOL_GCOALESCE;
14300         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14301         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14302         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14303         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14304         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14305         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14306         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14307         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14308         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14309
14310         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14311                                  HOSTCC_MODE_CLRTICK_TXBD)) {
14312                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14313                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14314                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14315                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14316         }
14317
14318         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14319                 ec->rx_coalesce_usecs_irq = 0;
14320                 ec->tx_coalesce_usecs_irq = 0;
14321                 ec->stats_block_coalesce_usecs = 0;
14322         }
14323 }
14324
14325 static const struct net_device_ops tg3_netdev_ops = {
14326         .ndo_open               = tg3_open,
14327         .ndo_stop               = tg3_close,
14328         .ndo_start_xmit         = tg3_start_xmit,
14329         .ndo_get_stats64        = tg3_get_stats64,
14330         .ndo_validate_addr      = eth_validate_addr,
14331         .ndo_set_multicast_list = tg3_set_rx_mode,
14332         .ndo_set_mac_address    = tg3_set_mac_addr,
14333         .ndo_do_ioctl           = tg3_ioctl,
14334         .ndo_tx_timeout         = tg3_tx_timeout,
14335         .ndo_change_mtu         = tg3_change_mtu,
14336 #if TG3_VLAN_TAG_USED
14337         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14338 #endif
14339 #ifdef CONFIG_NET_POLL_CONTROLLER
14340         .ndo_poll_controller    = tg3_poll_controller,
14341 #endif
14342 };
14343
14344 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14345         .ndo_open               = tg3_open,
14346         .ndo_stop               = tg3_close,
14347         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
14348         .ndo_get_stats64        = tg3_get_stats64,
14349         .ndo_validate_addr      = eth_validate_addr,
14350         .ndo_set_multicast_list = tg3_set_rx_mode,
14351         .ndo_set_mac_address    = tg3_set_mac_addr,
14352         .ndo_do_ioctl           = tg3_ioctl,
14353         .ndo_tx_timeout         = tg3_tx_timeout,
14354         .ndo_change_mtu         = tg3_change_mtu,
14355 #if TG3_VLAN_TAG_USED
14356         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14357 #endif
14358 #ifdef CONFIG_NET_POLL_CONTROLLER
14359         .ndo_poll_controller    = tg3_poll_controller,
14360 #endif
14361 };
14362
14363 static int __devinit tg3_init_one(struct pci_dev *pdev,
14364                                   const struct pci_device_id *ent)
14365 {
14366         struct net_device *dev;
14367         struct tg3 *tp;
14368         int i, err, pm_cap;
14369         u32 sndmbx, rcvmbx, intmbx;
14370         char str[40];
14371         u64 dma_mask, persist_dma_mask;
14372
14373         printk_once(KERN_INFO "%s\n", version);
14374
14375         err = pci_enable_device(pdev);
14376         if (err) {
14377                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
14378                 return err;
14379         }
14380
14381         err = pci_request_regions(pdev, DRV_MODULE_NAME);
14382         if (err) {
14383                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
14384                 goto err_out_disable_pdev;
14385         }
14386
14387         pci_set_master(pdev);
14388
14389         /* Find power-management capability. */
14390         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14391         if (pm_cap == 0) {
14392                 dev_err(&pdev->dev,
14393                         "Cannot find Power Management capability, aborting\n");
14394                 err = -EIO;
14395                 goto err_out_free_res;
14396         }
14397
14398         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14399         if (!dev) {
14400                 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
14401                 err = -ENOMEM;
14402                 goto err_out_free_res;
14403         }
14404
14405         SET_NETDEV_DEV(dev, &pdev->dev);
14406
14407 #if TG3_VLAN_TAG_USED
14408         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14409 #endif
14410
14411         tp = netdev_priv(dev);
14412         tp->pdev = pdev;
14413         tp->dev = dev;
14414         tp->pm_cap = pm_cap;
14415         tp->rx_mode = TG3_DEF_RX_MODE;
14416         tp->tx_mode = TG3_DEF_TX_MODE;
14417
14418         if (tg3_debug > 0)
14419                 tp->msg_enable = tg3_debug;
14420         else
14421                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14422
14423         /* The word/byte swap controls here control register access byte
14424          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
14425          * setting below.
14426          */
14427         tp->misc_host_ctrl =
14428                 MISC_HOST_CTRL_MASK_PCI_INT |
14429                 MISC_HOST_CTRL_WORD_SWAP |
14430                 MISC_HOST_CTRL_INDIR_ACCESS |
14431                 MISC_HOST_CTRL_PCISTATE_RW;
14432
14433         /* The NONFRM (non-frame) byte/word swap controls take effect
14434          * on descriptor entries, anything which isn't packet data.
14435          *
14436          * The StrongARM chips on the board (one for tx, one for rx)
14437          * are running in big-endian mode.
14438          */
14439         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14440                         GRC_MODE_WSWAP_NONFRM_DATA);
14441 #ifdef __BIG_ENDIAN
14442         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14443 #endif
14444         spin_lock_init(&tp->lock);
14445         spin_lock_init(&tp->indirect_lock);
14446         INIT_WORK(&tp->reset_task, tg3_reset_task);
14447
14448         tp->regs = pci_ioremap_bar(pdev, BAR_0);
14449         if (!tp->regs) {
14450                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
14451                 err = -ENOMEM;
14452                 goto err_out_free_dev;
14453         }
14454
14455         tg3_init_link_config(tp);
14456
14457         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14458         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14459
14460         dev->ethtool_ops = &tg3_ethtool_ops;
14461         dev->watchdog_timeo = TG3_TX_TIMEOUT;
14462         dev->irq = pdev->irq;
14463
14464         err = tg3_get_invariants(tp);
14465         if (err) {
14466                 dev_err(&pdev->dev,
14467                         "Problem fetching invariants of chip, aborting\n");
14468                 goto err_out_iounmap;
14469         }
14470
14471         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14472             tp->pci_chip_rev_id != CHIPREV_ID_5717_A0 &&
14473             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
14474                 dev->netdev_ops = &tg3_netdev_ops;
14475         else
14476                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14477
14478
14479         /* The EPB bridge inside 5714, 5715, and 5780 and any
14480          * device behind the EPB cannot support DMA addresses > 40-bit.
14481          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14482          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14483          * do DMA address check in tg3_start_xmit().
14484          */
14485         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14486                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14487         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14488                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14489 #ifdef CONFIG_HIGHMEM
14490                 dma_mask = DMA_BIT_MASK(64);
14491 #endif
14492         } else
14493                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14494
14495         /* Configure DMA attributes. */
14496         if (dma_mask > DMA_BIT_MASK(32)) {
14497                 err = pci_set_dma_mask(pdev, dma_mask);
14498                 if (!err) {
14499                         dev->features |= NETIF_F_HIGHDMA;
14500                         err = pci_set_consistent_dma_mask(pdev,
14501                                                           persist_dma_mask);
14502                         if (err < 0) {
14503                                 dev_err(&pdev->dev, "Unable to obtain 64 bit "
14504                                         "DMA for consistent allocations\n");
14505                                 goto err_out_iounmap;
14506                         }
14507                 }
14508         }
14509         if (err || dma_mask == DMA_BIT_MASK(32)) {
14510                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14511                 if (err) {
14512                         dev_err(&pdev->dev,
14513                                 "No usable DMA configuration, aborting\n");
14514                         goto err_out_iounmap;
14515                 }
14516         }
14517
14518         tg3_init_bufmgr_config(tp);
14519
14520         /* Selectively allow TSO based on operating conditions */
14521         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14522             (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14523                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14524         else {
14525                 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14526                 tp->fw_needed = NULL;
14527         }
14528
14529         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14530                 tp->fw_needed = FIRMWARE_TG3;
14531
14532         /* TSO is on by default on chips that support hardware TSO.
14533          * Firmware TSO on older chips gives lower performance, so it
14534          * is off by default, but can be enabled using ethtool.
14535          */
14536         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14537             (dev->features & NETIF_F_IP_CSUM)) {
14538                 dev->features |= NETIF_F_TSO;
14539                 vlan_features_add(dev, NETIF_F_TSO);
14540         }
14541         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14542             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14543                 if (dev->features & NETIF_F_IPV6_CSUM) {
14544                         dev->features |= NETIF_F_TSO6;
14545                         vlan_features_add(dev, NETIF_F_TSO6);
14546                 }
14547                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14548                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14549                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14550                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14551                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14552                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
14553                         dev->features |= NETIF_F_TSO_ECN;
14554                         vlan_features_add(dev, NETIF_F_TSO_ECN);
14555                 }
14556         }
14557
14558         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14559             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14560             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14561                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14562                 tp->rx_pending = 63;
14563         }
14564
14565         err = tg3_get_device_address(tp);
14566         if (err) {
14567                 dev_err(&pdev->dev,
14568                         "Could not obtain valid ethernet address, aborting\n");
14569                 goto err_out_iounmap;
14570         }
14571
14572         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14573                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14574                 if (!tp->aperegs) {
14575                         dev_err(&pdev->dev,
14576                                 "Cannot map APE registers, aborting\n");
14577                         err = -ENOMEM;
14578                         goto err_out_iounmap;
14579                 }
14580
14581                 tg3_ape_lock_init(tp);
14582
14583                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14584                         tg3_read_dash_ver(tp);
14585         }
14586
14587         /*
14588          * Reset chip in case UNDI or EFI driver did not shutdown
14589          * DMA self test will enable WDMAC and we'll see (spurious)
14590          * pending DMA on the PCI bus at that point.
14591          */
14592         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14593             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14594                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14595                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14596         }
14597
14598         err = tg3_test_dma(tp);
14599         if (err) {
14600                 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
14601                 goto err_out_apeunmap;
14602         }
14603
14604         /* flow control autonegotiation is default behavior */
14605         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14606         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14607
14608         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14609         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14610         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14611         for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14612                 struct tg3_napi *tnapi = &tp->napi[i];
14613
14614                 tnapi->tp = tp;
14615                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14616
14617                 tnapi->int_mbox = intmbx;
14618                 if (i < 4)
14619                         intmbx += 0x8;
14620                 else
14621                         intmbx += 0x4;
14622
14623                 tnapi->consmbox = rcvmbx;
14624                 tnapi->prodmbox = sndmbx;
14625
14626                 if (i) {
14627                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14628                         netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14629                 } else {
14630                         tnapi->coal_now = HOSTCC_MODE_NOW;
14631                         netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14632                 }
14633
14634                 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14635                         break;
14636
14637                 /*
14638                  * If we support MSIX, we'll be using RSS.  If we're using
14639                  * RSS, the first vector only handles link interrupts and the
14640                  * remaining vectors handle rx and tx interrupts.  Reuse the
14641                  * mailbox values for the next iteration.  The values we setup
14642                  * above are still useful for the single vectored mode.
14643                  */
14644                 if (!i)
14645                         continue;
14646
14647                 rcvmbx += 0x8;
14648
14649                 if (sndmbx & 0x4)
14650                         sndmbx -= 0x4;
14651                 else
14652                         sndmbx += 0xc;
14653         }
14654
14655         tg3_init_coal(tp);
14656
14657         pci_set_drvdata(pdev, dev);
14658
14659         err = register_netdev(dev);
14660         if (err) {
14661                 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
14662                 goto err_out_apeunmap;
14663         }
14664
14665         netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14666                     tp->board_part_number,
14667                     tp->pci_chip_rev_id,
14668                     tg3_bus_string(tp, str),
14669                     dev->dev_addr);
14670
14671         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14672                 struct phy_device *phydev;
14673                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14674                 netdev_info(dev,
14675                             "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14676                             phydev->drv->name, dev_name(&phydev->dev));
14677         } else
14678                 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
14679                             "(WireSpeed[%d])\n", tg3_phy_string(tp),
14680                             ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14681                              ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14682                               "10/100/1000Base-T")),
14683                             (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14684
14685         netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14686                     (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14687                     (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14688                     (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14689                     (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14690                     (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14691         netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14692                     tp->dma_rwctrl,
14693                     pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
14694                     ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
14695
14696         return 0;
14697
14698 err_out_apeunmap:
14699         if (tp->aperegs) {
14700                 iounmap(tp->aperegs);
14701                 tp->aperegs = NULL;
14702         }
14703
14704 err_out_iounmap:
14705         if (tp->regs) {
14706                 iounmap(tp->regs);
14707                 tp->regs = NULL;
14708         }
14709
14710 err_out_free_dev:
14711         free_netdev(dev);
14712
14713 err_out_free_res:
14714         pci_release_regions(pdev);
14715
14716 err_out_disable_pdev:
14717         pci_disable_device(pdev);
14718         pci_set_drvdata(pdev, NULL);
14719         return err;
14720 }
14721
14722 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14723 {
14724         struct net_device *dev = pci_get_drvdata(pdev);
14725
14726         if (dev) {
14727                 struct tg3 *tp = netdev_priv(dev);
14728
14729                 if (tp->fw)
14730                         release_firmware(tp->fw);
14731
14732                 flush_scheduled_work();
14733
14734                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14735                         tg3_phy_fini(tp);
14736                         tg3_mdio_fini(tp);
14737                 }
14738
14739                 unregister_netdev(dev);
14740                 if (tp->aperegs) {
14741                         iounmap(tp->aperegs);
14742                         tp->aperegs = NULL;
14743                 }
14744                 if (tp->regs) {
14745                         iounmap(tp->regs);
14746                         tp->regs = NULL;
14747                 }
14748                 free_netdev(dev);
14749                 pci_release_regions(pdev);
14750                 pci_disable_device(pdev);
14751                 pci_set_drvdata(pdev, NULL);
14752         }
14753 }
14754
14755 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14756 {
14757         struct net_device *dev = pci_get_drvdata(pdev);
14758         struct tg3 *tp = netdev_priv(dev);
14759         pci_power_t target_state;
14760         int err;
14761
14762         /* PCI register 4 needs to be saved whether netif_running() or not.
14763          * MSI address and data need to be saved if using MSI and
14764          * netif_running().
14765          */
14766         pci_save_state(pdev);
14767
14768         if (!netif_running(dev))
14769                 return 0;
14770
14771         flush_scheduled_work();
14772         tg3_phy_stop(tp);
14773         tg3_netif_stop(tp);
14774
14775         del_timer_sync(&tp->timer);
14776
14777         tg3_full_lock(tp, 1);
14778         tg3_disable_ints(tp);
14779         tg3_full_unlock(tp);
14780
14781         netif_device_detach(dev);
14782
14783         tg3_full_lock(tp, 0);
14784         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14785         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14786         tg3_full_unlock(tp);
14787
14788         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14789
14790         err = tg3_set_power_state(tp, target_state);
14791         if (err) {
14792                 int err2;
14793
14794                 tg3_full_lock(tp, 0);
14795
14796                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14797                 err2 = tg3_restart_hw(tp, 1);
14798                 if (err2)
14799                         goto out;
14800
14801                 tp->timer.expires = jiffies + tp->timer_offset;
14802                 add_timer(&tp->timer);
14803
14804                 netif_device_attach(dev);
14805                 tg3_netif_start(tp);
14806
14807 out:
14808                 tg3_full_unlock(tp);
14809
14810                 if (!err2)
14811                         tg3_phy_start(tp);
14812         }
14813
14814         return err;
14815 }
14816
14817 static int tg3_resume(struct pci_dev *pdev)
14818 {
14819         struct net_device *dev = pci_get_drvdata(pdev);
14820         struct tg3 *tp = netdev_priv(dev);
14821         int err;
14822
14823         pci_restore_state(tp->pdev);
14824
14825         if (!netif_running(dev))
14826                 return 0;
14827
14828         err = tg3_set_power_state(tp, PCI_D0);
14829         if (err)
14830                 return err;
14831
14832         netif_device_attach(dev);
14833
14834         tg3_full_lock(tp, 0);
14835
14836         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14837         err = tg3_restart_hw(tp, 1);
14838         if (err)
14839                 goto out;
14840
14841         tp->timer.expires = jiffies + tp->timer_offset;
14842         add_timer(&tp->timer);
14843
14844         tg3_netif_start(tp);
14845
14846 out:
14847         tg3_full_unlock(tp);
14848
14849         if (!err)
14850                 tg3_phy_start(tp);
14851
14852         return err;
14853 }
14854
14855 static struct pci_driver tg3_driver = {
14856         .name           = DRV_MODULE_NAME,
14857         .id_table       = tg3_pci_tbl,
14858         .probe          = tg3_init_one,
14859         .remove         = __devexit_p(tg3_remove_one),
14860         .suspend        = tg3_suspend,
14861         .resume         = tg3_resume
14862 };
14863
14864 static int __init tg3_init(void)
14865 {
14866         return pci_register_driver(&tg3_driver);
14867 }
14868
14869 static void __exit tg3_cleanup(void)
14870 {
14871         pci_unregister_driver(&tg3_driver);
14872 }
14873
14874 module_init(tg3_init);
14875 module_exit(tg3_cleanup);