drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2010 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/stringify.h>
  22 #include <linux/kernel.h>
  23 #include <linux/types.h>
  24 #include <linux/compiler.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/in.h>
  28 #include <linux/init.h>
  29 #include <linux/ioport.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/ethtool.h>
  35 #include <linux/mii.h>
  36 #include <linux/phy.h>
  37 #include <linux/brcmphy.h>
  38 #include <linux/if_vlan.h>
  39 #include <linux/ip.h>
  40 #include <linux/tcp.h>
  41 #include <linux/workqueue.h>
  42 #include <linux/prefetch.h>
  43 #include <linux/dma-mapping.h>
  44 #include <linux/firmware.h>
  45
  46 #include <net/checksum.h>
  47 #include <net/ip.h>
  48
  49 #include <asm/system.h>
  50 #include <asm/io.h>
  51 #include <asm/byteorder.h>
  52 #include <asm/uaccess.h>
  53
  54 #ifdef CONFIG_SPARC
  55 #include <asm/idprom.h>
  56 #include <asm/prom.h>
  57 #endif
  58
  59 #define BAR_0   0
  60 #define BAR_2   2
  61
  62 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  63 #define TG3_VLAN_TAG_USED 1
  64 #else
  65 #define TG3_VLAN_TAG_USED 0
  66 #endif
  67
  68 #include "tg3.h"
  69
  70 #define DRV_MODULE_NAME         "tg3"
  71 #define TG3_MAJ_NUM                     3
  72 #define TG3_MIN_NUM                     113
  73 #define DRV_MODULE_VERSION      \
  74         __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
  75 #define DRV_MODULE_RELDATE      "August 2, 2010"
  76
  77 #define TG3_DEF_MAC_MODE        0
  78 #define TG3_DEF_RX_MODE         0
  79 #define TG3_DEF_TX_MODE         0
  80 #define TG3_DEF_MSG_ENABLE        \
  81         (NETIF_MSG_DRV          | \
  82          NETIF_MSG_PROBE        | \
  83          NETIF_MSG_LINK         | \
  84          NETIF_MSG_TIMER        | \
  85          NETIF_MSG_IFDOWN       | \
  86          NETIF_MSG_IFUP         | \
  87          NETIF_MSG_RX_ERR       | \
  88          NETIF_MSG_TX_ERR)
  89
  90 /* length of time before we decide the hardware is borked,
  91  * and dev->tx_timeout() should be called to fix the problem
  92  */
  93 #define TG3_TX_TIMEOUT                  (5 * HZ)
  94
  95 /* hardware minimum and maximum for a single frame's data payload */
  96 #define TG3_MIN_MTU                     60
  97 #define TG3_MAX_MTU(tp) \
  98         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  99
 100 /* These numbers seem to be hard coded in the NIC firmware somehow.
 101  * You can't change the ring sizes, but you can change where you place
 102  * them in the NIC onboard memory.
 103  */
 104 #define TG3_RX_RING_SIZE                512
 105 #define TG3_DEF_RX_RING_PENDING         200
 106 #define TG3_RX_JUMBO_RING_SIZE          256
 107 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 108 #define TG3_RSS_INDIR_TBL_SIZE          128
 109
 110 /* Do not place this n-ring entries value into the tp struct itself,
 111  * we really want to expose these constants to GCC so that modulo et
 112  * al.  operations are done with shifts and masks instead of with
 113  * hw multiply/modulo instructions.  Another solution would be to
 114  * replace things like '% foo' with '& (foo - 1)'.
 115  */
 116 #define TG3_RX_RCB_RING_SIZE(tp)        \
 117         (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
 118           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
 119
 120 #define TG3_TX_RING_SIZE                512
 121 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 122
 123 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 124                                  TG3_RX_RING_SIZE)
 125 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
 126                                  TG3_RX_JUMBO_RING_SIZE)
 127 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 128                                  TG3_RX_RCB_RING_SIZE(tp))
 129 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 130                                  TG3_TX_RING_SIZE)
 131 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 132
 133 #define TG3_RX_DMA_ALIGN                16
 134 #define TG3_RX_HEADROOM                 ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
 135
 136 #define TG3_DMA_BYTE_ENAB               64
 137
 138 #define TG3_RX_STD_DMA_SZ               1536
 139 #define TG3_RX_JMB_DMA_SZ               9046
 140
 141 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 142
 143 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 144 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 145
 146 #define TG3_RX_STD_BUFF_RING_SIZE \
 147         (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
 148
 149 #define TG3_RX_JMB_BUFF_RING_SIZE \
 150         (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
 151
 152 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
 153  * that are at least dword aligned when used in PCIX mode.  The driver
 154  * works around this bug by double copying the packet.  This workaround
 155  * is built into the normal double copy length check for efficiency.
 156  *
 157  * However, the double copy is only necessary on those architectures
 158  * where unaligned memory accesses are inefficient.  For those architectures
 159  * where unaligned memory accesses incur little penalty, we can reintegrate
 160  * the 5701 in the normal rx path.  Doing so saves a device structure
 161  * dereference by hardcoding the double copy threshold in place.
 162  */
 163 #define TG3_RX_COPY_THRESHOLD           256
 164 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
 165         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
 166 #else
 167         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
 168 #endif
 169
 170 /* minimum number of free TX descriptors required to wake up TX process */
 171 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 172
 173 #define TG3_RAW_IP_ALIGN 2
 174
 175 /* number of ETHTOOL_GSTATS u64's */
 176 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 177
 178 #define TG3_NUM_TEST            6
 179
 180 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
 181
 182 #define FIRMWARE_TG3            "tigon/tg3.bin"
 183 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 184 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 185
 186 static char version[] __devinitdata =
 187         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
 188
 189 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 190 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 191 MODULE_LICENSE("GPL");
 192 MODULE_VERSION(DRV_MODULE_VERSION);
 193 MODULE_FIRMWARE(FIRMWARE_TG3);
 194 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 195 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 196
 197 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 198 module_param(tg3_debug, int, 0);
 199 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 200
 201 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 255         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 256         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 257         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 258         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 259         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 260         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 261         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 262         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 263         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 264         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 265         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
 266         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
 267         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
 268         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
 269         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
 270         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
 271         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
 272         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
 273         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
 274         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
 275         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 276         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 277         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 278         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 279         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 280         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 281         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 282         {}
 283 };
 284
 285 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 286
 287 static const struct {
 288         const char string[ETH_GSTRING_LEN];
 289 } ethtool_stats_keys[TG3_NUM_STATS] = {
 290         { "rx_octets" },
 291         { "rx_fragments" },
 292         { "rx_ucast_packets" },
 293         { "rx_mcast_packets" },
 294         { "rx_bcast_packets" },
 295         { "rx_fcs_errors" },
 296         { "rx_align_errors" },
 297         { "rx_xon_pause_rcvd" },
 298         { "rx_xoff_pause_rcvd" },
 299         { "rx_mac_ctrl_rcvd" },
 300         { "rx_xoff_entered" },
 301         { "rx_frame_too_long_errors" },
 302         { "rx_jabbers" },
 303         { "rx_undersize_packets" },
 304         { "rx_in_length_errors" },
 305         { "rx_out_length_errors" },
 306         { "rx_64_or_less_octet_packets" },
 307         { "rx_65_to_127_octet_packets" },
 308         { "rx_128_to_255_octet_packets" },
 309         { "rx_256_to_511_octet_packets" },
 310         { "rx_512_to_1023_octet_packets" },
 311         { "rx_1024_to_1522_octet_packets" },
 312         { "rx_1523_to_2047_octet_packets" },
 313         { "rx_2048_to_4095_octet_packets" },
 314         { "rx_4096_to_8191_octet_packets" },
 315         { "rx_8192_to_9022_octet_packets" },
 316
 317         { "tx_octets" },
 318         { "tx_collisions" },
 319
 320         { "tx_xon_sent" },
 321         { "tx_xoff_sent" },
 322         { "tx_flow_control" },
 323         { "tx_mac_errors" },
 324         { "tx_single_collisions" },
 325         { "tx_mult_collisions" },
 326         { "tx_deferred" },
 327         { "tx_excessive_collisions" },
 328         { "tx_late_collisions" },
 329         { "tx_collide_2times" },
 330         { "tx_collide_3times" },
 331         { "tx_collide_4times" },
 332         { "tx_collide_5times" },
 333         { "tx_collide_6times" },
 334         { "tx_collide_7times" },
 335         { "tx_collide_8times" },
 336         { "tx_collide_9times" },
 337         { "tx_collide_10times" },
 338         { "tx_collide_11times" },
 339         { "tx_collide_12times" },
 340         { "tx_collide_13times" },
 341         { "tx_collide_14times" },
 342         { "tx_collide_15times" },
 343         { "tx_ucast_packets" },
 344         { "tx_mcast_packets" },
 345         { "tx_bcast_packets" },
 346         { "tx_carrier_sense_errors" },
 347         { "tx_discards" },
 348         { "tx_errors" },
 349
 350         { "dma_writeq_full" },
 351         { "dma_write_prioq_full" },
 352         { "rxbds_empty" },
 353         { "rx_discards" },
 354         { "rx_errors" },
 355         { "rx_threshold_hit" },
 356
 357         { "dma_readq_full" },
 358         { "dma_read_prioq_full" },
 359         { "tx_comp_queue_full" },
 360
 361         { "ring_set_send_prod_index" },
 362         { "ring_status_update" },
 363         { "nic_irqs" },
 364         { "nic_avoided_irqs" },
 365         { "nic_tx_threshold_hit" }
 366 };
 367
 368 static const struct {
 369         const char string[ETH_GSTRING_LEN];
 370 } ethtool_test_keys[TG3_NUM_TEST] = {
 371         { "nvram test     (online) " },
 372         { "link test      (online) " },
 373         { "register test  (offline)" },
 374         { "memory test    (offline)" },
 375         { "loopback test  (offline)" },
 376         { "interrupt test (offline)" },
 377 };
 378
 379 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 380 {
 381         writel(val, tp->regs + off);
 382 }
 383
 384 static u32 tg3_read32(struct tg3 *tp, u32 off)
 385 {
 386         return readl(tp->regs + off);
 387 }
 388
 389 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 390 {
 391         writel(val, tp->aperegs + off);
 392 }
 393
 394 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 395 {
 396         return readl(tp->aperegs + off);
 397 }
 398
 399 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 400 {
 401         unsigned long flags;
 402
 403         spin_lock_irqsave(&tp->indirect_lock, flags);
 404         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 405         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 406         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 407 }
 408
 409 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 410 {
 411         writel(val, tp->regs + off);
 412         readl(tp->regs + off);
 413 }
 414
 415 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 416 {
 417         unsigned long flags;
 418         u32 val;
 419
 420         spin_lock_irqsave(&tp->indirect_lock, flags);
 421         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 422         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 423         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 424         return val;
 425 }
 426
 427 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 428 {
 429         unsigned long flags;
 430
 431         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 432                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 433                                        TG3_64BIT_REG_LOW, val);
 434                 return;
 435         }
 436         if (off == TG3_RX_STD_PROD_IDX_REG) {
 437                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 438                                        TG3_64BIT_REG_LOW, val);
 439                 return;
 440         }
 441
 442         spin_lock_irqsave(&tp->indirect_lock, flags);
 443         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 444         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 445         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 446
 447         /* In indirect mode when disabling interrupts, we also need
 448          * to clear the interrupt bit in the GRC local ctrl register.
 449          */
 450         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 451             (val == 0x1)) {
 452                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 453                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 454         }
 455 }
 456
 457 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 458 {
 459         unsigned long flags;
 460         u32 val;
 461
 462         spin_lock_irqsave(&tp->indirect_lock, flags);
 463         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 464         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 465         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 466         return val;
 467 }
 468
 469 /* usec_wait specifies the wait time in usec when writing to certain registers
 470  * where it is unsafe to read back the register without some delay.
 471  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 472  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 473  */
 474 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 475 {
 476         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 477             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 478                 /* Non-posted methods */
 479                 tp->write32(tp, off, val);
 480         else {
 481                 /* Posted method */
 482                 tg3_write32(tp, off, val);
 483                 if (usec_wait)
 484                         udelay(usec_wait);
 485                 tp->read32(tp, off);
 486         }
 487         /* Wait again after the read for the posted method to guarantee that
 488          * the wait time is met.
 489          */
 490         if (usec_wait)
 491                 udelay(usec_wait);
 492 }
 493
 494 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 495 {
 496         tp->write32_mbox(tp, off, val);
 497         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 498             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 499                 tp->read32_mbox(tp, off);
 500 }
 501
 502 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 503 {
 504         void __iomem *mbox = tp->regs + off;
 505         writel(val, mbox);
 506         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 507                 writel(val, mbox);
 508         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 509                 readl(mbox);
 510 }
 511
 512 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 513 {
 514         return readl(tp->regs + off + GRCMBOX_BASE);
 515 }
 516
 517 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 518 {
 519         writel(val, tp->regs + off + GRCMBOX_BASE);
 520 }
 521
 522 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
 523 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 524 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
 525 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
 526 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
 527
 528 #define tw32(reg, val)                  tp->write32(tp, reg, val)
 529 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
 530 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
 531 #define tr32(reg)                       tp->read32(tp, reg)
 532
 533 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 534 {
 535         unsigned long flags;
 536
 537         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 538             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 539                 return;
 540
 541         spin_lock_irqsave(&tp->indirect_lock, flags);
 542         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 543                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 544                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 545
 546                 /* Always leave this as zero. */
 547                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 548         } else {
 549                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 550                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 551
 552                 /* Always leave this as zero. */
 553                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 554         }
 555         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 556 }
 557
 558 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 559 {
 560         unsigned long flags;
 561
 562         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 563             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 564                 *val = 0;
 565                 return;
 566         }
 567
 568         spin_lock_irqsave(&tp->indirect_lock, flags);
 569         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 570                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 571                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 572
 573                 /* Always leave this as zero. */
 574                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 575         } else {
 576                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 577                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 578
 579                 /* Always leave this as zero. */
 580                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 581         }
 582         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 583 }
 584
 585 static void tg3_ape_lock_init(struct tg3 *tp)
 586 {
 587         int i;
 588         u32 regbase;
 589
 590         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 591                 regbase = TG3_APE_LOCK_GRANT;
 592         else
 593                 regbase = TG3_APE_PER_LOCK_GRANT;
 594
 595         /* Make sure the driver hasn't any stale locks. */
 596         for (i = 0; i < 8; i++)
 597                 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
 598 }
 599
 600 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 601 {
 602         int i, off;
 603         int ret = 0;
 604         u32 status, req, gnt;
 605
 606         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 607                 return 0;
 608
 609         switch (locknum) {
 610         case TG3_APE_LOCK_GRC:
 611         case TG3_APE_LOCK_MEM:
 612                 break;
 613         default:
 614                 return -EINVAL;
 615         }
 616
 617         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
 618                 req = TG3_APE_LOCK_REQ;
 619                 gnt = TG3_APE_LOCK_GRANT;
 620         } else {
 621                 req = TG3_APE_PER_LOCK_REQ;
 622                 gnt = TG3_APE_PER_LOCK_GRANT;
 623         }
 624
 625         off = 4 * locknum;
 626
 627         tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
 628
 629         /* Wait for up to 1 millisecond to acquire lock. */
 630         for (i = 0; i < 100; i++) {
 631                 status = tg3_ape_read32(tp, gnt + off);
 632                 if (status == APE_LOCK_GRANT_DRIVER)
 633                         break;
 634                 udelay(10);
 635         }
 636
 637         if (status != APE_LOCK_GRANT_DRIVER) {
 638                 /* Revoke the lock request. */
 639                 tg3_ape_write32(tp, gnt + off,
 640                                 APE_LOCK_GRANT_DRIVER);
 641
 642                 ret = -EBUSY;
 643         }
 644
 645         return ret;
 646 }
 647
 648 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 649 {
 650         u32 gnt;
 651
 652         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 653                 return;
 654
 655         switch (locknum) {
 656         case TG3_APE_LOCK_GRC:
 657         case TG3_APE_LOCK_MEM:
 658                 break;
 659         default:
 660                 return;
 661         }
 662
 663         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 664                 gnt = TG3_APE_LOCK_GRANT;
 665         else
 666                 gnt = TG3_APE_PER_LOCK_GRANT;
 667
 668         tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
 669 }
 670
 671 static void tg3_disable_ints(struct tg3 *tp)
 672 {
 673         int i;
 674
 675         tw32(TG3PCI_MISC_HOST_CTRL,
 676              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 677         for (i = 0; i < tp->irq_max; i++)
 678                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 679 }
 680
 681 static void tg3_enable_ints(struct tg3 *tp)
 682 {
 683         int i;
 684
 685         tp->irq_sync = 0;
 686         wmb();
 687
 688         tw32(TG3PCI_MISC_HOST_CTRL,
 689              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 690
 691         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
 692         for (i = 0; i < tp->irq_cnt; i++) {
 693                 struct tg3_napi *tnapi = &tp->napi[i];
 694
 695                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 696                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 697                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 698
 699                 tp->coal_now |= tnapi->coal_now;
 700         }
 701
 702         /* Force an initial interrupt */
 703         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 704             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 705                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 706         else
 707                 tw32(HOSTCC_MODE, tp->coal_now);
 708
 709         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
 710 }
 711
 712 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 713 {
 714         struct tg3 *tp = tnapi->tp;
 715         struct tg3_hw_status *sblk = tnapi->hw_status;
 716         unsigned int work_exists = 0;
 717
 718         /* check for phy events */
 719         if (!(tp->tg3_flags &
 720               (TG3_FLAG_USE_LINKCHG_REG |
 721                TG3_FLAG_POLL_SERDES))) {
 722                 if (sblk->status & SD_STATUS_LINK_CHG)
 723                         work_exists = 1;
 724         }
 725         /* check for RX/TX work to do */
 726         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 727             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
 728                 work_exists = 1;
 729
 730         return work_exists;
 731 }
 732
 733 /* tg3_int_reenable
 734  *  similar to tg3_enable_ints, but it accurately determines whether there
 735  *  is new work pending and can return without flushing the PIO write
 736  *  which reenables interrupts
 737  */
 738 static void tg3_int_reenable(struct tg3_napi *tnapi)
 739 {
 740         struct tg3 *tp = tnapi->tp;
 741
 742         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 743         mmiowb();
 744
 745         /* When doing tagged status, this work check is unnecessary.
 746          * The last_tag we write above tells the chip which piece of
 747          * work we've completed.
 748          */
 749         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 750             tg3_has_work(tnapi))
 751                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 752                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 753 }
 754
 755 static void tg3_switch_clocks(struct tg3 *tp)
 756 {
 757         u32 clock_ctrl;
 758         u32 orig_clock_ctrl;
 759
 760         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 761             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 762                 return;
 763
 764         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 765
 766         orig_clock_ctrl = clock_ctrl;
 767         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 768                        CLOCK_CTRL_CLKRUN_OENABLE |
 769                        0x1f);
 770         tp->pci_clock_ctrl = clock_ctrl;
 771
 772         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 773                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 774                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 775                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 776                 }
 777         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 778                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 779                             clock_ctrl |
 780                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 781                             40);
 782                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 783                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 784                             40);
 785         }
 786         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 787 }
 788
 789 #define PHY_BUSY_LOOPS  5000
 790
 791 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 792 {
 793         u32 frame_val;
 794         unsigned int loops;
 795         int ret;
 796
 797         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 798                 tw32_f(MAC_MI_MODE,
 799                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 800                 udelay(80);
 801         }
 802
 803         *val = 0x0;
 804
 805         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 806                       MI_COM_PHY_ADDR_MASK);
 807         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 808                       MI_COM_REG_ADDR_MASK);
 809         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 810
 811         tw32_f(MAC_MI_COM, frame_val);
 812
 813         loops = PHY_BUSY_LOOPS;
 814         while (loops != 0) {
 815                 udelay(10);
 816                 frame_val = tr32(MAC_MI_COM);
 817
 818                 if ((frame_val & MI_COM_BUSY) == 0) {
 819                         udelay(5);
 820                         frame_val = tr32(MAC_MI_COM);
 821                         break;
 822                 }
 823                 loops -= 1;
 824         }
 825
 826         ret = -EBUSY;
 827         if (loops != 0) {
 828                 *val = frame_val & MI_COM_DATA_MASK;
 829                 ret = 0;
 830         }
 831
 832         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 833                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 834                 udelay(80);
 835         }
 836
 837         return ret;
 838 }
 839
 840 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 841 {
 842         u32 frame_val;
 843         unsigned int loops;
 844         int ret;
 845
 846         if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
 847             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 848                 return 0;
 849
 850         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 851                 tw32_f(MAC_MI_MODE,
 852                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 853                 udelay(80);
 854         }
 855
 856         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 857                       MI_COM_PHY_ADDR_MASK);
 858         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 859                       MI_COM_REG_ADDR_MASK);
 860         frame_val |= (val & MI_COM_DATA_MASK);
 861         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 862
 863         tw32_f(MAC_MI_COM, frame_val);
 864
 865         loops = PHY_BUSY_LOOPS;
 866         while (loops != 0) {
 867                 udelay(10);
 868                 frame_val = tr32(MAC_MI_COM);
 869                 if ((frame_val & MI_COM_BUSY) == 0) {
 870                         udelay(5);
 871                         frame_val = tr32(MAC_MI_COM);
 872                         break;
 873                 }
 874                 loops -= 1;
 875         }
 876
 877         ret = -EBUSY;
 878         if (loops != 0)
 879                 ret = 0;
 880
 881         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 882                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 883                 udelay(80);
 884         }
 885
 886         return ret;
 887 }
 888
 889 static int tg3_bmcr_reset(struct tg3 *tp)
 890 {
 891         u32 phy_control;
 892         int limit, err;
 893
 894         /* OK, reset it, and poll the BMCR_RESET bit until it
 895          * clears or we time out.
 896          */
 897         phy_control = BMCR_RESET;
 898         err = tg3_writephy(tp, MII_BMCR, phy_control);
 899         if (err != 0)
 900                 return -EBUSY;
 901
 902         limit = 5000;
 903         while (limit--) {
 904                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 905                 if (err != 0)
 906                         return -EBUSY;
 907
 908                 if ((phy_control & BMCR_RESET) == 0) {
 909                         udelay(40);
 910                         break;
 911                 }
 912                 udelay(10);
 913         }
 914         if (limit < 0)
 915                 return -EBUSY;
 916
 917         return 0;
 918 }
 919
 920 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 921 {
 922         struct tg3 *tp = bp->priv;
 923         u32 val;
 924
 925         spin_lock_bh(&tp->lock);
 926
 927         if (tg3_readphy(tp, reg, &val))
 928                 val = -EIO;
 929
 930         spin_unlock_bh(&tp->lock);
 931
 932         return val;
 933 }
 934
 935 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 936 {
 937         struct tg3 *tp = bp->priv;
 938         u32 ret = 0;
 939
 940         spin_lock_bh(&tp->lock);
 941
 942         if (tg3_writephy(tp, reg, val))
 943                 ret = -EIO;
 944
 945         spin_unlock_bh(&tp->lock);
 946
 947         return ret;
 948 }
 949
 950 static int tg3_mdio_reset(struct mii_bus *bp)
 951 {
 952         return 0;
 953 }
 954
 955 static void tg3_mdio_config_5785(struct tg3 *tp)
 956 {
 957         u32 val;
 958         struct phy_device *phydev;
 959
 960         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
 961         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 962         case PHY_ID_BCM50610:
 963         case PHY_ID_BCM50610M:
 964                 val = MAC_PHYCFG2_50610_LED_MODES;
 965                 break;
 966         case PHY_ID_BCMAC131:
 967                 val = MAC_PHYCFG2_AC131_LED_MODES;
 968                 break;
 969         case PHY_ID_RTL8211C:
 970                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
 971                 break;
 972         case PHY_ID_RTL8201E:
 973                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
 974                 break;
 975         default:
 976                 return;
 977         }
 978
 979         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
 980                 tw32(MAC_PHYCFG2, val);
 981
 982                 val = tr32(MAC_PHYCFG1);
 983                 val &= ~(MAC_PHYCFG1_RGMII_INT |
 984                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
 985                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
 986                 tw32(MAC_PHYCFG1, val);
 987
 988                 return;
 989         }
 990
 991         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
 992                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
 993                        MAC_PHYCFG2_FMODE_MASK_MASK |
 994                        MAC_PHYCFG2_GMODE_MASK_MASK |
 995                        MAC_PHYCFG2_ACT_MASK_MASK   |
 996                        MAC_PHYCFG2_QUAL_MASK_MASK |
 997                        MAC_PHYCFG2_INBAND_ENABLE;
 998
 999         tw32(MAC_PHYCFG2, val);
1000
1001         val = tr32(MAC_PHYCFG1);
1002         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1003                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1004         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1005                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1006                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1007                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1008                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1009         }
1010         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1011                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1012         tw32(MAC_PHYCFG1, val);
1013
1014         val = tr32(MAC_EXT_RGMII_MODE);
1015         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1016                  MAC_RGMII_MODE_RX_QUALITY |
1017                  MAC_RGMII_MODE_RX_ACTIVITY |
1018                  MAC_RGMII_MODE_RX_ENG_DET |
1019                  MAC_RGMII_MODE_TX_ENABLE |
1020                  MAC_RGMII_MODE_TX_LOWPWR |
1021                  MAC_RGMII_MODE_TX_RESET);
1022         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1023                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1024                         val |= MAC_RGMII_MODE_RX_INT_B |
1025                                MAC_RGMII_MODE_RX_QUALITY |
1026                                MAC_RGMII_MODE_RX_ACTIVITY |
1027                                MAC_RGMII_MODE_RX_ENG_DET;
1028                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1029                         val |= MAC_RGMII_MODE_TX_ENABLE |
1030                                MAC_RGMII_MODE_TX_LOWPWR |
1031                                MAC_RGMII_MODE_TX_RESET;
1032         }
1033         tw32(MAC_EXT_RGMII_MODE, val);
1034 }
1035
1036 static void tg3_mdio_start(struct tg3 *tp)
1037 {
1038         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1039         tw32_f(MAC_MI_MODE, tp->mi_mode);
1040         udelay(80);
1041
1042         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1043             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1044                 tg3_mdio_config_5785(tp);
1045 }
1046
1047 static int tg3_mdio_init(struct tg3 *tp)
1048 {
1049         int i;
1050         u32 reg;
1051         struct phy_device *phydev;
1052
1053         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1054             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
1055                 u32 is_serdes;
1056
1057                 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1058
1059                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1060                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1061                 else
1062                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1063                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1064                 if (is_serdes)
1065                         tp->phy_addr += 7;
1066         } else
1067                 tp->phy_addr = TG3_PHY_MII_ADDR;
1068
1069         tg3_mdio_start(tp);
1070
1071         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1072             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1073                 return 0;
1074
1075         tp->mdio_bus = mdiobus_alloc();
1076         if (tp->mdio_bus == NULL)
1077                 return -ENOMEM;
1078
1079         tp->mdio_bus->name     = "tg3 mdio bus";
1080         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1081                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1082         tp->mdio_bus->priv     = tp;
1083         tp->mdio_bus->parent   = &tp->pdev->dev;
1084         tp->mdio_bus->read     = &tg3_mdio_read;
1085         tp->mdio_bus->write    = &tg3_mdio_write;
1086         tp->mdio_bus->reset    = &tg3_mdio_reset;
1087         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1088         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1089
1090         for (i = 0; i < PHY_MAX_ADDR; i++)
1091                 tp->mdio_bus->irq[i] = PHY_POLL;
1092
1093         /* The bus registration will look for all the PHYs on the mdio bus.
1094          * Unfortunately, it does not ensure the PHY is powered up before
1095          * accessing the PHY ID registers.  A chip reset is the
1096          * quickest way to bring the device back to an operational state..
1097          */
1098         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1099                 tg3_bmcr_reset(tp);
1100
1101         i = mdiobus_register(tp->mdio_bus);
1102         if (i) {
1103                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1104                 mdiobus_free(tp->mdio_bus);
1105                 return i;
1106         }
1107
1108         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1109
1110         if (!phydev || !phydev->drv) {
1111                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1112                 mdiobus_unregister(tp->mdio_bus);
1113                 mdiobus_free(tp->mdio_bus);
1114                 return -ENODEV;
1115         }
1116
1117         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1118         case PHY_ID_BCM57780:
1119                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1120                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1121                 break;
1122         case PHY_ID_BCM50610:
1123         case PHY_ID_BCM50610M:
1124                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1125                                      PHY_BRCM_RX_REFCLK_UNUSED |
1126                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1127                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1128                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1129                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1130                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1131                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1132                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1133                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1134                 /* fallthru */
1135         case PHY_ID_RTL8211C:
1136                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1137                 break;
1138         case PHY_ID_RTL8201E:
1139         case PHY_ID_BCMAC131:
1140                 phydev->interface = PHY_INTERFACE_MODE_MII;
1141                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1142                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1143                 break;
1144         }
1145
1146         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1147
1148         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1149                 tg3_mdio_config_5785(tp);
1150
1151         return 0;
1152 }
1153
1154 static void tg3_mdio_fini(struct tg3 *tp)
1155 {
1156         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1157                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1158                 mdiobus_unregister(tp->mdio_bus);
1159                 mdiobus_free(tp->mdio_bus);
1160         }
1161 }
1162
1163 /* tp->lock is held. */
1164 static inline void tg3_generate_fw_event(struct tg3 *tp)
1165 {
1166         u32 val;
1167
1168         val = tr32(GRC_RX_CPU_EVENT);
1169         val |= GRC_RX_CPU_DRIVER_EVENT;
1170         tw32_f(GRC_RX_CPU_EVENT, val);
1171
1172         tp->last_event_jiffies = jiffies;
1173 }
1174
1175 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1176
1177 /* tp->lock is held. */
1178 static void tg3_wait_for_event_ack(struct tg3 *tp)
1179 {
1180         int i;
1181         unsigned int delay_cnt;
1182         long time_remain;
1183
1184         /* If enough time has passed, no wait is necessary. */
1185         time_remain = (long)(tp->last_event_jiffies + 1 +
1186                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1187                       (long)jiffies;
1188         if (time_remain < 0)
1189                 return;
1190
1191         /* Check if we can shorten the wait time. */
1192         delay_cnt = jiffies_to_usecs(time_remain);
1193         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1194                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1195         delay_cnt = (delay_cnt >> 3) + 1;
1196
1197         for (i = 0; i < delay_cnt; i++) {
1198                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1199                         break;
1200                 udelay(8);
1201         }
1202 }
1203
1204 /* tp->lock is held. */
1205 static void tg3_ump_link_report(struct tg3 *tp)
1206 {
1207         u32 reg;
1208         u32 val;
1209
1210         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1211             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1212                 return;
1213
1214         tg3_wait_for_event_ack(tp);
1215
1216         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1217
1218         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1219
1220         val = 0;
1221         if (!tg3_readphy(tp, MII_BMCR, &reg))
1222                 val = reg << 16;
1223         if (!tg3_readphy(tp, MII_BMSR, &reg))
1224                 val |= (reg & 0xffff);
1225         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1226
1227         val = 0;
1228         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1229                 val = reg << 16;
1230         if (!tg3_readphy(tp, MII_LPA, &reg))
1231                 val |= (reg & 0xffff);
1232         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1233
1234         val = 0;
1235         if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1236                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1237                         val = reg << 16;
1238                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1239                         val |= (reg & 0xffff);
1240         }
1241         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1242
1243         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1244                 val = reg << 16;
1245         else
1246                 val = 0;
1247         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1248
1249         tg3_generate_fw_event(tp);
1250 }
1251
1252 static void tg3_link_report(struct tg3 *tp)
1253 {
1254         if (!netif_carrier_ok(tp->dev)) {
1255                 netif_info(tp, link, tp->dev, "Link is down\n");
1256                 tg3_ump_link_report(tp);
1257         } else if (netif_msg_link(tp)) {
1258                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1259                             (tp->link_config.active_speed == SPEED_1000 ?
1260                              1000 :
1261                              (tp->link_config.active_speed == SPEED_100 ?
1262                               100 : 10)),
1263                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1264                              "full" : "half"));
1265
1266                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1267                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1268                             "on" : "off",
1269                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1270                             "on" : "off");
1271                 tg3_ump_link_report(tp);
1272         }
1273 }
1274
1275 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1276 {
1277         u16 miireg;
1278
1279         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1280                 miireg = ADVERTISE_PAUSE_CAP;
1281         else if (flow_ctrl & FLOW_CTRL_TX)
1282                 miireg = ADVERTISE_PAUSE_ASYM;
1283         else if (flow_ctrl & FLOW_CTRL_RX)
1284                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1285         else
1286                 miireg = 0;
1287
1288         return miireg;
1289 }
1290
1291 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1292 {
1293         u16 miireg;
1294
1295         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1296                 miireg = ADVERTISE_1000XPAUSE;
1297         else if (flow_ctrl & FLOW_CTRL_TX)
1298                 miireg = ADVERTISE_1000XPSE_ASYM;
1299         else if (flow_ctrl & FLOW_CTRL_RX)
1300                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1301         else
1302                 miireg = 0;
1303
1304         return miireg;
1305 }
1306
1307 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1308 {
1309         u8 cap = 0;
1310
1311         if (lcladv & ADVERTISE_1000XPAUSE) {
1312                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1313                         if (rmtadv & LPA_1000XPAUSE)
1314                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1315                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1316                                 cap = FLOW_CTRL_RX;
1317                 } else {
1318                         if (rmtadv & LPA_1000XPAUSE)
1319                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1320                 }
1321         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1322                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1323                         cap = FLOW_CTRL_TX;
1324         }
1325
1326         return cap;
1327 }
1328
1329 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1330 {
1331         u8 autoneg;
1332         u8 flowctrl = 0;
1333         u32 old_rx_mode = tp->rx_mode;
1334         u32 old_tx_mode = tp->tx_mode;
1335
1336         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1337                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1338         else
1339                 autoneg = tp->link_config.autoneg;
1340
1341         if (autoneg == AUTONEG_ENABLE &&
1342             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1343                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1344                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1345                 else
1346                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1347         } else
1348                 flowctrl = tp->link_config.flowctrl;
1349
1350         tp->link_config.active_flowctrl = flowctrl;
1351
1352         if (flowctrl & FLOW_CTRL_RX)
1353                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1354         else
1355                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1356
1357         if (old_rx_mode != tp->rx_mode)
1358                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1359
1360         if (flowctrl & FLOW_CTRL_TX)
1361                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1362         else
1363                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1364
1365         if (old_tx_mode != tp->tx_mode)
1366                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1367 }
1368
1369 static void tg3_adjust_link(struct net_device *dev)
1370 {
1371         u8 oldflowctrl, linkmesg = 0;
1372         u32 mac_mode, lcl_adv, rmt_adv;
1373         struct tg3 *tp = netdev_priv(dev);
1374         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1375
1376         spin_lock_bh(&tp->lock);
1377
1378         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1379                                     MAC_MODE_HALF_DUPLEX);
1380
1381         oldflowctrl = tp->link_config.active_flowctrl;
1382
1383         if (phydev->link) {
1384                 lcl_adv = 0;
1385                 rmt_adv = 0;
1386
1387                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1388                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1389                 else if (phydev->speed == SPEED_1000 ||
1390                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1391                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1392                 else
1393                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1394
1395                 if (phydev->duplex == DUPLEX_HALF)
1396                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1397                 else {
1398                         lcl_adv = tg3_advert_flowctrl_1000T(
1399                                   tp->link_config.flowctrl);
1400
1401                         if (phydev->pause)
1402                                 rmt_adv = LPA_PAUSE_CAP;
1403                         if (phydev->asym_pause)
1404                                 rmt_adv |= LPA_PAUSE_ASYM;
1405                 }
1406
1407                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1408         } else
1409                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1410
1411         if (mac_mode != tp->mac_mode) {
1412                 tp->mac_mode = mac_mode;
1413                 tw32_f(MAC_MODE, tp->mac_mode);
1414                 udelay(40);
1415         }
1416
1417         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1418                 if (phydev->speed == SPEED_10)
1419                         tw32(MAC_MI_STAT,
1420                              MAC_MI_STAT_10MBPS_MODE |
1421                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1422                 else
1423                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1424         }
1425
1426         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1427                 tw32(MAC_TX_LENGTHS,
1428                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1429                       (6 << TX_LENGTHS_IPG_SHIFT) |
1430                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1431         else
1432                 tw32(MAC_TX_LENGTHS,
1433                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1434                       (6 << TX_LENGTHS_IPG_SHIFT) |
1435                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1436
1437         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1438             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1439             phydev->speed != tp->link_config.active_speed ||
1440             phydev->duplex != tp->link_config.active_duplex ||
1441             oldflowctrl != tp->link_config.active_flowctrl)
1442                 linkmesg = 1;
1443
1444         tp->link_config.active_speed = phydev->speed;
1445         tp->link_config.active_duplex = phydev->duplex;
1446
1447         spin_unlock_bh(&tp->lock);
1448
1449         if (linkmesg)
1450                 tg3_link_report(tp);
1451 }
1452
1453 static int tg3_phy_init(struct tg3 *tp)
1454 {
1455         struct phy_device *phydev;
1456
1457         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1458                 return 0;
1459
1460         /* Bring the PHY back to a known state. */
1461         tg3_bmcr_reset(tp);
1462
1463         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1464
1465         /* Attach the MAC to the PHY. */
1466         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1467                              phydev->dev_flags, phydev->interface);
1468         if (IS_ERR(phydev)) {
1469                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1470                 return PTR_ERR(phydev);
1471         }
1472
1473         /* Mask with MAC supported features. */
1474         switch (phydev->interface) {
1475         case PHY_INTERFACE_MODE_GMII:
1476         case PHY_INTERFACE_MODE_RGMII:
1477                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1478                         phydev->supported &= (PHY_GBIT_FEATURES |
1479                                               SUPPORTED_Pause |
1480                                               SUPPORTED_Asym_Pause);
1481                         break;
1482                 }
1483                 /* fallthru */
1484         case PHY_INTERFACE_MODE_MII:
1485                 phydev->supported &= (PHY_BASIC_FEATURES |
1486                                       SUPPORTED_Pause |
1487                                       SUPPORTED_Asym_Pause);
1488                 break;
1489         default:
1490                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1491                 return -EINVAL;
1492         }
1493
1494         tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1495
1496         phydev->advertising = phydev->supported;
1497
1498         return 0;
1499 }
1500
1501 static void tg3_phy_start(struct tg3 *tp)
1502 {
1503         struct phy_device *phydev;
1504
1505         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1506                 return;
1507
1508         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1509
1510         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1511                 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1512                 phydev->speed = tp->link_config.orig_speed;
1513                 phydev->duplex = tp->link_config.orig_duplex;
1514                 phydev->autoneg = tp->link_config.orig_autoneg;
1515                 phydev->advertising = tp->link_config.orig_advertising;
1516         }
1517
1518         phy_start(phydev);
1519
1520         phy_start_aneg(phydev);
1521 }
1522
1523 static void tg3_phy_stop(struct tg3 *tp)
1524 {
1525         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1526                 return;
1527
1528         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1529 }
1530
1531 static void tg3_phy_fini(struct tg3 *tp)
1532 {
1533         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1534                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1535                 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1536         }
1537 }
1538
1539 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1540 {
1541         int err;
1542
1543         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1544         if (!err)
1545                 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1546
1547         return err;
1548 }
1549
1550 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1551 {
1552         u32 phytest;
1553
1554         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1555                 u32 phy;
1556
1557                 tg3_writephy(tp, MII_TG3_FET_TEST,
1558                              phytest | MII_TG3_FET_SHADOW_EN);
1559                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1560                         if (enable)
1561                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1562                         else
1563                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1564                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1565                 }
1566                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1567         }
1568 }
1569
1570 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1571 {
1572         u32 reg;
1573
1574         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1575             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1576               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1577              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1578                 return;
1579
1580         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1581                 tg3_phy_fet_toggle_apd(tp, enable);
1582                 return;
1583         }
1584
1585         reg = MII_TG3_MISC_SHDW_WREN |
1586               MII_TG3_MISC_SHDW_SCR5_SEL |
1587               MII_TG3_MISC_SHDW_SCR5_LPED |
1588               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1589               MII_TG3_MISC_SHDW_SCR5_SDTL |
1590               MII_TG3_MISC_SHDW_SCR5_C125OE;
1591         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1592                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1593
1594         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1595
1596
1597         reg = MII_TG3_MISC_SHDW_WREN |
1598               MII_TG3_MISC_SHDW_APD_SEL |
1599               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1600         if (enable)
1601                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1602
1603         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1604 }
1605
1606 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1607 {
1608         u32 phy;
1609
1610         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1611             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
1612                 return;
1613
1614         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1615                 u32 ephy;
1616
1617                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1618                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1619
1620                         tg3_writephy(tp, MII_TG3_FET_TEST,
1621                                      ephy | MII_TG3_FET_SHADOW_EN);
1622                         if (!tg3_readphy(tp, reg, &phy)) {
1623                                 if (enable)
1624                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1625                                 else
1626                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1627                                 tg3_writephy(tp, reg, phy);
1628                         }
1629                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1630                 }
1631         } else {
1632                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1633                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1634                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1635                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1636                         if (enable)
1637                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1638                         else
1639                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1640                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1641                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1642                 }
1643         }
1644 }
1645
1646 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1647 {
1648         u32 val;
1649
1650         if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1651                 return;
1652
1653         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1654             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1655                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1656                              (val | (1 << 15) | (1 << 4)));
1657 }
1658
1659 static void tg3_phy_apply_otp(struct tg3 *tp)
1660 {
1661         u32 otp, phy;
1662
1663         if (!tp->phy_otp)
1664                 return;
1665
1666         otp = tp->phy_otp;
1667
1668         /* Enable SM_DSP clock and tx 6dB coding. */
1669         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1670               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1671               MII_TG3_AUXCTL_ACTL_TX_6DB;
1672         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1673
1674         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1675         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1676         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1677
1678         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1679               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1680         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1681
1682         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1683         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1684         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1685
1686         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1687         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1688
1689         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1690         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1691
1692         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1693               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1694         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1695
1696         /* Turn off SM_DSP clock. */
1697         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1698               MII_TG3_AUXCTL_ACTL_TX_6DB;
1699         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1700 }
1701
1702 static int tg3_wait_macro_done(struct tg3 *tp)
1703 {
1704         int limit = 100;
1705
1706         while (limit--) {
1707                 u32 tmp32;
1708
1709                 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1710                         if ((tmp32 & 0x1000) == 0)
1711                                 break;
1712                 }
1713         }
1714         if (limit < 0)
1715                 return -EBUSY;
1716
1717         return 0;
1718 }
1719
1720 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1721 {
1722         static const u32 test_pat[4][6] = {
1723         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1724         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1725         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1726         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1727         };
1728         int chan;
1729
1730         for (chan = 0; chan < 4; chan++) {
1731                 int i;
1732
1733                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1734                              (chan * 0x2000) | 0x0200);
1735                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1736
1737                 for (i = 0; i < 6; i++)
1738                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1739                                      test_pat[chan][i]);
1740
1741                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1742                 if (tg3_wait_macro_done(tp)) {
1743                         *resetp = 1;
1744                         return -EBUSY;
1745                 }
1746
1747                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1748                              (chan * 0x2000) | 0x0200);
1749                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1750                 if (tg3_wait_macro_done(tp)) {
1751                         *resetp = 1;
1752                         return -EBUSY;
1753                 }
1754
1755                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1756                 if (tg3_wait_macro_done(tp)) {
1757                         *resetp = 1;
1758                         return -EBUSY;
1759                 }
1760
1761                 for (i = 0; i < 6; i += 2) {
1762                         u32 low, high;
1763
1764                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1765                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1766                             tg3_wait_macro_done(tp)) {
1767                                 *resetp = 1;
1768                                 return -EBUSY;
1769                         }
1770                         low &= 0x7fff;
1771                         high &= 0x000f;
1772                         if (low != test_pat[chan][i] ||
1773                             high != test_pat[chan][i+1]) {
1774                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1775                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1776                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1777
1778                                 return -EBUSY;
1779                         }
1780                 }
1781         }
1782
1783         return 0;
1784 }
1785
1786 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1787 {
1788         int chan;
1789
1790         for (chan = 0; chan < 4; chan++) {
1791                 int i;
1792
1793                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1794                              (chan * 0x2000) | 0x0200);
1795                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1796                 for (i = 0; i < 6; i++)
1797                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1798                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1799                 if (tg3_wait_macro_done(tp))
1800                         return -EBUSY;
1801         }
1802
1803         return 0;
1804 }
1805
1806 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1807 {
1808         u32 reg32, phy9_orig;
1809         int retries, do_phy_reset, err;
1810
1811         retries = 10;
1812         do_phy_reset = 1;
1813         do {
1814                 if (do_phy_reset) {
1815                         err = tg3_bmcr_reset(tp);
1816                         if (err)
1817                                 return err;
1818                         do_phy_reset = 0;
1819                 }
1820
1821                 /* Disable transmitter and interrupt.  */
1822                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1823                         continue;
1824
1825                 reg32 |= 0x3000;
1826                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1827
1828                 /* Set full-duplex, 1000 mbps.  */
1829                 tg3_writephy(tp, MII_BMCR,
1830                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1831
1832                 /* Set to master mode.  */
1833                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1834                         continue;
1835
1836                 tg3_writephy(tp, MII_TG3_CTRL,
1837                              (MII_TG3_CTRL_AS_MASTER |
1838                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1839
1840                 /* Enable SM_DSP_CLOCK and 6dB.  */
1841                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1842
1843                 /* Block the PHY control access.  */
1844                 tg3_phydsp_write(tp, 0x8005, 0x0800);
1845
1846                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1847                 if (!err)
1848                         break;
1849         } while (--retries);
1850
1851         err = tg3_phy_reset_chanpat(tp);
1852         if (err)
1853                 return err;
1854
1855         tg3_phydsp_write(tp, 0x8005, 0x0000);
1856
1857         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1858         tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1859
1860         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1861             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1862                 /* Set Extended packet length bit for jumbo frames */
1863                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1864         } else {
1865                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1866         }
1867
1868         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1869
1870         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1871                 reg32 &= ~0x3000;
1872                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1873         } else if (!err)
1874                 err = -EBUSY;
1875
1876         return err;
1877 }
1878
1879 /* This will reset the tigon3 PHY if there is no valid
1880  * link unless the FORCE argument is non-zero.
1881  */
1882 static int tg3_phy_reset(struct tg3 *tp)
1883 {
1884         u32 val, cpmuctrl;
1885         int err;
1886
1887         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1888                 val = tr32(GRC_MISC_CFG);
1889                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1890                 udelay(40);
1891         }
1892         err  = tg3_readphy(tp, MII_BMSR, &val);
1893         err |= tg3_readphy(tp, MII_BMSR, &val);
1894         if (err != 0)
1895                 return -EBUSY;
1896
1897         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1898                 netif_carrier_off(tp->dev);
1899                 tg3_link_report(tp);
1900         }
1901
1902         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1903             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1904             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1905                 err = tg3_phy_reset_5703_4_5(tp);
1906                 if (err)
1907                         return err;
1908                 goto out;
1909         }
1910
1911         cpmuctrl = 0;
1912         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1913             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1914                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1915                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1916                         tw32(TG3_CPMU_CTRL,
1917                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1918         }
1919
1920         err = tg3_bmcr_reset(tp);
1921         if (err)
1922                 return err;
1923
1924         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1925                 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1926                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
1927
1928                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1929         }
1930
1931         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1932             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1933                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1934                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1935                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1936                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1937                         udelay(40);
1938                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1939                 }
1940         }
1941
1942         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1943              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1944             (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
1945                 return 0;
1946
1947         tg3_phy_apply_otp(tp);
1948
1949         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
1950                 tg3_phy_toggle_apd(tp, true);
1951         else
1952                 tg3_phy_toggle_apd(tp, false);
1953
1954 out:
1955         if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) {
1956                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1957                 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
1958                 tg3_phydsp_write(tp, 0x000a, 0x0323);
1959                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1960         }
1961         if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
1962                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
1963                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
1964         }
1965         if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
1966                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1967                 tg3_phydsp_write(tp, 0x000a, 0x310b);
1968                 tg3_phydsp_write(tp, 0x201f, 0x9506);
1969                 tg3_phydsp_write(tp, 0x401f, 0x14e2);
1970                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1971         } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
1972                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1973                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1974                 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
1975                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1976                         tg3_writephy(tp, MII_TG3_TEST1,
1977                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1978                 } else
1979                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1980                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1981         }
1982         /* Set Extended packet length bit (bit 14) on all chips that */
1983         /* support jumbo frames */
1984         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1985                 /* Cannot do read-modify-write on 5401 */
1986                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1987         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1988                 /* Set bit 14 with read-modify-write to preserve other bits */
1989                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1990                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1991                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val | 0x4000);
1992         }
1993
1994         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1995          * jumbo frames transmission.
1996          */
1997         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1998                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
1999                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2000                                      val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2001         }
2002
2003         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2004                 /* adjust output voltage */
2005                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2006         }
2007
2008         tg3_phy_toggle_automdix(tp, 1);
2009         tg3_phy_set_wirespeed(tp);
2010         return 0;
2011 }
2012
2013 static void tg3_frob_aux_power(struct tg3 *tp)
2014 {
2015         struct tg3 *tp_peer = tp;
2016
2017         /* The GPIOs do something completely different on 57765. */
2018         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2019             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2020             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2021                 return;
2022
2023         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2024             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2025             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2026                 struct net_device *dev_peer;
2027
2028                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2029                 /* remove_one() may have been run on the peer. */
2030                 if (!dev_peer)
2031                         tp_peer = tp;
2032                 else
2033                         tp_peer = netdev_priv(dev_peer);
2034         }
2035
2036         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2037             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2038             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2039             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2040                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2041                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2042                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2043                                     (GRC_LCLCTRL_GPIO_OE0 |
2044                                      GRC_LCLCTRL_GPIO_OE1 |
2045                                      GRC_LCLCTRL_GPIO_OE2 |
2046                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2047                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2048                                     100);
2049                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2050                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2051                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2052                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2053                                              GRC_LCLCTRL_GPIO_OE1 |
2054                                              GRC_LCLCTRL_GPIO_OE2 |
2055                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2056                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2057                                              tp->grc_local_ctrl;
2058                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2059
2060                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2061                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2062
2063                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2064                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2065                 } else {
2066                         u32 no_gpio2;
2067                         u32 grc_local_ctrl = 0;
2068
2069                         if (tp_peer != tp &&
2070                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2071                                 return;
2072
2073                         /* Workaround to prevent overdrawing Amps. */
2074                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2075                             ASIC_REV_5714) {
2076                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2077                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2078                                             grc_local_ctrl, 100);
2079                         }
2080
2081                         /* On 5753 and variants, GPIO2 cannot be used. */
2082                         no_gpio2 = tp->nic_sram_data_cfg &
2083                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2084
2085                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2086                                          GRC_LCLCTRL_GPIO_OE1 |
2087                                          GRC_LCLCTRL_GPIO_OE2 |
2088                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2089                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2090                         if (no_gpio2) {
2091                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2092                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2093                         }
2094                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2095                                                     grc_local_ctrl, 100);
2096
2097                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2098
2099                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2100                                                     grc_local_ctrl, 100);
2101
2102                         if (!no_gpio2) {
2103                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2104                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2105                                             grc_local_ctrl, 100);
2106                         }
2107                 }
2108         } else {
2109                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2110                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2111                         if (tp_peer != tp &&
2112                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2113                                 return;
2114
2115                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2116                                     (GRC_LCLCTRL_GPIO_OE1 |
2117                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2118
2119                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2120                                     GRC_LCLCTRL_GPIO_OE1, 100);
2121
2122                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2123                                     (GRC_LCLCTRL_GPIO_OE1 |
2124                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2125                 }
2126         }
2127 }
2128
2129 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2130 {
2131         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2132                 return 1;
2133         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2134                 if (speed != SPEED_10)
2135                         return 1;
2136         } else if (speed == SPEED_10)
2137                 return 1;
2138
2139         return 0;
2140 }
2141
2142 static int tg3_setup_phy(struct tg3 *, int);
2143
2144 #define RESET_KIND_SHUTDOWN     0
2145 #define RESET_KIND_INIT         1
2146 #define RESET_KIND_SUSPEND      2
2147
2148 static void tg3_write_sig_post_reset(struct tg3 *, int);
2149 static int tg3_halt_cpu(struct tg3 *, u32);
2150
2151 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2152 {
2153         u32 val;
2154
2155         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2156                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2157                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2158                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2159
2160                         sg_dig_ctrl |=
2161                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2162                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2163                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2164                 }
2165                 return;
2166         }
2167
2168         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2169                 tg3_bmcr_reset(tp);
2170                 val = tr32(GRC_MISC_CFG);
2171                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2172                 udelay(40);
2173                 return;
2174         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2175                 u32 phytest;
2176                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2177                         u32 phy;
2178
2179                         tg3_writephy(tp, MII_ADVERTISE, 0);
2180                         tg3_writephy(tp, MII_BMCR,
2181                                      BMCR_ANENABLE | BMCR_ANRESTART);
2182
2183                         tg3_writephy(tp, MII_TG3_FET_TEST,
2184                                      phytest | MII_TG3_FET_SHADOW_EN);
2185                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2186                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2187                                 tg3_writephy(tp,
2188                                              MII_TG3_FET_SHDW_AUXMODE4,
2189                                              phy);
2190                         }
2191                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2192                 }
2193                 return;
2194         } else if (do_low_power) {
2195                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2196                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2197
2198                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2199                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2200                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2201                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2202                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2203         }
2204
2205         /* The PHY should not be powered down on some chips because
2206          * of bugs.
2207          */
2208         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2209             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2210             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2211              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2212                 return;
2213
2214         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2215             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2216                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2217                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2218                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2219                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2220         }
2221
2222         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2223 }
2224
2225 /* tp->lock is held. */
2226 static int tg3_nvram_lock(struct tg3 *tp)
2227 {
2228         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2229                 int i;
2230
2231                 if (tp->nvram_lock_cnt == 0) {
2232                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2233                         for (i = 0; i < 8000; i++) {
2234                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2235                                         break;
2236                                 udelay(20);
2237                         }
2238                         if (i == 8000) {
2239                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2240                                 return -ENODEV;
2241                         }
2242                 }
2243                 tp->nvram_lock_cnt++;
2244         }
2245         return 0;
2246 }
2247
2248 /* tp->lock is held. */
2249 static void tg3_nvram_unlock(struct tg3 *tp)
2250 {
2251         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2252                 if (tp->nvram_lock_cnt > 0)
2253                         tp->nvram_lock_cnt--;
2254                 if (tp->nvram_lock_cnt == 0)
2255                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2256         }
2257 }
2258
2259 /* tp->lock is held. */
2260 static void tg3_enable_nvram_access(struct tg3 *tp)
2261 {
2262         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2263             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2264                 u32 nvaccess = tr32(NVRAM_ACCESS);
2265
2266                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2267         }
2268 }
2269
2270 /* tp->lock is held. */
2271 static void tg3_disable_nvram_access(struct tg3 *tp)
2272 {
2273         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2274             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2275                 u32 nvaccess = tr32(NVRAM_ACCESS);
2276
2277                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2278         }
2279 }
2280
2281 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2282                                         u32 offset, u32 *val)
2283 {
2284         u32 tmp;
2285         int i;
2286
2287         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2288                 return -EINVAL;
2289
2290         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2291                                         EEPROM_ADDR_DEVID_MASK |
2292                                         EEPROM_ADDR_READ);
2293         tw32(GRC_EEPROM_ADDR,
2294              tmp |
2295              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2296              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2297               EEPROM_ADDR_ADDR_MASK) |
2298              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2299
2300         for (i = 0; i < 1000; i++) {
2301                 tmp = tr32(GRC_EEPROM_ADDR);
2302
2303                 if (tmp & EEPROM_ADDR_COMPLETE)
2304                         break;
2305                 msleep(1);
2306         }
2307         if (!(tmp & EEPROM_ADDR_COMPLETE))
2308                 return -EBUSY;
2309
2310         tmp = tr32(GRC_EEPROM_DATA);
2311
2312         /*
2313          * The data will always be opposite the native endian
2314          * format.  Perform a blind byteswap to compensate.
2315          */
2316         *val = swab32(tmp);
2317
2318         return 0;
2319 }
2320
2321 #define NVRAM_CMD_TIMEOUT 10000
2322
2323 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2324 {
2325         int i;
2326
2327         tw32(NVRAM_CMD, nvram_cmd);
2328         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2329                 udelay(10);
2330                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2331                         udelay(10);
2332                         break;
2333                 }
2334         }
2335
2336         if (i == NVRAM_CMD_TIMEOUT)
2337                 return -EBUSY;
2338
2339         return 0;
2340 }
2341
2342 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2343 {
2344         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2345             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2346             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2347            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2348             (tp->nvram_jedecnum == JEDEC_ATMEL))
2349
2350                 addr = ((addr / tp->nvram_pagesize) <<
2351                         ATMEL_AT45DB0X1B_PAGE_POS) +
2352                        (addr % tp->nvram_pagesize);
2353
2354         return addr;
2355 }
2356
2357 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2358 {
2359         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2360             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2361             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2362            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2363             (tp->nvram_jedecnum == JEDEC_ATMEL))
2364
2365                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2366                         tp->nvram_pagesize) +
2367                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2368
2369         return addr;
2370 }
2371
2372 /* NOTE: Data read in from NVRAM is byteswapped according to
2373  * the byteswapping settings for all other register accesses.
2374  * tg3 devices are BE devices, so on a BE machine, the data
2375  * returned will be exactly as it is seen in NVRAM.  On a LE
2376  * machine, the 32-bit value will be byteswapped.
2377  */
2378 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2379 {
2380         int ret;
2381
2382         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2383                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2384
2385         offset = tg3_nvram_phys_addr(tp, offset);
2386
2387         if (offset > NVRAM_ADDR_MSK)
2388                 return -EINVAL;
2389
2390         ret = tg3_nvram_lock(tp);
2391         if (ret)
2392                 return ret;
2393
2394         tg3_enable_nvram_access(tp);
2395
2396         tw32(NVRAM_ADDR, offset);
2397         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2398                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2399
2400         if (ret == 0)
2401                 *val = tr32(NVRAM_RDDATA);
2402
2403         tg3_disable_nvram_access(tp);
2404
2405         tg3_nvram_unlock(tp);
2406
2407         return ret;
2408 }
2409
2410 /* Ensures NVRAM data is in bytestream format. */
2411 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2412 {
2413         u32 v;
2414         int res = tg3_nvram_read(tp, offset, &v);
2415         if (!res)
2416                 *val = cpu_to_be32(v);
2417         return res;
2418 }
2419
2420 /* tp->lock is held. */
2421 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2422 {
2423         u32 addr_high, addr_low;
2424         int i;
2425
2426         addr_high = ((tp->dev->dev_addr[0] << 8) |
2427                      tp->dev->dev_addr[1]);
2428         addr_low = ((tp->dev->dev_addr[2] << 24) |
2429                     (tp->dev->dev_addr[3] << 16) |
2430                     (tp->dev->dev_addr[4] <<  8) |
2431                     (tp->dev->dev_addr[5] <<  0));
2432         for (i = 0; i < 4; i++) {
2433                 if (i == 1 && skip_mac_1)
2434                         continue;
2435                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2436                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2437         }
2438
2439         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2440             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2441                 for (i = 0; i < 12; i++) {
2442                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2443                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2444                 }
2445         }
2446
2447         addr_high = (tp->dev->dev_addr[0] +
2448                      tp->dev->dev_addr[1] +
2449                      tp->dev->dev_addr[2] +
2450                      tp->dev->dev_addr[3] +
2451                      tp->dev->dev_addr[4] +
2452                      tp->dev->dev_addr[5]) &
2453                 TX_BACKOFF_SEED_MASK;
2454         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2455 }
2456
2457 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2458 {
2459         u32 misc_host_ctrl;
2460         bool device_should_wake, do_low_power;
2461
2462         /* Make sure register accesses (indirect or otherwise)
2463          * will function correctly.
2464          */
2465         pci_write_config_dword(tp->pdev,
2466                                TG3PCI_MISC_HOST_CTRL,
2467                                tp->misc_host_ctrl);
2468
2469         switch (state) {
2470         case PCI_D0:
2471                 pci_enable_wake(tp->pdev, state, false);
2472                 pci_set_power_state(tp->pdev, PCI_D0);
2473
2474                 /* Switch out of Vaux if it is a NIC */
2475                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2476                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2477
2478                 return 0;
2479
2480         case PCI_D1:
2481         case PCI_D2:
2482         case PCI_D3hot:
2483                 break;
2484
2485         default:
2486                 netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
2487                            state);
2488                 return -EINVAL;
2489         }
2490
2491         /* Restore the CLKREQ setting. */
2492         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2493                 u16 lnkctl;
2494
2495                 pci_read_config_word(tp->pdev,
2496                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2497                                      &lnkctl);
2498                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2499                 pci_write_config_word(tp->pdev,
2500                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2501                                       lnkctl);
2502         }
2503
2504         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2505         tw32(TG3PCI_MISC_HOST_CTRL,
2506              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2507
2508         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2509                              device_may_wakeup(&tp->pdev->dev) &&
2510                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2511
2512         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2513                 do_low_power = false;
2514                 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
2515                     !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2516                         struct phy_device *phydev;
2517                         u32 phyid, advertising;
2518
2519                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2520
2521                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2522
2523                         tp->link_config.orig_speed = phydev->speed;
2524                         tp->link_config.orig_duplex = phydev->duplex;
2525                         tp->link_config.orig_autoneg = phydev->autoneg;
2526                         tp->link_config.orig_advertising = phydev->advertising;
2527
2528                         advertising = ADVERTISED_TP |
2529                                       ADVERTISED_Pause |
2530                                       ADVERTISED_Autoneg |
2531                                       ADVERTISED_10baseT_Half;
2532
2533                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2534                             device_should_wake) {
2535                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2536                                         advertising |=
2537                                                 ADVERTISED_100baseT_Half |
2538                                                 ADVERTISED_100baseT_Full |
2539                                                 ADVERTISED_10baseT_Full;
2540                                 else
2541                                         advertising |= ADVERTISED_10baseT_Full;
2542                         }
2543
2544                         phydev->advertising = advertising;
2545
2546                         phy_start_aneg(phydev);
2547
2548                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2549                         if (phyid != PHY_ID_BCMAC131) {
2550                                 phyid &= PHY_BCM_OUI_MASK;
2551                                 if (phyid == PHY_BCM_OUI_1 ||
2552                                     phyid == PHY_BCM_OUI_2 ||
2553                                     phyid == PHY_BCM_OUI_3)
2554                                         do_low_power = true;
2555                         }
2556                 }
2557         } else {
2558                 do_low_power = true;
2559
2560                 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2561                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2562                         tp->link_config.orig_speed = tp->link_config.speed;
2563                         tp->link_config.orig_duplex = tp->link_config.duplex;
2564                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2565                 }
2566
2567                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
2568                         tp->link_config.speed = SPEED_10;
2569                         tp->link_config.duplex = DUPLEX_HALF;
2570                         tp->link_config.autoneg = AUTONEG_ENABLE;
2571                         tg3_setup_phy(tp, 0);
2572                 }
2573         }
2574
2575         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2576                 u32 val;
2577
2578                 val = tr32(GRC_VCPU_EXT_CTRL);
2579                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2580         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2581                 int i;
2582                 u32 val;
2583
2584                 for (i = 0; i < 200; i++) {
2585                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2586                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2587                                 break;
2588                         msleep(1);
2589                 }
2590         }
2591         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2592                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2593                                                      WOL_DRV_STATE_SHUTDOWN |
2594                                                      WOL_DRV_WOL |
2595                                                      WOL_SET_MAGIC_PKT);
2596
2597         if (device_should_wake) {
2598                 u32 mac_mode;
2599
2600                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
2601                         if (do_low_power) {
2602                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2603                                 udelay(40);
2604                         }
2605
2606                         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
2607                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2608                         else
2609                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2610
2611                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2612                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2613                             ASIC_REV_5700) {
2614                                 u32 speed = (tp->tg3_flags &
2615                                              TG3_FLAG_WOL_SPEED_100MB) ?
2616                                              SPEED_100 : SPEED_10;
2617                                 if (tg3_5700_link_polarity(tp, speed))
2618                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2619                                 else
2620                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2621                         }
2622                 } else {
2623                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2624                 }
2625
2626                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2627                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2628
2629                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2630                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2631                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2632                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2633                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2634                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2635
2636                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2637                         mac_mode |= tp->mac_mode &
2638                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2639                         if (mac_mode & MAC_MODE_APE_TX_EN)
2640                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2641                 }
2642
2643                 tw32_f(MAC_MODE, mac_mode);
2644                 udelay(100);
2645
2646                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2647                 udelay(10);
2648         }
2649
2650         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2651             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2652              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2653                 u32 base_val;
2654
2655                 base_val = tp->pci_clock_ctrl;
2656                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2657                              CLOCK_CTRL_TXCLK_DISABLE);
2658
2659                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2660                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2661         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2662                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2663                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2664                 /* do nothing */
2665         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2666                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2667                 u32 newbits1, newbits2;
2668
2669                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2670                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2671                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2672                                     CLOCK_CTRL_TXCLK_DISABLE |
2673                                     CLOCK_CTRL_ALTCLK);
2674                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2675                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2676                         newbits1 = CLOCK_CTRL_625_CORE;
2677                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2678                 } else {
2679                         newbits1 = CLOCK_CTRL_ALTCLK;
2680                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2681                 }
2682
2683                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2684                             40);
2685
2686                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2687                             40);
2688
2689                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2690                         u32 newbits3;
2691
2692                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2693                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2694                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2695                                             CLOCK_CTRL_TXCLK_DISABLE |
2696                                             CLOCK_CTRL_44MHZ_CORE);
2697                         } else {
2698                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2699                         }
2700
2701                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2702                                     tp->pci_clock_ctrl | newbits3, 40);
2703                 }
2704         }
2705
2706         if (!(device_should_wake) &&
2707             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2708                 tg3_power_down_phy(tp, do_low_power);
2709
2710         tg3_frob_aux_power(tp);
2711
2712         /* Workaround for unstable PLL clock */
2713         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2714             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2715                 u32 val = tr32(0x7d00);
2716
2717                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2718                 tw32(0x7d00, val);
2719                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2720                         int err;
2721
2722                         err = tg3_nvram_lock(tp);
2723                         tg3_halt_cpu(tp, RX_CPU_BASE);
2724                         if (!err)
2725                                 tg3_nvram_unlock(tp);
2726                 }
2727         }
2728
2729         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2730
2731         if (device_should_wake)
2732                 pci_enable_wake(tp->pdev, state, true);
2733
2734         /* Finally, set the new power state. */
2735         pci_set_power_state(tp->pdev, state);
2736
2737         return 0;
2738 }
2739
2740 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2741 {
2742         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2743         case MII_TG3_AUX_STAT_10HALF:
2744                 *speed = SPEED_10;
2745                 *duplex = DUPLEX_HALF;
2746                 break;
2747
2748         case MII_TG3_AUX_STAT_10FULL:
2749                 *speed = SPEED_10;
2750                 *duplex = DUPLEX_FULL;
2751                 break;
2752
2753         case MII_TG3_AUX_STAT_100HALF:
2754                 *speed = SPEED_100;
2755                 *duplex = DUPLEX_HALF;
2756                 break;
2757
2758         case MII_TG3_AUX_STAT_100FULL:
2759                 *speed = SPEED_100;
2760                 *duplex = DUPLEX_FULL;
2761                 break;
2762
2763         case MII_TG3_AUX_STAT_1000HALF:
2764                 *speed = SPEED_1000;
2765                 *duplex = DUPLEX_HALF;
2766                 break;
2767
2768         case MII_TG3_AUX_STAT_1000FULL:
2769                 *speed = SPEED_1000;
2770                 *duplex = DUPLEX_FULL;
2771                 break;
2772
2773         default:
2774                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2775                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2776                                  SPEED_10;
2777                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2778                                   DUPLEX_HALF;
2779                         break;
2780                 }
2781                 *speed = SPEED_INVALID;
2782                 *duplex = DUPLEX_INVALID;
2783                 break;
2784         }
2785 }
2786
2787 static void tg3_phy_copper_begin(struct tg3 *tp)
2788 {
2789         u32 new_adv;
2790         int i;
2791
2792         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2793                 /* Entering low power mode.  Disable gigabit and
2794                  * 100baseT advertisements.
2795                  */
2796                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2797
2798                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2799                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2800                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2801                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2802
2803                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2804         } else if (tp->link_config.speed == SPEED_INVALID) {
2805                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
2806                         tp->link_config.advertising &=
2807                                 ~(ADVERTISED_1000baseT_Half |
2808                                   ADVERTISED_1000baseT_Full);
2809
2810                 new_adv = ADVERTISE_CSMA;
2811                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2812                         new_adv |= ADVERTISE_10HALF;
2813                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2814                         new_adv |= ADVERTISE_10FULL;
2815                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2816                         new_adv |= ADVERTISE_100HALF;
2817                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2818                         new_adv |= ADVERTISE_100FULL;
2819
2820                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2821
2822                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2823
2824                 if (tp->link_config.advertising &
2825                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2826                         new_adv = 0;
2827                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2828                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2829                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2830                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2831                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) &&
2832                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2833                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2834                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2835                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2836                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2837                 } else {
2838                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2839                 }
2840         } else {
2841                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2842                 new_adv |= ADVERTISE_CSMA;
2843
2844                 /* Asking for a specific link mode. */
2845                 if (tp->link_config.speed == SPEED_1000) {
2846                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2847
2848                         if (tp->link_config.duplex == DUPLEX_FULL)
2849                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2850                         else
2851                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2852                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2853                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2854                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2855                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2856                 } else {
2857                         if (tp->link_config.speed == SPEED_100) {
2858                                 if (tp->link_config.duplex == DUPLEX_FULL)
2859                                         new_adv |= ADVERTISE_100FULL;
2860                                 else
2861                                         new_adv |= ADVERTISE_100HALF;
2862                         } else {
2863                                 if (tp->link_config.duplex == DUPLEX_FULL)
2864                                         new_adv |= ADVERTISE_10FULL;
2865                                 else
2866                                         new_adv |= ADVERTISE_10HALF;
2867                         }
2868                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2869
2870                         new_adv = 0;
2871                 }
2872
2873                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2874         }
2875
2876         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2877             tp->link_config.speed != SPEED_INVALID) {
2878                 u32 bmcr, orig_bmcr;
2879
2880                 tp->link_config.active_speed = tp->link_config.speed;
2881                 tp->link_config.active_duplex = tp->link_config.duplex;
2882
2883                 bmcr = 0;
2884                 switch (tp->link_config.speed) {
2885                 default:
2886                 case SPEED_10:
2887                         break;
2888
2889                 case SPEED_100:
2890                         bmcr |= BMCR_SPEED100;
2891                         break;
2892
2893                 case SPEED_1000:
2894                         bmcr |= TG3_BMCR_SPEED1000;
2895                         break;
2896                 }
2897
2898                 if (tp->link_config.duplex == DUPLEX_FULL)
2899                         bmcr |= BMCR_FULLDPLX;
2900
2901                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2902                     (bmcr != orig_bmcr)) {
2903                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2904                         for (i = 0; i < 1500; i++) {
2905                                 u32 tmp;
2906
2907                                 udelay(10);
2908                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2909                                     tg3_readphy(tp, MII_BMSR, &tmp))
2910                                         continue;
2911                                 if (!(tmp & BMSR_LSTATUS)) {
2912                                         udelay(40);
2913                                         break;
2914                                 }
2915                         }
2916                         tg3_writephy(tp, MII_BMCR, bmcr);
2917                         udelay(40);
2918                 }
2919         } else {
2920                 tg3_writephy(tp, MII_BMCR,
2921                              BMCR_ANENABLE | BMCR_ANRESTART);
2922         }
2923 }
2924
2925 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2926 {
2927         int err;
2928
2929         /* Turn off tap power management. */
2930         /* Set Extended packet length bit */
2931         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2932
2933         err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
2934         err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
2935         err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
2936         err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
2937         err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
2938
2939         udelay(40);
2940
2941         return err;
2942 }
2943
2944 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2945 {
2946         u32 adv_reg, all_mask = 0;
2947
2948         if (mask & ADVERTISED_10baseT_Half)
2949                 all_mask |= ADVERTISE_10HALF;
2950         if (mask & ADVERTISED_10baseT_Full)
2951                 all_mask |= ADVERTISE_10FULL;
2952         if (mask & ADVERTISED_100baseT_Half)
2953                 all_mask |= ADVERTISE_100HALF;
2954         if (mask & ADVERTISED_100baseT_Full)
2955                 all_mask |= ADVERTISE_100FULL;
2956
2957         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2958                 return 0;
2959
2960         if ((adv_reg & all_mask) != all_mask)
2961                 return 0;
2962         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
2963                 u32 tg3_ctrl;
2964
2965                 all_mask = 0;
2966                 if (mask & ADVERTISED_1000baseT_Half)
2967                         all_mask |= ADVERTISE_1000HALF;
2968                 if (mask & ADVERTISED_1000baseT_Full)
2969                         all_mask |= ADVERTISE_1000FULL;
2970
2971                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2972                         return 0;
2973
2974                 if ((tg3_ctrl & all_mask) != all_mask)
2975                         return 0;
2976         }
2977         return 1;
2978 }
2979
2980 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2981 {
2982         u32 curadv, reqadv;
2983
2984         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2985                 return 1;
2986
2987         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2988         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2989
2990         if (tp->link_config.active_duplex == DUPLEX_FULL) {
2991                 if (curadv != reqadv)
2992                         return 0;
2993
2994                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2995                         tg3_readphy(tp, MII_LPA, rmtadv);
2996         } else {
2997                 /* Reprogram the advertisement register, even if it
2998                  * does not affect the current link.  If the link
2999                  * gets renegotiated in the future, we can save an
3000                  * additional renegotiation cycle by advertising
3001                  * it correctly in the first place.
3002                  */
3003                 if (curadv != reqadv) {
3004                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3005                                      ADVERTISE_PAUSE_ASYM);
3006                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3007                 }
3008         }
3009
3010         return 1;
3011 }
3012
3013 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3014 {
3015         int current_link_up;
3016         u32 bmsr, val;
3017         u32 lcl_adv, rmt_adv;
3018         u16 current_speed;
3019         u8 current_duplex;
3020         int i, err;
3021
3022         tw32(MAC_EVENT, 0);
3023
3024         tw32_f(MAC_STATUS,
3025              (MAC_STATUS_SYNC_CHANGED |
3026               MAC_STATUS_CFG_CHANGED |
3027               MAC_STATUS_MI_COMPLETION |
3028               MAC_STATUS_LNKSTATE_CHANGED));
3029         udelay(40);
3030
3031         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3032                 tw32_f(MAC_MI_MODE,
3033                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3034                 udelay(80);
3035         }
3036
3037         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3038
3039         /* Some third-party PHYs need to be reset on link going
3040          * down.
3041          */
3042         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3043              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3044              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3045             netif_carrier_ok(tp->dev)) {
3046                 tg3_readphy(tp, MII_BMSR, &bmsr);
3047                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3048                     !(bmsr & BMSR_LSTATUS))
3049                         force_reset = 1;
3050         }
3051         if (force_reset)
3052                 tg3_phy_reset(tp);
3053
3054         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3055                 tg3_readphy(tp, MII_BMSR, &bmsr);
3056                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3057                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3058                         bmsr = 0;
3059
3060                 if (!(bmsr & BMSR_LSTATUS)) {
3061                         err = tg3_init_5401phy_dsp(tp);
3062                         if (err)
3063                                 return err;
3064
3065                         tg3_readphy(tp, MII_BMSR, &bmsr);
3066                         for (i = 0; i < 1000; i++) {
3067                                 udelay(10);
3068                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3069                                     (bmsr & BMSR_LSTATUS)) {
3070                                         udelay(40);
3071                                         break;
3072                                 }
3073                         }
3074
3075                         if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3076                             TG3_PHY_REV_BCM5401_B0 &&
3077                             !(bmsr & BMSR_LSTATUS) &&
3078                             tp->link_config.active_speed == SPEED_1000) {
3079                                 err = tg3_phy_reset(tp);
3080                                 if (!err)
3081                                         err = tg3_init_5401phy_dsp(tp);
3082                                 if (err)
3083                                         return err;
3084                         }
3085                 }
3086         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3087                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3088                 /* 5701 {A0,B0} CRC bug workaround */
3089                 tg3_writephy(tp, 0x15, 0x0a75);
3090                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3091                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3092                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3093         }
3094
3095         /* Clear pending interrupts... */
3096         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3097         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3098
3099         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3100                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3101         else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3102                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3103
3104         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3105             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3106                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3107                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3108                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3109                 else
3110                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3111         }
3112
3113         current_link_up = 0;
3114         current_speed = SPEED_INVALID;
3115         current_duplex = DUPLEX_INVALID;
3116
3117         if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3118                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3119                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3120                 if (!(val & (1 << 10))) {
3121                         val |= (1 << 10);
3122                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3123                         goto relink;
3124                 }
3125         }
3126
3127         bmsr = 0;
3128         for (i = 0; i < 100; i++) {
3129                 tg3_readphy(tp, MII_BMSR, &bmsr);
3130                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3131                     (bmsr & BMSR_LSTATUS))
3132                         break;
3133                 udelay(40);
3134         }
3135
3136         if (bmsr & BMSR_LSTATUS) {
3137                 u32 aux_stat, bmcr;
3138
3139                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3140                 for (i = 0; i < 2000; i++) {
3141                         udelay(10);
3142                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3143                             aux_stat)
3144                                 break;
3145                 }
3146
3147                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3148                                              &current_speed,
3149                                              &current_duplex);
3150
3151                 bmcr = 0;
3152                 for (i = 0; i < 200; i++) {
3153                         tg3_readphy(tp, MII_BMCR, &bmcr);
3154                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3155                                 continue;
3156                         if (bmcr && bmcr != 0x7fff)
3157                                 break;
3158                         udelay(10);
3159                 }
3160
3161                 lcl_adv = 0;
3162                 rmt_adv = 0;
3163
3164                 tp->link_config.active_speed = current_speed;
3165                 tp->link_config.active_duplex = current_duplex;
3166
3167                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3168                         if ((bmcr & BMCR_ANENABLE) &&
3169                             tg3_copper_is_advertising_all(tp,
3170                                                 tp->link_config.advertising)) {
3171                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3172                                                                   &rmt_adv))
3173                                         current_link_up = 1;
3174                         }
3175                 } else {
3176                         if (!(bmcr & BMCR_ANENABLE) &&
3177                             tp->link_config.speed == current_speed &&
3178                             tp->link_config.duplex == current_duplex &&
3179                             tp->link_config.flowctrl ==
3180                             tp->link_config.active_flowctrl) {
3181                                 current_link_up = 1;
3182                         }
3183                 }
3184
3185                 if (current_link_up == 1 &&
3186                     tp->link_config.active_duplex == DUPLEX_FULL)
3187                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3188         }
3189
3190 relink:
3191         if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3192                 tg3_phy_copper_begin(tp);
3193
3194                 tg3_readphy(tp, MII_BMSR, &bmsr);
3195                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3196                     (bmsr & BMSR_LSTATUS))
3197                         current_link_up = 1;
3198         }
3199
3200         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3201         if (current_link_up == 1) {
3202                 if (tp->link_config.active_speed == SPEED_100 ||
3203                     tp->link_config.active_speed == SPEED_10)
3204                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3205                 else
3206                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3207         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
3208                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3209         else
3210                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3211
3212         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3213         if (tp->link_config.active_duplex == DUPLEX_HALF)
3214                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3215
3216         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3217                 if (current_link_up == 1 &&
3218                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3219                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3220                 else
3221                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3222         }
3223
3224         /* ??? Without this setting Netgear GA302T PHY does not
3225          * ??? send/receive packets...
3226          */
3227         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3228             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3229                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3230                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3231                 udelay(80);
3232         }
3233
3234         tw32_f(MAC_MODE, tp->mac_mode);
3235         udelay(40);
3236
3237         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3238                 /* Polled via timer. */
3239                 tw32_f(MAC_EVENT, 0);
3240         } else {
3241                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3242         }
3243         udelay(40);
3244
3245         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3246             current_link_up == 1 &&
3247             tp->link_config.active_speed == SPEED_1000 &&
3248             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3249              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3250                 udelay(120);
3251                 tw32_f(MAC_STATUS,
3252                      (MAC_STATUS_SYNC_CHANGED |
3253                       MAC_STATUS_CFG_CHANGED));
3254                 udelay(40);
3255                 tg3_write_mem(tp,
3256                               NIC_SRAM_FIRMWARE_MBOX,
3257                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3258         }
3259
3260         /* Prevent send BD corruption. */
3261         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3262                 u16 oldlnkctl, newlnkctl;
3263
3264                 pci_read_config_word(tp->pdev,
3265                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3266                                      &oldlnkctl);
3267                 if (tp->link_config.active_speed == SPEED_100 ||
3268                     tp->link_config.active_speed == SPEED_10)
3269                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3270                 else
3271                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3272                 if (newlnkctl != oldlnkctl)
3273                         pci_write_config_word(tp->pdev,
3274                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3275                                               newlnkctl);
3276         }
3277
3278         if (current_link_up != netif_carrier_ok(tp->dev)) {
3279                 if (current_link_up)
3280                         netif_carrier_on(tp->dev);
3281                 else
3282                         netif_carrier_off(tp->dev);
3283                 tg3_link_report(tp);
3284         }
3285
3286         return 0;
3287 }
3288
3289 struct tg3_fiber_aneginfo {
3290         int state;
3291 #define ANEG_STATE_UNKNOWN              0
3292 #define ANEG_STATE_AN_ENABLE            1
3293 #define ANEG_STATE_RESTART_INIT         2
3294 #define ANEG_STATE_RESTART              3
3295 #define ANEG_STATE_DISABLE_LINK_OK      4
3296 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3297 #define ANEG_STATE_ABILITY_DETECT       6
3298 #define ANEG_STATE_ACK_DETECT_INIT      7
3299 #define ANEG_STATE_ACK_DETECT           8
3300 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3301 #define ANEG_STATE_COMPLETE_ACK         10
3302 #define ANEG_STATE_IDLE_DETECT_INIT     11
3303 #define ANEG_STATE_IDLE_DETECT          12
3304 #define ANEG_STATE_LINK_OK              13
3305 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3306 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3307
3308         u32 flags;
3309 #define MR_AN_ENABLE            0x00000001
3310 #define MR_RESTART_AN           0x00000002
3311 #define MR_AN_COMPLETE          0x00000004
3312 #define MR_PAGE_RX              0x00000008
3313 #define MR_NP_LOADED            0x00000010
3314 #define MR_TOGGLE_TX            0x00000020
3315 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3316 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3317 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3318 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3319 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3320 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3321 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3322 #define MR_TOGGLE_RX            0x00002000
3323 #define MR_NP_RX                0x00004000
3324
3325 #define MR_LINK_OK              0x80000000
3326
3327         unsigned long link_time, cur_time;
3328
3329         u32 ability_match_cfg;
3330         int ability_match_count;
3331
3332         char ability_match, idle_match, ack_match;
3333
3334         u32 txconfig, rxconfig;
3335 #define ANEG_CFG_NP             0x00000080
3336 #define ANEG_CFG_ACK            0x00000040
3337 #define ANEG_CFG_RF2            0x00000020
3338 #define ANEG_CFG_RF1            0x00000010
3339 #define ANEG_CFG_PS2            0x00000001
3340 #define ANEG_CFG_PS1            0x00008000
3341 #define ANEG_CFG_HD             0x00004000
3342 #define ANEG_CFG_FD             0x00002000
3343 #define ANEG_CFG_INVAL          0x00001f06
3344
3345 };
3346 #define ANEG_OK         0
3347 #define ANEG_DONE       1
3348 #define ANEG_TIMER_ENAB 2
3349 #define ANEG_FAILED     -1
3350
3351 #define ANEG_STATE_SETTLE_TIME  10000
3352
3353 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3354                                    struct tg3_fiber_aneginfo *ap)
3355 {
3356         u16 flowctrl;
3357         unsigned long delta;
3358         u32 rx_cfg_reg;
3359         int ret;
3360
3361         if (ap->state == ANEG_STATE_UNKNOWN) {
3362                 ap->rxconfig = 0;
3363                 ap->link_time = 0;
3364                 ap->cur_time = 0;
3365                 ap->ability_match_cfg = 0;
3366                 ap->ability_match_count = 0;
3367                 ap->ability_match = 0;
3368                 ap->idle_match = 0;
3369                 ap->ack_match = 0;
3370         }
3371         ap->cur_time++;
3372
3373         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3374                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3375
3376                 if (rx_cfg_reg != ap->ability_match_cfg) {
3377                         ap->ability_match_cfg = rx_cfg_reg;
3378                         ap->ability_match = 0;
3379                         ap->ability_match_count = 0;
3380                 } else {
3381                         if (++ap->ability_match_count > 1) {
3382                                 ap->ability_match = 1;
3383                                 ap->ability_match_cfg = rx_cfg_reg;
3384                         }
3385                 }
3386                 if (rx_cfg_reg & ANEG_CFG_ACK)
3387                         ap->ack_match = 1;
3388                 else
3389                         ap->ack_match = 0;
3390
3391                 ap->idle_match = 0;
3392         } else {
3393                 ap->idle_match = 1;
3394                 ap->ability_match_cfg = 0;
3395                 ap->ability_match_count = 0;
3396                 ap->ability_match = 0;
3397                 ap->ack_match = 0;
3398
3399                 rx_cfg_reg = 0;
3400         }
3401
3402         ap->rxconfig = rx_cfg_reg;
3403         ret = ANEG_OK;
3404
3405         switch (ap->state) {
3406         case ANEG_STATE_UNKNOWN:
3407                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3408                         ap->state = ANEG_STATE_AN_ENABLE;
3409
3410                 /* fallthru */
3411         case ANEG_STATE_AN_ENABLE:
3412                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3413                 if (ap->flags & MR_AN_ENABLE) {
3414                         ap->link_time = 0;
3415                         ap->cur_time = 0;
3416                         ap->ability_match_cfg = 0;
3417                         ap->ability_match_count = 0;
3418                         ap->ability_match = 0;
3419                         ap->idle_match = 0;
3420                         ap->ack_match = 0;
3421
3422                         ap->state = ANEG_STATE_RESTART_INIT;
3423                 } else {
3424                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3425                 }
3426                 break;
3427
3428         case ANEG_STATE_RESTART_INIT:
3429                 ap->link_time = ap->cur_time;
3430                 ap->flags &= ~(MR_NP_LOADED);
3431                 ap->txconfig = 0;
3432                 tw32(MAC_TX_AUTO_NEG, 0);
3433                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3434                 tw32_f(MAC_MODE, tp->mac_mode);
3435                 udelay(40);
3436
3437                 ret = ANEG_TIMER_ENAB;
3438                 ap->state = ANEG_STATE_RESTART;
3439
3440                 /* fallthru */
3441         case ANEG_STATE_RESTART:
3442                 delta = ap->cur_time - ap->link_time;
3443                 if (delta > ANEG_STATE_SETTLE_TIME)
3444                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3445                 else
3446                         ret = ANEG_TIMER_ENAB;
3447                 break;
3448
3449         case ANEG_STATE_DISABLE_LINK_OK:
3450                 ret = ANEG_DONE;
3451                 break;
3452
3453         case ANEG_STATE_ABILITY_DETECT_INIT:
3454                 ap->flags &= ~(MR_TOGGLE_TX);
3455                 ap->txconfig = ANEG_CFG_FD;
3456                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3457                 if (flowctrl & ADVERTISE_1000XPAUSE)
3458                         ap->txconfig |= ANEG_CFG_PS1;
3459                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3460                         ap->txconfig |= ANEG_CFG_PS2;
3461                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3462                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3463                 tw32_f(MAC_MODE, tp->mac_mode);
3464                 udelay(40);
3465
3466                 ap->state = ANEG_STATE_ABILITY_DETECT;
3467                 break;
3468
3469         case ANEG_STATE_ABILITY_DETECT:
3470                 if (ap->ability_match != 0 && ap->rxconfig != 0)
3471                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3472                 break;
3473
3474         case ANEG_STATE_ACK_DETECT_INIT:
3475                 ap->txconfig |= ANEG_CFG_ACK;
3476                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3477                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3478                 tw32_f(MAC_MODE, tp->mac_mode);
3479                 udelay(40);
3480
3481                 ap->state = ANEG_STATE_ACK_DETECT;
3482
3483                 /* fallthru */
3484         case ANEG_STATE_ACK_DETECT:
3485                 if (ap->ack_match != 0) {
3486                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3487                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3488                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3489                         } else {
3490                                 ap->state = ANEG_STATE_AN_ENABLE;
3491                         }
3492                 } else if (ap->ability_match != 0 &&
3493                            ap->rxconfig == 0) {
3494                         ap->state = ANEG_STATE_AN_ENABLE;
3495                 }
3496                 break;
3497
3498         case ANEG_STATE_COMPLETE_ACK_INIT:
3499                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3500                         ret = ANEG_FAILED;
3501                         break;
3502                 }
3503                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3504                                MR_LP_ADV_HALF_DUPLEX |
3505                                MR_LP_ADV_SYM_PAUSE |
3506                                MR_LP_ADV_ASYM_PAUSE |
3507                                MR_LP_ADV_REMOTE_FAULT1 |
3508                                MR_LP_ADV_REMOTE_FAULT2 |
3509                                MR_LP_ADV_NEXT_PAGE |
3510                                MR_TOGGLE_RX |
3511                                MR_NP_RX);
3512                 if (ap->rxconfig & ANEG_CFG_FD)
3513                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3514                 if (ap->rxconfig & ANEG_CFG_HD)
3515                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3516                 if (ap->rxconfig & ANEG_CFG_PS1)
3517                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3518                 if (ap->rxconfig & ANEG_CFG_PS2)
3519                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3520                 if (ap->rxconfig & ANEG_CFG_RF1)
3521                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3522                 if (ap->rxconfig & ANEG_CFG_RF2)
3523                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3524                 if (ap->rxconfig & ANEG_CFG_NP)
3525                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3526
3527                 ap->link_time = ap->cur_time;
3528
3529                 ap->flags ^= (MR_TOGGLE_TX);
3530                 if (ap->rxconfig & 0x0008)
3531                         ap->flags |= MR_TOGGLE_RX;
3532                 if (ap->rxconfig & ANEG_CFG_NP)
3533                         ap->flags |= MR_NP_RX;
3534                 ap->flags |= MR_PAGE_RX;
3535
3536                 ap->state = ANEG_STATE_COMPLETE_ACK;
3537                 ret = ANEG_TIMER_ENAB;
3538                 break;
3539
3540         case ANEG_STATE_COMPLETE_ACK:
3541                 if (ap->ability_match != 0 &&
3542                     ap->rxconfig == 0) {
3543                         ap->state = ANEG_STATE_AN_ENABLE;
3544                         break;
3545                 }
3546                 delta = ap->cur_time - ap->link_time;
3547                 if (delta > ANEG_STATE_SETTLE_TIME) {
3548                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3549                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3550                         } else {
3551                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3552                                     !(ap->flags & MR_NP_RX)) {
3553                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3554                                 } else {
3555                                         ret = ANEG_FAILED;
3556                                 }
3557                         }
3558                 }
3559                 break;
3560
3561         case ANEG_STATE_IDLE_DETECT_INIT:
3562                 ap->link_time = ap->cur_time;
3563                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3564                 tw32_f(MAC_MODE, tp->mac_mode);
3565                 udelay(40);
3566
3567                 ap->state = ANEG_STATE_IDLE_DETECT;
3568                 ret = ANEG_TIMER_ENAB;
3569                 break;
3570
3571         case ANEG_STATE_IDLE_DETECT:
3572                 if (ap->ability_match != 0 &&
3573                     ap->rxconfig == 0) {
3574                         ap->state = ANEG_STATE_AN_ENABLE;
3575                         break;
3576                 }
3577                 delta = ap->cur_time - ap->link_time;
3578                 if (delta > ANEG_STATE_SETTLE_TIME) {
3579                         /* XXX another gem from the Broadcom driver :( */
3580                         ap->state = ANEG_STATE_LINK_OK;
3581                 }
3582                 break;
3583
3584         case ANEG_STATE_LINK_OK:
3585                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3586                 ret = ANEG_DONE;
3587                 break;
3588
3589         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3590                 /* ??? unimplemented */
3591                 break;
3592
3593         case ANEG_STATE_NEXT_PAGE_WAIT:
3594                 /* ??? unimplemented */
3595                 break;
3596
3597         default:
3598                 ret = ANEG_FAILED;
3599                 break;
3600         }
3601
3602         return ret;
3603 }
3604
3605 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3606 {
3607         int res = 0;
3608         struct tg3_fiber_aneginfo aninfo;
3609         int status = ANEG_FAILED;
3610         unsigned int tick;
3611         u32 tmp;
3612
3613         tw32_f(MAC_TX_AUTO_NEG, 0);
3614
3615         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3616         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3617         udelay(40);
3618
3619         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3620         udelay(40);
3621
3622         memset(&aninfo, 0, sizeof(aninfo));
3623         aninfo.flags |= MR_AN_ENABLE;
3624         aninfo.state = ANEG_STATE_UNKNOWN;
3625         aninfo.cur_time = 0;
3626         tick = 0;
3627         while (++tick < 195000) {
3628                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3629                 if (status == ANEG_DONE || status == ANEG_FAILED)
3630                         break;
3631
3632                 udelay(1);
3633         }
3634
3635         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3636         tw32_f(MAC_MODE, tp->mac_mode);
3637         udelay(40);
3638
3639         *txflags = aninfo.txconfig;
3640         *rxflags = aninfo.flags;
3641
3642         if (status == ANEG_DONE &&
3643             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3644                              MR_LP_ADV_FULL_DUPLEX)))
3645                 res = 1;
3646
3647         return res;
3648 }
3649
3650 static void tg3_init_bcm8002(struct tg3 *tp)
3651 {
3652         u32 mac_status = tr32(MAC_STATUS);
3653         int i;
3654
3655         /* Reset when initting first time or we have a link. */
3656         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3657             !(mac_status & MAC_STATUS_PCS_SYNCED))
3658                 return;
3659
3660         /* Set PLL lock range. */
3661         tg3_writephy(tp, 0x16, 0x8007);
3662
3663         /* SW reset */
3664         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3665
3666         /* Wait for reset to complete. */
3667         /* XXX schedule_timeout() ... */
3668         for (i = 0; i < 500; i++)
3669                 udelay(10);
3670
3671         /* Config mode; select PMA/Ch 1 regs. */
3672         tg3_writephy(tp, 0x10, 0x8411);
3673
3674         /* Enable auto-lock and comdet, select txclk for tx. */
3675         tg3_writephy(tp, 0x11, 0x0a10);
3676
3677         tg3_writephy(tp, 0x18, 0x00a0);
3678         tg3_writephy(tp, 0x16, 0x41ff);
3679
3680         /* Assert and deassert POR. */
3681         tg3_writephy(tp, 0x13, 0x0400);
3682         udelay(40);
3683         tg3_writephy(tp, 0x13, 0x0000);
3684
3685         tg3_writephy(tp, 0x11, 0x0a50);
3686         udelay(40);
3687         tg3_writephy(tp, 0x11, 0x0a10);
3688
3689         /* Wait for signal to stabilize */
3690         /* XXX schedule_timeout() ... */
3691         for (i = 0; i < 15000; i++)
3692                 udelay(10);
3693
3694         /* Deselect the channel register so we can read the PHYID
3695          * later.
3696          */
3697         tg3_writephy(tp, 0x10, 0x8011);
3698 }
3699
3700 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3701 {
3702         u16 flowctrl;
3703         u32 sg_dig_ctrl, sg_dig_status;
3704         u32 serdes_cfg, expected_sg_dig_ctrl;
3705         int workaround, port_a;
3706         int current_link_up;
3707
3708         serdes_cfg = 0;
3709         expected_sg_dig_ctrl = 0;
3710         workaround = 0;
3711         port_a = 1;
3712         current_link_up = 0;
3713
3714         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3715             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3716                 workaround = 1;
3717                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3718                         port_a = 0;
3719
3720                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3721                 /* preserve bits 20-23 for voltage regulator */
3722                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3723         }
3724
3725         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3726
3727         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3728                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3729                         if (workaround) {
3730                                 u32 val = serdes_cfg;
3731
3732                                 if (port_a)
3733                                         val |= 0xc010000;
3734                                 else
3735                                         val |= 0x4010000;
3736                                 tw32_f(MAC_SERDES_CFG, val);
3737                         }
3738
3739                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3740                 }
3741                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3742                         tg3_setup_flow_control(tp, 0, 0);
3743                         current_link_up = 1;
3744                 }
3745                 goto out;
3746         }
3747
3748         /* Want auto-negotiation.  */
3749         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3750
3751         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3752         if (flowctrl & ADVERTISE_1000XPAUSE)
3753                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3754         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3755                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3756
3757         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3758                 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3759                     tp->serdes_counter &&
3760                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3761                                     MAC_STATUS_RCVD_CFG)) ==
3762                      MAC_STATUS_PCS_SYNCED)) {
3763                         tp->serdes_counter--;
3764                         current_link_up = 1;
3765                         goto out;
3766                 }
3767 restart_autoneg:
3768                 if (workaround)
3769                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3770                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3771                 udelay(5);
3772                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3773
3774                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3775                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3776         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3777                                  MAC_STATUS_SIGNAL_DET)) {
3778                 sg_dig_status = tr32(SG_DIG_STATUS);
3779                 mac_status = tr32(MAC_STATUS);
3780
3781                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3782                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3783                         u32 local_adv = 0, remote_adv = 0;
3784
3785                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3786                                 local_adv |= ADVERTISE_1000XPAUSE;
3787                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3788                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3789
3790                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3791                                 remote_adv |= LPA_1000XPAUSE;
3792                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3793                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3794
3795                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3796                         current_link_up = 1;
3797                         tp->serdes_counter = 0;
3798                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3799                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3800                         if (tp->serdes_counter)
3801                                 tp->serdes_counter--;
3802                         else {
3803                                 if (workaround) {
3804                                         u32 val = serdes_cfg;
3805
3806                                         if (port_a)
3807                                                 val |= 0xc010000;
3808                                         else
3809                                                 val |= 0x4010000;
3810
3811                                         tw32_f(MAC_SERDES_CFG, val);
3812                                 }
3813
3814                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3815                                 udelay(40);
3816
3817                                 /* Link parallel detection - link is up */
3818                                 /* only if we have PCS_SYNC and not */
3819                                 /* receiving config code words */
3820                                 mac_status = tr32(MAC_STATUS);
3821                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3822                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3823                                         tg3_setup_flow_control(tp, 0, 0);
3824                                         current_link_up = 1;
3825                                         tp->phy_flags |=
3826                                                 TG3_PHYFLG_PARALLEL_DETECT;
3827                                         tp->serdes_counter =
3828                                                 SERDES_PARALLEL_DET_TIMEOUT;
3829                                 } else
3830                                         goto restart_autoneg;
3831                         }
3832                 }
3833         } else {
3834                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3835                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3836         }
3837
3838 out:
3839         return current_link_up;
3840 }
3841
3842 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3843 {
3844         int current_link_up = 0;
3845
3846         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3847                 goto out;
3848
3849         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3850                 u32 txflags, rxflags;
3851                 int i;
3852
3853                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3854                         u32 local_adv = 0, remote_adv = 0;
3855
3856                         if (txflags & ANEG_CFG_PS1)
3857                                 local_adv |= ADVERTISE_1000XPAUSE;
3858                         if (txflags & ANEG_CFG_PS2)
3859                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3860
3861                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3862                                 remote_adv |= LPA_1000XPAUSE;
3863                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3864                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3865
3866                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3867
3868                         current_link_up = 1;
3869                 }
3870                 for (i = 0; i < 30; i++) {
3871                         udelay(20);
3872                         tw32_f(MAC_STATUS,
3873                                (MAC_STATUS_SYNC_CHANGED |
3874                                 MAC_STATUS_CFG_CHANGED));
3875                         udelay(40);
3876                         if ((tr32(MAC_STATUS) &
3877                              (MAC_STATUS_SYNC_CHANGED |
3878                               MAC_STATUS_CFG_CHANGED)) == 0)
3879                                 break;
3880                 }
3881
3882                 mac_status = tr32(MAC_STATUS);
3883                 if (current_link_up == 0 &&
3884                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3885                     !(mac_status & MAC_STATUS_RCVD_CFG))
3886                         current_link_up = 1;
3887         } else {
3888                 tg3_setup_flow_control(tp, 0, 0);
3889
3890                 /* Forcing 1000FD link up. */
3891                 current_link_up = 1;
3892
3893                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3894                 udelay(40);
3895
3896                 tw32_f(MAC_MODE, tp->mac_mode);
3897                 udelay(40);
3898         }
3899
3900 out:
3901         return current_link_up;
3902 }
3903
3904 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3905 {
3906         u32 orig_pause_cfg;
3907         u16 orig_active_speed;
3908         u8 orig_active_duplex;
3909         u32 mac_status;
3910         int current_link_up;
3911         int i;
3912
3913         orig_pause_cfg = tp->link_config.active_flowctrl;
3914         orig_active_speed = tp->link_config.active_speed;
3915         orig_active_duplex = tp->link_config.active_duplex;
3916
3917         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3918             netif_carrier_ok(tp->dev) &&
3919             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3920                 mac_status = tr32(MAC_STATUS);
3921                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3922                                MAC_STATUS_SIGNAL_DET |
3923                                MAC_STATUS_CFG_CHANGED |
3924                                MAC_STATUS_RCVD_CFG);
3925                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3926                                    MAC_STATUS_SIGNAL_DET)) {
3927                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3928                                             MAC_STATUS_CFG_CHANGED));
3929                         return 0;
3930                 }
3931         }
3932
3933         tw32_f(MAC_TX_AUTO_NEG, 0);
3934
3935         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3936         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3937         tw32_f(MAC_MODE, tp->mac_mode);
3938         udelay(40);
3939
3940         if (tp->phy_id == TG3_PHY_ID_BCM8002)
3941                 tg3_init_bcm8002(tp);
3942
3943         /* Enable link change event even when serdes polling.  */
3944         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3945         udelay(40);
3946
3947         current_link_up = 0;
3948         mac_status = tr32(MAC_STATUS);
3949
3950         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3951                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3952         else
3953                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3954
3955         tp->napi[0].hw_status->status =
3956                 (SD_STATUS_UPDATED |
3957                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3958
3959         for (i = 0; i < 100; i++) {
3960                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3961                                     MAC_STATUS_CFG_CHANGED));
3962                 udelay(5);
3963                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3964                                          MAC_STATUS_CFG_CHANGED |
3965                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3966                         break;
3967         }
3968
3969         mac_status = tr32(MAC_STATUS);
3970         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3971                 current_link_up = 0;
3972                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3973                     tp->serdes_counter == 0) {
3974                         tw32_f(MAC_MODE, (tp->mac_mode |
3975                                           MAC_MODE_SEND_CONFIGS));
3976                         udelay(1);
3977                         tw32_f(MAC_MODE, tp->mac_mode);
3978                 }
3979         }
3980
3981         if (current_link_up == 1) {
3982                 tp->link_config.active_speed = SPEED_1000;
3983                 tp->link_config.active_duplex = DUPLEX_FULL;
3984                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3985                                     LED_CTRL_LNKLED_OVERRIDE |
3986                                     LED_CTRL_1000MBPS_ON));
3987         } else {
3988                 tp->link_config.active_speed = SPEED_INVALID;
3989                 tp->link_config.active_duplex = DUPLEX_INVALID;
3990                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3991                                     LED_CTRL_LNKLED_OVERRIDE |
3992                                     LED_CTRL_TRAFFIC_OVERRIDE));
3993         }
3994
3995         if (current_link_up != netif_carrier_ok(tp->dev)) {
3996                 if (current_link_up)
3997                         netif_carrier_on(tp->dev);
3998                 else
3999                         netif_carrier_off(tp->dev);
4000                 tg3_link_report(tp);
4001         } else {
4002                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4003                 if (orig_pause_cfg != now_pause_cfg ||
4004                     orig_active_speed != tp->link_config.active_speed ||
4005                     orig_active_duplex != tp->link_config.active_duplex)
4006                         tg3_link_report(tp);
4007         }
4008
4009         return 0;
4010 }
4011
4012 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4013 {
4014         int current_link_up, err = 0;
4015         u32 bmsr, bmcr;
4016         u16 current_speed;
4017         u8 current_duplex;
4018         u32 local_adv, remote_adv;
4019
4020         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4021         tw32_f(MAC_MODE, tp->mac_mode);
4022         udelay(40);
4023
4024         tw32(MAC_EVENT, 0);
4025
4026         tw32_f(MAC_STATUS,
4027              (MAC_STATUS_SYNC_CHANGED |
4028               MAC_STATUS_CFG_CHANGED |
4029               MAC_STATUS_MI_COMPLETION |
4030               MAC_STATUS_LNKSTATE_CHANGED));
4031         udelay(40);
4032
4033         if (force_reset)
4034                 tg3_phy_reset(tp);
4035
4036         current_link_up = 0;
4037         current_speed = SPEED_INVALID;
4038         current_duplex = DUPLEX_INVALID;
4039
4040         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4041         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4042         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4043                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4044                         bmsr |= BMSR_LSTATUS;
4045                 else
4046                         bmsr &= ~BMSR_LSTATUS;
4047         }
4048
4049         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4050
4051         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4052             (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4053                 /* do nothing, just check for link up at the end */
4054         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4055                 u32 adv, new_adv;
4056
4057                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4058                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4059                                   ADVERTISE_1000XPAUSE |
4060                                   ADVERTISE_1000XPSE_ASYM |
4061                                   ADVERTISE_SLCT);
4062
4063                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4064
4065                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4066                         new_adv |= ADVERTISE_1000XHALF;
4067                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4068                         new_adv |= ADVERTISE_1000XFULL;
4069
4070                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4071                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4072                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4073                         tg3_writephy(tp, MII_BMCR, bmcr);
4074
4075                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4076                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4077                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4078
4079                         return err;
4080                 }
4081         } else {
4082                 u32 new_bmcr;
4083
4084                 bmcr &= ~BMCR_SPEED1000;
4085                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4086
4087                 if (tp->link_config.duplex == DUPLEX_FULL)
4088                         new_bmcr |= BMCR_FULLDPLX;
4089
4090                 if (new_bmcr != bmcr) {
4091                         /* BMCR_SPEED1000 is a reserved bit that needs
4092                          * to be set on write.
4093                          */
4094                         new_bmcr |= BMCR_SPEED1000;
4095
4096                         /* Force a linkdown */
4097                         if (netif_carrier_ok(tp->dev)) {
4098                                 u32 adv;
4099
4100                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4101                                 adv &= ~(ADVERTISE_1000XFULL |
4102                                          ADVERTISE_1000XHALF |
4103                                          ADVERTISE_SLCT);
4104                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4105                                 tg3_writephy(tp, MII_BMCR, bmcr |
4106                                                            BMCR_ANRESTART |
4107                                                            BMCR_ANENABLE);
4108                                 udelay(10);
4109                                 netif_carrier_off(tp->dev);
4110                         }
4111                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4112                         bmcr = new_bmcr;
4113                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4114                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4115                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4116                             ASIC_REV_5714) {
4117                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4118                                         bmsr |= BMSR_LSTATUS;
4119                                 else
4120                                         bmsr &= ~BMSR_LSTATUS;
4121                         }
4122                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4123                 }
4124         }
4125
4126         if (bmsr & BMSR_LSTATUS) {
4127                 current_speed = SPEED_1000;
4128                 current_link_up = 1;
4129                 if (bmcr & BMCR_FULLDPLX)
4130                         current_duplex = DUPLEX_FULL;
4131                 else
4132                         current_duplex = DUPLEX_HALF;
4133
4134                 local_adv = 0;
4135                 remote_adv = 0;
4136
4137                 if (bmcr & BMCR_ANENABLE) {
4138                         u32 common;
4139
4140                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4141                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4142                         common = local_adv & remote_adv;
4143                         if (common & (ADVERTISE_1000XHALF |
4144                                       ADVERTISE_1000XFULL)) {
4145                                 if (common & ADVERTISE_1000XFULL)
4146                                         current_duplex = DUPLEX_FULL;
4147                                 else
4148                                         current_duplex = DUPLEX_HALF;
4149                         } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4150                                 /* Link is up via parallel detect */
4151                         } else {
4152                                 current_link_up = 0;
4153                         }
4154                 }
4155         }
4156
4157         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4158                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4159
4160         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4161         if (tp->link_config.active_duplex == DUPLEX_HALF)
4162                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4163
4164         tw32_f(MAC_MODE, tp->mac_mode);
4165         udelay(40);
4166
4167         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4168
4169         tp->link_config.active_speed = current_speed;
4170         tp->link_config.active_duplex = current_duplex;
4171
4172         if (current_link_up != netif_carrier_ok(tp->dev)) {
4173                 if (current_link_up)
4174                         netif_carrier_on(tp->dev);
4175                 else {
4176                         netif_carrier_off(tp->dev);
4177                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4178                 }
4179                 tg3_link_report(tp);
4180         }
4181         return err;
4182 }
4183
4184 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4185 {
4186         if (tp->serdes_counter) {
4187                 /* Give autoneg time to complete. */
4188                 tp->serdes_counter--;
4189                 return;
4190         }
4191
4192         if (!netif_carrier_ok(tp->dev) &&
4193             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4194                 u32 bmcr;
4195
4196                 tg3_readphy(tp, MII_BMCR, &bmcr);
4197                 if (bmcr & BMCR_ANENABLE) {
4198                         u32 phy1, phy2;
4199
4200                         /* Select shadow register 0x1f */
4201                         tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
4202                         tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
4203
4204                         /* Select expansion interrupt status register */
4205                         tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4206                                          MII_TG3_DSP_EXP1_INT_STAT);
4207                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4208                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4209
4210                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4211                                 /* We have signal detect and not receiving
4212                                  * config code words, link is up by parallel
4213                                  * detection.
4214                                  */
4215
4216                                 bmcr &= ~BMCR_ANENABLE;
4217                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4218                                 tg3_writephy(tp, MII_BMCR, bmcr);
4219                                 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
4220                         }
4221                 }
4222         } else if (netif_carrier_ok(tp->dev) &&
4223                    (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4224                    (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4225                 u32 phy2;
4226
4227                 /* Select expansion interrupt status register */
4228                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4229                                  MII_TG3_DSP_EXP1_INT_STAT);
4230                 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4231                 if (phy2 & 0x20) {
4232                         u32 bmcr;
4233
4234                         /* Config code words received, turn on autoneg. */
4235                         tg3_readphy(tp, MII_BMCR, &bmcr);
4236                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4237
4238                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4239
4240                 }
4241         }
4242 }
4243
4244 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4245 {
4246         int err;
4247
4248         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
4249                 err = tg3_setup_fiber_phy(tp, force_reset);
4250         else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4251                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4252         else
4253                 err = tg3_setup_copper_phy(tp, force_reset);
4254
4255         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4256                 u32 val, scale;
4257
4258                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4259                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4260                         scale = 65;
4261                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4262                         scale = 6;
4263                 else
4264                         scale = 12;
4265
4266                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4267                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4268                 tw32(GRC_MISC_CFG, val);
4269         }
4270
4271         if (tp->link_config.active_speed == SPEED_1000 &&
4272             tp->link_config.active_duplex == DUPLEX_HALF)
4273                 tw32(MAC_TX_LENGTHS,
4274                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4275                       (6 << TX_LENGTHS_IPG_SHIFT) |
4276                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4277         else
4278                 tw32(MAC_TX_LENGTHS,
4279                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4280                       (6 << TX_LENGTHS_IPG_SHIFT) |
4281                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4282
4283         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4284                 if (netif_carrier_ok(tp->dev)) {
4285                         tw32(HOSTCC_STAT_COAL_TICKS,
4286                              tp->coal.stats_block_coalesce_usecs);
4287                 } else {
4288                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4289                 }
4290         }
4291
4292         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4293                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4294                 if (!netif_carrier_ok(tp->dev))
4295                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4296                               tp->pwrmgmt_thresh;
4297                 else
4298                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4299                 tw32(PCIE_PWR_MGMT_THRESH, val);
4300         }
4301
4302         return err;
4303 }
4304
4305 static inline int tg3_irq_sync(struct tg3 *tp)
4306 {
4307         return tp->irq_sync;
4308 }
4309
4310 /* This is called whenever we suspect that the system chipset is re-
4311  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4312  * is bogus tx completions. We try to recover by setting the
4313  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4314  * in the workqueue.
4315  */
4316 static void tg3_tx_recover(struct tg3 *tp)
4317 {
4318         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4319                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4320
4321         netdev_warn(tp->dev,
4322                     "The system may be re-ordering memory-mapped I/O "
4323                     "cycles to the network device, attempting to recover. "
4324                     "Please report the problem to the driver maintainer "
4325                     "and include system chipset information.\n");
4326
4327         spin_lock(&tp->lock);
4328         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4329         spin_unlock(&tp->lock);
4330 }
4331
4332 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4333 {
4334         /* Tell compiler to fetch tx indices from memory. */
4335         barrier();
4336         return tnapi->tx_pending -
4337                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4338 }
4339
4340 /* Tigon3 never reports partial packet sends.  So we do not
4341  * need special logic to handle SKBs that have not had all
4342  * of their frags sent yet, like SunGEM does.
4343  */
4344 static void tg3_tx(struct tg3_napi *tnapi)
4345 {
4346         struct tg3 *tp = tnapi->tp;
4347         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4348         u32 sw_idx = tnapi->tx_cons;
4349         struct netdev_queue *txq;
4350         int index = tnapi - tp->napi;
4351
4352         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4353                 index--;
4354
4355         txq = netdev_get_tx_queue(tp->dev, index);
4356
4357         while (sw_idx != hw_idx) {
4358                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4359                 struct sk_buff *skb = ri->skb;
4360                 int i, tx_bug = 0;
4361
4362                 if (unlikely(skb == NULL)) {
4363                         tg3_tx_recover(tp);
4364                         return;
4365                 }
4366
4367                 pci_unmap_single(tp->pdev,
4368                                  dma_unmap_addr(ri, mapping),
4369                                  skb_headlen(skb),
4370                                  PCI_DMA_TODEVICE);
4371
4372                 ri->skb = NULL;
4373
4374                 sw_idx = NEXT_TX(sw_idx);
4375
4376                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4377                         ri = &tnapi->tx_buffers[sw_idx];
4378                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4379                                 tx_bug = 1;
4380
4381                         pci_unmap_page(tp->pdev,
4382                                        dma_unmap_addr(ri, mapping),
4383                                        skb_shinfo(skb)->frags[i].size,
4384                                        PCI_DMA_TODEVICE);
4385                         sw_idx = NEXT_TX(sw_idx);
4386                 }
4387
4388                 dev_kfree_skb(skb);
4389
4390                 if (unlikely(tx_bug)) {
4391                         tg3_tx_recover(tp);
4392                         return;
4393                 }
4394         }
4395
4396         tnapi->tx_cons = sw_idx;
4397
4398         /* Need to make the tx_cons update visible to tg3_start_xmit()
4399          * before checking for netif_queue_stopped().  Without the
4400          * memory barrier, there is a small possibility that tg3_start_xmit()
4401          * will miss it and cause the queue to be stopped forever.
4402          */
4403         smp_mb();
4404
4405         if (unlikely(netif_tx_queue_stopped(txq) &&
4406                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4407                 __netif_tx_lock(txq, smp_processor_id());
4408                 if (netif_tx_queue_stopped(txq) &&
4409                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4410                         netif_tx_wake_queue(txq);
4411                 __netif_tx_unlock(txq);
4412         }
4413 }
4414
4415 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4416 {
4417         if (!ri->skb)
4418                 return;
4419
4420         pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4421                          map_sz, PCI_DMA_FROMDEVICE);
4422         dev_kfree_skb_any(ri->skb);
4423         ri->skb = NULL;
4424 }
4425
4426 /* Returns size of skb allocated or < 0 on error.
4427  *
4428  * We only need to fill in the address because the other members
4429  * of the RX descriptor are invariant, see tg3_init_rings.
4430  *
4431  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4432  * posting buffers we only dirty the first cache line of the RX
4433  * descriptor (containing the address).  Whereas for the RX status
4434  * buffers the cpu only reads the last cacheline of the RX descriptor
4435  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4436  */
4437 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4438                             u32 opaque_key, u32 dest_idx_unmasked)
4439 {
4440         struct tg3_rx_buffer_desc *desc;
4441         struct ring_info *map, *src_map;
4442         struct sk_buff *skb;
4443         dma_addr_t mapping;
4444         int skb_size, dest_idx;
4445
4446         src_map = NULL;
4447         switch (opaque_key) {
4448         case RXD_OPAQUE_RING_STD:
4449                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4450                 desc = &tpr->rx_std[dest_idx];
4451                 map = &tpr->rx_std_buffers[dest_idx];
4452                 skb_size = tp->rx_pkt_map_sz;
4453                 break;
4454
4455         case RXD_OPAQUE_RING_JUMBO:
4456                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4457                 desc = &tpr->rx_jmb[dest_idx].std;
4458                 map = &tpr->rx_jmb_buffers[dest_idx];
4459                 skb_size = TG3_RX_JMB_MAP_SZ;
4460                 break;
4461
4462         default:
4463                 return -EINVAL;
4464         }
4465
4466         /* Do not overwrite any of the map or rp information
4467          * until we are sure we can commit to a new buffer.
4468          *
4469          * Callers depend upon this behavior and assume that
4470          * we leave everything unchanged if we fail.
4471          */
4472         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4473         if (skb == NULL)
4474                 return -ENOMEM;
4475
4476         skb_reserve(skb, tp->rx_offset);
4477
4478         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4479                                  PCI_DMA_FROMDEVICE);
4480         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4481                 dev_kfree_skb(skb);
4482                 return -EIO;
4483         }
4484
4485         map->skb = skb;
4486         dma_unmap_addr_set(map, mapping, mapping);
4487
4488         desc->addr_hi = ((u64)mapping >> 32);
4489         desc->addr_lo = ((u64)mapping & 0xffffffff);
4490
4491         return skb_size;
4492 }
4493
4494 /* We only need to move over in the address because the other
4495  * members of the RX descriptor are invariant.  See notes above
4496  * tg3_alloc_rx_skb for full details.
4497  */
4498 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4499                            struct tg3_rx_prodring_set *dpr,
4500                            u32 opaque_key, int src_idx,
4501                            u32 dest_idx_unmasked)
4502 {
4503         struct tg3 *tp = tnapi->tp;
4504         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4505         struct ring_info *src_map, *dest_map;
4506         struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
4507         int dest_idx;
4508
4509         switch (opaque_key) {
4510         case RXD_OPAQUE_RING_STD:
4511                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4512                 dest_desc = &dpr->rx_std[dest_idx];
4513                 dest_map = &dpr->rx_std_buffers[dest_idx];
4514                 src_desc = &spr->rx_std[src_idx];
4515                 src_map = &spr->rx_std_buffers[src_idx];
4516                 break;
4517
4518         case RXD_OPAQUE_RING_JUMBO:
4519                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4520                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4521                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4522                 src_desc = &spr->rx_jmb[src_idx].std;
4523                 src_map = &spr->rx_jmb_buffers[src_idx];
4524                 break;
4525
4526         default:
4527                 return;
4528         }
4529
4530         dest_map->skb = src_map->skb;
4531         dma_unmap_addr_set(dest_map, mapping,
4532                            dma_unmap_addr(src_map, mapping));
4533         dest_desc->addr_hi = src_desc->addr_hi;
4534         dest_desc->addr_lo = src_desc->addr_lo;
4535
4536         /* Ensure that the update to the skb happens after the physical
4537          * addresses have been transferred to the new BD location.
4538          */
4539         smp_wmb();
4540
4541         src_map->skb = NULL;
4542 }
4543
4544 /* The RX ring scheme is composed of multiple rings which post fresh
4545  * buffers to the chip, and one special ring the chip uses to report
4546  * status back to the host.
4547  *
4548  * The special ring reports the status of received packets to the
4549  * host.  The chip does not write into the original descriptor the
4550  * RX buffer was obtained from.  The chip simply takes the original
4551  * descriptor as provided by the host, updates the status and length
4552  * field, then writes this into the next status ring entry.
4553  *
4554  * Each ring the host uses to post buffers to the chip is described
4555  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4556  * it is first placed into the on-chip ram.  When the packet's length
4557  * is known, it walks down the TG3_BDINFO entries to select the ring.
4558  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4559  * which is within the range of the new packet's length is chosen.
4560  *
4561  * The "separate ring for rx status" scheme may sound queer, but it makes
4562  * sense from a cache coherency perspective.  If only the host writes
4563  * to the buffer post rings, and only the chip writes to the rx status
4564  * rings, then cache lines never move beyond shared-modified state.
4565  * If both the host and chip were to write into the same ring, cache line
4566  * eviction could occur since both entities want it in an exclusive state.
4567  */
4568 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4569 {
4570         struct tg3 *tp = tnapi->tp;
4571         u32 work_mask, rx_std_posted = 0;
4572         u32 std_prod_idx, jmb_prod_idx;
4573         u32 sw_idx = tnapi->rx_rcb_ptr;
4574         u16 hw_idx;
4575         int received;
4576         struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
4577
4578         hw_idx = *(tnapi->rx_rcb_prod_idx);
4579         /*
4580          * We need to order the read of hw_idx and the read of
4581          * the opaque cookie.
4582          */
4583         rmb();
4584         work_mask = 0;
4585         received = 0;
4586         std_prod_idx = tpr->rx_std_prod_idx;
4587         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4588         while (sw_idx != hw_idx && budget > 0) {
4589                 struct ring_info *ri;
4590                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4591                 unsigned int len;
4592                 struct sk_buff *skb;
4593                 dma_addr_t dma_addr;
4594                 u32 opaque_key, desc_idx, *post_ptr;
4595                 bool hw_vlan __maybe_unused = false;
4596                 u16 vtag __maybe_unused = 0;
4597
4598                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4599                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4600                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4601                         ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4602                         dma_addr = dma_unmap_addr(ri, mapping);
4603                         skb = ri->skb;
4604                         post_ptr = &std_prod_idx;
4605                         rx_std_posted++;
4606                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4607                         ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4608                         dma_addr = dma_unmap_addr(ri, mapping);
4609                         skb = ri->skb;
4610                         post_ptr = &jmb_prod_idx;
4611                 } else
4612                         goto next_pkt_nopost;
4613
4614                 work_mask |= opaque_key;
4615
4616                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4617                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4618                 drop_it:
4619                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4620                                        desc_idx, *post_ptr);
4621                 drop_it_no_recycle:
4622                         /* Other statistics kept track of by card. */
4623                         tp->net_stats.rx_dropped++;
4624                         goto next_pkt;
4625                 }
4626
4627                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4628                       ETH_FCS_LEN;
4629
4630                 if (len > TG3_RX_COPY_THRESH(tp)) {
4631                         int skb_size;
4632
4633                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4634                                                     *post_ptr);
4635                         if (skb_size < 0)
4636                                 goto drop_it;
4637
4638                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4639                                          PCI_DMA_FROMDEVICE);
4640
4641                         /* Ensure that the update to the skb happens
4642                          * after the usage of the old DMA mapping.
4643                          */
4644                         smp_wmb();
4645
4646                         ri->skb = NULL;
4647
4648                         skb_put(skb, len);
4649                 } else {
4650                         struct sk_buff *copy_skb;
4651
4652                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4653                                        desc_idx, *post_ptr);
4654
4655                         copy_skb = netdev_alloc_skb(tp->dev, len + VLAN_HLEN +
4656                                                     TG3_RAW_IP_ALIGN);
4657                         if (copy_skb == NULL)
4658                                 goto drop_it_no_recycle;
4659
4660                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN + VLAN_HLEN);
4661                         skb_put(copy_skb, len);
4662                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4663                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4664                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4665
4666                         /* We'll reuse the original ring buffer. */
4667                         skb = copy_skb;
4668                 }
4669
4670                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4671                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4672                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4673                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4674                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4675                 else
4676                         skb_checksum_none_assert(skb);
4677
4678                 skb->protocol = eth_type_trans(skb, tp->dev);
4679
4680                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4681                     skb->protocol != htons(ETH_P_8021Q)) {
4682                         dev_kfree_skb(skb);
4683                         goto next_pkt;
4684                 }
4685
4686                 if (desc->type_flags & RXD_FLAG_VLAN &&
4687                     !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) {
4688                         vtag = desc->err_vlan & RXD_VLAN_MASK;
4689 #if TG3_VLAN_TAG_USED
4690                         if (tp->vlgrp)
4691                                 hw_vlan = true;
4692                         else
4693 #endif
4694                         {
4695                                 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
4696                                                     __skb_push(skb, VLAN_HLEN);
4697
4698                                 memmove(ve, skb->data + VLAN_HLEN,
4699                                         ETH_ALEN * 2);
4700                                 ve->h_vlan_proto = htons(ETH_P_8021Q);
4701                                 ve->h_vlan_TCI = htons(vtag);
4702                         }
4703                 }
4704
4705 #if TG3_VLAN_TAG_USED
4706                 if (hw_vlan)
4707                         vlan_gro_receive(&tnapi->napi, tp->vlgrp, vtag, skb);
4708                 else
4709 #endif
4710                         napi_gro_receive(&tnapi->napi, skb);
4711
4712                 received++;
4713                 budget--;
4714
4715 next_pkt:
4716                 (*post_ptr)++;
4717
4718                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4719                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4720                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4721                                      tpr->rx_std_prod_idx);
4722                         work_mask &= ~RXD_OPAQUE_RING_STD;
4723                         rx_std_posted = 0;
4724                 }
4725 next_pkt_nopost:
4726                 sw_idx++;
4727                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4728
4729                 /* Refresh hw_idx to see if there is new work */
4730                 if (sw_idx == hw_idx) {
4731                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4732                         rmb();
4733                 }
4734         }
4735
4736         /* ACK the status ring. */
4737         tnapi->rx_rcb_ptr = sw_idx;
4738         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4739
4740         /* Refill RX ring(s). */
4741         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4742                 if (work_mask & RXD_OPAQUE_RING_STD) {
4743                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4744                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4745                                      tpr->rx_std_prod_idx);
4746                 }
4747                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4748                         tpr->rx_jmb_prod_idx = jmb_prod_idx %
4749                                                TG3_RX_JUMBO_RING_SIZE;
4750                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4751                                      tpr->rx_jmb_prod_idx);
4752                 }
4753                 mmiowb();
4754         } else if (work_mask) {
4755                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4756                  * updated before the producer indices can be updated.
4757                  */
4758                 smp_wmb();
4759
4760                 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4761                 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
4762
4763                 if (tnapi != &tp->napi[1])
4764                         napi_schedule(&tp->napi[1].napi);
4765         }
4766
4767         return received;
4768 }
4769
4770 static void tg3_poll_link(struct tg3 *tp)
4771 {
4772         /* handle link change and other phy events */
4773         if (!(tp->tg3_flags &
4774               (TG3_FLAG_USE_LINKCHG_REG |
4775                TG3_FLAG_POLL_SERDES))) {
4776                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4777
4778                 if (sblk->status & SD_STATUS_LINK_CHG) {
4779                         sblk->status = SD_STATUS_UPDATED |
4780                                        (sblk->status & ~SD_STATUS_LINK_CHG);
4781                         spin_lock(&tp->lock);
4782                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4783                                 tw32_f(MAC_STATUS,
4784                                      (MAC_STATUS_SYNC_CHANGED |
4785                                       MAC_STATUS_CFG_CHANGED |
4786                                       MAC_STATUS_MI_COMPLETION |
4787                                       MAC_STATUS_LNKSTATE_CHANGED));
4788                                 udelay(40);
4789                         } else
4790                                 tg3_setup_phy(tp, 0);
4791                         spin_unlock(&tp->lock);
4792                 }
4793         }
4794 }
4795
4796 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4797                                 struct tg3_rx_prodring_set *dpr,
4798                                 struct tg3_rx_prodring_set *spr)
4799 {
4800         u32 si, di, cpycnt, src_prod_idx;
4801         int i, err = 0;
4802
4803         while (1) {
4804                 src_prod_idx = spr->rx_std_prod_idx;
4805
4806                 /* Make sure updates to the rx_std_buffers[] entries and the
4807                  * standard producer index are seen in the correct order.
4808                  */
4809                 smp_rmb();
4810
4811                 if (spr->rx_std_cons_idx == src_prod_idx)
4812                         break;
4813
4814                 if (spr->rx_std_cons_idx < src_prod_idx)
4815                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4816                 else
4817                         cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4818
4819                 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4820
4821                 si = spr->rx_std_cons_idx;
4822                 di = dpr->rx_std_prod_idx;
4823
4824                 for (i = di; i < di + cpycnt; i++) {
4825                         if (dpr->rx_std_buffers[i].skb) {
4826                                 cpycnt = i - di;
4827                                 err = -ENOSPC;
4828                                 break;
4829                         }
4830                 }
4831
4832                 if (!cpycnt)
4833                         break;
4834
4835                 /* Ensure that updates to the rx_std_buffers ring and the
4836                  * shadowed hardware producer ring from tg3_recycle_skb() are
4837                  * ordered correctly WRT the skb check above.
4838                  */
4839                 smp_rmb();
4840
4841                 memcpy(&dpr->rx_std_buffers[di],
4842                        &spr->rx_std_buffers[si],
4843                        cpycnt * sizeof(struct ring_info));
4844
4845                 for (i = 0; i < cpycnt; i++, di++, si++) {
4846                         struct tg3_rx_buffer_desc *sbd, *dbd;
4847                         sbd = &spr->rx_std[si];
4848                         dbd = &dpr->rx_std[di];
4849                         dbd->addr_hi = sbd->addr_hi;
4850                         dbd->addr_lo = sbd->addr_lo;
4851                 }
4852
4853                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4854                                        TG3_RX_RING_SIZE;
4855                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4856                                        TG3_RX_RING_SIZE;
4857         }
4858
4859         while (1) {
4860                 src_prod_idx = spr->rx_jmb_prod_idx;
4861
4862                 /* Make sure updates to the rx_jmb_buffers[] entries and
4863                  * the jumbo producer index are seen in the correct order.
4864                  */
4865                 smp_rmb();
4866
4867                 if (spr->rx_jmb_cons_idx == src_prod_idx)
4868                         break;
4869
4870                 if (spr->rx_jmb_cons_idx < src_prod_idx)
4871                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4872                 else
4873                         cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4874
4875                 cpycnt = min(cpycnt,
4876                              TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4877
4878                 si = spr->rx_jmb_cons_idx;
4879                 di = dpr->rx_jmb_prod_idx;
4880
4881                 for (i = di; i < di + cpycnt; i++) {
4882                         if (dpr->rx_jmb_buffers[i].skb) {
4883                                 cpycnt = i - di;
4884                                 err = -ENOSPC;
4885                                 break;
4886                         }
4887                 }
4888
4889                 if (!cpycnt)
4890                         break;
4891
4892                 /* Ensure that updates to the rx_jmb_buffers ring and the
4893                  * shadowed hardware producer ring from tg3_recycle_skb() are
4894                  * ordered correctly WRT the skb check above.
4895                  */
4896                 smp_rmb();
4897
4898                 memcpy(&dpr->rx_jmb_buffers[di],
4899                        &spr->rx_jmb_buffers[si],
4900                        cpycnt * sizeof(struct ring_info));
4901
4902                 for (i = 0; i < cpycnt; i++, di++, si++) {
4903                         struct tg3_rx_buffer_desc *sbd, *dbd;
4904                         sbd = &spr->rx_jmb[si].std;
4905                         dbd = &dpr->rx_jmb[di].std;
4906                         dbd->addr_hi = sbd->addr_hi;
4907                         dbd->addr_lo = sbd->addr_lo;
4908                 }
4909
4910                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4911                                        TG3_RX_JUMBO_RING_SIZE;
4912                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4913                                        TG3_RX_JUMBO_RING_SIZE;
4914         }
4915
4916         return err;
4917 }
4918
4919 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4920 {
4921         struct tg3 *tp = tnapi->tp;
4922
4923         /* run TX completion thread */
4924         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4925                 tg3_tx(tnapi);
4926                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4927                         return work_done;
4928         }
4929
4930         /* run RX thread, within the bounds set by NAPI.
4931          * All RX "locking" is done by ensuring outside
4932          * code synchronizes with tg3->napi.poll()
4933          */
4934         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4935                 work_done += tg3_rx(tnapi, budget - work_done);
4936
4937         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4938                 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
4939                 int i, err = 0;
4940                 u32 std_prod_idx = dpr->rx_std_prod_idx;
4941                 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
4942
4943                 for (i = 1; i < tp->irq_cnt; i++)
4944                         err |= tg3_rx_prodring_xfer(tp, dpr,
4945                                                     &tp->napi[i].prodring);
4946
4947                 wmb();
4948
4949                 if (std_prod_idx != dpr->rx_std_prod_idx)
4950                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4951                                      dpr->rx_std_prod_idx);
4952
4953                 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
4954                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4955                                      dpr->rx_jmb_prod_idx);
4956
4957                 mmiowb();
4958
4959                 if (err)
4960                         tw32_f(HOSTCC_MODE, tp->coal_now);
4961         }
4962
4963         return work_done;
4964 }
4965
4966 static int tg3_poll_msix(struct napi_struct *napi, int budget)
4967 {
4968         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4969         struct tg3 *tp = tnapi->tp;
4970         int work_done = 0;
4971         struct tg3_hw_status *sblk = tnapi->hw_status;
4972
4973         while (1) {
4974                 work_done = tg3_poll_work(tnapi, work_done, budget);
4975
4976                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4977                         goto tx_recovery;
4978
4979                 if (unlikely(work_done >= budget))
4980                         break;
4981
4982                 /* tp->last_tag is used in tg3_int_reenable() below
4983                  * to tell the hw how much work has been processed,
4984                  * so we must read it before checking for more work.
4985                  */
4986                 tnapi->last_tag = sblk->status_tag;
4987                 tnapi->last_irq_tag = tnapi->last_tag;
4988                 rmb();
4989
4990                 /* check for RX/TX work to do */
4991                 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
4992                            *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
4993                         napi_complete(napi);
4994                         /* Reenable interrupts. */
4995                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
4996                         mmiowb();
4997                         break;
4998                 }
4999         }
5000
5001         return work_done;
5002
5003 tx_recovery:
5004         /* work_done is guaranteed to be less than budget. */
5005         napi_complete(napi);
5006         schedule_work(&tp->reset_task);
5007         return work_done;
5008 }
5009
5010 static int tg3_poll(struct napi_struct *napi, int budget)
5011 {
5012         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5013         struct tg3 *tp = tnapi->tp;
5014         int work_done = 0;
5015         struct tg3_hw_status *sblk = tnapi->hw_status;
5016
5017         while (1) {
5018                 tg3_poll_link(tp);
5019
5020                 work_done = tg3_poll_work(tnapi, work_done, budget);
5021
5022                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5023                         goto tx_recovery;
5024
5025                 if (unlikely(work_done >= budget))
5026                         break;
5027
5028                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5029                         /* tp->last_tag is used in tg3_int_reenable() below
5030                          * to tell the hw how much work has been processed,
5031                          * so we must read it before checking for more work.
5032                          */
5033                         tnapi->last_tag = sblk->status_tag;
5034                         tnapi->last_irq_tag = tnapi->last_tag;
5035                         rmb();
5036                 } else
5037                         sblk->status &= ~SD_STATUS_UPDATED;
5038
5039                 if (likely(!tg3_has_work(tnapi))) {
5040                         napi_complete(napi);
5041                         tg3_int_reenable(tnapi);
5042                         break;
5043                 }
5044         }
5045
5046         return work_done;
5047
5048 tx_recovery:
5049         /* work_done is guaranteed to be less than budget. */
5050         napi_complete(napi);
5051         schedule_work(&tp->reset_task);
5052         return work_done;
5053 }
5054
5055 static void tg3_napi_disable(struct tg3 *tp)
5056 {
5057         int i;
5058
5059         for (i = tp->irq_cnt - 1; i >= 0; i--)
5060                 napi_disable(&tp->napi[i].napi);
5061 }
5062
5063 static void tg3_napi_enable(struct tg3 *tp)
5064 {
5065         int i;
5066
5067         for (i = 0; i < tp->irq_cnt; i++)
5068                 napi_enable(&tp->napi[i].napi);
5069 }
5070
5071 static void tg3_napi_init(struct tg3 *tp)
5072 {
5073         int i;
5074
5075         netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
5076         for (i = 1; i < tp->irq_cnt; i++)
5077                 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
5078 }
5079
5080 static void tg3_napi_fini(struct tg3 *tp)
5081 {
5082         int i;
5083
5084         for (i = 0; i < tp->irq_cnt; i++)
5085                 netif_napi_del(&tp->napi[i].napi);
5086 }
5087
5088 static inline void tg3_netif_stop(struct tg3 *tp)
5089 {
5090         tp->dev->trans_start = jiffies; /* prevent tx timeout */
5091         tg3_napi_disable(tp);
5092         netif_tx_disable(tp->dev);
5093 }
5094
5095 static inline void tg3_netif_start(struct tg3 *tp)
5096 {
5097         /* NOTE: unconditional netif_tx_wake_all_queues is only
5098          * appropriate so long as all callers are assured to
5099          * have free tx slots (such as after tg3_init_hw)
5100          */
5101         netif_tx_wake_all_queues(tp->dev);
5102
5103         tg3_napi_enable(tp);
5104         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
5105         tg3_enable_ints(tp);
5106 }
5107
5108 static void tg3_irq_quiesce(struct tg3 *tp)
5109 {
5110         int i;
5111
5112         BUG_ON(tp->irq_sync);
5113
5114         tp->irq_sync = 1;
5115         smp_mb();
5116
5117         for (i = 0; i < tp->irq_cnt; i++)
5118                 synchronize_irq(tp->napi[i].irq_vec);
5119 }
5120
5121 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5122  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5123  * with as well.  Most of the time, this is not necessary except when
5124  * shutting down the device.
5125  */
5126 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5127 {
5128         spin_lock_bh(&tp->lock);
5129         if (irq_sync)
5130                 tg3_irq_quiesce(tp);
5131 }
5132
5133 static inline void tg3_full_unlock(struct tg3 *tp)
5134 {
5135         spin_unlock_bh(&tp->lock);
5136 }
5137
5138 /* One-shot MSI handler - Chip automatically disables interrupt
5139  * after sending MSI so driver doesn't have to do it.
5140  */
5141 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5142 {
5143         struct tg3_napi *tnapi = dev_id;
5144         struct tg3 *tp = tnapi->tp;
5145
5146         prefetch(tnapi->hw_status);
5147         if (tnapi->rx_rcb)
5148                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5149
5150         if (likely(!tg3_irq_sync(tp)))
5151                 napi_schedule(&tnapi->napi);
5152
5153         return IRQ_HANDLED;
5154 }
5155
5156 /* MSI ISR - No need to check for interrupt sharing and no need to
5157  * flush status block and interrupt mailbox. PCI ordering rules
5158  * guarantee that MSI will arrive after the status block.
5159  */
5160 static irqreturn_t tg3_msi(int irq, void *dev_id)
5161 {
5162         struct tg3_napi *tnapi = dev_id;
5163         struct tg3 *tp = tnapi->tp;
5164
5165         prefetch(tnapi->hw_status);
5166         if (tnapi->rx_rcb)
5167                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5168         /*
5169          * Writing any value to intr-mbox-0 clears PCI INTA# and
5170          * chip-internal interrupt pending events.
5171          * Writing non-zero to intr-mbox-0 additional tells the
5172          * NIC to stop sending us irqs, engaging "in-intr-handler"
5173          * event coalescing.
5174          */
5175         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5176         if (likely(!tg3_irq_sync(tp)))
5177                 napi_schedule(&tnapi->napi);
5178
5179         return IRQ_RETVAL(1);
5180 }
5181
5182 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5183 {
5184         struct tg3_napi *tnapi = dev_id;
5185         struct tg3 *tp = tnapi->tp;
5186         struct tg3_hw_status *sblk = tnapi->hw_status;
5187         unsigned int handled = 1;
5188
5189         /* In INTx mode, it is possible for the interrupt to arrive at
5190          * the CPU before the status block posted prior to the interrupt.
5191          * Reading the PCI State register will confirm whether the
5192          * interrupt is ours and will flush the status block.
5193          */
5194         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5195                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5196                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5197                         handled = 0;
5198                         goto out;
5199                 }
5200         }
5201
5202         /*
5203          * Writing any value to intr-mbox-0 clears PCI INTA# and
5204          * chip-internal interrupt pending events.
5205          * Writing non-zero to intr-mbox-0 additional tells the
5206          * NIC to stop sending us irqs, engaging "in-intr-handler"
5207          * event coalescing.
5208          *
5209          * Flush the mailbox to de-assert the IRQ immediately to prevent
5210          * spurious interrupts.  The flush impacts performance but
5211          * excessive spurious interrupts can be worse in some cases.
5212          */
5213         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5214         if (tg3_irq_sync(tp))
5215                 goto out;
5216         sblk->status &= ~SD_STATUS_UPDATED;
5217         if (likely(tg3_has_work(tnapi))) {
5218                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5219                 napi_schedule(&tnapi->napi);
5220         } else {
5221                 /* No work, shared interrupt perhaps?  re-enable
5222                  * interrupts, and flush that PCI write
5223                  */
5224                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5225                                0x00000000);
5226         }
5227 out:
5228         return IRQ_RETVAL(handled);
5229 }
5230
5231 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5232 {
5233         struct tg3_napi *tnapi = dev_id;
5234         struct tg3 *tp = tnapi->tp;
5235         struct tg3_hw_status *sblk = tnapi->hw_status;
5236         unsigned int handled = 1;
5237
5238         /* In INTx mode, it is possible for the interrupt to arrive at
5239          * the CPU before the status block posted prior to the interrupt.
5240          * Reading the PCI State register will confirm whether the
5241          * interrupt is ours and will flush the status block.
5242          */
5243         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5244                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5245                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5246                         handled = 0;
5247                         goto out;
5248                 }
5249         }
5250
5251         /*
5252          * writing any value to intr-mbox-0 clears PCI INTA# and
5253          * chip-internal interrupt pending events.
5254          * writing non-zero to intr-mbox-0 additional tells the
5255          * NIC to stop sending us irqs, engaging "in-intr-handler"
5256          * event coalescing.
5257          *
5258          * Flush the mailbox to de-assert the IRQ immediately to prevent
5259          * spurious interrupts.  The flush impacts performance but
5260          * excessive spurious interrupts can be worse in some cases.
5261          */
5262         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5263
5264         /*
5265          * In a shared interrupt configuration, sometimes other devices'
5266          * interrupts will scream.  We record the current status tag here
5267          * so that the above check can report that the screaming interrupts
5268          * are unhandled.  Eventually they will be silenced.
5269          */
5270         tnapi->last_irq_tag = sblk->status_tag;
5271
5272         if (tg3_irq_sync(tp))
5273                 goto out;
5274
5275         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5276
5277         napi_schedule(&tnapi->napi);
5278
5279 out:
5280         return IRQ_RETVAL(handled);
5281 }
5282
5283 /* ISR for interrupt test */
5284 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5285 {
5286         struct tg3_napi *tnapi = dev_id;
5287         struct tg3 *tp = tnapi->tp;
5288         struct tg3_hw_status *sblk = tnapi->hw_status;
5289
5290         if ((sblk->status & SD_STATUS_UPDATED) ||
5291             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5292                 tg3_disable_ints(tp);
5293                 return IRQ_RETVAL(1);
5294         }
5295         return IRQ_RETVAL(0);
5296 }
5297
5298 static int tg3_init_hw(struct tg3 *, int);
5299 static int tg3_halt(struct tg3 *, int, int);
5300
5301 /* Restart hardware after configuration changes, self-test, etc.
5302  * Invoked with tp->lock held.
5303  */
5304 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5305         __releases(tp->lock)
5306         __acquires(tp->lock)
5307 {
5308         int err;
5309
5310         err = tg3_init_hw(tp, reset_phy);
5311         if (err) {
5312                 netdev_err(tp->dev,
5313                            "Failed to re-initialize device, aborting\n");
5314                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5315                 tg3_full_unlock(tp);
5316                 del_timer_sync(&tp->timer);
5317                 tp->irq_sync = 0;
5318                 tg3_napi_enable(tp);
5319                 dev_close(tp->dev);
5320                 tg3_full_lock(tp, 0);
5321         }
5322         return err;
5323 }
5324
5325 #ifdef CONFIG_NET_POLL_CONTROLLER
5326 static void tg3_poll_controller(struct net_device *dev)
5327 {
5328         int i;
5329         struct tg3 *tp = netdev_priv(dev);
5330
5331         for (i = 0; i < tp->irq_cnt; i++)
5332                 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5333 }
5334 #endif
5335
5336 static void tg3_reset_task(struct work_struct *work)
5337 {
5338         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5339         int err;
5340         unsigned int restart_timer;
5341
5342         tg3_full_lock(tp, 0);
5343
5344         if (!netif_running(tp->dev)) {
5345                 tg3_full_unlock(tp);
5346                 return;
5347         }
5348
5349         tg3_full_unlock(tp);
5350
5351         tg3_phy_stop(tp);
5352
5353         tg3_netif_stop(tp);
5354
5355         tg3_full_lock(tp, 1);
5356
5357         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5358         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5359
5360         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5361                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5362                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5363                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5364                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5365         }
5366
5367         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5368         err = tg3_init_hw(tp, 1);
5369         if (err)
5370                 goto out;
5371
5372         tg3_netif_start(tp);
5373
5374         if (restart_timer)
5375                 mod_timer(&tp->timer, jiffies + 1);
5376
5377 out:
5378         tg3_full_unlock(tp);
5379
5380         if (!err)
5381                 tg3_phy_start(tp);
5382 }
5383
5384 static void tg3_dump_short_state(struct tg3 *tp)
5385 {
5386         netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5387                    tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5388         netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5389                    tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5390 }
5391
5392 static void tg3_tx_timeout(struct net_device *dev)
5393 {
5394         struct tg3 *tp = netdev_priv(dev);
5395
5396         if (netif_msg_tx_err(tp)) {
5397                 netdev_err(dev, "transmit timed out, resetting\n");
5398                 tg3_dump_short_state(tp);
5399         }
5400
5401         schedule_work(&tp->reset_task);
5402 }
5403
5404 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5405 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5406 {
5407         u32 base = (u32) mapping & 0xffffffff;
5408
5409         return (base > 0xffffdcc0) && (base + len + 8 < base);
5410 }
5411
5412 /* Test for DMA addresses > 40-bit */
5413 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5414                                           int len)
5415 {
5416 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5417         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5418                 return ((u64) mapping + len) > DMA_BIT_MASK(40);
5419         return 0;
5420 #else
5421         return 0;
5422 #endif
5423 }
5424
5425 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5426
5427 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5428 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5429                                        struct sk_buff *skb, u32 last_plus_one,
5430                                        u32 *start, u32 base_flags, u32 mss)
5431 {
5432         struct tg3 *tp = tnapi->tp;
5433         struct sk_buff *new_skb;
5434         dma_addr_t new_addr = 0;
5435         u32 entry = *start;
5436         int i, ret = 0;
5437
5438         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5439                 new_skb = skb_copy(skb, GFP_ATOMIC);
5440         else {
5441                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5442
5443                 new_skb = skb_copy_expand(skb,
5444                                           skb_headroom(skb) + more_headroom,
5445                                           skb_tailroom(skb), GFP_ATOMIC);
5446         }
5447
5448         if (!new_skb) {
5449                 ret = -1;
5450         } else {
5451                 /* New SKB is guaranteed to be linear. */
5452                 entry = *start;
5453                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5454                                           PCI_DMA_TODEVICE);
5455                 /* Make sure the mapping succeeded */
5456                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5457                         ret = -1;
5458                         dev_kfree_skb(new_skb);
5459                         new_skb = NULL;
5460
5461                 /* Make sure new skb does not cross any 4G boundaries.
5462                  * Drop the packet if it does.
5463                  */
5464                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5465                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5466                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5467                                          PCI_DMA_TODEVICE);
5468                         ret = -1;
5469                         dev_kfree_skb(new_skb);
5470                         new_skb = NULL;
5471                 } else {
5472                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5473                                     base_flags, 1 | (mss << 1));
5474                         *start = NEXT_TX(entry);
5475                 }
5476         }
5477
5478         /* Now clean up the sw ring entries. */
5479         i = 0;
5480         while (entry != last_plus_one) {
5481                 int len;
5482
5483                 if (i == 0)
5484                         len = skb_headlen(skb);
5485                 else
5486                         len = skb_shinfo(skb)->frags[i-1].size;
5487
5488                 pci_unmap_single(tp->pdev,
5489                                  dma_unmap_addr(&tnapi->tx_buffers[entry],
5490                                                 mapping),
5491                                  len, PCI_DMA_TODEVICE);
5492                 if (i == 0) {
5493                         tnapi->tx_buffers[entry].skb = new_skb;
5494                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5495                                            new_addr);
5496                 } else {
5497                         tnapi->tx_buffers[entry].skb = NULL;
5498                 }
5499                 entry = NEXT_TX(entry);
5500                 i++;
5501         }
5502
5503         dev_kfree_skb(skb);
5504
5505         return ret;
5506 }
5507
5508 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5509                         dma_addr_t mapping, int len, u32 flags,
5510                         u32 mss_and_is_end)
5511 {
5512         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5513         int is_end = (mss_and_is_end & 0x1);
5514         u32 mss = (mss_and_is_end >> 1);
5515         u32 vlan_tag = 0;
5516
5517         if (is_end)
5518                 flags |= TXD_FLAG_END;
5519         if (flags & TXD_FLAG_VLAN) {
5520                 vlan_tag = flags >> 16;
5521                 flags &= 0xffff;
5522         }
5523         vlan_tag |= (mss << TXD_MSS_SHIFT);
5524
5525         txd->addr_hi = ((u64) mapping >> 32);
5526         txd->addr_lo = ((u64) mapping & 0xffffffff);
5527         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5528         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5529 }
5530
5531 /* hard_start_xmit for devices that don't have any bugs and
5532  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5533  */
5534 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5535                                   struct net_device *dev)
5536 {
5537         struct tg3 *tp = netdev_priv(dev);
5538         u32 len, entry, base_flags, mss;
5539         dma_addr_t mapping;
5540         struct tg3_napi *tnapi;
5541         struct netdev_queue *txq;
5542         unsigned int i, last;
5543
5544         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5545         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5546         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5547                 tnapi++;
5548
5549         /* We are running in BH disabled context with netif_tx_lock
5550          * and TX reclaim runs via tp->napi.poll inside of a software
5551          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5552          * no IRQ context deadlocks to worry about either.  Rejoice!
5553          */
5554         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5555                 if (!netif_tx_queue_stopped(txq)) {
5556                         netif_tx_stop_queue(txq);
5557
5558                         /* This is a hard error, log it. */
5559                         netdev_err(dev,
5560                                    "BUG! Tx Ring full when queue awake!\n");
5561                 }
5562                 return NETDEV_TX_BUSY;
5563         }
5564
5565         entry = tnapi->tx_prod;
5566         base_flags = 0;
5567         mss = skb_shinfo(skb)->gso_size;
5568         if (mss) {
5569                 int tcp_opt_len, ip_tcp_len;
5570                 u32 hdrlen;
5571
5572                 if (skb_header_cloned(skb) &&
5573                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5574                         dev_kfree_skb(skb);
5575                         goto out_unlock;
5576                 }
5577
5578                 if (skb_is_gso_v6(skb)) {
5579                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5580                 } else {
5581                         struct iphdr *iph = ip_hdr(skb);
5582
5583                         tcp_opt_len = tcp_optlen(skb);
5584                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5585
5586                         iph->check = 0;
5587                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5588                         hdrlen = ip_tcp_len + tcp_opt_len;
5589                 }
5590
5591                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5592                         mss |= (hdrlen & 0xc) << 12;
5593                         if (hdrlen & 0x10)
5594                                 base_flags |= 0x00000010;
5595                         base_flags |= (hdrlen & 0x3e0) << 5;
5596                 } else
5597                         mss |= hdrlen << 9;
5598
5599                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5600                                TXD_FLAG_CPU_POST_DMA);
5601
5602                 tcp_hdr(skb)->check = 0;
5603
5604         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5605                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5606         }
5607
5608 #if TG3_VLAN_TAG_USED
5609         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5610                 base_flags |= (TXD_FLAG_VLAN |
5611                                (vlan_tx_tag_get(skb) << 16));
5612 #endif
5613
5614         len = skb_headlen(skb);
5615
5616         /* Queue skb data, a.k.a. the main skb fragment. */
5617         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5618         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5619                 dev_kfree_skb(skb);
5620                 goto out_unlock;
5621         }
5622
5623         tnapi->tx_buffers[entry].skb = skb;
5624         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5625
5626         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5627             !mss && skb->len > ETH_DATA_LEN)
5628                 base_flags |= TXD_FLAG_JMB_PKT;
5629
5630         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5631                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5632
5633         entry = NEXT_TX(entry);
5634
5635         /* Now loop through additional data fragments, and queue them. */
5636         if (skb_shinfo(skb)->nr_frags > 0) {
5637                 last = skb_shinfo(skb)->nr_frags - 1;
5638                 for (i = 0; i <= last; i++) {
5639                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5640
5641                         len = frag->size;
5642                         mapping = pci_map_page(tp->pdev,
5643                                                frag->page,
5644                                                frag->page_offset,
5645                                                len, PCI_DMA_TODEVICE);
5646                         if (pci_dma_mapping_error(tp->pdev, mapping))
5647                                 goto dma_error;
5648
5649                         tnapi->tx_buffers[entry].skb = NULL;
5650                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5651                                            mapping);
5652
5653                         tg3_set_txd(tnapi, entry, mapping, len,
5654                                     base_flags, (i == last) | (mss << 1));
5655
5656                         entry = NEXT_TX(entry);
5657                 }
5658         }
5659
5660         /* Packets are ready, update Tx producer idx local and on card. */
5661         tw32_tx_mbox(tnapi->prodmbox, entry);
5662
5663         tnapi->tx_prod = entry;
5664         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5665                 netif_tx_stop_queue(txq);
5666
5667                 /* netif_tx_stop_queue() must be done before checking
5668                  * checking tx index in tg3_tx_avail() below, because in
5669                  * tg3_tx(), we update tx index before checking for
5670                  * netif_tx_queue_stopped().
5671                  */
5672                 smp_mb();
5673                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5674                         netif_tx_wake_queue(txq);
5675         }
5676
5677 out_unlock:
5678         mmiowb();
5679
5680         return NETDEV_TX_OK;
5681
5682 dma_error:
5683         last = i;
5684         entry = tnapi->tx_prod;
5685         tnapi->tx_buffers[entry].skb = NULL;
5686         pci_unmap_single(tp->pdev,
5687                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5688                          skb_headlen(skb),
5689                          PCI_DMA_TODEVICE);
5690         for (i = 0; i <= last; i++) {
5691                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5692                 entry = NEXT_TX(entry);
5693
5694                 pci_unmap_page(tp->pdev,
5695                                dma_unmap_addr(&tnapi->tx_buffers[entry],
5696                                               mapping),
5697                                frag->size, PCI_DMA_TODEVICE);
5698         }
5699
5700         dev_kfree_skb(skb);
5701         return NETDEV_TX_OK;
5702 }
5703
5704 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5705                                           struct net_device *);
5706
5707 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5708  * TSO header is greater than 80 bytes.
5709  */
5710 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5711 {
5712         struct sk_buff *segs, *nskb;
5713         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5714
5715         /* Estimate the number of fragments in the worst case */
5716         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5717                 netif_stop_queue(tp->dev);
5718
5719                 /* netif_tx_stop_queue() must be done before checking
5720                  * checking tx index in tg3_tx_avail() below, because in
5721                  * tg3_tx(), we update tx index before checking for
5722                  * netif_tx_queue_stopped().
5723                  */
5724                 smp_mb();
5725                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5726                         return NETDEV_TX_BUSY;
5727
5728                 netif_wake_queue(tp->dev);
5729         }
5730
5731         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5732         if (IS_ERR(segs))
5733                 goto tg3_tso_bug_end;
5734
5735         do {
5736                 nskb = segs;
5737                 segs = segs->next;
5738                 nskb->next = NULL;
5739                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5740         } while (segs);
5741
5742 tg3_tso_bug_end:
5743         dev_kfree_skb(skb);
5744
5745         return NETDEV_TX_OK;
5746 }
5747
5748 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5749  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5750  */
5751 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5752                                           struct net_device *dev)
5753 {
5754         struct tg3 *tp = netdev_priv(dev);
5755         u32 len, entry, base_flags, mss;
5756         int would_hit_hwbug;
5757         dma_addr_t mapping;
5758         struct tg3_napi *tnapi;
5759         struct netdev_queue *txq;
5760         unsigned int i, last;
5761
5762         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5763         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5764         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5765                 tnapi++;
5766
5767         /* We are running in BH disabled context with netif_tx_lock
5768          * and TX reclaim runs via tp->napi.poll inside of a software
5769          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5770          * no IRQ context deadlocks to worry about either.  Rejoice!
5771          */
5772         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5773                 if (!netif_tx_queue_stopped(txq)) {
5774                         netif_tx_stop_queue(txq);
5775
5776                         /* This is a hard error, log it. */
5777                         netdev_err(dev,
5778                                    "BUG! Tx Ring full when queue awake!\n");
5779                 }
5780                 return NETDEV_TX_BUSY;
5781         }
5782
5783         entry = tnapi->tx_prod;
5784         base_flags = 0;
5785         if (skb->ip_summed == CHECKSUM_PARTIAL)
5786                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5787
5788         mss = skb_shinfo(skb)->gso_size;
5789         if (mss) {
5790                 struct iphdr *iph;
5791                 u32 tcp_opt_len, hdr_len;
5792
5793                 if (skb_header_cloned(skb) &&
5794                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5795                         dev_kfree_skb(skb);
5796                         goto out_unlock;
5797                 }
5798
5799                 iph = ip_hdr(skb);
5800                 tcp_opt_len = tcp_optlen(skb);
5801
5802                 if (skb_is_gso_v6(skb)) {
5803                         hdr_len = skb_headlen(skb) - ETH_HLEN;
5804                 } else {
5805                         u32 ip_tcp_len;
5806
5807                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5808                         hdr_len = ip_tcp_len + tcp_opt_len;
5809
5810                         iph->check = 0;
5811                         iph->tot_len = htons(mss + hdr_len);
5812                 }
5813
5814                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5815                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5816                         return tg3_tso_bug(tp, skb);
5817
5818                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5819                                TXD_FLAG_CPU_POST_DMA);
5820
5821                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5822                         tcp_hdr(skb)->check = 0;
5823                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5824                 } else
5825                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5826                                                                  iph->daddr, 0,
5827                                                                  IPPROTO_TCP,
5828                                                                  0);
5829
5830                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5831                         mss |= (hdr_len & 0xc) << 12;
5832                         if (hdr_len & 0x10)
5833                                 base_flags |= 0x00000010;
5834                         base_flags |= (hdr_len & 0x3e0) << 5;
5835                 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5836                         mss |= hdr_len << 9;
5837                 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5838                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5839                         if (tcp_opt_len || iph->ihl > 5) {
5840                                 int tsflags;
5841
5842                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5843                                 mss |= (tsflags << 11);
5844                         }
5845                 } else {
5846                         if (tcp_opt_len || iph->ihl > 5) {
5847                                 int tsflags;
5848
5849                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5850                                 base_flags |= tsflags << 12;
5851                         }
5852                 }
5853         }
5854 #if TG3_VLAN_TAG_USED
5855         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5856                 base_flags |= (TXD_FLAG_VLAN |
5857                                (vlan_tx_tag_get(skb) << 16));
5858 #endif
5859
5860         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5861             !mss && skb->len > ETH_DATA_LEN)
5862                 base_flags |= TXD_FLAG_JMB_PKT;
5863
5864         len = skb_headlen(skb);
5865
5866         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5867         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5868                 dev_kfree_skb(skb);
5869                 goto out_unlock;
5870         }
5871
5872         tnapi->tx_buffers[entry].skb = skb;
5873         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5874
5875         would_hit_hwbug = 0;
5876
5877         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5878                 would_hit_hwbug = 1;
5879
5880         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5881             tg3_4g_overflow_test(mapping, len))
5882                 would_hit_hwbug = 1;
5883
5884         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5885             tg3_40bit_overflow_test(tp, mapping, len))
5886                 would_hit_hwbug = 1;
5887
5888         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5889                 would_hit_hwbug = 1;
5890
5891         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5892                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5893
5894         entry = NEXT_TX(entry);
5895
5896         /* Now loop through additional data fragments, and queue them. */
5897         if (skb_shinfo(skb)->nr_frags > 0) {
5898                 last = skb_shinfo(skb)->nr_frags - 1;
5899                 for (i = 0; i <= last; i++) {
5900                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5901
5902                         len = frag->size;
5903                         mapping = pci_map_page(tp->pdev,
5904                                                frag->page,
5905                                                frag->page_offset,
5906                                                len, PCI_DMA_TODEVICE);
5907
5908                         tnapi->tx_buffers[entry].skb = NULL;
5909                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5910                                            mapping);
5911                         if (pci_dma_mapping_error(tp->pdev, mapping))
5912                                 goto dma_error;
5913
5914                         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5915                             len <= 8)
5916                                 would_hit_hwbug = 1;
5917
5918                         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5919                             tg3_4g_overflow_test(mapping, len))
5920                                 would_hit_hwbug = 1;
5921
5922                         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5923                             tg3_40bit_overflow_test(tp, mapping, len))
5924                                 would_hit_hwbug = 1;
5925
5926                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5927                                 tg3_set_txd(tnapi, entry, mapping, len,
5928                                             base_flags, (i == last)|(mss << 1));
5929                         else
5930                                 tg3_set_txd(tnapi, entry, mapping, len,
5931                                             base_flags, (i == last));
5932
5933                         entry = NEXT_TX(entry);
5934                 }
5935         }
5936
5937         if (would_hit_hwbug) {
5938                 u32 last_plus_one = entry;
5939                 u32 start;
5940
5941                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5942                 start &= (TG3_TX_RING_SIZE - 1);
5943
5944                 /* If the workaround fails due to memory/mapping
5945                  * failure, silently drop this packet.
5946                  */
5947                 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
5948                                                 &start, base_flags, mss))
5949                         goto out_unlock;
5950
5951                 entry = start;
5952         }
5953
5954         /* Packets are ready, update Tx producer idx local and on card. */
5955         tw32_tx_mbox(tnapi->prodmbox, entry);
5956
5957         tnapi->tx_prod = entry;
5958         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5959                 netif_tx_stop_queue(txq);
5960
5961                 /* netif_tx_stop_queue() must be done before checking
5962                  * checking tx index in tg3_tx_avail() below, because in
5963                  * tg3_tx(), we update tx index before checking for
5964                  * netif_tx_queue_stopped().
5965                  */
5966                 smp_mb();
5967                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5968                         netif_tx_wake_queue(txq);
5969         }
5970
5971 out_unlock:
5972         mmiowb();
5973
5974         return NETDEV_TX_OK;
5975
5976 dma_error:
5977         last = i;
5978         entry = tnapi->tx_prod;
5979         tnapi->tx_buffers[entry].skb = NULL;
5980         pci_unmap_single(tp->pdev,
5981                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5982                          skb_headlen(skb),
5983                          PCI_DMA_TODEVICE);
5984         for (i = 0; i <= last; i++) {
5985                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5986                 entry = NEXT_TX(entry);
5987
5988                 pci_unmap_page(tp->pdev,
5989                                dma_unmap_addr(&tnapi->tx_buffers[entry],
5990                                               mapping),
5991                                frag->size, PCI_DMA_TODEVICE);
5992         }
5993
5994         dev_kfree_skb(skb);
5995         return NETDEV_TX_OK;
5996 }
5997
5998 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5999                                int new_mtu)
6000 {
6001         dev->mtu = new_mtu;
6002
6003         if (new_mtu > ETH_DATA_LEN) {
6004                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6005                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
6006                         ethtool_op_set_tso(dev, 0);
6007                 } else {
6008                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
6009                 }
6010         } else {
6011                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6012                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
6013                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
6014         }
6015 }
6016
6017 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
6018 {
6019         struct tg3 *tp = netdev_priv(dev);
6020         int err;
6021
6022         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
6023                 return -EINVAL;
6024
6025         if (!netif_running(dev)) {
6026                 /* We'll just catch it later when the
6027                  * device is up'd.
6028                  */
6029                 tg3_set_mtu(dev, tp, new_mtu);
6030                 return 0;
6031         }
6032
6033         tg3_phy_stop(tp);
6034
6035         tg3_netif_stop(tp);
6036
6037         tg3_full_lock(tp, 1);
6038
6039         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6040
6041         tg3_set_mtu(dev, tp, new_mtu);
6042
6043         err = tg3_restart_hw(tp, 0);
6044
6045         if (!err)
6046                 tg3_netif_start(tp);
6047
6048         tg3_full_unlock(tp);
6049
6050         if (!err)
6051                 tg3_phy_start(tp);
6052
6053         return err;
6054 }
6055
6056 static void tg3_rx_prodring_free(struct tg3 *tp,
6057                                  struct tg3_rx_prodring_set *tpr)
6058 {
6059         int i;
6060
6061         if (tpr != &tp->napi[0].prodring) {
6062                 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
6063                      i = (i + 1) % TG3_RX_RING_SIZE)
6064                         tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6065                                         tp->rx_pkt_map_sz);
6066
6067                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6068                         for (i = tpr->rx_jmb_cons_idx;
6069                              i != tpr->rx_jmb_prod_idx;
6070                              i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
6071                                 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6072                                                 TG3_RX_JMB_MAP_SZ);
6073                         }
6074                 }
6075
6076                 return;
6077         }
6078
6079         for (i = 0; i < TG3_RX_RING_SIZE; i++)
6080                 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6081                                 tp->rx_pkt_map_sz);
6082
6083         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6084                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
6085                         tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6086                                         TG3_RX_JMB_MAP_SZ);
6087         }
6088 }
6089
6090 /* Initialize rx rings for packet processing.
6091  *
6092  * The chip has been shut down and the driver detached from
6093  * the networking, so no interrupts or new tx packets will
6094  * end up in the driver.  tp->{tx,}lock are held and thus
6095  * we may not sleep.
6096  */
6097 static int tg3_rx_prodring_alloc(struct tg3 *tp,
6098                                  struct tg3_rx_prodring_set *tpr)
6099 {
6100         u32 i, rx_pkt_dma_sz;
6101
6102         tpr->rx_std_cons_idx = 0;
6103         tpr->rx_std_prod_idx = 0;
6104         tpr->rx_jmb_cons_idx = 0;
6105         tpr->rx_jmb_prod_idx = 0;
6106
6107         if (tpr != &tp->napi[0].prodring) {
6108                 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
6109                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
6110                         memset(&tpr->rx_jmb_buffers[0], 0,
6111                                TG3_RX_JMB_BUFF_RING_SIZE);
6112                 goto done;
6113         }
6114
6115         /* Zero out all descriptors. */
6116         memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
6117
6118         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6119         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
6120             tp->dev->mtu > ETH_DATA_LEN)
6121                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6122         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6123
6124         /* Initialize invariants of the rings, we only set this
6125          * stuff once.  This works because the card does not
6126          * write into the rx buffer posting rings.
6127          */
6128         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
6129                 struct tg3_rx_buffer_desc *rxd;
6130
6131                 rxd = &tpr->rx_std[i];
6132                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6133                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6134                 rxd->opaque = (RXD_OPAQUE_RING_STD |
6135                                (i << RXD_OPAQUE_INDEX_SHIFT));
6136         }
6137
6138         /* Now allocate fresh SKBs for each rx ring. */
6139         for (i = 0; i < tp->rx_pending; i++) {
6140                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6141                         netdev_warn(tp->dev,
6142                                     "Using a smaller RX standard ring. Only "
6143                                     "%d out of %d buffers were allocated "
6144                                     "successfully\n", i, tp->rx_pending);
6145                         if (i == 0)
6146                                 goto initfail;
6147                         tp->rx_pending = i;
6148                         break;
6149                 }
6150         }
6151
6152         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6153                 goto done;
6154
6155         memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
6156
6157         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
6158                 goto done;
6159
6160         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
6161                 struct tg3_rx_buffer_desc *rxd;
6162
6163                 rxd = &tpr->rx_jmb[i].std;
6164                 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6165                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6166                                   RXD_FLAG_JUMBO;
6167                 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6168                        (i << RXD_OPAQUE_INDEX_SHIFT));
6169         }
6170
6171         for (i = 0; i < tp->rx_jumbo_pending; i++) {
6172                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
6173                         netdev_warn(tp->dev,
6174                                     "Using a smaller RX jumbo ring. Only %d "
6175                                     "out of %d buffers were allocated "
6176                                     "successfully\n", i, tp->rx_jumbo_pending);
6177                         if (i == 0)
6178                                 goto initfail;
6179                         tp->rx_jumbo_pending = i;
6180                         break;
6181                 }
6182         }
6183
6184 done:
6185         return 0;
6186
6187 initfail:
6188         tg3_rx_prodring_free(tp, tpr);
6189         return -ENOMEM;
6190 }
6191
6192 static void tg3_rx_prodring_fini(struct tg3 *tp,
6193                                  struct tg3_rx_prodring_set *tpr)
6194 {
6195         kfree(tpr->rx_std_buffers);
6196         tpr->rx_std_buffers = NULL;
6197         kfree(tpr->rx_jmb_buffers);
6198         tpr->rx_jmb_buffers = NULL;
6199         if (tpr->rx_std) {
6200                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
6201                                     tpr->rx_std, tpr->rx_std_mapping);
6202                 tpr->rx_std = NULL;
6203         }
6204         if (tpr->rx_jmb) {
6205                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
6206                                     tpr->rx_jmb, tpr->rx_jmb_mapping);
6207                 tpr->rx_jmb = NULL;
6208         }
6209 }
6210
6211 static int tg3_rx_prodring_init(struct tg3 *tp,
6212                                 struct tg3_rx_prodring_set *tpr)
6213 {
6214         tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
6215         if (!tpr->rx_std_buffers)
6216                 return -ENOMEM;
6217
6218         tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6219                                            &tpr->rx_std_mapping);
6220         if (!tpr->rx_std)
6221                 goto err_out;
6222
6223         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6224                 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
6225                                               GFP_KERNEL);
6226                 if (!tpr->rx_jmb_buffers)
6227                         goto err_out;
6228
6229                 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6230                                                    TG3_RX_JUMBO_RING_BYTES,
6231                                                    &tpr->rx_jmb_mapping);
6232                 if (!tpr->rx_jmb)
6233                         goto err_out;
6234         }
6235
6236         return 0;
6237
6238 err_out:
6239         tg3_rx_prodring_fini(tp, tpr);
6240         return -ENOMEM;
6241 }
6242
6243 /* Free up pending packets in all rx/tx rings.
6244  *
6245  * The chip has been shut down and the driver detached from
6246  * the networking, so no interrupts or new tx packets will
6247  * end up in the driver.  tp->{tx,}lock is not held and we are not
6248  * in an interrupt context and thus may sleep.
6249  */
6250 static void tg3_free_rings(struct tg3 *tp)
6251 {
6252         int i, j;
6253
6254         for (j = 0; j < tp->irq_cnt; j++) {
6255                 struct tg3_napi *tnapi = &tp->napi[j];
6256
6257                 tg3_rx_prodring_free(tp, &tnapi->prodring);
6258
6259                 if (!tnapi->tx_buffers)
6260                         continue;
6261
6262                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6263                         struct ring_info *txp;
6264                         struct sk_buff *skb;
6265                         unsigned int k;
6266
6267                         txp = &tnapi->tx_buffers[i];
6268                         skb = txp->skb;
6269
6270                         if (skb == NULL) {
6271                                 i++;
6272                                 continue;
6273                         }
6274
6275                         pci_unmap_single(tp->pdev,
6276                                          dma_unmap_addr(txp, mapping),
6277                                          skb_headlen(skb),
6278                                          PCI_DMA_TODEVICE);
6279                         txp->skb = NULL;
6280
6281                         i++;
6282
6283                         for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6284                                 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6285                                 pci_unmap_page(tp->pdev,
6286                                                dma_unmap_addr(txp, mapping),
6287                                                skb_shinfo(skb)->frags[k].size,
6288                                                PCI_DMA_TODEVICE);
6289                                 i++;
6290                         }
6291
6292                         dev_kfree_skb_any(skb);
6293                 }
6294         }
6295 }
6296
6297 /* Initialize tx/rx rings for packet processing.
6298  *
6299  * The chip has been shut down and the driver detached from
6300  * the networking, so no interrupts or new tx packets will
6301  * end up in the driver.  tp->{tx,}lock are held and thus
6302  * we may not sleep.
6303  */
6304 static int tg3_init_rings(struct tg3 *tp)
6305 {
6306         int i;
6307
6308         /* Free up all the SKBs. */
6309         tg3_free_rings(tp);
6310
6311         for (i = 0; i < tp->irq_cnt; i++) {
6312                 struct tg3_napi *tnapi = &tp->napi[i];
6313
6314                 tnapi->last_tag = 0;
6315                 tnapi->last_irq_tag = 0;
6316                 tnapi->hw_status->status = 0;
6317                 tnapi->hw_status->status_tag = 0;
6318                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6319
6320                 tnapi->tx_prod = 0;
6321                 tnapi->tx_cons = 0;
6322                 if (tnapi->tx_ring)
6323                         memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6324
6325                 tnapi->rx_rcb_ptr = 0;
6326                 if (tnapi->rx_rcb)
6327                         memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6328
6329                 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
6330                         tg3_free_rings(tp);
6331                         return -ENOMEM;
6332                 }
6333         }
6334
6335         return 0;
6336 }
6337
6338 /*
6339  * Must not be invoked with interrupt sources disabled and
6340  * the hardware shutdown down.
6341  */
6342 static void tg3_free_consistent(struct tg3 *tp)
6343 {
6344         int i;
6345
6346         for (i = 0; i < tp->irq_cnt; i++) {
6347                 struct tg3_napi *tnapi = &tp->napi[i];
6348
6349                 if (tnapi->tx_ring) {
6350                         pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6351                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
6352                         tnapi->tx_ring = NULL;
6353                 }
6354
6355                 kfree(tnapi->tx_buffers);
6356                 tnapi->tx_buffers = NULL;
6357
6358                 if (tnapi->rx_rcb) {
6359                         pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6360                                             tnapi->rx_rcb,
6361                                             tnapi->rx_rcb_mapping);
6362                         tnapi->rx_rcb = NULL;
6363                 }
6364
6365                 tg3_rx_prodring_fini(tp, &tnapi->prodring);
6366
6367                 if (tnapi->hw_status) {
6368                         pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6369                                             tnapi->hw_status,
6370                                             tnapi->status_mapping);
6371                         tnapi->hw_status = NULL;
6372                 }
6373         }
6374
6375         if (tp->hw_stats) {
6376                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6377                                     tp->hw_stats, tp->stats_mapping);
6378                 tp->hw_stats = NULL;
6379         }
6380 }
6381
6382 /*
6383  * Must not be invoked with interrupt sources disabled and
6384  * the hardware shutdown down.  Can sleep.
6385  */
6386 static int tg3_alloc_consistent(struct tg3 *tp)
6387 {
6388         int i;
6389
6390         tp->hw_stats = pci_alloc_consistent(tp->pdev,
6391                                             sizeof(struct tg3_hw_stats),
6392                                             &tp->stats_mapping);
6393         if (!tp->hw_stats)
6394                 goto err_out;
6395
6396         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6397
6398         for (i = 0; i < tp->irq_cnt; i++) {
6399                 struct tg3_napi *tnapi = &tp->napi[i];
6400                 struct tg3_hw_status *sblk;
6401
6402                 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6403                                                         TG3_HW_STATUS_SIZE,
6404                                                         &tnapi->status_mapping);
6405                 if (!tnapi->hw_status)
6406                         goto err_out;
6407
6408                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6409                 sblk = tnapi->hw_status;
6410
6411                 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
6412                         goto err_out;
6413
6414                 /* If multivector TSS is enabled, vector 0 does not handle
6415                  * tx interrupts.  Don't allocate any resources for it.
6416                  */
6417                 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6418                     (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6419                         tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6420                                                     TG3_TX_RING_SIZE,
6421                                                     GFP_KERNEL);
6422                         if (!tnapi->tx_buffers)
6423                                 goto err_out;
6424
6425                         tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6426                                                               TG3_TX_RING_BYTES,
6427                                                        &tnapi->tx_desc_mapping);
6428                         if (!tnapi->tx_ring)
6429                                 goto err_out;
6430                 }
6431
6432                 /*
6433                  * When RSS is enabled, the status block format changes
6434                  * slightly.  The "rx_jumbo_consumer", "reserved",
6435                  * and "rx_mini_consumer" members get mapped to the
6436                  * other three rx return ring producer indexes.
6437                  */
6438                 switch (i) {
6439                 default:
6440                         tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6441                         break;
6442                 case 2:
6443                         tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6444                         break;
6445                 case 3:
6446                         tnapi->rx_rcb_prod_idx = &sblk->reserved;
6447                         break;
6448                 case 4:
6449                         tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6450                         break;
6451                 }
6452
6453                 /*
6454                  * If multivector RSS is enabled, vector 0 does not handle
6455                  * rx or tx interrupts.  Don't allocate any resources for it.
6456                  */
6457                 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6458                         continue;
6459
6460                 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6461                                                      TG3_RX_RCB_RING_BYTES(tp),
6462                                                      &tnapi->rx_rcb_mapping);
6463                 if (!tnapi->rx_rcb)
6464                         goto err_out;
6465
6466                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6467         }
6468
6469         return 0;
6470
6471 err_out:
6472         tg3_free_consistent(tp);
6473         return -ENOMEM;
6474 }
6475
6476 #define MAX_WAIT_CNT 1000
6477
6478 /* To stop a block, clear the enable bit and poll till it
6479  * clears.  tp->lock is held.
6480  */
6481 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6482 {
6483         unsigned int i;
6484         u32 val;
6485
6486         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6487                 switch (ofs) {
6488                 case RCVLSC_MODE:
6489                 case DMAC_MODE:
6490                 case MBFREE_MODE:
6491                 case BUFMGR_MODE:
6492                 case MEMARB_MODE:
6493                         /* We can't enable/disable these bits of the
6494                          * 5705/5750, just say success.
6495                          */
6496                         return 0;
6497
6498                 default:
6499                         break;
6500                 }
6501         }
6502
6503         val = tr32(ofs);
6504         val &= ~enable_bit;
6505         tw32_f(ofs, val);
6506
6507         for (i = 0; i < MAX_WAIT_CNT; i++) {
6508                 udelay(100);
6509                 val = tr32(ofs);
6510                 if ((val & enable_bit) == 0)
6511                         break;
6512         }
6513
6514         if (i == MAX_WAIT_CNT && !silent) {
6515                 dev_err(&tp->pdev->dev,
6516                         "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6517                         ofs, enable_bit);
6518                 return -ENODEV;
6519         }
6520
6521         return 0;
6522 }
6523
6524 /* tp->lock is held. */
6525 static int tg3_abort_hw(struct tg3 *tp, int silent)
6526 {
6527         int i, err;
6528
6529         tg3_disable_ints(tp);
6530
6531         tp->rx_mode &= ~RX_MODE_ENABLE;
6532         tw32_f(MAC_RX_MODE, tp->rx_mode);
6533         udelay(10);
6534
6535         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6536         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6537         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6538         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6539         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6540         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6541
6542         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6543         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6544         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6545         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6546         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6547         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6548         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6549
6550         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6551         tw32_f(MAC_MODE, tp->mac_mode);
6552         udelay(40);
6553
6554         tp->tx_mode &= ~TX_MODE_ENABLE;
6555         tw32_f(MAC_TX_MODE, tp->tx_mode);
6556
6557         for (i = 0; i < MAX_WAIT_CNT; i++) {
6558                 udelay(100);
6559                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6560                         break;
6561         }
6562         if (i >= MAX_WAIT_CNT) {
6563                 dev_err(&tp->pdev->dev,
6564                         "%s timed out, TX_MODE_ENABLE will not clear "
6565                         "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
6566                 err |= -ENODEV;
6567         }
6568
6569         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6570         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6571         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6572
6573         tw32(FTQ_RESET, 0xffffffff);
6574         tw32(FTQ_RESET, 0x00000000);
6575
6576         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6577         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6578
6579         for (i = 0; i < tp->irq_cnt; i++) {
6580                 struct tg3_napi *tnapi = &tp->napi[i];
6581                 if (tnapi->hw_status)
6582                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6583         }
6584         if (tp->hw_stats)
6585                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6586
6587         return err;
6588 }
6589
6590 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6591 {
6592         int i;
6593         u32 apedata;
6594
6595         /* NCSI does not support APE events */
6596         if (tp->tg3_flags3 & TG3_FLG3_APE_HAS_NCSI)
6597                 return;
6598
6599         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6600         if (apedata != APE_SEG_SIG_MAGIC)
6601                 return;
6602
6603         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6604         if (!(apedata & APE_FW_STATUS_READY))
6605                 return;
6606
6607         /* Wait for up to 1 millisecond for APE to service previous event. */
6608         for (i = 0; i < 10; i++) {
6609                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6610                         return;
6611
6612                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6613
6614                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6615                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6616                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6617
6618                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6619
6620                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6621                         break;
6622
6623                 udelay(100);
6624         }
6625
6626         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6627                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6628 }
6629
6630 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6631 {
6632         u32 event;
6633         u32 apedata;
6634
6635         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6636                 return;
6637
6638         switch (kind) {
6639         case RESET_KIND_INIT:
6640                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6641                                 APE_HOST_SEG_SIG_MAGIC);
6642                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6643                                 APE_HOST_SEG_LEN_MAGIC);
6644                 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6645                 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6646                 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6647                         APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
6648                 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6649                                 APE_HOST_BEHAV_NO_PHYLOCK);
6650                 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
6651                                     TG3_APE_HOST_DRVR_STATE_START);
6652
6653                 event = APE_EVENT_STATUS_STATE_START;
6654                 break;
6655         case RESET_KIND_SHUTDOWN:
6656                 /* With the interface we are currently using,
6657                  * APE does not track driver state.  Wiping
6658                  * out the HOST SEGMENT SIGNATURE forces
6659                  * the APE to assume OS absent status.
6660                  */
6661                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6662
6663                 if (device_may_wakeup(&tp->pdev->dev) &&
6664                     (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) {
6665                         tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
6666                                             TG3_APE_HOST_WOL_SPEED_AUTO);
6667                         apedata = TG3_APE_HOST_DRVR_STATE_WOL;
6668                 } else
6669                         apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
6670
6671                 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
6672
6673                 event = APE_EVENT_STATUS_STATE_UNLOAD;
6674                 break;
6675         case RESET_KIND_SUSPEND:
6676                 event = APE_EVENT_STATUS_STATE_SUSPEND;
6677                 break;
6678         default:
6679                 return;
6680         }
6681
6682         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6683
6684         tg3_ape_send_event(tp, event);
6685 }
6686
6687 /* tp->lock is held. */
6688 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6689 {
6690         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6691                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6692
6693         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6694                 switch (kind) {
6695                 case RESET_KIND_INIT:
6696                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6697                                       DRV_STATE_START);
6698                         break;
6699
6700                 case RESET_KIND_SHUTDOWN:
6701                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6702                                       DRV_STATE_UNLOAD);
6703                         break;
6704
6705                 case RESET_KIND_SUSPEND:
6706                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6707                                       DRV_STATE_SUSPEND);
6708                         break;
6709
6710                 default:
6711                         break;
6712                 }
6713         }
6714
6715         if (kind == RESET_KIND_INIT ||
6716             kind == RESET_KIND_SUSPEND)
6717                 tg3_ape_driver_state_change(tp, kind);
6718 }
6719
6720 /* tp->lock is held. */
6721 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6722 {
6723         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6724                 switch (kind) {
6725                 case RESET_KIND_INIT:
6726                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6727                                       DRV_STATE_START_DONE);
6728                         break;
6729
6730                 case RESET_KIND_SHUTDOWN:
6731                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6732                                       DRV_STATE_UNLOAD_DONE);
6733                         break;
6734
6735                 default:
6736                         break;
6737                 }
6738         }
6739
6740         if (kind == RESET_KIND_SHUTDOWN)
6741                 tg3_ape_driver_state_change(tp, kind);
6742 }
6743
6744 /* tp->lock is held. */
6745 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6746 {
6747         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6748                 switch (kind) {
6749                 case RESET_KIND_INIT:
6750                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6751                                       DRV_STATE_START);
6752                         break;
6753
6754                 case RESET_KIND_SHUTDOWN:
6755                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6756                                       DRV_STATE_UNLOAD);
6757                         break;
6758
6759                 case RESET_KIND_SUSPEND:
6760                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6761                                       DRV_STATE_SUSPEND);
6762                         break;
6763
6764                 default:
6765                         break;
6766                 }
6767         }
6768 }
6769
6770 static int tg3_poll_fw(struct tg3 *tp)
6771 {
6772         int i;
6773         u32 val;
6774
6775         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6776                 /* Wait up to 20ms for init done. */
6777                 for (i = 0; i < 200; i++) {
6778                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6779                                 return 0;
6780                         udelay(100);
6781                 }
6782                 return -ENODEV;
6783         }
6784
6785         /* Wait for firmware initialization to complete. */
6786         for (i = 0; i < 100000; i++) {
6787                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6788                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6789                         break;
6790                 udelay(10);
6791         }
6792
6793         /* Chip might not be fitted with firmware.  Some Sun onboard
6794          * parts are configured like that.  So don't signal the timeout
6795          * of the above loop as an error, but do report the lack of
6796          * running firmware once.
6797          */
6798         if (i >= 100000 &&
6799             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6800                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6801
6802                 netdev_info(tp->dev, "No firmware running\n");
6803         }
6804
6805         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6806                 /* The 57765 A0 needs a little more
6807                  * time to do some important work.
6808                  */
6809                 mdelay(10);
6810         }
6811
6812         return 0;
6813 }
6814
6815 /* Save PCI command register before chip reset */
6816 static void tg3_save_pci_state(struct tg3 *tp)
6817 {
6818         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6819 }
6820
6821 /* Restore PCI state after chip reset */
6822 static void tg3_restore_pci_state(struct tg3 *tp)
6823 {
6824         u32 val;
6825
6826         /* Re-enable indirect register accesses. */
6827         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6828                                tp->misc_host_ctrl);
6829
6830         /* Set MAX PCI retry to zero. */
6831         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6832         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6833             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6834                 val |= PCISTATE_RETRY_SAME_DMA;
6835         /* Allow reads and writes to the APE register and memory space. */
6836         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6837                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6838                        PCISTATE_ALLOW_APE_SHMEM_WR |
6839                        PCISTATE_ALLOW_APE_PSPACE_WR;
6840         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6841
6842         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6843
6844         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6845                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6846                         pcie_set_readrq(tp->pdev, 4096);
6847                 else {
6848                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6849                                               tp->pci_cacheline_sz);
6850                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6851                                               tp->pci_lat_timer);
6852                 }
6853         }
6854
6855         /* Make sure PCI-X relaxed ordering bit is clear. */
6856         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6857                 u16 pcix_cmd;
6858
6859                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6860                                      &pcix_cmd);
6861                 pcix_cmd &= ~PCI_X_CMD_ERO;
6862                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6863                                       pcix_cmd);
6864         }
6865
6866         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6867
6868                 /* Chip reset on 5780 will reset MSI enable bit,
6869                  * so need to restore it.
6870                  */
6871                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6872                         u16 ctrl;
6873
6874                         pci_read_config_word(tp->pdev,
6875                                              tp->msi_cap + PCI_MSI_FLAGS,
6876                                              &ctrl);
6877                         pci_write_config_word(tp->pdev,
6878                                               tp->msi_cap + PCI_MSI_FLAGS,
6879                                               ctrl | PCI_MSI_FLAGS_ENABLE);
6880                         val = tr32(MSGINT_MODE);
6881                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6882                 }
6883         }
6884 }
6885
6886 static void tg3_stop_fw(struct tg3 *);
6887
6888 /* tp->lock is held. */
6889 static int tg3_chip_reset(struct tg3 *tp)
6890 {
6891         u32 val;
6892         void (*write_op)(struct tg3 *, u32, u32);
6893         int i, err;
6894
6895         tg3_nvram_lock(tp);
6896
6897         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6898
6899         /* No matching tg3_nvram_unlock() after this because
6900          * chip reset below will undo the nvram lock.
6901          */
6902         tp->nvram_lock_cnt = 0;
6903
6904         /* GRC_MISC_CFG core clock reset will clear the memory
6905          * enable bit in PCI register 4 and the MSI enable bit
6906          * on some chips, so we save relevant registers here.
6907          */
6908         tg3_save_pci_state(tp);
6909
6910         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6911             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6912                 tw32(GRC_FASTBOOT_PC, 0);
6913
6914         /*
6915          * We must avoid the readl() that normally takes place.
6916          * It locks machines, causes machine checks, and other
6917          * fun things.  So, temporarily disable the 5701
6918          * hardware workaround, while we do the reset.
6919          */
6920         write_op = tp->write32;
6921         if (write_op == tg3_write_flush_reg32)
6922                 tp->write32 = tg3_write32;
6923
6924         /* Prevent the irq handler from reading or writing PCI registers
6925          * during chip reset when the memory enable bit in the PCI command
6926          * register may be cleared.  The chip does not generate interrupt
6927          * at this time, but the irq handler may still be called due to irq
6928          * sharing or irqpoll.
6929          */
6930         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6931         for (i = 0; i < tp->irq_cnt; i++) {
6932                 struct tg3_napi *tnapi = &tp->napi[i];
6933                 if (tnapi->hw_status) {
6934                         tnapi->hw_status->status = 0;
6935                         tnapi->hw_status->status_tag = 0;
6936                 }
6937                 tnapi->last_tag = 0;
6938                 tnapi->last_irq_tag = 0;
6939         }
6940         smp_mb();
6941
6942         for (i = 0; i < tp->irq_cnt; i++)
6943                 synchronize_irq(tp->napi[i].irq_vec);
6944
6945         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6946                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6947                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6948         }
6949
6950         /* do the reset */
6951         val = GRC_MISC_CFG_CORECLK_RESET;
6952
6953         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6954                 /* Force PCIe 1.0a mode */
6955                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
6956                     !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
6957                     tr32(TG3_PCIE_PHY_TSTCTL) ==
6958                     (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
6959                         tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
6960
6961                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6962                         tw32(GRC_MISC_CFG, (1 << 29));
6963                         val |= (1 << 29);
6964                 }
6965         }
6966
6967         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6968                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6969                 tw32(GRC_VCPU_EXT_CTRL,
6970                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6971         }
6972
6973         /* Manage gphy power for all CPMU absent PCIe devices. */
6974         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6975             !(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
6976                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6977
6978         tw32(GRC_MISC_CFG, val);
6979
6980         /* restore 5701 hardware bug workaround write method */
6981         tp->write32 = write_op;
6982
6983         /* Unfortunately, we have to delay before the PCI read back.
6984          * Some 575X chips even will not respond to a PCI cfg access
6985          * when the reset command is given to the chip.
6986          *
6987          * How do these hardware designers expect things to work
6988          * properly if the PCI write is posted for a long period
6989          * of time?  It is always necessary to have some method by
6990          * which a register read back can occur to push the write
6991          * out which does the reset.
6992          *
6993          * For most tg3 variants the trick below was working.
6994          * Ho hum...
6995          */
6996         udelay(120);
6997
6998         /* Flush PCI posted writes.  The normal MMIO registers
6999          * are inaccessible at this time so this is the only
7000          * way to make this reliably (actually, this is no longer
7001          * the case, see above).  I tried to use indirect
7002          * register read/write but this upset some 5701 variants.
7003          */
7004         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
7005
7006         udelay(120);
7007
7008         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
7009                 u16 val16;
7010
7011                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
7012                         int i;
7013                         u32 cfg_val;
7014
7015                         /* Wait for link training to complete.  */
7016                         for (i = 0; i < 5000; i++)
7017                                 udelay(100);
7018
7019                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
7020                         pci_write_config_dword(tp->pdev, 0xc4,
7021                                                cfg_val | (1 << 15));
7022                 }
7023
7024                 /* Clear the "no snoop" and "relaxed ordering" bits. */
7025                 pci_read_config_word(tp->pdev,
7026                                      tp->pcie_cap + PCI_EXP_DEVCTL,
7027                                      &val16);
7028                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
7029                            PCI_EXP_DEVCTL_NOSNOOP_EN);
7030                 /*
7031                  * Older PCIe devices only support the 128 byte
7032                  * MPS setting.  Enforce the restriction.
7033                  */
7034                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7035                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
7036                 pci_write_config_word(tp->pdev,
7037                                       tp->pcie_cap + PCI_EXP_DEVCTL,
7038                                       val16);
7039
7040                 pcie_set_readrq(tp->pdev, 4096);
7041
7042                 /* Clear error status */
7043                 pci_write_config_word(tp->pdev,
7044                                       tp->pcie_cap + PCI_EXP_DEVSTA,
7045                                       PCI_EXP_DEVSTA_CED |
7046                                       PCI_EXP_DEVSTA_NFED |
7047                                       PCI_EXP_DEVSTA_FED |
7048                                       PCI_EXP_DEVSTA_URD);
7049         }
7050
7051         tg3_restore_pci_state(tp);
7052
7053         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
7054
7055         val = 0;
7056         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
7057                 val = tr32(MEMARB_MODE);
7058         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7059
7060         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7061                 tg3_stop_fw(tp);
7062                 tw32(0x5000, 0x400);
7063         }
7064
7065         tw32(GRC_MODE, tp->grc_mode);
7066
7067         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
7068                 val = tr32(0xc4);
7069
7070                 tw32(0xc4, val | (1 << 15));
7071         }
7072
7073         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7074             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7075                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7076                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7077                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7078                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7079         }
7080
7081         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
7082                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
7083                 tw32_f(MAC_MODE, tp->mac_mode);
7084         } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
7085                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
7086                 tw32_f(MAC_MODE, tp->mac_mode);
7087         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7088                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
7089                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
7090                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
7091                 tw32_f(MAC_MODE, tp->mac_mode);
7092         } else
7093                 tw32_f(MAC_MODE, 0);
7094         udelay(40);
7095
7096         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7097
7098         err = tg3_poll_fw(tp);
7099         if (err)
7100                 return err;
7101
7102         tg3_mdio_start(tp);
7103
7104         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
7105             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7106             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7107             !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
7108                 val = tr32(0x7c00);
7109
7110                 tw32(0x7c00, val | (1 << 25));
7111         }
7112
7113         /* Reprobe ASF enable state.  */
7114         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7115         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7116         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7117         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7118                 u32 nic_cfg;
7119
7120                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7121                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7122                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7123                         tp->last_event_jiffies = jiffies;
7124                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7125                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7126                 }
7127         }
7128
7129         return 0;
7130 }
7131
7132 /* tp->lock is held. */
7133 static void tg3_stop_fw(struct tg3 *tp)
7134 {
7135         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7136            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7137                 /* Wait for RX cpu to ACK the previous event. */
7138                 tg3_wait_for_event_ack(tp);
7139
7140                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7141
7142                 tg3_generate_fw_event(tp);
7143
7144                 /* Wait for RX cpu to ACK this event. */
7145                 tg3_wait_for_event_ack(tp);
7146         }
7147 }
7148
7149 /* tp->lock is held. */
7150 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7151 {
7152         int err;
7153
7154         tg3_stop_fw(tp);
7155
7156         tg3_write_sig_pre_reset(tp, kind);
7157
7158         tg3_abort_hw(tp, silent);
7159         err = tg3_chip_reset(tp);
7160
7161         __tg3_set_mac_addr(tp, 0);
7162
7163         tg3_write_sig_legacy(tp, kind);
7164         tg3_write_sig_post_reset(tp, kind);
7165
7166         if (err)
7167                 return err;
7168
7169         return 0;
7170 }
7171
7172 #define RX_CPU_SCRATCH_BASE     0x30000
7173 #define RX_CPU_SCRATCH_SIZE     0x04000
7174 #define TX_CPU_SCRATCH_BASE     0x34000
7175 #define TX_CPU_SCRATCH_SIZE     0x04000
7176
7177 /* tp->lock is held. */
7178 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7179 {
7180         int i;
7181
7182         BUG_ON(offset == TX_CPU_BASE &&
7183             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7184
7185         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7186                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7187
7188                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7189                 return 0;
7190         }
7191         if (offset == RX_CPU_BASE) {
7192                 for (i = 0; i < 10000; i++) {
7193                         tw32(offset + CPU_STATE, 0xffffffff);
7194                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7195                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7196                                 break;
7197                 }
7198
7199                 tw32(offset + CPU_STATE, 0xffffffff);
7200                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
7201                 udelay(10);
7202         } else {
7203                 for (i = 0; i < 10000; i++) {
7204                         tw32(offset + CPU_STATE, 0xffffffff);
7205                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7206                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7207                                 break;
7208                 }
7209         }
7210
7211         if (i >= 10000) {
7212                 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7213                            __func__, offset == RX_CPU_BASE ? "RX" : "TX");
7214                 return -ENODEV;
7215         }
7216
7217         /* Clear firmware's nvram arbitration. */
7218         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7219                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7220         return 0;
7221 }
7222
7223 struct fw_info {
7224         unsigned int fw_base;
7225         unsigned int fw_len;
7226         const __be32 *fw_data;
7227 };
7228
7229 /* tp->lock is held. */
7230 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7231                                  int cpu_scratch_size, struct fw_info *info)
7232 {
7233         int err, lock_err, i;
7234         void (*write_op)(struct tg3 *, u32, u32);
7235
7236         if (cpu_base == TX_CPU_BASE &&
7237             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7238                 netdev_err(tp->dev,
7239                            "%s: Trying to load TX cpu firmware which is 5705\n",
7240                            __func__);
7241                 return -EINVAL;
7242         }
7243
7244         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7245                 write_op = tg3_write_mem;
7246         else
7247                 write_op = tg3_write_indirect_reg32;
7248
7249         /* It is possible that bootcode is still loading at this point.
7250          * Get the nvram lock first before halting the cpu.
7251          */
7252         lock_err = tg3_nvram_lock(tp);
7253         err = tg3_halt_cpu(tp, cpu_base);
7254         if (!lock_err)
7255                 tg3_nvram_unlock(tp);
7256         if (err)
7257                 goto out;
7258
7259         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7260                 write_op(tp, cpu_scratch_base + i, 0);
7261         tw32(cpu_base + CPU_STATE, 0xffffffff);
7262         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7263         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7264                 write_op(tp, (cpu_scratch_base +
7265                               (info->fw_base & 0xffff) +
7266                               (i * sizeof(u32))),
7267                               be32_to_cpu(info->fw_data[i]));
7268
7269         err = 0;
7270
7271 out:
7272         return err;
7273 }
7274
7275 /* tp->lock is held. */
7276 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7277 {
7278         struct fw_info info;
7279         const __be32 *fw_data;
7280         int err, i;
7281
7282         fw_data = (void *)tp->fw->data;
7283
7284         /* Firmware blob starts with version numbers, followed by
7285            start address and length. We are setting complete length.
7286            length = end_address_of_bss - start_address_of_text.
7287            Remainder is the blob to be loaded contiguously
7288            from start address. */
7289
7290         info.fw_base = be32_to_cpu(fw_data[1]);
7291         info.fw_len = tp->fw->size - 12;
7292         info.fw_data = &fw_data[3];
7293
7294         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7295                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7296                                     &info);
7297         if (err)
7298                 return err;
7299
7300         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7301                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7302                                     &info);
7303         if (err)
7304                 return err;
7305
7306         /* Now startup only the RX cpu. */
7307         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7308         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7309
7310         for (i = 0; i < 5; i++) {
7311                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7312                         break;
7313                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7314                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
7315                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7316                 udelay(1000);
7317         }
7318         if (i >= 5) {
7319                 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7320                            "should be %08x\n", __func__,
7321                            tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
7322                 return -ENODEV;
7323         }
7324         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7325         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
7326
7327         return 0;
7328 }
7329
7330 /* 5705 needs a special version of the TSO firmware.  */
7331
7332 /* tp->lock is held. */
7333 static int tg3_load_tso_firmware(struct tg3 *tp)
7334 {
7335         struct fw_info info;
7336         const __be32 *fw_data;
7337         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7338         int err, i;
7339
7340         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7341                 return 0;
7342
7343         fw_data = (void *)tp->fw->data;
7344
7345         /* Firmware blob starts with version numbers, followed by
7346            start address and length. We are setting complete length.
7347            length = end_address_of_bss - start_address_of_text.
7348            Remainder is the blob to be loaded contiguously
7349            from start address. */
7350
7351         info.fw_base = be32_to_cpu(fw_data[1]);
7352         cpu_scratch_size = tp->fw_len;
7353         info.fw_len = tp->fw->size - 12;
7354         info.fw_data = &fw_data[3];
7355
7356         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7357                 cpu_base = RX_CPU_BASE;
7358                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7359         } else {
7360                 cpu_base = TX_CPU_BASE;
7361                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7362                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7363         }
7364
7365         err = tg3_load_firmware_cpu(tp, cpu_base,
7366                                     cpu_scratch_base, cpu_scratch_size,
7367                                     &info);
7368         if (err)
7369                 return err;
7370
7371         /* Now startup the cpu. */
7372         tw32(cpu_base + CPU_STATE, 0xffffffff);
7373         tw32_f(cpu_base + CPU_PC, info.fw_base);
7374
7375         for (i = 0; i < 5; i++) {
7376                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7377                         break;
7378                 tw32(cpu_base + CPU_STATE, 0xffffffff);
7379                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
7380                 tw32_f(cpu_base + CPU_PC, info.fw_base);
7381                 udelay(1000);
7382         }
7383         if (i >= 5) {
7384                 netdev_err(tp->dev,
7385                            "%s fails to set CPU PC, is %08x should be %08x\n",
7386                            __func__, tr32(cpu_base + CPU_PC), info.fw_base);
7387                 return -ENODEV;
7388         }
7389         tw32(cpu_base + CPU_STATE, 0xffffffff);
7390         tw32_f(cpu_base + CPU_MODE,  0x00000000);
7391         return 0;
7392 }
7393
7394
7395 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7396 {
7397         struct tg3 *tp = netdev_priv(dev);
7398         struct sockaddr *addr = p;
7399         int err = 0, skip_mac_1 = 0;
7400
7401         if (!is_valid_ether_addr(addr->sa_data))
7402                 return -EINVAL;
7403
7404         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7405
7406         if (!netif_running(dev))
7407                 return 0;
7408
7409         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7410                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7411
7412                 addr0_high = tr32(MAC_ADDR_0_HIGH);
7413                 addr0_low = tr32(MAC_ADDR_0_LOW);
7414                 addr1_high = tr32(MAC_ADDR_1_HIGH);
7415                 addr1_low = tr32(MAC_ADDR_1_LOW);
7416
7417                 /* Skip MAC addr 1 if ASF is using it. */
7418                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7419                     !(addr1_high == 0 && addr1_low == 0))
7420                         skip_mac_1 = 1;
7421         }
7422         spin_lock_bh(&tp->lock);
7423         __tg3_set_mac_addr(tp, skip_mac_1);
7424         spin_unlock_bh(&tp->lock);
7425
7426         return err;
7427 }
7428
7429 /* tp->lock is held. */
7430 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7431                            dma_addr_t mapping, u32 maxlen_flags,
7432                            u32 nic_addr)
7433 {
7434         tg3_write_mem(tp,
7435                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7436                       ((u64) mapping >> 32));
7437         tg3_write_mem(tp,
7438                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7439                       ((u64) mapping & 0xffffffff));
7440         tg3_write_mem(tp,
7441                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7442                        maxlen_flags);
7443
7444         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7445                 tg3_write_mem(tp,
7446                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7447                               nic_addr);
7448 }
7449
7450 static void __tg3_set_rx_mode(struct net_device *);
7451 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7452 {
7453         int i;
7454
7455         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7456                 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7457                 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7458                 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7459         } else {
7460                 tw32(HOSTCC_TXCOL_TICKS, 0);
7461                 tw32(HOSTCC_TXMAX_FRAMES, 0);
7462                 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7463         }
7464
7465         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
7466                 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7467                 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7468                 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7469         } else {
7470                 tw32(HOSTCC_RXCOL_TICKS, 0);
7471                 tw32(HOSTCC_RXMAX_FRAMES, 0);
7472                 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7473         }
7474
7475         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7476                 u32 val = ec->stats_block_coalesce_usecs;
7477
7478                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7479                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7480
7481                 if (!netif_carrier_ok(tp->dev))
7482                         val = 0;
7483
7484                 tw32(HOSTCC_STAT_COAL_TICKS, val);
7485         }
7486
7487         for (i = 0; i < tp->irq_cnt - 1; i++) {
7488                 u32 reg;
7489
7490                 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7491                 tw32(reg, ec->rx_coalesce_usecs);
7492                 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7493                 tw32(reg, ec->rx_max_coalesced_frames);
7494                 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7495                 tw32(reg, ec->rx_max_coalesced_frames_irq);
7496
7497                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7498                         reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7499                         tw32(reg, ec->tx_coalesce_usecs);
7500                         reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7501                         tw32(reg, ec->tx_max_coalesced_frames);
7502                         reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7503                         tw32(reg, ec->tx_max_coalesced_frames_irq);
7504                 }
7505         }
7506
7507         for (; i < tp->irq_max - 1; i++) {
7508                 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7509                 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7510                 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7511
7512                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7513                         tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7514                         tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7515                         tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7516                 }
7517         }
7518 }
7519
7520 /* tp->lock is held. */
7521 static void tg3_rings_reset(struct tg3 *tp)
7522 {
7523         int i;
7524         u32 stblk, txrcb, rxrcb, limit;
7525         struct tg3_napi *tnapi = &tp->napi[0];
7526
7527         /* Disable all transmit rings but the first. */
7528         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7529                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7530         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7531                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7532         else
7533                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7534
7535         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7536              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7537                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7538                               BDINFO_FLAGS_DISABLED);
7539
7540
7541         /* Disable all receive return rings but the first. */
7542         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7543             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7544                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7545         else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7546                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7547         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7548                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7549                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7550         else
7551                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7552
7553         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7554              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7555                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7556                               BDINFO_FLAGS_DISABLED);
7557
7558         /* Disable interrupts */
7559         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7560
7561         /* Zero mailbox registers. */
7562         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7563                 for (i = 1; i < tp->irq_max; i++) {
7564                         tp->napi[i].tx_prod = 0;
7565                         tp->napi[i].tx_cons = 0;
7566                         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7567                                 tw32_mailbox(tp->napi[i].prodmbox, 0);
7568                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
7569                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7570                 }
7571                 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7572                         tw32_mailbox(tp->napi[0].prodmbox, 0);
7573         } else {
7574                 tp->napi[0].tx_prod = 0;
7575                 tp->napi[0].tx_cons = 0;
7576                 tw32_mailbox(tp->napi[0].prodmbox, 0);
7577                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7578         }
7579
7580         /* Make sure the NIC-based send BD rings are disabled. */
7581         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7582                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7583                 for (i = 0; i < 16; i++)
7584                         tw32_tx_mbox(mbox + i * 8, 0);
7585         }
7586
7587         txrcb = NIC_SRAM_SEND_RCB;
7588         rxrcb = NIC_SRAM_RCV_RET_RCB;
7589
7590         /* Clear status block in ram. */
7591         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7592
7593         /* Set status block DMA address */
7594         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7595              ((u64) tnapi->status_mapping >> 32));
7596         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7597              ((u64) tnapi->status_mapping & 0xffffffff));
7598
7599         if (tnapi->tx_ring) {
7600                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7601                                (TG3_TX_RING_SIZE <<
7602                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7603                                NIC_SRAM_TX_BUFFER_DESC);
7604                 txrcb += TG3_BDINFO_SIZE;
7605         }
7606
7607         if (tnapi->rx_rcb) {
7608                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7609                                (TG3_RX_RCB_RING_SIZE(tp) <<
7610                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7611                 rxrcb += TG3_BDINFO_SIZE;
7612         }
7613
7614         stblk = HOSTCC_STATBLCK_RING1;
7615
7616         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7617                 u64 mapping = (u64)tnapi->status_mapping;
7618                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7619                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7620
7621                 /* Clear status block in ram. */
7622                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7623
7624                 if (tnapi->tx_ring) {
7625                         tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7626                                        (TG3_TX_RING_SIZE <<
7627                                         BDINFO_FLAGS_MAXLEN_SHIFT),
7628                                        NIC_SRAM_TX_BUFFER_DESC);
7629                         txrcb += TG3_BDINFO_SIZE;
7630                 }
7631
7632                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7633                                (TG3_RX_RCB_RING_SIZE(tp) <<
7634                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7635
7636                 stblk += 8;
7637                 rxrcb += TG3_BDINFO_SIZE;
7638         }
7639 }
7640
7641 /* tp->lock is held. */
7642 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7643 {
7644         u32 val, rdmac_mode;
7645         int i, err, limit;
7646         struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
7647
7648         tg3_disable_ints(tp);
7649
7650         tg3_stop_fw(tp);
7651
7652         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7653
7654         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
7655                 tg3_abort_hw(tp, 1);
7656
7657         if (reset_phy)
7658                 tg3_phy_reset(tp);
7659
7660         err = tg3_chip_reset(tp);
7661         if (err)
7662                 return err;
7663
7664         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7665
7666         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7667                 val = tr32(TG3_CPMU_CTRL);
7668                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7669                 tw32(TG3_CPMU_CTRL, val);
7670
7671                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7672                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7673                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7674                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7675
7676                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7677                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7678                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7679                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7680
7681                 val = tr32(TG3_CPMU_HST_ACC);
7682                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7683                 val |= CPMU_HST_ACC_MACCLK_6_25;
7684                 tw32(TG3_CPMU_HST_ACC, val);
7685         }
7686
7687         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7688                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7689                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7690                        PCIE_PWR_MGMT_L1_THRESH_4MS;
7691                 tw32(PCIE_PWR_MGMT_THRESH, val);
7692
7693                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7694                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7695
7696                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7697
7698                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7699                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7700         }
7701
7702         if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7703                 u32 grc_mode = tr32(GRC_MODE);
7704
7705                 /* Access the lower 1K of PL PCIE block registers. */
7706                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7707                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7708
7709                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7710                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7711                      val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7712
7713                 tw32(GRC_MODE, grc_mode);
7714         }
7715
7716         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
7717                 u32 grc_mode = tr32(GRC_MODE);
7718
7719                 /* Access the lower 1K of PL PCIE block registers. */
7720                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7721                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7722
7723                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5);
7724                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
7725                      val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
7726
7727                 tw32(GRC_MODE, grc_mode);
7728
7729                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7730                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7731                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7732                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7733         }
7734
7735         /* This works around an issue with Athlon chipsets on
7736          * B3 tigon3 silicon.  This bit has no effect on any
7737          * other revision.  But do not set this on PCI Express
7738          * chips and don't even touch the clocks if the CPMU is present.
7739          */
7740         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7741                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7742                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7743                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7744         }
7745
7746         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7747             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7748                 val = tr32(TG3PCI_PCISTATE);
7749                 val |= PCISTATE_RETRY_SAME_DMA;
7750                 tw32(TG3PCI_PCISTATE, val);
7751         }
7752
7753         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7754                 /* Allow reads and writes to the
7755                  * APE register and memory space.
7756                  */
7757                 val = tr32(TG3PCI_PCISTATE);
7758                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7759                        PCISTATE_ALLOW_APE_SHMEM_WR |
7760                        PCISTATE_ALLOW_APE_PSPACE_WR;
7761                 tw32(TG3PCI_PCISTATE, val);
7762         }
7763
7764         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7765                 /* Enable some hw fixes.  */
7766                 val = tr32(TG3PCI_MSI_DATA);
7767                 val |= (1 << 26) | (1 << 28) | (1 << 29);
7768                 tw32(TG3PCI_MSI_DATA, val);
7769         }
7770
7771         /* Descriptor ring init may make accesses to the
7772          * NIC SRAM area to setup the TX descriptors, so we
7773          * can only do this after the hardware has been
7774          * successfully reset.
7775          */
7776         err = tg3_init_rings(tp);
7777         if (err)
7778                 return err;
7779
7780         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
7781                 val = tr32(TG3PCI_DMA_RW_CTRL) &
7782                       ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7783                 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
7784                         val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
7785                 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7786         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7787                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7788                 /* This value is determined during the probe time DMA
7789                  * engine test, tg3_test_dma.
7790                  */
7791                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7792         }
7793
7794         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7795                           GRC_MODE_4X_NIC_SEND_RINGS |
7796                           GRC_MODE_NO_TX_PHDR_CSUM |
7797                           GRC_MODE_NO_RX_PHDR_CSUM);
7798         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7799
7800         /* Pseudo-header checksum is done by hardware logic and not
7801          * the offload processers, so make the chip do the pseudo-
7802          * header checksums on receive.  For transmit it is more
7803          * convenient to do the pseudo-header checksum in software
7804          * as Linux does that on transmit for us in all cases.
7805          */
7806         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7807
7808         tw32(GRC_MODE,
7809              tp->grc_mode |
7810              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7811
7812         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7813         val = tr32(GRC_MISC_CFG);
7814         val &= ~0xff;
7815         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7816         tw32(GRC_MISC_CFG, val);
7817
7818         /* Initialize MBUF/DESC pool. */
7819         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7820                 /* Do nothing.  */
7821         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7822                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7823                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7824                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7825                 else
7826                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7827                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7828                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7829         } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7830                 int fw_len;
7831
7832                 fw_len = tp->fw_len;
7833                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7834                 tw32(BUFMGR_MB_POOL_ADDR,
7835                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7836                 tw32(BUFMGR_MB_POOL_SIZE,
7837                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7838         }
7839
7840         if (tp->dev->mtu <= ETH_DATA_LEN) {
7841                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7842                      tp->bufmgr_config.mbuf_read_dma_low_water);
7843                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7844                      tp->bufmgr_config.mbuf_mac_rx_low_water);
7845                 tw32(BUFMGR_MB_HIGH_WATER,
7846                      tp->bufmgr_config.mbuf_high_water);
7847         } else {
7848                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7849                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7850                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7851                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7852                 tw32(BUFMGR_MB_HIGH_WATER,
7853                      tp->bufmgr_config.mbuf_high_water_jumbo);
7854         }
7855         tw32(BUFMGR_DMA_LOW_WATER,
7856              tp->bufmgr_config.dma_low_water);
7857         tw32(BUFMGR_DMA_HIGH_WATER,
7858              tp->bufmgr_config.dma_high_water);
7859
7860         val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
7861         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7862                 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
7863         tw32(BUFMGR_MODE, val);
7864         for (i = 0; i < 2000; i++) {
7865                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7866                         break;
7867                 udelay(10);
7868         }
7869         if (i >= 2000) {
7870                 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
7871                 return -ENODEV;
7872         }
7873
7874         /* Setup replenish threshold. */
7875         val = tp->rx_pending / 8;
7876         if (val == 0)
7877                 val = 1;
7878         else if (val > tp->rx_std_max_post)
7879                 val = tp->rx_std_max_post;
7880         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7881                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7882                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7883
7884                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7885                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7886         }
7887
7888         tw32(RCVBDI_STD_THRESH, val);
7889
7890         /* Initialize TG3_BDINFO's at:
7891          *  RCVDBDI_STD_BD:     standard eth size rx ring
7892          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
7893          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
7894          *
7895          * like so:
7896          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
7897          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
7898          *                              ring attribute flags
7899          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
7900          *
7901          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7902          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7903          *
7904          * The size of each ring is fixed in the firmware, but the location is
7905          * configurable.
7906          */
7907         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7908              ((u64) tpr->rx_std_mapping >> 32));
7909         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7910              ((u64) tpr->rx_std_mapping & 0xffffffff));
7911         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
7912             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
7913                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7914                      NIC_SRAM_RX_BUFFER_DESC);
7915
7916         /* Disable the mini ring */
7917         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7918                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7919                      BDINFO_FLAGS_DISABLED);
7920
7921         /* Program the jumbo buffer descriptor ring control
7922          * blocks on those devices that have them.
7923          */
7924         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7925             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7926                 /* Setup replenish threshold. */
7927                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7928
7929                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7930                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7931                              ((u64) tpr->rx_jmb_mapping >> 32));
7932                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7933                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7934                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7935                              (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7936                              BDINFO_FLAGS_USE_EXT_RECV);
7937                         if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) ||
7938                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7939                                 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7940                                      NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7941                 } else {
7942                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7943                              BDINFO_FLAGS_DISABLED);
7944                 }
7945
7946                 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
7947                         val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7948                               (TG3_RX_STD_DMA_SZ << 2);
7949                 else
7950                         val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
7951         } else
7952                 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7953
7954         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7955
7956         tpr->rx_std_prod_idx = tp->rx_pending;
7957         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
7958
7959         tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7960                           tp->rx_jumbo_pending : 0;
7961         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
7962
7963         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
7964                 tw32(STD_REPLENISH_LWM, 32);
7965                 tw32(JMB_REPLENISH_LWM, 16);
7966         }
7967
7968         tg3_rings_reset(tp);
7969
7970         /* Initialize MAC address and backoff seed. */
7971         __tg3_set_mac_addr(tp, 0);
7972
7973         /* MTU + ethernet header + FCS + optional VLAN tag */
7974         tw32(MAC_RX_MTU_SIZE,
7975              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7976
7977         /* The slot time is changed by tg3_setup_phy if we
7978          * run at gigabit with half duplex.
7979          */
7980         tw32(MAC_TX_LENGTHS,
7981              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7982              (6 << TX_LENGTHS_IPG_SHIFT) |
7983              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7984
7985         /* Receive rules. */
7986         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7987         tw32(RCVLPC_CONFIG, 0x0181);
7988
7989         /* Calculate RDMAC_MODE setting early, we need it to determine
7990          * the RCVLPC_STATE_ENABLE mask.
7991          */
7992         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7993                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7994                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7995                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7996                       RDMAC_MODE_LNGREAD_ENAB);
7997
7998         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7999             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8000                 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
8001
8002         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8003             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8004             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8005                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
8006                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
8007                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
8008
8009         /* If statement applies to 5705 and 5750 PCI devices only */
8010         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8011              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8012             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
8013                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
8014                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
8015                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
8016                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8017                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
8018                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8019                 }
8020         }
8021
8022         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
8023                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8024
8025         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8026                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8027
8028         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
8029             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8030             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8031                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
8032
8033         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8034             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8035             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8036             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
8037             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
8038                 val = tr32(TG3_RDMA_RSRVCTRL_REG);
8039                 tw32(TG3_RDMA_RSRVCTRL_REG,
8040                      val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
8041         }
8042
8043         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
8044                 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
8045                 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val |
8046                      TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
8047                      TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
8048         }
8049
8050         /* Receive/send statistics. */
8051         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
8052                 val = tr32(RCVLPC_STATS_ENABLE);
8053                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8054                 tw32(RCVLPC_STATS_ENABLE, val);
8055         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8056                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8057                 val = tr32(RCVLPC_STATS_ENABLE);
8058                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8059                 tw32(RCVLPC_STATS_ENABLE, val);
8060         } else {
8061                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8062         }
8063         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8064         tw32(SNDDATAI_STATSENAB, 0xffffff);
8065         tw32(SNDDATAI_STATSCTRL,
8066              (SNDDATAI_SCTRL_ENABLE |
8067               SNDDATAI_SCTRL_FASTUPD));
8068
8069         /* Setup host coalescing engine. */
8070         tw32(HOSTCC_MODE, 0);
8071         for (i = 0; i < 2000; i++) {
8072                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8073                         break;
8074                 udelay(10);
8075         }
8076
8077         __tg3_set_coalesce(tp, &tp->coal);
8078
8079         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8080                 /* Status/statistics block address.  See tg3_timer,
8081                  * the tg3_periodic_fetch_stats call there, and
8082                  * tg3_get_stats to see how this works for 5705/5750 chips.
8083                  */
8084                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8085                      ((u64) tp->stats_mapping >> 32));
8086                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8087                      ((u64) tp->stats_mapping & 0xffffffff));
8088                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8089
8090                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
8091
8092                 /* Clear statistics and status block memory areas */
8093                 for (i = NIC_SRAM_STATS_BLK;
8094                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8095                      i += sizeof(u32)) {
8096                         tg3_write_mem(tp, i, 0);
8097                         udelay(40);
8098                 }
8099         }
8100
8101         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8102
8103         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8104         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8105         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8106                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8107
8108         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
8109                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
8110                 /* reset to prevent losing 1st rx packet intermittently */
8111                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8112                 udelay(10);
8113         }
8114
8115         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8116                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8117         else
8118                 tp->mac_mode = 0;
8119         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8120                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
8121         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8122             !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8123             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8124                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8125         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8126         udelay(40);
8127
8128         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8129          * If TG3_FLG2_IS_NIC is zero, we should read the
8130          * register to preserve the GPIO settings for LOMs. The GPIOs,
8131          * whether used as inputs or outputs, are set by boot code after
8132          * reset.
8133          */
8134         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
8135                 u32 gpio_mask;
8136
8137                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8138                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8139                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8140
8141                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8142                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8143                                      GRC_LCLCTRL_GPIO_OUTPUT3;
8144
8145                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8146                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8147
8148                 tp->grc_local_ctrl &= ~gpio_mask;
8149                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8150
8151                 /* GPIO1 must be driven high for eeprom write protect */
8152                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8153                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8154                                                GRC_LCLCTRL_GPIO_OUTPUT1);
8155         }
8156         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8157         udelay(100);
8158
8159         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
8160                 val = tr32(MSGINT_MODE);
8161                 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8162                 tw32(MSGINT_MODE, val);
8163         }
8164
8165         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8166                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8167                 udelay(40);
8168         }
8169
8170         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8171                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8172                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8173                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8174                WDMAC_MODE_LNGREAD_ENAB);
8175
8176         /* If statement applies to 5705 and 5750 PCI devices only */
8177         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8178              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8179             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
8180                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8181                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8182                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8183                         /* nothing */
8184                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8185                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8186                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8187                         val |= WDMAC_MODE_RX_ACCEL;
8188                 }
8189         }
8190
8191         /* Enable host coalescing bug fix */
8192         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8193                 val |= WDMAC_MODE_STATUS_TAG_FIX;
8194
8195         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8196                 val |= WDMAC_MODE_BURST_ALL_DATA;
8197
8198         tw32_f(WDMAC_MODE, val);
8199         udelay(40);
8200
8201         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8202                 u16 pcix_cmd;
8203
8204                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8205                                      &pcix_cmd);
8206                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8207                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8208                         pcix_cmd |= PCI_X_CMD_READ_2K;
8209                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8210                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8211                         pcix_cmd |= PCI_X_CMD_READ_2K;
8212                 }
8213                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8214                                       pcix_cmd);
8215         }
8216
8217         tw32_f(RDMAC_MODE, rdmac_mode);
8218         udelay(40);
8219
8220         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8221         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8222                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8223
8224         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8225                 tw32(SNDDATAC_MODE,
8226                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8227         else
8228                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8229
8230         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8231         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8232         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8233         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8234         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8235                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8236         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8237         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8238                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8239         tw32(SNDBDI_MODE, val);
8240         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8241
8242         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8243                 err = tg3_load_5701_a0_firmware_fix(tp);
8244                 if (err)
8245                         return err;
8246         }
8247
8248         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8249                 err = tg3_load_tso_firmware(tp);
8250                 if (err)
8251                         return err;
8252         }
8253
8254         tp->tx_mode = TX_MODE_ENABLE;
8255         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
8256             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8257                 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
8258         tw32_f(MAC_TX_MODE, tp->tx_mode);
8259         udelay(100);
8260
8261         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8262                 u32 reg = MAC_RSS_INDIR_TBL_0;
8263                 u8 *ent = (u8 *)&val;
8264
8265                 /* Setup the indirection table */
8266                 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8267                         int idx = i % sizeof(val);
8268
8269                         ent[idx] = i % (tp->irq_cnt - 1);
8270                         if (idx == sizeof(val) - 1) {
8271                                 tw32(reg, val);
8272                                 reg += 4;
8273                         }
8274                 }
8275
8276                 /* Setup the "secret" hash key. */
8277                 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8278                 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8279                 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8280                 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8281                 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8282                 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8283                 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8284                 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8285                 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8286                 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8287         }
8288
8289         tp->rx_mode = RX_MODE_ENABLE;
8290         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8291                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8292
8293         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8294                 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8295                                RX_MODE_RSS_ITBL_HASH_BITS_7 |
8296                                RX_MODE_RSS_IPV6_HASH_EN |
8297                                RX_MODE_RSS_TCP_IPV6_HASH_EN |
8298                                RX_MODE_RSS_IPV4_HASH_EN |
8299                                RX_MODE_RSS_TCP_IPV4_HASH_EN;
8300
8301         tw32_f(MAC_RX_MODE, tp->rx_mode);
8302         udelay(10);
8303
8304         tw32(MAC_LED_CTRL, tp->led_ctrl);
8305
8306         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8307         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8308                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8309                 udelay(10);
8310         }
8311         tw32_f(MAC_RX_MODE, tp->rx_mode);
8312         udelay(10);
8313
8314         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8315                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8316                         !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
8317                         /* Set drive transmission level to 1.2V  */
8318                         /* only if the signal pre-emphasis bit is not set  */
8319                         val = tr32(MAC_SERDES_CFG);
8320                         val &= 0xfffff000;
8321                         val |= 0x880;
8322                         tw32(MAC_SERDES_CFG, val);
8323                 }
8324                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8325                         tw32(MAC_SERDES_CFG, 0x616000);
8326         }
8327
8328         /* Prevent chip from dropping frames when flow control
8329          * is enabled.
8330          */
8331         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8332                 val = 1;
8333         else
8334                 val = 2;
8335         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8336
8337         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8338             (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
8339                 /* Use hardware link auto-negotiation */
8340                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8341         }
8342
8343         if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8344             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8345                 u32 tmp;
8346
8347                 tmp = tr32(SERDES_RX_CTRL);
8348                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8349                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8350                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8351                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8352         }
8353
8354         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8355                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
8356                         tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
8357                         tp->link_config.speed = tp->link_config.orig_speed;
8358                         tp->link_config.duplex = tp->link_config.orig_duplex;
8359                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
8360                 }
8361
8362                 err = tg3_setup_phy(tp, 0);
8363                 if (err)
8364                         return err;
8365
8366                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8367                     !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8368                         u32 tmp;
8369
8370                         /* Clear CRC stats. */
8371                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8372                                 tg3_writephy(tp, MII_TG3_TEST1,
8373                                              tmp | MII_TG3_TEST1_CRC_EN);
8374                                 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
8375                         }
8376                 }
8377         }
8378
8379         __tg3_set_rx_mode(tp->dev);
8380
8381         /* Initialize receive rules. */
8382         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
8383         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8384         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
8385         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8386
8387         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8388             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8389                 limit = 8;
8390         else
8391                 limit = 16;
8392         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8393                 limit -= 4;
8394         switch (limit) {
8395         case 16:
8396                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
8397         case 15:
8398                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
8399         case 14:
8400                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
8401         case 13:
8402                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
8403         case 12:
8404                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
8405         case 11:
8406                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
8407         case 10:
8408                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
8409         case 9:
8410                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
8411         case 8:
8412                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
8413         case 7:
8414                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
8415         case 6:
8416                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
8417         case 5:
8418                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
8419         case 4:
8420                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
8421         case 3:
8422                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
8423         case 2:
8424         case 1:
8425
8426         default:
8427                 break;
8428         }
8429
8430         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8431                 /* Write our heartbeat update interval to APE. */
8432                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8433                                 APE_HOST_HEARTBEAT_INT_DISABLE);
8434
8435         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8436
8437         return 0;
8438 }
8439
8440 /* Called at device open time to get the chip ready for
8441  * packet processing.  Invoked with tp->lock held.
8442  */
8443 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8444 {
8445         tg3_switch_clocks(tp);
8446
8447         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8448
8449         return tg3_reset_hw(tp, reset_phy);
8450 }
8451
8452 #define TG3_STAT_ADD32(PSTAT, REG) \
8453 do {    u32 __val = tr32(REG); \
8454         (PSTAT)->low += __val; \
8455         if ((PSTAT)->low < __val) \
8456                 (PSTAT)->high += 1; \
8457 } while (0)
8458
8459 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8460 {
8461         struct tg3_hw_stats *sp = tp->hw_stats;
8462
8463         if (!netif_carrier_ok(tp->dev))
8464                 return;
8465
8466         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8467         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8468         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8469         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8470         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8471         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8472         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8473         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8474         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8475         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8476         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8477         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8478         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8479
8480         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8481         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8482         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8483         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8484         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8485         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8486         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8487         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8488         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8489         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8490         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8491         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8492         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8493         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8494
8495         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8496         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8497         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8498 }
8499
8500 static void tg3_timer(unsigned long __opaque)
8501 {
8502         struct tg3 *tp = (struct tg3 *) __opaque;
8503
8504         if (tp->irq_sync)
8505                 goto restart_timer;
8506
8507         spin_lock(&tp->lock);
8508
8509         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8510                 /* All of this garbage is because when using non-tagged
8511                  * IRQ status the mailbox/status_block protocol the chip
8512                  * uses with the cpu is race prone.
8513                  */
8514                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8515                         tw32(GRC_LOCAL_CTRL,
8516                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8517                 } else {
8518                         tw32(HOSTCC_MODE, tp->coalesce_mode |
8519                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8520                 }
8521
8522                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8523                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8524                         spin_unlock(&tp->lock);
8525                         schedule_work(&tp->reset_task);
8526                         return;
8527                 }
8528         }
8529
8530         /* This part only runs once per second. */
8531         if (!--tp->timer_counter) {
8532                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8533                         tg3_periodic_fetch_stats(tp);
8534
8535                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8536                         u32 mac_stat;
8537                         int phy_event;
8538
8539                         mac_stat = tr32(MAC_STATUS);
8540
8541                         phy_event = 0;
8542                         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
8543                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8544                                         phy_event = 1;
8545                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8546                                 phy_event = 1;
8547
8548                         if (phy_event)
8549                                 tg3_setup_phy(tp, 0);
8550                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8551                         u32 mac_stat = tr32(MAC_STATUS);
8552                         int need_setup = 0;
8553
8554                         if (netif_carrier_ok(tp->dev) &&
8555                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8556                                 need_setup = 1;
8557                         }
8558                         if (!netif_carrier_ok(tp->dev) &&
8559                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
8560                                          MAC_STATUS_SIGNAL_DET))) {
8561                                 need_setup = 1;
8562                         }
8563                         if (need_setup) {
8564                                 if (!tp->serdes_counter) {
8565                                         tw32_f(MAC_MODE,
8566                                              (tp->mac_mode &
8567                                               ~MAC_MODE_PORT_MODE_MASK));
8568                                         udelay(40);
8569                                         tw32_f(MAC_MODE, tp->mac_mode);
8570                                         udelay(40);
8571                                 }
8572                                 tg3_setup_phy(tp, 0);
8573                         }
8574                 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8575                            (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8576                         tg3_serdes_parallel_detect(tp);
8577                 }
8578
8579                 tp->timer_counter = tp->timer_multiplier;
8580         }
8581
8582         /* Heartbeat is only sent once every 2 seconds.
8583          *
8584          * The heartbeat is to tell the ASF firmware that the host
8585          * driver is still alive.  In the event that the OS crashes,
8586          * ASF needs to reset the hardware to free up the FIFO space
8587          * that may be filled with rx packets destined for the host.
8588          * If the FIFO is full, ASF will no longer function properly.
8589          *
8590          * Unintended resets have been reported on real time kernels
8591          * where the timer doesn't run on time.  Netpoll will also have
8592          * same problem.
8593          *
8594          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8595          * to check the ring condition when the heartbeat is expiring
8596          * before doing the reset.  This will prevent most unintended
8597          * resets.
8598          */
8599         if (!--tp->asf_counter) {
8600                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8601                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8602                         tg3_wait_for_event_ack(tp);
8603
8604                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8605                                       FWCMD_NICDRV_ALIVE3);
8606                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8607                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
8608                                       TG3_FW_UPDATE_TIMEOUT_SEC);
8609
8610                         tg3_generate_fw_event(tp);
8611                 }
8612                 tp->asf_counter = tp->asf_multiplier;
8613         }
8614
8615         spin_unlock(&tp->lock);
8616
8617 restart_timer:
8618         tp->timer.expires = jiffies + tp->timer_offset;
8619         add_timer(&tp->timer);
8620 }
8621
8622 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8623 {
8624         irq_handler_t fn;
8625         unsigned long flags;
8626         char *name;
8627         struct tg3_napi *tnapi = &tp->napi[irq_num];
8628
8629         if (tp->irq_cnt == 1)
8630                 name = tp->dev->name;
8631         else {
8632                 name = &tnapi->irq_lbl[0];
8633                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8634                 name[IFNAMSIZ-1] = 0;
8635         }
8636
8637         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8638                 fn = tg3_msi;
8639                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8640                         fn = tg3_msi_1shot;
8641                 flags = IRQF_SAMPLE_RANDOM;
8642         } else {
8643                 fn = tg3_interrupt;
8644                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8645                         fn = tg3_interrupt_tagged;
8646                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8647         }
8648
8649         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8650 }
8651
8652 static int tg3_test_interrupt(struct tg3 *tp)
8653 {
8654         struct tg3_napi *tnapi = &tp->napi[0];
8655         struct net_device *dev = tp->dev;
8656         int err, i, intr_ok = 0;
8657         u32 val;
8658
8659         if (!netif_running(dev))
8660                 return -ENODEV;
8661
8662         tg3_disable_ints(tp);
8663
8664         free_irq(tnapi->irq_vec, tnapi);
8665
8666         /*
8667          * Turn off MSI one shot mode.  Otherwise this test has no
8668          * observable way to know whether the interrupt was delivered.
8669          */
8670         if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8671             (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8672                 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8673                 tw32(MSGINT_MODE, val);
8674         }
8675
8676         err = request_irq(tnapi->irq_vec, tg3_test_isr,
8677                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8678         if (err)
8679                 return err;
8680
8681         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8682         tg3_enable_ints(tp);
8683
8684         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8685                tnapi->coal_now);
8686
8687         for (i = 0; i < 5; i++) {
8688                 u32 int_mbox, misc_host_ctrl;
8689
8690                 int_mbox = tr32_mailbox(tnapi->int_mbox);
8691                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8692
8693                 if ((int_mbox != 0) ||
8694                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8695                         intr_ok = 1;
8696                         break;
8697                 }
8698
8699                 msleep(10);
8700         }
8701
8702         tg3_disable_ints(tp);
8703
8704         free_irq(tnapi->irq_vec, tnapi);
8705
8706         err = tg3_request_irq(tp, 0);
8707
8708         if (err)
8709                 return err;
8710
8711         if (intr_ok) {
8712                 /* Reenable MSI one shot mode. */
8713                 if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8714                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8715                         val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8716                         tw32(MSGINT_MODE, val);
8717                 }
8718                 return 0;
8719         }
8720
8721         return -EIO;
8722 }
8723
8724 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8725  * successfully restored
8726  */
8727 static int tg3_test_msi(struct tg3 *tp)
8728 {
8729         int err;
8730         u16 pci_cmd;
8731
8732         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8733                 return 0;
8734
8735         /* Turn off SERR reporting in case MSI terminates with Master
8736          * Abort.
8737          */
8738         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8739         pci_write_config_word(tp->pdev, PCI_COMMAND,
8740                               pci_cmd & ~PCI_COMMAND_SERR);
8741
8742         err = tg3_test_interrupt(tp);
8743
8744         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8745
8746         if (!err)
8747                 return 0;
8748
8749         /* other failures */
8750         if (err != -EIO)
8751                 return err;
8752
8753         /* MSI test failed, go back to INTx mode */
8754         netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
8755                     "to INTx mode. Please report this failure to the PCI "
8756                     "maintainer and include system chipset information\n");
8757
8758         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8759
8760         pci_disable_msi(tp->pdev);
8761
8762         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8763         tp->napi[0].irq_vec = tp->pdev->irq;
8764
8765         err = tg3_request_irq(tp, 0);
8766         if (err)
8767                 return err;
8768
8769         /* Need to reset the chip because the MSI cycle may have terminated
8770          * with Master Abort.
8771          */
8772         tg3_full_lock(tp, 1);
8773
8774         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8775         err = tg3_init_hw(tp, 1);
8776
8777         tg3_full_unlock(tp);
8778
8779         if (err)
8780                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8781
8782         return err;
8783 }
8784
8785 static int tg3_request_firmware(struct tg3 *tp)
8786 {
8787         const __be32 *fw_data;
8788
8789         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8790                 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
8791                            tp->fw_needed);
8792                 return -ENOENT;
8793         }
8794
8795         fw_data = (void *)tp->fw->data;
8796
8797         /* Firmware blob starts with version numbers, followed by
8798          * start address and _full_ length including BSS sections
8799          * (which must be longer than the actual data, of course
8800          */
8801
8802         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
8803         if (tp->fw_len < (tp->fw->size - 12)) {
8804                 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
8805                            tp->fw_len, tp->fw_needed);
8806                 release_firmware(tp->fw);
8807                 tp->fw = NULL;
8808                 return -EINVAL;
8809         }
8810
8811         /* We no longer need firmware; we have it. */
8812         tp->fw_needed = NULL;
8813         return 0;
8814 }
8815
8816 static bool tg3_enable_msix(struct tg3 *tp)
8817 {
8818         int i, rc, cpus = num_online_cpus();
8819         struct msix_entry msix_ent[tp->irq_max];
8820
8821         if (cpus == 1)
8822                 /* Just fallback to the simpler MSI mode. */
8823                 return false;
8824
8825         /*
8826          * We want as many rx rings enabled as there are cpus.
8827          * The first MSIX vector only deals with link interrupts, etc,
8828          * so we add one to the number of vectors we are requesting.
8829          */
8830         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8831
8832         for (i = 0; i < tp->irq_max; i++) {
8833                 msix_ent[i].entry  = i;
8834                 msix_ent[i].vector = 0;
8835         }
8836
8837         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8838         if (rc < 0) {
8839                 return false;
8840         } else if (rc != 0) {
8841                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8842                         return false;
8843                 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
8844                               tp->irq_cnt, rc);
8845                 tp->irq_cnt = rc;
8846         }
8847
8848         for (i = 0; i < tp->irq_max; i++)
8849                 tp->napi[i].irq_vec = msix_ent[i].vector;
8850
8851         netif_set_real_num_tx_queues(tp->dev, 1);
8852         rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1;
8853         if (netif_set_real_num_rx_queues(tp->dev, rc)) {
8854                 pci_disable_msix(tp->pdev);
8855                 return false;
8856         }
8857         if (tp->irq_cnt > 1)
8858                 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8859
8860         return true;
8861 }
8862
8863 static void tg3_ints_init(struct tg3 *tp)
8864 {
8865         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8866             !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8867                 /* All MSI supporting chips should support tagged
8868                  * status.  Assert that this is the case.
8869                  */
8870                 netdev_warn(tp->dev,
8871                             "MSI without TAGGED_STATUS? Not using MSI\n");
8872                 goto defcfg;
8873         }
8874
8875         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8876                 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8877         else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8878                  pci_enable_msi(tp->pdev) == 0)
8879                 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8880
8881         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8882                 u32 msi_mode = tr32(MSGINT_MODE);
8883                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8884                         msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8885                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8886         }
8887 defcfg:
8888         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8889                 tp->irq_cnt = 1;
8890                 tp->napi[0].irq_vec = tp->pdev->irq;
8891                 netif_set_real_num_tx_queues(tp->dev, 1);
8892         }
8893 }
8894
8895 static void tg3_ints_fini(struct tg3 *tp)
8896 {
8897         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8898                 pci_disable_msix(tp->pdev);
8899         else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8900                 pci_disable_msi(tp->pdev);
8901         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8902         tp->tg3_flags3 &= ~(TG3_FLG3_ENABLE_RSS | TG3_FLG3_ENABLE_TSS);
8903 }
8904
8905 static int tg3_open(struct net_device *dev)
8906 {
8907         struct tg3 *tp = netdev_priv(dev);
8908         int i, err;
8909
8910         if (tp->fw_needed) {
8911                 err = tg3_request_firmware(tp);
8912                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8913                         if (err)
8914                                 return err;
8915                 } else if (err) {
8916                         netdev_warn(tp->dev, "TSO capability disabled\n");
8917                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8918                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8919                         netdev_notice(tp->dev, "TSO capability restored\n");
8920                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8921                 }
8922         }
8923
8924         netif_carrier_off(tp->dev);
8925
8926         err = tg3_set_power_state(tp, PCI_D0);
8927         if (err)
8928                 return err;
8929
8930         tg3_full_lock(tp, 0);
8931
8932         tg3_disable_ints(tp);
8933         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8934
8935         tg3_full_unlock(tp);
8936
8937         /*
8938          * Setup interrupts first so we know how
8939          * many NAPI resources to allocate
8940          */
8941         tg3_ints_init(tp);
8942
8943         /* The placement of this call is tied
8944          * to the setup and use of Host TX descriptors.
8945          */
8946         err = tg3_alloc_consistent(tp);
8947         if (err)
8948                 goto err_out1;
8949
8950         tg3_napi_init(tp);
8951
8952         tg3_napi_enable(tp);
8953
8954         for (i = 0; i < tp->irq_cnt; i++) {
8955                 struct tg3_napi *tnapi = &tp->napi[i];
8956                 err = tg3_request_irq(tp, i);
8957                 if (err) {
8958                         for (i--; i >= 0; i--)
8959                                 free_irq(tnapi->irq_vec, tnapi);
8960                         break;
8961                 }
8962         }
8963
8964         if (err)
8965                 goto err_out2;
8966
8967         tg3_full_lock(tp, 0);
8968
8969         err = tg3_init_hw(tp, 1);
8970         if (err) {
8971                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8972                 tg3_free_rings(tp);
8973         } else {
8974                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8975                         tp->timer_offset = HZ;
8976                 else
8977                         tp->timer_offset = HZ / 10;
8978
8979                 BUG_ON(tp->timer_offset > HZ);
8980                 tp->timer_counter = tp->timer_multiplier =
8981                         (HZ / tp->timer_offset);
8982                 tp->asf_counter = tp->asf_multiplier =
8983                         ((HZ / tp->timer_offset) * 2);
8984
8985                 init_timer(&tp->timer);
8986                 tp->timer.expires = jiffies + tp->timer_offset;
8987                 tp->timer.data = (unsigned long) tp;
8988                 tp->timer.function = tg3_timer;
8989         }
8990
8991         tg3_full_unlock(tp);
8992
8993         if (err)
8994                 goto err_out3;
8995
8996         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8997                 err = tg3_test_msi(tp);
8998
8999                 if (err) {
9000                         tg3_full_lock(tp, 0);
9001                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9002                         tg3_free_rings(tp);
9003                         tg3_full_unlock(tp);
9004
9005                         goto err_out2;
9006                 }
9007
9008                 if (!(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
9009                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
9010                         u32 val = tr32(PCIE_TRANSACTION_CFG);
9011
9012                         tw32(PCIE_TRANSACTION_CFG,
9013                              val | PCIE_TRANS_CFG_1SHOT_MSI);
9014                 }
9015         }
9016
9017         tg3_phy_start(tp);
9018
9019         tg3_full_lock(tp, 0);
9020
9021         add_timer(&tp->timer);
9022         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9023         tg3_enable_ints(tp);
9024
9025         tg3_full_unlock(tp);
9026
9027         netif_tx_start_all_queues(dev);
9028
9029         return 0;
9030
9031 err_out3:
9032         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9033                 struct tg3_napi *tnapi = &tp->napi[i];
9034                 free_irq(tnapi->irq_vec, tnapi);
9035         }
9036
9037 err_out2:
9038         tg3_napi_disable(tp);
9039         tg3_napi_fini(tp);
9040         tg3_free_consistent(tp);
9041
9042 err_out1:
9043         tg3_ints_fini(tp);
9044         return err;
9045 }
9046
9047 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
9048                                                  struct rtnl_link_stats64 *);
9049 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9050
9051 static int tg3_close(struct net_device *dev)
9052 {
9053         int i;
9054         struct tg3 *tp = netdev_priv(dev);
9055
9056         tg3_napi_disable(tp);
9057         cancel_work_sync(&tp->reset_task);
9058
9059         netif_tx_stop_all_queues(dev);
9060
9061         del_timer_sync(&tp->timer);
9062
9063         tg3_phy_stop(tp);
9064
9065         tg3_full_lock(tp, 1);
9066
9067         tg3_disable_ints(tp);
9068
9069         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9070         tg3_free_rings(tp);
9071         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9072
9073         tg3_full_unlock(tp);
9074
9075         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9076                 struct tg3_napi *tnapi = &tp->napi[i];
9077                 free_irq(tnapi->irq_vec, tnapi);
9078         }
9079
9080         tg3_ints_fini(tp);
9081
9082         tg3_get_stats64(tp->dev, &tp->net_stats_prev);
9083
9084         memcpy(&tp->estats_prev, tg3_get_estats(tp),
9085                sizeof(tp->estats_prev));
9086
9087         tg3_napi_fini(tp);
9088
9089         tg3_free_consistent(tp);
9090
9091         tg3_set_power_state(tp, PCI_D3hot);
9092
9093         netif_carrier_off(tp->dev);
9094
9095         return 0;
9096 }
9097
9098 static inline u64 get_stat64(tg3_stat64_t *val)
9099 {
9100        return ((u64)val->high << 32) | ((u64)val->low);
9101 }
9102
9103 static u64 calc_crc_errors(struct tg3 *tp)
9104 {
9105         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9106
9107         if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9108             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9109              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9110                 u32 val;
9111
9112                 spin_lock_bh(&tp->lock);
9113                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9114                         tg3_writephy(tp, MII_TG3_TEST1,
9115                                      val | MII_TG3_TEST1_CRC_EN);
9116                         tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
9117                 } else
9118                         val = 0;
9119                 spin_unlock_bh(&tp->lock);
9120
9121                 tp->phy_crc_errors += val;
9122
9123                 return tp->phy_crc_errors;
9124         }
9125
9126         return get_stat64(&hw_stats->rx_fcs_errors);
9127 }
9128
9129 #define ESTAT_ADD(member) \
9130         estats->member =        old_estats->member + \
9131                                 get_stat64(&hw_stats->member)
9132
9133 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9134 {
9135         struct tg3_ethtool_stats *estats = &tp->estats;
9136         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9137         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9138
9139         if (!hw_stats)
9140                 return old_estats;
9141
9142         ESTAT_ADD(rx_octets);
9143         ESTAT_ADD(rx_fragments);
9144         ESTAT_ADD(rx_ucast_packets);
9145         ESTAT_ADD(rx_mcast_packets);
9146         ESTAT_ADD(rx_bcast_packets);
9147         ESTAT_ADD(rx_fcs_errors);
9148         ESTAT_ADD(rx_align_errors);
9149         ESTAT_ADD(rx_xon_pause_rcvd);
9150         ESTAT_ADD(rx_xoff_pause_rcvd);
9151         ESTAT_ADD(rx_mac_ctrl_rcvd);
9152         ESTAT_ADD(rx_xoff_entered);
9153         ESTAT_ADD(rx_frame_too_long_errors);
9154         ESTAT_ADD(rx_jabbers);
9155         ESTAT_ADD(rx_undersize_packets);
9156         ESTAT_ADD(rx_in_length_errors);
9157         ESTAT_ADD(rx_out_length_errors);
9158         ESTAT_ADD(rx_64_or_less_octet_packets);
9159         ESTAT_ADD(rx_65_to_127_octet_packets);
9160         ESTAT_ADD(rx_128_to_255_octet_packets);
9161         ESTAT_ADD(rx_256_to_511_octet_packets);
9162         ESTAT_ADD(rx_512_to_1023_octet_packets);
9163         ESTAT_ADD(rx_1024_to_1522_octet_packets);
9164         ESTAT_ADD(rx_1523_to_2047_octet_packets);
9165         ESTAT_ADD(rx_2048_to_4095_octet_packets);
9166         ESTAT_ADD(rx_4096_to_8191_octet_packets);
9167         ESTAT_ADD(rx_8192_to_9022_octet_packets);
9168
9169         ESTAT_ADD(tx_octets);
9170         ESTAT_ADD(tx_collisions);
9171         ESTAT_ADD(tx_xon_sent);
9172         ESTAT_ADD(tx_xoff_sent);
9173         ESTAT_ADD(tx_flow_control);
9174         ESTAT_ADD(tx_mac_errors);
9175         ESTAT_ADD(tx_single_collisions);
9176         ESTAT_ADD(tx_mult_collisions);
9177         ESTAT_ADD(tx_deferred);
9178         ESTAT_ADD(tx_excessive_collisions);
9179         ESTAT_ADD(tx_late_collisions);
9180         ESTAT_ADD(tx_collide_2times);
9181         ESTAT_ADD(tx_collide_3times);
9182         ESTAT_ADD(tx_collide_4times);
9183         ESTAT_ADD(tx_collide_5times);
9184         ESTAT_ADD(tx_collide_6times);
9185         ESTAT_ADD(tx_collide_7times);
9186         ESTAT_ADD(tx_collide_8times);
9187         ESTAT_ADD(tx_collide_9times);
9188         ESTAT_ADD(tx_collide_10times);
9189         ESTAT_ADD(tx_collide_11times);
9190         ESTAT_ADD(tx_collide_12times);
9191         ESTAT_ADD(tx_collide_13times);
9192         ESTAT_ADD(tx_collide_14times);
9193         ESTAT_ADD(tx_collide_15times);
9194         ESTAT_ADD(tx_ucast_packets);
9195         ESTAT_ADD(tx_mcast_packets);
9196         ESTAT_ADD(tx_bcast_packets);
9197         ESTAT_ADD(tx_carrier_sense_errors);
9198         ESTAT_ADD(tx_discards);
9199         ESTAT_ADD(tx_errors);
9200
9201         ESTAT_ADD(dma_writeq_full);
9202         ESTAT_ADD(dma_write_prioq_full);
9203         ESTAT_ADD(rxbds_empty);
9204         ESTAT_ADD(rx_discards);
9205         ESTAT_ADD(rx_errors);
9206         ESTAT_ADD(rx_threshold_hit);
9207
9208         ESTAT_ADD(dma_readq_full);
9209         ESTAT_ADD(dma_read_prioq_full);
9210         ESTAT_ADD(tx_comp_queue_full);
9211
9212         ESTAT_ADD(ring_set_send_prod_index);
9213         ESTAT_ADD(ring_status_update);
9214         ESTAT_ADD(nic_irqs);
9215         ESTAT_ADD(nic_avoided_irqs);
9216         ESTAT_ADD(nic_tx_threshold_hit);
9217
9218         return estats;
9219 }
9220
9221 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
9222                                                  struct rtnl_link_stats64 *stats)
9223 {
9224         struct tg3 *tp = netdev_priv(dev);
9225         struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
9226         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9227
9228         if (!hw_stats)
9229                 return old_stats;
9230
9231         stats->rx_packets = old_stats->rx_packets +
9232                 get_stat64(&hw_stats->rx_ucast_packets) +
9233                 get_stat64(&hw_stats->rx_mcast_packets) +
9234                 get_stat64(&hw_stats->rx_bcast_packets);
9235
9236         stats->tx_packets = old_stats->tx_packets +
9237                 get_stat64(&hw_stats->tx_ucast_packets) +
9238                 get_stat64(&hw_stats->tx_mcast_packets) +
9239                 get_stat64(&hw_stats->tx_bcast_packets);
9240
9241         stats->rx_bytes = old_stats->rx_bytes +
9242                 get_stat64(&hw_stats->rx_octets);
9243         stats->tx_bytes = old_stats->tx_bytes +
9244                 get_stat64(&hw_stats->tx_octets);
9245
9246         stats->rx_errors = old_stats->rx_errors +
9247                 get_stat64(&hw_stats->rx_errors);
9248         stats->tx_errors = old_stats->tx_errors +
9249                 get_stat64(&hw_stats->tx_errors) +
9250                 get_stat64(&hw_stats->tx_mac_errors) +
9251                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9252                 get_stat64(&hw_stats->tx_discards);
9253
9254         stats->multicast = old_stats->multicast +
9255                 get_stat64(&hw_stats->rx_mcast_packets);
9256         stats->collisions = old_stats->collisions +
9257                 get_stat64(&hw_stats->tx_collisions);
9258
9259         stats->rx_length_errors = old_stats->rx_length_errors +
9260                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9261                 get_stat64(&hw_stats->rx_undersize_packets);
9262
9263         stats->rx_over_errors = old_stats->rx_over_errors +
9264                 get_stat64(&hw_stats->rxbds_empty);
9265         stats->rx_frame_errors = old_stats->rx_frame_errors +
9266                 get_stat64(&hw_stats->rx_align_errors);
9267         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9268                 get_stat64(&hw_stats->tx_discards);
9269         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9270                 get_stat64(&hw_stats->tx_carrier_sense_errors);
9271
9272         stats->rx_crc_errors = old_stats->rx_crc_errors +
9273                 calc_crc_errors(tp);
9274
9275         stats->rx_missed_errors = old_stats->rx_missed_errors +
9276                 get_stat64(&hw_stats->rx_discards);
9277
9278         return stats;
9279 }
9280
9281 static inline u32 calc_crc(unsigned char *buf, int len)
9282 {
9283         u32 reg;
9284         u32 tmp;
9285         int j, k;
9286
9287         reg = 0xffffffff;
9288
9289         for (j = 0; j < len; j++) {
9290                 reg ^= buf[j];
9291
9292                 for (k = 0; k < 8; k++) {
9293                         tmp = reg & 0x01;
9294
9295                         reg >>= 1;
9296
9297                         if (tmp)
9298                                 reg ^= 0xedb88320;
9299                 }
9300         }
9301
9302         return ~reg;
9303 }
9304
9305 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9306 {
9307         /* accept or reject all multicast frames */
9308         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9309         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9310         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9311         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9312 }
9313
9314 static void __tg3_set_rx_mode(struct net_device *dev)
9315 {
9316         struct tg3 *tp = netdev_priv(dev);
9317         u32 rx_mode;
9318
9319         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9320                                   RX_MODE_KEEP_VLAN_TAG);
9321
9322         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9323          * flag clear.
9324          */
9325 #if TG3_VLAN_TAG_USED
9326         if (!tp->vlgrp &&
9327             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9328                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9329 #else
9330         /* By definition, VLAN is disabled always in this
9331          * case.
9332          */
9333         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9334                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9335 #endif
9336
9337         if (dev->flags & IFF_PROMISC) {
9338                 /* Promiscuous mode. */
9339                 rx_mode |= RX_MODE_PROMISC;
9340         } else if (dev->flags & IFF_ALLMULTI) {
9341                 /* Accept all multicast. */
9342                 tg3_set_multi(tp, 1);
9343         } else if (netdev_mc_empty(dev)) {
9344                 /* Reject all multicast. */
9345                 tg3_set_multi(tp, 0);
9346         } else {
9347                 /* Accept one or more multicast(s). */
9348                 struct netdev_hw_addr *ha;
9349                 u32 mc_filter[4] = { 0, };
9350                 u32 regidx;
9351                 u32 bit;
9352                 u32 crc;
9353
9354                 netdev_for_each_mc_addr(ha, dev) {
9355                         crc = calc_crc(ha->addr, ETH_ALEN);
9356                         bit = ~crc & 0x7f;
9357                         regidx = (bit & 0x60) >> 5;
9358                         bit &= 0x1f;
9359                         mc_filter[regidx] |= (1 << bit);
9360                 }
9361
9362                 tw32(MAC_HASH_REG_0, mc_filter[0]);
9363                 tw32(MAC_HASH_REG_1, mc_filter[1]);
9364                 tw32(MAC_HASH_REG_2, mc_filter[2]);
9365                 tw32(MAC_HASH_REG_3, mc_filter[3]);
9366         }
9367
9368         if (rx_mode != tp->rx_mode) {
9369                 tp->rx_mode = rx_mode;
9370                 tw32_f(MAC_RX_MODE, rx_mode);
9371                 udelay(10);
9372         }
9373 }
9374
9375 static void tg3_set_rx_mode(struct net_device *dev)
9376 {
9377         struct tg3 *tp = netdev_priv(dev);
9378
9379         if (!netif_running(dev))
9380                 return;
9381
9382         tg3_full_lock(tp, 0);
9383         __tg3_set_rx_mode(dev);
9384         tg3_full_unlock(tp);
9385 }
9386
9387 #define TG3_REGDUMP_LEN         (32 * 1024)
9388
9389 static int tg3_get_regs_len(struct net_device *dev)
9390 {
9391         return TG3_REGDUMP_LEN;
9392 }
9393
9394 static void tg3_get_regs(struct net_device *dev,
9395                 struct ethtool_regs *regs, void *_p)
9396 {
9397         u32 *p = _p;
9398         struct tg3 *tp = netdev_priv(dev);
9399         u8 *orig_p = _p;
9400         int i;
9401
9402         regs->version = 0;
9403
9404         memset(p, 0, TG3_REGDUMP_LEN);
9405
9406         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9407                 return;
9408
9409         tg3_full_lock(tp, 0);
9410
9411 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
9412 #define GET_REG32_LOOP(base, len)               \
9413 do {    p = (u32 *)(orig_p + (base));           \
9414         for (i = 0; i < len; i += 4)            \
9415                 __GET_REG32((base) + i);        \
9416 } while (0)
9417 #define GET_REG32_1(reg)                        \
9418 do {    p = (u32 *)(orig_p + (reg));            \
9419         __GET_REG32((reg));                     \
9420 } while (0)
9421
9422         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9423         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9424         GET_REG32_LOOP(MAC_MODE, 0x4f0);
9425         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9426         GET_REG32_1(SNDDATAC_MODE);
9427         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9428         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9429         GET_REG32_1(SNDBDC_MODE);
9430         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9431         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9432         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9433         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9434         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9435         GET_REG32_1(RCVDCC_MODE);
9436         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9437         GET_REG32_LOOP(RCVCC_MODE, 0x14);
9438         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9439         GET_REG32_1(MBFREE_MODE);
9440         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9441         GET_REG32_LOOP(MEMARB_MODE, 0x10);
9442         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9443         GET_REG32_LOOP(RDMAC_MODE, 0x08);
9444         GET_REG32_LOOP(WDMAC_MODE, 0x08);
9445         GET_REG32_1(RX_CPU_MODE);
9446         GET_REG32_1(RX_CPU_STATE);
9447         GET_REG32_1(RX_CPU_PGMCTR);
9448         GET_REG32_1(RX_CPU_HWBKPT);
9449         GET_REG32_1(TX_CPU_MODE);
9450         GET_REG32_1(TX_CPU_STATE);
9451         GET_REG32_1(TX_CPU_PGMCTR);
9452         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9453         GET_REG32_LOOP(FTQ_RESET, 0x120);
9454         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9455         GET_REG32_1(DMAC_MODE);
9456         GET_REG32_LOOP(GRC_MODE, 0x4c);
9457         if (tp->tg3_flags & TG3_FLAG_NVRAM)
9458                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9459
9460 #undef __GET_REG32
9461 #undef GET_REG32_LOOP
9462 #undef GET_REG32_1
9463
9464         tg3_full_unlock(tp);
9465 }
9466
9467 static int tg3_get_eeprom_len(struct net_device *dev)
9468 {
9469         struct tg3 *tp = netdev_priv(dev);
9470
9471         return tp->nvram_size;
9472 }
9473
9474 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9475 {
9476         struct tg3 *tp = netdev_priv(dev);
9477         int ret;
9478         u8  *pd;
9479         u32 i, offset, len, b_offset, b_count;
9480         __be32 val;
9481
9482         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9483                 return -EINVAL;
9484
9485         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9486                 return -EAGAIN;
9487
9488         offset = eeprom->offset;
9489         len = eeprom->len;
9490         eeprom->len = 0;
9491
9492         eeprom->magic = TG3_EEPROM_MAGIC;
9493
9494         if (offset & 3) {
9495                 /* adjustments to start on required 4 byte boundary */
9496                 b_offset = offset & 3;
9497                 b_count = 4 - b_offset;
9498                 if (b_count > len) {
9499                         /* i.e. offset=1 len=2 */
9500                         b_count = len;
9501                 }
9502                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9503                 if (ret)
9504                         return ret;
9505                 memcpy(data, ((char *)&val) + b_offset, b_count);
9506                 len -= b_count;
9507                 offset += b_count;
9508                 eeprom->len += b_count;
9509         }
9510
9511         /* read bytes upto the last 4 byte boundary */
9512         pd = &data[eeprom->len];
9513         for (i = 0; i < (len - (len & 3)); i += 4) {
9514                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9515                 if (ret) {
9516                         eeprom->len += i;
9517                         return ret;
9518                 }
9519                 memcpy(pd + i, &val, 4);
9520         }
9521         eeprom->len += i;
9522
9523         if (len & 3) {
9524                 /* read last bytes not ending on 4 byte boundary */
9525                 pd = &data[eeprom->len];
9526                 b_count = len & 3;
9527                 b_offset = offset + len - b_count;
9528                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9529                 if (ret)
9530                         return ret;
9531                 memcpy(pd, &val, b_count);
9532                 eeprom->len += b_count;
9533         }
9534         return 0;
9535 }
9536
9537 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9538
9539 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9540 {
9541         struct tg3 *tp = netdev_priv(dev);
9542         int ret;
9543         u32 offset, len, b_offset, odd_len;
9544         u8 *buf;
9545         __be32 start, end;
9546
9547         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9548                 return -EAGAIN;
9549
9550         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9551             eeprom->magic != TG3_EEPROM_MAGIC)
9552                 return -EINVAL;
9553
9554         offset = eeprom->offset;
9555         len = eeprom->len;
9556
9557         if ((b_offset = (offset & 3))) {
9558                 /* adjustments to start on required 4 byte boundary */
9559                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9560                 if (ret)
9561                         return ret;
9562                 len += b_offset;
9563                 offset &= ~3;
9564                 if (len < 4)
9565                         len = 4;
9566         }
9567
9568         odd_len = 0;
9569         if (len & 3) {
9570                 /* adjustments to end on required 4 byte boundary */
9571                 odd_len = 1;
9572                 len = (len + 3) & ~3;
9573                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9574                 if (ret)
9575                         return ret;
9576         }
9577
9578         buf = data;
9579         if (b_offset || odd_len) {
9580                 buf = kmalloc(len, GFP_KERNEL);
9581                 if (!buf)
9582                         return -ENOMEM;
9583                 if (b_offset)
9584                         memcpy(buf, &start, 4);
9585                 if (odd_len)
9586                         memcpy(buf+len-4, &end, 4);
9587                 memcpy(buf + b_offset, data, eeprom->len);
9588         }
9589
9590         ret = tg3_nvram_write_block(tp, offset, len, buf);
9591
9592         if (buf != data)
9593                 kfree(buf);
9594
9595         return ret;
9596 }
9597
9598 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9599 {
9600         struct tg3 *tp = netdev_priv(dev);
9601
9602         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9603                 struct phy_device *phydev;
9604                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9605                         return -EAGAIN;
9606                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9607                 return phy_ethtool_gset(phydev, cmd);
9608         }
9609
9610         cmd->supported = (SUPPORTED_Autoneg);
9611
9612         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9613                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9614                                    SUPPORTED_1000baseT_Full);
9615
9616         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
9617                 cmd->supported |= (SUPPORTED_100baseT_Half |
9618                                   SUPPORTED_100baseT_Full |
9619                                   SUPPORTED_10baseT_Half |
9620                                   SUPPORTED_10baseT_Full |
9621                                   SUPPORTED_TP);
9622                 cmd->port = PORT_TP;
9623         } else {
9624                 cmd->supported |= SUPPORTED_FIBRE;
9625                 cmd->port = PORT_FIBRE;
9626         }
9627
9628         cmd->advertising = tp->link_config.advertising;
9629         if (netif_running(dev)) {
9630                 cmd->speed = tp->link_config.active_speed;
9631                 cmd->duplex = tp->link_config.active_duplex;
9632         }
9633         cmd->phy_address = tp->phy_addr;
9634         cmd->transceiver = XCVR_INTERNAL;
9635         cmd->autoneg = tp->link_config.autoneg;
9636         cmd->maxtxpkt = 0;
9637         cmd->maxrxpkt = 0;
9638         return 0;
9639 }
9640
9641 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9642 {
9643         struct tg3 *tp = netdev_priv(dev);
9644
9645         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9646                 struct phy_device *phydev;
9647                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9648                         return -EAGAIN;
9649                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9650                 return phy_ethtool_sset(phydev, cmd);
9651         }
9652
9653         if (cmd->autoneg != AUTONEG_ENABLE &&
9654             cmd->autoneg != AUTONEG_DISABLE)
9655                 return -EINVAL;
9656
9657         if (cmd->autoneg == AUTONEG_DISABLE &&
9658             cmd->duplex != DUPLEX_FULL &&
9659             cmd->duplex != DUPLEX_HALF)
9660                 return -EINVAL;
9661
9662         if (cmd->autoneg == AUTONEG_ENABLE) {
9663                 u32 mask = ADVERTISED_Autoneg |
9664                            ADVERTISED_Pause |
9665                            ADVERTISED_Asym_Pause;
9666
9667                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9668                         mask |= ADVERTISED_1000baseT_Half |
9669                                 ADVERTISED_1000baseT_Full;
9670
9671                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
9672                         mask |= ADVERTISED_100baseT_Half |
9673                                 ADVERTISED_100baseT_Full |
9674                                 ADVERTISED_10baseT_Half |
9675                                 ADVERTISED_10baseT_Full |
9676                                 ADVERTISED_TP;
9677                 else
9678                         mask |= ADVERTISED_FIBRE;
9679
9680                 if (cmd->advertising & ~mask)
9681                         return -EINVAL;
9682
9683                 mask &= (ADVERTISED_1000baseT_Half |
9684                          ADVERTISED_1000baseT_Full |
9685                          ADVERTISED_100baseT_Half |
9686                          ADVERTISED_100baseT_Full |
9687                          ADVERTISED_10baseT_Half |
9688                          ADVERTISED_10baseT_Full);
9689
9690                 cmd->advertising &= mask;
9691         } else {
9692                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
9693                         if (cmd->speed != SPEED_1000)
9694                                 return -EINVAL;
9695
9696                         if (cmd->duplex != DUPLEX_FULL)
9697                                 return -EINVAL;
9698                 } else {
9699                         if (cmd->speed != SPEED_100 &&
9700                             cmd->speed != SPEED_10)
9701                                 return -EINVAL;
9702                 }
9703         }
9704
9705         tg3_full_lock(tp, 0);
9706
9707         tp->link_config.autoneg = cmd->autoneg;
9708         if (cmd->autoneg == AUTONEG_ENABLE) {
9709                 tp->link_config.advertising = (cmd->advertising |
9710                                               ADVERTISED_Autoneg);
9711                 tp->link_config.speed = SPEED_INVALID;
9712                 tp->link_config.duplex = DUPLEX_INVALID;
9713         } else {
9714                 tp->link_config.advertising = 0;
9715                 tp->link_config.speed = cmd->speed;
9716                 tp->link_config.duplex = cmd->duplex;
9717         }
9718
9719         tp->link_config.orig_speed = tp->link_config.speed;
9720         tp->link_config.orig_duplex = tp->link_config.duplex;
9721         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9722
9723         if (netif_running(dev))
9724                 tg3_setup_phy(tp, 1);
9725
9726         tg3_full_unlock(tp);
9727
9728         return 0;
9729 }
9730
9731 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9732 {
9733         struct tg3 *tp = netdev_priv(dev);
9734
9735         strcpy(info->driver, DRV_MODULE_NAME);
9736         strcpy(info->version, DRV_MODULE_VERSION);
9737         strcpy(info->fw_version, tp->fw_ver);
9738         strcpy(info->bus_info, pci_name(tp->pdev));
9739 }
9740
9741 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9742 {
9743         struct tg3 *tp = netdev_priv(dev);
9744
9745         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9746             device_can_wakeup(&tp->pdev->dev))
9747                 wol->supported = WAKE_MAGIC;
9748         else
9749                 wol->supported = 0;
9750         wol->wolopts = 0;
9751         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9752             device_can_wakeup(&tp->pdev->dev))
9753                 wol->wolopts = WAKE_MAGIC;
9754         memset(&wol->sopass, 0, sizeof(wol->sopass));
9755 }
9756
9757 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9758 {
9759         struct tg3 *tp = netdev_priv(dev);
9760         struct device *dp = &tp->pdev->dev;
9761
9762         if (wol->wolopts & ~WAKE_MAGIC)
9763                 return -EINVAL;
9764         if ((wol->wolopts & WAKE_MAGIC) &&
9765             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9766                 return -EINVAL;
9767
9768         spin_lock_bh(&tp->lock);
9769         if (wol->wolopts & WAKE_MAGIC) {
9770                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9771                 device_set_wakeup_enable(dp, true);
9772         } else {
9773                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9774                 device_set_wakeup_enable(dp, false);
9775         }
9776         spin_unlock_bh(&tp->lock);
9777
9778         return 0;
9779 }
9780
9781 static u32 tg3_get_msglevel(struct net_device *dev)
9782 {
9783         struct tg3 *tp = netdev_priv(dev);
9784         return tp->msg_enable;
9785 }
9786
9787 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9788 {
9789         struct tg3 *tp = netdev_priv(dev);
9790         tp->msg_enable = value;
9791 }
9792
9793 static int tg3_set_tso(struct net_device *dev, u32 value)
9794 {
9795         struct tg3 *tp = netdev_priv(dev);
9796
9797         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9798                 if (value)
9799                         return -EINVAL;
9800                 return 0;
9801         }
9802         if ((dev->features & NETIF_F_IPV6_CSUM) &&
9803             ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9804              (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9805                 if (value) {
9806                         dev->features |= NETIF_F_TSO6;
9807                         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9808                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9809                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9810                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9811                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9812                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9813                                 dev->features |= NETIF_F_TSO_ECN;
9814                 } else
9815                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9816         }
9817         return ethtool_op_set_tso(dev, value);
9818 }
9819
9820 static int tg3_nway_reset(struct net_device *dev)
9821 {
9822         struct tg3 *tp = netdev_priv(dev);
9823         int r;
9824
9825         if (!netif_running(dev))
9826                 return -EAGAIN;
9827
9828         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
9829                 return -EINVAL;
9830
9831         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9832                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9833                         return -EAGAIN;
9834                 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9835         } else {
9836                 u32 bmcr;
9837
9838                 spin_lock_bh(&tp->lock);
9839                 r = -EINVAL;
9840                 tg3_readphy(tp, MII_BMCR, &bmcr);
9841                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9842                     ((bmcr & BMCR_ANENABLE) ||
9843                      (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
9844                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9845                                                    BMCR_ANENABLE);
9846                         r = 0;
9847                 }
9848                 spin_unlock_bh(&tp->lock);
9849         }
9850
9851         return r;
9852 }
9853
9854 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9855 {
9856         struct tg3 *tp = netdev_priv(dev);
9857
9858         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9859         ering->rx_mini_max_pending = 0;
9860         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9861                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9862         else
9863                 ering->rx_jumbo_max_pending = 0;
9864
9865         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9866
9867         ering->rx_pending = tp->rx_pending;
9868         ering->rx_mini_pending = 0;
9869         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9870                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9871         else
9872                 ering->rx_jumbo_pending = 0;
9873
9874         ering->tx_pending = tp->napi[0].tx_pending;
9875 }
9876
9877 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9878 {
9879         struct tg3 *tp = netdev_priv(dev);
9880         int i, irq_sync = 0, err = 0;
9881
9882         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9883             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9884             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9885             (ering->tx_pending <= MAX_SKB_FRAGS) ||
9886             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9887              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9888                 return -EINVAL;
9889
9890         if (netif_running(dev)) {
9891                 tg3_phy_stop(tp);
9892                 tg3_netif_stop(tp);
9893                 irq_sync = 1;
9894         }
9895
9896         tg3_full_lock(tp, irq_sync);
9897
9898         tp->rx_pending = ering->rx_pending;
9899
9900         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9901             tp->rx_pending > 63)
9902                 tp->rx_pending = 63;
9903         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9904
9905         for (i = 0; i < tp->irq_max; i++)
9906                 tp->napi[i].tx_pending = ering->tx_pending;
9907
9908         if (netif_running(dev)) {
9909                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9910                 err = tg3_restart_hw(tp, 1);
9911                 if (!err)
9912                         tg3_netif_start(tp);
9913         }
9914
9915         tg3_full_unlock(tp);
9916
9917         if (irq_sync && !err)
9918                 tg3_phy_start(tp);
9919
9920         return err;
9921 }
9922
9923 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9924 {
9925         struct tg3 *tp = netdev_priv(dev);
9926
9927         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9928
9929         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9930                 epause->rx_pause = 1;
9931         else
9932                 epause->rx_pause = 0;
9933
9934         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9935                 epause->tx_pause = 1;
9936         else
9937                 epause->tx_pause = 0;
9938 }
9939
9940 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9941 {
9942         struct tg3 *tp = netdev_priv(dev);
9943         int err = 0;
9944
9945         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9946                 u32 newadv;
9947                 struct phy_device *phydev;
9948
9949                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9950
9951                 if (!(phydev->supported & SUPPORTED_Pause) ||
9952                     (!(phydev->supported & SUPPORTED_Asym_Pause) &&
9953                      ((epause->rx_pause && !epause->tx_pause) ||
9954                       (!epause->rx_pause && epause->tx_pause))))
9955                         return -EINVAL;
9956
9957                 tp->link_config.flowctrl = 0;
9958                 if (epause->rx_pause) {
9959                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
9960
9961                         if (epause->tx_pause) {
9962                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9963                                 newadv = ADVERTISED_Pause;
9964                         } else
9965                                 newadv = ADVERTISED_Pause |
9966                                          ADVERTISED_Asym_Pause;
9967                 } else if (epause->tx_pause) {
9968                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
9969                         newadv = ADVERTISED_Asym_Pause;
9970                 } else
9971                         newadv = 0;
9972
9973                 if (epause->autoneg)
9974                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9975                 else
9976                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9977
9978                 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
9979                         u32 oldadv = phydev->advertising &
9980                                      (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
9981                         if (oldadv != newadv) {
9982                                 phydev->advertising &=
9983                                         ~(ADVERTISED_Pause |
9984                                           ADVERTISED_Asym_Pause);
9985                                 phydev->advertising |= newadv;
9986                                 if (phydev->autoneg) {
9987                                         /*
9988                                          * Always renegotiate the link to
9989                                          * inform our link partner of our
9990                                          * flow control settings, even if the
9991                                          * flow control is forced.  Let
9992                                          * tg3_adjust_link() do the final
9993                                          * flow control setup.
9994                                          */
9995                                         return phy_start_aneg(phydev);
9996                                 }
9997                         }
9998
9999                         if (!epause->autoneg)
10000                                 tg3_setup_flow_control(tp, 0, 0);
10001                 } else {
10002                         tp->link_config.orig_advertising &=
10003                                         ~(ADVERTISED_Pause |
10004                                           ADVERTISED_Asym_Pause);
10005                         tp->link_config.orig_advertising |= newadv;
10006                 }
10007         } else {
10008                 int irq_sync = 0;
10009
10010                 if (netif_running(dev)) {
10011                         tg3_netif_stop(tp);
10012                         irq_sync = 1;
10013                 }
10014
10015                 tg3_full_lock(tp, irq_sync);
10016
10017                 if (epause->autoneg)
10018                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10019                 else
10020                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10021                 if (epause->rx_pause)
10022                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
10023                 else
10024                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10025                 if (epause->tx_pause)
10026                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
10027                 else
10028                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10029
10030                 if (netif_running(dev)) {
10031                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10032                         err = tg3_restart_hw(tp, 1);
10033                         if (!err)
10034                                 tg3_netif_start(tp);
10035                 }
10036
10037                 tg3_full_unlock(tp);
10038         }
10039
10040         return err;
10041 }
10042
10043 static u32 tg3_get_rx_csum(struct net_device *dev)
10044 {
10045         struct tg3 *tp = netdev_priv(dev);
10046         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10047 }
10048
10049 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10050 {
10051         struct tg3 *tp = netdev_priv(dev);
10052
10053         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10054                 if (data != 0)
10055                         return -EINVAL;
10056                 return 0;
10057         }
10058
10059         spin_lock_bh(&tp->lock);
10060         if (data)
10061                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10062         else
10063                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10064         spin_unlock_bh(&tp->lock);
10065
10066         return 0;
10067 }
10068
10069 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10070 {
10071         struct tg3 *tp = netdev_priv(dev);
10072
10073         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10074                 if (data != 0)
10075                         return -EINVAL;
10076                 return 0;
10077         }
10078
10079         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10080                 ethtool_op_set_tx_ipv6_csum(dev, data);
10081         else
10082                 ethtool_op_set_tx_csum(dev, data);
10083
10084         return 0;
10085 }
10086
10087 static int tg3_get_sset_count(struct net_device *dev, int sset)
10088 {
10089         switch (sset) {
10090         case ETH_SS_TEST:
10091                 return TG3_NUM_TEST;
10092         case ETH_SS_STATS:
10093                 return TG3_NUM_STATS;
10094         default:
10095                 return -EOPNOTSUPP;
10096         }
10097 }
10098
10099 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
10100 {
10101         switch (stringset) {
10102         case ETH_SS_STATS:
10103                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10104                 break;
10105         case ETH_SS_TEST:
10106                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10107                 break;
10108         default:
10109                 WARN_ON(1);     /* we need a WARN() */
10110                 break;
10111         }
10112 }
10113
10114 static int tg3_phys_id(struct net_device *dev, u32 data)
10115 {
10116         struct tg3 *tp = netdev_priv(dev);
10117         int i;
10118
10119         if (!netif_running(tp->dev))
10120                 return -EAGAIN;
10121
10122         if (data == 0)
10123                 data = UINT_MAX / 2;
10124
10125         for (i = 0; i < (data * 2); i++) {
10126                 if ((i % 2) == 0)
10127                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10128                                            LED_CTRL_1000MBPS_ON |
10129                                            LED_CTRL_100MBPS_ON |
10130                                            LED_CTRL_10MBPS_ON |
10131                                            LED_CTRL_TRAFFIC_OVERRIDE |
10132                                            LED_CTRL_TRAFFIC_BLINK |
10133                                            LED_CTRL_TRAFFIC_LED);
10134
10135                 else
10136                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10137                                            LED_CTRL_TRAFFIC_OVERRIDE);
10138
10139                 if (msleep_interruptible(500))
10140                         break;
10141         }
10142         tw32(MAC_LED_CTRL, tp->led_ctrl);
10143         return 0;
10144 }
10145
10146 static void tg3_get_ethtool_stats(struct net_device *dev,
10147                                    struct ethtool_stats *estats, u64 *tmp_stats)
10148 {
10149         struct tg3 *tp = netdev_priv(dev);
10150         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10151 }
10152
10153 #define NVRAM_TEST_SIZE 0x100
10154 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
10155 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
10156 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
10157 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10158 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10159
10160 static int tg3_test_nvram(struct tg3 *tp)
10161 {
10162         u32 csum, magic;
10163         __be32 *buf;
10164         int i, j, k, err = 0, size;
10165
10166         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10167                 return 0;
10168
10169         if (tg3_nvram_read(tp, 0, &magic) != 0)
10170                 return -EIO;
10171
10172         if (magic == TG3_EEPROM_MAGIC)
10173                 size = NVRAM_TEST_SIZE;
10174         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10175                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10176                     TG3_EEPROM_SB_FORMAT_1) {
10177                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10178                         case TG3_EEPROM_SB_REVISION_0:
10179                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10180                                 break;
10181                         case TG3_EEPROM_SB_REVISION_2:
10182                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10183                                 break;
10184                         case TG3_EEPROM_SB_REVISION_3:
10185                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10186                                 break;
10187                         default:
10188                                 return 0;
10189                         }
10190                 } else
10191                         return 0;
10192         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10193                 size = NVRAM_SELFBOOT_HW_SIZE;
10194         else
10195                 return -EIO;
10196
10197         buf = kmalloc(size, GFP_KERNEL);
10198         if (buf == NULL)
10199                 return -ENOMEM;
10200
10201         err = -EIO;
10202         for (i = 0, j = 0; i < size; i += 4, j++) {
10203                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10204                 if (err)
10205                         break;
10206         }
10207         if (i < size)
10208                 goto out;
10209
10210         /* Selfboot format */
10211         magic = be32_to_cpu(buf[0]);
10212         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10213             TG3_EEPROM_MAGIC_FW) {
10214                 u8 *buf8 = (u8 *) buf, csum8 = 0;
10215
10216                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10217                     TG3_EEPROM_SB_REVISION_2) {
10218                         /* For rev 2, the csum doesn't include the MBA. */
10219                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10220                                 csum8 += buf8[i];
10221                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10222                                 csum8 += buf8[i];
10223                 } else {
10224                         for (i = 0; i < size; i++)
10225                                 csum8 += buf8[i];
10226                 }
10227
10228                 if (csum8 == 0) {
10229                         err = 0;
10230                         goto out;
10231                 }
10232
10233                 err = -EIO;
10234                 goto out;
10235         }
10236
10237         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10238             TG3_EEPROM_MAGIC_HW) {
10239                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10240                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10241                 u8 *buf8 = (u8 *) buf;
10242
10243                 /* Separate the parity bits and the data bytes.  */
10244                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10245                         if ((i == 0) || (i == 8)) {
10246                                 int l;
10247                                 u8 msk;
10248
10249                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10250                                         parity[k++] = buf8[i] & msk;
10251                                 i++;
10252                         } else if (i == 16) {
10253                                 int l;
10254                                 u8 msk;
10255
10256                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10257                                         parity[k++] = buf8[i] & msk;
10258                                 i++;
10259
10260                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10261                                         parity[k++] = buf8[i] & msk;
10262                                 i++;
10263                         }
10264                         data[j++] = buf8[i];
10265                 }
10266
10267                 err = -EIO;
10268                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10269                         u8 hw8 = hweight8(data[i]);
10270
10271                         if ((hw8 & 0x1) && parity[i])
10272                                 goto out;
10273                         else if (!(hw8 & 0x1) && !parity[i])
10274                                 goto out;
10275                 }
10276                 err = 0;
10277                 goto out;
10278         }
10279
10280         /* Bootstrap checksum at offset 0x10 */
10281         csum = calc_crc((unsigned char *) buf, 0x10);
10282         if (csum != be32_to_cpu(buf[0x10/4]))
10283                 goto out;
10284
10285         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10286         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10287         if (csum != be32_to_cpu(buf[0xfc/4]))
10288                 goto out;
10289
10290         err = 0;
10291
10292 out:
10293         kfree(buf);
10294         return err;
10295 }
10296
10297 #define TG3_SERDES_TIMEOUT_SEC  2
10298 #define TG3_COPPER_TIMEOUT_SEC  6
10299
10300 static int tg3_test_link(struct tg3 *tp)
10301 {
10302         int i, max;
10303
10304         if (!netif_running(tp->dev))
10305                 return -ENODEV;
10306
10307         if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
10308                 max = TG3_SERDES_TIMEOUT_SEC;
10309         else
10310                 max = TG3_COPPER_TIMEOUT_SEC;
10311
10312         for (i = 0; i < max; i++) {
10313                 if (netif_carrier_ok(tp->dev))
10314                         return 0;
10315
10316                 if (msleep_interruptible(1000))
10317                         break;
10318         }
10319
10320         return -EIO;
10321 }
10322
10323 /* Only test the commonly used registers */
10324 static int tg3_test_registers(struct tg3 *tp)
10325 {
10326         int i, is_5705, is_5750;
10327         u32 offset, read_mask, write_mask, val, save_val, read_val;
10328         static struct {
10329                 u16 offset;
10330                 u16 flags;
10331 #define TG3_FL_5705     0x1
10332 #define TG3_FL_NOT_5705 0x2
10333 #define TG3_FL_NOT_5788 0x4
10334 #define TG3_FL_NOT_5750 0x8
10335                 u32 read_mask;
10336                 u32 write_mask;
10337         } reg_tbl[] = {
10338                 /* MAC Control Registers */
10339                 { MAC_MODE, TG3_FL_NOT_5705,
10340                         0x00000000, 0x00ef6f8c },
10341                 { MAC_MODE, TG3_FL_5705,
10342                         0x00000000, 0x01ef6b8c },
10343                 { MAC_STATUS, TG3_FL_NOT_5705,
10344                         0x03800107, 0x00000000 },
10345                 { MAC_STATUS, TG3_FL_5705,
10346                         0x03800100, 0x00000000 },
10347                 { MAC_ADDR_0_HIGH, 0x0000,
10348                         0x00000000, 0x0000ffff },
10349                 { MAC_ADDR_0_LOW, 0x0000,
10350                         0x00000000, 0xffffffff },
10351                 { MAC_RX_MTU_SIZE, 0x0000,
10352                         0x00000000, 0x0000ffff },
10353                 { MAC_TX_MODE, 0x0000,
10354                         0x00000000, 0x00000070 },
10355                 { MAC_TX_LENGTHS, 0x0000,
10356                         0x00000000, 0x00003fff },
10357                 { MAC_RX_MODE, TG3_FL_NOT_5705,
10358                         0x00000000, 0x000007fc },
10359                 { MAC_RX_MODE, TG3_FL_5705,
10360                         0x00000000, 0x000007dc },
10361                 { MAC_HASH_REG_0, 0x0000,
10362                         0x00000000, 0xffffffff },
10363                 { MAC_HASH_REG_1, 0x0000,
10364                         0x00000000, 0xffffffff },
10365                 { MAC_HASH_REG_2, 0x0000,
10366                         0x00000000, 0xffffffff },
10367                 { MAC_HASH_REG_3, 0x0000,
10368                         0x00000000, 0xffffffff },
10369
10370                 /* Receive Data and Receive BD Initiator Control Registers. */
10371                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10372                         0x00000000, 0xffffffff },
10373                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10374                         0x00000000, 0xffffffff },
10375                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10376                         0x00000000, 0x00000003 },
10377                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10378                         0x00000000, 0xffffffff },
10379                 { RCVDBDI_STD_BD+0, 0x0000,
10380                         0x00000000, 0xffffffff },
10381                 { RCVDBDI_STD_BD+4, 0x0000,
10382                         0x00000000, 0xffffffff },
10383                 { RCVDBDI_STD_BD+8, 0x0000,
10384                         0x00000000, 0xffff0002 },
10385                 { RCVDBDI_STD_BD+0xc, 0x0000,
10386                         0x00000000, 0xffffffff },
10387
10388                 /* Receive BD Initiator Control Registers. */
10389                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10390                         0x00000000, 0xffffffff },
10391                 { RCVBDI_STD_THRESH, TG3_FL_5705,
10392                         0x00000000, 0x000003ff },
10393                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10394                         0x00000000, 0xffffffff },
10395
10396                 /* Host Coalescing Control Registers. */
10397                 { HOSTCC_MODE, TG3_FL_NOT_5705,
10398                         0x00000000, 0x00000004 },
10399                 { HOSTCC_MODE, TG3_FL_5705,
10400                         0x00000000, 0x000000f6 },
10401                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10402                         0x00000000, 0xffffffff },
10403                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10404                         0x00000000, 0x000003ff },
10405                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10406                         0x00000000, 0xffffffff },
10407                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10408                         0x00000000, 0x000003ff },
10409                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10410                         0x00000000, 0xffffffff },
10411                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10412                         0x00000000, 0x000000ff },
10413                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10414                         0x00000000, 0xffffffff },
10415                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10416                         0x00000000, 0x000000ff },
10417                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10418                         0x00000000, 0xffffffff },
10419                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10420                         0x00000000, 0xffffffff },
10421                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10422                         0x00000000, 0xffffffff },
10423                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10424                         0x00000000, 0x000000ff },
10425                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10426                         0x00000000, 0xffffffff },
10427                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10428                         0x00000000, 0x000000ff },
10429                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10430                         0x00000000, 0xffffffff },
10431                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10432                         0x00000000, 0xffffffff },
10433                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10434                         0x00000000, 0xffffffff },
10435                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10436                         0x00000000, 0xffffffff },
10437                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10438                         0x00000000, 0xffffffff },
10439                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10440                         0xffffffff, 0x00000000 },
10441                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10442                         0xffffffff, 0x00000000 },
10443
10444                 /* Buffer Manager Control Registers. */
10445                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10446                         0x00000000, 0x007fff80 },
10447                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10448                         0x00000000, 0x007fffff },
10449                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10450                         0x00000000, 0x0000003f },
10451                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10452                         0x00000000, 0x000001ff },
10453                 { BUFMGR_MB_HIGH_WATER, 0x0000,
10454                         0x00000000, 0x000001ff },
10455                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10456                         0xffffffff, 0x00000000 },
10457                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10458                         0xffffffff, 0x00000000 },
10459
10460                 /* Mailbox Registers */
10461                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10462                         0x00000000, 0x000001ff },
10463                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10464                         0x00000000, 0x000001ff },
10465                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10466                         0x00000000, 0x000007ff },
10467                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10468                         0x00000000, 0x000001ff },
10469
10470                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10471         };
10472
10473         is_5705 = is_5750 = 0;
10474         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10475                 is_5705 = 1;
10476                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10477                         is_5750 = 1;
10478         }
10479
10480         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10481                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10482                         continue;
10483
10484                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10485                         continue;
10486
10487                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10488                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
10489                         continue;
10490
10491                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10492                         continue;
10493
10494                 offset = (u32) reg_tbl[i].offset;
10495                 read_mask = reg_tbl[i].read_mask;
10496                 write_mask = reg_tbl[i].write_mask;
10497
10498                 /* Save the original register content */
10499                 save_val = tr32(offset);
10500
10501                 /* Determine the read-only value. */
10502                 read_val = save_val & read_mask;
10503
10504                 /* Write zero to the register, then make sure the read-only bits
10505                  * are not changed and the read/write bits are all zeros.
10506                  */
10507                 tw32(offset, 0);
10508
10509                 val = tr32(offset);
10510
10511                 /* Test the read-only and read/write bits. */
10512                 if (((val & read_mask) != read_val) || (val & write_mask))
10513                         goto out;
10514
10515                 /* Write ones to all the bits defined by RdMask and WrMask, then
10516                  * make sure the read-only bits are not changed and the
10517                  * read/write bits are all ones.
10518                  */
10519                 tw32(offset, read_mask | write_mask);
10520
10521                 val = tr32(offset);
10522
10523                 /* Test the read-only bits. */
10524                 if ((val & read_mask) != read_val)
10525                         goto out;
10526
10527                 /* Test the read/write bits. */
10528                 if ((val & write_mask) != write_mask)
10529                         goto out;
10530
10531                 tw32(offset, save_val);
10532         }
10533
10534         return 0;
10535
10536 out:
10537         if (netif_msg_hw(tp))
10538                 netdev_err(tp->dev,
10539                            "Register test failed at offset %x\n", offset);
10540         tw32(offset, save_val);
10541         return -EIO;
10542 }
10543
10544 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10545 {
10546         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10547         int i;
10548         u32 j;
10549
10550         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10551                 for (j = 0; j < len; j += 4) {
10552                         u32 val;
10553
10554                         tg3_write_mem(tp, offset + j, test_pattern[i]);
10555                         tg3_read_mem(tp, offset + j, &val);
10556                         if (val != test_pattern[i])
10557                                 return -EIO;
10558                 }
10559         }
10560         return 0;
10561 }
10562
10563 static int tg3_test_memory(struct tg3 *tp)
10564 {
10565         static struct mem_entry {
10566                 u32 offset;
10567                 u32 len;
10568         } mem_tbl_570x[] = {
10569                 { 0x00000000, 0x00b50},
10570                 { 0x00002000, 0x1c000},
10571                 { 0xffffffff, 0x00000}
10572         }, mem_tbl_5705[] = {
10573                 { 0x00000100, 0x0000c},
10574                 { 0x00000200, 0x00008},
10575                 { 0x00004000, 0x00800},
10576                 { 0x00006000, 0x01000},
10577                 { 0x00008000, 0x02000},
10578                 { 0x00010000, 0x0e000},
10579                 { 0xffffffff, 0x00000}
10580         }, mem_tbl_5755[] = {
10581                 { 0x00000200, 0x00008},
10582                 { 0x00004000, 0x00800},
10583                 { 0x00006000, 0x00800},
10584                 { 0x00008000, 0x02000},
10585                 { 0x00010000, 0x0c000},
10586                 { 0xffffffff, 0x00000}
10587         }, mem_tbl_5906[] = {
10588                 { 0x00000200, 0x00008},
10589                 { 0x00004000, 0x00400},
10590                 { 0x00006000, 0x00400},
10591                 { 0x00008000, 0x01000},
10592                 { 0x00010000, 0x01000},
10593                 { 0xffffffff, 0x00000}
10594         }, mem_tbl_5717[] = {
10595                 { 0x00000200, 0x00008},
10596                 { 0x00010000, 0x0a000},
10597                 { 0x00020000, 0x13c00},
10598                 { 0xffffffff, 0x00000}
10599         }, mem_tbl_57765[] = {
10600                 { 0x00000200, 0x00008},
10601                 { 0x00004000, 0x00800},
10602                 { 0x00006000, 0x09800},
10603                 { 0x00010000, 0x0a000},
10604                 { 0xffffffff, 0x00000}
10605         };
10606         struct mem_entry *mem_tbl;
10607         int err = 0;
10608         int i;
10609
10610         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
10611             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
10612                 mem_tbl = mem_tbl_5717;
10613         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10614                 mem_tbl = mem_tbl_57765;
10615         else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10616                 mem_tbl = mem_tbl_5755;
10617         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10618                 mem_tbl = mem_tbl_5906;
10619         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10620                 mem_tbl = mem_tbl_5705;
10621         else
10622                 mem_tbl = mem_tbl_570x;
10623
10624         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10625                 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
10626                 if (err)
10627                         break;
10628         }
10629
10630         return err;
10631 }
10632
10633 #define TG3_MAC_LOOPBACK        0
10634 #define TG3_PHY_LOOPBACK        1
10635
10636 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10637 {
10638         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10639         u32 desc_idx, coal_now;
10640         struct sk_buff *skb, *rx_skb;
10641         u8 *tx_data;
10642         dma_addr_t map;
10643         int num_pkts, tx_len, rx_len, i, err;
10644         struct tg3_rx_buffer_desc *desc;
10645         struct tg3_napi *tnapi, *rnapi;
10646         struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
10647
10648         tnapi = &tp->napi[0];
10649         rnapi = &tp->napi[0];
10650         if (tp->irq_cnt > 1) {
10651                 rnapi = &tp->napi[1];
10652                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
10653                         tnapi = &tp->napi[1];
10654         }
10655         coal_now = tnapi->coal_now | rnapi->coal_now;
10656
10657         if (loopback_mode == TG3_MAC_LOOPBACK) {
10658                 /* HW errata - mac loopback fails in some cases on 5780.
10659                  * Normal traffic and PHY loopback are not affected by
10660                  * errata.
10661                  */
10662                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10663                         return 0;
10664
10665                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10666                            MAC_MODE_PORT_INT_LPBACK;
10667                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10668                         mac_mode |= MAC_MODE_LINK_POLARITY;
10669                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
10670                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10671                 else
10672                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10673                 tw32(MAC_MODE, mac_mode);
10674         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10675                 u32 val;
10676
10677                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10678                         tg3_phy_fet_toggle_apd(tp, false);
10679                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10680                 } else
10681                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10682
10683                 tg3_phy_toggle_automdix(tp, 0);
10684
10685                 tg3_writephy(tp, MII_BMCR, val);
10686                 udelay(40);
10687
10688                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10689                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10690                         tg3_writephy(tp, MII_TG3_FET_PTEST,
10691                                      MII_TG3_FET_PTEST_FRC_TX_LINK |
10692                                      MII_TG3_FET_PTEST_FRC_TX_LOCK);
10693                         /* The write needs to be flushed for the AC131 */
10694                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10695                                 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
10696                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10697                 } else
10698                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10699
10700                 /* reset to prevent losing 1st rx packet intermittently */
10701                 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10702                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10703                         udelay(10);
10704                         tw32_f(MAC_RX_MODE, tp->rx_mode);
10705                 }
10706                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10707                         u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
10708                         if (masked_phy_id == TG3_PHY_ID_BCM5401)
10709                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10710                         else if (masked_phy_id == TG3_PHY_ID_BCM5411)
10711                                 mac_mode |= MAC_MODE_LINK_POLARITY;
10712                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
10713                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10714                 }
10715                 tw32(MAC_MODE, mac_mode);
10716         } else {
10717                 return -EINVAL;
10718         }
10719
10720         err = -EIO;
10721
10722         tx_len = 1514;
10723         skb = netdev_alloc_skb(tp->dev, tx_len);
10724         if (!skb)
10725                 return -ENOMEM;
10726
10727         tx_data = skb_put(skb, tx_len);
10728         memcpy(tx_data, tp->dev->dev_addr, 6);
10729         memset(tx_data + 6, 0x0, 8);
10730
10731         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10732
10733         for (i = 14; i < tx_len; i++)
10734                 tx_data[i] = (u8) (i & 0xff);
10735
10736         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10737         if (pci_dma_mapping_error(tp->pdev, map)) {
10738                 dev_kfree_skb(skb);
10739                 return -EIO;
10740         }
10741
10742         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10743                rnapi->coal_now);
10744
10745         udelay(10);
10746
10747         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10748
10749         num_pkts = 0;
10750
10751         tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10752
10753         tnapi->tx_prod++;
10754         num_pkts++;
10755
10756         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10757         tr32_mailbox(tnapi->prodmbox);
10758
10759         udelay(10);
10760
10761         /* 350 usec to allow enough time on some 10/100 Mbps devices.  */
10762         for (i = 0; i < 35; i++) {
10763                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10764                        coal_now);
10765
10766                 udelay(10);
10767
10768                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10769                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10770                 if ((tx_idx == tnapi->tx_prod) &&
10771                     (rx_idx == (rx_start_idx + num_pkts)))
10772                         break;
10773         }
10774
10775         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10776         dev_kfree_skb(skb);
10777
10778         if (tx_idx != tnapi->tx_prod)
10779                 goto out;
10780
10781         if (rx_idx != rx_start_idx + num_pkts)
10782                 goto out;
10783
10784         desc = &rnapi->rx_rcb[rx_start_idx];
10785         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10786         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10787         if (opaque_key != RXD_OPAQUE_RING_STD)
10788                 goto out;
10789
10790         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10791             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10792                 goto out;
10793
10794         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10795         if (rx_len != tx_len)
10796                 goto out;
10797
10798         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10799
10800         map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10801         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10802
10803         for (i = 14; i < tx_len; i++) {
10804                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10805                         goto out;
10806         }
10807         err = 0;
10808
10809         /* tg3_free_rings will unmap and free the rx_skb */
10810 out:
10811         return err;
10812 }
10813
10814 #define TG3_MAC_LOOPBACK_FAILED         1
10815 #define TG3_PHY_LOOPBACK_FAILED         2
10816 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
10817                                          TG3_PHY_LOOPBACK_FAILED)
10818
10819 static int tg3_test_loopback(struct tg3 *tp)
10820 {
10821         int err = 0;
10822         u32 cpmuctrl = 0;
10823
10824         if (!netif_running(tp->dev))
10825                 return TG3_LOOPBACK_FAILED;
10826
10827         err = tg3_reset_hw(tp, 1);
10828         if (err)
10829                 return TG3_LOOPBACK_FAILED;
10830
10831         /* Turn off gphy autopowerdown. */
10832         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
10833                 tg3_phy_toggle_apd(tp, false);
10834
10835         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10836                 int i;
10837                 u32 status;
10838
10839                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10840
10841                 /* Wait for up to 40 microseconds to acquire lock. */
10842                 for (i = 0; i < 4; i++) {
10843                         status = tr32(TG3_CPMU_MUTEX_GNT);
10844                         if (status == CPMU_MUTEX_GNT_DRIVER)
10845                                 break;
10846                         udelay(10);
10847                 }
10848
10849                 if (status != CPMU_MUTEX_GNT_DRIVER)
10850                         return TG3_LOOPBACK_FAILED;
10851
10852                 /* Turn off link-based power management. */
10853                 cpmuctrl = tr32(TG3_CPMU_CTRL);
10854                 tw32(TG3_CPMU_CTRL,
10855                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10856                                   CPMU_CTRL_LINK_AWARE_MODE));
10857         }
10858
10859         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10860                 err |= TG3_MAC_LOOPBACK_FAILED;
10861
10862         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10863                 tw32(TG3_CPMU_CTRL, cpmuctrl);
10864
10865                 /* Release the mutex */
10866                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10867         }
10868
10869         if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10870             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10871                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10872                         err |= TG3_PHY_LOOPBACK_FAILED;
10873         }
10874
10875         /* Re-enable gphy autopowerdown. */
10876         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
10877                 tg3_phy_toggle_apd(tp, true);
10878
10879         return err;
10880 }
10881
10882 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10883                           u64 *data)
10884 {
10885         struct tg3 *tp = netdev_priv(dev);
10886
10887         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10888                 tg3_set_power_state(tp, PCI_D0);
10889
10890         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10891
10892         if (tg3_test_nvram(tp) != 0) {
10893                 etest->flags |= ETH_TEST_FL_FAILED;
10894                 data[0] = 1;
10895         }
10896         if (tg3_test_link(tp) != 0) {
10897                 etest->flags |= ETH_TEST_FL_FAILED;
10898                 data[1] = 1;
10899         }
10900         if (etest->flags & ETH_TEST_FL_OFFLINE) {
10901                 int err, err2 = 0, irq_sync = 0;
10902
10903                 if (netif_running(dev)) {
10904                         tg3_phy_stop(tp);
10905                         tg3_netif_stop(tp);
10906                         irq_sync = 1;
10907                 }
10908
10909                 tg3_full_lock(tp, irq_sync);
10910
10911                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10912                 err = tg3_nvram_lock(tp);
10913                 tg3_halt_cpu(tp, RX_CPU_BASE);
10914                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10915                         tg3_halt_cpu(tp, TX_CPU_BASE);
10916                 if (!err)
10917                         tg3_nvram_unlock(tp);
10918
10919                 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
10920                         tg3_phy_reset(tp);
10921
10922                 if (tg3_test_registers(tp) != 0) {
10923                         etest->flags |= ETH_TEST_FL_FAILED;
10924                         data[2] = 1;
10925                 }
10926                 if (tg3_test_memory(tp) != 0) {
10927                         etest->flags |= ETH_TEST_FL_FAILED;
10928                         data[3] = 1;
10929                 }
10930                 if ((data[4] = tg3_test_loopback(tp)) != 0)
10931                         etest->flags |= ETH_TEST_FL_FAILED;
10932
10933                 tg3_full_unlock(tp);
10934
10935                 if (tg3_test_interrupt(tp) != 0) {
10936                         etest->flags |= ETH_TEST_FL_FAILED;
10937                         data[5] = 1;
10938                 }
10939
10940                 tg3_full_lock(tp, 0);
10941
10942                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10943                 if (netif_running(dev)) {
10944                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10945                         err2 = tg3_restart_hw(tp, 1);
10946                         if (!err2)
10947                                 tg3_netif_start(tp);
10948                 }
10949
10950                 tg3_full_unlock(tp);
10951
10952                 if (irq_sync && !err2)
10953                         tg3_phy_start(tp);
10954         }
10955         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10956                 tg3_set_power_state(tp, PCI_D3hot);
10957
10958 }
10959
10960 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10961 {
10962         struct mii_ioctl_data *data = if_mii(ifr);
10963         struct tg3 *tp = netdev_priv(dev);
10964         int err;
10965
10966         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10967                 struct phy_device *phydev;
10968                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10969                         return -EAGAIN;
10970                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10971                 return phy_mii_ioctl(phydev, ifr, cmd);
10972         }
10973
10974         switch (cmd) {
10975         case SIOCGMIIPHY:
10976                 data->phy_id = tp->phy_addr;
10977
10978                 /* fallthru */
10979         case SIOCGMIIREG: {
10980                 u32 mii_regval;
10981
10982                 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
10983                         break;                  /* We have no PHY */
10984
10985                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10986                         return -EAGAIN;
10987
10988                 spin_lock_bh(&tp->lock);
10989                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10990                 spin_unlock_bh(&tp->lock);
10991
10992                 data->val_out = mii_regval;
10993
10994                 return err;
10995         }
10996
10997         case SIOCSMIIREG:
10998                 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
10999                         break;                  /* We have no PHY */
11000
11001                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11002                         return -EAGAIN;
11003
11004                 spin_lock_bh(&tp->lock);
11005                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
11006                 spin_unlock_bh(&tp->lock);
11007
11008                 return err;
11009
11010         default:
11011                 /* do nothing */
11012                 break;
11013         }
11014         return -EOPNOTSUPP;
11015 }
11016
11017 #if TG3_VLAN_TAG_USED
11018 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
11019 {
11020         struct tg3 *tp = netdev_priv(dev);
11021
11022         if (!netif_running(dev)) {
11023                 tp->vlgrp = grp;
11024                 return;
11025         }
11026
11027         tg3_netif_stop(tp);
11028
11029         tg3_full_lock(tp, 0);
11030
11031         tp->vlgrp = grp;
11032
11033         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11034         __tg3_set_rx_mode(dev);
11035
11036         tg3_netif_start(tp);
11037
11038         tg3_full_unlock(tp);
11039 }
11040 #endif
11041
11042 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11043 {
11044         struct tg3 *tp = netdev_priv(dev);
11045
11046         memcpy(ec, &tp->coal, sizeof(*ec));
11047         return 0;
11048 }
11049
11050 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11051 {
11052         struct tg3 *tp = netdev_priv(dev);
11053         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11054         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11055
11056         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11057                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11058                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11059                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11060                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11061         }
11062
11063         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11064             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11065             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11066             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11067             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11068             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11069             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11070             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11071             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11072             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11073                 return -EINVAL;
11074
11075         /* No rx interrupts will be generated if both are zero */
11076         if ((ec->rx_coalesce_usecs == 0) &&
11077             (ec->rx_max_coalesced_frames == 0))
11078                 return -EINVAL;
11079
11080         /* No tx interrupts will be generated if both are zero */
11081         if ((ec->tx_coalesce_usecs == 0) &&
11082             (ec->tx_max_coalesced_frames == 0))
11083                 return -EINVAL;
11084
11085         /* Only copy relevant parameters, ignore all others. */
11086         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11087         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11088         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11089         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11090         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11091         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11092         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11093         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11094         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11095
11096         if (netif_running(dev)) {
11097                 tg3_full_lock(tp, 0);
11098                 __tg3_set_coalesce(tp, &tp->coal);
11099                 tg3_full_unlock(tp);
11100         }
11101         return 0;
11102 }
11103
11104 static const struct ethtool_ops tg3_ethtool_ops = {
11105         .get_settings           = tg3_get_settings,
11106         .set_settings           = tg3_set_settings,
11107         .get_drvinfo            = tg3_get_drvinfo,
11108         .get_regs_len           = tg3_get_regs_len,
11109         .get_regs               = tg3_get_regs,
11110         .get_wol                = tg3_get_wol,
11111         .set_wol                = tg3_set_wol,
11112         .get_msglevel           = tg3_get_msglevel,
11113         .set_msglevel           = tg3_set_msglevel,
11114         .nway_reset             = tg3_nway_reset,
11115         .get_link               = ethtool_op_get_link,
11116         .get_eeprom_len         = tg3_get_eeprom_len,
11117         .get_eeprom             = tg3_get_eeprom,
11118         .set_eeprom             = tg3_set_eeprom,
11119         .get_ringparam          = tg3_get_ringparam,
11120         .set_ringparam          = tg3_set_ringparam,
11121         .get_pauseparam         = tg3_get_pauseparam,
11122         .set_pauseparam         = tg3_set_pauseparam,
11123         .get_rx_csum            = tg3_get_rx_csum,
11124         .set_rx_csum            = tg3_set_rx_csum,
11125         .set_tx_csum            = tg3_set_tx_csum,
11126         .set_sg                 = ethtool_op_set_sg,
11127         .set_tso                = tg3_set_tso,
11128         .self_test              = tg3_self_test,
11129         .get_strings            = tg3_get_strings,
11130         .phys_id                = tg3_phys_id,
11131         .get_ethtool_stats      = tg3_get_ethtool_stats,
11132         .get_coalesce           = tg3_get_coalesce,
11133         .set_coalesce           = tg3_set_coalesce,
11134         .get_sset_count         = tg3_get_sset_count,
11135 };
11136
11137 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11138 {
11139         u32 cursize, val, magic;
11140
11141         tp->nvram_size = EEPROM_CHIP_SIZE;
11142
11143         if (tg3_nvram_read(tp, 0, &magic) != 0)
11144                 return;
11145
11146         if ((magic != TG3_EEPROM_MAGIC) &&
11147             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11148             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11149                 return;
11150
11151         /*
11152          * Size the chip by reading offsets at increasing powers of two.
11153          * When we encounter our validation signature, we know the addressing
11154          * has wrapped around, and thus have our chip size.
11155          */
11156         cursize = 0x10;
11157
11158         while (cursize < tp->nvram_size) {
11159                 if (tg3_nvram_read(tp, cursize, &val) != 0)
11160                         return;
11161
11162                 if (val == magic)
11163                         break;
11164
11165                 cursize <<= 1;
11166         }
11167
11168         tp->nvram_size = cursize;
11169 }
11170
11171 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11172 {
11173         u32 val;
11174
11175         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11176             tg3_nvram_read(tp, 0, &val) != 0)
11177                 return;
11178
11179         /* Selfboot format */
11180         if (val != TG3_EEPROM_MAGIC) {
11181                 tg3_get_eeprom_size(tp);
11182                 return;
11183         }
11184
11185         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11186                 if (val != 0) {
11187                         /* This is confusing.  We want to operate on the
11188                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
11189                          * call will read from NVRAM and byteswap the data
11190                          * according to the byteswapping settings for all
11191                          * other register accesses.  This ensures the data we
11192                          * want will always reside in the lower 16-bits.
11193                          * However, the data in NVRAM is in LE format, which
11194                          * means the data from the NVRAM read will always be
11195                          * opposite the endianness of the CPU.  The 16-bit
11196                          * byteswap then brings the data to CPU endianness.
11197                          */
11198                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11199                         return;
11200                 }
11201         }
11202         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11203 }
11204
11205 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11206 {
11207         u32 nvcfg1;
11208
11209         nvcfg1 = tr32(NVRAM_CFG1);
11210         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11211                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11212         } else {
11213                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11214                 tw32(NVRAM_CFG1, nvcfg1);
11215         }
11216
11217         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11218             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11219                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11220                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11221                         tp->nvram_jedecnum = JEDEC_ATMEL;
11222                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11223                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11224                         break;
11225                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11226                         tp->nvram_jedecnum = JEDEC_ATMEL;
11227                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11228                         break;
11229                 case FLASH_VENDOR_ATMEL_EEPROM:
11230                         tp->nvram_jedecnum = JEDEC_ATMEL;
11231                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11232                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11233                         break;
11234                 case FLASH_VENDOR_ST:
11235                         tp->nvram_jedecnum = JEDEC_ST;
11236                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11237                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11238                         break;
11239                 case FLASH_VENDOR_SAIFUN:
11240                         tp->nvram_jedecnum = JEDEC_SAIFUN;
11241                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11242                         break;
11243                 case FLASH_VENDOR_SST_SMALL:
11244                 case FLASH_VENDOR_SST_LARGE:
11245                         tp->nvram_jedecnum = JEDEC_SST;
11246                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11247                         break;
11248                 }
11249         } else {
11250                 tp->nvram_jedecnum = JEDEC_ATMEL;
11251                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11252                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11253         }
11254 }
11255
11256 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11257 {
11258         switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11259         case FLASH_5752PAGE_SIZE_256:
11260                 tp->nvram_pagesize = 256;
11261                 break;
11262         case FLASH_5752PAGE_SIZE_512:
11263                 tp->nvram_pagesize = 512;
11264                 break;
11265         case FLASH_5752PAGE_SIZE_1K:
11266                 tp->nvram_pagesize = 1024;
11267                 break;
11268         case FLASH_5752PAGE_SIZE_2K:
11269                 tp->nvram_pagesize = 2048;
11270                 break;
11271         case FLASH_5752PAGE_SIZE_4K:
11272                 tp->nvram_pagesize = 4096;
11273                 break;
11274         case FLASH_5752PAGE_SIZE_264:
11275                 tp->nvram_pagesize = 264;
11276                 break;
11277         case FLASH_5752PAGE_SIZE_528:
11278                 tp->nvram_pagesize = 528;
11279                 break;
11280         }
11281 }
11282
11283 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11284 {
11285         u32 nvcfg1;
11286
11287         nvcfg1 = tr32(NVRAM_CFG1);
11288
11289         /* NVRAM protection for TPM */
11290         if (nvcfg1 & (1 << 27))
11291                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11292
11293         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11294         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11295         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11296                 tp->nvram_jedecnum = JEDEC_ATMEL;
11297                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11298                 break;
11299         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11300                 tp->nvram_jedecnum = JEDEC_ATMEL;
11301                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11302                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11303                 break;
11304         case FLASH_5752VENDOR_ST_M45PE10:
11305         case FLASH_5752VENDOR_ST_M45PE20:
11306         case FLASH_5752VENDOR_ST_M45PE40:
11307                 tp->nvram_jedecnum = JEDEC_ST;
11308                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11309                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11310                 break;
11311         }
11312
11313         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11314                 tg3_nvram_get_pagesize(tp, nvcfg1);
11315         } else {
11316                 /* For eeprom, set pagesize to maximum eeprom size */
11317                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11318
11319                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11320                 tw32(NVRAM_CFG1, nvcfg1);
11321         }
11322 }
11323
11324 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11325 {
11326         u32 nvcfg1, protect = 0;
11327
11328         nvcfg1 = tr32(NVRAM_CFG1);
11329
11330         /* NVRAM protection for TPM */
11331         if (nvcfg1 & (1 << 27)) {
11332                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11333                 protect = 1;
11334         }
11335
11336         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11337         switch (nvcfg1) {
11338         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11339         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11340         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11341         case FLASH_5755VENDOR_ATMEL_FLASH_5:
11342                 tp->nvram_jedecnum = JEDEC_ATMEL;
11343                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11344                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11345                 tp->nvram_pagesize = 264;
11346                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11347                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11348                         tp->nvram_size = (protect ? 0x3e200 :
11349                                           TG3_NVRAM_SIZE_512KB);
11350                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11351                         tp->nvram_size = (protect ? 0x1f200 :
11352                                           TG3_NVRAM_SIZE_256KB);
11353                 else
11354                         tp->nvram_size = (protect ? 0x1f200 :
11355                                           TG3_NVRAM_SIZE_128KB);
11356                 break;
11357         case FLASH_5752VENDOR_ST_M45PE10:
11358         case FLASH_5752VENDOR_ST_M45PE20:
11359         case FLASH_5752VENDOR_ST_M45PE40:
11360                 tp->nvram_jedecnum = JEDEC_ST;
11361                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11362                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11363                 tp->nvram_pagesize = 256;
11364                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11365                         tp->nvram_size = (protect ?
11366                                           TG3_NVRAM_SIZE_64KB :
11367                                           TG3_NVRAM_SIZE_128KB);
11368                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11369                         tp->nvram_size = (protect ?
11370                                           TG3_NVRAM_SIZE_64KB :
11371                                           TG3_NVRAM_SIZE_256KB);
11372                 else
11373                         tp->nvram_size = (protect ?
11374                                           TG3_NVRAM_SIZE_128KB :
11375                                           TG3_NVRAM_SIZE_512KB);
11376                 break;
11377         }
11378 }
11379
11380 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11381 {
11382         u32 nvcfg1;
11383
11384         nvcfg1 = tr32(NVRAM_CFG1);
11385
11386         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11387         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11388         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11389         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11390         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11391                 tp->nvram_jedecnum = JEDEC_ATMEL;
11392                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11393                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11394
11395                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11396                 tw32(NVRAM_CFG1, nvcfg1);
11397                 break;
11398         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11399         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11400         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11401         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11402                 tp->nvram_jedecnum = JEDEC_ATMEL;
11403                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11404                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11405                 tp->nvram_pagesize = 264;
11406                 break;
11407         case FLASH_5752VENDOR_ST_M45PE10:
11408         case FLASH_5752VENDOR_ST_M45PE20:
11409         case FLASH_5752VENDOR_ST_M45PE40:
11410                 tp->nvram_jedecnum = JEDEC_ST;
11411                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11412                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11413                 tp->nvram_pagesize = 256;
11414                 break;
11415         }
11416 }
11417
11418 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11419 {
11420         u32 nvcfg1, protect = 0;
11421
11422         nvcfg1 = tr32(NVRAM_CFG1);
11423
11424         /* NVRAM protection for TPM */
11425         if (nvcfg1 & (1 << 27)) {
11426                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11427                 protect = 1;
11428         }
11429
11430         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11431         switch (nvcfg1) {
11432         case FLASH_5761VENDOR_ATMEL_ADB021D:
11433         case FLASH_5761VENDOR_ATMEL_ADB041D:
11434         case FLASH_5761VENDOR_ATMEL_ADB081D:
11435         case FLASH_5761VENDOR_ATMEL_ADB161D:
11436         case FLASH_5761VENDOR_ATMEL_MDB021D:
11437         case FLASH_5761VENDOR_ATMEL_MDB041D:
11438         case FLASH_5761VENDOR_ATMEL_MDB081D:
11439         case FLASH_5761VENDOR_ATMEL_MDB161D:
11440                 tp->nvram_jedecnum = JEDEC_ATMEL;
11441                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11442                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11443                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11444                 tp->nvram_pagesize = 256;
11445                 break;
11446         case FLASH_5761VENDOR_ST_A_M45PE20:
11447         case FLASH_5761VENDOR_ST_A_M45PE40:
11448         case FLASH_5761VENDOR_ST_A_M45PE80:
11449         case FLASH_5761VENDOR_ST_A_M45PE16:
11450         case FLASH_5761VENDOR_ST_M_M45PE20:
11451         case FLASH_5761VENDOR_ST_M_M45PE40:
11452         case FLASH_5761VENDOR_ST_M_M45PE80:
11453         case FLASH_5761VENDOR_ST_M_M45PE16:
11454                 tp->nvram_jedecnum = JEDEC_ST;
11455                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11456                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11457                 tp->nvram_pagesize = 256;
11458                 break;
11459         }
11460
11461         if (protect) {
11462                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11463         } else {
11464                 switch (nvcfg1) {
11465                 case FLASH_5761VENDOR_ATMEL_ADB161D:
11466                 case FLASH_5761VENDOR_ATMEL_MDB161D:
11467                 case FLASH_5761VENDOR_ST_A_M45PE16:
11468                 case FLASH_5761VENDOR_ST_M_M45PE16:
11469                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11470                         break;
11471                 case FLASH_5761VENDOR_ATMEL_ADB081D:
11472                 case FLASH_5761VENDOR_ATMEL_MDB081D:
11473                 case FLASH_5761VENDOR_ST_A_M45PE80:
11474                 case FLASH_5761VENDOR_ST_M_M45PE80:
11475                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11476                         break;
11477                 case FLASH_5761VENDOR_ATMEL_ADB041D:
11478                 case FLASH_5761VENDOR_ATMEL_MDB041D:
11479                 case FLASH_5761VENDOR_ST_A_M45PE40:
11480                 case FLASH_5761VENDOR_ST_M_M45PE40:
11481                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11482                         break;
11483                 case FLASH_5761VENDOR_ATMEL_ADB021D:
11484                 case FLASH_5761VENDOR_ATMEL_MDB021D:
11485                 case FLASH_5761VENDOR_ST_A_M45PE20:
11486                 case FLASH_5761VENDOR_ST_M_M45PE20:
11487                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11488                         break;
11489                 }
11490         }
11491 }
11492
11493 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11494 {
11495         tp->nvram_jedecnum = JEDEC_ATMEL;
11496         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11497         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11498 }
11499
11500 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11501 {
11502         u32 nvcfg1;
11503
11504         nvcfg1 = tr32(NVRAM_CFG1);
11505
11506         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11507         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11508         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11509                 tp->nvram_jedecnum = JEDEC_ATMEL;
11510                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11511                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11512
11513                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11514                 tw32(NVRAM_CFG1, nvcfg1);
11515                 return;
11516         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11517         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11518         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11519         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11520         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11521         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11522         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11523                 tp->nvram_jedecnum = JEDEC_ATMEL;
11524                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11525                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11526
11527                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11528                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11529                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11530                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11531                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11532                         break;
11533                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11534                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11535                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11536                         break;
11537                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11538                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11539                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11540                         break;
11541                 }
11542                 break;
11543         case FLASH_5752VENDOR_ST_M45PE10:
11544         case FLASH_5752VENDOR_ST_M45PE20:
11545         case FLASH_5752VENDOR_ST_M45PE40:
11546                 tp->nvram_jedecnum = JEDEC_ST;
11547                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11548                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11549
11550                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11551                 case FLASH_5752VENDOR_ST_M45PE10:
11552                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11553                         break;
11554                 case FLASH_5752VENDOR_ST_M45PE20:
11555                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11556                         break;
11557                 case FLASH_5752VENDOR_ST_M45PE40:
11558                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11559                         break;
11560                 }
11561                 break;
11562         default:
11563                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11564                 return;
11565         }
11566
11567         tg3_nvram_get_pagesize(tp, nvcfg1);
11568         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11569                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11570 }
11571
11572
11573 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11574 {
11575         u32 nvcfg1;
11576
11577         nvcfg1 = tr32(NVRAM_CFG1);
11578
11579         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11580         case FLASH_5717VENDOR_ATMEL_EEPROM:
11581         case FLASH_5717VENDOR_MICRO_EEPROM:
11582                 tp->nvram_jedecnum = JEDEC_ATMEL;
11583                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11584                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11585
11586                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11587                 tw32(NVRAM_CFG1, nvcfg1);
11588                 return;
11589         case FLASH_5717VENDOR_ATMEL_MDB011D:
11590         case FLASH_5717VENDOR_ATMEL_ADB011B:
11591         case FLASH_5717VENDOR_ATMEL_ADB011D:
11592         case FLASH_5717VENDOR_ATMEL_MDB021D:
11593         case FLASH_5717VENDOR_ATMEL_ADB021B:
11594         case FLASH_5717VENDOR_ATMEL_ADB021D:
11595         case FLASH_5717VENDOR_ATMEL_45USPT:
11596                 tp->nvram_jedecnum = JEDEC_ATMEL;
11597                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11598                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11599
11600                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11601                 case FLASH_5717VENDOR_ATMEL_MDB021D:
11602                 case FLASH_5717VENDOR_ATMEL_ADB021B:
11603                 case FLASH_5717VENDOR_ATMEL_ADB021D:
11604                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11605                         break;
11606                 default:
11607                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11608                         break;
11609                 }
11610                 break;
11611         case FLASH_5717VENDOR_ST_M_M25PE10:
11612         case FLASH_5717VENDOR_ST_A_M25PE10:
11613         case FLASH_5717VENDOR_ST_M_M45PE10:
11614         case FLASH_5717VENDOR_ST_A_M45PE10:
11615         case FLASH_5717VENDOR_ST_M_M25PE20:
11616         case FLASH_5717VENDOR_ST_A_M25PE20:
11617         case FLASH_5717VENDOR_ST_M_M45PE20:
11618         case FLASH_5717VENDOR_ST_A_M45PE20:
11619         case FLASH_5717VENDOR_ST_25USPT:
11620         case FLASH_5717VENDOR_ST_45USPT:
11621                 tp->nvram_jedecnum = JEDEC_ST;
11622                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11623                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11624
11625                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11626                 case FLASH_5717VENDOR_ST_M_M25PE20:
11627                 case FLASH_5717VENDOR_ST_A_M25PE20:
11628                 case FLASH_5717VENDOR_ST_M_M45PE20:
11629                 case FLASH_5717VENDOR_ST_A_M45PE20:
11630                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11631                         break;
11632                 default:
11633                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11634                         break;
11635                 }
11636                 break;
11637         default:
11638                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11639                 return;
11640         }
11641
11642         tg3_nvram_get_pagesize(tp, nvcfg1);
11643         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11644                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11645 }
11646
11647 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11648 static void __devinit tg3_nvram_init(struct tg3 *tp)
11649 {
11650         tw32_f(GRC_EEPROM_ADDR,
11651              (EEPROM_ADDR_FSM_RESET |
11652               (EEPROM_DEFAULT_CLOCK_PERIOD <<
11653                EEPROM_ADDR_CLKPERD_SHIFT)));
11654
11655         msleep(1);
11656
11657         /* Enable seeprom accesses. */
11658         tw32_f(GRC_LOCAL_CTRL,
11659              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11660         udelay(100);
11661
11662         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11663             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11664                 tp->tg3_flags |= TG3_FLAG_NVRAM;
11665
11666                 if (tg3_nvram_lock(tp)) {
11667                         netdev_warn(tp->dev,
11668                                     "Cannot get nvram lock, %s failed\n",
11669                                     __func__);
11670                         return;
11671                 }
11672                 tg3_enable_nvram_access(tp);
11673
11674                 tp->nvram_size = 0;
11675
11676                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11677                         tg3_get_5752_nvram_info(tp);
11678                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11679                         tg3_get_5755_nvram_info(tp);
11680                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11681                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11682                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11683                         tg3_get_5787_nvram_info(tp);
11684                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11685                         tg3_get_5761_nvram_info(tp);
11686                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11687                         tg3_get_5906_nvram_info(tp);
11688                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11689                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11690                         tg3_get_57780_nvram_info(tp);
11691                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
11692                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
11693                         tg3_get_5717_nvram_info(tp);
11694                 else
11695                         tg3_get_nvram_info(tp);
11696
11697                 if (tp->nvram_size == 0)
11698                         tg3_get_nvram_size(tp);
11699
11700                 tg3_disable_nvram_access(tp);
11701                 tg3_nvram_unlock(tp);
11702
11703         } else {
11704                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11705
11706                 tg3_get_eeprom_size(tp);
11707         }
11708 }
11709
11710 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11711                                     u32 offset, u32 len, u8 *buf)
11712 {
11713         int i, j, rc = 0;
11714         u32 val;
11715
11716         for (i = 0; i < len; i += 4) {
11717                 u32 addr;
11718                 __be32 data;
11719
11720                 addr = offset + i;
11721
11722                 memcpy(&data, buf + i, 4);
11723
11724                 /*
11725                  * The SEEPROM interface expects the data to always be opposite
11726                  * the native endian format.  We accomplish this by reversing
11727                  * all the operations that would have been performed on the
11728                  * data from a call to tg3_nvram_read_be32().
11729                  */
11730                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11731
11732                 val = tr32(GRC_EEPROM_ADDR);
11733                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11734
11735                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11736                         EEPROM_ADDR_READ);
11737                 tw32(GRC_EEPROM_ADDR, val |
11738                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
11739                         (addr & EEPROM_ADDR_ADDR_MASK) |
11740                         EEPROM_ADDR_START |
11741                         EEPROM_ADDR_WRITE);
11742
11743                 for (j = 0; j < 1000; j++) {
11744                         val = tr32(GRC_EEPROM_ADDR);
11745
11746                         if (val & EEPROM_ADDR_COMPLETE)
11747                                 break;
11748                         msleep(1);
11749                 }
11750                 if (!(val & EEPROM_ADDR_COMPLETE)) {
11751                         rc = -EBUSY;
11752                         break;
11753                 }
11754         }
11755
11756         return rc;
11757 }
11758
11759 /* offset and length are dword aligned */
11760 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11761                 u8 *buf)
11762 {
11763         int ret = 0;
11764         u32 pagesize = tp->nvram_pagesize;
11765         u32 pagemask = pagesize - 1;
11766         u32 nvram_cmd;
11767         u8 *tmp;
11768
11769         tmp = kmalloc(pagesize, GFP_KERNEL);
11770         if (tmp == NULL)
11771                 return -ENOMEM;
11772
11773         while (len) {
11774                 int j;
11775                 u32 phy_addr, page_off, size;
11776
11777                 phy_addr = offset & ~pagemask;
11778
11779                 for (j = 0; j < pagesize; j += 4) {
11780                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
11781                                                   (__be32 *) (tmp + j));
11782                         if (ret)
11783                                 break;
11784                 }
11785                 if (ret)
11786                         break;
11787
11788                 page_off = offset & pagemask;
11789                 size = pagesize;
11790                 if (len < size)
11791                         size = len;
11792
11793                 len -= size;
11794
11795                 memcpy(tmp + page_off, buf, size);
11796
11797                 offset = offset + (pagesize - page_off);
11798
11799                 tg3_enable_nvram_access(tp);
11800
11801                 /*
11802                  * Before we can erase the flash page, we need
11803                  * to issue a special "write enable" command.
11804                  */
11805                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11806
11807                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11808                         break;
11809
11810                 /* Erase the target page */
11811                 tw32(NVRAM_ADDR, phy_addr);
11812
11813                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11814                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11815
11816                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11817                         break;
11818
11819                 /* Issue another write enable to start the write. */
11820                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11821
11822                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11823                         break;
11824
11825                 for (j = 0; j < pagesize; j += 4) {
11826                         __be32 data;
11827
11828                         data = *((__be32 *) (tmp + j));
11829
11830                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
11831
11832                         tw32(NVRAM_ADDR, phy_addr + j);
11833
11834                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11835                                 NVRAM_CMD_WR;
11836
11837                         if (j == 0)
11838                                 nvram_cmd |= NVRAM_CMD_FIRST;
11839                         else if (j == (pagesize - 4))
11840                                 nvram_cmd |= NVRAM_CMD_LAST;
11841
11842                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11843                                 break;
11844                 }
11845                 if (ret)
11846                         break;
11847         }
11848
11849         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11850         tg3_nvram_exec_cmd(tp, nvram_cmd);
11851
11852         kfree(tmp);
11853
11854         return ret;
11855 }
11856
11857 /* offset and length are dword aligned */
11858 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11859                 u8 *buf)
11860 {
11861         int i, ret = 0;
11862
11863         for (i = 0; i < len; i += 4, offset += 4) {
11864                 u32 page_off, phy_addr, nvram_cmd;
11865                 __be32 data;
11866
11867                 memcpy(&data, buf + i, 4);
11868                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11869
11870                 page_off = offset % tp->nvram_pagesize;
11871
11872                 phy_addr = tg3_nvram_phys_addr(tp, offset);
11873
11874                 tw32(NVRAM_ADDR, phy_addr);
11875
11876                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11877
11878                 if (page_off == 0 || i == 0)
11879                         nvram_cmd |= NVRAM_CMD_FIRST;
11880                 if (page_off == (tp->nvram_pagesize - 4))
11881                         nvram_cmd |= NVRAM_CMD_LAST;
11882
11883                 if (i == (len - 4))
11884                         nvram_cmd |= NVRAM_CMD_LAST;
11885
11886                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11887                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11888                     (tp->nvram_jedecnum == JEDEC_ST) &&
11889                     (nvram_cmd & NVRAM_CMD_FIRST)) {
11890
11891                         if ((ret = tg3_nvram_exec_cmd(tp,
11892                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11893                                 NVRAM_CMD_DONE)))
11894
11895                                 break;
11896                 }
11897                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11898                         /* We always do complete word writes to eeprom. */
11899                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11900                 }
11901
11902                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11903                         break;
11904         }
11905         return ret;
11906 }
11907
11908 /* offset and length are dword aligned */
11909 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11910 {
11911         int ret;
11912
11913         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11914                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11915                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
11916                 udelay(40);
11917         }
11918
11919         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11920                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11921         } else {
11922                 u32 grc_mode;
11923
11924                 ret = tg3_nvram_lock(tp);
11925                 if (ret)
11926                         return ret;
11927
11928                 tg3_enable_nvram_access(tp);
11929                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11930                     !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
11931                         tw32(NVRAM_WRITE1, 0x406);
11932
11933                 grc_mode = tr32(GRC_MODE);
11934                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11935
11936                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11937                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11938
11939                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
11940                                 buf);
11941                 } else {
11942                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11943                                 buf);
11944                 }
11945
11946                 grc_mode = tr32(GRC_MODE);
11947                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11948
11949                 tg3_disable_nvram_access(tp);
11950                 tg3_nvram_unlock(tp);
11951         }
11952
11953         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11954                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11955                 udelay(40);
11956         }
11957
11958         return ret;
11959 }
11960
11961 struct subsys_tbl_ent {
11962         u16 subsys_vendor, subsys_devid;
11963         u32 phy_id;
11964 };
11965
11966 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
11967         /* Broadcom boards. */
11968         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11969           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
11970         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11971           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
11972         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11973           TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
11974         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11975           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
11976         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11977           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
11978         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11979           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
11980         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11981           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
11982         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11983           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
11984         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11985           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
11986         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11987           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
11988         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11989           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
11990
11991         /* 3com boards. */
11992         { TG3PCI_SUBVENDOR_ID_3COM,
11993           TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
11994         { TG3PCI_SUBVENDOR_ID_3COM,
11995           TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
11996         { TG3PCI_SUBVENDOR_ID_3COM,
11997           TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
11998         { TG3PCI_SUBVENDOR_ID_3COM,
11999           TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
12000         { TG3PCI_SUBVENDOR_ID_3COM,
12001           TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
12002
12003         /* DELL boards. */
12004         { TG3PCI_SUBVENDOR_ID_DELL,
12005           TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
12006         { TG3PCI_SUBVENDOR_ID_DELL,
12007           TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
12008         { TG3PCI_SUBVENDOR_ID_DELL,
12009           TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
12010         { TG3PCI_SUBVENDOR_ID_DELL,
12011           TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
12012
12013         /* Compaq boards. */
12014         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12015           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
12016         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12017           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
12018         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12019           TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
12020         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12021           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
12022         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12023           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
12024
12025         /* IBM boards. */
12026         { TG3PCI_SUBVENDOR_ID_IBM,
12027           TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
12028 };
12029
12030 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
12031 {
12032         int i;
12033
12034         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12035                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12036                      tp->pdev->subsystem_vendor) &&
12037                     (subsys_id_to_phy_id[i].subsys_devid ==
12038                      tp->pdev->subsystem_device))
12039                         return &subsys_id_to_phy_id[i];
12040         }
12041         return NULL;
12042 }
12043
12044 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12045 {
12046         u32 val;
12047         u16 pmcsr;
12048
12049         /* On some early chips the SRAM cannot be accessed in D3hot state,
12050          * so need make sure we're in D0.
12051          */
12052         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12053         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12054         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12055         msleep(1);
12056
12057         /* Make sure register accesses (indirect or otherwise)
12058          * will function correctly.
12059          */
12060         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12061                                tp->misc_host_ctrl);
12062
12063         /* The memory arbiter has to be enabled in order for SRAM accesses
12064          * to succeed.  Normally on powerup the tg3 chip firmware will make
12065          * sure it is enabled, but other entities such as system netboot
12066          * code might disable it.
12067          */
12068         val = tr32(MEMARB_MODE);
12069         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12070
12071         tp->phy_id = TG3_PHY_ID_INVALID;
12072         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12073
12074         /* Assume an onboard device and WOL capable by default.  */
12075         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12076
12077         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12078                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12079                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12080                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12081                 }
12082                 val = tr32(VCPU_CFGSHDW);
12083                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12084                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12085                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12086                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
12087                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12088                 goto done;
12089         }
12090
12091         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12092         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12093                 u32 nic_cfg, led_cfg;
12094                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12095                 int eeprom_phy_serdes = 0;
12096
12097                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12098                 tp->nic_sram_data_cfg = nic_cfg;
12099
12100                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12101                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12102                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12103                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12104                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12105                     (ver > 0) && (ver < 0x100))
12106                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12107
12108                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12109                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12110
12111                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12112                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12113                         eeprom_phy_serdes = 1;
12114
12115                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12116                 if (nic_phy_id != 0) {
12117                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12118                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12119
12120                         eeprom_phy_id  = (id1 >> 16) << 10;
12121                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
12122                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
12123                 } else
12124                         eeprom_phy_id = 0;
12125
12126                 tp->phy_id = eeprom_phy_id;
12127                 if (eeprom_phy_serdes) {
12128                         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12129                                 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12130                         else
12131                                 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
12132                 }
12133
12134                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12135                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12136                                     SHASTA_EXT_LED_MODE_MASK);
12137                 else
12138                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12139
12140                 switch (led_cfg) {
12141                 default:
12142                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12143                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12144                         break;
12145
12146                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12147                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12148                         break;
12149
12150                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12151                         tp->led_ctrl = LED_CTRL_MODE_MAC;
12152
12153                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12154                          * read on some older 5700/5701 bootcode.
12155                          */
12156                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12157                             ASIC_REV_5700 ||
12158                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
12159                             ASIC_REV_5701)
12160                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12161
12162                         break;
12163
12164                 case SHASTA_EXT_LED_SHARED:
12165                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
12166                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12167                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12168                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12169                                                  LED_CTRL_MODE_PHY_2);
12170                         break;
12171
12172                 case SHASTA_EXT_LED_MAC:
12173                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12174                         break;
12175
12176                 case SHASTA_EXT_LED_COMBO:
12177                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
12178                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12179                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12180                                                  LED_CTRL_MODE_PHY_2);
12181                         break;
12182
12183                 }
12184
12185                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12186                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12187                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12188                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12189
12190                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12191                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12192
12193                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12194                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12195                         if ((tp->pdev->subsystem_vendor ==
12196                              PCI_VENDOR_ID_ARIMA) &&
12197                             (tp->pdev->subsystem_device == 0x205a ||
12198                              tp->pdev->subsystem_device == 0x2063))
12199                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12200                 } else {
12201                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12202                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12203                 }
12204
12205                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12206                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12207                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12208                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12209                 }
12210
12211                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12212                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12213                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12214
12215                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
12216                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12217                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12218
12219                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12220                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12221                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12222
12223                 if (cfg2 & (1 << 17))
12224                         tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
12225
12226                 /* serdes signal pre-emphasis in register 0x590 set by */
12227                 /* bootcode if bit 18 is set */
12228                 if (cfg2 & (1 << 18))
12229                         tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
12230
12231                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12232                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
12233                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12234                         tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
12235
12236                 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12237                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12238                     !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
12239                         u32 cfg3;
12240
12241                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12242                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12243                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12244                 }
12245
12246                 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12247                         tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
12248                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12249                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12250                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12251                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12252         }
12253 done:
12254         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12255         device_set_wakeup_enable(&tp->pdev->dev,
12256                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12257 }
12258
12259 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12260 {
12261         int i;
12262         u32 val;
12263
12264         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12265         tw32(OTP_CTRL, cmd);
12266
12267         /* Wait for up to 1 ms for command to execute. */
12268         for (i = 0; i < 100; i++) {
12269                 val = tr32(OTP_STATUS);
12270                 if (val & OTP_STATUS_CMD_DONE)
12271                         break;
12272                 udelay(10);
12273         }
12274
12275         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12276 }
12277
12278 /* Read the gphy configuration from the OTP region of the chip.  The gphy
12279  * configuration is a 32-bit value that straddles the alignment boundary.
12280  * We do two 32-bit reads and then shift and merge the results.
12281  */
12282 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12283 {
12284         u32 bhalf_otp, thalf_otp;
12285
12286         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12287
12288         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12289                 return 0;
12290
12291         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12292
12293         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12294                 return 0;
12295
12296         thalf_otp = tr32(OTP_READ_DATA);
12297
12298         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12299
12300         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12301                 return 0;
12302
12303         bhalf_otp = tr32(OTP_READ_DATA);
12304
12305         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12306 }
12307
12308 static int __devinit tg3_phy_probe(struct tg3 *tp)
12309 {
12310         u32 hw_phy_id_1, hw_phy_id_2;
12311         u32 hw_phy_id, hw_phy_id_masked;
12312         int err;
12313
12314         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12315                 return tg3_phy_init(tp);
12316
12317         /* Reading the PHY ID register can conflict with ASF
12318          * firmware access to the PHY hardware.
12319          */
12320         err = 0;
12321         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12322             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12323                 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
12324         } else {
12325                 /* Now read the physical PHY_ID from the chip and verify
12326                  * that it is sane.  If it doesn't look good, we fall back
12327                  * to either the hard-coded table based PHY_ID and failing
12328                  * that the value found in the eeprom area.
12329                  */
12330                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12331                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12332
12333                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
12334                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12335                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
12336
12337                 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
12338         }
12339
12340         if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
12341                 tp->phy_id = hw_phy_id;
12342                 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
12343                         tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12344                 else
12345                         tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
12346         } else {
12347                 if (tp->phy_id != TG3_PHY_ID_INVALID) {
12348                         /* Do nothing, phy ID already set up in
12349                          * tg3_get_eeprom_hw_cfg().
12350                          */
12351                 } else {
12352                         struct subsys_tbl_ent *p;
12353
12354                         /* No eeprom signature?  Try the hardcoded
12355                          * subsys device table.
12356                          */
12357                         p = tg3_lookup_by_subsys(tp);
12358                         if (!p)
12359                                 return -ENODEV;
12360
12361                         tp->phy_id = p->phy_id;
12362                         if (!tp->phy_id ||
12363                             tp->phy_id == TG3_PHY_ID_BCM8002)
12364                                 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12365                 }
12366         }
12367
12368         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
12369             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12370             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12371                 u32 bmsr, adv_reg, tg3_ctrl, mask;
12372
12373                 tg3_readphy(tp, MII_BMSR, &bmsr);
12374                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12375                     (bmsr & BMSR_LSTATUS))
12376                         goto skip_phy_reset;
12377
12378                 err = tg3_phy_reset(tp);
12379                 if (err)
12380                         return err;
12381
12382                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12383                            ADVERTISE_100HALF | ADVERTISE_100FULL |
12384                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12385                 tg3_ctrl = 0;
12386                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
12387                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12388                                     MII_TG3_CTRL_ADV_1000_FULL);
12389                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12390                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12391                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12392                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
12393                 }
12394
12395                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12396                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12397                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12398                 if (!tg3_copper_is_advertising_all(tp, mask)) {
12399                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12400
12401                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12402                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12403
12404                         tg3_writephy(tp, MII_BMCR,
12405                                      BMCR_ANENABLE | BMCR_ANRESTART);
12406                 }
12407                 tg3_phy_set_wirespeed(tp);
12408
12409                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12410                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12411                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12412         }
12413
12414 skip_phy_reset:
12415         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
12416                 err = tg3_init_5401phy_dsp(tp);
12417                 if (err)
12418                         return err;
12419
12420                 err = tg3_init_5401phy_dsp(tp);
12421         }
12422
12423         if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
12424                 tp->link_config.advertising =
12425                         (ADVERTISED_1000baseT_Half |
12426                          ADVERTISED_1000baseT_Full |
12427                          ADVERTISED_Autoneg |
12428                          ADVERTISED_FIBRE);
12429         if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
12430                 tp->link_config.advertising &=
12431                         ~(ADVERTISED_1000baseT_Half |
12432                           ADVERTISED_1000baseT_Full);
12433
12434         return err;
12435 }
12436
12437 static void __devinit tg3_read_vpd(struct tg3 *tp)
12438 {
12439         u8 *vpd_data;
12440         unsigned int block_end, rosize, len;
12441         int j, i = 0;
12442         u32 magic;
12443
12444         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12445             tg3_nvram_read(tp, 0x0, &magic))
12446                 goto out_no_vpd;
12447
12448         vpd_data = kmalloc(TG3_NVM_VPD_LEN, GFP_KERNEL);
12449         if (!vpd_data)
12450                 goto out_no_vpd;
12451
12452         if (magic == TG3_EEPROM_MAGIC) {
12453                 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12454                         u32 tmp;
12455
12456                         /* The data is in little-endian format in NVRAM.
12457                          * Use the big-endian read routines to preserve
12458                          * the byte order as it exists in NVRAM.
12459                          */
12460                         if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12461                                 goto out_not_found;
12462
12463                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12464                 }
12465         } else {
12466                 ssize_t cnt;
12467                 unsigned int pos = 0;
12468
12469                 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12470                         cnt = pci_read_vpd(tp->pdev, pos,
12471                                            TG3_NVM_VPD_LEN - pos,
12472                                            &vpd_data[pos]);
12473                         if (cnt == -ETIMEDOUT || -EINTR)
12474                                 cnt = 0;
12475                         else if (cnt < 0)
12476                                 goto out_not_found;
12477                 }
12478                 if (pos != TG3_NVM_VPD_LEN)
12479                         goto out_not_found;
12480         }
12481
12482         i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
12483                              PCI_VPD_LRDT_RO_DATA);
12484         if (i < 0)
12485                 goto out_not_found;
12486
12487         rosize = pci_vpd_lrdt_size(&vpd_data[i]);
12488         block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
12489         i += PCI_VPD_LRDT_TAG_SIZE;
12490
12491         if (block_end > TG3_NVM_VPD_LEN)
12492                 goto out_not_found;
12493
12494         j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12495                                       PCI_VPD_RO_KEYWORD_MFR_ID);
12496         if (j > 0) {
12497                 len = pci_vpd_info_field_size(&vpd_data[j]);
12498
12499                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12500                 if (j + len > block_end || len != 4 ||
12501                     memcmp(&vpd_data[j], "1028", 4))
12502                         goto partno;
12503
12504                 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12505                                               PCI_VPD_RO_KEYWORD_VENDOR0);
12506                 if (j < 0)
12507                         goto partno;
12508
12509                 len = pci_vpd_info_field_size(&vpd_data[j]);
12510
12511                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12512                 if (j + len > block_end)
12513                         goto partno;
12514
12515                 memcpy(tp->fw_ver, &vpd_data[j], len);
12516                 strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
12517         }
12518
12519 partno:
12520         i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12521                                       PCI_VPD_RO_KEYWORD_PARTNO);
12522         if (i < 0)
12523                 goto out_not_found;
12524
12525         len = pci_vpd_info_field_size(&vpd_data[i]);
12526
12527         i += PCI_VPD_INFO_FLD_HDR_SIZE;
12528         if (len > TG3_BPN_SIZE ||
12529             (len + i) > TG3_NVM_VPD_LEN)
12530                 goto out_not_found;
12531
12532         memcpy(tp->board_part_number, &vpd_data[i], len);
12533
12534 out_not_found:
12535         kfree(vpd_data);
12536         if (!tp->board_part_number[0])
12537                 return;
12538
12539 out_no_vpd:
12540         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12541                 strcpy(tp->board_part_number, "BCM95906");
12542         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12543                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12544                 strcpy(tp->board_part_number, "BCM57780");
12545         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12546                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12547                 strcpy(tp->board_part_number, "BCM57760");
12548         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12549                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12550                 strcpy(tp->board_part_number, "BCM57790");
12551         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12552                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12553                 strcpy(tp->board_part_number, "BCM57788");
12554         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12555                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
12556                 strcpy(tp->board_part_number, "BCM57761");
12557         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12558                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
12559                 strcpy(tp->board_part_number, "BCM57765");
12560         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12561                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
12562                 strcpy(tp->board_part_number, "BCM57781");
12563         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12564                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
12565                 strcpy(tp->board_part_number, "BCM57785");
12566         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12567                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
12568                 strcpy(tp->board_part_number, "BCM57791");
12569         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12570                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12571                 strcpy(tp->board_part_number, "BCM57795");
12572         else
12573                 strcpy(tp->board_part_number, "none");
12574 }
12575
12576 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12577 {
12578         u32 val;
12579
12580         if (tg3_nvram_read(tp, offset, &val) ||
12581             (val & 0xfc000000) != 0x0c000000 ||
12582             tg3_nvram_read(tp, offset + 4, &val) ||
12583             val != 0)
12584                 return 0;
12585
12586         return 1;
12587 }
12588
12589 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12590 {
12591         u32 val, offset, start, ver_offset;
12592         int i, dst_off;
12593         bool newver = false;
12594
12595         if (tg3_nvram_read(tp, 0xc, &offset) ||
12596             tg3_nvram_read(tp, 0x4, &start))
12597                 return;
12598
12599         offset = tg3_nvram_logical_addr(tp, offset);
12600
12601         if (tg3_nvram_read(tp, offset, &val))
12602                 return;
12603
12604         if ((val & 0xfc000000) == 0x0c000000) {
12605                 if (tg3_nvram_read(tp, offset + 4, &val))
12606                         return;
12607
12608                 if (val == 0)
12609                         newver = true;
12610         }
12611
12612         dst_off = strlen(tp->fw_ver);
12613
12614         if (newver) {
12615                 if (TG3_VER_SIZE - dst_off < 16 ||
12616                     tg3_nvram_read(tp, offset + 8, &ver_offset))
12617                         return;
12618
12619                 offset = offset + ver_offset - start;
12620                 for (i = 0; i < 16; i += 4) {
12621                         __be32 v;
12622                         if (tg3_nvram_read_be32(tp, offset + i, &v))
12623                                 return;
12624
12625                         memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
12626                 }
12627         } else {
12628                 u32 major, minor;
12629
12630                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12631                         return;
12632
12633                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12634                         TG3_NVM_BCVER_MAJSFT;
12635                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12636                 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
12637                          "v%d.%02d", major, minor);
12638         }
12639 }
12640
12641 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12642 {
12643         u32 val, major, minor;
12644
12645         /* Use native endian representation */
12646         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12647                 return;
12648
12649         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12650                 TG3_NVM_HWSB_CFG1_MAJSFT;
12651         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12652                 TG3_NVM_HWSB_CFG1_MINSFT;
12653
12654         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12655 }
12656
12657 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12658 {
12659         u32 offset, major, minor, build;
12660
12661         strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
12662
12663         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12664                 return;
12665
12666         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12667         case TG3_EEPROM_SB_REVISION_0:
12668                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12669                 break;
12670         case TG3_EEPROM_SB_REVISION_2:
12671                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12672                 break;
12673         case TG3_EEPROM_SB_REVISION_3:
12674                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12675                 break;
12676         case TG3_EEPROM_SB_REVISION_4:
12677                 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
12678                 break;
12679         case TG3_EEPROM_SB_REVISION_5:
12680                 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
12681                 break;
12682         default:
12683                 return;
12684         }
12685
12686         if (tg3_nvram_read(tp, offset, &val))
12687                 return;
12688
12689         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12690                 TG3_EEPROM_SB_EDH_BLD_SHFT;
12691         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12692                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12693         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
12694
12695         if (minor > 99 || build > 26)
12696                 return;
12697
12698         offset = strlen(tp->fw_ver);
12699         snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
12700                  " v%d.%02d", major, minor);
12701
12702         if (build > 0) {
12703                 offset = strlen(tp->fw_ver);
12704                 if (offset < TG3_VER_SIZE - 1)
12705                         tp->fw_ver[offset] = 'a' + build - 1;
12706         }
12707 }
12708
12709 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12710 {
12711         u32 val, offset, start;
12712         int i, vlen;
12713
12714         for (offset = TG3_NVM_DIR_START;
12715              offset < TG3_NVM_DIR_END;
12716              offset += TG3_NVM_DIRENT_SIZE) {
12717                 if (tg3_nvram_read(tp, offset, &val))
12718                         return;
12719
12720                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12721                         break;
12722         }
12723
12724         if (offset == TG3_NVM_DIR_END)
12725                 return;
12726
12727         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12728                 start = 0x08000000;
12729         else if (tg3_nvram_read(tp, offset - 4, &start))
12730                 return;
12731
12732         if (tg3_nvram_read(tp, offset + 4, &offset) ||
12733             !tg3_fw_img_is_valid(tp, offset) ||
12734             tg3_nvram_read(tp, offset + 8, &val))
12735                 return;
12736
12737         offset += val - start;
12738
12739         vlen = strlen(tp->fw_ver);
12740
12741         tp->fw_ver[vlen++] = ',';
12742         tp->fw_ver[vlen++] = ' ';
12743
12744         for (i = 0; i < 4; i++) {
12745                 __be32 v;
12746                 if (tg3_nvram_read_be32(tp, offset, &v))
12747                         return;
12748
12749                 offset += sizeof(v);
12750
12751                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12752                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12753                         break;
12754                 }
12755
12756                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12757                 vlen += sizeof(v);
12758         }
12759 }
12760
12761 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12762 {
12763         int vlen;
12764         u32 apedata;
12765         char *fwtype;
12766
12767         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12768             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
12769                 return;
12770
12771         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12772         if (apedata != APE_SEG_SIG_MAGIC)
12773                 return;
12774
12775         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12776         if (!(apedata & APE_FW_STATUS_READY))
12777                 return;
12778
12779         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12780
12781         if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) {
12782                 tp->tg3_flags3 |= TG3_FLG3_APE_HAS_NCSI;
12783                 fwtype = "NCSI";
12784         } else {
12785                 fwtype = "DASH";
12786         }
12787
12788         vlen = strlen(tp->fw_ver);
12789
12790         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
12791                  fwtype,
12792                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12793                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12794                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12795                  (apedata & APE_FW_VERSION_BLDMSK));
12796 }
12797
12798 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12799 {
12800         u32 val;
12801         bool vpd_vers = false;
12802
12803         if (tp->fw_ver[0] != 0)
12804                 vpd_vers = true;
12805
12806         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12807                 strcat(tp->fw_ver, "sb");
12808                 return;
12809         }
12810
12811         if (tg3_nvram_read(tp, 0, &val))
12812                 return;
12813
12814         if (val == TG3_EEPROM_MAGIC)
12815                 tg3_read_bc_ver(tp);
12816         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12817                 tg3_read_sb_ver(tp, val);
12818         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12819                 tg3_read_hwsb_ver(tp);
12820         else
12821                 return;
12822
12823         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12824              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
12825                 goto done;
12826
12827         tg3_read_mgmtfw_ver(tp);
12828
12829 done:
12830         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12831 }
12832
12833 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12834
12835 static void inline vlan_features_add(struct net_device *dev, unsigned long flags)
12836 {
12837 #if TG3_VLAN_TAG_USED
12838         dev->vlan_features |= flags;
12839 #endif
12840 }
12841
12842 static int __devinit tg3_get_invariants(struct tg3 *tp)
12843 {
12844         static struct pci_device_id write_reorder_chipsets[] = {
12845                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12846                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12847                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12848                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12849                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12850                              PCI_DEVICE_ID_VIA_8385_0) },
12851                 { },
12852         };
12853         u32 misc_ctrl_reg;
12854         u32 pci_state_reg, grc_misc_cfg;
12855         u32 val;
12856         u16 pci_cmd;
12857         int err;
12858
12859         /* Force memory write invalidate off.  If we leave it on,
12860          * then on 5700_BX chips we have to enable a workaround.
12861          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12862          * to match the cacheline size.  The Broadcom driver have this
12863          * workaround but turns MWI off all the times so never uses
12864          * it.  This seems to suggest that the workaround is insufficient.
12865          */
12866         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12867         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12868         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12869
12870         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12871          * has the register indirect write enable bit set before
12872          * we try to access any of the MMIO registers.  It is also
12873          * critical that the PCI-X hw workaround situation is decided
12874          * before that as well.
12875          */
12876         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12877                               &misc_ctrl_reg);
12878
12879         tp->pci_chip_rev_id = (misc_ctrl_reg >>
12880                                MISC_HOST_CTRL_CHIPREV_SHIFT);
12881         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12882                 u32 prod_id_asic_rev;
12883
12884                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12885                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12886                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724 ||
12887                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719)
12888                         pci_read_config_dword(tp->pdev,
12889                                               TG3PCI_GEN2_PRODID_ASICREV,
12890                                               &prod_id_asic_rev);
12891                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
12892                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
12893                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
12894                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
12895                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
12896                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12897                         pci_read_config_dword(tp->pdev,
12898                                               TG3PCI_GEN15_PRODID_ASICREV,
12899                                               &prod_id_asic_rev);
12900                 else
12901                         pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12902                                               &prod_id_asic_rev);
12903
12904                 tp->pci_chip_rev_id = prod_id_asic_rev;
12905         }
12906
12907         /* Wrong chip ID in 5752 A0. This code can be removed later
12908          * as A0 is not in production.
12909          */
12910         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12911                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12912
12913         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12914          * we need to disable memory and use config. cycles
12915          * only to access all registers. The 5702/03 chips
12916          * can mistakenly decode the special cycles from the
12917          * ICH chipsets as memory write cycles, causing corruption
12918          * of register and memory space. Only certain ICH bridges
12919          * will drive special cycles with non-zero data during the
12920          * address phase which can fall within the 5703's address
12921          * range. This is not an ICH bug as the PCI spec allows
12922          * non-zero address during special cycles. However, only
12923          * these ICH bridges are known to drive non-zero addresses
12924          * during special cycles.
12925          *
12926          * Since special cycles do not cross PCI bridges, we only
12927          * enable this workaround if the 5703 is on the secondary
12928          * bus of these ICH bridges.
12929          */
12930         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12931             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12932                 static struct tg3_dev_id {
12933                         u32     vendor;
12934                         u32     device;
12935                         u32     rev;
12936                 } ich_chipsets[] = {
12937                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12938                           PCI_ANY_ID },
12939                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12940                           PCI_ANY_ID },
12941                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12942                           0xa },
12943                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12944                           PCI_ANY_ID },
12945                         { },
12946                 };
12947                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12948                 struct pci_dev *bridge = NULL;
12949
12950                 while (pci_id->vendor != 0) {
12951                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
12952                                                 bridge);
12953                         if (!bridge) {
12954                                 pci_id++;
12955                                 continue;
12956                         }
12957                         if (pci_id->rev != PCI_ANY_ID) {
12958                                 if (bridge->revision > pci_id->rev)
12959                                         continue;
12960                         }
12961                         if (bridge->subordinate &&
12962                             (bridge->subordinate->number ==
12963                              tp->pdev->bus->number)) {
12964
12965                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12966                                 pci_dev_put(bridge);
12967                                 break;
12968                         }
12969                 }
12970         }
12971
12972         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12973                 static struct tg3_dev_id {
12974                         u32     vendor;
12975                         u32     device;
12976                 } bridge_chipsets[] = {
12977                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12978                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12979                         { },
12980                 };
12981                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12982                 struct pci_dev *bridge = NULL;
12983
12984                 while (pci_id->vendor != 0) {
12985                         bridge = pci_get_device(pci_id->vendor,
12986                                                 pci_id->device,
12987                                                 bridge);
12988                         if (!bridge) {
12989                                 pci_id++;
12990                                 continue;
12991                         }
12992                         if (bridge->subordinate &&
12993                             (bridge->subordinate->number <=
12994                              tp->pdev->bus->number) &&
12995                             (bridge->subordinate->subordinate >=
12996                              tp->pdev->bus->number)) {
12997                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12998                                 pci_dev_put(bridge);
12999                                 break;
13000                         }
13001                 }
13002         }
13003
13004         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
13005          * DMA addresses > 40-bit. This bridge may have other additional
13006          * 57xx devices behind it in some 4-port NIC designs for example.
13007          * Any tg3 device found behind the bridge will also need the 40-bit
13008          * DMA workaround.
13009          */
13010         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
13011             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13012                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
13013                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13014                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
13015         } else {
13016                 struct pci_dev *bridge = NULL;
13017
13018                 do {
13019                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
13020                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
13021                                                 bridge);
13022                         if (bridge && bridge->subordinate &&
13023                             (bridge->subordinate->number <=
13024                              tp->pdev->bus->number) &&
13025                             (bridge->subordinate->subordinate >=
13026                              tp->pdev->bus->number)) {
13027                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13028                                 pci_dev_put(bridge);
13029                                 break;
13030                         }
13031                 } while (bridge);
13032         }
13033
13034         /* Initialize misc host control in PCI block. */
13035         tp->misc_host_ctrl |= (misc_ctrl_reg &
13036                                MISC_HOST_CTRL_CHIPREV);
13037         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13038                                tp->misc_host_ctrl);
13039
13040         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13041             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13042             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13043                 tp->pdev_peer = tg3_find_peer(tp);
13044
13045         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13046             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13047             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13048                 tp->tg3_flags3 |= TG3_FLG3_5717_PLUS;
13049
13050         /* Intentionally exclude ASIC_REV_5906 */
13051         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13052             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13053             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13054             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13055             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13056             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13057             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13058                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13059
13060         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13061             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13062             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13063             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13064             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13065                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13066
13067         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13068             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13069                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13070
13071         /* 5700 B0 chips do not support checksumming correctly due
13072          * to hardware bugs.
13073          */
13074         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13075                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13076         else {
13077                 unsigned long features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_GRO;
13078
13079                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13080                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13081                         features |= NETIF_F_IPV6_CSUM;
13082                 tp->dev->features |= features;
13083                 vlan_features_add(tp->dev, features);
13084         }
13085
13086         /* Determine TSO capabilities */
13087         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13088                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13089         else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13090                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13091                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13092         else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13093                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13094                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13095                     tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13096                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13097         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13098                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13099                    tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13100                 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13101                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13102                         tp->fw_needed = FIRMWARE_TG3TSO5;
13103                 else
13104                         tp->fw_needed = FIRMWARE_TG3TSO;
13105         }
13106
13107         tp->irq_max = 1;
13108
13109         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13110                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13111                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13112                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13113                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13114                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13115                      tp->pdev_peer == tp->pdev))
13116                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13117
13118                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13119                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13120                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13121                 }
13122
13123                 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
13124                         tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13125                         tp->irq_max = TG3_IRQ_MAX_VECS;
13126                 }
13127         }
13128
13129         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13130             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13131             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13132                 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13133         else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13134                 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13135                 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13136         }
13137
13138         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13139                 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13140
13141         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13142             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13143             (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13144                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13145
13146         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13147                               &pci_state_reg);
13148
13149         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13150         if (tp->pcie_cap != 0) {
13151                 u16 lnkctl;
13152
13153                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13154
13155                 pcie_set_readrq(tp->pdev, 4096);
13156
13157                 pci_read_config_word(tp->pdev,
13158                                      tp->pcie_cap + PCI_EXP_LNKCTL,
13159                                      &lnkctl);
13160                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13161                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13162                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13163                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13164                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13165                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13166                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13167                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13168                 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13169                         tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13170                 }
13171         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13172                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13173         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13174                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13175                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13176                 if (!tp->pcix_cap) {
13177                         dev_err(&tp->pdev->dev,
13178                                 "Cannot find PCI-X capability, aborting\n");
13179                         return -EIO;
13180                 }
13181
13182                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13183                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13184         }
13185
13186         /* If we have an AMD 762 or VIA K8T800 chipset, write
13187          * reordering to the mailbox registers done by the host
13188          * controller can cause major troubles.  We read back from
13189          * every mailbox register write to force the writes to be
13190          * posted to the chip in order.
13191          */
13192         if (pci_dev_present(write_reorder_chipsets) &&
13193             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13194                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13195
13196         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13197                              &tp->pci_cacheline_sz);
13198         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13199                              &tp->pci_lat_timer);
13200         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13201             tp->pci_lat_timer < 64) {
13202                 tp->pci_lat_timer = 64;
13203                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13204                                       tp->pci_lat_timer);
13205         }
13206
13207         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13208                 /* 5700 BX chips need to have their TX producer index
13209                  * mailboxes written twice to workaround a bug.
13210                  */
13211                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13212
13213                 /* If we are in PCI-X mode, enable register write workaround.
13214                  *
13215                  * The workaround is to use indirect register accesses
13216                  * for all chip writes not to mailbox registers.
13217                  */
13218                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13219                         u32 pm_reg;
13220
13221                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13222
13223                         /* The chip can have it's power management PCI config
13224                          * space registers clobbered due to this bug.
13225                          * So explicitly force the chip into D0 here.
13226                          */
13227                         pci_read_config_dword(tp->pdev,
13228                                               tp->pm_cap + PCI_PM_CTRL,
13229                                               &pm_reg);
13230                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13231                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13232                         pci_write_config_dword(tp->pdev,
13233                                                tp->pm_cap + PCI_PM_CTRL,
13234                                                pm_reg);
13235
13236                         /* Also, force SERR#/PERR# in PCI command. */
13237                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13238                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13239                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13240                 }
13241         }
13242
13243         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13244                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13245         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13246                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13247
13248         /* Chip-specific fixup from Broadcom driver */
13249         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13250             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13251                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13252                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13253         }
13254
13255         /* Default fast path register access methods */
13256         tp->read32 = tg3_read32;
13257         tp->write32 = tg3_write32;
13258         tp->read32_mbox = tg3_read32;
13259         tp->write32_mbox = tg3_write32;
13260         tp->write32_tx_mbox = tg3_write32;
13261         tp->write32_rx_mbox = tg3_write32;
13262
13263         /* Various workaround register access methods */
13264         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13265                 tp->write32 = tg3_write_indirect_reg32;
13266         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13267                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13268                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13269                 /*
13270                  * Back to back register writes can cause problems on these
13271                  * chips, the workaround is to read back all reg writes
13272                  * except those to mailbox regs.
13273                  *
13274                  * See tg3_write_indirect_reg32().
13275                  */
13276                 tp->write32 = tg3_write_flush_reg32;
13277         }
13278
13279         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13280             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13281                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13282                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13283                         tp->write32_rx_mbox = tg3_write_flush_reg32;
13284         }
13285
13286         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13287                 tp->read32 = tg3_read_indirect_reg32;
13288                 tp->write32 = tg3_write_indirect_reg32;
13289                 tp->read32_mbox = tg3_read_indirect_mbox;
13290                 tp->write32_mbox = tg3_write_indirect_mbox;
13291                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13292                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13293
13294                 iounmap(tp->regs);
13295                 tp->regs = NULL;
13296
13297                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13298                 pci_cmd &= ~PCI_COMMAND_MEMORY;
13299                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13300         }
13301         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13302                 tp->read32_mbox = tg3_read32_mbox_5906;
13303                 tp->write32_mbox = tg3_write32_mbox_5906;
13304                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13305                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13306         }
13307
13308         if (tp->write32 == tg3_write_indirect_reg32 ||
13309             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13310              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13311               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13312                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13313
13314         /* Get eeprom hw config before calling tg3_set_power_state().
13315          * In particular, the TG3_FLG2_IS_NIC flag must be
13316          * determined before calling tg3_set_power_state() so that
13317          * we know whether or not to switch out of Vaux power.
13318          * When the flag is set, it means that GPIO1 is used for eeprom
13319          * write protect and also implies that it is a LOM where GPIOs
13320          * are not used to switch power.
13321          */
13322         tg3_get_eeprom_hw_cfg(tp);
13323
13324         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13325                 /* Allow reads and writes to the
13326                  * APE register and memory space.
13327                  */
13328                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13329                                  PCISTATE_ALLOW_APE_SHMEM_WR |
13330                                  PCISTATE_ALLOW_APE_PSPACE_WR;
13331                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13332                                        pci_state_reg);
13333         }
13334
13335         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13336             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13337             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13338             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13339             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13340                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13341
13342         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13343          * GPIO1 driven high will bring 5700's external PHY out of reset.
13344          * It is also used as eeprom write protect on LOMs.
13345          */
13346         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13347         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13348             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13349                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13350                                        GRC_LCLCTRL_GPIO_OUTPUT1);
13351         /* Unused GPIO3 must be driven as output on 5752 because there
13352          * are no pull-up resistors on unused GPIO pins.
13353          */
13354         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13355                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13356
13357         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13358             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13359             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13360                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13361
13362         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13363             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13364                 /* Turn off the debug UART. */
13365                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13366                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13367                         /* Keep VMain power. */
13368                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13369                                               GRC_LCLCTRL_GPIO_OUTPUT0;
13370         }
13371
13372         /* Force the chip into D0. */
13373         err = tg3_set_power_state(tp, PCI_D0);
13374         if (err) {
13375                 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
13376                 return err;
13377         }
13378
13379         /* Derive initial jumbo mode from MTU assigned in
13380          * ether_setup() via the alloc_etherdev() call
13381          */
13382         if (tp->dev->mtu > ETH_DATA_LEN &&
13383             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13384                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13385
13386         /* Determine WakeOnLan speed to use. */
13387         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13388             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13389             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13390             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13391                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13392         } else {
13393                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13394         }
13395
13396         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13397                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
13398
13399         /* A few boards don't want Ethernet@WireSpeed phy feature */
13400         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13401             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13402              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13403              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13404             (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
13405             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
13406                 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
13407
13408         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13409             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13410                 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
13411         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13412                 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
13413
13414         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13415             !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
13416             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13417             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13418             !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
13419                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13420                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13421                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13422                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13423                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13424                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13425                                 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
13426                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13427                                 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
13428                 } else
13429                         tp->phy_flags |= TG3_PHYFLG_BER_BUG;
13430         }
13431
13432         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13433             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13434                 tp->phy_otp = tg3_read_otp_phycfg(tp);
13435                 if (tp->phy_otp == 0)
13436                         tp->phy_otp = TG3_OTP_DEFAULT;
13437         }
13438
13439         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13440                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13441         else
13442                 tp->mi_mode = MAC_MI_MODE_BASE;
13443
13444         tp->coalesce_mode = 0;
13445         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13446             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13447                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13448
13449         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13450             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13451                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13452
13453         err = tg3_mdio_init(tp);
13454         if (err)
13455                 return err;
13456
13457         /* Initialize data/descriptor byte/word swapping. */
13458         val = tr32(GRC_MODE);
13459         val &= GRC_MODE_HOST_STACKUP;
13460         tw32(GRC_MODE, val | tp->grc_mode);
13461
13462         tg3_switch_clocks(tp);
13463
13464         /* Clear this out for sanity. */
13465         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13466
13467         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13468                               &pci_state_reg);
13469         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13470             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13471                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13472
13473                 if (chiprevid == CHIPREV_ID_5701_A0 ||
13474                     chiprevid == CHIPREV_ID_5701_B0 ||
13475                     chiprevid == CHIPREV_ID_5701_B2 ||
13476                     chiprevid == CHIPREV_ID_5701_B5) {
13477                         void __iomem *sram_base;
13478
13479                         /* Write some dummy words into the SRAM status block
13480                          * area, see if it reads back correctly.  If the return
13481                          * value is bad, force enable the PCIX workaround.
13482                          */
13483                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13484
13485                         writel(0x00000000, sram_base);
13486                         writel(0x00000000, sram_base + 4);
13487                         writel(0xffffffff, sram_base + 4);
13488                         if (readl(sram_base) != 0x00000000)
13489                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13490                 }
13491         }
13492
13493         udelay(50);
13494         tg3_nvram_init(tp);
13495
13496         grc_misc_cfg = tr32(GRC_MISC_CFG);
13497         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13498
13499         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13500             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13501              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13502                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13503
13504         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13505             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13506                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13507         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13508                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13509                                       HOSTCC_MODE_CLRTICK_TXBD);
13510
13511                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13512                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13513                                        tp->misc_host_ctrl);
13514         }
13515
13516         /* Preserve the APE MAC_MODE bits */
13517         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13518                 tp->mac_mode = tr32(MAC_MODE) |
13519                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13520         else
13521                 tp->mac_mode = TG3_DEF_MAC_MODE;
13522
13523         /* these are limited to 10/100 only */
13524         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13525              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13526             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13527              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13528              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13529               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13530               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13531             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13532              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13533               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13534               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13535             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13536             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13537             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
13538             (tp->phy_flags & TG3_PHYFLG_IS_FET))
13539                 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
13540
13541         err = tg3_phy_probe(tp);
13542         if (err) {
13543                 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
13544                 /* ... but do not return immediately ... */
13545                 tg3_mdio_fini(tp);
13546         }
13547
13548         tg3_read_vpd(tp);
13549         tg3_read_fw_ver(tp);
13550
13551         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
13552                 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
13553         } else {
13554                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13555                         tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
13556                 else
13557                         tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
13558         }
13559
13560         /* 5700 {AX,BX} chips have a broken status block link
13561          * change bit implementation, so we must use the
13562          * status register in those cases.
13563          */
13564         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13565                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13566         else
13567                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13568
13569         /* The led_ctrl is set during tg3_phy_probe, here we might
13570          * have to force the link status polling mechanism based
13571          * upon subsystem IDs.
13572          */
13573         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13574             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13575             !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
13576                 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
13577                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13578         }
13579
13580         /* For all SERDES we poll the MAC status register. */
13581         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
13582                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13583         else
13584                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13585
13586         tp->rx_offset = NET_IP_ALIGN + TG3_RX_HEADROOM;
13587         tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
13588         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13589             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
13590                 tp->rx_offset -= NET_IP_ALIGN;
13591 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
13592                 tp->rx_copy_thresh = ~(u16)0;
13593 #endif
13594         }
13595
13596         tp->rx_std_max_post = TG3_RX_RING_SIZE;
13597
13598         /* Increment the rx prod index on the rx std ring by at most
13599          * 8 for these chips to workaround hw errata.
13600          */
13601         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13602             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13603             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13604                 tp->rx_std_max_post = 8;
13605
13606         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13607                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13608                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
13609
13610         return err;
13611 }
13612
13613 #ifdef CONFIG_SPARC
13614 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13615 {
13616         struct net_device *dev = tp->dev;
13617         struct pci_dev *pdev = tp->pdev;
13618         struct device_node *dp = pci_device_to_OF_node(pdev);
13619         const unsigned char *addr;
13620         int len;
13621
13622         addr = of_get_property(dp, "local-mac-address", &len);
13623         if (addr && len == 6) {
13624                 memcpy(dev->dev_addr, addr, 6);
13625                 memcpy(dev->perm_addr, dev->dev_addr, 6);
13626                 return 0;
13627         }
13628         return -ENODEV;
13629 }
13630
13631 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13632 {
13633         struct net_device *dev = tp->dev;
13634
13635         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13636         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13637         return 0;
13638 }
13639 #endif
13640
13641 static int __devinit tg3_get_device_address(struct tg3 *tp)
13642 {
13643         struct net_device *dev = tp->dev;
13644         u32 hi, lo, mac_offset;
13645         int addr_ok = 0;
13646
13647 #ifdef CONFIG_SPARC
13648         if (!tg3_get_macaddr_sparc(tp))
13649                 return 0;
13650 #endif
13651
13652         mac_offset = 0x7c;
13653         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13654             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13655                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13656                         mac_offset = 0xcc;
13657                 if (tg3_nvram_lock(tp))
13658                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13659                 else
13660                         tg3_nvram_unlock(tp);
13661         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13662                    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
13663                 if (PCI_FUNC(tp->pdev->devfn) & 1)
13664                         mac_offset = 0xcc;
13665                 if (PCI_FUNC(tp->pdev->devfn) > 1)
13666                         mac_offset += 0x18c;
13667         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13668                 mac_offset = 0x10;
13669
13670         /* First try to get it from MAC address mailbox. */
13671         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13672         if ((hi >> 16) == 0x484b) {
13673                 dev->dev_addr[0] = (hi >>  8) & 0xff;
13674                 dev->dev_addr[1] = (hi >>  0) & 0xff;
13675
13676                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13677                 dev->dev_addr[2] = (lo >> 24) & 0xff;
13678                 dev->dev_addr[3] = (lo >> 16) & 0xff;
13679                 dev->dev_addr[4] = (lo >>  8) & 0xff;
13680                 dev->dev_addr[5] = (lo >>  0) & 0xff;
13681
13682                 /* Some old bootcode may report a 0 MAC address in SRAM */
13683                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13684         }
13685         if (!addr_ok) {
13686                 /* Next, try NVRAM. */
13687                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13688                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13689                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13690                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13691                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13692                 }
13693                 /* Finally just fetch it out of the MAC control regs. */
13694                 else {
13695                         hi = tr32(MAC_ADDR_0_HIGH);
13696                         lo = tr32(MAC_ADDR_0_LOW);
13697
13698                         dev->dev_addr[5] = lo & 0xff;
13699                         dev->dev_addr[4] = (lo >> 8) & 0xff;
13700                         dev->dev_addr[3] = (lo >> 16) & 0xff;
13701                         dev->dev_addr[2] = (lo >> 24) & 0xff;
13702                         dev->dev_addr[1] = hi & 0xff;
13703                         dev->dev_addr[0] = (hi >> 8) & 0xff;
13704                 }
13705         }
13706
13707         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13708 #ifdef CONFIG_SPARC
13709                 if (!tg3_get_default_macaddr_sparc(tp))
13710                         return 0;
13711 #endif
13712                 return -EINVAL;
13713         }
13714         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13715         return 0;
13716 }
13717
13718 #define BOUNDARY_SINGLE_CACHELINE       1
13719 #define BOUNDARY_MULTI_CACHELINE        2
13720
13721 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13722 {
13723         int cacheline_size;
13724         u8 byte;
13725         int goal;
13726
13727         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13728         if (byte == 0)
13729                 cacheline_size = 1024;
13730         else
13731                 cacheline_size = (int) byte * 4;
13732
13733         /* On 5703 and later chips, the boundary bits have no
13734          * effect.
13735          */
13736         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13737             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13738             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13739                 goto out;
13740
13741 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13742         goal = BOUNDARY_MULTI_CACHELINE;
13743 #else
13744 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13745         goal = BOUNDARY_SINGLE_CACHELINE;
13746 #else
13747         goal = 0;
13748 #endif
13749 #endif
13750
13751         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
13752                 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13753                 goto out;
13754         }
13755
13756         if (!goal)
13757                 goto out;
13758
13759         /* PCI controllers on most RISC systems tend to disconnect
13760          * when a device tries to burst across a cache-line boundary.
13761          * Therefore, letting tg3 do so just wastes PCI bandwidth.
13762          *
13763          * Unfortunately, for PCI-E there are only limited
13764          * write-side controls for this, and thus for reads
13765          * we will still get the disconnects.  We'll also waste
13766          * these PCI cycles for both read and write for chips
13767          * other than 5700 and 5701 which do not implement the
13768          * boundary bits.
13769          */
13770         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13771             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13772                 switch (cacheline_size) {
13773                 case 16:
13774                 case 32:
13775                 case 64:
13776                 case 128:
13777                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13778                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13779                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13780                         } else {
13781                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13782                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13783                         }
13784                         break;
13785
13786                 case 256:
13787                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13788                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13789                         break;
13790
13791                 default:
13792                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13793                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13794                         break;
13795                 }
13796         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13797                 switch (cacheline_size) {
13798                 case 16:
13799                 case 32:
13800                 case 64:
13801                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13802                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13803                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13804                                 break;
13805                         }
13806                         /* fallthrough */
13807                 case 128:
13808                 default:
13809                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13810                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13811                         break;
13812                 }
13813         } else {
13814                 switch (cacheline_size) {
13815                 case 16:
13816                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13817                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13818                                         DMA_RWCTRL_WRITE_BNDRY_16);
13819                                 break;
13820                         }
13821                         /* fallthrough */
13822                 case 32:
13823                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13824                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13825                                         DMA_RWCTRL_WRITE_BNDRY_32);
13826                                 break;
13827                         }
13828                         /* fallthrough */
13829                 case 64:
13830                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13831                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13832                                         DMA_RWCTRL_WRITE_BNDRY_64);
13833                                 break;
13834                         }
13835                         /* fallthrough */
13836                 case 128:
13837                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13838                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13839                                         DMA_RWCTRL_WRITE_BNDRY_128);
13840                                 break;
13841                         }
13842                         /* fallthrough */
13843                 case 256:
13844                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
13845                                 DMA_RWCTRL_WRITE_BNDRY_256);
13846                         break;
13847                 case 512:
13848                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
13849                                 DMA_RWCTRL_WRITE_BNDRY_512);
13850                         break;
13851                 case 1024:
13852                 default:
13853                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13854                                 DMA_RWCTRL_WRITE_BNDRY_1024);
13855                         break;
13856                 }
13857         }
13858
13859 out:
13860         return val;
13861 }
13862
13863 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13864 {
13865         struct tg3_internal_buffer_desc test_desc;
13866         u32 sram_dma_descs;
13867         int i, ret;
13868
13869         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13870
13871         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13872         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13873         tw32(RDMAC_STATUS, 0);
13874         tw32(WDMAC_STATUS, 0);
13875
13876         tw32(BUFMGR_MODE, 0);
13877         tw32(FTQ_RESET, 0);
13878
13879         test_desc.addr_hi = ((u64) buf_dma) >> 32;
13880         test_desc.addr_lo = buf_dma & 0xffffffff;
13881         test_desc.nic_mbuf = 0x00002100;
13882         test_desc.len = size;
13883
13884         /*
13885          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13886          * the *second* time the tg3 driver was getting loaded after an
13887          * initial scan.
13888          *
13889          * Broadcom tells me:
13890          *   ...the DMA engine is connected to the GRC block and a DMA
13891          *   reset may affect the GRC block in some unpredictable way...
13892          *   The behavior of resets to individual blocks has not been tested.
13893          *
13894          * Broadcom noted the GRC reset will also reset all sub-components.
13895          */
13896         if (to_device) {
13897                 test_desc.cqid_sqid = (13 << 8) | 2;
13898
13899                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13900                 udelay(40);
13901         } else {
13902                 test_desc.cqid_sqid = (16 << 8) | 7;
13903
13904                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13905                 udelay(40);
13906         }
13907         test_desc.flags = 0x00000005;
13908
13909         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13910                 u32 val;
13911
13912                 val = *(((u32 *)&test_desc) + i);
13913                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13914                                        sram_dma_descs + (i * sizeof(u32)));
13915                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13916         }
13917         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13918
13919         if (to_device)
13920                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13921         else
13922                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13923
13924         ret = -ENODEV;
13925         for (i = 0; i < 40; i++) {
13926                 u32 val;
13927
13928                 if (to_device)
13929                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13930                 else
13931                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13932                 if ((val & 0xffff) == sram_dma_descs) {
13933                         ret = 0;
13934                         break;
13935                 }
13936
13937                 udelay(100);
13938         }
13939
13940         return ret;
13941 }
13942
13943 #define TEST_BUFFER_SIZE        0x2000
13944
13945 static int __devinit tg3_test_dma(struct tg3 *tp)
13946 {
13947         dma_addr_t buf_dma;
13948         u32 *buf, saved_dma_rwctrl;
13949         int ret = 0;
13950
13951         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13952         if (!buf) {
13953                 ret = -ENOMEM;
13954                 goto out_nofree;
13955         }
13956
13957         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13958                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13959
13960         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13961
13962         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13963                 goto out;
13964
13965         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13966                 /* DMA read watermark not used on PCIE */
13967                 tp->dma_rwctrl |= 0x00180000;
13968         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
13969                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13970                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
13971                         tp->dma_rwctrl |= 0x003f0000;
13972                 else
13973                         tp->dma_rwctrl |= 0x003f000f;
13974         } else {
13975                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13976                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13977                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
13978                         u32 read_water = 0x7;
13979
13980                         /* If the 5704 is behind the EPB bridge, we can
13981                          * do the less restrictive ONE_DMA workaround for
13982                          * better performance.
13983                          */
13984                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13985                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13986                                 tp->dma_rwctrl |= 0x8000;
13987                         else if (ccval == 0x6 || ccval == 0x7)
13988                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13989
13990                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13991                                 read_water = 4;
13992                         /* Set bit 23 to enable PCIX hw bug fix */
13993                         tp->dma_rwctrl |=
13994                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13995                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13996                                 (1 << 23);
13997                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13998                         /* 5780 always in PCIX mode */
13999                         tp->dma_rwctrl |= 0x00144000;
14000                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
14001                         /* 5714 always in PCIX mode */
14002                         tp->dma_rwctrl |= 0x00148000;
14003                 } else {
14004                         tp->dma_rwctrl |= 0x001b000f;
14005                 }
14006         }
14007
14008         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14009             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14010                 tp->dma_rwctrl &= 0xfffffff0;
14011
14012         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14013             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
14014                 /* Remove this if it causes problems for some boards. */
14015                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
14016
14017                 /* On 5700/5701 chips, we need to set this bit.
14018                  * Otherwise the chip will issue cacheline transactions
14019                  * to streamable DMA memory with not all the byte
14020                  * enables turned on.  This is an error on several
14021                  * RISC PCI controllers, in particular sparc64.
14022                  *
14023                  * On 5703/5704 chips, this bit has been reassigned
14024                  * a different meaning.  In particular, it is used
14025                  * on those chips to enable a PCI-X workaround.
14026                  */
14027                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
14028         }
14029
14030         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14031
14032 #if 0
14033         /* Unneeded, already done by tg3_get_invariants.  */
14034         tg3_switch_clocks(tp);
14035 #endif
14036
14037         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14038             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14039                 goto out;
14040
14041         /* It is best to perform DMA test with maximum write burst size
14042          * to expose the 5700/5701 write DMA bug.
14043          */
14044         saved_dma_rwctrl = tp->dma_rwctrl;
14045         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14046         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14047
14048         while (1) {
14049                 u32 *p = buf, i;
14050
14051                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14052                         p[i] = i;
14053
14054                 /* Send the buffer to the chip. */
14055                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14056                 if (ret) {
14057                         dev_err(&tp->pdev->dev,
14058                                 "%s: Buffer write failed. err = %d\n",
14059                                 __func__, ret);
14060                         break;
14061                 }
14062
14063 #if 0
14064                 /* validate data reached card RAM correctly. */
14065                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14066                         u32 val;
14067                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
14068                         if (le32_to_cpu(val) != p[i]) {
14069                                 dev_err(&tp->pdev->dev,
14070                                         "%s: Buffer corrupted on device! "
14071                                         "(%d != %d)\n", __func__, val, i);
14072                                 /* ret = -ENODEV here? */
14073                         }
14074                         p[i] = 0;
14075                 }
14076 #endif
14077                 /* Now read it back. */
14078                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14079                 if (ret) {
14080                         dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
14081                                 "err = %d\n", __func__, ret);
14082                         break;
14083                 }
14084
14085                 /* Verify it. */
14086                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14087                         if (p[i] == i)
14088                                 continue;
14089
14090                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14091                             DMA_RWCTRL_WRITE_BNDRY_16) {
14092                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14093                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14094                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14095                                 break;
14096                         } else {
14097                                 dev_err(&tp->pdev->dev,
14098                                         "%s: Buffer corrupted on read back! "
14099                                         "(%d != %d)\n", __func__, p[i], i);
14100                                 ret = -ENODEV;
14101                                 goto out;
14102                         }
14103                 }
14104
14105                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14106                         /* Success. */
14107                         ret = 0;
14108                         break;
14109                 }
14110         }
14111         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14112             DMA_RWCTRL_WRITE_BNDRY_16) {
14113                 static struct pci_device_id dma_wait_state_chipsets[] = {
14114                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14115                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14116                         { },
14117                 };
14118
14119                 /* DMA test passed without adjusting DMA boundary,
14120                  * now look for chipsets that are known to expose the
14121                  * DMA bug without failing the test.
14122                  */
14123                 if (pci_dev_present(dma_wait_state_chipsets)) {
14124                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14125                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14126                 } else {
14127                         /* Safe to use the calculated DMA boundary. */
14128                         tp->dma_rwctrl = saved_dma_rwctrl;
14129                 }
14130
14131                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14132         }
14133
14134 out:
14135         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14136 out_nofree:
14137         return ret;
14138 }
14139
14140 static void __devinit tg3_init_link_config(struct tg3 *tp)
14141 {
14142         tp->link_config.advertising =
14143                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14144                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14145                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14146                  ADVERTISED_Autoneg | ADVERTISED_MII);
14147         tp->link_config.speed = SPEED_INVALID;
14148         tp->link_config.duplex = DUPLEX_INVALID;
14149         tp->link_config.autoneg = AUTONEG_ENABLE;
14150         tp->link_config.active_speed = SPEED_INVALID;
14151         tp->link_config.active_duplex = DUPLEX_INVALID;
14152         tp->link_config.orig_speed = SPEED_INVALID;
14153         tp->link_config.orig_duplex = DUPLEX_INVALID;
14154         tp->link_config.orig_autoneg = AUTONEG_INVALID;
14155 }
14156
14157 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14158 {
14159         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
14160                 tp->bufmgr_config.mbuf_read_dma_low_water =
14161                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14162                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14163                         DEFAULT_MB_MACRX_LOW_WATER_57765;
14164                 tp->bufmgr_config.mbuf_high_water =
14165                         DEFAULT_MB_HIGH_WATER_57765;
14166
14167                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14168                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14169                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14170                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14171                 tp->bufmgr_config.mbuf_high_water_jumbo =
14172                         DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14173         } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14174                 tp->bufmgr_config.mbuf_read_dma_low_water =
14175                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14176                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14177                         DEFAULT_MB_MACRX_LOW_WATER_5705;
14178                 tp->bufmgr_config.mbuf_high_water =
14179                         DEFAULT_MB_HIGH_WATER_5705;
14180                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14181                         tp->bufmgr_config.mbuf_mac_rx_low_water =
14182                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
14183                         tp->bufmgr_config.mbuf_high_water =
14184                                 DEFAULT_MB_HIGH_WATER_5906;
14185                 }
14186
14187                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14188                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14189                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14190                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14191                 tp->bufmgr_config.mbuf_high_water_jumbo =
14192                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14193         } else {
14194                 tp->bufmgr_config.mbuf_read_dma_low_water =
14195                         DEFAULT_MB_RDMA_LOW_WATER;
14196                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14197                         DEFAULT_MB_MACRX_LOW_WATER;
14198                 tp->bufmgr_config.mbuf_high_water =
14199                         DEFAULT_MB_HIGH_WATER;
14200
14201                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14202                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14203                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14204                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14205                 tp->bufmgr_config.mbuf_high_water_jumbo =
14206                         DEFAULT_MB_HIGH_WATER_JUMBO;
14207         }
14208
14209         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14210         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14211 }
14212
14213 static char * __devinit tg3_phy_string(struct tg3 *tp)
14214 {
14215         switch (tp->phy_id & TG3_PHY_ID_MASK) {
14216         case TG3_PHY_ID_BCM5400:        return "5400";
14217         case TG3_PHY_ID_BCM5401:        return "5401";
14218         case TG3_PHY_ID_BCM5411:        return "5411";
14219         case TG3_PHY_ID_BCM5701:        return "5701";
14220         case TG3_PHY_ID_BCM5703:        return "5703";
14221         case TG3_PHY_ID_BCM5704:        return "5704";
14222         case TG3_PHY_ID_BCM5705:        return "5705";
14223         case TG3_PHY_ID_BCM5750:        return "5750";
14224         case TG3_PHY_ID_BCM5752:        return "5752";
14225         case TG3_PHY_ID_BCM5714:        return "5714";
14226         case TG3_PHY_ID_BCM5780:        return "5780";
14227         case TG3_PHY_ID_BCM5755:        return "5755";
14228         case TG3_PHY_ID_BCM5787:        return "5787";
14229         case TG3_PHY_ID_BCM5784:        return "5784";
14230         case TG3_PHY_ID_BCM5756:        return "5722/5756";
14231         case TG3_PHY_ID_BCM5906:        return "5906";
14232         case TG3_PHY_ID_BCM5761:        return "5761";
14233         case TG3_PHY_ID_BCM5718C:       return "5718C";
14234         case TG3_PHY_ID_BCM5718S:       return "5718S";
14235         case TG3_PHY_ID_BCM57765:       return "57765";
14236         case TG3_PHY_ID_BCM5719C:       return "5719C";
14237         case TG3_PHY_ID_BCM8002:        return "8002/serdes";
14238         case 0:                 return "serdes";
14239         default:                return "unknown";
14240         }
14241 }
14242
14243 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14244 {
14245         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14246                 strcpy(str, "PCI Express");
14247                 return str;
14248         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14249                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14250
14251                 strcpy(str, "PCIX:");
14252
14253                 if ((clock_ctrl == 7) ||
14254                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14255                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14256                         strcat(str, "133MHz");
14257                 else if (clock_ctrl == 0)
14258                         strcat(str, "33MHz");
14259                 else if (clock_ctrl == 2)
14260                         strcat(str, "50MHz");
14261                 else if (clock_ctrl == 4)
14262                         strcat(str, "66MHz");
14263                 else if (clock_ctrl == 6)
14264                         strcat(str, "100MHz");
14265         } else {
14266                 strcpy(str, "PCI:");
14267                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14268                         strcat(str, "66MHz");
14269                 else
14270                         strcat(str, "33MHz");
14271         }
14272         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14273                 strcat(str, ":32-bit");
14274         else
14275                 strcat(str, ":64-bit");
14276         return str;
14277 }
14278
14279 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14280 {
14281         struct pci_dev *peer;
14282         unsigned int func, devnr = tp->pdev->devfn & ~7;
14283
14284         for (func = 0; func < 8; func++) {
14285                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14286                 if (peer && peer != tp->pdev)
14287                         break;
14288                 pci_dev_put(peer);
14289         }
14290         /* 5704 can be configured in single-port mode, set peer to
14291          * tp->pdev in that case.
14292          */
14293         if (!peer) {
14294                 peer = tp->pdev;
14295                 return peer;
14296         }
14297
14298         /*
14299          * We don't need to keep the refcount elevated; there's no way
14300          * to remove one half of this device without removing the other
14301          */
14302         pci_dev_put(peer);
14303
14304         return peer;
14305 }
14306
14307 static void __devinit tg3_init_coal(struct tg3 *tp)
14308 {
14309         struct ethtool_coalesce *ec = &tp->coal;
14310
14311         memset(ec, 0, sizeof(*ec));
14312         ec->cmd = ETHTOOL_GCOALESCE;
14313         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14314         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14315         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14316         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14317         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14318         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14319         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14320         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14321         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14322
14323         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14324                                  HOSTCC_MODE_CLRTICK_TXBD)) {
14325                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14326                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14327                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14328                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14329         }
14330
14331         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14332                 ec->rx_coalesce_usecs_irq = 0;
14333                 ec->tx_coalesce_usecs_irq = 0;
14334                 ec->stats_block_coalesce_usecs = 0;
14335         }
14336 }
14337
14338 static const struct net_device_ops tg3_netdev_ops = {
14339         .ndo_open               = tg3_open,
14340         .ndo_stop               = tg3_close,
14341         .ndo_start_xmit         = tg3_start_xmit,
14342         .ndo_get_stats64        = tg3_get_stats64,
14343         .ndo_validate_addr      = eth_validate_addr,
14344         .ndo_set_multicast_list = tg3_set_rx_mode,
14345         .ndo_set_mac_address    = tg3_set_mac_addr,
14346         .ndo_do_ioctl           = tg3_ioctl,
14347         .ndo_tx_timeout         = tg3_tx_timeout,
14348         .ndo_change_mtu         = tg3_change_mtu,
14349 #if TG3_VLAN_TAG_USED
14350         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14351 #endif
14352 #ifdef CONFIG_NET_POLL_CONTROLLER
14353         .ndo_poll_controller    = tg3_poll_controller,
14354 #endif
14355 };
14356
14357 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14358         .ndo_open               = tg3_open,
14359         .ndo_stop               = tg3_close,
14360         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
14361         .ndo_get_stats64        = tg3_get_stats64,
14362         .ndo_validate_addr      = eth_validate_addr,
14363         .ndo_set_multicast_list = tg3_set_rx_mode,
14364         .ndo_set_mac_address    = tg3_set_mac_addr,
14365         .ndo_do_ioctl           = tg3_ioctl,
14366         .ndo_tx_timeout         = tg3_tx_timeout,
14367         .ndo_change_mtu         = tg3_change_mtu,
14368 #if TG3_VLAN_TAG_USED
14369         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14370 #endif
14371 #ifdef CONFIG_NET_POLL_CONTROLLER
14372         .ndo_poll_controller    = tg3_poll_controller,
14373 #endif
14374 };
14375
14376 static int __devinit tg3_init_one(struct pci_dev *pdev,
14377                                   const struct pci_device_id *ent)
14378 {
14379         struct net_device *dev;
14380         struct tg3 *tp;
14381         int i, err, pm_cap;
14382         u32 sndmbx, rcvmbx, intmbx;
14383         char str[40];
14384         u64 dma_mask, persist_dma_mask;
14385
14386         printk_once(KERN_INFO "%s\n", version);
14387
14388         err = pci_enable_device(pdev);
14389         if (err) {
14390                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
14391                 return err;
14392         }
14393
14394         err = pci_request_regions(pdev, DRV_MODULE_NAME);
14395         if (err) {
14396                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
14397                 goto err_out_disable_pdev;
14398         }
14399
14400         pci_set_master(pdev);
14401
14402         /* Find power-management capability. */
14403         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14404         if (pm_cap == 0) {
14405                 dev_err(&pdev->dev,
14406                         "Cannot find Power Management capability, aborting\n");
14407                 err = -EIO;
14408                 goto err_out_free_res;
14409         }
14410
14411         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14412         if (!dev) {
14413                 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
14414                 err = -ENOMEM;
14415                 goto err_out_free_res;
14416         }
14417
14418         SET_NETDEV_DEV(dev, &pdev->dev);
14419
14420 #if TG3_VLAN_TAG_USED
14421         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14422 #endif
14423
14424         tp = netdev_priv(dev);
14425         tp->pdev = pdev;
14426         tp->dev = dev;
14427         tp->pm_cap = pm_cap;
14428         tp->rx_mode = TG3_DEF_RX_MODE;
14429         tp->tx_mode = TG3_DEF_TX_MODE;
14430
14431         if (tg3_debug > 0)
14432                 tp->msg_enable = tg3_debug;
14433         else
14434                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14435
14436         /* The word/byte swap controls here control register access byte
14437          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
14438          * setting below.
14439          */
14440         tp->misc_host_ctrl =
14441                 MISC_HOST_CTRL_MASK_PCI_INT |
14442                 MISC_HOST_CTRL_WORD_SWAP |
14443                 MISC_HOST_CTRL_INDIR_ACCESS |
14444                 MISC_HOST_CTRL_PCISTATE_RW;
14445
14446         /* The NONFRM (non-frame) byte/word swap controls take effect
14447          * on descriptor entries, anything which isn't packet data.
14448          *
14449          * The StrongARM chips on the board (one for tx, one for rx)
14450          * are running in big-endian mode.
14451          */
14452         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14453                         GRC_MODE_WSWAP_NONFRM_DATA);
14454 #ifdef __BIG_ENDIAN
14455         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14456 #endif
14457         spin_lock_init(&tp->lock);
14458         spin_lock_init(&tp->indirect_lock);
14459         INIT_WORK(&tp->reset_task, tg3_reset_task);
14460
14461         tp->regs = pci_ioremap_bar(pdev, BAR_0);
14462         if (!tp->regs) {
14463                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
14464                 err = -ENOMEM;
14465                 goto err_out_free_dev;
14466         }
14467
14468         tg3_init_link_config(tp);
14469
14470         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14471         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14472
14473         dev->ethtool_ops = &tg3_ethtool_ops;
14474         dev->watchdog_timeo = TG3_TX_TIMEOUT;
14475         dev->irq = pdev->irq;
14476
14477         err = tg3_get_invariants(tp);
14478         if (err) {
14479                 dev_err(&pdev->dev,
14480                         "Problem fetching invariants of chip, aborting\n");
14481                 goto err_out_iounmap;
14482         }
14483
14484         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14485             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
14486             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
14487                 dev->netdev_ops = &tg3_netdev_ops;
14488         else
14489                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14490
14491
14492         /* The EPB bridge inside 5714, 5715, and 5780 and any
14493          * device behind the EPB cannot support DMA addresses > 40-bit.
14494          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14495          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14496          * do DMA address check in tg3_start_xmit().
14497          */
14498         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14499                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14500         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14501                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14502 #ifdef CONFIG_HIGHMEM
14503                 dma_mask = DMA_BIT_MASK(64);
14504 #endif
14505         } else
14506                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14507
14508         /* Configure DMA attributes. */
14509         if (dma_mask > DMA_BIT_MASK(32)) {
14510                 err = pci_set_dma_mask(pdev, dma_mask);
14511                 if (!err) {
14512                         dev->features |= NETIF_F_HIGHDMA;
14513                         err = pci_set_consistent_dma_mask(pdev,
14514                                                           persist_dma_mask);
14515                         if (err < 0) {
14516                                 dev_err(&pdev->dev, "Unable to obtain 64 bit "
14517                                         "DMA for consistent allocations\n");
14518                                 goto err_out_iounmap;
14519                         }
14520                 }
14521         }
14522         if (err || dma_mask == DMA_BIT_MASK(32)) {
14523                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14524                 if (err) {
14525                         dev_err(&pdev->dev,
14526                                 "No usable DMA configuration, aborting\n");
14527                         goto err_out_iounmap;
14528                 }
14529         }
14530
14531         tg3_init_bufmgr_config(tp);
14532
14533         /* Selectively allow TSO based on operating conditions */
14534         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14535             (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14536                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14537         else {
14538                 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14539                 tp->fw_needed = NULL;
14540         }
14541
14542         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14543                 tp->fw_needed = FIRMWARE_TG3;
14544
14545         /* TSO is on by default on chips that support hardware TSO.
14546          * Firmware TSO on older chips gives lower performance, so it
14547          * is off by default, but can be enabled using ethtool.
14548          */
14549         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14550             (dev->features & NETIF_F_IP_CSUM)) {
14551                 dev->features |= NETIF_F_TSO;
14552                 vlan_features_add(dev, NETIF_F_TSO);
14553         }
14554         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14555             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14556                 if (dev->features & NETIF_F_IPV6_CSUM) {
14557                         dev->features |= NETIF_F_TSO6;
14558                         vlan_features_add(dev, NETIF_F_TSO6);
14559                 }
14560                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14561                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14562                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14563                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14564                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14565                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
14566                         dev->features |= NETIF_F_TSO_ECN;
14567                         vlan_features_add(dev, NETIF_F_TSO_ECN);
14568                 }
14569         }
14570
14571         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14572             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14573             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14574                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14575                 tp->rx_pending = 63;
14576         }
14577
14578         err = tg3_get_device_address(tp);
14579         if (err) {
14580                 dev_err(&pdev->dev,
14581                         "Could not obtain valid ethernet address, aborting\n");
14582                 goto err_out_iounmap;
14583         }
14584
14585         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14586                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14587                 if (!tp->aperegs) {
14588                         dev_err(&pdev->dev,
14589                                 "Cannot map APE registers, aborting\n");
14590                         err = -ENOMEM;
14591                         goto err_out_iounmap;
14592                 }
14593
14594                 tg3_ape_lock_init(tp);
14595
14596                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14597                         tg3_read_dash_ver(tp);
14598         }
14599
14600         /*
14601          * Reset chip in case UNDI or EFI driver did not shutdown
14602          * DMA self test will enable WDMAC and we'll see (spurious)
14603          * pending DMA on the PCI bus at that point.
14604          */
14605         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14606             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14607                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14608                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14609         }
14610
14611         err = tg3_test_dma(tp);
14612         if (err) {
14613                 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
14614                 goto err_out_apeunmap;
14615         }
14616
14617         /* flow control autonegotiation is default behavior */
14618         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14619         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14620
14621         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14622         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14623         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14624         for (i = 0; i < tp->irq_max; i++) {
14625                 struct tg3_napi *tnapi = &tp->napi[i];
14626
14627                 tnapi->tp = tp;
14628                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14629
14630                 tnapi->int_mbox = intmbx;
14631                 if (i < 4)
14632                         intmbx += 0x8;
14633                 else
14634                         intmbx += 0x4;
14635
14636                 tnapi->consmbox = rcvmbx;
14637                 tnapi->prodmbox = sndmbx;
14638
14639                 if (i)
14640                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14641                 else
14642                         tnapi->coal_now = HOSTCC_MODE_NOW;
14643
14644                 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14645                         break;
14646
14647                 /*
14648                  * If we support MSIX, we'll be using RSS.  If we're using
14649                  * RSS, the first vector only handles link interrupts and the
14650                  * remaining vectors handle rx and tx interrupts.  Reuse the
14651                  * mailbox values for the next iteration.  The values we setup
14652                  * above are still useful for the single vectored mode.
14653                  */
14654                 if (!i)
14655                         continue;
14656
14657                 rcvmbx += 0x8;
14658
14659                 if (sndmbx & 0x4)
14660                         sndmbx -= 0x4;
14661                 else
14662                         sndmbx += 0xc;
14663         }
14664
14665         tg3_init_coal(tp);
14666
14667         pci_set_drvdata(pdev, dev);
14668
14669         err = register_netdev(dev);
14670         if (err) {
14671                 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
14672                 goto err_out_apeunmap;
14673         }
14674
14675         netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14676                     tp->board_part_number,
14677                     tp->pci_chip_rev_id,
14678                     tg3_bus_string(tp, str),
14679                     dev->dev_addr);
14680
14681         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
14682                 struct phy_device *phydev;
14683                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14684                 netdev_info(dev,
14685                             "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14686                             phydev->drv->name, dev_name(&phydev->dev));
14687         } else {
14688                 char *ethtype;
14689
14690                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
14691                         ethtype = "10/100Base-TX";
14692                 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
14693                         ethtype = "1000Base-SX";
14694                 else
14695                         ethtype = "10/100/1000Base-T";
14696
14697                 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
14698                             "(WireSpeed[%d])\n", tg3_phy_string(tp), ethtype,
14699                           (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0);
14700         }
14701
14702         netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14703                     (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14704                     (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14705                     (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
14706                     (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14707                     (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14708         netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14709                     tp->dma_rwctrl,
14710                     pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
14711                     ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
14712
14713         return 0;
14714
14715 err_out_apeunmap:
14716         if (tp->aperegs) {
14717                 iounmap(tp->aperegs);
14718                 tp->aperegs = NULL;
14719         }
14720
14721 err_out_iounmap:
14722         if (tp->regs) {
14723                 iounmap(tp->regs);
14724                 tp->regs = NULL;
14725         }
14726
14727 err_out_free_dev:
14728         free_netdev(dev);
14729
14730 err_out_free_res:
14731         pci_release_regions(pdev);
14732
14733 err_out_disable_pdev:
14734         pci_disable_device(pdev);
14735         pci_set_drvdata(pdev, NULL);
14736         return err;
14737 }
14738
14739 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14740 {
14741         struct net_device *dev = pci_get_drvdata(pdev);
14742
14743         if (dev) {
14744                 struct tg3 *tp = netdev_priv(dev);
14745
14746                 if (tp->fw)
14747                         release_firmware(tp->fw);
14748
14749                 flush_scheduled_work();
14750
14751                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14752                         tg3_phy_fini(tp);
14753                         tg3_mdio_fini(tp);
14754                 }
14755
14756                 unregister_netdev(dev);
14757                 if (tp->aperegs) {
14758                         iounmap(tp->aperegs);
14759                         tp->aperegs = NULL;
14760                 }
14761                 if (tp->regs) {
14762                         iounmap(tp->regs);
14763                         tp->regs = NULL;
14764                 }
14765                 free_netdev(dev);
14766                 pci_release_regions(pdev);
14767                 pci_disable_device(pdev);
14768                 pci_set_drvdata(pdev, NULL);
14769         }
14770 }
14771
14772 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14773 {
14774         struct net_device *dev = pci_get_drvdata(pdev);
14775         struct tg3 *tp = netdev_priv(dev);
14776         pci_power_t target_state;
14777         int err;
14778
14779         /* PCI register 4 needs to be saved whether netif_running() or not.
14780          * MSI address and data need to be saved if using MSI and
14781          * netif_running().
14782          */
14783         pci_save_state(pdev);
14784
14785         if (!netif_running(dev))
14786                 return 0;
14787
14788         flush_scheduled_work();
14789         tg3_phy_stop(tp);
14790         tg3_netif_stop(tp);
14791
14792         del_timer_sync(&tp->timer);
14793
14794         tg3_full_lock(tp, 1);
14795         tg3_disable_ints(tp);
14796         tg3_full_unlock(tp);
14797
14798         netif_device_detach(dev);
14799
14800         tg3_full_lock(tp, 0);
14801         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14802         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14803         tg3_full_unlock(tp);
14804
14805         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14806
14807         err = tg3_set_power_state(tp, target_state);
14808         if (err) {
14809                 int err2;
14810
14811                 tg3_full_lock(tp, 0);
14812
14813                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14814                 err2 = tg3_restart_hw(tp, 1);
14815                 if (err2)
14816                         goto out;
14817
14818                 tp->timer.expires = jiffies + tp->timer_offset;
14819                 add_timer(&tp->timer);
14820
14821                 netif_device_attach(dev);
14822                 tg3_netif_start(tp);
14823
14824 out:
14825                 tg3_full_unlock(tp);
14826
14827                 if (!err2)
14828                         tg3_phy_start(tp);
14829         }
14830
14831         return err;
14832 }
14833
14834 static int tg3_resume(struct pci_dev *pdev)
14835 {
14836         struct net_device *dev = pci_get_drvdata(pdev);
14837         struct tg3 *tp = netdev_priv(dev);
14838         int err;
14839
14840         pci_restore_state(tp->pdev);
14841
14842         if (!netif_running(dev))
14843                 return 0;
14844
14845         err = tg3_set_power_state(tp, PCI_D0);
14846         if (err)
14847                 return err;
14848
14849         netif_device_attach(dev);
14850
14851         tg3_full_lock(tp, 0);
14852
14853         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14854         err = tg3_restart_hw(tp, 1);
14855         if (err)
14856                 goto out;
14857
14858         tp->timer.expires = jiffies + tp->timer_offset;
14859         add_timer(&tp->timer);
14860
14861         tg3_netif_start(tp);
14862
14863 out:
14864         tg3_full_unlock(tp);
14865
14866         if (!err)
14867                 tg3_phy_start(tp);
14868
14869         return err;
14870 }
14871
14872 static struct pci_driver tg3_driver = {
14873         .name           = DRV_MODULE_NAME,
14874         .id_table       = tg3_pci_tbl,
14875         .probe          = tg3_init_one,
14876         .remove         = __devexit_p(tg3_remove_one),
14877         .suspend        = tg3_suspend,
14878         .resume         = tg3_resume
14879 };
14880
14881 static int __init tg3_init(void)
14882 {
14883         return pci_register_driver(&tg3_driver);
14884 }
14885
14886 static void __exit tg3_cleanup(void)
14887 {
14888         pci_unregister_driver(&tg3_driver);
14889 }
14890
14891 module_init(tg3_init);
14892 module_exit(tg3_cleanup);