drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2010 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/stringify.h>
  22 #include <linux/kernel.h>
  23 #include <linux/types.h>
  24 #include <linux/compiler.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/in.h>
  28 #include <linux/init.h>
  29 #include <linux/ioport.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/ethtool.h>
  35 #include <linux/mii.h>
  36 #include <linux/phy.h>
  37 #include <linux/brcmphy.h>
  38 #include <linux/if_vlan.h>
  39 #include <linux/ip.h>
  40 #include <linux/tcp.h>
  41 #include <linux/workqueue.h>
  42 #include <linux/prefetch.h>
  43 #include <linux/dma-mapping.h>
  44 #include <linux/firmware.h>
  45
  46 #include <net/checksum.h>
  47 #include <net/ip.h>
  48
  49 #include <asm/system.h>
  50 #include <asm/io.h>
  51 #include <asm/byteorder.h>
  52 #include <asm/uaccess.h>
  53
  54 #ifdef CONFIG_SPARC
  55 #include <asm/idprom.h>
  56 #include <asm/prom.h>
  57 #endif
  58
  59 #define BAR_0   0
  60 #define BAR_2   2
  61
  62 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  63 #define TG3_VLAN_TAG_USED 1
  64 #else
  65 #define TG3_VLAN_TAG_USED 0
  66 #endif
  67
  68 #include "tg3.h"
  69
  70 #define DRV_MODULE_NAME         "tg3"
  71 #define TG3_MAJ_NUM                     3
  72 #define TG3_MIN_NUM                     113
  73 #define DRV_MODULE_VERSION      \
  74         __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
  75 #define DRV_MODULE_RELDATE      "August 2, 2010"
  76
  77 #define TG3_DEF_MAC_MODE        0
  78 #define TG3_DEF_RX_MODE         0
  79 #define TG3_DEF_TX_MODE         0
  80 #define TG3_DEF_MSG_ENABLE        \
  81         (NETIF_MSG_DRV          | \
  82          NETIF_MSG_PROBE        | \
  83          NETIF_MSG_LINK         | \
  84          NETIF_MSG_TIMER        | \
  85          NETIF_MSG_IFDOWN       | \
  86          NETIF_MSG_IFUP         | \
  87          NETIF_MSG_RX_ERR       | \
  88          NETIF_MSG_TX_ERR)
  89
  90 /* length of time before we decide the hardware is borked,
  91  * and dev->tx_timeout() should be called to fix the problem
  92  */
  93 #define TG3_TX_TIMEOUT                  (5 * HZ)
  94
  95 /* hardware minimum and maximum for a single frame's data payload */
  96 #define TG3_MIN_MTU                     60
  97 #define TG3_MAX_MTU(tp) \
  98         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  99
 100 /* These numbers seem to be hard coded in the NIC firmware somehow.
 101  * You can't change the ring sizes, but you can change where you place
 102  * them in the NIC onboard memory.
 103  */
 104 #define TG3_RX_STD_RING_SIZE(tp)        512
 105 #define TG3_DEF_RX_RING_PENDING         200
 106 #define TG3_RX_JMB_RING_SIZE(tp)        256
 107 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 108 #define TG3_RSS_INDIR_TBL_SIZE          128
 109
 110 /* Do not place this n-ring entries value into the tp struct itself,
 111  * we really want to expose these constants to GCC so that modulo et
 112  * al.  operations are done with shifts and masks instead of with
 113  * hw multiply/modulo instructions.  Another solution would be to
 114  * replace things like '% foo' with '& (foo - 1)'.
 115  */
 116 #define TG3_RX_RCB_RING_SIZE(tp)        \
 117         (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
 118           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
 119
 120 #define TG3_TX_RING_SIZE                512
 121 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 122
 123 #define TG3_RX_STD_RING_BYTES(tp) \
 124         (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
 125 #define TG3_RX_JMB_RING_BYTES(tp) \
 126         (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
 127 #define TG3_RX_RCB_RING_BYTES(tp) \
 128         (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_RCB_RING_SIZE(tp))
 129 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 130                                  TG3_TX_RING_SIZE)
 131 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 132
 133 #define TG3_RX_DMA_ALIGN                16
 134 #define TG3_RX_HEADROOM                 ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
 135
 136 #define TG3_DMA_BYTE_ENAB               64
 137
 138 #define TG3_RX_STD_DMA_SZ               1536
 139 #define TG3_RX_JMB_DMA_SZ               9046
 140
 141 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 142
 143 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 144 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 145
 146 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
 147         (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
 148
 149 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
 150         (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
 151
 152 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
 153  * that are at least dword aligned when used in PCIX mode.  The driver
 154  * works around this bug by double copying the packet.  This workaround
 155  * is built into the normal double copy length check for efficiency.
 156  *
 157  * However, the double copy is only necessary on those architectures
 158  * where unaligned memory accesses are inefficient.  For those architectures
 159  * where unaligned memory accesses incur little penalty, we can reintegrate
 160  * the 5701 in the normal rx path.  Doing so saves a device structure
 161  * dereference by hardcoding the double copy threshold in place.
 162  */
 163 #define TG3_RX_COPY_THRESHOLD           256
 164 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
 165         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
 166 #else
 167         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
 168 #endif
 169
 170 /* minimum number of free TX descriptors required to wake up TX process */
 171 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 172
 173 #define TG3_RAW_IP_ALIGN 2
 174
 175 /* number of ETHTOOL_GSTATS u64's */
 176 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 177
 178 #define TG3_NUM_TEST            6
 179
 180 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
 181
 182 #define FIRMWARE_TG3            "tigon/tg3.bin"
 183 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 184 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 185
 186 static char version[] __devinitdata =
 187         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
 188
 189 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 190 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 191 MODULE_LICENSE("GPL");
 192 MODULE_VERSION(DRV_MODULE_VERSION);
 193 MODULE_FIRMWARE(FIRMWARE_TG3);
 194 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 195 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 196
 197 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 198 module_param(tg3_debug, int, 0);
 199 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 200
 201 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 255         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 256         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 257         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 258         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 259         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 260         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 261         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 262         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 263         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 264         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 265         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
 266         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
 267         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
 268         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
 269         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
 270         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
 271         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
 272         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
 273         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
 274         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 275         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 276         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 277         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 278         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 279         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 280         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 281         {}
 282 };
 283
 284 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 285
 286 static const struct {
 287         const char string[ETH_GSTRING_LEN];
 288 } ethtool_stats_keys[TG3_NUM_STATS] = {
 289         { "rx_octets" },
 290         { "rx_fragments" },
 291         { "rx_ucast_packets" },
 292         { "rx_mcast_packets" },
 293         { "rx_bcast_packets" },
 294         { "rx_fcs_errors" },
 295         { "rx_align_errors" },
 296         { "rx_xon_pause_rcvd" },
 297         { "rx_xoff_pause_rcvd" },
 298         { "rx_mac_ctrl_rcvd" },
 299         { "rx_xoff_entered" },
 300         { "rx_frame_too_long_errors" },
 301         { "rx_jabbers" },
 302         { "rx_undersize_packets" },
 303         { "rx_in_length_errors" },
 304         { "rx_out_length_errors" },
 305         { "rx_64_or_less_octet_packets" },
 306         { "rx_65_to_127_octet_packets" },
 307         { "rx_128_to_255_octet_packets" },
 308         { "rx_256_to_511_octet_packets" },
 309         { "rx_512_to_1023_octet_packets" },
 310         { "rx_1024_to_1522_octet_packets" },
 311         { "rx_1523_to_2047_octet_packets" },
 312         { "rx_2048_to_4095_octet_packets" },
 313         { "rx_4096_to_8191_octet_packets" },
 314         { "rx_8192_to_9022_octet_packets" },
 315
 316         { "tx_octets" },
 317         { "tx_collisions" },
 318
 319         { "tx_xon_sent" },
 320         { "tx_xoff_sent" },
 321         { "tx_flow_control" },
 322         { "tx_mac_errors" },
 323         { "tx_single_collisions" },
 324         { "tx_mult_collisions" },
 325         { "tx_deferred" },
 326         { "tx_excessive_collisions" },
 327         { "tx_late_collisions" },
 328         { "tx_collide_2times" },
 329         { "tx_collide_3times" },
 330         { "tx_collide_4times" },
 331         { "tx_collide_5times" },
 332         { "tx_collide_6times" },
 333         { "tx_collide_7times" },
 334         { "tx_collide_8times" },
 335         { "tx_collide_9times" },
 336         { "tx_collide_10times" },
 337         { "tx_collide_11times" },
 338         { "tx_collide_12times" },
 339         { "tx_collide_13times" },
 340         { "tx_collide_14times" },
 341         { "tx_collide_15times" },
 342         { "tx_ucast_packets" },
 343         { "tx_mcast_packets" },
 344         { "tx_bcast_packets" },
 345         { "tx_carrier_sense_errors" },
 346         { "tx_discards" },
 347         { "tx_errors" },
 348
 349         { "dma_writeq_full" },
 350         { "dma_write_prioq_full" },
 351         { "rxbds_empty" },
 352         { "rx_discards" },
 353         { "rx_errors" },
 354         { "rx_threshold_hit" },
 355
 356         { "dma_readq_full" },
 357         { "dma_read_prioq_full" },
 358         { "tx_comp_queue_full" },
 359
 360         { "ring_set_send_prod_index" },
 361         { "ring_status_update" },
 362         { "nic_irqs" },
 363         { "nic_avoided_irqs" },
 364         { "nic_tx_threshold_hit" }
 365 };
 366
 367 static const struct {
 368         const char string[ETH_GSTRING_LEN];
 369 } ethtool_test_keys[TG3_NUM_TEST] = {
 370         { "nvram test     (online) " },
 371         { "link test      (online) " },
 372         { "register test  (offline)" },
 373         { "memory test    (offline)" },
 374         { "loopback test  (offline)" },
 375         { "interrupt test (offline)" },
 376 };
 377
 378 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 379 {
 380         writel(val, tp->regs + off);
 381 }
 382
 383 static u32 tg3_read32(struct tg3 *tp, u32 off)
 384 {
 385         return readl(tp->regs + off);
 386 }
 387
 388 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 389 {
 390         writel(val, tp->aperegs + off);
 391 }
 392
 393 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 394 {
 395         return readl(tp->aperegs + off);
 396 }
 397
 398 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 399 {
 400         unsigned long flags;
 401
 402         spin_lock_irqsave(&tp->indirect_lock, flags);
 403         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 404         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 405         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 406 }
 407
 408 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 409 {
 410         writel(val, tp->regs + off);
 411         readl(tp->regs + off);
 412 }
 413
 414 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 415 {
 416         unsigned long flags;
 417         u32 val;
 418
 419         spin_lock_irqsave(&tp->indirect_lock, flags);
 420         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 421         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 422         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 423         return val;
 424 }
 425
 426 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 427 {
 428         unsigned long flags;
 429
 430         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 431                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 432                                        TG3_64BIT_REG_LOW, val);
 433                 return;
 434         }
 435         if (off == TG3_RX_STD_PROD_IDX_REG) {
 436                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 437                                        TG3_64BIT_REG_LOW, val);
 438                 return;
 439         }
 440
 441         spin_lock_irqsave(&tp->indirect_lock, flags);
 442         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 443         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 444         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 445
 446         /* In indirect mode when disabling interrupts, we also need
 447          * to clear the interrupt bit in the GRC local ctrl register.
 448          */
 449         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 450             (val == 0x1)) {
 451                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 452                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 453         }
 454 }
 455
 456 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 457 {
 458         unsigned long flags;
 459         u32 val;
 460
 461         spin_lock_irqsave(&tp->indirect_lock, flags);
 462         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 463         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 464         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 465         return val;
 466 }
 467
 468 /* usec_wait specifies the wait time in usec when writing to certain registers
 469  * where it is unsafe to read back the register without some delay.
 470  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 471  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 472  */
 473 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 474 {
 475         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 476             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 477                 /* Non-posted methods */
 478                 tp->write32(tp, off, val);
 479         else {
 480                 /* Posted method */
 481                 tg3_write32(tp, off, val);
 482                 if (usec_wait)
 483                         udelay(usec_wait);
 484                 tp->read32(tp, off);
 485         }
 486         /* Wait again after the read for the posted method to guarantee that
 487          * the wait time is met.
 488          */
 489         if (usec_wait)
 490                 udelay(usec_wait);
 491 }
 492
 493 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 494 {
 495         tp->write32_mbox(tp, off, val);
 496         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 497             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 498                 tp->read32_mbox(tp, off);
 499 }
 500
 501 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 502 {
 503         void __iomem *mbox = tp->regs + off;
 504         writel(val, mbox);
 505         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 506                 writel(val, mbox);
 507         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 508                 readl(mbox);
 509 }
 510
 511 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 512 {
 513         return readl(tp->regs + off + GRCMBOX_BASE);
 514 }
 515
 516 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 517 {
 518         writel(val, tp->regs + off + GRCMBOX_BASE);
 519 }
 520
 521 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
 522 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 523 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
 524 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
 525 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
 526
 527 #define tw32(reg, val)                  tp->write32(tp, reg, val)
 528 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
 529 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
 530 #define tr32(reg)                       tp->read32(tp, reg)
 531
 532 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 533 {
 534         unsigned long flags;
 535
 536         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 537             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 538                 return;
 539
 540         spin_lock_irqsave(&tp->indirect_lock, flags);
 541         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 542                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 543                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 544
 545                 /* Always leave this as zero. */
 546                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 547         } else {
 548                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 549                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 550
 551                 /* Always leave this as zero. */
 552                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 553         }
 554         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 555 }
 556
 557 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 558 {
 559         unsigned long flags;
 560
 561         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 562             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 563                 *val = 0;
 564                 return;
 565         }
 566
 567         spin_lock_irqsave(&tp->indirect_lock, flags);
 568         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 569                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 570                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 571
 572                 /* Always leave this as zero. */
 573                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 574         } else {
 575                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 576                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 577
 578                 /* Always leave this as zero. */
 579                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 580         }
 581         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 582 }
 583
 584 static void tg3_ape_lock_init(struct tg3 *tp)
 585 {
 586         int i;
 587         u32 regbase;
 588
 589         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 590                 regbase = TG3_APE_LOCK_GRANT;
 591         else
 592                 regbase = TG3_APE_PER_LOCK_GRANT;
 593
 594         /* Make sure the driver hasn't any stale locks. */
 595         for (i = 0; i < 8; i++)
 596                 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
 597 }
 598
 599 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 600 {
 601         int i, off;
 602         int ret = 0;
 603         u32 status, req, gnt;
 604
 605         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 606                 return 0;
 607
 608         switch (locknum) {
 609         case TG3_APE_LOCK_GRC:
 610         case TG3_APE_LOCK_MEM:
 611                 break;
 612         default:
 613                 return -EINVAL;
 614         }
 615
 616         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
 617                 req = TG3_APE_LOCK_REQ;
 618                 gnt = TG3_APE_LOCK_GRANT;
 619         } else {
 620                 req = TG3_APE_PER_LOCK_REQ;
 621                 gnt = TG3_APE_PER_LOCK_GRANT;
 622         }
 623
 624         off = 4 * locknum;
 625
 626         tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
 627
 628         /* Wait for up to 1 millisecond to acquire lock. */
 629         for (i = 0; i < 100; i++) {
 630                 status = tg3_ape_read32(tp, gnt + off);
 631                 if (status == APE_LOCK_GRANT_DRIVER)
 632                         break;
 633                 udelay(10);
 634         }
 635
 636         if (status != APE_LOCK_GRANT_DRIVER) {
 637                 /* Revoke the lock request. */
 638                 tg3_ape_write32(tp, gnt + off,
 639                                 APE_LOCK_GRANT_DRIVER);
 640
 641                 ret = -EBUSY;
 642         }
 643
 644         return ret;
 645 }
 646
 647 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 648 {
 649         u32 gnt;
 650
 651         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 652                 return;
 653
 654         switch (locknum) {
 655         case TG3_APE_LOCK_GRC:
 656         case TG3_APE_LOCK_MEM:
 657                 break;
 658         default:
 659                 return;
 660         }
 661
 662         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 663                 gnt = TG3_APE_LOCK_GRANT;
 664         else
 665                 gnt = TG3_APE_PER_LOCK_GRANT;
 666
 667         tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
 668 }
 669
 670 static void tg3_disable_ints(struct tg3 *tp)
 671 {
 672         int i;
 673
 674         tw32(TG3PCI_MISC_HOST_CTRL,
 675              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 676         for (i = 0; i < tp->irq_max; i++)
 677                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 678 }
 679
 680 static void tg3_enable_ints(struct tg3 *tp)
 681 {
 682         int i;
 683
 684         tp->irq_sync = 0;
 685         wmb();
 686
 687         tw32(TG3PCI_MISC_HOST_CTRL,
 688              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 689
 690         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
 691         for (i = 0; i < tp->irq_cnt; i++) {
 692                 struct tg3_napi *tnapi = &tp->napi[i];
 693
 694                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 695                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 696                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 697
 698                 tp->coal_now |= tnapi->coal_now;
 699         }
 700
 701         /* Force an initial interrupt */
 702         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 703             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 704                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 705         else
 706                 tw32(HOSTCC_MODE, tp->coal_now);
 707
 708         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
 709 }
 710
 711 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 712 {
 713         struct tg3 *tp = tnapi->tp;
 714         struct tg3_hw_status *sblk = tnapi->hw_status;
 715         unsigned int work_exists = 0;
 716
 717         /* check for phy events */
 718         if (!(tp->tg3_flags &
 719               (TG3_FLAG_USE_LINKCHG_REG |
 720                TG3_FLAG_POLL_SERDES))) {
 721                 if (sblk->status & SD_STATUS_LINK_CHG)
 722                         work_exists = 1;
 723         }
 724         /* check for RX/TX work to do */
 725         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 726             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
 727                 work_exists = 1;
 728
 729         return work_exists;
 730 }
 731
 732 /* tg3_int_reenable
 733  *  similar to tg3_enable_ints, but it accurately determines whether there
 734  *  is new work pending and can return without flushing the PIO write
 735  *  which reenables interrupts
 736  */
 737 static void tg3_int_reenable(struct tg3_napi *tnapi)
 738 {
 739         struct tg3 *tp = tnapi->tp;
 740
 741         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 742         mmiowb();
 743
 744         /* When doing tagged status, this work check is unnecessary.
 745          * The last_tag we write above tells the chip which piece of
 746          * work we've completed.
 747          */
 748         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 749             tg3_has_work(tnapi))
 750                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 751                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 752 }
 753
 754 static void tg3_switch_clocks(struct tg3 *tp)
 755 {
 756         u32 clock_ctrl;
 757         u32 orig_clock_ctrl;
 758
 759         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 760             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 761                 return;
 762
 763         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 764
 765         orig_clock_ctrl = clock_ctrl;
 766         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 767                        CLOCK_CTRL_CLKRUN_OENABLE |
 768                        0x1f);
 769         tp->pci_clock_ctrl = clock_ctrl;
 770
 771         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 772                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 773                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 774                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 775                 }
 776         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 777                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 778                             clock_ctrl |
 779                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 780                             40);
 781                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 782                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 783                             40);
 784         }
 785         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 786 }
 787
 788 #define PHY_BUSY_LOOPS  5000
 789
 790 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 791 {
 792         u32 frame_val;
 793         unsigned int loops;
 794         int ret;
 795
 796         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 797                 tw32_f(MAC_MI_MODE,
 798                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 799                 udelay(80);
 800         }
 801
 802         *val = 0x0;
 803
 804         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 805                       MI_COM_PHY_ADDR_MASK);
 806         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 807                       MI_COM_REG_ADDR_MASK);
 808         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 809
 810         tw32_f(MAC_MI_COM, frame_val);
 811
 812         loops = PHY_BUSY_LOOPS;
 813         while (loops != 0) {
 814                 udelay(10);
 815                 frame_val = tr32(MAC_MI_COM);
 816
 817                 if ((frame_val & MI_COM_BUSY) == 0) {
 818                         udelay(5);
 819                         frame_val = tr32(MAC_MI_COM);
 820                         break;
 821                 }
 822                 loops -= 1;
 823         }
 824
 825         ret = -EBUSY;
 826         if (loops != 0) {
 827                 *val = frame_val & MI_COM_DATA_MASK;
 828                 ret = 0;
 829         }
 830
 831         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 832                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 833                 udelay(80);
 834         }
 835
 836         return ret;
 837 }
 838
 839 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 840 {
 841         u32 frame_val;
 842         unsigned int loops;
 843         int ret;
 844
 845         if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
 846             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 847                 return 0;
 848
 849         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 850                 tw32_f(MAC_MI_MODE,
 851                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 852                 udelay(80);
 853         }
 854
 855         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 856                       MI_COM_PHY_ADDR_MASK);
 857         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 858                       MI_COM_REG_ADDR_MASK);
 859         frame_val |= (val & MI_COM_DATA_MASK);
 860         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 861
 862         tw32_f(MAC_MI_COM, frame_val);
 863
 864         loops = PHY_BUSY_LOOPS;
 865         while (loops != 0) {
 866                 udelay(10);
 867                 frame_val = tr32(MAC_MI_COM);
 868                 if ((frame_val & MI_COM_BUSY) == 0) {
 869                         udelay(5);
 870                         frame_val = tr32(MAC_MI_COM);
 871                         break;
 872                 }
 873                 loops -= 1;
 874         }
 875
 876         ret = -EBUSY;
 877         if (loops != 0)
 878                 ret = 0;
 879
 880         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 881                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 882                 udelay(80);
 883         }
 884
 885         return ret;
 886 }
 887
 888 static int tg3_bmcr_reset(struct tg3 *tp)
 889 {
 890         u32 phy_control;
 891         int limit, err;
 892
 893         /* OK, reset it, and poll the BMCR_RESET bit until it
 894          * clears or we time out.
 895          */
 896         phy_control = BMCR_RESET;
 897         err = tg3_writephy(tp, MII_BMCR, phy_control);
 898         if (err != 0)
 899                 return -EBUSY;
 900
 901         limit = 5000;
 902         while (limit--) {
 903                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 904                 if (err != 0)
 905                         return -EBUSY;
 906
 907                 if ((phy_control & BMCR_RESET) == 0) {
 908                         udelay(40);
 909                         break;
 910                 }
 911                 udelay(10);
 912         }
 913         if (limit < 0)
 914                 return -EBUSY;
 915
 916         return 0;
 917 }
 918
 919 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 920 {
 921         struct tg3 *tp = bp->priv;
 922         u32 val;
 923
 924         spin_lock_bh(&tp->lock);
 925
 926         if (tg3_readphy(tp, reg, &val))
 927                 val = -EIO;
 928
 929         spin_unlock_bh(&tp->lock);
 930
 931         return val;
 932 }
 933
 934 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 935 {
 936         struct tg3 *tp = bp->priv;
 937         u32 ret = 0;
 938
 939         spin_lock_bh(&tp->lock);
 940
 941         if (tg3_writephy(tp, reg, val))
 942                 ret = -EIO;
 943
 944         spin_unlock_bh(&tp->lock);
 945
 946         return ret;
 947 }
 948
 949 static int tg3_mdio_reset(struct mii_bus *bp)
 950 {
 951         return 0;
 952 }
 953
 954 static void tg3_mdio_config_5785(struct tg3 *tp)
 955 {
 956         u32 val;
 957         struct phy_device *phydev;
 958
 959         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
 960         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 961         case PHY_ID_BCM50610:
 962         case PHY_ID_BCM50610M:
 963                 val = MAC_PHYCFG2_50610_LED_MODES;
 964                 break;
 965         case PHY_ID_BCMAC131:
 966                 val = MAC_PHYCFG2_AC131_LED_MODES;
 967                 break;
 968         case PHY_ID_RTL8211C:
 969                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
 970                 break;
 971         case PHY_ID_RTL8201E:
 972                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
 973                 break;
 974         default:
 975                 return;
 976         }
 977
 978         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
 979                 tw32(MAC_PHYCFG2, val);
 980
 981                 val = tr32(MAC_PHYCFG1);
 982                 val &= ~(MAC_PHYCFG1_RGMII_INT |
 983                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
 984                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
 985                 tw32(MAC_PHYCFG1, val);
 986
 987                 return;
 988         }
 989
 990         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
 991                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
 992                        MAC_PHYCFG2_FMODE_MASK_MASK |
 993                        MAC_PHYCFG2_GMODE_MASK_MASK |
 994                        MAC_PHYCFG2_ACT_MASK_MASK   |
 995                        MAC_PHYCFG2_QUAL_MASK_MASK |
 996                        MAC_PHYCFG2_INBAND_ENABLE;
 997
 998         tw32(MAC_PHYCFG2, val);
 999
1000         val = tr32(MAC_PHYCFG1);
1001         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1002                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1003         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1004                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1005                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1006                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1007                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1008         }
1009         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1010                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1011         tw32(MAC_PHYCFG1, val);
1012
1013         val = tr32(MAC_EXT_RGMII_MODE);
1014         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1015                  MAC_RGMII_MODE_RX_QUALITY |
1016                  MAC_RGMII_MODE_RX_ACTIVITY |
1017                  MAC_RGMII_MODE_RX_ENG_DET |
1018                  MAC_RGMII_MODE_TX_ENABLE |
1019                  MAC_RGMII_MODE_TX_LOWPWR |
1020                  MAC_RGMII_MODE_TX_RESET);
1021         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1022                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1023                         val |= MAC_RGMII_MODE_RX_INT_B |
1024                                MAC_RGMII_MODE_RX_QUALITY |
1025                                MAC_RGMII_MODE_RX_ACTIVITY |
1026                                MAC_RGMII_MODE_RX_ENG_DET;
1027                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1028                         val |= MAC_RGMII_MODE_TX_ENABLE |
1029                                MAC_RGMII_MODE_TX_LOWPWR |
1030                                MAC_RGMII_MODE_TX_RESET;
1031         }
1032         tw32(MAC_EXT_RGMII_MODE, val);
1033 }
1034
1035 static void tg3_mdio_start(struct tg3 *tp)
1036 {
1037         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1038         tw32_f(MAC_MI_MODE, tp->mi_mode);
1039         udelay(80);
1040
1041         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1042             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1043                 tg3_mdio_config_5785(tp);
1044 }
1045
1046 static int tg3_mdio_init(struct tg3 *tp)
1047 {
1048         int i;
1049         u32 reg;
1050         struct phy_device *phydev;
1051
1052         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1053             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
1054                 u32 is_serdes;
1055
1056                 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1057
1058                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1059                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1060                 else
1061                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1062                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1063                 if (is_serdes)
1064                         tp->phy_addr += 7;
1065         } else
1066                 tp->phy_addr = TG3_PHY_MII_ADDR;
1067
1068         tg3_mdio_start(tp);
1069
1070         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1071             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1072                 return 0;
1073
1074         tp->mdio_bus = mdiobus_alloc();
1075         if (tp->mdio_bus == NULL)
1076                 return -ENOMEM;
1077
1078         tp->mdio_bus->name     = "tg3 mdio bus";
1079         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1080                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1081         tp->mdio_bus->priv     = tp;
1082         tp->mdio_bus->parent   = &tp->pdev->dev;
1083         tp->mdio_bus->read     = &tg3_mdio_read;
1084         tp->mdio_bus->write    = &tg3_mdio_write;
1085         tp->mdio_bus->reset    = &tg3_mdio_reset;
1086         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1087         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1088
1089         for (i = 0; i < PHY_MAX_ADDR; i++)
1090                 tp->mdio_bus->irq[i] = PHY_POLL;
1091
1092         /* The bus registration will look for all the PHYs on the mdio bus.
1093          * Unfortunately, it does not ensure the PHY is powered up before
1094          * accessing the PHY ID registers.  A chip reset is the
1095          * quickest way to bring the device back to an operational state..
1096          */
1097         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1098                 tg3_bmcr_reset(tp);
1099
1100         i = mdiobus_register(tp->mdio_bus);
1101         if (i) {
1102                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1103                 mdiobus_free(tp->mdio_bus);
1104                 return i;
1105         }
1106
1107         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1108
1109         if (!phydev || !phydev->drv) {
1110                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1111                 mdiobus_unregister(tp->mdio_bus);
1112                 mdiobus_free(tp->mdio_bus);
1113                 return -ENODEV;
1114         }
1115
1116         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1117         case PHY_ID_BCM57780:
1118                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1119                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1120                 break;
1121         case PHY_ID_BCM50610:
1122         case PHY_ID_BCM50610M:
1123                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1124                                      PHY_BRCM_RX_REFCLK_UNUSED |
1125                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1126                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1127                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1128                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1129                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1130                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1131                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1132                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1133                 /* fallthru */
1134         case PHY_ID_RTL8211C:
1135                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1136                 break;
1137         case PHY_ID_RTL8201E:
1138         case PHY_ID_BCMAC131:
1139                 phydev->interface = PHY_INTERFACE_MODE_MII;
1140                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1141                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1142                 break;
1143         }
1144
1145         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1146
1147         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1148                 tg3_mdio_config_5785(tp);
1149
1150         return 0;
1151 }
1152
1153 static void tg3_mdio_fini(struct tg3 *tp)
1154 {
1155         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1156                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1157                 mdiobus_unregister(tp->mdio_bus);
1158                 mdiobus_free(tp->mdio_bus);
1159         }
1160 }
1161
1162 /* tp->lock is held. */
1163 static inline void tg3_generate_fw_event(struct tg3 *tp)
1164 {
1165         u32 val;
1166
1167         val = tr32(GRC_RX_CPU_EVENT);
1168         val |= GRC_RX_CPU_DRIVER_EVENT;
1169         tw32_f(GRC_RX_CPU_EVENT, val);
1170
1171         tp->last_event_jiffies = jiffies;
1172 }
1173
1174 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1175
1176 /* tp->lock is held. */
1177 static void tg3_wait_for_event_ack(struct tg3 *tp)
1178 {
1179         int i;
1180         unsigned int delay_cnt;
1181         long time_remain;
1182
1183         /* If enough time has passed, no wait is necessary. */
1184         time_remain = (long)(tp->last_event_jiffies + 1 +
1185                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1186                       (long)jiffies;
1187         if (time_remain < 0)
1188                 return;
1189
1190         /* Check if we can shorten the wait time. */
1191         delay_cnt = jiffies_to_usecs(time_remain);
1192         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1193                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1194         delay_cnt = (delay_cnt >> 3) + 1;
1195
1196         for (i = 0; i < delay_cnt; i++) {
1197                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1198                         break;
1199                 udelay(8);
1200         }
1201 }
1202
1203 /* tp->lock is held. */
1204 static void tg3_ump_link_report(struct tg3 *tp)
1205 {
1206         u32 reg;
1207         u32 val;
1208
1209         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1210             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1211                 return;
1212
1213         tg3_wait_for_event_ack(tp);
1214
1215         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1216
1217         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1218
1219         val = 0;
1220         if (!tg3_readphy(tp, MII_BMCR, &reg))
1221                 val = reg << 16;
1222         if (!tg3_readphy(tp, MII_BMSR, &reg))
1223                 val |= (reg & 0xffff);
1224         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1225
1226         val = 0;
1227         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1228                 val = reg << 16;
1229         if (!tg3_readphy(tp, MII_LPA, &reg))
1230                 val |= (reg & 0xffff);
1231         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1232
1233         val = 0;
1234         if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1235                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1236                         val = reg << 16;
1237                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1238                         val |= (reg & 0xffff);
1239         }
1240         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1241
1242         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1243                 val = reg << 16;
1244         else
1245                 val = 0;
1246         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1247
1248         tg3_generate_fw_event(tp);
1249 }
1250
1251 static void tg3_link_report(struct tg3 *tp)
1252 {
1253         if (!netif_carrier_ok(tp->dev)) {
1254                 netif_info(tp, link, tp->dev, "Link is down\n");
1255                 tg3_ump_link_report(tp);
1256         } else if (netif_msg_link(tp)) {
1257                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1258                             (tp->link_config.active_speed == SPEED_1000 ?
1259                              1000 :
1260                              (tp->link_config.active_speed == SPEED_100 ?
1261                               100 : 10)),
1262                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1263                              "full" : "half"));
1264
1265                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1266                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1267                             "on" : "off",
1268                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1269                             "on" : "off");
1270                 tg3_ump_link_report(tp);
1271         }
1272 }
1273
1274 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1275 {
1276         u16 miireg;
1277
1278         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1279                 miireg = ADVERTISE_PAUSE_CAP;
1280         else if (flow_ctrl & FLOW_CTRL_TX)
1281                 miireg = ADVERTISE_PAUSE_ASYM;
1282         else if (flow_ctrl & FLOW_CTRL_RX)
1283                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1284         else
1285                 miireg = 0;
1286
1287         return miireg;
1288 }
1289
1290 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1291 {
1292         u16 miireg;
1293
1294         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1295                 miireg = ADVERTISE_1000XPAUSE;
1296         else if (flow_ctrl & FLOW_CTRL_TX)
1297                 miireg = ADVERTISE_1000XPSE_ASYM;
1298         else if (flow_ctrl & FLOW_CTRL_RX)
1299                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1300         else
1301                 miireg = 0;
1302
1303         return miireg;
1304 }
1305
1306 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1307 {
1308         u8 cap = 0;
1309
1310         if (lcladv & ADVERTISE_1000XPAUSE) {
1311                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1312                         if (rmtadv & LPA_1000XPAUSE)
1313                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1314                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1315                                 cap = FLOW_CTRL_RX;
1316                 } else {
1317                         if (rmtadv & LPA_1000XPAUSE)
1318                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1319                 }
1320         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1321                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1322                         cap = FLOW_CTRL_TX;
1323         }
1324
1325         return cap;
1326 }
1327
1328 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1329 {
1330         u8 autoneg;
1331         u8 flowctrl = 0;
1332         u32 old_rx_mode = tp->rx_mode;
1333         u32 old_tx_mode = tp->tx_mode;
1334
1335         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1336                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1337         else
1338                 autoneg = tp->link_config.autoneg;
1339
1340         if (autoneg == AUTONEG_ENABLE &&
1341             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1342                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1343                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1344                 else
1345                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1346         } else
1347                 flowctrl = tp->link_config.flowctrl;
1348
1349         tp->link_config.active_flowctrl = flowctrl;
1350
1351         if (flowctrl & FLOW_CTRL_RX)
1352                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1353         else
1354                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1355
1356         if (old_rx_mode != tp->rx_mode)
1357                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1358
1359         if (flowctrl & FLOW_CTRL_TX)
1360                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1361         else
1362                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1363
1364         if (old_tx_mode != tp->tx_mode)
1365                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1366 }
1367
1368 static void tg3_adjust_link(struct net_device *dev)
1369 {
1370         u8 oldflowctrl, linkmesg = 0;
1371         u32 mac_mode, lcl_adv, rmt_adv;
1372         struct tg3 *tp = netdev_priv(dev);
1373         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1374
1375         spin_lock_bh(&tp->lock);
1376
1377         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1378                                     MAC_MODE_HALF_DUPLEX);
1379
1380         oldflowctrl = tp->link_config.active_flowctrl;
1381
1382         if (phydev->link) {
1383                 lcl_adv = 0;
1384                 rmt_adv = 0;
1385
1386                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1387                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1388                 else if (phydev->speed == SPEED_1000 ||
1389                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1390                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1391                 else
1392                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1393
1394                 if (phydev->duplex == DUPLEX_HALF)
1395                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1396                 else {
1397                         lcl_adv = tg3_advert_flowctrl_1000T(
1398                                   tp->link_config.flowctrl);
1399
1400                         if (phydev->pause)
1401                                 rmt_adv = LPA_PAUSE_CAP;
1402                         if (phydev->asym_pause)
1403                                 rmt_adv |= LPA_PAUSE_ASYM;
1404                 }
1405
1406                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1407         } else
1408                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1409
1410         if (mac_mode != tp->mac_mode) {
1411                 tp->mac_mode = mac_mode;
1412                 tw32_f(MAC_MODE, tp->mac_mode);
1413                 udelay(40);
1414         }
1415
1416         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1417                 if (phydev->speed == SPEED_10)
1418                         tw32(MAC_MI_STAT,
1419                              MAC_MI_STAT_10MBPS_MODE |
1420                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1421                 else
1422                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1423         }
1424
1425         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1426                 tw32(MAC_TX_LENGTHS,
1427                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1428                       (6 << TX_LENGTHS_IPG_SHIFT) |
1429                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1430         else
1431                 tw32(MAC_TX_LENGTHS,
1432                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1433                       (6 << TX_LENGTHS_IPG_SHIFT) |
1434                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1435
1436         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1437             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1438             phydev->speed != tp->link_config.active_speed ||
1439             phydev->duplex != tp->link_config.active_duplex ||
1440             oldflowctrl != tp->link_config.active_flowctrl)
1441                 linkmesg = 1;
1442
1443         tp->link_config.active_speed = phydev->speed;
1444         tp->link_config.active_duplex = phydev->duplex;
1445
1446         spin_unlock_bh(&tp->lock);
1447
1448         if (linkmesg)
1449                 tg3_link_report(tp);
1450 }
1451
1452 static int tg3_phy_init(struct tg3 *tp)
1453 {
1454         struct phy_device *phydev;
1455
1456         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1457                 return 0;
1458
1459         /* Bring the PHY back to a known state. */
1460         tg3_bmcr_reset(tp);
1461
1462         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1463
1464         /* Attach the MAC to the PHY. */
1465         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1466                              phydev->dev_flags, phydev->interface);
1467         if (IS_ERR(phydev)) {
1468                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1469                 return PTR_ERR(phydev);
1470         }
1471
1472         /* Mask with MAC supported features. */
1473         switch (phydev->interface) {
1474         case PHY_INTERFACE_MODE_GMII:
1475         case PHY_INTERFACE_MODE_RGMII:
1476                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1477                         phydev->supported &= (PHY_GBIT_FEATURES |
1478                                               SUPPORTED_Pause |
1479                                               SUPPORTED_Asym_Pause);
1480                         break;
1481                 }
1482                 /* fallthru */
1483         case PHY_INTERFACE_MODE_MII:
1484                 phydev->supported &= (PHY_BASIC_FEATURES |
1485                                       SUPPORTED_Pause |
1486                                       SUPPORTED_Asym_Pause);
1487                 break;
1488         default:
1489                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1490                 return -EINVAL;
1491         }
1492
1493         tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1494
1495         phydev->advertising = phydev->supported;
1496
1497         return 0;
1498 }
1499
1500 static void tg3_phy_start(struct tg3 *tp)
1501 {
1502         struct phy_device *phydev;
1503
1504         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1505                 return;
1506
1507         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1508
1509         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1510                 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1511                 phydev->speed = tp->link_config.orig_speed;
1512                 phydev->duplex = tp->link_config.orig_duplex;
1513                 phydev->autoneg = tp->link_config.orig_autoneg;
1514                 phydev->advertising = tp->link_config.orig_advertising;
1515         }
1516
1517         phy_start(phydev);
1518
1519         phy_start_aneg(phydev);
1520 }
1521
1522 static void tg3_phy_stop(struct tg3 *tp)
1523 {
1524         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1525                 return;
1526
1527         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1528 }
1529
1530 static void tg3_phy_fini(struct tg3 *tp)
1531 {
1532         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1533                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1534                 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1535         }
1536 }
1537
1538 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1539 {
1540         int err;
1541
1542         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1543         if (!err)
1544                 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1545
1546         return err;
1547 }
1548
1549 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1550 {
1551         u32 phytest;
1552
1553         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1554                 u32 phy;
1555
1556                 tg3_writephy(tp, MII_TG3_FET_TEST,
1557                              phytest | MII_TG3_FET_SHADOW_EN);
1558                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1559                         if (enable)
1560                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1561                         else
1562                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1563                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1564                 }
1565                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1566         }
1567 }
1568
1569 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1570 {
1571         u32 reg;
1572
1573         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1574             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1575               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1576              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1577                 return;
1578
1579         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1580                 tg3_phy_fet_toggle_apd(tp, enable);
1581                 return;
1582         }
1583
1584         reg = MII_TG3_MISC_SHDW_WREN |
1585               MII_TG3_MISC_SHDW_SCR5_SEL |
1586               MII_TG3_MISC_SHDW_SCR5_LPED |
1587               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1588               MII_TG3_MISC_SHDW_SCR5_SDTL |
1589               MII_TG3_MISC_SHDW_SCR5_C125OE;
1590         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1591                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1592
1593         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1594
1595
1596         reg = MII_TG3_MISC_SHDW_WREN |
1597               MII_TG3_MISC_SHDW_APD_SEL |
1598               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1599         if (enable)
1600                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1601
1602         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1603 }
1604
1605 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1606 {
1607         u32 phy;
1608
1609         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1610             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
1611                 return;
1612
1613         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1614                 u32 ephy;
1615
1616                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1617                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1618
1619                         tg3_writephy(tp, MII_TG3_FET_TEST,
1620                                      ephy | MII_TG3_FET_SHADOW_EN);
1621                         if (!tg3_readphy(tp, reg, &phy)) {
1622                                 if (enable)
1623                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1624                                 else
1625                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1626                                 tg3_writephy(tp, reg, phy);
1627                         }
1628                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1629                 }
1630         } else {
1631                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1632                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1633                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1634                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1635                         if (enable)
1636                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1637                         else
1638                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1639                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1640                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1641                 }
1642         }
1643 }
1644
1645 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1646 {
1647         u32 val;
1648
1649         if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1650                 return;
1651
1652         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1653             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1654                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1655                              (val | (1 << 15) | (1 << 4)));
1656 }
1657
1658 static void tg3_phy_apply_otp(struct tg3 *tp)
1659 {
1660         u32 otp, phy;
1661
1662         if (!tp->phy_otp)
1663                 return;
1664
1665         otp = tp->phy_otp;
1666
1667         /* Enable SM_DSP clock and tx 6dB coding. */
1668         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1669               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1670               MII_TG3_AUXCTL_ACTL_TX_6DB;
1671         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1672
1673         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1674         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1675         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1676
1677         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1678               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1679         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1680
1681         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1682         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1683         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1684
1685         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1686         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1687
1688         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1689         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1690
1691         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1692               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1693         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1694
1695         /* Turn off SM_DSP clock. */
1696         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1697               MII_TG3_AUXCTL_ACTL_TX_6DB;
1698         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1699 }
1700
1701 static int tg3_wait_macro_done(struct tg3 *tp)
1702 {
1703         int limit = 100;
1704
1705         while (limit--) {
1706                 u32 tmp32;
1707
1708                 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1709                         if ((tmp32 & 0x1000) == 0)
1710                                 break;
1711                 }
1712         }
1713         if (limit < 0)
1714                 return -EBUSY;
1715
1716         return 0;
1717 }
1718
1719 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1720 {
1721         static const u32 test_pat[4][6] = {
1722         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1723         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1724         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1725         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1726         };
1727         int chan;
1728
1729         for (chan = 0; chan < 4; chan++) {
1730                 int i;
1731
1732                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1733                              (chan * 0x2000) | 0x0200);
1734                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1735
1736                 for (i = 0; i < 6; i++)
1737                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1738                                      test_pat[chan][i]);
1739
1740                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1741                 if (tg3_wait_macro_done(tp)) {
1742                         *resetp = 1;
1743                         return -EBUSY;
1744                 }
1745
1746                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1747                              (chan * 0x2000) | 0x0200);
1748                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1749                 if (tg3_wait_macro_done(tp)) {
1750                         *resetp = 1;
1751                         return -EBUSY;
1752                 }
1753
1754                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1755                 if (tg3_wait_macro_done(tp)) {
1756                         *resetp = 1;
1757                         return -EBUSY;
1758                 }
1759
1760                 for (i = 0; i < 6; i += 2) {
1761                         u32 low, high;
1762
1763                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1764                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1765                             tg3_wait_macro_done(tp)) {
1766                                 *resetp = 1;
1767                                 return -EBUSY;
1768                         }
1769                         low &= 0x7fff;
1770                         high &= 0x000f;
1771                         if (low != test_pat[chan][i] ||
1772                             high != test_pat[chan][i+1]) {
1773                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1774                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1775                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1776
1777                                 return -EBUSY;
1778                         }
1779                 }
1780         }
1781
1782         return 0;
1783 }
1784
1785 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1786 {
1787         int chan;
1788
1789         for (chan = 0; chan < 4; chan++) {
1790                 int i;
1791
1792                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1793                              (chan * 0x2000) | 0x0200);
1794                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1795                 for (i = 0; i < 6; i++)
1796                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1797                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1798                 if (tg3_wait_macro_done(tp))
1799                         return -EBUSY;
1800         }
1801
1802         return 0;
1803 }
1804
1805 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1806 {
1807         u32 reg32, phy9_orig;
1808         int retries, do_phy_reset, err;
1809
1810         retries = 10;
1811         do_phy_reset = 1;
1812         do {
1813                 if (do_phy_reset) {
1814                         err = tg3_bmcr_reset(tp);
1815                         if (err)
1816                                 return err;
1817                         do_phy_reset = 0;
1818                 }
1819
1820                 /* Disable transmitter and interrupt.  */
1821                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1822                         continue;
1823
1824                 reg32 |= 0x3000;
1825                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1826
1827                 /* Set full-duplex, 1000 mbps.  */
1828                 tg3_writephy(tp, MII_BMCR,
1829                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1830
1831                 /* Set to master mode.  */
1832                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1833                         continue;
1834
1835                 tg3_writephy(tp, MII_TG3_CTRL,
1836                              (MII_TG3_CTRL_AS_MASTER |
1837                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1838
1839                 /* Enable SM_DSP_CLOCK and 6dB.  */
1840                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1841
1842                 /* Block the PHY control access.  */
1843                 tg3_phydsp_write(tp, 0x8005, 0x0800);
1844
1845                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1846                 if (!err)
1847                         break;
1848         } while (--retries);
1849
1850         err = tg3_phy_reset_chanpat(tp);
1851         if (err)
1852                 return err;
1853
1854         tg3_phydsp_write(tp, 0x8005, 0x0000);
1855
1856         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1857         tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1858
1859         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1860             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1861                 /* Set Extended packet length bit for jumbo frames */
1862                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1863         } else {
1864                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1865         }
1866
1867         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1868
1869         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1870                 reg32 &= ~0x3000;
1871                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1872         } else if (!err)
1873                 err = -EBUSY;
1874
1875         return err;
1876 }
1877
1878 /* This will reset the tigon3 PHY if there is no valid
1879  * link unless the FORCE argument is non-zero.
1880  */
1881 static int tg3_phy_reset(struct tg3 *tp)
1882 {
1883         u32 val, cpmuctrl;
1884         int err;
1885
1886         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1887                 val = tr32(GRC_MISC_CFG);
1888                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1889                 udelay(40);
1890         }
1891         err  = tg3_readphy(tp, MII_BMSR, &val);
1892         err |= tg3_readphy(tp, MII_BMSR, &val);
1893         if (err != 0)
1894                 return -EBUSY;
1895
1896         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1897                 netif_carrier_off(tp->dev);
1898                 tg3_link_report(tp);
1899         }
1900
1901         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1902             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1903             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1904                 err = tg3_phy_reset_5703_4_5(tp);
1905                 if (err)
1906                         return err;
1907                 goto out;
1908         }
1909
1910         cpmuctrl = 0;
1911         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1912             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1913                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1914                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1915                         tw32(TG3_CPMU_CTRL,
1916                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1917         }
1918
1919         err = tg3_bmcr_reset(tp);
1920         if (err)
1921                 return err;
1922
1923         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1924                 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1925                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
1926
1927                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1928         }
1929
1930         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1931             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1932                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1933                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1934                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1935                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1936                         udelay(40);
1937                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1938                 }
1939         }
1940
1941         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1942              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1943             (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
1944                 return 0;
1945
1946         tg3_phy_apply_otp(tp);
1947
1948         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
1949                 tg3_phy_toggle_apd(tp, true);
1950         else
1951                 tg3_phy_toggle_apd(tp, false);
1952
1953 out:
1954         if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) {
1955                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1956                 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
1957                 tg3_phydsp_write(tp, 0x000a, 0x0323);
1958                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1959         }
1960         if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
1961                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
1962                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
1963         }
1964         if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
1965                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1966                 tg3_phydsp_write(tp, 0x000a, 0x310b);
1967                 tg3_phydsp_write(tp, 0x201f, 0x9506);
1968                 tg3_phydsp_write(tp, 0x401f, 0x14e2);
1969                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1970         } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
1971                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1972                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1973                 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
1974                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1975                         tg3_writephy(tp, MII_TG3_TEST1,
1976                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1977                 } else
1978                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1979                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1980         }
1981         /* Set Extended packet length bit (bit 14) on all chips that */
1982         /* support jumbo frames */
1983         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1984                 /* Cannot do read-modify-write on 5401 */
1985                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1986         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1987                 /* Set bit 14 with read-modify-write to preserve other bits */
1988                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1989                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1990                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val | 0x4000);
1991         }
1992
1993         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1994          * jumbo frames transmission.
1995          */
1996         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1997                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
1998                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
1999                                      val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2000         }
2001
2002         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2003                 /* adjust output voltage */
2004                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2005         }
2006
2007         tg3_phy_toggle_automdix(tp, 1);
2008         tg3_phy_set_wirespeed(tp);
2009         return 0;
2010 }
2011
2012 static void tg3_frob_aux_power(struct tg3 *tp)
2013 {
2014         struct tg3 *tp_peer = tp;
2015
2016         /* The GPIOs do something completely different on 57765. */
2017         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2018             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2019             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2020                 return;
2021
2022         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2023             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2024             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2025                 struct net_device *dev_peer;
2026
2027                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2028                 /* remove_one() may have been run on the peer. */
2029                 if (!dev_peer)
2030                         tp_peer = tp;
2031                 else
2032                         tp_peer = netdev_priv(dev_peer);
2033         }
2034
2035         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2036             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2037             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2038             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2039                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2040                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2041                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2042                                     (GRC_LCLCTRL_GPIO_OE0 |
2043                                      GRC_LCLCTRL_GPIO_OE1 |
2044                                      GRC_LCLCTRL_GPIO_OE2 |
2045                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2046                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2047                                     100);
2048                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2049                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2050                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2051                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2052                                              GRC_LCLCTRL_GPIO_OE1 |
2053                                              GRC_LCLCTRL_GPIO_OE2 |
2054                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2055                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2056                                              tp->grc_local_ctrl;
2057                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2058
2059                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2060                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2061
2062                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2063                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2064                 } else {
2065                         u32 no_gpio2;
2066                         u32 grc_local_ctrl = 0;
2067
2068                         if (tp_peer != tp &&
2069                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2070                                 return;
2071
2072                         /* Workaround to prevent overdrawing Amps. */
2073                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2074                             ASIC_REV_5714) {
2075                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2076                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2077                                             grc_local_ctrl, 100);
2078                         }
2079
2080                         /* On 5753 and variants, GPIO2 cannot be used. */
2081                         no_gpio2 = tp->nic_sram_data_cfg &
2082                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2083
2084                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2085                                          GRC_LCLCTRL_GPIO_OE1 |
2086                                          GRC_LCLCTRL_GPIO_OE2 |
2087                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2088                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2089                         if (no_gpio2) {
2090                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2091                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2092                         }
2093                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2094                                                     grc_local_ctrl, 100);
2095
2096                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2097
2098                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2099                                                     grc_local_ctrl, 100);
2100
2101                         if (!no_gpio2) {
2102                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2103                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2104                                             grc_local_ctrl, 100);
2105                         }
2106                 }
2107         } else {
2108                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2109                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2110                         if (tp_peer != tp &&
2111                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2112                                 return;
2113
2114                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2115                                     (GRC_LCLCTRL_GPIO_OE1 |
2116                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2117
2118                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2119                                     GRC_LCLCTRL_GPIO_OE1, 100);
2120
2121                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2122                                     (GRC_LCLCTRL_GPIO_OE1 |
2123                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2124                 }
2125         }
2126 }
2127
2128 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2129 {
2130         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2131                 return 1;
2132         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2133                 if (speed != SPEED_10)
2134                         return 1;
2135         } else if (speed == SPEED_10)
2136                 return 1;
2137
2138         return 0;
2139 }
2140
2141 static int tg3_setup_phy(struct tg3 *, int);
2142
2143 #define RESET_KIND_SHUTDOWN     0
2144 #define RESET_KIND_INIT         1
2145 #define RESET_KIND_SUSPEND      2
2146
2147 static void tg3_write_sig_post_reset(struct tg3 *, int);
2148 static int tg3_halt_cpu(struct tg3 *, u32);
2149
2150 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2151 {
2152         u32 val;
2153
2154         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2155                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2156                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2157                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2158
2159                         sg_dig_ctrl |=
2160                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2161                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2162                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2163                 }
2164                 return;
2165         }
2166
2167         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2168                 tg3_bmcr_reset(tp);
2169                 val = tr32(GRC_MISC_CFG);
2170                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2171                 udelay(40);
2172                 return;
2173         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2174                 u32 phytest;
2175                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2176                         u32 phy;
2177
2178                         tg3_writephy(tp, MII_ADVERTISE, 0);
2179                         tg3_writephy(tp, MII_BMCR,
2180                                      BMCR_ANENABLE | BMCR_ANRESTART);
2181
2182                         tg3_writephy(tp, MII_TG3_FET_TEST,
2183                                      phytest | MII_TG3_FET_SHADOW_EN);
2184                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2185                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2186                                 tg3_writephy(tp,
2187                                              MII_TG3_FET_SHDW_AUXMODE4,
2188                                              phy);
2189                         }
2190                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2191                 }
2192                 return;
2193         } else if (do_low_power) {
2194                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2195                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2196
2197                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2198                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2199                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2200                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2201                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2202         }
2203
2204         /* The PHY should not be powered down on some chips because
2205          * of bugs.
2206          */
2207         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2208             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2209             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2210              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2211                 return;
2212
2213         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2214             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2215                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2216                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2217                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2218                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2219         }
2220
2221         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2222 }
2223
2224 /* tp->lock is held. */
2225 static int tg3_nvram_lock(struct tg3 *tp)
2226 {
2227         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2228                 int i;
2229
2230                 if (tp->nvram_lock_cnt == 0) {
2231                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2232                         for (i = 0; i < 8000; i++) {
2233                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2234                                         break;
2235                                 udelay(20);
2236                         }
2237                         if (i == 8000) {
2238                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2239                                 return -ENODEV;
2240                         }
2241                 }
2242                 tp->nvram_lock_cnt++;
2243         }
2244         return 0;
2245 }
2246
2247 /* tp->lock is held. */
2248 static void tg3_nvram_unlock(struct tg3 *tp)
2249 {
2250         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2251                 if (tp->nvram_lock_cnt > 0)
2252                         tp->nvram_lock_cnt--;
2253                 if (tp->nvram_lock_cnt == 0)
2254                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2255         }
2256 }
2257
2258 /* tp->lock is held. */
2259 static void tg3_enable_nvram_access(struct tg3 *tp)
2260 {
2261         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2262             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2263                 u32 nvaccess = tr32(NVRAM_ACCESS);
2264
2265                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2266         }
2267 }
2268
2269 /* tp->lock is held. */
2270 static void tg3_disable_nvram_access(struct tg3 *tp)
2271 {
2272         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2273             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2274                 u32 nvaccess = tr32(NVRAM_ACCESS);
2275
2276                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2277         }
2278 }
2279
2280 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2281                                         u32 offset, u32 *val)
2282 {
2283         u32 tmp;
2284         int i;
2285
2286         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2287                 return -EINVAL;
2288
2289         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2290                                         EEPROM_ADDR_DEVID_MASK |
2291                                         EEPROM_ADDR_READ);
2292         tw32(GRC_EEPROM_ADDR,
2293              tmp |
2294              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2295              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2296               EEPROM_ADDR_ADDR_MASK) |
2297              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2298
2299         for (i = 0; i < 1000; i++) {
2300                 tmp = tr32(GRC_EEPROM_ADDR);
2301
2302                 if (tmp & EEPROM_ADDR_COMPLETE)
2303                         break;
2304                 msleep(1);
2305         }
2306         if (!(tmp & EEPROM_ADDR_COMPLETE))
2307                 return -EBUSY;
2308
2309         tmp = tr32(GRC_EEPROM_DATA);
2310
2311         /*
2312          * The data will always be opposite the native endian
2313          * format.  Perform a blind byteswap to compensate.
2314          */
2315         *val = swab32(tmp);
2316
2317         return 0;
2318 }
2319
2320 #define NVRAM_CMD_TIMEOUT 10000
2321
2322 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2323 {
2324         int i;
2325
2326         tw32(NVRAM_CMD, nvram_cmd);
2327         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2328                 udelay(10);
2329                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2330                         udelay(10);
2331                         break;
2332                 }
2333         }
2334
2335         if (i == NVRAM_CMD_TIMEOUT)
2336                 return -EBUSY;
2337
2338         return 0;
2339 }
2340
2341 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2342 {
2343         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2344             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2345             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2346            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2347             (tp->nvram_jedecnum == JEDEC_ATMEL))
2348
2349                 addr = ((addr / tp->nvram_pagesize) <<
2350                         ATMEL_AT45DB0X1B_PAGE_POS) +
2351                        (addr % tp->nvram_pagesize);
2352
2353         return addr;
2354 }
2355
2356 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2357 {
2358         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2359             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2360             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2361            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2362             (tp->nvram_jedecnum == JEDEC_ATMEL))
2363
2364                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2365                         tp->nvram_pagesize) +
2366                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2367
2368         return addr;
2369 }
2370
2371 /* NOTE: Data read in from NVRAM is byteswapped according to
2372  * the byteswapping settings for all other register accesses.
2373  * tg3 devices are BE devices, so on a BE machine, the data
2374  * returned will be exactly as it is seen in NVRAM.  On a LE
2375  * machine, the 32-bit value will be byteswapped.
2376  */
2377 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2378 {
2379         int ret;
2380
2381         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2382                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2383
2384         offset = tg3_nvram_phys_addr(tp, offset);
2385
2386         if (offset > NVRAM_ADDR_MSK)
2387                 return -EINVAL;
2388
2389         ret = tg3_nvram_lock(tp);
2390         if (ret)
2391                 return ret;
2392
2393         tg3_enable_nvram_access(tp);
2394
2395         tw32(NVRAM_ADDR, offset);
2396         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2397                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2398
2399         if (ret == 0)
2400                 *val = tr32(NVRAM_RDDATA);
2401
2402         tg3_disable_nvram_access(tp);
2403
2404         tg3_nvram_unlock(tp);
2405
2406         return ret;
2407 }
2408
2409 /* Ensures NVRAM data is in bytestream format. */
2410 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2411 {
2412         u32 v;
2413         int res = tg3_nvram_read(tp, offset, &v);
2414         if (!res)
2415                 *val = cpu_to_be32(v);
2416         return res;
2417 }
2418
2419 /* tp->lock is held. */
2420 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2421 {
2422         u32 addr_high, addr_low;
2423         int i;
2424
2425         addr_high = ((tp->dev->dev_addr[0] << 8) |
2426                      tp->dev->dev_addr[1]);
2427         addr_low = ((tp->dev->dev_addr[2] << 24) |
2428                     (tp->dev->dev_addr[3] << 16) |
2429                     (tp->dev->dev_addr[4] <<  8) |
2430                     (tp->dev->dev_addr[5] <<  0));
2431         for (i = 0; i < 4; i++) {
2432                 if (i == 1 && skip_mac_1)
2433                         continue;
2434                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2435                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2436         }
2437
2438         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2439             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2440                 for (i = 0; i < 12; i++) {
2441                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2442                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2443                 }
2444         }
2445
2446         addr_high = (tp->dev->dev_addr[0] +
2447                      tp->dev->dev_addr[1] +
2448                      tp->dev->dev_addr[2] +
2449                      tp->dev->dev_addr[3] +
2450                      tp->dev->dev_addr[4] +
2451                      tp->dev->dev_addr[5]) &
2452                 TX_BACKOFF_SEED_MASK;
2453         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2454 }
2455
2456 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2457 {
2458         u32 misc_host_ctrl;
2459         bool device_should_wake, do_low_power;
2460
2461         /* Make sure register accesses (indirect or otherwise)
2462          * will function correctly.
2463          */
2464         pci_write_config_dword(tp->pdev,
2465                                TG3PCI_MISC_HOST_CTRL,
2466                                tp->misc_host_ctrl);
2467
2468         switch (state) {
2469         case PCI_D0:
2470                 pci_enable_wake(tp->pdev, state, false);
2471                 pci_set_power_state(tp->pdev, PCI_D0);
2472
2473                 /* Switch out of Vaux if it is a NIC */
2474                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2475                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2476
2477                 return 0;
2478
2479         case PCI_D1:
2480         case PCI_D2:
2481         case PCI_D3hot:
2482                 break;
2483
2484         default:
2485                 netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
2486                            state);
2487                 return -EINVAL;
2488         }
2489
2490         /* Restore the CLKREQ setting. */
2491         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2492                 u16 lnkctl;
2493
2494                 pci_read_config_word(tp->pdev,
2495                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2496                                      &lnkctl);
2497                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2498                 pci_write_config_word(tp->pdev,
2499                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2500                                       lnkctl);
2501         }
2502
2503         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2504         tw32(TG3PCI_MISC_HOST_CTRL,
2505              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2506
2507         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2508                              device_may_wakeup(&tp->pdev->dev) &&
2509                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2510
2511         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2512                 do_low_power = false;
2513                 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
2514                     !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2515                         struct phy_device *phydev;
2516                         u32 phyid, advertising;
2517
2518                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2519
2520                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2521
2522                         tp->link_config.orig_speed = phydev->speed;
2523                         tp->link_config.orig_duplex = phydev->duplex;
2524                         tp->link_config.orig_autoneg = phydev->autoneg;
2525                         tp->link_config.orig_advertising = phydev->advertising;
2526
2527                         advertising = ADVERTISED_TP |
2528                                       ADVERTISED_Pause |
2529                                       ADVERTISED_Autoneg |
2530                                       ADVERTISED_10baseT_Half;
2531
2532                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2533                             device_should_wake) {
2534                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2535                                         advertising |=
2536                                                 ADVERTISED_100baseT_Half |
2537                                                 ADVERTISED_100baseT_Full |
2538                                                 ADVERTISED_10baseT_Full;
2539                                 else
2540                                         advertising |= ADVERTISED_10baseT_Full;
2541                         }
2542
2543                         phydev->advertising = advertising;
2544
2545                         phy_start_aneg(phydev);
2546
2547                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2548                         if (phyid != PHY_ID_BCMAC131) {
2549                                 phyid &= PHY_BCM_OUI_MASK;
2550                                 if (phyid == PHY_BCM_OUI_1 ||
2551                                     phyid == PHY_BCM_OUI_2 ||
2552                                     phyid == PHY_BCM_OUI_3)
2553                                         do_low_power = true;
2554                         }
2555                 }
2556         } else {
2557                 do_low_power = true;
2558
2559                 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2560                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2561                         tp->link_config.orig_speed = tp->link_config.speed;
2562                         tp->link_config.orig_duplex = tp->link_config.duplex;
2563                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2564                 }
2565
2566                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
2567                         tp->link_config.speed = SPEED_10;
2568                         tp->link_config.duplex = DUPLEX_HALF;
2569                         tp->link_config.autoneg = AUTONEG_ENABLE;
2570                         tg3_setup_phy(tp, 0);
2571                 }
2572         }
2573
2574         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2575                 u32 val;
2576
2577                 val = tr32(GRC_VCPU_EXT_CTRL);
2578                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2579         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2580                 int i;
2581                 u32 val;
2582
2583                 for (i = 0; i < 200; i++) {
2584                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2585                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2586                                 break;
2587                         msleep(1);
2588                 }
2589         }
2590         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2591                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2592                                                      WOL_DRV_STATE_SHUTDOWN |
2593                                                      WOL_DRV_WOL |
2594                                                      WOL_SET_MAGIC_PKT);
2595
2596         if (device_should_wake) {
2597                 u32 mac_mode;
2598
2599                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
2600                         if (do_low_power) {
2601                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2602                                 udelay(40);
2603                         }
2604
2605                         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
2606                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2607                         else
2608                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2609
2610                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2611                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2612                             ASIC_REV_5700) {
2613                                 u32 speed = (tp->tg3_flags &
2614                                              TG3_FLAG_WOL_SPEED_100MB) ?
2615                                              SPEED_100 : SPEED_10;
2616                                 if (tg3_5700_link_polarity(tp, speed))
2617                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2618                                 else
2619                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2620                         }
2621                 } else {
2622                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2623                 }
2624
2625                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2626                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2627
2628                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2629                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2630                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2631                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2632                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2633                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2634
2635                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2636                         mac_mode |= tp->mac_mode &
2637                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2638                         if (mac_mode & MAC_MODE_APE_TX_EN)
2639                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2640                 }
2641
2642                 tw32_f(MAC_MODE, mac_mode);
2643                 udelay(100);
2644
2645                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2646                 udelay(10);
2647         }
2648
2649         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2650             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2651              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2652                 u32 base_val;
2653
2654                 base_val = tp->pci_clock_ctrl;
2655                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2656                              CLOCK_CTRL_TXCLK_DISABLE);
2657
2658                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2659                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2660         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2661                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2662                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2663                 /* do nothing */
2664         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2665                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2666                 u32 newbits1, newbits2;
2667
2668                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2669                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2670                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2671                                     CLOCK_CTRL_TXCLK_DISABLE |
2672                                     CLOCK_CTRL_ALTCLK);
2673                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2674                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2675                         newbits1 = CLOCK_CTRL_625_CORE;
2676                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2677                 } else {
2678                         newbits1 = CLOCK_CTRL_ALTCLK;
2679                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2680                 }
2681
2682                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2683                             40);
2684
2685                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2686                             40);
2687
2688                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2689                         u32 newbits3;
2690
2691                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2692                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2693                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2694                                             CLOCK_CTRL_TXCLK_DISABLE |
2695                                             CLOCK_CTRL_44MHZ_CORE);
2696                         } else {
2697                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2698                         }
2699
2700                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2701                                     tp->pci_clock_ctrl | newbits3, 40);
2702                 }
2703         }
2704
2705         if (!(device_should_wake) &&
2706             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2707                 tg3_power_down_phy(tp, do_low_power);
2708
2709         tg3_frob_aux_power(tp);
2710
2711         /* Workaround for unstable PLL clock */
2712         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2713             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2714                 u32 val = tr32(0x7d00);
2715
2716                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2717                 tw32(0x7d00, val);
2718                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2719                         int err;
2720
2721                         err = tg3_nvram_lock(tp);
2722                         tg3_halt_cpu(tp, RX_CPU_BASE);
2723                         if (!err)
2724                                 tg3_nvram_unlock(tp);
2725                 }
2726         }
2727
2728         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2729
2730         if (device_should_wake)
2731                 pci_enable_wake(tp->pdev, state, true);
2732
2733         /* Finally, set the new power state. */
2734         pci_set_power_state(tp->pdev, state);
2735
2736         return 0;
2737 }
2738
2739 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2740 {
2741         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2742         case MII_TG3_AUX_STAT_10HALF:
2743                 *speed = SPEED_10;
2744                 *duplex = DUPLEX_HALF;
2745                 break;
2746
2747         case MII_TG3_AUX_STAT_10FULL:
2748                 *speed = SPEED_10;
2749                 *duplex = DUPLEX_FULL;
2750                 break;
2751
2752         case MII_TG3_AUX_STAT_100HALF:
2753                 *speed = SPEED_100;
2754                 *duplex = DUPLEX_HALF;
2755                 break;
2756
2757         case MII_TG3_AUX_STAT_100FULL:
2758                 *speed = SPEED_100;
2759                 *duplex = DUPLEX_FULL;
2760                 break;
2761
2762         case MII_TG3_AUX_STAT_1000HALF:
2763                 *speed = SPEED_1000;
2764                 *duplex = DUPLEX_HALF;
2765                 break;
2766
2767         case MII_TG3_AUX_STAT_1000FULL:
2768                 *speed = SPEED_1000;
2769                 *duplex = DUPLEX_FULL;
2770                 break;
2771
2772         default:
2773                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2774                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2775                                  SPEED_10;
2776                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2777                                   DUPLEX_HALF;
2778                         break;
2779                 }
2780                 *speed = SPEED_INVALID;
2781                 *duplex = DUPLEX_INVALID;
2782                 break;
2783         }
2784 }
2785
2786 static void tg3_phy_copper_begin(struct tg3 *tp)
2787 {
2788         u32 new_adv;
2789         int i;
2790
2791         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2792                 /* Entering low power mode.  Disable gigabit and
2793                  * 100baseT advertisements.
2794                  */
2795                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2796
2797                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2798                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2799                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2800                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2801
2802                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2803         } else if (tp->link_config.speed == SPEED_INVALID) {
2804                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
2805                         tp->link_config.advertising &=
2806                                 ~(ADVERTISED_1000baseT_Half |
2807                                   ADVERTISED_1000baseT_Full);
2808
2809                 new_adv = ADVERTISE_CSMA;
2810                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2811                         new_adv |= ADVERTISE_10HALF;
2812                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2813                         new_adv |= ADVERTISE_10FULL;
2814                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2815                         new_adv |= ADVERTISE_100HALF;
2816                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2817                         new_adv |= ADVERTISE_100FULL;
2818
2819                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2820
2821                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2822
2823                 if (tp->link_config.advertising &
2824                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2825                         new_adv = 0;
2826                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2827                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2828                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2829                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2830                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) &&
2831                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2832                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2833                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2834                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2835                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2836                 } else {
2837                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2838                 }
2839         } else {
2840                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2841                 new_adv |= ADVERTISE_CSMA;
2842
2843                 /* Asking for a specific link mode. */
2844                 if (tp->link_config.speed == SPEED_1000) {
2845                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2846
2847                         if (tp->link_config.duplex == DUPLEX_FULL)
2848                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2849                         else
2850                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2851                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2852                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2853                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2854                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2855                 } else {
2856                         if (tp->link_config.speed == SPEED_100) {
2857                                 if (tp->link_config.duplex == DUPLEX_FULL)
2858                                         new_adv |= ADVERTISE_100FULL;
2859                                 else
2860                                         new_adv |= ADVERTISE_100HALF;
2861                         } else {
2862                                 if (tp->link_config.duplex == DUPLEX_FULL)
2863                                         new_adv |= ADVERTISE_10FULL;
2864                                 else
2865                                         new_adv |= ADVERTISE_10HALF;
2866                         }
2867                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2868
2869                         new_adv = 0;
2870                 }
2871
2872                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2873         }
2874
2875         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2876             tp->link_config.speed != SPEED_INVALID) {
2877                 u32 bmcr, orig_bmcr;
2878
2879                 tp->link_config.active_speed = tp->link_config.speed;
2880                 tp->link_config.active_duplex = tp->link_config.duplex;
2881
2882                 bmcr = 0;
2883                 switch (tp->link_config.speed) {
2884                 default:
2885                 case SPEED_10:
2886                         break;
2887
2888                 case SPEED_100:
2889                         bmcr |= BMCR_SPEED100;
2890                         break;
2891
2892                 case SPEED_1000:
2893                         bmcr |= TG3_BMCR_SPEED1000;
2894                         break;
2895                 }
2896
2897                 if (tp->link_config.duplex == DUPLEX_FULL)
2898                         bmcr |= BMCR_FULLDPLX;
2899
2900                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2901                     (bmcr != orig_bmcr)) {
2902                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2903                         for (i = 0; i < 1500; i++) {
2904                                 u32 tmp;
2905
2906                                 udelay(10);
2907                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2908                                     tg3_readphy(tp, MII_BMSR, &tmp))
2909                                         continue;
2910                                 if (!(tmp & BMSR_LSTATUS)) {
2911                                         udelay(40);
2912                                         break;
2913                                 }
2914                         }
2915                         tg3_writephy(tp, MII_BMCR, bmcr);
2916                         udelay(40);
2917                 }
2918         } else {
2919                 tg3_writephy(tp, MII_BMCR,
2920                              BMCR_ANENABLE | BMCR_ANRESTART);
2921         }
2922 }
2923
2924 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2925 {
2926         int err;
2927
2928         /* Turn off tap power management. */
2929         /* Set Extended packet length bit */
2930         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2931
2932         err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
2933         err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
2934         err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
2935         err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
2936         err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
2937
2938         udelay(40);
2939
2940         return err;
2941 }
2942
2943 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2944 {
2945         u32 adv_reg, all_mask = 0;
2946
2947         if (mask & ADVERTISED_10baseT_Half)
2948                 all_mask |= ADVERTISE_10HALF;
2949         if (mask & ADVERTISED_10baseT_Full)
2950                 all_mask |= ADVERTISE_10FULL;
2951         if (mask & ADVERTISED_100baseT_Half)
2952                 all_mask |= ADVERTISE_100HALF;
2953         if (mask & ADVERTISED_100baseT_Full)
2954                 all_mask |= ADVERTISE_100FULL;
2955
2956         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2957                 return 0;
2958
2959         if ((adv_reg & all_mask) != all_mask)
2960                 return 0;
2961         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
2962                 u32 tg3_ctrl;
2963
2964                 all_mask = 0;
2965                 if (mask & ADVERTISED_1000baseT_Half)
2966                         all_mask |= ADVERTISE_1000HALF;
2967                 if (mask & ADVERTISED_1000baseT_Full)
2968                         all_mask |= ADVERTISE_1000FULL;
2969
2970                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2971                         return 0;
2972
2973                 if ((tg3_ctrl & all_mask) != all_mask)
2974                         return 0;
2975         }
2976         return 1;
2977 }
2978
2979 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2980 {
2981         u32 curadv, reqadv;
2982
2983         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2984                 return 1;
2985
2986         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2987         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2988
2989         if (tp->link_config.active_duplex == DUPLEX_FULL) {
2990                 if (curadv != reqadv)
2991                         return 0;
2992
2993                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2994                         tg3_readphy(tp, MII_LPA, rmtadv);
2995         } else {
2996                 /* Reprogram the advertisement register, even if it
2997                  * does not affect the current link.  If the link
2998                  * gets renegotiated in the future, we can save an
2999                  * additional renegotiation cycle by advertising
3000                  * it correctly in the first place.
3001                  */
3002                 if (curadv != reqadv) {
3003                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3004                                      ADVERTISE_PAUSE_ASYM);
3005                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3006                 }
3007         }
3008
3009         return 1;
3010 }
3011
3012 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3013 {
3014         int current_link_up;
3015         u32 bmsr, val;
3016         u32 lcl_adv, rmt_adv;
3017         u16 current_speed;
3018         u8 current_duplex;
3019         int i, err;
3020
3021         tw32(MAC_EVENT, 0);
3022
3023         tw32_f(MAC_STATUS,
3024              (MAC_STATUS_SYNC_CHANGED |
3025               MAC_STATUS_CFG_CHANGED |
3026               MAC_STATUS_MI_COMPLETION |
3027               MAC_STATUS_LNKSTATE_CHANGED));
3028         udelay(40);
3029
3030         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3031                 tw32_f(MAC_MI_MODE,
3032                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3033                 udelay(80);
3034         }
3035
3036         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3037
3038         /* Some third-party PHYs need to be reset on link going
3039          * down.
3040          */
3041         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3042              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3043              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3044             netif_carrier_ok(tp->dev)) {
3045                 tg3_readphy(tp, MII_BMSR, &bmsr);
3046                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3047                     !(bmsr & BMSR_LSTATUS))
3048                         force_reset = 1;
3049         }
3050         if (force_reset)
3051                 tg3_phy_reset(tp);
3052
3053         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3054                 tg3_readphy(tp, MII_BMSR, &bmsr);
3055                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3056                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3057                         bmsr = 0;
3058
3059                 if (!(bmsr & BMSR_LSTATUS)) {
3060                         err = tg3_init_5401phy_dsp(tp);
3061                         if (err)
3062                                 return err;
3063
3064                         tg3_readphy(tp, MII_BMSR, &bmsr);
3065                         for (i = 0; i < 1000; i++) {
3066                                 udelay(10);
3067                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3068                                     (bmsr & BMSR_LSTATUS)) {
3069                                         udelay(40);
3070                                         break;
3071                                 }
3072                         }
3073
3074                         if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3075                             TG3_PHY_REV_BCM5401_B0 &&
3076                             !(bmsr & BMSR_LSTATUS) &&
3077                             tp->link_config.active_speed == SPEED_1000) {
3078                                 err = tg3_phy_reset(tp);
3079                                 if (!err)
3080                                         err = tg3_init_5401phy_dsp(tp);
3081                                 if (err)
3082                                         return err;
3083                         }
3084                 }
3085         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3086                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3087                 /* 5701 {A0,B0} CRC bug workaround */
3088                 tg3_writephy(tp, 0x15, 0x0a75);
3089                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3090                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3091                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3092         }
3093
3094         /* Clear pending interrupts... */
3095         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3096         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3097
3098         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3099                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3100         else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3101                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3102
3103         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3104             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3105                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3106                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3107                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3108                 else
3109                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3110         }
3111
3112         current_link_up = 0;
3113         current_speed = SPEED_INVALID;
3114         current_duplex = DUPLEX_INVALID;
3115
3116         if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3117                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3118                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3119                 if (!(val & (1 << 10))) {
3120                         val |= (1 << 10);
3121                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3122                         goto relink;
3123                 }
3124         }
3125
3126         bmsr = 0;
3127         for (i = 0; i < 100; i++) {
3128                 tg3_readphy(tp, MII_BMSR, &bmsr);
3129                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3130                     (bmsr & BMSR_LSTATUS))
3131                         break;
3132                 udelay(40);
3133         }
3134
3135         if (bmsr & BMSR_LSTATUS) {
3136                 u32 aux_stat, bmcr;
3137
3138                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3139                 for (i = 0; i < 2000; i++) {
3140                         udelay(10);
3141                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3142                             aux_stat)
3143                                 break;
3144                 }
3145
3146                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3147                                              &current_speed,
3148                                              &current_duplex);
3149
3150                 bmcr = 0;
3151                 for (i = 0; i < 200; i++) {
3152                         tg3_readphy(tp, MII_BMCR, &bmcr);
3153                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3154                                 continue;
3155                         if (bmcr && bmcr != 0x7fff)
3156                                 break;
3157                         udelay(10);
3158                 }
3159
3160                 lcl_adv = 0;
3161                 rmt_adv = 0;
3162
3163                 tp->link_config.active_speed = current_speed;
3164                 tp->link_config.active_duplex = current_duplex;
3165
3166                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3167                         if ((bmcr & BMCR_ANENABLE) &&
3168                             tg3_copper_is_advertising_all(tp,
3169                                                 tp->link_config.advertising)) {
3170                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3171                                                                   &rmt_adv))
3172                                         current_link_up = 1;
3173                         }
3174                 } else {
3175                         if (!(bmcr & BMCR_ANENABLE) &&
3176                             tp->link_config.speed == current_speed &&
3177                             tp->link_config.duplex == current_duplex &&
3178                             tp->link_config.flowctrl ==
3179                             tp->link_config.active_flowctrl) {
3180                                 current_link_up = 1;
3181                         }
3182                 }
3183
3184                 if (current_link_up == 1 &&
3185                     tp->link_config.active_duplex == DUPLEX_FULL)
3186                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3187         }
3188
3189 relink:
3190         if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3191                 tg3_phy_copper_begin(tp);
3192
3193                 tg3_readphy(tp, MII_BMSR, &bmsr);
3194                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3195                     (bmsr & BMSR_LSTATUS))
3196                         current_link_up = 1;
3197         }
3198
3199         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3200         if (current_link_up == 1) {
3201                 if (tp->link_config.active_speed == SPEED_100 ||
3202                     tp->link_config.active_speed == SPEED_10)
3203                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3204                 else
3205                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3206         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
3207                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3208         else
3209                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3210
3211         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3212         if (tp->link_config.active_duplex == DUPLEX_HALF)
3213                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3214
3215         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3216                 if (current_link_up == 1 &&
3217                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3218                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3219                 else
3220                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3221         }
3222
3223         /* ??? Without this setting Netgear GA302T PHY does not
3224          * ??? send/receive packets...
3225          */
3226         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3227             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3228                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3229                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3230                 udelay(80);
3231         }
3232
3233         tw32_f(MAC_MODE, tp->mac_mode);
3234         udelay(40);
3235
3236         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3237                 /* Polled via timer. */
3238                 tw32_f(MAC_EVENT, 0);
3239         } else {
3240                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3241         }
3242         udelay(40);
3243
3244         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3245             current_link_up == 1 &&
3246             tp->link_config.active_speed == SPEED_1000 &&
3247             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3248              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3249                 udelay(120);
3250                 tw32_f(MAC_STATUS,
3251                      (MAC_STATUS_SYNC_CHANGED |
3252                       MAC_STATUS_CFG_CHANGED));
3253                 udelay(40);
3254                 tg3_write_mem(tp,
3255                               NIC_SRAM_FIRMWARE_MBOX,
3256                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3257         }
3258
3259         /* Prevent send BD corruption. */
3260         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3261                 u16 oldlnkctl, newlnkctl;
3262
3263                 pci_read_config_word(tp->pdev,
3264                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3265                                      &oldlnkctl);
3266                 if (tp->link_config.active_speed == SPEED_100 ||
3267                     tp->link_config.active_speed == SPEED_10)
3268                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3269                 else
3270                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3271                 if (newlnkctl != oldlnkctl)
3272                         pci_write_config_word(tp->pdev,
3273                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3274                                               newlnkctl);
3275         }
3276
3277         if (current_link_up != netif_carrier_ok(tp->dev)) {
3278                 if (current_link_up)
3279                         netif_carrier_on(tp->dev);
3280                 else
3281                         netif_carrier_off(tp->dev);
3282                 tg3_link_report(tp);
3283         }
3284
3285         return 0;
3286 }
3287
3288 struct tg3_fiber_aneginfo {
3289         int state;
3290 #define ANEG_STATE_UNKNOWN              0
3291 #define ANEG_STATE_AN_ENABLE            1
3292 #define ANEG_STATE_RESTART_INIT         2
3293 #define ANEG_STATE_RESTART              3
3294 #define ANEG_STATE_DISABLE_LINK_OK      4
3295 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3296 #define ANEG_STATE_ABILITY_DETECT       6
3297 #define ANEG_STATE_ACK_DETECT_INIT      7
3298 #define ANEG_STATE_ACK_DETECT           8
3299 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3300 #define ANEG_STATE_COMPLETE_ACK         10
3301 #define ANEG_STATE_IDLE_DETECT_INIT     11
3302 #define ANEG_STATE_IDLE_DETECT          12
3303 #define ANEG_STATE_LINK_OK              13
3304 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3305 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3306
3307         u32 flags;
3308 #define MR_AN_ENABLE            0x00000001
3309 #define MR_RESTART_AN           0x00000002
3310 #define MR_AN_COMPLETE          0x00000004
3311 #define MR_PAGE_RX              0x00000008
3312 #define MR_NP_LOADED            0x00000010
3313 #define MR_TOGGLE_TX            0x00000020
3314 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3315 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3316 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3317 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3318 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3319 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3320 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3321 #define MR_TOGGLE_RX            0x00002000
3322 #define MR_NP_RX                0x00004000
3323
3324 #define MR_LINK_OK              0x80000000
3325
3326         unsigned long link_time, cur_time;
3327
3328         u32 ability_match_cfg;
3329         int ability_match_count;
3330
3331         char ability_match, idle_match, ack_match;
3332
3333         u32 txconfig, rxconfig;
3334 #define ANEG_CFG_NP             0x00000080
3335 #define ANEG_CFG_ACK            0x00000040
3336 #define ANEG_CFG_RF2            0x00000020
3337 #define ANEG_CFG_RF1            0x00000010
3338 #define ANEG_CFG_PS2            0x00000001
3339 #define ANEG_CFG_PS1            0x00008000
3340 #define ANEG_CFG_HD             0x00004000
3341 #define ANEG_CFG_FD             0x00002000
3342 #define ANEG_CFG_INVAL          0x00001f06
3343
3344 };
3345 #define ANEG_OK         0
3346 #define ANEG_DONE       1
3347 #define ANEG_TIMER_ENAB 2
3348 #define ANEG_FAILED     -1
3349
3350 #define ANEG_STATE_SETTLE_TIME  10000
3351
3352 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3353                                    struct tg3_fiber_aneginfo *ap)
3354 {
3355         u16 flowctrl;
3356         unsigned long delta;
3357         u32 rx_cfg_reg;
3358         int ret;
3359
3360         if (ap->state == ANEG_STATE_UNKNOWN) {
3361                 ap->rxconfig = 0;
3362                 ap->link_time = 0;
3363                 ap->cur_time = 0;
3364                 ap->ability_match_cfg = 0;
3365                 ap->ability_match_count = 0;
3366                 ap->ability_match = 0;
3367                 ap->idle_match = 0;
3368                 ap->ack_match = 0;
3369         }
3370         ap->cur_time++;
3371
3372         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3373                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3374
3375                 if (rx_cfg_reg != ap->ability_match_cfg) {
3376                         ap->ability_match_cfg = rx_cfg_reg;
3377                         ap->ability_match = 0;
3378                         ap->ability_match_count = 0;
3379                 } else {
3380                         if (++ap->ability_match_count > 1) {
3381                                 ap->ability_match = 1;
3382                                 ap->ability_match_cfg = rx_cfg_reg;
3383                         }
3384                 }
3385                 if (rx_cfg_reg & ANEG_CFG_ACK)
3386                         ap->ack_match = 1;
3387                 else
3388                         ap->ack_match = 0;
3389
3390                 ap->idle_match = 0;
3391         } else {
3392                 ap->idle_match = 1;
3393                 ap->ability_match_cfg = 0;
3394                 ap->ability_match_count = 0;
3395                 ap->ability_match = 0;
3396                 ap->ack_match = 0;
3397
3398                 rx_cfg_reg = 0;
3399         }
3400
3401         ap->rxconfig = rx_cfg_reg;
3402         ret = ANEG_OK;
3403
3404         switch (ap->state) {
3405         case ANEG_STATE_UNKNOWN:
3406                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3407                         ap->state = ANEG_STATE_AN_ENABLE;
3408
3409                 /* fallthru */
3410         case ANEG_STATE_AN_ENABLE:
3411                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3412                 if (ap->flags & MR_AN_ENABLE) {
3413                         ap->link_time = 0;
3414                         ap->cur_time = 0;
3415                         ap->ability_match_cfg = 0;
3416                         ap->ability_match_count = 0;
3417                         ap->ability_match = 0;
3418                         ap->idle_match = 0;
3419                         ap->ack_match = 0;
3420
3421                         ap->state = ANEG_STATE_RESTART_INIT;
3422                 } else {
3423                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3424                 }
3425                 break;
3426
3427         case ANEG_STATE_RESTART_INIT:
3428                 ap->link_time = ap->cur_time;
3429                 ap->flags &= ~(MR_NP_LOADED);
3430                 ap->txconfig = 0;
3431                 tw32(MAC_TX_AUTO_NEG, 0);
3432                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3433                 tw32_f(MAC_MODE, tp->mac_mode);
3434                 udelay(40);
3435
3436                 ret = ANEG_TIMER_ENAB;
3437                 ap->state = ANEG_STATE_RESTART;
3438
3439                 /* fallthru */
3440         case ANEG_STATE_RESTART:
3441                 delta = ap->cur_time - ap->link_time;
3442                 if (delta > ANEG_STATE_SETTLE_TIME)
3443                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3444                 else
3445                         ret = ANEG_TIMER_ENAB;
3446                 break;
3447
3448         case ANEG_STATE_DISABLE_LINK_OK:
3449                 ret = ANEG_DONE;
3450                 break;
3451
3452         case ANEG_STATE_ABILITY_DETECT_INIT:
3453                 ap->flags &= ~(MR_TOGGLE_TX);
3454                 ap->txconfig = ANEG_CFG_FD;
3455                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3456                 if (flowctrl & ADVERTISE_1000XPAUSE)
3457                         ap->txconfig |= ANEG_CFG_PS1;
3458                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3459                         ap->txconfig |= ANEG_CFG_PS2;
3460                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3461                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3462                 tw32_f(MAC_MODE, tp->mac_mode);
3463                 udelay(40);
3464
3465                 ap->state = ANEG_STATE_ABILITY_DETECT;
3466                 break;
3467
3468         case ANEG_STATE_ABILITY_DETECT:
3469                 if (ap->ability_match != 0 && ap->rxconfig != 0)
3470                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3471                 break;
3472
3473         case ANEG_STATE_ACK_DETECT_INIT:
3474                 ap->txconfig |= ANEG_CFG_ACK;
3475                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3476                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3477                 tw32_f(MAC_MODE, tp->mac_mode);
3478                 udelay(40);
3479
3480                 ap->state = ANEG_STATE_ACK_DETECT;
3481
3482                 /* fallthru */
3483         case ANEG_STATE_ACK_DETECT:
3484                 if (ap->ack_match != 0) {
3485                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3486                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3487                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3488                         } else {
3489                                 ap->state = ANEG_STATE_AN_ENABLE;
3490                         }
3491                 } else if (ap->ability_match != 0 &&
3492                            ap->rxconfig == 0) {
3493                         ap->state = ANEG_STATE_AN_ENABLE;
3494                 }
3495                 break;
3496
3497         case ANEG_STATE_COMPLETE_ACK_INIT:
3498                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3499                         ret = ANEG_FAILED;
3500                         break;
3501                 }
3502                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3503                                MR_LP_ADV_HALF_DUPLEX |
3504                                MR_LP_ADV_SYM_PAUSE |
3505                                MR_LP_ADV_ASYM_PAUSE |
3506                                MR_LP_ADV_REMOTE_FAULT1 |
3507                                MR_LP_ADV_REMOTE_FAULT2 |
3508                                MR_LP_ADV_NEXT_PAGE |
3509                                MR_TOGGLE_RX |
3510                                MR_NP_RX);
3511                 if (ap->rxconfig & ANEG_CFG_FD)
3512                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3513                 if (ap->rxconfig & ANEG_CFG_HD)
3514                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3515                 if (ap->rxconfig & ANEG_CFG_PS1)
3516                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3517                 if (ap->rxconfig & ANEG_CFG_PS2)
3518                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3519                 if (ap->rxconfig & ANEG_CFG_RF1)
3520                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3521                 if (ap->rxconfig & ANEG_CFG_RF2)
3522                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3523                 if (ap->rxconfig & ANEG_CFG_NP)
3524                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3525
3526                 ap->link_time = ap->cur_time;
3527
3528                 ap->flags ^= (MR_TOGGLE_TX);
3529                 if (ap->rxconfig & 0x0008)
3530                         ap->flags |= MR_TOGGLE_RX;
3531                 if (ap->rxconfig & ANEG_CFG_NP)
3532                         ap->flags |= MR_NP_RX;
3533                 ap->flags |= MR_PAGE_RX;
3534
3535                 ap->state = ANEG_STATE_COMPLETE_ACK;
3536                 ret = ANEG_TIMER_ENAB;
3537                 break;
3538
3539         case ANEG_STATE_COMPLETE_ACK:
3540                 if (ap->ability_match != 0 &&
3541                     ap->rxconfig == 0) {
3542                         ap->state = ANEG_STATE_AN_ENABLE;
3543                         break;
3544                 }
3545                 delta = ap->cur_time - ap->link_time;
3546                 if (delta > ANEG_STATE_SETTLE_TIME) {
3547                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3548                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3549                         } else {
3550                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3551                                     !(ap->flags & MR_NP_RX)) {
3552                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3553                                 } else {
3554                                         ret = ANEG_FAILED;
3555                                 }
3556                         }
3557                 }
3558                 break;
3559
3560         case ANEG_STATE_IDLE_DETECT_INIT:
3561                 ap->link_time = ap->cur_time;
3562                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3563                 tw32_f(MAC_MODE, tp->mac_mode);
3564                 udelay(40);
3565
3566                 ap->state = ANEG_STATE_IDLE_DETECT;
3567                 ret = ANEG_TIMER_ENAB;
3568                 break;
3569
3570         case ANEG_STATE_IDLE_DETECT:
3571                 if (ap->ability_match != 0 &&
3572                     ap->rxconfig == 0) {
3573                         ap->state = ANEG_STATE_AN_ENABLE;
3574                         break;
3575                 }
3576                 delta = ap->cur_time - ap->link_time;
3577                 if (delta > ANEG_STATE_SETTLE_TIME) {
3578                         /* XXX another gem from the Broadcom driver :( */
3579                         ap->state = ANEG_STATE_LINK_OK;
3580                 }
3581                 break;
3582
3583         case ANEG_STATE_LINK_OK:
3584                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3585                 ret = ANEG_DONE;
3586                 break;
3587
3588         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3589                 /* ??? unimplemented */
3590                 break;
3591
3592         case ANEG_STATE_NEXT_PAGE_WAIT:
3593                 /* ??? unimplemented */
3594                 break;
3595
3596         default:
3597                 ret = ANEG_FAILED;
3598                 break;
3599         }
3600
3601         return ret;
3602 }
3603
3604 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3605 {
3606         int res = 0;
3607         struct tg3_fiber_aneginfo aninfo;
3608         int status = ANEG_FAILED;
3609         unsigned int tick;
3610         u32 tmp;
3611
3612         tw32_f(MAC_TX_AUTO_NEG, 0);
3613
3614         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3615         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3616         udelay(40);
3617
3618         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3619         udelay(40);
3620
3621         memset(&aninfo, 0, sizeof(aninfo));
3622         aninfo.flags |= MR_AN_ENABLE;
3623         aninfo.state = ANEG_STATE_UNKNOWN;
3624         aninfo.cur_time = 0;
3625         tick = 0;
3626         while (++tick < 195000) {
3627                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3628                 if (status == ANEG_DONE || status == ANEG_FAILED)
3629                         break;
3630
3631                 udelay(1);
3632         }
3633
3634         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3635         tw32_f(MAC_MODE, tp->mac_mode);
3636         udelay(40);
3637
3638         *txflags = aninfo.txconfig;
3639         *rxflags = aninfo.flags;
3640
3641         if (status == ANEG_DONE &&
3642             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3643                              MR_LP_ADV_FULL_DUPLEX)))
3644                 res = 1;
3645
3646         return res;
3647 }
3648
3649 static void tg3_init_bcm8002(struct tg3 *tp)
3650 {
3651         u32 mac_status = tr32(MAC_STATUS);
3652         int i;
3653
3654         /* Reset when initting first time or we have a link. */
3655         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3656             !(mac_status & MAC_STATUS_PCS_SYNCED))
3657                 return;
3658
3659         /* Set PLL lock range. */
3660         tg3_writephy(tp, 0x16, 0x8007);
3661
3662         /* SW reset */
3663         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3664
3665         /* Wait for reset to complete. */
3666         /* XXX schedule_timeout() ... */
3667         for (i = 0; i < 500; i++)
3668                 udelay(10);
3669
3670         /* Config mode; select PMA/Ch 1 regs. */
3671         tg3_writephy(tp, 0x10, 0x8411);
3672
3673         /* Enable auto-lock and comdet, select txclk for tx. */
3674         tg3_writephy(tp, 0x11, 0x0a10);
3675
3676         tg3_writephy(tp, 0x18, 0x00a0);
3677         tg3_writephy(tp, 0x16, 0x41ff);
3678
3679         /* Assert and deassert POR. */
3680         tg3_writephy(tp, 0x13, 0x0400);
3681         udelay(40);
3682         tg3_writephy(tp, 0x13, 0x0000);
3683
3684         tg3_writephy(tp, 0x11, 0x0a50);
3685         udelay(40);
3686         tg3_writephy(tp, 0x11, 0x0a10);
3687
3688         /* Wait for signal to stabilize */
3689         /* XXX schedule_timeout() ... */
3690         for (i = 0; i < 15000; i++)
3691                 udelay(10);
3692
3693         /* Deselect the channel register so we can read the PHYID
3694          * later.
3695          */
3696         tg3_writephy(tp, 0x10, 0x8011);
3697 }
3698
3699 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3700 {
3701         u16 flowctrl;
3702         u32 sg_dig_ctrl, sg_dig_status;
3703         u32 serdes_cfg, expected_sg_dig_ctrl;
3704         int workaround, port_a;
3705         int current_link_up;
3706
3707         serdes_cfg = 0;
3708         expected_sg_dig_ctrl = 0;
3709         workaround = 0;
3710         port_a = 1;
3711         current_link_up = 0;
3712
3713         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3714             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3715                 workaround = 1;
3716                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3717                         port_a = 0;
3718
3719                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3720                 /* preserve bits 20-23 for voltage regulator */
3721                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3722         }
3723
3724         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3725
3726         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3727                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3728                         if (workaround) {
3729                                 u32 val = serdes_cfg;
3730
3731                                 if (port_a)
3732                                         val |= 0xc010000;
3733                                 else
3734                                         val |= 0x4010000;
3735                                 tw32_f(MAC_SERDES_CFG, val);
3736                         }
3737
3738                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3739                 }
3740                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3741                         tg3_setup_flow_control(tp, 0, 0);
3742                         current_link_up = 1;
3743                 }
3744                 goto out;
3745         }
3746
3747         /* Want auto-negotiation.  */
3748         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3749
3750         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3751         if (flowctrl & ADVERTISE_1000XPAUSE)
3752                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3753         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3754                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3755
3756         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3757                 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3758                     tp->serdes_counter &&
3759                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3760                                     MAC_STATUS_RCVD_CFG)) ==
3761                      MAC_STATUS_PCS_SYNCED)) {
3762                         tp->serdes_counter--;
3763                         current_link_up = 1;
3764                         goto out;
3765                 }
3766 restart_autoneg:
3767                 if (workaround)
3768                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3769                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3770                 udelay(5);
3771                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3772
3773                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3774                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3775         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3776                                  MAC_STATUS_SIGNAL_DET)) {
3777                 sg_dig_status = tr32(SG_DIG_STATUS);
3778                 mac_status = tr32(MAC_STATUS);
3779
3780                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3781                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3782                         u32 local_adv = 0, remote_adv = 0;
3783
3784                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3785                                 local_adv |= ADVERTISE_1000XPAUSE;
3786                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3787                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3788
3789                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3790                                 remote_adv |= LPA_1000XPAUSE;
3791                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3792                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3793
3794                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3795                         current_link_up = 1;
3796                         tp->serdes_counter = 0;
3797                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3798                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3799                         if (tp->serdes_counter)
3800                                 tp->serdes_counter--;
3801                         else {
3802                                 if (workaround) {
3803                                         u32 val = serdes_cfg;
3804
3805                                         if (port_a)
3806                                                 val |= 0xc010000;
3807                                         else
3808                                                 val |= 0x4010000;
3809
3810                                         tw32_f(MAC_SERDES_CFG, val);
3811                                 }
3812
3813                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3814                                 udelay(40);
3815
3816                                 /* Link parallel detection - link is up */
3817                                 /* only if we have PCS_SYNC and not */
3818                                 /* receiving config code words */
3819                                 mac_status = tr32(MAC_STATUS);
3820                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3821                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3822                                         tg3_setup_flow_control(tp, 0, 0);
3823                                         current_link_up = 1;
3824                                         tp->phy_flags |=
3825                                                 TG3_PHYFLG_PARALLEL_DETECT;
3826                                         tp->serdes_counter =
3827                                                 SERDES_PARALLEL_DET_TIMEOUT;
3828                                 } else
3829                                         goto restart_autoneg;
3830                         }
3831                 }
3832         } else {
3833                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3834                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3835         }
3836
3837 out:
3838         return current_link_up;
3839 }
3840
3841 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3842 {
3843         int current_link_up = 0;
3844
3845         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3846                 goto out;
3847
3848         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3849                 u32 txflags, rxflags;
3850                 int i;
3851
3852                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3853                         u32 local_adv = 0, remote_adv = 0;
3854
3855                         if (txflags & ANEG_CFG_PS1)
3856                                 local_adv |= ADVERTISE_1000XPAUSE;
3857                         if (txflags & ANEG_CFG_PS2)
3858                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3859
3860                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3861                                 remote_adv |= LPA_1000XPAUSE;
3862                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3863                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3864
3865                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3866
3867                         current_link_up = 1;
3868                 }
3869                 for (i = 0; i < 30; i++) {
3870                         udelay(20);
3871                         tw32_f(MAC_STATUS,
3872                                (MAC_STATUS_SYNC_CHANGED |
3873                                 MAC_STATUS_CFG_CHANGED));
3874                         udelay(40);
3875                         if ((tr32(MAC_STATUS) &
3876                              (MAC_STATUS_SYNC_CHANGED |
3877                               MAC_STATUS_CFG_CHANGED)) == 0)
3878                                 break;
3879                 }
3880
3881                 mac_status = tr32(MAC_STATUS);
3882                 if (current_link_up == 0 &&
3883                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3884                     !(mac_status & MAC_STATUS_RCVD_CFG))
3885                         current_link_up = 1;
3886         } else {
3887                 tg3_setup_flow_control(tp, 0, 0);
3888
3889                 /* Forcing 1000FD link up. */
3890                 current_link_up = 1;
3891
3892                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3893                 udelay(40);
3894
3895                 tw32_f(MAC_MODE, tp->mac_mode);
3896                 udelay(40);
3897         }
3898
3899 out:
3900         return current_link_up;
3901 }
3902
3903 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3904 {
3905         u32 orig_pause_cfg;
3906         u16 orig_active_speed;
3907         u8 orig_active_duplex;
3908         u32 mac_status;
3909         int current_link_up;
3910         int i;
3911
3912         orig_pause_cfg = tp->link_config.active_flowctrl;
3913         orig_active_speed = tp->link_config.active_speed;
3914         orig_active_duplex = tp->link_config.active_duplex;
3915
3916         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3917             netif_carrier_ok(tp->dev) &&
3918             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3919                 mac_status = tr32(MAC_STATUS);
3920                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3921                                MAC_STATUS_SIGNAL_DET |
3922                                MAC_STATUS_CFG_CHANGED |
3923                                MAC_STATUS_RCVD_CFG);
3924                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3925                                    MAC_STATUS_SIGNAL_DET)) {
3926                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3927                                             MAC_STATUS_CFG_CHANGED));
3928                         return 0;
3929                 }
3930         }
3931
3932         tw32_f(MAC_TX_AUTO_NEG, 0);
3933
3934         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3935         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3936         tw32_f(MAC_MODE, tp->mac_mode);
3937         udelay(40);
3938
3939         if (tp->phy_id == TG3_PHY_ID_BCM8002)
3940                 tg3_init_bcm8002(tp);
3941
3942         /* Enable link change event even when serdes polling.  */
3943         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3944         udelay(40);
3945
3946         current_link_up = 0;
3947         mac_status = tr32(MAC_STATUS);
3948
3949         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3950                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3951         else
3952                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3953
3954         tp->napi[0].hw_status->status =
3955                 (SD_STATUS_UPDATED |
3956                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3957
3958         for (i = 0; i < 100; i++) {
3959                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3960                                     MAC_STATUS_CFG_CHANGED));
3961                 udelay(5);
3962                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3963                                          MAC_STATUS_CFG_CHANGED |
3964                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3965                         break;
3966         }
3967
3968         mac_status = tr32(MAC_STATUS);
3969         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3970                 current_link_up = 0;
3971                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3972                     tp->serdes_counter == 0) {
3973                         tw32_f(MAC_MODE, (tp->mac_mode |
3974                                           MAC_MODE_SEND_CONFIGS));
3975                         udelay(1);
3976                         tw32_f(MAC_MODE, tp->mac_mode);
3977                 }
3978         }
3979
3980         if (current_link_up == 1) {
3981                 tp->link_config.active_speed = SPEED_1000;
3982                 tp->link_config.active_duplex = DUPLEX_FULL;
3983                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3984                                     LED_CTRL_LNKLED_OVERRIDE |
3985                                     LED_CTRL_1000MBPS_ON));
3986         } else {
3987                 tp->link_config.active_speed = SPEED_INVALID;
3988                 tp->link_config.active_duplex = DUPLEX_INVALID;
3989                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3990                                     LED_CTRL_LNKLED_OVERRIDE |
3991                                     LED_CTRL_TRAFFIC_OVERRIDE));
3992         }
3993
3994         if (current_link_up != netif_carrier_ok(tp->dev)) {
3995                 if (current_link_up)
3996                         netif_carrier_on(tp->dev);
3997                 else
3998                         netif_carrier_off(tp->dev);
3999                 tg3_link_report(tp);
4000         } else {
4001                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4002                 if (orig_pause_cfg != now_pause_cfg ||
4003                     orig_active_speed != tp->link_config.active_speed ||
4004                     orig_active_duplex != tp->link_config.active_duplex)
4005                         tg3_link_report(tp);
4006         }
4007
4008         return 0;
4009 }
4010
4011 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4012 {
4013         int current_link_up, err = 0;
4014         u32 bmsr, bmcr;
4015         u16 current_speed;
4016         u8 current_duplex;
4017         u32 local_adv, remote_adv;
4018
4019         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4020         tw32_f(MAC_MODE, tp->mac_mode);
4021         udelay(40);
4022
4023         tw32(MAC_EVENT, 0);
4024
4025         tw32_f(MAC_STATUS,
4026              (MAC_STATUS_SYNC_CHANGED |
4027               MAC_STATUS_CFG_CHANGED |
4028               MAC_STATUS_MI_COMPLETION |
4029               MAC_STATUS_LNKSTATE_CHANGED));
4030         udelay(40);
4031
4032         if (force_reset)
4033                 tg3_phy_reset(tp);
4034
4035         current_link_up = 0;
4036         current_speed = SPEED_INVALID;
4037         current_duplex = DUPLEX_INVALID;
4038
4039         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4040         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4041         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4042                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4043                         bmsr |= BMSR_LSTATUS;
4044                 else
4045                         bmsr &= ~BMSR_LSTATUS;
4046         }
4047
4048         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4049
4050         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4051             (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4052                 /* do nothing, just check for link up at the end */
4053         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4054                 u32 adv, new_adv;
4055
4056                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4057                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4058                                   ADVERTISE_1000XPAUSE |
4059                                   ADVERTISE_1000XPSE_ASYM |
4060                                   ADVERTISE_SLCT);
4061
4062                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4063
4064                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4065                         new_adv |= ADVERTISE_1000XHALF;
4066                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4067                         new_adv |= ADVERTISE_1000XFULL;
4068
4069                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4070                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4071                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4072                         tg3_writephy(tp, MII_BMCR, bmcr);
4073
4074                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4075                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4076                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4077
4078                         return err;
4079                 }
4080         } else {
4081                 u32 new_bmcr;
4082
4083                 bmcr &= ~BMCR_SPEED1000;
4084                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4085
4086                 if (tp->link_config.duplex == DUPLEX_FULL)
4087                         new_bmcr |= BMCR_FULLDPLX;
4088
4089                 if (new_bmcr != bmcr) {
4090                         /* BMCR_SPEED1000 is a reserved bit that needs
4091                          * to be set on write.
4092                          */
4093                         new_bmcr |= BMCR_SPEED1000;
4094
4095                         /* Force a linkdown */
4096                         if (netif_carrier_ok(tp->dev)) {
4097                                 u32 adv;
4098
4099                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4100                                 adv &= ~(ADVERTISE_1000XFULL |
4101                                          ADVERTISE_1000XHALF |
4102                                          ADVERTISE_SLCT);
4103                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4104                                 tg3_writephy(tp, MII_BMCR, bmcr |
4105                                                            BMCR_ANRESTART |
4106                                                            BMCR_ANENABLE);
4107                                 udelay(10);
4108                                 netif_carrier_off(tp->dev);
4109                         }
4110                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4111                         bmcr = new_bmcr;
4112                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4113                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4114                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4115                             ASIC_REV_5714) {
4116                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4117                                         bmsr |= BMSR_LSTATUS;
4118                                 else
4119                                         bmsr &= ~BMSR_LSTATUS;
4120                         }
4121                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4122                 }
4123         }
4124
4125         if (bmsr & BMSR_LSTATUS) {
4126                 current_speed = SPEED_1000;
4127                 current_link_up = 1;
4128                 if (bmcr & BMCR_FULLDPLX)
4129                         current_duplex = DUPLEX_FULL;
4130                 else
4131                         current_duplex = DUPLEX_HALF;
4132
4133                 local_adv = 0;
4134                 remote_adv = 0;
4135
4136                 if (bmcr & BMCR_ANENABLE) {
4137                         u32 common;
4138
4139                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4140                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4141                         common = local_adv & remote_adv;
4142                         if (common & (ADVERTISE_1000XHALF |
4143                                       ADVERTISE_1000XFULL)) {
4144                                 if (common & ADVERTISE_1000XFULL)
4145                                         current_duplex = DUPLEX_FULL;
4146                                 else
4147                                         current_duplex = DUPLEX_HALF;
4148                         } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4149                                 /* Link is up via parallel detect */
4150                         } else {
4151                                 current_link_up = 0;
4152                         }
4153                 }
4154         }
4155
4156         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4157                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4158
4159         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4160         if (tp->link_config.active_duplex == DUPLEX_HALF)
4161                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4162
4163         tw32_f(MAC_MODE, tp->mac_mode);
4164         udelay(40);
4165
4166         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4167
4168         tp->link_config.active_speed = current_speed;
4169         tp->link_config.active_duplex = current_duplex;
4170
4171         if (current_link_up != netif_carrier_ok(tp->dev)) {
4172                 if (current_link_up)
4173                         netif_carrier_on(tp->dev);
4174                 else {
4175                         netif_carrier_off(tp->dev);
4176                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4177                 }
4178                 tg3_link_report(tp);
4179         }
4180         return err;
4181 }
4182
4183 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4184 {
4185         if (tp->serdes_counter) {
4186                 /* Give autoneg time to complete. */
4187                 tp->serdes_counter--;
4188                 return;
4189         }
4190
4191         if (!netif_carrier_ok(tp->dev) &&
4192             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4193                 u32 bmcr;
4194
4195                 tg3_readphy(tp, MII_BMCR, &bmcr);
4196                 if (bmcr & BMCR_ANENABLE) {
4197                         u32 phy1, phy2;
4198
4199                         /* Select shadow register 0x1f */
4200                         tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
4201                         tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
4202
4203                         /* Select expansion interrupt status register */
4204                         tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4205                                          MII_TG3_DSP_EXP1_INT_STAT);
4206                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4207                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4208
4209                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4210                                 /* We have signal detect and not receiving
4211                                  * config code words, link is up by parallel
4212                                  * detection.
4213                                  */
4214
4215                                 bmcr &= ~BMCR_ANENABLE;
4216                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4217                                 tg3_writephy(tp, MII_BMCR, bmcr);
4218                                 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
4219                         }
4220                 }
4221         } else if (netif_carrier_ok(tp->dev) &&
4222                    (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4223                    (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4224                 u32 phy2;
4225
4226                 /* Select expansion interrupt status register */
4227                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4228                                  MII_TG3_DSP_EXP1_INT_STAT);
4229                 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4230                 if (phy2 & 0x20) {
4231                         u32 bmcr;
4232
4233                         /* Config code words received, turn on autoneg. */
4234                         tg3_readphy(tp, MII_BMCR, &bmcr);
4235                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4236
4237                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4238
4239                 }
4240         }
4241 }
4242
4243 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4244 {
4245         int err;
4246
4247         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
4248                 err = tg3_setup_fiber_phy(tp, force_reset);
4249         else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4250                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4251         else
4252                 err = tg3_setup_copper_phy(tp, force_reset);
4253
4254         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4255                 u32 val, scale;
4256
4257                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4258                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4259                         scale = 65;
4260                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4261                         scale = 6;
4262                 else
4263                         scale = 12;
4264
4265                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4266                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4267                 tw32(GRC_MISC_CFG, val);
4268         }
4269
4270         if (tp->link_config.active_speed == SPEED_1000 &&
4271             tp->link_config.active_duplex == DUPLEX_HALF)
4272                 tw32(MAC_TX_LENGTHS,
4273                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4274                       (6 << TX_LENGTHS_IPG_SHIFT) |
4275                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4276         else
4277                 tw32(MAC_TX_LENGTHS,
4278                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4279                       (6 << TX_LENGTHS_IPG_SHIFT) |
4280                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4281
4282         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4283                 if (netif_carrier_ok(tp->dev)) {
4284                         tw32(HOSTCC_STAT_COAL_TICKS,
4285                              tp->coal.stats_block_coalesce_usecs);
4286                 } else {
4287                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4288                 }
4289         }
4290
4291         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4292                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4293                 if (!netif_carrier_ok(tp->dev))
4294                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4295                               tp->pwrmgmt_thresh;
4296                 else
4297                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4298                 tw32(PCIE_PWR_MGMT_THRESH, val);
4299         }
4300
4301         return err;
4302 }
4303
4304 static inline int tg3_irq_sync(struct tg3 *tp)
4305 {
4306         return tp->irq_sync;
4307 }
4308
4309 /* This is called whenever we suspect that the system chipset is re-
4310  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4311  * is bogus tx completions. We try to recover by setting the
4312  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4313  * in the workqueue.
4314  */
4315 static void tg3_tx_recover(struct tg3 *tp)
4316 {
4317         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4318                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4319
4320         netdev_warn(tp->dev,
4321                     "The system may be re-ordering memory-mapped I/O "
4322                     "cycles to the network device, attempting to recover. "
4323                     "Please report the problem to the driver maintainer "
4324                     "and include system chipset information.\n");
4325
4326         spin_lock(&tp->lock);
4327         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4328         spin_unlock(&tp->lock);
4329 }
4330
4331 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4332 {
4333         /* Tell compiler to fetch tx indices from memory. */
4334         barrier();
4335         return tnapi->tx_pending -
4336                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4337 }
4338
4339 /* Tigon3 never reports partial packet sends.  So we do not
4340  * need special logic to handle SKBs that have not had all
4341  * of their frags sent yet, like SunGEM does.
4342  */
4343 static void tg3_tx(struct tg3_napi *tnapi)
4344 {
4345         struct tg3 *tp = tnapi->tp;
4346         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4347         u32 sw_idx = tnapi->tx_cons;
4348         struct netdev_queue *txq;
4349         int index = tnapi - tp->napi;
4350
4351         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4352                 index--;
4353
4354         txq = netdev_get_tx_queue(tp->dev, index);
4355
4356         while (sw_idx != hw_idx) {
4357                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4358                 struct sk_buff *skb = ri->skb;
4359                 int i, tx_bug = 0;
4360
4361                 if (unlikely(skb == NULL)) {
4362                         tg3_tx_recover(tp);
4363                         return;
4364                 }
4365
4366                 pci_unmap_single(tp->pdev,
4367                                  dma_unmap_addr(ri, mapping),
4368                                  skb_headlen(skb),
4369                                  PCI_DMA_TODEVICE);
4370
4371                 ri->skb = NULL;
4372
4373                 sw_idx = NEXT_TX(sw_idx);
4374
4375                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4376                         ri = &tnapi->tx_buffers[sw_idx];
4377                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4378                                 tx_bug = 1;
4379
4380                         pci_unmap_page(tp->pdev,
4381                                        dma_unmap_addr(ri, mapping),
4382                                        skb_shinfo(skb)->frags[i].size,
4383                                        PCI_DMA_TODEVICE);
4384                         sw_idx = NEXT_TX(sw_idx);
4385                 }
4386
4387                 dev_kfree_skb(skb);
4388
4389                 if (unlikely(tx_bug)) {
4390                         tg3_tx_recover(tp);
4391                         return;
4392                 }
4393         }
4394
4395         tnapi->tx_cons = sw_idx;
4396
4397         /* Need to make the tx_cons update visible to tg3_start_xmit()
4398          * before checking for netif_queue_stopped().  Without the
4399          * memory barrier, there is a small possibility that tg3_start_xmit()
4400          * will miss it and cause the queue to be stopped forever.
4401          */
4402         smp_mb();
4403
4404         if (unlikely(netif_tx_queue_stopped(txq) &&
4405                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4406                 __netif_tx_lock(txq, smp_processor_id());
4407                 if (netif_tx_queue_stopped(txq) &&
4408                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4409                         netif_tx_wake_queue(txq);
4410                 __netif_tx_unlock(txq);
4411         }
4412 }
4413
4414 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4415 {
4416         if (!ri->skb)
4417                 return;
4418
4419         pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4420                          map_sz, PCI_DMA_FROMDEVICE);
4421         dev_kfree_skb_any(ri->skb);
4422         ri->skb = NULL;
4423 }
4424
4425 /* Returns size of skb allocated or < 0 on error.
4426  *
4427  * We only need to fill in the address because the other members
4428  * of the RX descriptor are invariant, see tg3_init_rings.
4429  *
4430  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4431  * posting buffers we only dirty the first cache line of the RX
4432  * descriptor (containing the address).  Whereas for the RX status
4433  * buffers the cpu only reads the last cacheline of the RX descriptor
4434  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4435  */
4436 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4437                             u32 opaque_key, u32 dest_idx_unmasked)
4438 {
4439         struct tg3_rx_buffer_desc *desc;
4440         struct ring_info *map, *src_map;
4441         struct sk_buff *skb;
4442         dma_addr_t mapping;
4443         int skb_size, dest_idx;
4444
4445         src_map = NULL;
4446         switch (opaque_key) {
4447         case RXD_OPAQUE_RING_STD:
4448                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4449                 desc = &tpr->rx_std[dest_idx];
4450                 map = &tpr->rx_std_buffers[dest_idx];
4451                 skb_size = tp->rx_pkt_map_sz;
4452                 break;
4453
4454         case RXD_OPAQUE_RING_JUMBO:
4455                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4456                 desc = &tpr->rx_jmb[dest_idx].std;
4457                 map = &tpr->rx_jmb_buffers[dest_idx];
4458                 skb_size = TG3_RX_JMB_MAP_SZ;
4459                 break;
4460
4461         default:
4462                 return -EINVAL;
4463         }
4464
4465         /* Do not overwrite any of the map or rp information
4466          * until we are sure we can commit to a new buffer.
4467          *
4468          * Callers depend upon this behavior and assume that
4469          * we leave everything unchanged if we fail.
4470          */
4471         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4472         if (skb == NULL)
4473                 return -ENOMEM;
4474
4475         skb_reserve(skb, tp->rx_offset);
4476
4477         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4478                                  PCI_DMA_FROMDEVICE);
4479         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4480                 dev_kfree_skb(skb);
4481                 return -EIO;
4482         }
4483
4484         map->skb = skb;
4485         dma_unmap_addr_set(map, mapping, mapping);
4486
4487         desc->addr_hi = ((u64)mapping >> 32);
4488         desc->addr_lo = ((u64)mapping & 0xffffffff);
4489
4490         return skb_size;
4491 }
4492
4493 /* We only need to move over in the address because the other
4494  * members of the RX descriptor are invariant.  See notes above
4495  * tg3_alloc_rx_skb for full details.
4496  */
4497 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4498                            struct tg3_rx_prodring_set *dpr,
4499                            u32 opaque_key, int src_idx,
4500                            u32 dest_idx_unmasked)
4501 {
4502         struct tg3 *tp = tnapi->tp;
4503         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4504         struct ring_info *src_map, *dest_map;
4505         struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
4506         int dest_idx;
4507
4508         switch (opaque_key) {
4509         case RXD_OPAQUE_RING_STD:
4510                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4511                 dest_desc = &dpr->rx_std[dest_idx];
4512                 dest_map = &dpr->rx_std_buffers[dest_idx];
4513                 src_desc = &spr->rx_std[src_idx];
4514                 src_map = &spr->rx_std_buffers[src_idx];
4515                 break;
4516
4517         case RXD_OPAQUE_RING_JUMBO:
4518                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4519                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4520                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4521                 src_desc = &spr->rx_jmb[src_idx].std;
4522                 src_map = &spr->rx_jmb_buffers[src_idx];
4523                 break;
4524
4525         default:
4526                 return;
4527         }
4528
4529         dest_map->skb = src_map->skb;
4530         dma_unmap_addr_set(dest_map, mapping,
4531                            dma_unmap_addr(src_map, mapping));
4532         dest_desc->addr_hi = src_desc->addr_hi;
4533         dest_desc->addr_lo = src_desc->addr_lo;
4534
4535         /* Ensure that the update to the skb happens after the physical
4536          * addresses have been transferred to the new BD location.
4537          */
4538         smp_wmb();
4539
4540         src_map->skb = NULL;
4541 }
4542
4543 /* The RX ring scheme is composed of multiple rings which post fresh
4544  * buffers to the chip, and one special ring the chip uses to report
4545  * status back to the host.
4546  *
4547  * The special ring reports the status of received packets to the
4548  * host.  The chip does not write into the original descriptor the
4549  * RX buffer was obtained from.  The chip simply takes the original
4550  * descriptor as provided by the host, updates the status and length
4551  * field, then writes this into the next status ring entry.
4552  *
4553  * Each ring the host uses to post buffers to the chip is described
4554  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4555  * it is first placed into the on-chip ram.  When the packet's length
4556  * is known, it walks down the TG3_BDINFO entries to select the ring.
4557  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4558  * which is within the range of the new packet's length is chosen.
4559  *
4560  * The "separate ring for rx status" scheme may sound queer, but it makes
4561  * sense from a cache coherency perspective.  If only the host writes
4562  * to the buffer post rings, and only the chip writes to the rx status
4563  * rings, then cache lines never move beyond shared-modified state.
4564  * If both the host and chip were to write into the same ring, cache line
4565  * eviction could occur since both entities want it in an exclusive state.
4566  */
4567 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4568 {
4569         struct tg3 *tp = tnapi->tp;
4570         u32 work_mask, rx_std_posted = 0;
4571         u32 std_prod_idx, jmb_prod_idx;
4572         u32 sw_idx = tnapi->rx_rcb_ptr;
4573         u16 hw_idx;
4574         int received;
4575         struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
4576
4577         hw_idx = *(tnapi->rx_rcb_prod_idx);
4578         /*
4579          * We need to order the read of hw_idx and the read of
4580          * the opaque cookie.
4581          */
4582         rmb();
4583         work_mask = 0;
4584         received = 0;
4585         std_prod_idx = tpr->rx_std_prod_idx;
4586         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4587         while (sw_idx != hw_idx && budget > 0) {
4588                 struct ring_info *ri;
4589                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4590                 unsigned int len;
4591                 struct sk_buff *skb;
4592                 dma_addr_t dma_addr;
4593                 u32 opaque_key, desc_idx, *post_ptr;
4594                 bool hw_vlan __maybe_unused = false;
4595                 u16 vtag __maybe_unused = 0;
4596
4597                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4598                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4599                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4600                         ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4601                         dma_addr = dma_unmap_addr(ri, mapping);
4602                         skb = ri->skb;
4603                         post_ptr = &std_prod_idx;
4604                         rx_std_posted++;
4605                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4606                         ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4607                         dma_addr = dma_unmap_addr(ri, mapping);
4608                         skb = ri->skb;
4609                         post_ptr = &jmb_prod_idx;
4610                 } else
4611                         goto next_pkt_nopost;
4612
4613                 work_mask |= opaque_key;
4614
4615                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4616                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4617                 drop_it:
4618                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4619                                        desc_idx, *post_ptr);
4620                 drop_it_no_recycle:
4621                         /* Other statistics kept track of by card. */
4622                         tp->net_stats.rx_dropped++;
4623                         goto next_pkt;
4624                 }
4625
4626                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4627                       ETH_FCS_LEN;
4628
4629                 if (len > TG3_RX_COPY_THRESH(tp)) {
4630                         int skb_size;
4631
4632                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4633                                                     *post_ptr);
4634                         if (skb_size < 0)
4635                                 goto drop_it;
4636
4637                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4638                                          PCI_DMA_FROMDEVICE);
4639
4640                         /* Ensure that the update to the skb happens
4641                          * after the usage of the old DMA mapping.
4642                          */
4643                         smp_wmb();
4644
4645                         ri->skb = NULL;
4646
4647                         skb_put(skb, len);
4648                 } else {
4649                         struct sk_buff *copy_skb;
4650
4651                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4652                                        desc_idx, *post_ptr);
4653
4654                         copy_skb = netdev_alloc_skb(tp->dev, len + VLAN_HLEN +
4655                                                     TG3_RAW_IP_ALIGN);
4656                         if (copy_skb == NULL)
4657                                 goto drop_it_no_recycle;
4658
4659                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN + VLAN_HLEN);
4660                         skb_put(copy_skb, len);
4661                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4662                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4663                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4664
4665                         /* We'll reuse the original ring buffer. */
4666                         skb = copy_skb;
4667                 }
4668
4669                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4670                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4671                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4672                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4673                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4674                 else
4675                         skb_checksum_none_assert(skb);
4676
4677                 skb->protocol = eth_type_trans(skb, tp->dev);
4678
4679                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4680                     skb->protocol != htons(ETH_P_8021Q)) {
4681                         dev_kfree_skb(skb);
4682                         goto next_pkt;
4683                 }
4684
4685                 if (desc->type_flags & RXD_FLAG_VLAN &&
4686                     !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) {
4687                         vtag = desc->err_vlan & RXD_VLAN_MASK;
4688 #if TG3_VLAN_TAG_USED
4689                         if (tp->vlgrp)
4690                                 hw_vlan = true;
4691                         else
4692 #endif
4693                         {
4694                                 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
4695                                                     __skb_push(skb, VLAN_HLEN);
4696
4697                                 memmove(ve, skb->data + VLAN_HLEN,
4698                                         ETH_ALEN * 2);
4699                                 ve->h_vlan_proto = htons(ETH_P_8021Q);
4700                                 ve->h_vlan_TCI = htons(vtag);
4701                         }
4702                 }
4703
4704 #if TG3_VLAN_TAG_USED
4705                 if (hw_vlan)
4706                         vlan_gro_receive(&tnapi->napi, tp->vlgrp, vtag, skb);
4707                 else
4708 #endif
4709                         napi_gro_receive(&tnapi->napi, skb);
4710
4711                 received++;
4712                 budget--;
4713
4714 next_pkt:
4715                 (*post_ptr)++;
4716
4717                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4718                         tpr->rx_std_prod_idx = std_prod_idx &
4719                                                tp->rx_std_ring_mask;
4720                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4721                                      tpr->rx_std_prod_idx);
4722                         work_mask &= ~RXD_OPAQUE_RING_STD;
4723                         rx_std_posted = 0;
4724                 }
4725 next_pkt_nopost:
4726                 sw_idx++;
4727                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4728
4729                 /* Refresh hw_idx to see if there is new work */
4730                 if (sw_idx == hw_idx) {
4731                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4732                         rmb();
4733                 }
4734         }
4735
4736         /* ACK the status ring. */
4737         tnapi->rx_rcb_ptr = sw_idx;
4738         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4739
4740         /* Refill RX ring(s). */
4741         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4742                 if (work_mask & RXD_OPAQUE_RING_STD) {
4743                         tpr->rx_std_prod_idx = std_prod_idx &
4744                                                tp->rx_std_ring_mask;
4745                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4746                                      tpr->rx_std_prod_idx);
4747                 }
4748                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4749                         tpr->rx_jmb_prod_idx = jmb_prod_idx &
4750                                                tp->rx_jmb_ring_mask;
4751                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4752                                      tpr->rx_jmb_prod_idx);
4753                 }
4754                 mmiowb();
4755         } else if (work_mask) {
4756                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4757                  * updated before the producer indices can be updated.
4758                  */
4759                 smp_wmb();
4760
4761                 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
4762                 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
4763
4764                 if (tnapi != &tp->napi[1])
4765                         napi_schedule(&tp->napi[1].napi);
4766         }
4767
4768         return received;
4769 }
4770
4771 static void tg3_poll_link(struct tg3 *tp)
4772 {
4773         /* handle link change and other phy events */
4774         if (!(tp->tg3_flags &
4775               (TG3_FLAG_USE_LINKCHG_REG |
4776                TG3_FLAG_POLL_SERDES))) {
4777                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4778
4779                 if (sblk->status & SD_STATUS_LINK_CHG) {
4780                         sblk->status = SD_STATUS_UPDATED |
4781                                        (sblk->status & ~SD_STATUS_LINK_CHG);
4782                         spin_lock(&tp->lock);
4783                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4784                                 tw32_f(MAC_STATUS,
4785                                      (MAC_STATUS_SYNC_CHANGED |
4786                                       MAC_STATUS_CFG_CHANGED |
4787                                       MAC_STATUS_MI_COMPLETION |
4788                                       MAC_STATUS_LNKSTATE_CHANGED));
4789                                 udelay(40);
4790                         } else
4791                                 tg3_setup_phy(tp, 0);
4792                         spin_unlock(&tp->lock);
4793                 }
4794         }
4795 }
4796
4797 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4798                                 struct tg3_rx_prodring_set *dpr,
4799                                 struct tg3_rx_prodring_set *spr)
4800 {
4801         u32 si, di, cpycnt, src_prod_idx;
4802         int i, err = 0;
4803
4804         while (1) {
4805                 src_prod_idx = spr->rx_std_prod_idx;
4806
4807                 /* Make sure updates to the rx_std_buffers[] entries and the
4808                  * standard producer index are seen in the correct order.
4809                  */
4810                 smp_rmb();
4811
4812                 if (spr->rx_std_cons_idx == src_prod_idx)
4813                         break;
4814
4815                 if (spr->rx_std_cons_idx < src_prod_idx)
4816                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4817                 else
4818                         cpycnt = tp->rx_std_ring_mask + 1 -
4819                                  spr->rx_std_cons_idx;
4820
4821                 cpycnt = min(cpycnt,
4822                              tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
4823
4824                 si = spr->rx_std_cons_idx;
4825                 di = dpr->rx_std_prod_idx;
4826
4827                 for (i = di; i < di + cpycnt; i++) {
4828                         if (dpr->rx_std_buffers[i].skb) {
4829                                 cpycnt = i - di;
4830                                 err = -ENOSPC;
4831                                 break;
4832                         }
4833                 }
4834
4835                 if (!cpycnt)
4836                         break;
4837
4838                 /* Ensure that updates to the rx_std_buffers ring and the
4839                  * shadowed hardware producer ring from tg3_recycle_skb() are
4840                  * ordered correctly WRT the skb check above.
4841                  */
4842                 smp_rmb();
4843
4844                 memcpy(&dpr->rx_std_buffers[di],
4845                        &spr->rx_std_buffers[si],
4846                        cpycnt * sizeof(struct ring_info));
4847
4848                 for (i = 0; i < cpycnt; i++, di++, si++) {
4849                         struct tg3_rx_buffer_desc *sbd, *dbd;
4850                         sbd = &spr->rx_std[si];
4851                         dbd = &dpr->rx_std[di];
4852                         dbd->addr_hi = sbd->addr_hi;
4853                         dbd->addr_lo = sbd->addr_lo;
4854                 }
4855
4856                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
4857                                        tp->rx_std_ring_mask;
4858                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
4859                                        tp->rx_std_ring_mask;
4860         }
4861
4862         while (1) {
4863                 src_prod_idx = spr->rx_jmb_prod_idx;
4864
4865                 /* Make sure updates to the rx_jmb_buffers[] entries and
4866                  * the jumbo producer index are seen in the correct order.
4867                  */
4868                 smp_rmb();
4869
4870                 if (spr->rx_jmb_cons_idx == src_prod_idx)
4871                         break;
4872
4873                 if (spr->rx_jmb_cons_idx < src_prod_idx)
4874                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4875                 else
4876                         cpycnt = tp->rx_jmb_ring_mask + 1 -
4877                                  spr->rx_jmb_cons_idx;
4878
4879                 cpycnt = min(cpycnt,
4880                              tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
4881
4882                 si = spr->rx_jmb_cons_idx;
4883                 di = dpr->rx_jmb_prod_idx;
4884
4885                 for (i = di; i < di + cpycnt; i++) {
4886                         if (dpr->rx_jmb_buffers[i].skb) {
4887                                 cpycnt = i - di;
4888                                 err = -ENOSPC;
4889                                 break;
4890                         }
4891                 }
4892
4893                 if (!cpycnt)
4894                         break;
4895
4896                 /* Ensure that updates to the rx_jmb_buffers ring and the
4897                  * shadowed hardware producer ring from tg3_recycle_skb() are
4898                  * ordered correctly WRT the skb check above.
4899                  */
4900                 smp_rmb();
4901
4902                 memcpy(&dpr->rx_jmb_buffers[di],
4903                        &spr->rx_jmb_buffers[si],
4904                        cpycnt * sizeof(struct ring_info));
4905
4906                 for (i = 0; i < cpycnt; i++, di++, si++) {
4907                         struct tg3_rx_buffer_desc *sbd, *dbd;
4908                         sbd = &spr->rx_jmb[si].std;
4909                         dbd = &dpr->rx_jmb[di].std;
4910                         dbd->addr_hi = sbd->addr_hi;
4911                         dbd->addr_lo = sbd->addr_lo;
4912                 }
4913
4914                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
4915                                        tp->rx_jmb_ring_mask;
4916                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
4917                                        tp->rx_jmb_ring_mask;
4918         }
4919
4920         return err;
4921 }
4922
4923 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4924 {
4925         struct tg3 *tp = tnapi->tp;
4926
4927         /* run TX completion thread */
4928         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4929                 tg3_tx(tnapi);
4930                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4931                         return work_done;
4932         }
4933
4934         /* run RX thread, within the bounds set by NAPI.
4935          * All RX "locking" is done by ensuring outside
4936          * code synchronizes with tg3->napi.poll()
4937          */
4938         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4939                 work_done += tg3_rx(tnapi, budget - work_done);
4940
4941         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4942                 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
4943                 int i, err = 0;
4944                 u32 std_prod_idx = dpr->rx_std_prod_idx;
4945                 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
4946
4947                 for (i = 1; i < tp->irq_cnt; i++)
4948                         err |= tg3_rx_prodring_xfer(tp, dpr,
4949                                                     &tp->napi[i].prodring);
4950
4951                 wmb();
4952
4953                 if (std_prod_idx != dpr->rx_std_prod_idx)
4954                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4955                                      dpr->rx_std_prod_idx);
4956
4957                 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
4958                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4959                                      dpr->rx_jmb_prod_idx);
4960
4961                 mmiowb();
4962
4963                 if (err)
4964                         tw32_f(HOSTCC_MODE, tp->coal_now);
4965         }
4966
4967         return work_done;
4968 }
4969
4970 static int tg3_poll_msix(struct napi_struct *napi, int budget)
4971 {
4972         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4973         struct tg3 *tp = tnapi->tp;
4974         int work_done = 0;
4975         struct tg3_hw_status *sblk = tnapi->hw_status;
4976
4977         while (1) {
4978                 work_done = tg3_poll_work(tnapi, work_done, budget);
4979
4980                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4981                         goto tx_recovery;
4982
4983                 if (unlikely(work_done >= budget))
4984                         break;
4985
4986                 /* tp->last_tag is used in tg3_int_reenable() below
4987                  * to tell the hw how much work has been processed,
4988                  * so we must read it before checking for more work.
4989                  */
4990                 tnapi->last_tag = sblk->status_tag;
4991                 tnapi->last_irq_tag = tnapi->last_tag;
4992                 rmb();
4993
4994                 /* check for RX/TX work to do */
4995                 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
4996                            *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
4997                         napi_complete(napi);
4998                         /* Reenable interrupts. */
4999                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5000                         mmiowb();
5001                         break;
5002                 }
5003         }
5004
5005         return work_done;
5006
5007 tx_recovery:
5008         /* work_done is guaranteed to be less than budget. */
5009         napi_complete(napi);
5010         schedule_work(&tp->reset_task);
5011         return work_done;
5012 }
5013
5014 static int tg3_poll(struct napi_struct *napi, int budget)
5015 {
5016         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5017         struct tg3 *tp = tnapi->tp;
5018         int work_done = 0;
5019         struct tg3_hw_status *sblk = tnapi->hw_status;
5020
5021         while (1) {
5022                 tg3_poll_link(tp);
5023
5024                 work_done = tg3_poll_work(tnapi, work_done, budget);
5025
5026                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5027                         goto tx_recovery;
5028
5029                 if (unlikely(work_done >= budget))
5030                         break;
5031
5032                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5033                         /* tp->last_tag is used in tg3_int_reenable() below
5034                          * to tell the hw how much work has been processed,
5035                          * so we must read it before checking for more work.
5036                          */
5037                         tnapi->last_tag = sblk->status_tag;
5038                         tnapi->last_irq_tag = tnapi->last_tag;
5039                         rmb();
5040                 } else
5041                         sblk->status &= ~SD_STATUS_UPDATED;
5042
5043                 if (likely(!tg3_has_work(tnapi))) {
5044                         napi_complete(napi);
5045                         tg3_int_reenable(tnapi);
5046                         break;
5047                 }
5048         }
5049
5050         return work_done;
5051
5052 tx_recovery:
5053         /* work_done is guaranteed to be less than budget. */
5054         napi_complete(napi);
5055         schedule_work(&tp->reset_task);
5056         return work_done;
5057 }
5058
5059 static void tg3_napi_disable(struct tg3 *tp)
5060 {
5061         int i;
5062
5063         for (i = tp->irq_cnt - 1; i >= 0; i--)
5064                 napi_disable(&tp->napi[i].napi);
5065 }
5066
5067 static void tg3_napi_enable(struct tg3 *tp)
5068 {
5069         int i;
5070
5071         for (i = 0; i < tp->irq_cnt; i++)
5072                 napi_enable(&tp->napi[i].napi);
5073 }
5074
5075 static void tg3_napi_init(struct tg3 *tp)
5076 {
5077         int i;
5078
5079         netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
5080         for (i = 1; i < tp->irq_cnt; i++)
5081                 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
5082 }
5083
5084 static void tg3_napi_fini(struct tg3 *tp)
5085 {
5086         int i;
5087
5088         for (i = 0; i < tp->irq_cnt; i++)
5089                 netif_napi_del(&tp->napi[i].napi);
5090 }
5091
5092 static inline void tg3_netif_stop(struct tg3 *tp)
5093 {
5094         tp->dev->trans_start = jiffies; /* prevent tx timeout */
5095         tg3_napi_disable(tp);
5096         netif_tx_disable(tp->dev);
5097 }
5098
5099 static inline void tg3_netif_start(struct tg3 *tp)
5100 {
5101         /* NOTE: unconditional netif_tx_wake_all_queues is only
5102          * appropriate so long as all callers are assured to
5103          * have free tx slots (such as after tg3_init_hw)
5104          */
5105         netif_tx_wake_all_queues(tp->dev);
5106
5107         tg3_napi_enable(tp);
5108         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
5109         tg3_enable_ints(tp);
5110 }
5111
5112 static void tg3_irq_quiesce(struct tg3 *tp)
5113 {
5114         int i;
5115
5116         BUG_ON(tp->irq_sync);
5117
5118         tp->irq_sync = 1;
5119         smp_mb();
5120
5121         for (i = 0; i < tp->irq_cnt; i++)
5122                 synchronize_irq(tp->napi[i].irq_vec);
5123 }
5124
5125 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5126  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5127  * with as well.  Most of the time, this is not necessary except when
5128  * shutting down the device.
5129  */
5130 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5131 {
5132         spin_lock_bh(&tp->lock);
5133         if (irq_sync)
5134                 tg3_irq_quiesce(tp);
5135 }
5136
5137 static inline void tg3_full_unlock(struct tg3 *tp)
5138 {
5139         spin_unlock_bh(&tp->lock);
5140 }
5141
5142 /* One-shot MSI handler - Chip automatically disables interrupt
5143  * after sending MSI so driver doesn't have to do it.
5144  */
5145 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5146 {
5147         struct tg3_napi *tnapi = dev_id;
5148         struct tg3 *tp = tnapi->tp;
5149
5150         prefetch(tnapi->hw_status);
5151         if (tnapi->rx_rcb)
5152                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5153
5154         if (likely(!tg3_irq_sync(tp)))
5155                 napi_schedule(&tnapi->napi);
5156
5157         return IRQ_HANDLED;
5158 }
5159
5160 /* MSI ISR - No need to check for interrupt sharing and no need to
5161  * flush status block and interrupt mailbox. PCI ordering rules
5162  * guarantee that MSI will arrive after the status block.
5163  */
5164 static irqreturn_t tg3_msi(int irq, void *dev_id)
5165 {
5166         struct tg3_napi *tnapi = dev_id;
5167         struct tg3 *tp = tnapi->tp;
5168
5169         prefetch(tnapi->hw_status);
5170         if (tnapi->rx_rcb)
5171                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5172         /*
5173          * Writing any value to intr-mbox-0 clears PCI INTA# and
5174          * chip-internal interrupt pending events.
5175          * Writing non-zero to intr-mbox-0 additional tells the
5176          * NIC to stop sending us irqs, engaging "in-intr-handler"
5177          * event coalescing.
5178          */
5179         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5180         if (likely(!tg3_irq_sync(tp)))
5181                 napi_schedule(&tnapi->napi);
5182
5183         return IRQ_RETVAL(1);
5184 }
5185
5186 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5187 {
5188         struct tg3_napi *tnapi = dev_id;
5189         struct tg3 *tp = tnapi->tp;
5190         struct tg3_hw_status *sblk = tnapi->hw_status;
5191         unsigned int handled = 1;
5192
5193         /* In INTx mode, it is possible for the interrupt to arrive at
5194          * the CPU before the status block posted prior to the interrupt.
5195          * Reading the PCI State register will confirm whether the
5196          * interrupt is ours and will flush the status block.
5197          */
5198         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5199                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5200                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5201                         handled = 0;
5202                         goto out;
5203                 }
5204         }
5205
5206         /*
5207          * Writing any value to intr-mbox-0 clears PCI INTA# and
5208          * chip-internal interrupt pending events.
5209          * Writing non-zero to intr-mbox-0 additional tells the
5210          * NIC to stop sending us irqs, engaging "in-intr-handler"
5211          * event coalescing.
5212          *
5213          * Flush the mailbox to de-assert the IRQ immediately to prevent
5214          * spurious interrupts.  The flush impacts performance but
5215          * excessive spurious interrupts can be worse in some cases.
5216          */
5217         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5218         if (tg3_irq_sync(tp))
5219                 goto out;
5220         sblk->status &= ~SD_STATUS_UPDATED;
5221         if (likely(tg3_has_work(tnapi))) {
5222                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5223                 napi_schedule(&tnapi->napi);
5224         } else {
5225                 /* No work, shared interrupt perhaps?  re-enable
5226                  * interrupts, and flush that PCI write
5227                  */
5228                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5229                                0x00000000);
5230         }
5231 out:
5232         return IRQ_RETVAL(handled);
5233 }
5234
5235 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5236 {
5237         struct tg3_napi *tnapi = dev_id;
5238         struct tg3 *tp = tnapi->tp;
5239         struct tg3_hw_status *sblk = tnapi->hw_status;
5240         unsigned int handled = 1;
5241
5242         /* In INTx mode, it is possible for the interrupt to arrive at
5243          * the CPU before the status block posted prior to the interrupt.
5244          * Reading the PCI State register will confirm whether the
5245          * interrupt is ours and will flush the status block.
5246          */
5247         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5248                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5249                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5250                         handled = 0;
5251                         goto out;
5252                 }
5253         }
5254
5255         /*
5256          * writing any value to intr-mbox-0 clears PCI INTA# and
5257          * chip-internal interrupt pending events.
5258          * writing non-zero to intr-mbox-0 additional tells the
5259          * NIC to stop sending us irqs, engaging "in-intr-handler"
5260          * event coalescing.
5261          *
5262          * Flush the mailbox to de-assert the IRQ immediately to prevent
5263          * spurious interrupts.  The flush impacts performance but
5264          * excessive spurious interrupts can be worse in some cases.
5265          */
5266         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5267
5268         /*
5269          * In a shared interrupt configuration, sometimes other devices'
5270          * interrupts will scream.  We record the current status tag here
5271          * so that the above check can report that the screaming interrupts
5272          * are unhandled.  Eventually they will be silenced.
5273          */
5274         tnapi->last_irq_tag = sblk->status_tag;
5275
5276         if (tg3_irq_sync(tp))
5277                 goto out;
5278
5279         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5280
5281         napi_schedule(&tnapi->napi);
5282
5283 out:
5284         return IRQ_RETVAL(handled);
5285 }
5286
5287 /* ISR for interrupt test */
5288 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5289 {
5290         struct tg3_napi *tnapi = dev_id;
5291         struct tg3 *tp = tnapi->tp;
5292         struct tg3_hw_status *sblk = tnapi->hw_status;
5293
5294         if ((sblk->status & SD_STATUS_UPDATED) ||
5295             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5296                 tg3_disable_ints(tp);
5297                 return IRQ_RETVAL(1);
5298         }
5299         return IRQ_RETVAL(0);
5300 }
5301
5302 static int tg3_init_hw(struct tg3 *, int);
5303 static int tg3_halt(struct tg3 *, int, int);
5304
5305 /* Restart hardware after configuration changes, self-test, etc.
5306  * Invoked with tp->lock held.
5307  */
5308 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5309         __releases(tp->lock)
5310         __acquires(tp->lock)
5311 {
5312         int err;
5313
5314         err = tg3_init_hw(tp, reset_phy);
5315         if (err) {
5316                 netdev_err(tp->dev,
5317                            "Failed to re-initialize device, aborting\n");
5318                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5319                 tg3_full_unlock(tp);
5320                 del_timer_sync(&tp->timer);
5321                 tp->irq_sync = 0;
5322                 tg3_napi_enable(tp);
5323                 dev_close(tp->dev);
5324                 tg3_full_lock(tp, 0);
5325         }
5326         return err;
5327 }
5328
5329 #ifdef CONFIG_NET_POLL_CONTROLLER
5330 static void tg3_poll_controller(struct net_device *dev)
5331 {
5332         int i;
5333         struct tg3 *tp = netdev_priv(dev);
5334
5335         for (i = 0; i < tp->irq_cnt; i++)
5336                 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5337 }
5338 #endif
5339
5340 static void tg3_reset_task(struct work_struct *work)
5341 {
5342         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5343         int err;
5344         unsigned int restart_timer;
5345
5346         tg3_full_lock(tp, 0);
5347
5348         if (!netif_running(tp->dev)) {
5349                 tg3_full_unlock(tp);
5350                 return;
5351         }
5352
5353         tg3_full_unlock(tp);
5354
5355         tg3_phy_stop(tp);
5356
5357         tg3_netif_stop(tp);
5358
5359         tg3_full_lock(tp, 1);
5360
5361         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5362         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5363
5364         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5365                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5366                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5367                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5368                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5369         }
5370
5371         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5372         err = tg3_init_hw(tp, 1);
5373         if (err)
5374                 goto out;
5375
5376         tg3_netif_start(tp);
5377
5378         if (restart_timer)
5379                 mod_timer(&tp->timer, jiffies + 1);
5380
5381 out:
5382         tg3_full_unlock(tp);
5383
5384         if (!err)
5385                 tg3_phy_start(tp);
5386 }
5387
5388 static void tg3_dump_short_state(struct tg3 *tp)
5389 {
5390         netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5391                    tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5392         netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5393                    tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5394 }
5395
5396 static void tg3_tx_timeout(struct net_device *dev)
5397 {
5398         struct tg3 *tp = netdev_priv(dev);
5399
5400         if (netif_msg_tx_err(tp)) {
5401                 netdev_err(dev, "transmit timed out, resetting\n");
5402                 tg3_dump_short_state(tp);
5403         }
5404
5405         schedule_work(&tp->reset_task);
5406 }
5407
5408 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5409 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5410 {
5411         u32 base = (u32) mapping & 0xffffffff;
5412
5413         return (base > 0xffffdcc0) && (base + len + 8 < base);
5414 }
5415
5416 /* Test for DMA addresses > 40-bit */
5417 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5418                                           int len)
5419 {
5420 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5421         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5422                 return ((u64) mapping + len) > DMA_BIT_MASK(40);
5423         return 0;
5424 #else
5425         return 0;
5426 #endif
5427 }
5428
5429 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5430
5431 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5432 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5433                                        struct sk_buff *skb, u32 last_plus_one,
5434                                        u32 *start, u32 base_flags, u32 mss)
5435 {
5436         struct tg3 *tp = tnapi->tp;
5437         struct sk_buff *new_skb;
5438         dma_addr_t new_addr = 0;
5439         u32 entry = *start;
5440         int i, ret = 0;
5441
5442         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5443                 new_skb = skb_copy(skb, GFP_ATOMIC);
5444         else {
5445                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5446
5447                 new_skb = skb_copy_expand(skb,
5448                                           skb_headroom(skb) + more_headroom,
5449                                           skb_tailroom(skb), GFP_ATOMIC);
5450         }
5451
5452         if (!new_skb) {
5453                 ret = -1;
5454         } else {
5455                 /* New SKB is guaranteed to be linear. */
5456                 entry = *start;
5457                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5458                                           PCI_DMA_TODEVICE);
5459                 /* Make sure the mapping succeeded */
5460                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5461                         ret = -1;
5462                         dev_kfree_skb(new_skb);
5463                         new_skb = NULL;
5464
5465                 /* Make sure new skb does not cross any 4G boundaries.
5466                  * Drop the packet if it does.
5467                  */
5468                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5469                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5470                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5471                                          PCI_DMA_TODEVICE);
5472                         ret = -1;
5473                         dev_kfree_skb(new_skb);
5474                         new_skb = NULL;
5475                 } else {
5476                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5477                                     base_flags, 1 | (mss << 1));
5478                         *start = NEXT_TX(entry);
5479                 }
5480         }
5481
5482         /* Now clean up the sw ring entries. */
5483         i = 0;
5484         while (entry != last_plus_one) {
5485                 int len;
5486
5487                 if (i == 0)
5488                         len = skb_headlen(skb);
5489                 else
5490                         len = skb_shinfo(skb)->frags[i-1].size;
5491
5492                 pci_unmap_single(tp->pdev,
5493                                  dma_unmap_addr(&tnapi->tx_buffers[entry],
5494                                                 mapping),
5495                                  len, PCI_DMA_TODEVICE);
5496                 if (i == 0) {
5497                         tnapi->tx_buffers[entry].skb = new_skb;
5498                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5499                                            new_addr);
5500                 } else {
5501                         tnapi->tx_buffers[entry].skb = NULL;
5502                 }
5503                 entry = NEXT_TX(entry);
5504                 i++;
5505         }
5506
5507         dev_kfree_skb(skb);
5508
5509         return ret;
5510 }
5511
5512 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5513                         dma_addr_t mapping, int len, u32 flags,
5514                         u32 mss_and_is_end)
5515 {
5516         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5517         int is_end = (mss_and_is_end & 0x1);
5518         u32 mss = (mss_and_is_end >> 1);
5519         u32 vlan_tag = 0;
5520
5521         if (is_end)
5522                 flags |= TXD_FLAG_END;
5523         if (flags & TXD_FLAG_VLAN) {
5524                 vlan_tag = flags >> 16;
5525                 flags &= 0xffff;
5526         }
5527         vlan_tag |= (mss << TXD_MSS_SHIFT);
5528
5529         txd->addr_hi = ((u64) mapping >> 32);
5530         txd->addr_lo = ((u64) mapping & 0xffffffff);
5531         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5532         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5533 }
5534
5535 /* hard_start_xmit for devices that don't have any bugs and
5536  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5537  */
5538 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5539                                   struct net_device *dev)
5540 {
5541         struct tg3 *tp = netdev_priv(dev);
5542         u32 len, entry, base_flags, mss;
5543         dma_addr_t mapping;
5544         struct tg3_napi *tnapi;
5545         struct netdev_queue *txq;
5546         unsigned int i, last;
5547
5548         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5549         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5550         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5551                 tnapi++;
5552
5553         /* We are running in BH disabled context with netif_tx_lock
5554          * and TX reclaim runs via tp->napi.poll inside of a software
5555          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5556          * no IRQ context deadlocks to worry about either.  Rejoice!
5557          */
5558         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5559                 if (!netif_tx_queue_stopped(txq)) {
5560                         netif_tx_stop_queue(txq);
5561
5562                         /* This is a hard error, log it. */
5563                         netdev_err(dev,
5564                                    "BUG! Tx Ring full when queue awake!\n");
5565                 }
5566                 return NETDEV_TX_BUSY;
5567         }
5568
5569         entry = tnapi->tx_prod;
5570         base_flags = 0;
5571         mss = skb_shinfo(skb)->gso_size;
5572         if (mss) {
5573                 int tcp_opt_len, ip_tcp_len;
5574                 u32 hdrlen;
5575
5576                 if (skb_header_cloned(skb) &&
5577                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5578                         dev_kfree_skb(skb);
5579                         goto out_unlock;
5580                 }
5581
5582                 if (skb_is_gso_v6(skb)) {
5583                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5584                 } else {
5585                         struct iphdr *iph = ip_hdr(skb);
5586
5587                         tcp_opt_len = tcp_optlen(skb);
5588                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5589
5590                         iph->check = 0;
5591                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5592                         hdrlen = ip_tcp_len + tcp_opt_len;
5593                 }
5594
5595                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5596                         mss |= (hdrlen & 0xc) << 12;
5597                         if (hdrlen & 0x10)
5598                                 base_flags |= 0x00000010;
5599                         base_flags |= (hdrlen & 0x3e0) << 5;
5600                 } else
5601                         mss |= hdrlen << 9;
5602
5603                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5604                                TXD_FLAG_CPU_POST_DMA);
5605
5606                 tcp_hdr(skb)->check = 0;
5607
5608         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5609                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5610         }
5611
5612 #if TG3_VLAN_TAG_USED
5613         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5614                 base_flags |= (TXD_FLAG_VLAN |
5615                                (vlan_tx_tag_get(skb) << 16));
5616 #endif
5617
5618         len = skb_headlen(skb);
5619
5620         /* Queue skb data, a.k.a. the main skb fragment. */
5621         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5622         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5623                 dev_kfree_skb(skb);
5624                 goto out_unlock;
5625         }
5626
5627         tnapi->tx_buffers[entry].skb = skb;
5628         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5629
5630         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5631             !mss && skb->len > ETH_DATA_LEN)
5632                 base_flags |= TXD_FLAG_JMB_PKT;
5633
5634         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5635                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5636
5637         entry = NEXT_TX(entry);
5638
5639         /* Now loop through additional data fragments, and queue them. */
5640         if (skb_shinfo(skb)->nr_frags > 0) {
5641                 last = skb_shinfo(skb)->nr_frags - 1;
5642                 for (i = 0; i <= last; i++) {
5643                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5644
5645                         len = frag->size;
5646                         mapping = pci_map_page(tp->pdev,
5647                                                frag->page,
5648                                                frag->page_offset,
5649                                                len, PCI_DMA_TODEVICE);
5650                         if (pci_dma_mapping_error(tp->pdev, mapping))
5651                                 goto dma_error;
5652
5653                         tnapi->tx_buffers[entry].skb = NULL;
5654                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5655                                            mapping);
5656
5657                         tg3_set_txd(tnapi, entry, mapping, len,
5658                                     base_flags, (i == last) | (mss << 1));
5659
5660                         entry = NEXT_TX(entry);
5661                 }
5662         }
5663
5664         /* Packets are ready, update Tx producer idx local and on card. */
5665         tw32_tx_mbox(tnapi->prodmbox, entry);
5666
5667         tnapi->tx_prod = entry;
5668         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5669                 netif_tx_stop_queue(txq);
5670
5671                 /* netif_tx_stop_queue() must be done before checking
5672                  * checking tx index in tg3_tx_avail() below, because in
5673                  * tg3_tx(), we update tx index before checking for
5674                  * netif_tx_queue_stopped().
5675                  */
5676                 smp_mb();
5677                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5678                         netif_tx_wake_queue(txq);
5679         }
5680
5681 out_unlock:
5682         mmiowb();
5683
5684         return NETDEV_TX_OK;
5685
5686 dma_error:
5687         last = i;
5688         entry = tnapi->tx_prod;
5689         tnapi->tx_buffers[entry].skb = NULL;
5690         pci_unmap_single(tp->pdev,
5691                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5692                          skb_headlen(skb),
5693                          PCI_DMA_TODEVICE);
5694         for (i = 0; i <= last; i++) {
5695                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5696                 entry = NEXT_TX(entry);
5697
5698                 pci_unmap_page(tp->pdev,
5699                                dma_unmap_addr(&tnapi->tx_buffers[entry],
5700                                               mapping),
5701                                frag->size, PCI_DMA_TODEVICE);
5702         }
5703
5704         dev_kfree_skb(skb);
5705         return NETDEV_TX_OK;
5706 }
5707
5708 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5709                                           struct net_device *);
5710
5711 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5712  * TSO header is greater than 80 bytes.
5713  */
5714 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5715 {
5716         struct sk_buff *segs, *nskb;
5717         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5718
5719         /* Estimate the number of fragments in the worst case */
5720         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5721                 netif_stop_queue(tp->dev);
5722
5723                 /* netif_tx_stop_queue() must be done before checking
5724                  * checking tx index in tg3_tx_avail() below, because in
5725                  * tg3_tx(), we update tx index before checking for
5726                  * netif_tx_queue_stopped().
5727                  */
5728                 smp_mb();
5729                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5730                         return NETDEV_TX_BUSY;
5731
5732                 netif_wake_queue(tp->dev);
5733         }
5734
5735         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5736         if (IS_ERR(segs))
5737                 goto tg3_tso_bug_end;
5738
5739         do {
5740                 nskb = segs;
5741                 segs = segs->next;
5742                 nskb->next = NULL;
5743                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5744         } while (segs);
5745
5746 tg3_tso_bug_end:
5747         dev_kfree_skb(skb);
5748
5749         return NETDEV_TX_OK;
5750 }
5751
5752 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5753  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5754  */
5755 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5756                                           struct net_device *dev)
5757 {
5758         struct tg3 *tp = netdev_priv(dev);
5759         u32 len, entry, base_flags, mss;
5760         int would_hit_hwbug;
5761         dma_addr_t mapping;
5762         struct tg3_napi *tnapi;
5763         struct netdev_queue *txq;
5764         unsigned int i, last;
5765
5766         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5767         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5768         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5769                 tnapi++;
5770
5771         /* We are running in BH disabled context with netif_tx_lock
5772          * and TX reclaim runs via tp->napi.poll inside of a software
5773          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5774          * no IRQ context deadlocks to worry about either.  Rejoice!
5775          */
5776         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5777                 if (!netif_tx_queue_stopped(txq)) {
5778                         netif_tx_stop_queue(txq);
5779
5780                         /* This is a hard error, log it. */
5781                         netdev_err(dev,
5782                                    "BUG! Tx Ring full when queue awake!\n");
5783                 }
5784                 return NETDEV_TX_BUSY;
5785         }
5786
5787         entry = tnapi->tx_prod;
5788         base_flags = 0;
5789         if (skb->ip_summed == CHECKSUM_PARTIAL)
5790                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5791
5792         mss = skb_shinfo(skb)->gso_size;
5793         if (mss) {
5794                 struct iphdr *iph;
5795                 u32 tcp_opt_len, hdr_len;
5796
5797                 if (skb_header_cloned(skb) &&
5798                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5799                         dev_kfree_skb(skb);
5800                         goto out_unlock;
5801                 }
5802
5803                 iph = ip_hdr(skb);
5804                 tcp_opt_len = tcp_optlen(skb);
5805
5806                 if (skb_is_gso_v6(skb)) {
5807                         hdr_len = skb_headlen(skb) - ETH_HLEN;
5808                 } else {
5809                         u32 ip_tcp_len;
5810
5811                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5812                         hdr_len = ip_tcp_len + tcp_opt_len;
5813
5814                         iph->check = 0;
5815                         iph->tot_len = htons(mss + hdr_len);
5816                 }
5817
5818                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5819                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5820                         return tg3_tso_bug(tp, skb);
5821
5822                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5823                                TXD_FLAG_CPU_POST_DMA);
5824
5825                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5826                         tcp_hdr(skb)->check = 0;
5827                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5828                 } else
5829                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5830                                                                  iph->daddr, 0,
5831                                                                  IPPROTO_TCP,
5832                                                                  0);
5833
5834                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5835                         mss |= (hdr_len & 0xc) << 12;
5836                         if (hdr_len & 0x10)
5837                                 base_flags |= 0x00000010;
5838                         base_flags |= (hdr_len & 0x3e0) << 5;
5839                 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5840                         mss |= hdr_len << 9;
5841                 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5842                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5843                         if (tcp_opt_len || iph->ihl > 5) {
5844                                 int tsflags;
5845
5846                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5847                                 mss |= (tsflags << 11);
5848                         }
5849                 } else {
5850                         if (tcp_opt_len || iph->ihl > 5) {
5851                                 int tsflags;
5852
5853                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5854                                 base_flags |= tsflags << 12;
5855                         }
5856                 }
5857         }
5858 #if TG3_VLAN_TAG_USED
5859         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5860                 base_flags |= (TXD_FLAG_VLAN |
5861                                (vlan_tx_tag_get(skb) << 16));
5862 #endif
5863
5864         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5865             !mss && skb->len > ETH_DATA_LEN)
5866                 base_flags |= TXD_FLAG_JMB_PKT;
5867
5868         len = skb_headlen(skb);
5869
5870         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5871         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5872                 dev_kfree_skb(skb);
5873                 goto out_unlock;
5874         }
5875
5876         tnapi->tx_buffers[entry].skb = skb;
5877         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5878
5879         would_hit_hwbug = 0;
5880
5881         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5882                 would_hit_hwbug = 1;
5883
5884         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5885             tg3_4g_overflow_test(mapping, len))
5886                 would_hit_hwbug = 1;
5887
5888         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5889             tg3_40bit_overflow_test(tp, mapping, len))
5890                 would_hit_hwbug = 1;
5891
5892         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5893                 would_hit_hwbug = 1;
5894
5895         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5896                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5897
5898         entry = NEXT_TX(entry);
5899
5900         /* Now loop through additional data fragments, and queue them. */
5901         if (skb_shinfo(skb)->nr_frags > 0) {
5902                 last = skb_shinfo(skb)->nr_frags - 1;
5903                 for (i = 0; i <= last; i++) {
5904                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5905
5906                         len = frag->size;
5907                         mapping = pci_map_page(tp->pdev,
5908                                                frag->page,
5909                                                frag->page_offset,
5910                                                len, PCI_DMA_TODEVICE);
5911
5912                         tnapi->tx_buffers[entry].skb = NULL;
5913                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5914                                            mapping);
5915                         if (pci_dma_mapping_error(tp->pdev, mapping))
5916                                 goto dma_error;
5917
5918                         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5919                             len <= 8)
5920                                 would_hit_hwbug = 1;
5921
5922                         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5923                             tg3_4g_overflow_test(mapping, len))
5924                                 would_hit_hwbug = 1;
5925
5926                         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5927                             tg3_40bit_overflow_test(tp, mapping, len))
5928                                 would_hit_hwbug = 1;
5929
5930                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5931                                 tg3_set_txd(tnapi, entry, mapping, len,
5932                                             base_flags, (i == last)|(mss << 1));
5933                         else
5934                                 tg3_set_txd(tnapi, entry, mapping, len,
5935                                             base_flags, (i == last));
5936
5937                         entry = NEXT_TX(entry);
5938                 }
5939         }
5940
5941         if (would_hit_hwbug) {
5942                 u32 last_plus_one = entry;
5943                 u32 start;
5944
5945                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5946                 start &= (TG3_TX_RING_SIZE - 1);
5947
5948                 /* If the workaround fails due to memory/mapping
5949                  * failure, silently drop this packet.
5950                  */
5951                 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
5952                                                 &start, base_flags, mss))
5953                         goto out_unlock;
5954
5955                 entry = start;
5956         }
5957
5958         /* Packets are ready, update Tx producer idx local and on card. */
5959         tw32_tx_mbox(tnapi->prodmbox, entry);
5960
5961         tnapi->tx_prod = entry;
5962         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5963                 netif_tx_stop_queue(txq);
5964
5965                 /* netif_tx_stop_queue() must be done before checking
5966                  * checking tx index in tg3_tx_avail() below, because in
5967                  * tg3_tx(), we update tx index before checking for
5968                  * netif_tx_queue_stopped().
5969                  */
5970                 smp_mb();
5971                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5972                         netif_tx_wake_queue(txq);
5973         }
5974
5975 out_unlock:
5976         mmiowb();
5977
5978         return NETDEV_TX_OK;
5979
5980 dma_error:
5981         last = i;
5982         entry = tnapi->tx_prod;
5983         tnapi->tx_buffers[entry].skb = NULL;
5984         pci_unmap_single(tp->pdev,
5985                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5986                          skb_headlen(skb),
5987                          PCI_DMA_TODEVICE);
5988         for (i = 0; i <= last; i++) {
5989                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5990                 entry = NEXT_TX(entry);
5991
5992                 pci_unmap_page(tp->pdev,
5993                                dma_unmap_addr(&tnapi->tx_buffers[entry],
5994                                               mapping),
5995                                frag->size, PCI_DMA_TODEVICE);
5996         }
5997
5998         dev_kfree_skb(skb);
5999         return NETDEV_TX_OK;
6000 }
6001
6002 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
6003                                int new_mtu)
6004 {
6005         dev->mtu = new_mtu;
6006
6007         if (new_mtu > ETH_DATA_LEN) {
6008                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6009                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
6010                         ethtool_op_set_tso(dev, 0);
6011                 } else {
6012                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
6013                 }
6014         } else {
6015                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6016                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
6017                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
6018         }
6019 }
6020
6021 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
6022 {
6023         struct tg3 *tp = netdev_priv(dev);
6024         int err;
6025
6026         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
6027                 return -EINVAL;
6028
6029         if (!netif_running(dev)) {
6030                 /* We'll just catch it later when the
6031                  * device is up'd.
6032                  */
6033                 tg3_set_mtu(dev, tp, new_mtu);
6034                 return 0;
6035         }
6036
6037         tg3_phy_stop(tp);
6038
6039         tg3_netif_stop(tp);
6040
6041         tg3_full_lock(tp, 1);
6042
6043         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6044
6045         tg3_set_mtu(dev, tp, new_mtu);
6046
6047         err = tg3_restart_hw(tp, 0);
6048
6049         if (!err)
6050                 tg3_netif_start(tp);
6051
6052         tg3_full_unlock(tp);
6053
6054         if (!err)
6055                 tg3_phy_start(tp);
6056
6057         return err;
6058 }
6059
6060 static void tg3_rx_prodring_free(struct tg3 *tp,
6061                                  struct tg3_rx_prodring_set *tpr)
6062 {
6063         int i;
6064
6065         if (tpr != &tp->napi[0].prodring) {
6066                 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
6067                      i = (i + 1) & tp->rx_std_ring_mask)
6068                         tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6069                                         tp->rx_pkt_map_sz);
6070
6071                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6072                         for (i = tpr->rx_jmb_cons_idx;
6073                              i != tpr->rx_jmb_prod_idx;
6074                              i = (i + 1) & tp->rx_jmb_ring_mask) {
6075                                 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6076                                                 TG3_RX_JMB_MAP_SZ);
6077                         }
6078                 }
6079
6080                 return;
6081         }
6082
6083         for (i = 0; i <= tp->rx_std_ring_mask; i++)
6084                 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6085                                 tp->rx_pkt_map_sz);
6086
6087         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6088                 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
6089                         tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6090                                         TG3_RX_JMB_MAP_SZ);
6091         }
6092 }
6093
6094 /* Initialize rx rings for packet processing.
6095  *
6096  * The chip has been shut down and the driver detached from
6097  * the networking, so no interrupts or new tx packets will
6098  * end up in the driver.  tp->{tx,}lock are held and thus
6099  * we may not sleep.
6100  */
6101 static int tg3_rx_prodring_alloc(struct tg3 *tp,
6102                                  struct tg3_rx_prodring_set *tpr)
6103 {
6104         u32 i, rx_pkt_dma_sz;
6105
6106         tpr->rx_std_cons_idx = 0;
6107         tpr->rx_std_prod_idx = 0;
6108         tpr->rx_jmb_cons_idx = 0;
6109         tpr->rx_jmb_prod_idx = 0;
6110
6111         if (tpr != &tp->napi[0].prodring) {
6112                 memset(&tpr->rx_std_buffers[0], 0,
6113                        TG3_RX_STD_BUFF_RING_SIZE(tp));
6114                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
6115                         memset(&tpr->rx_jmb_buffers[0], 0,
6116                                TG3_RX_JMB_BUFF_RING_SIZE(tp));
6117                 goto done;
6118         }
6119
6120         /* Zero out all descriptors. */
6121         memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
6122
6123         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6124         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
6125             tp->dev->mtu > ETH_DATA_LEN)
6126                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6127         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6128
6129         /* Initialize invariants of the rings, we only set this
6130          * stuff once.  This works because the card does not
6131          * write into the rx buffer posting rings.
6132          */
6133         for (i = 0; i <= tp->rx_std_ring_mask; i++) {
6134                 struct tg3_rx_buffer_desc *rxd;
6135
6136                 rxd = &tpr->rx_std[i];
6137                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6138                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6139                 rxd->opaque = (RXD_OPAQUE_RING_STD |
6140                                (i << RXD_OPAQUE_INDEX_SHIFT));
6141         }
6142
6143         /* Now allocate fresh SKBs for each rx ring. */
6144         for (i = 0; i < tp->rx_pending; i++) {
6145                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6146                         netdev_warn(tp->dev,
6147                                     "Using a smaller RX standard ring. Only "
6148                                     "%d out of %d buffers were allocated "
6149                                     "successfully\n", i, tp->rx_pending);
6150                         if (i == 0)
6151                                 goto initfail;
6152                         tp->rx_pending = i;
6153                         break;
6154                 }
6155         }
6156
6157         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6158                 goto done;
6159
6160         memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
6161
6162         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
6163                 goto done;
6164
6165         for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
6166                 struct tg3_rx_buffer_desc *rxd;
6167
6168                 rxd = &tpr->rx_jmb[i].std;
6169                 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6170                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6171                                   RXD_FLAG_JUMBO;
6172                 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6173                        (i << RXD_OPAQUE_INDEX_SHIFT));
6174         }
6175
6176         for (i = 0; i < tp->rx_jumbo_pending; i++) {
6177                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
6178                         netdev_warn(tp->dev,
6179                                     "Using a smaller RX jumbo ring. Only %d "
6180                                     "out of %d buffers were allocated "
6181                                     "successfully\n", i, tp->rx_jumbo_pending);
6182                         if (i == 0)
6183                                 goto initfail;
6184                         tp->rx_jumbo_pending = i;
6185                         break;
6186                 }
6187         }
6188
6189 done:
6190         return 0;
6191
6192 initfail:
6193         tg3_rx_prodring_free(tp, tpr);
6194         return -ENOMEM;
6195 }
6196
6197 static void tg3_rx_prodring_fini(struct tg3 *tp,
6198                                  struct tg3_rx_prodring_set *tpr)
6199 {
6200         kfree(tpr->rx_std_buffers);
6201         tpr->rx_std_buffers = NULL;
6202         kfree(tpr->rx_jmb_buffers);
6203         tpr->rx_jmb_buffers = NULL;
6204         if (tpr->rx_std) {
6205                 pci_free_consistent(tp->pdev, TG3_RX_STD_RING_BYTES(tp),
6206                                     tpr->rx_std, tpr->rx_std_mapping);
6207                 tpr->rx_std = NULL;
6208         }
6209         if (tpr->rx_jmb) {
6210                 pci_free_consistent(tp->pdev, TG3_RX_JMB_RING_BYTES(tp),
6211                                     tpr->rx_jmb, tpr->rx_jmb_mapping);
6212                 tpr->rx_jmb = NULL;
6213         }
6214 }
6215
6216 static int tg3_rx_prodring_init(struct tg3 *tp,
6217                                 struct tg3_rx_prodring_set *tpr)
6218 {
6219         tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
6220                                       GFP_KERNEL);
6221         if (!tpr->rx_std_buffers)
6222                 return -ENOMEM;
6223
6224         tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_STD_RING_BYTES(tp),
6225                                            &tpr->rx_std_mapping);
6226         if (!tpr->rx_std)
6227                 goto err_out;
6228
6229         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6230                 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
6231                                               GFP_KERNEL);
6232                 if (!tpr->rx_jmb_buffers)
6233                         goto err_out;
6234
6235                 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6236                                                    TG3_RX_JMB_RING_BYTES(tp),
6237                                                    &tpr->rx_jmb_mapping);
6238                 if (!tpr->rx_jmb)
6239                         goto err_out;
6240         }
6241
6242         return 0;
6243
6244 err_out:
6245         tg3_rx_prodring_fini(tp, tpr);
6246         return -ENOMEM;
6247 }
6248
6249 /* Free up pending packets in all rx/tx rings.
6250  *
6251  * The chip has been shut down and the driver detached from
6252  * the networking, so no interrupts or new tx packets will
6253  * end up in the driver.  tp->{tx,}lock is not held and we are not
6254  * in an interrupt context and thus may sleep.
6255  */
6256 static void tg3_free_rings(struct tg3 *tp)
6257 {
6258         int i, j;
6259
6260         for (j = 0; j < tp->irq_cnt; j++) {
6261                 struct tg3_napi *tnapi = &tp->napi[j];
6262
6263                 tg3_rx_prodring_free(tp, &tnapi->prodring);
6264
6265                 if (!tnapi->tx_buffers)
6266                         continue;
6267
6268                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6269                         struct ring_info *txp;
6270                         struct sk_buff *skb;
6271                         unsigned int k;
6272
6273                         txp = &tnapi->tx_buffers[i];
6274                         skb = txp->skb;
6275
6276                         if (skb == NULL) {
6277                                 i++;
6278                                 continue;
6279                         }
6280
6281                         pci_unmap_single(tp->pdev,
6282                                          dma_unmap_addr(txp, mapping),
6283                                          skb_headlen(skb),
6284                                          PCI_DMA_TODEVICE);
6285                         txp->skb = NULL;
6286
6287                         i++;
6288
6289                         for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6290                                 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6291                                 pci_unmap_page(tp->pdev,
6292                                                dma_unmap_addr(txp, mapping),
6293                                                skb_shinfo(skb)->frags[k].size,
6294                                                PCI_DMA_TODEVICE);
6295                                 i++;
6296                         }
6297
6298                         dev_kfree_skb_any(skb);
6299                 }
6300         }
6301 }
6302
6303 /* Initialize tx/rx rings for packet processing.
6304  *
6305  * The chip has been shut down and the driver detached from
6306  * the networking, so no interrupts or new tx packets will
6307  * end up in the driver.  tp->{tx,}lock are held and thus
6308  * we may not sleep.
6309  */
6310 static int tg3_init_rings(struct tg3 *tp)
6311 {
6312         int i;
6313
6314         /* Free up all the SKBs. */
6315         tg3_free_rings(tp);
6316
6317         for (i = 0; i < tp->irq_cnt; i++) {
6318                 struct tg3_napi *tnapi = &tp->napi[i];
6319
6320                 tnapi->last_tag = 0;
6321                 tnapi->last_irq_tag = 0;
6322                 tnapi->hw_status->status = 0;
6323                 tnapi->hw_status->status_tag = 0;
6324                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6325
6326                 tnapi->tx_prod = 0;
6327                 tnapi->tx_cons = 0;
6328                 if (tnapi->tx_ring)
6329                         memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6330
6331                 tnapi->rx_rcb_ptr = 0;
6332                 if (tnapi->rx_rcb)
6333                         memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6334
6335                 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
6336                         tg3_free_rings(tp);
6337                         return -ENOMEM;
6338                 }
6339         }
6340
6341         return 0;
6342 }
6343
6344 /*
6345  * Must not be invoked with interrupt sources disabled and
6346  * the hardware shutdown down.
6347  */
6348 static void tg3_free_consistent(struct tg3 *tp)
6349 {
6350         int i;
6351
6352         for (i = 0; i < tp->irq_cnt; i++) {
6353                 struct tg3_napi *tnapi = &tp->napi[i];
6354
6355                 if (tnapi->tx_ring) {
6356                         pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6357                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
6358                         tnapi->tx_ring = NULL;
6359                 }
6360
6361                 kfree(tnapi->tx_buffers);
6362                 tnapi->tx_buffers = NULL;
6363
6364                 if (tnapi->rx_rcb) {
6365                         pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6366                                             tnapi->rx_rcb,
6367                                             tnapi->rx_rcb_mapping);
6368                         tnapi->rx_rcb = NULL;
6369                 }
6370
6371                 tg3_rx_prodring_fini(tp, &tnapi->prodring);
6372
6373                 if (tnapi->hw_status) {
6374                         pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6375                                             tnapi->hw_status,
6376                                             tnapi->status_mapping);
6377                         tnapi->hw_status = NULL;
6378                 }
6379         }
6380
6381         if (tp->hw_stats) {
6382                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6383                                     tp->hw_stats, tp->stats_mapping);
6384                 tp->hw_stats = NULL;
6385         }
6386 }
6387
6388 /*
6389  * Must not be invoked with interrupt sources disabled and
6390  * the hardware shutdown down.  Can sleep.
6391  */
6392 static int tg3_alloc_consistent(struct tg3 *tp)
6393 {
6394         int i;
6395
6396         tp->hw_stats = pci_alloc_consistent(tp->pdev,
6397                                             sizeof(struct tg3_hw_stats),
6398                                             &tp->stats_mapping);
6399         if (!tp->hw_stats)
6400                 goto err_out;
6401
6402         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6403
6404         for (i = 0; i < tp->irq_cnt; i++) {
6405                 struct tg3_napi *tnapi = &tp->napi[i];
6406                 struct tg3_hw_status *sblk;
6407
6408                 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6409                                                         TG3_HW_STATUS_SIZE,
6410                                                         &tnapi->status_mapping);
6411                 if (!tnapi->hw_status)
6412                         goto err_out;
6413
6414                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6415                 sblk = tnapi->hw_status;
6416
6417                 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
6418                         goto err_out;
6419
6420                 /* If multivector TSS is enabled, vector 0 does not handle
6421                  * tx interrupts.  Don't allocate any resources for it.
6422                  */
6423                 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6424                     (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6425                         tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6426                                                     TG3_TX_RING_SIZE,
6427                                                     GFP_KERNEL);
6428                         if (!tnapi->tx_buffers)
6429                                 goto err_out;
6430
6431                         tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6432                                                               TG3_TX_RING_BYTES,
6433                                                        &tnapi->tx_desc_mapping);
6434                         if (!tnapi->tx_ring)
6435                                 goto err_out;
6436                 }
6437
6438                 /*
6439                  * When RSS is enabled, the status block format changes
6440                  * slightly.  The "rx_jumbo_consumer", "reserved",
6441                  * and "rx_mini_consumer" members get mapped to the
6442                  * other three rx return ring producer indexes.
6443                  */
6444                 switch (i) {
6445                 default:
6446                         tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6447                         break;
6448                 case 2:
6449                         tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6450                         break;
6451                 case 3:
6452                         tnapi->rx_rcb_prod_idx = &sblk->reserved;
6453                         break;
6454                 case 4:
6455                         tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6456                         break;
6457                 }
6458
6459                 /*
6460                  * If multivector RSS is enabled, vector 0 does not handle
6461                  * rx or tx interrupts.  Don't allocate any resources for it.
6462                  */
6463                 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6464                         continue;
6465
6466                 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6467                                                      TG3_RX_RCB_RING_BYTES(tp),
6468                                                      &tnapi->rx_rcb_mapping);
6469                 if (!tnapi->rx_rcb)
6470                         goto err_out;
6471
6472                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6473         }
6474
6475         return 0;
6476
6477 err_out:
6478         tg3_free_consistent(tp);
6479         return -ENOMEM;
6480 }
6481
6482 #define MAX_WAIT_CNT 1000
6483
6484 /* To stop a block, clear the enable bit and poll till it
6485  * clears.  tp->lock is held.
6486  */
6487 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6488 {
6489         unsigned int i;
6490         u32 val;
6491
6492         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6493                 switch (ofs) {
6494                 case RCVLSC_MODE:
6495                 case DMAC_MODE:
6496                 case MBFREE_MODE:
6497                 case BUFMGR_MODE:
6498                 case MEMARB_MODE:
6499                         /* We can't enable/disable these bits of the
6500                          * 5705/5750, just say success.
6501                          */
6502                         return 0;
6503
6504                 default:
6505                         break;
6506                 }
6507         }
6508
6509         val = tr32(ofs);
6510         val &= ~enable_bit;
6511         tw32_f(ofs, val);
6512
6513         for (i = 0; i < MAX_WAIT_CNT; i++) {
6514                 udelay(100);
6515                 val = tr32(ofs);
6516                 if ((val & enable_bit) == 0)
6517                         break;
6518         }
6519
6520         if (i == MAX_WAIT_CNT && !silent) {
6521                 dev_err(&tp->pdev->dev,
6522                         "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6523                         ofs, enable_bit);
6524                 return -ENODEV;
6525         }
6526
6527         return 0;
6528 }
6529
6530 /* tp->lock is held. */
6531 static int tg3_abort_hw(struct tg3 *tp, int silent)
6532 {
6533         int i, err;
6534
6535         tg3_disable_ints(tp);
6536
6537         tp->rx_mode &= ~RX_MODE_ENABLE;
6538         tw32_f(MAC_RX_MODE, tp->rx_mode);
6539         udelay(10);
6540
6541         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6542         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6543         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6544         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6545         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6546         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6547
6548         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6549         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6550         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6551         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6552         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6553         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6554         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6555
6556         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6557         tw32_f(MAC_MODE, tp->mac_mode);
6558         udelay(40);
6559
6560         tp->tx_mode &= ~TX_MODE_ENABLE;
6561         tw32_f(MAC_TX_MODE, tp->tx_mode);
6562
6563         for (i = 0; i < MAX_WAIT_CNT; i++) {
6564                 udelay(100);
6565                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6566                         break;
6567         }
6568         if (i >= MAX_WAIT_CNT) {
6569                 dev_err(&tp->pdev->dev,
6570                         "%s timed out, TX_MODE_ENABLE will not clear "
6571                         "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
6572                 err |= -ENODEV;
6573         }
6574
6575         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6576         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6577         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6578
6579         tw32(FTQ_RESET, 0xffffffff);
6580         tw32(FTQ_RESET, 0x00000000);
6581
6582         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6583         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6584
6585         for (i = 0; i < tp->irq_cnt; i++) {
6586                 struct tg3_napi *tnapi = &tp->napi[i];
6587                 if (tnapi->hw_status)
6588                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6589         }
6590         if (tp->hw_stats)
6591                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6592
6593         return err;
6594 }
6595
6596 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6597 {
6598         int i;
6599         u32 apedata;
6600
6601         /* NCSI does not support APE events */
6602         if (tp->tg3_flags3 & TG3_FLG3_APE_HAS_NCSI)
6603                 return;
6604
6605         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6606         if (apedata != APE_SEG_SIG_MAGIC)
6607                 return;
6608
6609         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6610         if (!(apedata & APE_FW_STATUS_READY))
6611                 return;
6612
6613         /* Wait for up to 1 millisecond for APE to service previous event. */
6614         for (i = 0; i < 10; i++) {
6615                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6616                         return;
6617
6618                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6619
6620                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6621                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6622                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6623
6624                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6625
6626                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6627                         break;
6628
6629                 udelay(100);
6630         }
6631
6632         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6633                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6634 }
6635
6636 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6637 {
6638         u32 event;
6639         u32 apedata;
6640
6641         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6642                 return;
6643
6644         switch (kind) {
6645         case RESET_KIND_INIT:
6646                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6647                                 APE_HOST_SEG_SIG_MAGIC);
6648                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6649                                 APE_HOST_SEG_LEN_MAGIC);
6650                 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6651                 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6652                 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6653                         APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
6654                 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6655                                 APE_HOST_BEHAV_NO_PHYLOCK);
6656                 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
6657                                     TG3_APE_HOST_DRVR_STATE_START);
6658
6659                 event = APE_EVENT_STATUS_STATE_START;
6660                 break;
6661         case RESET_KIND_SHUTDOWN:
6662                 /* With the interface we are currently using,
6663                  * APE does not track driver state.  Wiping
6664                  * out the HOST SEGMENT SIGNATURE forces
6665                  * the APE to assume OS absent status.
6666                  */
6667                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6668
6669                 if (device_may_wakeup(&tp->pdev->dev) &&
6670                     (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) {
6671                         tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
6672                                             TG3_APE_HOST_WOL_SPEED_AUTO);
6673                         apedata = TG3_APE_HOST_DRVR_STATE_WOL;
6674                 } else
6675                         apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
6676
6677                 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
6678
6679                 event = APE_EVENT_STATUS_STATE_UNLOAD;
6680                 break;
6681         case RESET_KIND_SUSPEND:
6682                 event = APE_EVENT_STATUS_STATE_SUSPEND;
6683                 break;
6684         default:
6685                 return;
6686         }
6687
6688         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6689
6690         tg3_ape_send_event(tp, event);
6691 }
6692
6693 /* tp->lock is held. */
6694 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6695 {
6696         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6697                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6698
6699         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6700                 switch (kind) {
6701                 case RESET_KIND_INIT:
6702                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6703                                       DRV_STATE_START);
6704                         break;
6705
6706                 case RESET_KIND_SHUTDOWN:
6707                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6708                                       DRV_STATE_UNLOAD);
6709                         break;
6710
6711                 case RESET_KIND_SUSPEND:
6712                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6713                                       DRV_STATE_SUSPEND);
6714                         break;
6715
6716                 default:
6717                         break;
6718                 }
6719         }
6720
6721         if (kind == RESET_KIND_INIT ||
6722             kind == RESET_KIND_SUSPEND)
6723                 tg3_ape_driver_state_change(tp, kind);
6724 }
6725
6726 /* tp->lock is held. */
6727 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6728 {
6729         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6730                 switch (kind) {
6731                 case RESET_KIND_INIT:
6732                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6733                                       DRV_STATE_START_DONE);
6734                         break;
6735
6736                 case RESET_KIND_SHUTDOWN:
6737                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6738                                       DRV_STATE_UNLOAD_DONE);
6739                         break;
6740
6741                 default:
6742                         break;
6743                 }
6744         }
6745
6746         if (kind == RESET_KIND_SHUTDOWN)
6747                 tg3_ape_driver_state_change(tp, kind);
6748 }
6749
6750 /* tp->lock is held. */
6751 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6752 {
6753         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6754                 switch (kind) {
6755                 case RESET_KIND_INIT:
6756                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6757                                       DRV_STATE_START);
6758                         break;
6759
6760                 case RESET_KIND_SHUTDOWN:
6761                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6762                                       DRV_STATE_UNLOAD);
6763                         break;
6764
6765                 case RESET_KIND_SUSPEND:
6766                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6767                                       DRV_STATE_SUSPEND);
6768                         break;
6769
6770                 default:
6771                         break;
6772                 }
6773         }
6774 }
6775
6776 static int tg3_poll_fw(struct tg3 *tp)
6777 {
6778         int i;
6779         u32 val;
6780
6781         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6782                 /* Wait up to 20ms for init done. */
6783                 for (i = 0; i < 200; i++) {
6784                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6785                                 return 0;
6786                         udelay(100);
6787                 }
6788                 return -ENODEV;
6789         }
6790
6791         /* Wait for firmware initialization to complete. */
6792         for (i = 0; i < 100000; i++) {
6793                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6794                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6795                         break;
6796                 udelay(10);
6797         }
6798
6799         /* Chip might not be fitted with firmware.  Some Sun onboard
6800          * parts are configured like that.  So don't signal the timeout
6801          * of the above loop as an error, but do report the lack of
6802          * running firmware once.
6803          */
6804         if (i >= 100000 &&
6805             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6806                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6807
6808                 netdev_info(tp->dev, "No firmware running\n");
6809         }
6810
6811         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6812                 /* The 57765 A0 needs a little more
6813                  * time to do some important work.
6814                  */
6815                 mdelay(10);
6816         }
6817
6818         return 0;
6819 }
6820
6821 /* Save PCI command register before chip reset */
6822 static void tg3_save_pci_state(struct tg3 *tp)
6823 {
6824         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6825 }
6826
6827 /* Restore PCI state after chip reset */
6828 static void tg3_restore_pci_state(struct tg3 *tp)
6829 {
6830         u32 val;
6831
6832         /* Re-enable indirect register accesses. */
6833         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6834                                tp->misc_host_ctrl);
6835
6836         /* Set MAX PCI retry to zero. */
6837         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6838         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6839             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6840                 val |= PCISTATE_RETRY_SAME_DMA;
6841         /* Allow reads and writes to the APE register and memory space. */
6842         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6843                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6844                        PCISTATE_ALLOW_APE_SHMEM_WR |
6845                        PCISTATE_ALLOW_APE_PSPACE_WR;
6846         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6847
6848         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6849
6850         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6851                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6852                         pcie_set_readrq(tp->pdev, 4096);
6853                 else {
6854                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6855                                               tp->pci_cacheline_sz);
6856                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6857                                               tp->pci_lat_timer);
6858                 }
6859         }
6860
6861         /* Make sure PCI-X relaxed ordering bit is clear. */
6862         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6863                 u16 pcix_cmd;
6864
6865                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6866                                      &pcix_cmd);
6867                 pcix_cmd &= ~PCI_X_CMD_ERO;
6868                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6869                                       pcix_cmd);
6870         }
6871
6872         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6873
6874                 /* Chip reset on 5780 will reset MSI enable bit,
6875                  * so need to restore it.
6876                  */
6877                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6878                         u16 ctrl;
6879
6880                         pci_read_config_word(tp->pdev,
6881                                              tp->msi_cap + PCI_MSI_FLAGS,
6882                                              &ctrl);
6883                         pci_write_config_word(tp->pdev,
6884                                               tp->msi_cap + PCI_MSI_FLAGS,
6885                                               ctrl | PCI_MSI_FLAGS_ENABLE);
6886                         val = tr32(MSGINT_MODE);
6887                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6888                 }
6889         }
6890 }
6891
6892 static void tg3_stop_fw(struct tg3 *);
6893
6894 /* tp->lock is held. */
6895 static int tg3_chip_reset(struct tg3 *tp)
6896 {
6897         u32 val;
6898         void (*write_op)(struct tg3 *, u32, u32);
6899         int i, err;
6900
6901         tg3_nvram_lock(tp);
6902
6903         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6904
6905         /* No matching tg3_nvram_unlock() after this because
6906          * chip reset below will undo the nvram lock.
6907          */
6908         tp->nvram_lock_cnt = 0;
6909
6910         /* GRC_MISC_CFG core clock reset will clear the memory
6911          * enable bit in PCI register 4 and the MSI enable bit
6912          * on some chips, so we save relevant registers here.
6913          */
6914         tg3_save_pci_state(tp);
6915
6916         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6917             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6918                 tw32(GRC_FASTBOOT_PC, 0);
6919
6920         /*
6921          * We must avoid the readl() that normally takes place.
6922          * It locks machines, causes machine checks, and other
6923          * fun things.  So, temporarily disable the 5701
6924          * hardware workaround, while we do the reset.
6925          */
6926         write_op = tp->write32;
6927         if (write_op == tg3_write_flush_reg32)
6928                 tp->write32 = tg3_write32;
6929
6930         /* Prevent the irq handler from reading or writing PCI registers
6931          * during chip reset when the memory enable bit in the PCI command
6932          * register may be cleared.  The chip does not generate interrupt
6933          * at this time, but the irq handler may still be called due to irq
6934          * sharing or irqpoll.
6935          */
6936         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6937         for (i = 0; i < tp->irq_cnt; i++) {
6938                 struct tg3_napi *tnapi = &tp->napi[i];
6939                 if (tnapi->hw_status) {
6940                         tnapi->hw_status->status = 0;
6941                         tnapi->hw_status->status_tag = 0;
6942                 }
6943                 tnapi->last_tag = 0;
6944                 tnapi->last_irq_tag = 0;
6945         }
6946         smp_mb();
6947
6948         for (i = 0; i < tp->irq_cnt; i++)
6949                 synchronize_irq(tp->napi[i].irq_vec);
6950
6951         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6952                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6953                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6954         }
6955
6956         /* do the reset */
6957         val = GRC_MISC_CFG_CORECLK_RESET;
6958
6959         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6960                 /* Force PCIe 1.0a mode */
6961                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
6962                     !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
6963                     tr32(TG3_PCIE_PHY_TSTCTL) ==
6964                     (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
6965                         tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
6966
6967                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6968                         tw32(GRC_MISC_CFG, (1 << 29));
6969                         val |= (1 << 29);
6970                 }
6971         }
6972
6973         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6974                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6975                 tw32(GRC_VCPU_EXT_CTRL,
6976                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6977         }
6978
6979         /* Manage gphy power for all CPMU absent PCIe devices. */
6980         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6981             !(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
6982                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6983
6984         tw32(GRC_MISC_CFG, val);
6985
6986         /* restore 5701 hardware bug workaround write method */
6987         tp->write32 = write_op;
6988
6989         /* Unfortunately, we have to delay before the PCI read back.
6990          * Some 575X chips even will not respond to a PCI cfg access
6991          * when the reset command is given to the chip.
6992          *
6993          * How do these hardware designers expect things to work
6994          * properly if the PCI write is posted for a long period
6995          * of time?  It is always necessary to have some method by
6996          * which a register read back can occur to push the write
6997          * out which does the reset.
6998          *
6999          * For most tg3 variants the trick below was working.
7000          * Ho hum...
7001          */
7002         udelay(120);
7003
7004         /* Flush PCI posted writes.  The normal MMIO registers
7005          * are inaccessible at this time so this is the only
7006          * way to make this reliably (actually, this is no longer
7007          * the case, see above).  I tried to use indirect
7008          * register read/write but this upset some 5701 variants.
7009          */
7010         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
7011
7012         udelay(120);
7013
7014         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
7015                 u16 val16;
7016
7017                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
7018                         int i;
7019                         u32 cfg_val;
7020
7021                         /* Wait for link training to complete.  */
7022                         for (i = 0; i < 5000; i++)
7023                                 udelay(100);
7024
7025                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
7026                         pci_write_config_dword(tp->pdev, 0xc4,
7027                                                cfg_val | (1 << 15));
7028                 }
7029
7030                 /* Clear the "no snoop" and "relaxed ordering" bits. */
7031                 pci_read_config_word(tp->pdev,
7032                                      tp->pcie_cap + PCI_EXP_DEVCTL,
7033                                      &val16);
7034                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
7035                            PCI_EXP_DEVCTL_NOSNOOP_EN);
7036                 /*
7037                  * Older PCIe devices only support the 128 byte
7038                  * MPS setting.  Enforce the restriction.
7039                  */
7040                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7041                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
7042                 pci_write_config_word(tp->pdev,
7043                                       tp->pcie_cap + PCI_EXP_DEVCTL,
7044                                       val16);
7045
7046                 pcie_set_readrq(tp->pdev, 4096);
7047
7048                 /* Clear error status */
7049                 pci_write_config_word(tp->pdev,
7050                                       tp->pcie_cap + PCI_EXP_DEVSTA,
7051                                       PCI_EXP_DEVSTA_CED |
7052                                       PCI_EXP_DEVSTA_NFED |
7053                                       PCI_EXP_DEVSTA_FED |
7054                                       PCI_EXP_DEVSTA_URD);
7055         }
7056
7057         tg3_restore_pci_state(tp);
7058
7059         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
7060
7061         val = 0;
7062         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
7063                 val = tr32(MEMARB_MODE);
7064         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7065
7066         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7067                 tg3_stop_fw(tp);
7068                 tw32(0x5000, 0x400);
7069         }
7070
7071         tw32(GRC_MODE, tp->grc_mode);
7072
7073         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
7074                 val = tr32(0xc4);
7075
7076                 tw32(0xc4, val | (1 << 15));
7077         }
7078
7079         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7080             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7081                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7082                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7083                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7084                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7085         }
7086
7087         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
7088                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
7089                 tw32_f(MAC_MODE, tp->mac_mode);
7090         } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
7091                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
7092                 tw32_f(MAC_MODE, tp->mac_mode);
7093         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7094                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
7095                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
7096                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
7097                 tw32_f(MAC_MODE, tp->mac_mode);
7098         } else
7099                 tw32_f(MAC_MODE, 0);
7100         udelay(40);
7101
7102         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7103
7104         err = tg3_poll_fw(tp);
7105         if (err)
7106                 return err;
7107
7108         tg3_mdio_start(tp);
7109
7110         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
7111             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7112             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7113             !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
7114                 val = tr32(0x7c00);
7115
7116                 tw32(0x7c00, val | (1 << 25));
7117         }
7118
7119         /* Reprobe ASF enable state.  */
7120         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7121         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7122         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7123         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7124                 u32 nic_cfg;
7125
7126                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7127                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7128                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7129                         tp->last_event_jiffies = jiffies;
7130                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7131                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7132                 }
7133         }
7134
7135         return 0;
7136 }
7137
7138 /* tp->lock is held. */
7139 static void tg3_stop_fw(struct tg3 *tp)
7140 {
7141         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7142            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7143                 /* Wait for RX cpu to ACK the previous event. */
7144                 tg3_wait_for_event_ack(tp);
7145
7146                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7147
7148                 tg3_generate_fw_event(tp);
7149
7150                 /* Wait for RX cpu to ACK this event. */
7151                 tg3_wait_for_event_ack(tp);
7152         }
7153 }
7154
7155 /* tp->lock is held. */
7156 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7157 {
7158         int err;
7159
7160         tg3_stop_fw(tp);
7161
7162         tg3_write_sig_pre_reset(tp, kind);
7163
7164         tg3_abort_hw(tp, silent);
7165         err = tg3_chip_reset(tp);
7166
7167         __tg3_set_mac_addr(tp, 0);
7168
7169         tg3_write_sig_legacy(tp, kind);
7170         tg3_write_sig_post_reset(tp, kind);
7171
7172         if (err)
7173                 return err;
7174
7175         return 0;
7176 }
7177
7178 #define RX_CPU_SCRATCH_BASE     0x30000
7179 #define RX_CPU_SCRATCH_SIZE     0x04000
7180 #define TX_CPU_SCRATCH_BASE     0x34000
7181 #define TX_CPU_SCRATCH_SIZE     0x04000
7182
7183 /* tp->lock is held. */
7184 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7185 {
7186         int i;
7187
7188         BUG_ON(offset == TX_CPU_BASE &&
7189             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7190
7191         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7192                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7193
7194                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7195                 return 0;
7196         }
7197         if (offset == RX_CPU_BASE) {
7198                 for (i = 0; i < 10000; i++) {
7199                         tw32(offset + CPU_STATE, 0xffffffff);
7200                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7201                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7202                                 break;
7203                 }
7204
7205                 tw32(offset + CPU_STATE, 0xffffffff);
7206                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
7207                 udelay(10);
7208         } else {
7209                 for (i = 0; i < 10000; i++) {
7210                         tw32(offset + CPU_STATE, 0xffffffff);
7211                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7212                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7213                                 break;
7214                 }
7215         }
7216
7217         if (i >= 10000) {
7218                 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7219                            __func__, offset == RX_CPU_BASE ? "RX" : "TX");
7220                 return -ENODEV;
7221         }
7222
7223         /* Clear firmware's nvram arbitration. */
7224         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7225                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7226         return 0;
7227 }
7228
7229 struct fw_info {
7230         unsigned int fw_base;
7231         unsigned int fw_len;
7232         const __be32 *fw_data;
7233 };
7234
7235 /* tp->lock is held. */
7236 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7237                                  int cpu_scratch_size, struct fw_info *info)
7238 {
7239         int err, lock_err, i;
7240         void (*write_op)(struct tg3 *, u32, u32);
7241
7242         if (cpu_base == TX_CPU_BASE &&
7243             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7244                 netdev_err(tp->dev,
7245                            "%s: Trying to load TX cpu firmware which is 5705\n",
7246                            __func__);
7247                 return -EINVAL;
7248         }
7249
7250         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7251                 write_op = tg3_write_mem;
7252         else
7253                 write_op = tg3_write_indirect_reg32;
7254
7255         /* It is possible that bootcode is still loading at this point.
7256          * Get the nvram lock first before halting the cpu.
7257          */
7258         lock_err = tg3_nvram_lock(tp);
7259         err = tg3_halt_cpu(tp, cpu_base);
7260         if (!lock_err)
7261                 tg3_nvram_unlock(tp);
7262         if (err)
7263                 goto out;
7264
7265         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7266                 write_op(tp, cpu_scratch_base + i, 0);
7267         tw32(cpu_base + CPU_STATE, 0xffffffff);
7268         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7269         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7270                 write_op(tp, (cpu_scratch_base +
7271                               (info->fw_base & 0xffff) +
7272                               (i * sizeof(u32))),
7273                               be32_to_cpu(info->fw_data[i]));
7274
7275         err = 0;
7276
7277 out:
7278         return err;
7279 }
7280
7281 /* tp->lock is held. */
7282 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7283 {
7284         struct fw_info info;
7285         const __be32 *fw_data;
7286         int err, i;
7287
7288         fw_data = (void *)tp->fw->data;
7289
7290         /* Firmware blob starts with version numbers, followed by
7291            start address and length. We are setting complete length.
7292            length = end_address_of_bss - start_address_of_text.
7293            Remainder is the blob to be loaded contiguously
7294            from start address. */
7295
7296         info.fw_base = be32_to_cpu(fw_data[1]);
7297         info.fw_len = tp->fw->size - 12;
7298         info.fw_data = &fw_data[3];
7299
7300         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7301                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7302                                     &info);
7303         if (err)
7304                 return err;
7305
7306         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7307                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7308                                     &info);
7309         if (err)
7310                 return err;
7311
7312         /* Now startup only the RX cpu. */
7313         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7314         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7315
7316         for (i = 0; i < 5; i++) {
7317                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7318                         break;
7319                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7320                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
7321                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7322                 udelay(1000);
7323         }
7324         if (i >= 5) {
7325                 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7326                            "should be %08x\n", __func__,
7327                            tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
7328                 return -ENODEV;
7329         }
7330         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7331         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
7332
7333         return 0;
7334 }
7335
7336 /* 5705 needs a special version of the TSO firmware.  */
7337
7338 /* tp->lock is held. */
7339 static int tg3_load_tso_firmware(struct tg3 *tp)
7340 {
7341         struct fw_info info;
7342         const __be32 *fw_data;
7343         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7344         int err, i;
7345
7346         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7347                 return 0;
7348
7349         fw_data = (void *)tp->fw->data;
7350
7351         /* Firmware blob starts with version numbers, followed by
7352            start address and length. We are setting complete length.
7353            length = end_address_of_bss - start_address_of_text.
7354            Remainder is the blob to be loaded contiguously
7355            from start address. */
7356
7357         info.fw_base = be32_to_cpu(fw_data[1]);
7358         cpu_scratch_size = tp->fw_len;
7359         info.fw_len = tp->fw->size - 12;
7360         info.fw_data = &fw_data[3];
7361
7362         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7363                 cpu_base = RX_CPU_BASE;
7364                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7365         } else {
7366                 cpu_base = TX_CPU_BASE;
7367                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7368                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7369         }
7370
7371         err = tg3_load_firmware_cpu(tp, cpu_base,
7372                                     cpu_scratch_base, cpu_scratch_size,
7373                                     &info);
7374         if (err)
7375                 return err;
7376
7377         /* Now startup the cpu. */
7378         tw32(cpu_base + CPU_STATE, 0xffffffff);
7379         tw32_f(cpu_base + CPU_PC, info.fw_base);
7380
7381         for (i = 0; i < 5; i++) {
7382                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7383                         break;
7384                 tw32(cpu_base + CPU_STATE, 0xffffffff);
7385                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
7386                 tw32_f(cpu_base + CPU_PC, info.fw_base);
7387                 udelay(1000);
7388         }
7389         if (i >= 5) {
7390                 netdev_err(tp->dev,
7391                            "%s fails to set CPU PC, is %08x should be %08x\n",
7392                            __func__, tr32(cpu_base + CPU_PC), info.fw_base);
7393                 return -ENODEV;
7394         }
7395         tw32(cpu_base + CPU_STATE, 0xffffffff);
7396         tw32_f(cpu_base + CPU_MODE,  0x00000000);
7397         return 0;
7398 }
7399
7400
7401 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7402 {
7403         struct tg3 *tp = netdev_priv(dev);
7404         struct sockaddr *addr = p;
7405         int err = 0, skip_mac_1 = 0;
7406
7407         if (!is_valid_ether_addr(addr->sa_data))
7408                 return -EINVAL;
7409
7410         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7411
7412         if (!netif_running(dev))
7413                 return 0;
7414
7415         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7416                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7417
7418                 addr0_high = tr32(MAC_ADDR_0_HIGH);
7419                 addr0_low = tr32(MAC_ADDR_0_LOW);
7420                 addr1_high = tr32(MAC_ADDR_1_HIGH);
7421                 addr1_low = tr32(MAC_ADDR_1_LOW);
7422
7423                 /* Skip MAC addr 1 if ASF is using it. */
7424                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7425                     !(addr1_high == 0 && addr1_low == 0))
7426                         skip_mac_1 = 1;
7427         }
7428         spin_lock_bh(&tp->lock);
7429         __tg3_set_mac_addr(tp, skip_mac_1);
7430         spin_unlock_bh(&tp->lock);
7431
7432         return err;
7433 }
7434
7435 /* tp->lock is held. */
7436 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7437                            dma_addr_t mapping, u32 maxlen_flags,
7438                            u32 nic_addr)
7439 {
7440         tg3_write_mem(tp,
7441                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7442                       ((u64) mapping >> 32));
7443         tg3_write_mem(tp,
7444                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7445                       ((u64) mapping & 0xffffffff));
7446         tg3_write_mem(tp,
7447                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7448                        maxlen_flags);
7449
7450         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7451                 tg3_write_mem(tp,
7452                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7453                               nic_addr);
7454 }
7455
7456 static void __tg3_set_rx_mode(struct net_device *);
7457 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7458 {
7459         int i;
7460
7461         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7462                 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7463                 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7464                 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7465         } else {
7466                 tw32(HOSTCC_TXCOL_TICKS, 0);
7467                 tw32(HOSTCC_TXMAX_FRAMES, 0);
7468                 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7469         }
7470
7471         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
7472                 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7473                 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7474                 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7475         } else {
7476                 tw32(HOSTCC_RXCOL_TICKS, 0);
7477                 tw32(HOSTCC_RXMAX_FRAMES, 0);
7478                 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7479         }
7480
7481         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7482                 u32 val = ec->stats_block_coalesce_usecs;
7483
7484                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7485                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7486
7487                 if (!netif_carrier_ok(tp->dev))
7488                         val = 0;
7489
7490                 tw32(HOSTCC_STAT_COAL_TICKS, val);
7491         }
7492
7493         for (i = 0; i < tp->irq_cnt - 1; i++) {
7494                 u32 reg;
7495
7496                 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7497                 tw32(reg, ec->rx_coalesce_usecs);
7498                 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7499                 tw32(reg, ec->rx_max_coalesced_frames);
7500                 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7501                 tw32(reg, ec->rx_max_coalesced_frames_irq);
7502
7503                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7504                         reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7505                         tw32(reg, ec->tx_coalesce_usecs);
7506                         reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7507                         tw32(reg, ec->tx_max_coalesced_frames);
7508                         reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7509                         tw32(reg, ec->tx_max_coalesced_frames_irq);
7510                 }
7511         }
7512
7513         for (; i < tp->irq_max - 1; i++) {
7514                 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7515                 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7516                 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7517
7518                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7519                         tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7520                         tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7521                         tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7522                 }
7523         }
7524 }
7525
7526 /* tp->lock is held. */
7527 static void tg3_rings_reset(struct tg3 *tp)
7528 {
7529         int i;
7530         u32 stblk, txrcb, rxrcb, limit;
7531         struct tg3_napi *tnapi = &tp->napi[0];
7532
7533         /* Disable all transmit rings but the first. */
7534         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7535                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7536         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7537                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7538         else
7539                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7540
7541         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7542              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7543                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7544                               BDINFO_FLAGS_DISABLED);
7545
7546
7547         /* Disable all receive return rings but the first. */
7548         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7549             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7550                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7551         else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7552                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7553         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7554                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7555                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7556         else
7557                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7558
7559         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7560              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7561                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7562                               BDINFO_FLAGS_DISABLED);
7563
7564         /* Disable interrupts */
7565         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7566
7567         /* Zero mailbox registers. */
7568         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7569                 for (i = 1; i < tp->irq_max; i++) {
7570                         tp->napi[i].tx_prod = 0;
7571                         tp->napi[i].tx_cons = 0;
7572                         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7573                                 tw32_mailbox(tp->napi[i].prodmbox, 0);
7574                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
7575                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7576                 }
7577                 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7578                         tw32_mailbox(tp->napi[0].prodmbox, 0);
7579         } else {
7580                 tp->napi[0].tx_prod = 0;
7581                 tp->napi[0].tx_cons = 0;
7582                 tw32_mailbox(tp->napi[0].prodmbox, 0);
7583                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7584         }
7585
7586         /* Make sure the NIC-based send BD rings are disabled. */
7587         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7588                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7589                 for (i = 0; i < 16; i++)
7590                         tw32_tx_mbox(mbox + i * 8, 0);
7591         }
7592
7593         txrcb = NIC_SRAM_SEND_RCB;
7594         rxrcb = NIC_SRAM_RCV_RET_RCB;
7595
7596         /* Clear status block in ram. */
7597         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7598
7599         /* Set status block DMA address */
7600         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7601              ((u64) tnapi->status_mapping >> 32));
7602         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7603              ((u64) tnapi->status_mapping & 0xffffffff));
7604
7605         if (tnapi->tx_ring) {
7606                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7607                                (TG3_TX_RING_SIZE <<
7608                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7609                                NIC_SRAM_TX_BUFFER_DESC);
7610                 txrcb += TG3_BDINFO_SIZE;
7611         }
7612
7613         if (tnapi->rx_rcb) {
7614                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7615                                (TG3_RX_RCB_RING_SIZE(tp) <<
7616                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7617                 rxrcb += TG3_BDINFO_SIZE;
7618         }
7619
7620         stblk = HOSTCC_STATBLCK_RING1;
7621
7622         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7623                 u64 mapping = (u64)tnapi->status_mapping;
7624                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7625                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7626
7627                 /* Clear status block in ram. */
7628                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7629
7630                 if (tnapi->tx_ring) {
7631                         tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7632                                        (TG3_TX_RING_SIZE <<
7633                                         BDINFO_FLAGS_MAXLEN_SHIFT),
7634                                        NIC_SRAM_TX_BUFFER_DESC);
7635                         txrcb += TG3_BDINFO_SIZE;
7636                 }
7637
7638                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7639                                (TG3_RX_RCB_RING_SIZE(tp) <<
7640                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7641
7642                 stblk += 8;
7643                 rxrcb += TG3_BDINFO_SIZE;
7644         }
7645 }
7646
7647 /* tp->lock is held. */
7648 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7649 {
7650         u32 val, rdmac_mode;
7651         int i, err, limit;
7652         struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
7653
7654         tg3_disable_ints(tp);
7655
7656         tg3_stop_fw(tp);
7657
7658         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7659
7660         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
7661                 tg3_abort_hw(tp, 1);
7662
7663         if (reset_phy)
7664                 tg3_phy_reset(tp);
7665
7666         err = tg3_chip_reset(tp);
7667         if (err)
7668                 return err;
7669
7670         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7671
7672         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7673                 val = tr32(TG3_CPMU_CTRL);
7674                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7675                 tw32(TG3_CPMU_CTRL, val);
7676
7677                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7678                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7679                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7680                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7681
7682                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7683                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7684                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7685                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7686
7687                 val = tr32(TG3_CPMU_HST_ACC);
7688                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7689                 val |= CPMU_HST_ACC_MACCLK_6_25;
7690                 tw32(TG3_CPMU_HST_ACC, val);
7691         }
7692
7693         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7694                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7695                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7696                        PCIE_PWR_MGMT_L1_THRESH_4MS;
7697                 tw32(PCIE_PWR_MGMT_THRESH, val);
7698
7699                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7700                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7701
7702                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7703
7704                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7705                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7706         }
7707
7708         if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7709                 u32 grc_mode = tr32(GRC_MODE);
7710
7711                 /* Access the lower 1K of PL PCIE block registers. */
7712                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7713                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7714
7715                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7716                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7717                      val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7718
7719                 tw32(GRC_MODE, grc_mode);
7720         }
7721
7722         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
7723                 u32 grc_mode = tr32(GRC_MODE);
7724
7725                 /* Access the lower 1K of PL PCIE block registers. */
7726                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7727                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7728
7729                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5);
7730                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
7731                      val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
7732
7733                 tw32(GRC_MODE, grc_mode);
7734
7735                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7736                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7737                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7738                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7739         }
7740
7741         /* This works around an issue with Athlon chipsets on
7742          * B3 tigon3 silicon.  This bit has no effect on any
7743          * other revision.  But do not set this on PCI Express
7744          * chips and don't even touch the clocks if the CPMU is present.
7745          */
7746         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7747                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7748                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7749                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7750         }
7751
7752         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7753             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7754                 val = tr32(TG3PCI_PCISTATE);
7755                 val |= PCISTATE_RETRY_SAME_DMA;
7756                 tw32(TG3PCI_PCISTATE, val);
7757         }
7758
7759         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7760                 /* Allow reads and writes to the
7761                  * APE register and memory space.
7762                  */
7763                 val = tr32(TG3PCI_PCISTATE);
7764                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7765                        PCISTATE_ALLOW_APE_SHMEM_WR |
7766                        PCISTATE_ALLOW_APE_PSPACE_WR;
7767                 tw32(TG3PCI_PCISTATE, val);
7768         }
7769
7770         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7771                 /* Enable some hw fixes.  */
7772                 val = tr32(TG3PCI_MSI_DATA);
7773                 val |= (1 << 26) | (1 << 28) | (1 << 29);
7774                 tw32(TG3PCI_MSI_DATA, val);
7775         }
7776
7777         /* Descriptor ring init may make accesses to the
7778          * NIC SRAM area to setup the TX descriptors, so we
7779          * can only do this after the hardware has been
7780          * successfully reset.
7781          */
7782         err = tg3_init_rings(tp);
7783         if (err)
7784                 return err;
7785
7786         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
7787                 val = tr32(TG3PCI_DMA_RW_CTRL) &
7788                       ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7789                 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
7790                         val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
7791                 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7792         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7793                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7794                 /* This value is determined during the probe time DMA
7795                  * engine test, tg3_test_dma.
7796                  */
7797                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7798         }
7799
7800         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7801                           GRC_MODE_4X_NIC_SEND_RINGS |
7802                           GRC_MODE_NO_TX_PHDR_CSUM |
7803                           GRC_MODE_NO_RX_PHDR_CSUM);
7804         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7805
7806         /* Pseudo-header checksum is done by hardware logic and not
7807          * the offload processers, so make the chip do the pseudo-
7808          * header checksums on receive.  For transmit it is more
7809          * convenient to do the pseudo-header checksum in software
7810          * as Linux does that on transmit for us in all cases.
7811          */
7812         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7813
7814         tw32(GRC_MODE,
7815              tp->grc_mode |
7816              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7817
7818         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7819         val = tr32(GRC_MISC_CFG);
7820         val &= ~0xff;
7821         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7822         tw32(GRC_MISC_CFG, val);
7823
7824         /* Initialize MBUF/DESC pool. */
7825         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7826                 /* Do nothing.  */
7827         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7828                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7829                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7830                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7831                 else
7832                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7833                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7834                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7835         } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7836                 int fw_len;
7837
7838                 fw_len = tp->fw_len;
7839                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7840                 tw32(BUFMGR_MB_POOL_ADDR,
7841                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7842                 tw32(BUFMGR_MB_POOL_SIZE,
7843                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7844         }
7845
7846         if (tp->dev->mtu <= ETH_DATA_LEN) {
7847                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7848                      tp->bufmgr_config.mbuf_read_dma_low_water);
7849                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7850                      tp->bufmgr_config.mbuf_mac_rx_low_water);
7851                 tw32(BUFMGR_MB_HIGH_WATER,
7852                      tp->bufmgr_config.mbuf_high_water);
7853         } else {
7854                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7855                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7856                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7857                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7858                 tw32(BUFMGR_MB_HIGH_WATER,
7859                      tp->bufmgr_config.mbuf_high_water_jumbo);
7860         }
7861         tw32(BUFMGR_DMA_LOW_WATER,
7862              tp->bufmgr_config.dma_low_water);
7863         tw32(BUFMGR_DMA_HIGH_WATER,
7864              tp->bufmgr_config.dma_high_water);
7865
7866         val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
7867         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7868                 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
7869         tw32(BUFMGR_MODE, val);
7870         for (i = 0; i < 2000; i++) {
7871                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7872                         break;
7873                 udelay(10);
7874         }
7875         if (i >= 2000) {
7876                 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
7877                 return -ENODEV;
7878         }
7879
7880         /* Setup replenish threshold. */
7881         val = tp->rx_pending / 8;
7882         if (val == 0)
7883                 val = 1;
7884         else if (val > tp->rx_std_max_post)
7885                 val = tp->rx_std_max_post;
7886         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7887                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7888                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7889
7890                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7891                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7892         }
7893
7894         tw32(RCVBDI_STD_THRESH, val);
7895
7896         /* Initialize TG3_BDINFO's at:
7897          *  RCVDBDI_STD_BD:     standard eth size rx ring
7898          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
7899          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
7900          *
7901          * like so:
7902          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
7903          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
7904          *                              ring attribute flags
7905          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
7906          *
7907          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7908          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7909          *
7910          * The size of each ring is fixed in the firmware, but the location is
7911          * configurable.
7912          */
7913         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7914              ((u64) tpr->rx_std_mapping >> 32));
7915         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7916              ((u64) tpr->rx_std_mapping & 0xffffffff));
7917         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
7918             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
7919                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7920                      NIC_SRAM_RX_BUFFER_DESC);
7921
7922         /* Disable the mini ring */
7923         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7924                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7925                      BDINFO_FLAGS_DISABLED);
7926
7927         /* Program the jumbo buffer descriptor ring control
7928          * blocks on those devices that have them.
7929          */
7930         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7931             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7932                 /* Setup replenish threshold. */
7933                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7934
7935                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7936                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7937                              ((u64) tpr->rx_jmb_mapping >> 32));
7938                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7939                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7940                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7941                              (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7942                              BDINFO_FLAGS_USE_EXT_RECV);
7943                         if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) ||
7944                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7945                                 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7946                                      NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7947                 } else {
7948                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7949                              BDINFO_FLAGS_DISABLED);
7950                 }
7951
7952                 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
7953                         val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7954                               (TG3_RX_STD_DMA_SZ << 2);
7955                 else
7956                         val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
7957         } else
7958                 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7959
7960         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7961
7962         tpr->rx_std_prod_idx = tp->rx_pending;
7963         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
7964
7965         tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7966                           tp->rx_jumbo_pending : 0;
7967         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
7968
7969         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
7970                 tw32(STD_REPLENISH_LWM, 32);
7971                 tw32(JMB_REPLENISH_LWM, 16);
7972         }
7973
7974         tg3_rings_reset(tp);
7975
7976         /* Initialize MAC address and backoff seed. */
7977         __tg3_set_mac_addr(tp, 0);
7978
7979         /* MTU + ethernet header + FCS + optional VLAN tag */
7980         tw32(MAC_RX_MTU_SIZE,
7981              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7982
7983         /* The slot time is changed by tg3_setup_phy if we
7984          * run at gigabit with half duplex.
7985          */
7986         tw32(MAC_TX_LENGTHS,
7987              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7988              (6 << TX_LENGTHS_IPG_SHIFT) |
7989              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7990
7991         /* Receive rules. */
7992         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7993         tw32(RCVLPC_CONFIG, 0x0181);
7994
7995         /* Calculate RDMAC_MODE setting early, we need it to determine
7996          * the RCVLPC_STATE_ENABLE mask.
7997          */
7998         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7999                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
8000                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
8001                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
8002                       RDMAC_MODE_LNGREAD_ENAB);
8003
8004         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8005             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8006                 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
8007
8008         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8009             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8010             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8011                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
8012                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
8013                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
8014
8015         /* If statement applies to 5705 and 5750 PCI devices only */
8016         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8017              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8018             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
8019                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
8020                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
8021                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
8022                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8023                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
8024                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8025                 }
8026         }
8027
8028         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
8029                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8030
8031         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8032                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8033
8034         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
8035             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8036             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8037                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
8038
8039         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8040             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8041             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8042             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
8043             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
8044                 val = tr32(TG3_RDMA_RSRVCTRL_REG);
8045                 tw32(TG3_RDMA_RSRVCTRL_REG,
8046                      val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
8047         }
8048
8049         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
8050                 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
8051                 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val |
8052                      TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
8053                      TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
8054         }
8055
8056         /* Receive/send statistics. */
8057         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
8058                 val = tr32(RCVLPC_STATS_ENABLE);
8059                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8060                 tw32(RCVLPC_STATS_ENABLE, val);
8061         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8062                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8063                 val = tr32(RCVLPC_STATS_ENABLE);
8064                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8065                 tw32(RCVLPC_STATS_ENABLE, val);
8066         } else {
8067                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8068         }
8069         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8070         tw32(SNDDATAI_STATSENAB, 0xffffff);
8071         tw32(SNDDATAI_STATSCTRL,
8072              (SNDDATAI_SCTRL_ENABLE |
8073               SNDDATAI_SCTRL_FASTUPD));
8074
8075         /* Setup host coalescing engine. */
8076         tw32(HOSTCC_MODE, 0);
8077         for (i = 0; i < 2000; i++) {
8078                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8079                         break;
8080                 udelay(10);
8081         }
8082
8083         __tg3_set_coalesce(tp, &tp->coal);
8084
8085         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8086                 /* Status/statistics block address.  See tg3_timer,
8087                  * the tg3_periodic_fetch_stats call there, and
8088                  * tg3_get_stats to see how this works for 5705/5750 chips.
8089                  */
8090                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8091                      ((u64) tp->stats_mapping >> 32));
8092                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8093                      ((u64) tp->stats_mapping & 0xffffffff));
8094                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8095
8096                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
8097
8098                 /* Clear statistics and status block memory areas */
8099                 for (i = NIC_SRAM_STATS_BLK;
8100                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8101                      i += sizeof(u32)) {
8102                         tg3_write_mem(tp, i, 0);
8103                         udelay(40);
8104                 }
8105         }
8106
8107         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8108
8109         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8110         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8111         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8112                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8113
8114         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
8115                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
8116                 /* reset to prevent losing 1st rx packet intermittently */
8117                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8118                 udelay(10);
8119         }
8120
8121         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8122                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8123         else
8124                 tp->mac_mode = 0;
8125         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8126                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
8127         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8128             !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8129             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8130                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8131         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8132         udelay(40);
8133
8134         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8135          * If TG3_FLG2_IS_NIC is zero, we should read the
8136          * register to preserve the GPIO settings for LOMs. The GPIOs,
8137          * whether used as inputs or outputs, are set by boot code after
8138          * reset.
8139          */
8140         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
8141                 u32 gpio_mask;
8142
8143                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8144                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8145                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8146
8147                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8148                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8149                                      GRC_LCLCTRL_GPIO_OUTPUT3;
8150
8151                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8152                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8153
8154                 tp->grc_local_ctrl &= ~gpio_mask;
8155                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8156
8157                 /* GPIO1 must be driven high for eeprom write protect */
8158                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8159                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8160                                                GRC_LCLCTRL_GPIO_OUTPUT1);
8161         }
8162         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8163         udelay(100);
8164
8165         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
8166                 val = tr32(MSGINT_MODE);
8167                 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8168                 tw32(MSGINT_MODE, val);
8169         }
8170
8171         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8172                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8173                 udelay(40);
8174         }
8175
8176         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8177                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8178                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8179                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8180                WDMAC_MODE_LNGREAD_ENAB);
8181
8182         /* If statement applies to 5705 and 5750 PCI devices only */
8183         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8184              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8185             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
8186                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8187                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8188                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8189                         /* nothing */
8190                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8191                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8192                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8193                         val |= WDMAC_MODE_RX_ACCEL;
8194                 }
8195         }
8196
8197         /* Enable host coalescing bug fix */
8198         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8199                 val |= WDMAC_MODE_STATUS_TAG_FIX;
8200
8201         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8202                 val |= WDMAC_MODE_BURST_ALL_DATA;
8203
8204         tw32_f(WDMAC_MODE, val);
8205         udelay(40);
8206
8207         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8208                 u16 pcix_cmd;
8209
8210                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8211                                      &pcix_cmd);
8212                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8213                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8214                         pcix_cmd |= PCI_X_CMD_READ_2K;
8215                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8216                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8217                         pcix_cmd |= PCI_X_CMD_READ_2K;
8218                 }
8219                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8220                                       pcix_cmd);
8221         }
8222
8223         tw32_f(RDMAC_MODE, rdmac_mode);
8224         udelay(40);
8225
8226         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8227         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8228                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8229
8230         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8231                 tw32(SNDDATAC_MODE,
8232                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8233         else
8234                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8235
8236         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8237         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8238         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8239         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8240         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8241                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8242         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8243         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8244                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8245         tw32(SNDBDI_MODE, val);
8246         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8247
8248         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8249                 err = tg3_load_5701_a0_firmware_fix(tp);
8250                 if (err)
8251                         return err;
8252         }
8253
8254         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8255                 err = tg3_load_tso_firmware(tp);
8256                 if (err)
8257                         return err;
8258         }
8259
8260         tp->tx_mode = TX_MODE_ENABLE;
8261         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
8262             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8263                 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
8264         tw32_f(MAC_TX_MODE, tp->tx_mode);
8265         udelay(100);
8266
8267         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8268                 u32 reg = MAC_RSS_INDIR_TBL_0;
8269                 u8 *ent = (u8 *)&val;
8270
8271                 /* Setup the indirection table */
8272                 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8273                         int idx = i % sizeof(val);
8274
8275                         ent[idx] = i % (tp->irq_cnt - 1);
8276                         if (idx == sizeof(val) - 1) {
8277                                 tw32(reg, val);
8278                                 reg += 4;
8279                         }
8280                 }
8281
8282                 /* Setup the "secret" hash key. */
8283                 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8284                 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8285                 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8286                 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8287                 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8288                 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8289                 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8290                 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8291                 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8292                 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8293         }
8294
8295         tp->rx_mode = RX_MODE_ENABLE;
8296         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8297                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8298
8299         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8300                 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8301                                RX_MODE_RSS_ITBL_HASH_BITS_7 |
8302                                RX_MODE_RSS_IPV6_HASH_EN |
8303                                RX_MODE_RSS_TCP_IPV6_HASH_EN |
8304                                RX_MODE_RSS_IPV4_HASH_EN |
8305                                RX_MODE_RSS_TCP_IPV4_HASH_EN;
8306
8307         tw32_f(MAC_RX_MODE, tp->rx_mode);
8308         udelay(10);
8309
8310         tw32(MAC_LED_CTRL, tp->led_ctrl);
8311
8312         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8313         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8314                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8315                 udelay(10);
8316         }
8317         tw32_f(MAC_RX_MODE, tp->rx_mode);
8318         udelay(10);
8319
8320         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8321                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8322                         !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
8323                         /* Set drive transmission level to 1.2V  */
8324                         /* only if the signal pre-emphasis bit is not set  */
8325                         val = tr32(MAC_SERDES_CFG);
8326                         val &= 0xfffff000;
8327                         val |= 0x880;
8328                         tw32(MAC_SERDES_CFG, val);
8329                 }
8330                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8331                         tw32(MAC_SERDES_CFG, 0x616000);
8332         }
8333
8334         /* Prevent chip from dropping frames when flow control
8335          * is enabled.
8336          */
8337         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8338                 val = 1;
8339         else
8340                 val = 2;
8341         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8342
8343         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8344             (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
8345                 /* Use hardware link auto-negotiation */
8346                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8347         }
8348
8349         if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8350             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8351                 u32 tmp;
8352
8353                 tmp = tr32(SERDES_RX_CTRL);
8354                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8355                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8356                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8357                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8358         }
8359
8360         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8361                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
8362                         tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
8363                         tp->link_config.speed = tp->link_config.orig_speed;
8364                         tp->link_config.duplex = tp->link_config.orig_duplex;
8365                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
8366                 }
8367
8368                 err = tg3_setup_phy(tp, 0);
8369                 if (err)
8370                         return err;
8371
8372                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8373                     !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8374                         u32 tmp;
8375
8376                         /* Clear CRC stats. */
8377                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8378                                 tg3_writephy(tp, MII_TG3_TEST1,
8379                                              tmp | MII_TG3_TEST1_CRC_EN);
8380                                 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
8381                         }
8382                 }
8383         }
8384
8385         __tg3_set_rx_mode(tp->dev);
8386
8387         /* Initialize receive rules. */
8388         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
8389         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8390         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
8391         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8392
8393         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8394             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8395                 limit = 8;
8396         else
8397                 limit = 16;
8398         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8399                 limit -= 4;
8400         switch (limit) {
8401         case 16:
8402                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
8403         case 15:
8404                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
8405         case 14:
8406                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
8407         case 13:
8408                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
8409         case 12:
8410                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
8411         case 11:
8412                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
8413         case 10:
8414                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
8415         case 9:
8416                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
8417         case 8:
8418                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
8419         case 7:
8420                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
8421         case 6:
8422                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
8423         case 5:
8424                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
8425         case 4:
8426                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
8427         case 3:
8428                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
8429         case 2:
8430         case 1:
8431
8432         default:
8433                 break;
8434         }
8435
8436         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8437                 /* Write our heartbeat update interval to APE. */
8438                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8439                                 APE_HOST_HEARTBEAT_INT_DISABLE);
8440
8441         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8442
8443         return 0;
8444 }
8445
8446 /* Called at device open time to get the chip ready for
8447  * packet processing.  Invoked with tp->lock held.
8448  */
8449 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8450 {
8451         tg3_switch_clocks(tp);
8452
8453         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8454
8455         return tg3_reset_hw(tp, reset_phy);
8456 }
8457
8458 #define TG3_STAT_ADD32(PSTAT, REG) \
8459 do {    u32 __val = tr32(REG); \
8460         (PSTAT)->low += __val; \
8461         if ((PSTAT)->low < __val) \
8462                 (PSTAT)->high += 1; \
8463 } while (0)
8464
8465 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8466 {
8467         struct tg3_hw_stats *sp = tp->hw_stats;
8468
8469         if (!netif_carrier_ok(tp->dev))
8470                 return;
8471
8472         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8473         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8474         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8475         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8476         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8477         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8478         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8479         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8480         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8481         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8482         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8483         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8484         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8485
8486         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8487         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8488         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8489         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8490         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8491         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8492         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8493         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8494         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8495         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8496         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8497         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8498         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8499         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8500
8501         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8502         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8503         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8504 }
8505
8506 static void tg3_timer(unsigned long __opaque)
8507 {
8508         struct tg3 *tp = (struct tg3 *) __opaque;
8509
8510         if (tp->irq_sync)
8511                 goto restart_timer;
8512
8513         spin_lock(&tp->lock);
8514
8515         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8516                 /* All of this garbage is because when using non-tagged
8517                  * IRQ status the mailbox/status_block protocol the chip
8518                  * uses with the cpu is race prone.
8519                  */
8520                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8521                         tw32(GRC_LOCAL_CTRL,
8522                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8523                 } else {
8524                         tw32(HOSTCC_MODE, tp->coalesce_mode |
8525                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8526                 }
8527
8528                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8529                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8530                         spin_unlock(&tp->lock);
8531                         schedule_work(&tp->reset_task);
8532                         return;
8533                 }
8534         }
8535
8536         /* This part only runs once per second. */
8537         if (!--tp->timer_counter) {
8538                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8539                         tg3_periodic_fetch_stats(tp);
8540
8541                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8542                         u32 mac_stat;
8543                         int phy_event;
8544
8545                         mac_stat = tr32(MAC_STATUS);
8546
8547                         phy_event = 0;
8548                         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
8549                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8550                                         phy_event = 1;
8551                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8552                                 phy_event = 1;
8553
8554                         if (phy_event)
8555                                 tg3_setup_phy(tp, 0);
8556                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8557                         u32 mac_stat = tr32(MAC_STATUS);
8558                         int need_setup = 0;
8559
8560                         if (netif_carrier_ok(tp->dev) &&
8561                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8562                                 need_setup = 1;
8563                         }
8564                         if (!netif_carrier_ok(tp->dev) &&
8565                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
8566                                          MAC_STATUS_SIGNAL_DET))) {
8567                                 need_setup = 1;
8568                         }
8569                         if (need_setup) {
8570                                 if (!tp->serdes_counter) {
8571                                         tw32_f(MAC_MODE,
8572                                              (tp->mac_mode &
8573                                               ~MAC_MODE_PORT_MODE_MASK));
8574                                         udelay(40);
8575                                         tw32_f(MAC_MODE, tp->mac_mode);
8576                                         udelay(40);
8577                                 }
8578                                 tg3_setup_phy(tp, 0);
8579                         }
8580                 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8581                            (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8582                         tg3_serdes_parallel_detect(tp);
8583                 }
8584
8585                 tp->timer_counter = tp->timer_multiplier;
8586         }
8587
8588         /* Heartbeat is only sent once every 2 seconds.
8589          *
8590          * The heartbeat is to tell the ASF firmware that the host
8591          * driver is still alive.  In the event that the OS crashes,
8592          * ASF needs to reset the hardware to free up the FIFO space
8593          * that may be filled with rx packets destined for the host.
8594          * If the FIFO is full, ASF will no longer function properly.
8595          *
8596          * Unintended resets have been reported on real time kernels
8597          * where the timer doesn't run on time.  Netpoll will also have
8598          * same problem.
8599          *
8600          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8601          * to check the ring condition when the heartbeat is expiring
8602          * before doing the reset.  This will prevent most unintended
8603          * resets.
8604          */
8605         if (!--tp->asf_counter) {
8606                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8607                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8608                         tg3_wait_for_event_ack(tp);
8609
8610                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8611                                       FWCMD_NICDRV_ALIVE3);
8612                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8613                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
8614                                       TG3_FW_UPDATE_TIMEOUT_SEC);
8615
8616                         tg3_generate_fw_event(tp);
8617                 }
8618                 tp->asf_counter = tp->asf_multiplier;
8619         }
8620
8621         spin_unlock(&tp->lock);
8622
8623 restart_timer:
8624         tp->timer.expires = jiffies + tp->timer_offset;
8625         add_timer(&tp->timer);
8626 }
8627
8628 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8629 {
8630         irq_handler_t fn;
8631         unsigned long flags;
8632         char *name;
8633         struct tg3_napi *tnapi = &tp->napi[irq_num];
8634
8635         if (tp->irq_cnt == 1)
8636                 name = tp->dev->name;
8637         else {
8638                 name = &tnapi->irq_lbl[0];
8639                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8640                 name[IFNAMSIZ-1] = 0;
8641         }
8642
8643         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8644                 fn = tg3_msi;
8645                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8646                         fn = tg3_msi_1shot;
8647                 flags = IRQF_SAMPLE_RANDOM;
8648         } else {
8649                 fn = tg3_interrupt;
8650                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8651                         fn = tg3_interrupt_tagged;
8652                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8653         }
8654
8655         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8656 }
8657
8658 static int tg3_test_interrupt(struct tg3 *tp)
8659 {
8660         struct tg3_napi *tnapi = &tp->napi[0];
8661         struct net_device *dev = tp->dev;
8662         int err, i, intr_ok = 0;
8663         u32 val;
8664
8665         if (!netif_running(dev))
8666                 return -ENODEV;
8667
8668         tg3_disable_ints(tp);
8669
8670         free_irq(tnapi->irq_vec, tnapi);
8671
8672         /*
8673          * Turn off MSI one shot mode.  Otherwise this test has no
8674          * observable way to know whether the interrupt was delivered.
8675          */
8676         if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8677             (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8678                 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8679                 tw32(MSGINT_MODE, val);
8680         }
8681
8682         err = request_irq(tnapi->irq_vec, tg3_test_isr,
8683                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8684         if (err)
8685                 return err;
8686
8687         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8688         tg3_enable_ints(tp);
8689
8690         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8691                tnapi->coal_now);
8692
8693         for (i = 0; i < 5; i++) {
8694                 u32 int_mbox, misc_host_ctrl;
8695
8696                 int_mbox = tr32_mailbox(tnapi->int_mbox);
8697                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8698
8699                 if ((int_mbox != 0) ||
8700                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8701                         intr_ok = 1;
8702                         break;
8703                 }
8704
8705                 msleep(10);
8706         }
8707
8708         tg3_disable_ints(tp);
8709
8710         free_irq(tnapi->irq_vec, tnapi);
8711
8712         err = tg3_request_irq(tp, 0);
8713
8714         if (err)
8715                 return err;
8716
8717         if (intr_ok) {
8718                 /* Reenable MSI one shot mode. */
8719                 if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8720                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8721                         val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8722                         tw32(MSGINT_MODE, val);
8723                 }
8724                 return 0;
8725         }
8726
8727         return -EIO;
8728 }
8729
8730 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8731  * successfully restored
8732  */
8733 static int tg3_test_msi(struct tg3 *tp)
8734 {
8735         int err;
8736         u16 pci_cmd;
8737
8738         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8739                 return 0;
8740
8741         /* Turn off SERR reporting in case MSI terminates with Master
8742          * Abort.
8743          */
8744         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8745         pci_write_config_word(tp->pdev, PCI_COMMAND,
8746                               pci_cmd & ~PCI_COMMAND_SERR);
8747
8748         err = tg3_test_interrupt(tp);
8749
8750         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8751
8752         if (!err)
8753                 return 0;
8754
8755         /* other failures */
8756         if (err != -EIO)
8757                 return err;
8758
8759         /* MSI test failed, go back to INTx mode */
8760         netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
8761                     "to INTx mode. Please report this failure to the PCI "
8762                     "maintainer and include system chipset information\n");
8763
8764         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8765
8766         pci_disable_msi(tp->pdev);
8767
8768         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8769         tp->napi[0].irq_vec = tp->pdev->irq;
8770
8771         err = tg3_request_irq(tp, 0);
8772         if (err)
8773                 return err;
8774
8775         /* Need to reset the chip because the MSI cycle may have terminated
8776          * with Master Abort.
8777          */
8778         tg3_full_lock(tp, 1);
8779
8780         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8781         err = tg3_init_hw(tp, 1);
8782
8783         tg3_full_unlock(tp);
8784
8785         if (err)
8786                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8787
8788         return err;
8789 }
8790
8791 static int tg3_request_firmware(struct tg3 *tp)
8792 {
8793         const __be32 *fw_data;
8794
8795         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8796                 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
8797                            tp->fw_needed);
8798                 return -ENOENT;
8799         }
8800
8801         fw_data = (void *)tp->fw->data;
8802
8803         /* Firmware blob starts with version numbers, followed by
8804          * start address and _full_ length including BSS sections
8805          * (which must be longer than the actual data, of course
8806          */
8807
8808         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
8809         if (tp->fw_len < (tp->fw->size - 12)) {
8810                 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
8811                            tp->fw_len, tp->fw_needed);
8812                 release_firmware(tp->fw);
8813                 tp->fw = NULL;
8814                 return -EINVAL;
8815         }
8816
8817         /* We no longer need firmware; we have it. */
8818         tp->fw_needed = NULL;
8819         return 0;
8820 }
8821
8822 static bool tg3_enable_msix(struct tg3 *tp)
8823 {
8824         int i, rc, cpus = num_online_cpus();
8825         struct msix_entry msix_ent[tp->irq_max];
8826
8827         if (cpus == 1)
8828                 /* Just fallback to the simpler MSI mode. */
8829                 return false;
8830
8831         /*
8832          * We want as many rx rings enabled as there are cpus.
8833          * The first MSIX vector only deals with link interrupts, etc,
8834          * so we add one to the number of vectors we are requesting.
8835          */
8836         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8837
8838         for (i = 0; i < tp->irq_max; i++) {
8839                 msix_ent[i].entry  = i;
8840                 msix_ent[i].vector = 0;
8841         }
8842
8843         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8844         if (rc < 0) {
8845                 return false;
8846         } else if (rc != 0) {
8847                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8848                         return false;
8849                 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
8850                               tp->irq_cnt, rc);
8851                 tp->irq_cnt = rc;
8852         }
8853
8854         for (i = 0; i < tp->irq_max; i++)
8855                 tp->napi[i].irq_vec = msix_ent[i].vector;
8856
8857         netif_set_real_num_tx_queues(tp->dev, 1);
8858         rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1;
8859         if (netif_set_real_num_rx_queues(tp->dev, rc)) {
8860                 pci_disable_msix(tp->pdev);
8861                 return false;
8862         }
8863         if (tp->irq_cnt > 1)
8864                 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8865
8866         return true;
8867 }
8868
8869 static void tg3_ints_init(struct tg3 *tp)
8870 {
8871         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8872             !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8873                 /* All MSI supporting chips should support tagged
8874                  * status.  Assert that this is the case.
8875                  */
8876                 netdev_warn(tp->dev,
8877                             "MSI without TAGGED_STATUS? Not using MSI\n");
8878                 goto defcfg;
8879         }
8880
8881         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8882                 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8883         else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8884                  pci_enable_msi(tp->pdev) == 0)
8885                 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8886
8887         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8888                 u32 msi_mode = tr32(MSGINT_MODE);
8889                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8890                         msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8891                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8892         }
8893 defcfg:
8894         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8895                 tp->irq_cnt = 1;
8896                 tp->napi[0].irq_vec = tp->pdev->irq;
8897                 netif_set_real_num_tx_queues(tp->dev, 1);
8898         }
8899 }
8900
8901 static void tg3_ints_fini(struct tg3 *tp)
8902 {
8903         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8904                 pci_disable_msix(tp->pdev);
8905         else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8906                 pci_disable_msi(tp->pdev);
8907         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8908         tp->tg3_flags3 &= ~(TG3_FLG3_ENABLE_RSS | TG3_FLG3_ENABLE_TSS);
8909 }
8910
8911 static int tg3_open(struct net_device *dev)
8912 {
8913         struct tg3 *tp = netdev_priv(dev);
8914         int i, err;
8915
8916         if (tp->fw_needed) {
8917                 err = tg3_request_firmware(tp);
8918                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8919                         if (err)
8920                                 return err;
8921                 } else if (err) {
8922                         netdev_warn(tp->dev, "TSO capability disabled\n");
8923                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8924                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8925                         netdev_notice(tp->dev, "TSO capability restored\n");
8926                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8927                 }
8928         }
8929
8930         netif_carrier_off(tp->dev);
8931
8932         err = tg3_set_power_state(tp, PCI_D0);
8933         if (err)
8934                 return err;
8935
8936         tg3_full_lock(tp, 0);
8937
8938         tg3_disable_ints(tp);
8939         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8940
8941         tg3_full_unlock(tp);
8942
8943         /*
8944          * Setup interrupts first so we know how
8945          * many NAPI resources to allocate
8946          */
8947         tg3_ints_init(tp);
8948
8949         /* The placement of this call is tied
8950          * to the setup and use of Host TX descriptors.
8951          */
8952         err = tg3_alloc_consistent(tp);
8953         if (err)
8954                 goto err_out1;
8955
8956         tg3_napi_init(tp);
8957
8958         tg3_napi_enable(tp);
8959
8960         for (i = 0; i < tp->irq_cnt; i++) {
8961                 struct tg3_napi *tnapi = &tp->napi[i];
8962                 err = tg3_request_irq(tp, i);
8963                 if (err) {
8964                         for (i--; i >= 0; i--)
8965                                 free_irq(tnapi->irq_vec, tnapi);
8966                         break;
8967                 }
8968         }
8969
8970         if (err)
8971                 goto err_out2;
8972
8973         tg3_full_lock(tp, 0);
8974
8975         err = tg3_init_hw(tp, 1);
8976         if (err) {
8977                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8978                 tg3_free_rings(tp);
8979         } else {
8980                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8981                         tp->timer_offset = HZ;
8982                 else
8983                         tp->timer_offset = HZ / 10;
8984
8985                 BUG_ON(tp->timer_offset > HZ);
8986                 tp->timer_counter = tp->timer_multiplier =
8987                         (HZ / tp->timer_offset);
8988                 tp->asf_counter = tp->asf_multiplier =
8989                         ((HZ / tp->timer_offset) * 2);
8990
8991                 init_timer(&tp->timer);
8992                 tp->timer.expires = jiffies + tp->timer_offset;
8993                 tp->timer.data = (unsigned long) tp;
8994                 tp->timer.function = tg3_timer;
8995         }
8996
8997         tg3_full_unlock(tp);
8998
8999         if (err)
9000                 goto err_out3;
9001
9002         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
9003                 err = tg3_test_msi(tp);
9004
9005                 if (err) {
9006                         tg3_full_lock(tp, 0);
9007                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9008                         tg3_free_rings(tp);
9009                         tg3_full_unlock(tp);
9010
9011                         goto err_out2;
9012                 }
9013
9014                 if (!(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
9015                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
9016                         u32 val = tr32(PCIE_TRANSACTION_CFG);
9017
9018                         tw32(PCIE_TRANSACTION_CFG,
9019                              val | PCIE_TRANS_CFG_1SHOT_MSI);
9020                 }
9021         }
9022
9023         tg3_phy_start(tp);
9024
9025         tg3_full_lock(tp, 0);
9026
9027         add_timer(&tp->timer);
9028         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9029         tg3_enable_ints(tp);
9030
9031         tg3_full_unlock(tp);
9032
9033         netif_tx_start_all_queues(dev);
9034
9035         return 0;
9036
9037 err_out3:
9038         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9039                 struct tg3_napi *tnapi = &tp->napi[i];
9040                 free_irq(tnapi->irq_vec, tnapi);
9041         }
9042
9043 err_out2:
9044         tg3_napi_disable(tp);
9045         tg3_napi_fini(tp);
9046         tg3_free_consistent(tp);
9047
9048 err_out1:
9049         tg3_ints_fini(tp);
9050         return err;
9051 }
9052
9053 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
9054                                                  struct rtnl_link_stats64 *);
9055 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9056
9057 static int tg3_close(struct net_device *dev)
9058 {
9059         int i;
9060         struct tg3 *tp = netdev_priv(dev);
9061
9062         tg3_napi_disable(tp);
9063         cancel_work_sync(&tp->reset_task);
9064
9065         netif_tx_stop_all_queues(dev);
9066
9067         del_timer_sync(&tp->timer);
9068
9069         tg3_phy_stop(tp);
9070
9071         tg3_full_lock(tp, 1);
9072
9073         tg3_disable_ints(tp);
9074
9075         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9076         tg3_free_rings(tp);
9077         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9078
9079         tg3_full_unlock(tp);
9080
9081         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9082                 struct tg3_napi *tnapi = &tp->napi[i];
9083                 free_irq(tnapi->irq_vec, tnapi);
9084         }
9085
9086         tg3_ints_fini(tp);
9087
9088         tg3_get_stats64(tp->dev, &tp->net_stats_prev);
9089
9090         memcpy(&tp->estats_prev, tg3_get_estats(tp),
9091                sizeof(tp->estats_prev));
9092
9093         tg3_napi_fini(tp);
9094
9095         tg3_free_consistent(tp);
9096
9097         tg3_set_power_state(tp, PCI_D3hot);
9098
9099         netif_carrier_off(tp->dev);
9100
9101         return 0;
9102 }
9103
9104 static inline u64 get_stat64(tg3_stat64_t *val)
9105 {
9106        return ((u64)val->high << 32) | ((u64)val->low);
9107 }
9108
9109 static u64 calc_crc_errors(struct tg3 *tp)
9110 {
9111         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9112
9113         if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9114             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9115              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9116                 u32 val;
9117
9118                 spin_lock_bh(&tp->lock);
9119                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9120                         tg3_writephy(tp, MII_TG3_TEST1,
9121                                      val | MII_TG3_TEST1_CRC_EN);
9122                         tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
9123                 } else
9124                         val = 0;
9125                 spin_unlock_bh(&tp->lock);
9126
9127                 tp->phy_crc_errors += val;
9128
9129                 return tp->phy_crc_errors;
9130         }
9131
9132         return get_stat64(&hw_stats->rx_fcs_errors);
9133 }
9134
9135 #define ESTAT_ADD(member) \
9136         estats->member =        old_estats->member + \
9137                                 get_stat64(&hw_stats->member)
9138
9139 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9140 {
9141         struct tg3_ethtool_stats *estats = &tp->estats;
9142         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9143         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9144
9145         if (!hw_stats)
9146                 return old_estats;
9147
9148         ESTAT_ADD(rx_octets);
9149         ESTAT_ADD(rx_fragments);
9150         ESTAT_ADD(rx_ucast_packets);
9151         ESTAT_ADD(rx_mcast_packets);
9152         ESTAT_ADD(rx_bcast_packets);
9153         ESTAT_ADD(rx_fcs_errors);
9154         ESTAT_ADD(rx_align_errors);
9155         ESTAT_ADD(rx_xon_pause_rcvd);
9156         ESTAT_ADD(rx_xoff_pause_rcvd);
9157         ESTAT_ADD(rx_mac_ctrl_rcvd);
9158         ESTAT_ADD(rx_xoff_entered);
9159         ESTAT_ADD(rx_frame_too_long_errors);
9160         ESTAT_ADD(rx_jabbers);
9161         ESTAT_ADD(rx_undersize_packets);
9162         ESTAT_ADD(rx_in_length_errors);
9163         ESTAT_ADD(rx_out_length_errors);
9164         ESTAT_ADD(rx_64_or_less_octet_packets);
9165         ESTAT_ADD(rx_65_to_127_octet_packets);
9166         ESTAT_ADD(rx_128_to_255_octet_packets);
9167         ESTAT_ADD(rx_256_to_511_octet_packets);
9168         ESTAT_ADD(rx_512_to_1023_octet_packets);
9169         ESTAT_ADD(rx_1024_to_1522_octet_packets);
9170         ESTAT_ADD(rx_1523_to_2047_octet_packets);
9171         ESTAT_ADD(rx_2048_to_4095_octet_packets);
9172         ESTAT_ADD(rx_4096_to_8191_octet_packets);
9173         ESTAT_ADD(rx_8192_to_9022_octet_packets);
9174
9175         ESTAT_ADD(tx_octets);
9176         ESTAT_ADD(tx_collisions);
9177         ESTAT_ADD(tx_xon_sent);
9178         ESTAT_ADD(tx_xoff_sent);
9179         ESTAT_ADD(tx_flow_control);
9180         ESTAT_ADD(tx_mac_errors);
9181         ESTAT_ADD(tx_single_collisions);
9182         ESTAT_ADD(tx_mult_collisions);
9183         ESTAT_ADD(tx_deferred);
9184         ESTAT_ADD(tx_excessive_collisions);
9185         ESTAT_ADD(tx_late_collisions);
9186         ESTAT_ADD(tx_collide_2times);
9187         ESTAT_ADD(tx_collide_3times);
9188         ESTAT_ADD(tx_collide_4times);
9189         ESTAT_ADD(tx_collide_5times);
9190         ESTAT_ADD(tx_collide_6times);
9191         ESTAT_ADD(tx_collide_7times);
9192         ESTAT_ADD(tx_collide_8times);
9193         ESTAT_ADD(tx_collide_9times);
9194         ESTAT_ADD(tx_collide_10times);
9195         ESTAT_ADD(tx_collide_11times);
9196         ESTAT_ADD(tx_collide_12times);
9197         ESTAT_ADD(tx_collide_13times);
9198         ESTAT_ADD(tx_collide_14times);
9199         ESTAT_ADD(tx_collide_15times);
9200         ESTAT_ADD(tx_ucast_packets);
9201         ESTAT_ADD(tx_mcast_packets);
9202         ESTAT_ADD(tx_bcast_packets);
9203         ESTAT_ADD(tx_carrier_sense_errors);
9204         ESTAT_ADD(tx_discards);
9205         ESTAT_ADD(tx_errors);
9206
9207         ESTAT_ADD(dma_writeq_full);
9208         ESTAT_ADD(dma_write_prioq_full);
9209         ESTAT_ADD(rxbds_empty);
9210         ESTAT_ADD(rx_discards);
9211         ESTAT_ADD(rx_errors);
9212         ESTAT_ADD(rx_threshold_hit);
9213
9214         ESTAT_ADD(dma_readq_full);
9215         ESTAT_ADD(dma_read_prioq_full);
9216         ESTAT_ADD(tx_comp_queue_full);
9217
9218         ESTAT_ADD(ring_set_send_prod_index);
9219         ESTAT_ADD(ring_status_update);
9220         ESTAT_ADD(nic_irqs);
9221         ESTAT_ADD(nic_avoided_irqs);
9222         ESTAT_ADD(nic_tx_threshold_hit);
9223
9224         return estats;
9225 }
9226
9227 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
9228                                                  struct rtnl_link_stats64 *stats)
9229 {
9230         struct tg3 *tp = netdev_priv(dev);
9231         struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
9232         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9233
9234         if (!hw_stats)
9235                 return old_stats;
9236
9237         stats->rx_packets = old_stats->rx_packets +
9238                 get_stat64(&hw_stats->rx_ucast_packets) +
9239                 get_stat64(&hw_stats->rx_mcast_packets) +
9240                 get_stat64(&hw_stats->rx_bcast_packets);
9241
9242         stats->tx_packets = old_stats->tx_packets +
9243                 get_stat64(&hw_stats->tx_ucast_packets) +
9244                 get_stat64(&hw_stats->tx_mcast_packets) +
9245                 get_stat64(&hw_stats->tx_bcast_packets);
9246
9247         stats->rx_bytes = old_stats->rx_bytes +
9248                 get_stat64(&hw_stats->rx_octets);
9249         stats->tx_bytes = old_stats->tx_bytes +
9250                 get_stat64(&hw_stats->tx_octets);
9251
9252         stats->rx_errors = old_stats->rx_errors +
9253                 get_stat64(&hw_stats->rx_errors);
9254         stats->tx_errors = old_stats->tx_errors +
9255                 get_stat64(&hw_stats->tx_errors) +
9256                 get_stat64(&hw_stats->tx_mac_errors) +
9257                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9258                 get_stat64(&hw_stats->tx_discards);
9259
9260         stats->multicast = old_stats->multicast +
9261                 get_stat64(&hw_stats->rx_mcast_packets);
9262         stats->collisions = old_stats->collisions +
9263                 get_stat64(&hw_stats->tx_collisions);
9264
9265         stats->rx_length_errors = old_stats->rx_length_errors +
9266                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9267                 get_stat64(&hw_stats->rx_undersize_packets);
9268
9269         stats->rx_over_errors = old_stats->rx_over_errors +
9270                 get_stat64(&hw_stats->rxbds_empty);
9271         stats->rx_frame_errors = old_stats->rx_frame_errors +
9272                 get_stat64(&hw_stats->rx_align_errors);
9273         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9274                 get_stat64(&hw_stats->tx_discards);
9275         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9276                 get_stat64(&hw_stats->tx_carrier_sense_errors);
9277
9278         stats->rx_crc_errors = old_stats->rx_crc_errors +
9279                 calc_crc_errors(tp);
9280
9281         stats->rx_missed_errors = old_stats->rx_missed_errors +
9282                 get_stat64(&hw_stats->rx_discards);
9283
9284         return stats;
9285 }
9286
9287 static inline u32 calc_crc(unsigned char *buf, int len)
9288 {
9289         u32 reg;
9290         u32 tmp;
9291         int j, k;
9292
9293         reg = 0xffffffff;
9294
9295         for (j = 0; j < len; j++) {
9296                 reg ^= buf[j];
9297
9298                 for (k = 0; k < 8; k++) {
9299                         tmp = reg & 0x01;
9300
9301                         reg >>= 1;
9302
9303                         if (tmp)
9304                                 reg ^= 0xedb88320;
9305                 }
9306         }
9307
9308         return ~reg;
9309 }
9310
9311 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9312 {
9313         /* accept or reject all multicast frames */
9314         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9315         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9316         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9317         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9318 }
9319
9320 static void __tg3_set_rx_mode(struct net_device *dev)
9321 {
9322         struct tg3 *tp = netdev_priv(dev);
9323         u32 rx_mode;
9324
9325         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9326                                   RX_MODE_KEEP_VLAN_TAG);
9327
9328         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9329          * flag clear.
9330          */
9331 #if TG3_VLAN_TAG_USED
9332         if (!tp->vlgrp &&
9333             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9334                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9335 #else
9336         /* By definition, VLAN is disabled always in this
9337          * case.
9338          */
9339         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9340                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9341 #endif
9342
9343         if (dev->flags & IFF_PROMISC) {
9344                 /* Promiscuous mode. */
9345                 rx_mode |= RX_MODE_PROMISC;
9346         } else if (dev->flags & IFF_ALLMULTI) {
9347                 /* Accept all multicast. */
9348                 tg3_set_multi(tp, 1);
9349         } else if (netdev_mc_empty(dev)) {
9350                 /* Reject all multicast. */
9351                 tg3_set_multi(tp, 0);
9352         } else {
9353                 /* Accept one or more multicast(s). */
9354                 struct netdev_hw_addr *ha;
9355                 u32 mc_filter[4] = { 0, };
9356                 u32 regidx;
9357                 u32 bit;
9358                 u32 crc;
9359
9360                 netdev_for_each_mc_addr(ha, dev) {
9361                         crc = calc_crc(ha->addr, ETH_ALEN);
9362                         bit = ~crc & 0x7f;
9363                         regidx = (bit & 0x60) >> 5;
9364                         bit &= 0x1f;
9365                         mc_filter[regidx] |= (1 << bit);
9366                 }
9367
9368                 tw32(MAC_HASH_REG_0, mc_filter[0]);
9369                 tw32(MAC_HASH_REG_1, mc_filter[1]);
9370                 tw32(MAC_HASH_REG_2, mc_filter[2]);
9371                 tw32(MAC_HASH_REG_3, mc_filter[3]);
9372         }
9373
9374         if (rx_mode != tp->rx_mode) {
9375                 tp->rx_mode = rx_mode;
9376                 tw32_f(MAC_RX_MODE, rx_mode);
9377                 udelay(10);
9378         }
9379 }
9380
9381 static void tg3_set_rx_mode(struct net_device *dev)
9382 {
9383         struct tg3 *tp = netdev_priv(dev);
9384
9385         if (!netif_running(dev))
9386                 return;
9387
9388         tg3_full_lock(tp, 0);
9389         __tg3_set_rx_mode(dev);
9390         tg3_full_unlock(tp);
9391 }
9392
9393 #define TG3_REGDUMP_LEN         (32 * 1024)
9394
9395 static int tg3_get_regs_len(struct net_device *dev)
9396 {
9397         return TG3_REGDUMP_LEN;
9398 }
9399
9400 static void tg3_get_regs(struct net_device *dev,
9401                 struct ethtool_regs *regs, void *_p)
9402 {
9403         u32 *p = _p;
9404         struct tg3 *tp = netdev_priv(dev);
9405         u8 *orig_p = _p;
9406         int i;
9407
9408         regs->version = 0;
9409
9410         memset(p, 0, TG3_REGDUMP_LEN);
9411
9412         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9413                 return;
9414
9415         tg3_full_lock(tp, 0);
9416
9417 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
9418 #define GET_REG32_LOOP(base, len)               \
9419 do {    p = (u32 *)(orig_p + (base));           \
9420         for (i = 0; i < len; i += 4)            \
9421                 __GET_REG32((base) + i);        \
9422 } while (0)
9423 #define GET_REG32_1(reg)                        \
9424 do {    p = (u32 *)(orig_p + (reg));            \
9425         __GET_REG32((reg));                     \
9426 } while (0)
9427
9428         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9429         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9430         GET_REG32_LOOP(MAC_MODE, 0x4f0);
9431         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9432         GET_REG32_1(SNDDATAC_MODE);
9433         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9434         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9435         GET_REG32_1(SNDBDC_MODE);
9436         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9437         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9438         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9439         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9440         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9441         GET_REG32_1(RCVDCC_MODE);
9442         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9443         GET_REG32_LOOP(RCVCC_MODE, 0x14);
9444         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9445         GET_REG32_1(MBFREE_MODE);
9446         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9447         GET_REG32_LOOP(MEMARB_MODE, 0x10);
9448         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9449         GET_REG32_LOOP(RDMAC_MODE, 0x08);
9450         GET_REG32_LOOP(WDMAC_MODE, 0x08);
9451         GET_REG32_1(RX_CPU_MODE);
9452         GET_REG32_1(RX_CPU_STATE);
9453         GET_REG32_1(RX_CPU_PGMCTR);
9454         GET_REG32_1(RX_CPU_HWBKPT);
9455         GET_REG32_1(TX_CPU_MODE);
9456         GET_REG32_1(TX_CPU_STATE);
9457         GET_REG32_1(TX_CPU_PGMCTR);
9458         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9459         GET_REG32_LOOP(FTQ_RESET, 0x120);
9460         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9461         GET_REG32_1(DMAC_MODE);
9462         GET_REG32_LOOP(GRC_MODE, 0x4c);
9463         if (tp->tg3_flags & TG3_FLAG_NVRAM)
9464                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9465
9466 #undef __GET_REG32
9467 #undef GET_REG32_LOOP
9468 #undef GET_REG32_1
9469
9470         tg3_full_unlock(tp);
9471 }
9472
9473 static int tg3_get_eeprom_len(struct net_device *dev)
9474 {
9475         struct tg3 *tp = netdev_priv(dev);
9476
9477         return tp->nvram_size;
9478 }
9479
9480 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9481 {
9482         struct tg3 *tp = netdev_priv(dev);
9483         int ret;
9484         u8  *pd;
9485         u32 i, offset, len, b_offset, b_count;
9486         __be32 val;
9487
9488         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9489                 return -EINVAL;
9490
9491         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9492                 return -EAGAIN;
9493
9494         offset = eeprom->offset;
9495         len = eeprom->len;
9496         eeprom->len = 0;
9497
9498         eeprom->magic = TG3_EEPROM_MAGIC;
9499
9500         if (offset & 3) {
9501                 /* adjustments to start on required 4 byte boundary */
9502                 b_offset = offset & 3;
9503                 b_count = 4 - b_offset;
9504                 if (b_count > len) {
9505                         /* i.e. offset=1 len=2 */
9506                         b_count = len;
9507                 }
9508                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9509                 if (ret)
9510                         return ret;
9511                 memcpy(data, ((char *)&val) + b_offset, b_count);
9512                 len -= b_count;
9513                 offset += b_count;
9514                 eeprom->len += b_count;
9515         }
9516
9517         /* read bytes upto the last 4 byte boundary */
9518         pd = &data[eeprom->len];
9519         for (i = 0; i < (len - (len & 3)); i += 4) {
9520                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9521                 if (ret) {
9522                         eeprom->len += i;
9523                         return ret;
9524                 }
9525                 memcpy(pd + i, &val, 4);
9526         }
9527         eeprom->len += i;
9528
9529         if (len & 3) {
9530                 /* read last bytes not ending on 4 byte boundary */
9531                 pd = &data[eeprom->len];
9532                 b_count = len & 3;
9533                 b_offset = offset + len - b_count;
9534                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9535                 if (ret)
9536                         return ret;
9537                 memcpy(pd, &val, b_count);
9538                 eeprom->len += b_count;
9539         }
9540         return 0;
9541 }
9542
9543 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9544
9545 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9546 {
9547         struct tg3 *tp = netdev_priv(dev);
9548         int ret;
9549         u32 offset, len, b_offset, odd_len;
9550         u8 *buf;
9551         __be32 start, end;
9552
9553         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9554                 return -EAGAIN;
9555
9556         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9557             eeprom->magic != TG3_EEPROM_MAGIC)
9558                 return -EINVAL;
9559
9560         offset = eeprom->offset;
9561         len = eeprom->len;
9562
9563         if ((b_offset = (offset & 3))) {
9564                 /* adjustments to start on required 4 byte boundary */
9565                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9566                 if (ret)
9567                         return ret;
9568                 len += b_offset;
9569                 offset &= ~3;
9570                 if (len < 4)
9571                         len = 4;
9572         }
9573
9574         odd_len = 0;
9575         if (len & 3) {
9576                 /* adjustments to end on required 4 byte boundary */
9577                 odd_len = 1;
9578                 len = (len + 3) & ~3;
9579                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9580                 if (ret)
9581                         return ret;
9582         }
9583
9584         buf = data;
9585         if (b_offset || odd_len) {
9586                 buf = kmalloc(len, GFP_KERNEL);
9587                 if (!buf)
9588                         return -ENOMEM;
9589                 if (b_offset)
9590                         memcpy(buf, &start, 4);
9591                 if (odd_len)
9592                         memcpy(buf+len-4, &end, 4);
9593                 memcpy(buf + b_offset, data, eeprom->len);
9594         }
9595
9596         ret = tg3_nvram_write_block(tp, offset, len, buf);
9597
9598         if (buf != data)
9599                 kfree(buf);
9600
9601         return ret;
9602 }
9603
9604 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9605 {
9606         struct tg3 *tp = netdev_priv(dev);
9607
9608         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9609                 struct phy_device *phydev;
9610                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9611                         return -EAGAIN;
9612                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9613                 return phy_ethtool_gset(phydev, cmd);
9614         }
9615
9616         cmd->supported = (SUPPORTED_Autoneg);
9617
9618         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9619                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9620                                    SUPPORTED_1000baseT_Full);
9621
9622         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
9623                 cmd->supported |= (SUPPORTED_100baseT_Half |
9624                                   SUPPORTED_100baseT_Full |
9625                                   SUPPORTED_10baseT_Half |
9626                                   SUPPORTED_10baseT_Full |
9627                                   SUPPORTED_TP);
9628                 cmd->port = PORT_TP;
9629         } else {
9630                 cmd->supported |= SUPPORTED_FIBRE;
9631                 cmd->port = PORT_FIBRE;
9632         }
9633
9634         cmd->advertising = tp->link_config.advertising;
9635         if (netif_running(dev)) {
9636                 cmd->speed = tp->link_config.active_speed;
9637                 cmd->duplex = tp->link_config.active_duplex;
9638         }
9639         cmd->phy_address = tp->phy_addr;
9640         cmd->transceiver = XCVR_INTERNAL;
9641         cmd->autoneg = tp->link_config.autoneg;
9642         cmd->maxtxpkt = 0;
9643         cmd->maxrxpkt = 0;
9644         return 0;
9645 }
9646
9647 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9648 {
9649         struct tg3 *tp = netdev_priv(dev);
9650
9651         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9652                 struct phy_device *phydev;
9653                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9654                         return -EAGAIN;
9655                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9656                 return phy_ethtool_sset(phydev, cmd);
9657         }
9658
9659         if (cmd->autoneg != AUTONEG_ENABLE &&
9660             cmd->autoneg != AUTONEG_DISABLE)
9661                 return -EINVAL;
9662
9663         if (cmd->autoneg == AUTONEG_DISABLE &&
9664             cmd->duplex != DUPLEX_FULL &&
9665             cmd->duplex != DUPLEX_HALF)
9666                 return -EINVAL;
9667
9668         if (cmd->autoneg == AUTONEG_ENABLE) {
9669                 u32 mask = ADVERTISED_Autoneg |
9670                            ADVERTISED_Pause |
9671                            ADVERTISED_Asym_Pause;
9672
9673                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9674                         mask |= ADVERTISED_1000baseT_Half |
9675                                 ADVERTISED_1000baseT_Full;
9676
9677                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
9678                         mask |= ADVERTISED_100baseT_Half |
9679                                 ADVERTISED_100baseT_Full |
9680                                 ADVERTISED_10baseT_Half |
9681                                 ADVERTISED_10baseT_Full |
9682                                 ADVERTISED_TP;
9683                 else
9684                         mask |= ADVERTISED_FIBRE;
9685
9686                 if (cmd->advertising & ~mask)
9687                         return -EINVAL;
9688
9689                 mask &= (ADVERTISED_1000baseT_Half |
9690                          ADVERTISED_1000baseT_Full |
9691                          ADVERTISED_100baseT_Half |
9692                          ADVERTISED_100baseT_Full |
9693                          ADVERTISED_10baseT_Half |
9694                          ADVERTISED_10baseT_Full);
9695
9696                 cmd->advertising &= mask;
9697         } else {
9698                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
9699                         if (cmd->speed != SPEED_1000)
9700                                 return -EINVAL;
9701
9702                         if (cmd->duplex != DUPLEX_FULL)
9703                                 return -EINVAL;
9704                 } else {
9705                         if (cmd->speed != SPEED_100 &&
9706                             cmd->speed != SPEED_10)
9707                                 return -EINVAL;
9708                 }
9709         }
9710
9711         tg3_full_lock(tp, 0);
9712
9713         tp->link_config.autoneg = cmd->autoneg;
9714         if (cmd->autoneg == AUTONEG_ENABLE) {
9715                 tp->link_config.advertising = (cmd->advertising |
9716                                               ADVERTISED_Autoneg);
9717                 tp->link_config.speed = SPEED_INVALID;
9718                 tp->link_config.duplex = DUPLEX_INVALID;
9719         } else {
9720                 tp->link_config.advertising = 0;
9721                 tp->link_config.speed = cmd->speed;
9722                 tp->link_config.duplex = cmd->duplex;
9723         }
9724
9725         tp->link_config.orig_speed = tp->link_config.speed;
9726         tp->link_config.orig_duplex = tp->link_config.duplex;
9727         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9728
9729         if (netif_running(dev))
9730                 tg3_setup_phy(tp, 1);
9731
9732         tg3_full_unlock(tp);
9733
9734         return 0;
9735 }
9736
9737 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9738 {
9739         struct tg3 *tp = netdev_priv(dev);
9740
9741         strcpy(info->driver, DRV_MODULE_NAME);
9742         strcpy(info->version, DRV_MODULE_VERSION);
9743         strcpy(info->fw_version, tp->fw_ver);
9744         strcpy(info->bus_info, pci_name(tp->pdev));
9745 }
9746
9747 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9748 {
9749         struct tg3 *tp = netdev_priv(dev);
9750
9751         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9752             device_can_wakeup(&tp->pdev->dev))
9753                 wol->supported = WAKE_MAGIC;
9754         else
9755                 wol->supported = 0;
9756         wol->wolopts = 0;
9757         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9758             device_can_wakeup(&tp->pdev->dev))
9759                 wol->wolopts = WAKE_MAGIC;
9760         memset(&wol->sopass, 0, sizeof(wol->sopass));
9761 }
9762
9763 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9764 {
9765         struct tg3 *tp = netdev_priv(dev);
9766         struct device *dp = &tp->pdev->dev;
9767
9768         if (wol->wolopts & ~WAKE_MAGIC)
9769                 return -EINVAL;
9770         if ((wol->wolopts & WAKE_MAGIC) &&
9771             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9772                 return -EINVAL;
9773
9774         spin_lock_bh(&tp->lock);
9775         if (wol->wolopts & WAKE_MAGIC) {
9776                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9777                 device_set_wakeup_enable(dp, true);
9778         } else {
9779                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9780                 device_set_wakeup_enable(dp, false);
9781         }
9782         spin_unlock_bh(&tp->lock);
9783
9784         return 0;
9785 }
9786
9787 static u32 tg3_get_msglevel(struct net_device *dev)
9788 {
9789         struct tg3 *tp = netdev_priv(dev);
9790         return tp->msg_enable;
9791 }
9792
9793 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9794 {
9795         struct tg3 *tp = netdev_priv(dev);
9796         tp->msg_enable = value;
9797 }
9798
9799 static int tg3_set_tso(struct net_device *dev, u32 value)
9800 {
9801         struct tg3 *tp = netdev_priv(dev);
9802
9803         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9804                 if (value)
9805                         return -EINVAL;
9806                 return 0;
9807         }
9808         if ((dev->features & NETIF_F_IPV6_CSUM) &&
9809             ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9810              (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9811                 if (value) {
9812                         dev->features |= NETIF_F_TSO6;
9813                         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9814                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9815                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9816                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9817                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9818                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9819                                 dev->features |= NETIF_F_TSO_ECN;
9820                 } else
9821                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9822         }
9823         return ethtool_op_set_tso(dev, value);
9824 }
9825
9826 static int tg3_nway_reset(struct net_device *dev)
9827 {
9828         struct tg3 *tp = netdev_priv(dev);
9829         int r;
9830
9831         if (!netif_running(dev))
9832                 return -EAGAIN;
9833
9834         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
9835                 return -EINVAL;
9836
9837         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9838                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9839                         return -EAGAIN;
9840                 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9841         } else {
9842                 u32 bmcr;
9843
9844                 spin_lock_bh(&tp->lock);
9845                 r = -EINVAL;
9846                 tg3_readphy(tp, MII_BMCR, &bmcr);
9847                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9848                     ((bmcr & BMCR_ANENABLE) ||
9849                      (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
9850                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9851                                                    BMCR_ANENABLE);
9852                         r = 0;
9853                 }
9854                 spin_unlock_bh(&tp->lock);
9855         }
9856
9857         return r;
9858 }
9859
9860 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9861 {
9862         struct tg3 *tp = netdev_priv(dev);
9863
9864         ering->rx_max_pending = tp->rx_std_ring_mask;
9865         ering->rx_mini_max_pending = 0;
9866         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9867                 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
9868         else
9869                 ering->rx_jumbo_max_pending = 0;
9870
9871         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9872
9873         ering->rx_pending = tp->rx_pending;
9874         ering->rx_mini_pending = 0;
9875         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9876                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9877         else
9878                 ering->rx_jumbo_pending = 0;
9879
9880         ering->tx_pending = tp->napi[0].tx_pending;
9881 }
9882
9883 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9884 {
9885         struct tg3 *tp = netdev_priv(dev);
9886         int i, irq_sync = 0, err = 0;
9887
9888         if ((ering->rx_pending > tp->rx_std_ring_mask) ||
9889             (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
9890             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9891             (ering->tx_pending <= MAX_SKB_FRAGS) ||
9892             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9893              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9894                 return -EINVAL;
9895
9896         if (netif_running(dev)) {
9897                 tg3_phy_stop(tp);
9898                 tg3_netif_stop(tp);
9899                 irq_sync = 1;
9900         }
9901
9902         tg3_full_lock(tp, irq_sync);
9903
9904         tp->rx_pending = ering->rx_pending;
9905
9906         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9907             tp->rx_pending > 63)
9908                 tp->rx_pending = 63;
9909         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9910
9911         for (i = 0; i < tp->irq_max; i++)
9912                 tp->napi[i].tx_pending = ering->tx_pending;
9913
9914         if (netif_running(dev)) {
9915                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9916                 err = tg3_restart_hw(tp, 1);
9917                 if (!err)
9918                         tg3_netif_start(tp);
9919         }
9920
9921         tg3_full_unlock(tp);
9922
9923         if (irq_sync && !err)
9924                 tg3_phy_start(tp);
9925
9926         return err;
9927 }
9928
9929 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9930 {
9931         struct tg3 *tp = netdev_priv(dev);
9932
9933         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9934
9935         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9936                 epause->rx_pause = 1;
9937         else
9938                 epause->rx_pause = 0;
9939
9940         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9941                 epause->tx_pause = 1;
9942         else
9943                 epause->tx_pause = 0;
9944 }
9945
9946 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9947 {
9948         struct tg3 *tp = netdev_priv(dev);
9949         int err = 0;
9950
9951         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9952                 u32 newadv;
9953                 struct phy_device *phydev;
9954
9955                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9956
9957                 if (!(phydev->supported & SUPPORTED_Pause) ||
9958                     (!(phydev->supported & SUPPORTED_Asym_Pause) &&
9959                      ((epause->rx_pause && !epause->tx_pause) ||
9960                       (!epause->rx_pause && epause->tx_pause))))
9961                         return -EINVAL;
9962
9963                 tp->link_config.flowctrl = 0;
9964                 if (epause->rx_pause) {
9965                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
9966
9967                         if (epause->tx_pause) {
9968                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9969                                 newadv = ADVERTISED_Pause;
9970                         } else
9971                                 newadv = ADVERTISED_Pause |
9972                                          ADVERTISED_Asym_Pause;
9973                 } else if (epause->tx_pause) {
9974                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
9975                         newadv = ADVERTISED_Asym_Pause;
9976                 } else
9977                         newadv = 0;
9978
9979                 if (epause->autoneg)
9980                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9981                 else
9982                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9983
9984                 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
9985                         u32 oldadv = phydev->advertising &
9986                                      (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
9987                         if (oldadv != newadv) {
9988                                 phydev->advertising &=
9989                                         ~(ADVERTISED_Pause |
9990                                           ADVERTISED_Asym_Pause);
9991                                 phydev->advertising |= newadv;
9992                                 if (phydev->autoneg) {
9993                                         /*
9994                                          * Always renegotiate the link to
9995                                          * inform our link partner of our
9996                                          * flow control settings, even if the
9997                                          * flow control is forced.  Let
9998                                          * tg3_adjust_link() do the final
9999                                          * flow control setup.
10000                                          */
10001                                         return phy_start_aneg(phydev);
10002                                 }
10003                         }
10004
10005                         if (!epause->autoneg)
10006                                 tg3_setup_flow_control(tp, 0, 0);
10007                 } else {
10008                         tp->link_config.orig_advertising &=
10009                                         ~(ADVERTISED_Pause |
10010                                           ADVERTISED_Asym_Pause);
10011                         tp->link_config.orig_advertising |= newadv;
10012                 }
10013         } else {
10014                 int irq_sync = 0;
10015
10016                 if (netif_running(dev)) {
10017                         tg3_netif_stop(tp);
10018                         irq_sync = 1;
10019                 }
10020
10021                 tg3_full_lock(tp, irq_sync);
10022
10023                 if (epause->autoneg)
10024                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10025                 else
10026                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10027                 if (epause->rx_pause)
10028                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
10029                 else
10030                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10031                 if (epause->tx_pause)
10032                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
10033                 else
10034                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10035
10036                 if (netif_running(dev)) {
10037                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10038                         err = tg3_restart_hw(tp, 1);
10039                         if (!err)
10040                                 tg3_netif_start(tp);
10041                 }
10042
10043                 tg3_full_unlock(tp);
10044         }
10045
10046         return err;
10047 }
10048
10049 static u32 tg3_get_rx_csum(struct net_device *dev)
10050 {
10051         struct tg3 *tp = netdev_priv(dev);
10052         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10053 }
10054
10055 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10056 {
10057         struct tg3 *tp = netdev_priv(dev);
10058
10059         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10060                 if (data != 0)
10061                         return -EINVAL;
10062                 return 0;
10063         }
10064
10065         spin_lock_bh(&tp->lock);
10066         if (data)
10067                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10068         else
10069                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10070         spin_unlock_bh(&tp->lock);
10071
10072         return 0;
10073 }
10074
10075 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10076 {
10077         struct tg3 *tp = netdev_priv(dev);
10078
10079         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10080                 if (data != 0)
10081                         return -EINVAL;
10082                 return 0;
10083         }
10084
10085         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10086                 ethtool_op_set_tx_ipv6_csum(dev, data);
10087         else
10088                 ethtool_op_set_tx_csum(dev, data);
10089
10090         return 0;
10091 }
10092
10093 static int tg3_get_sset_count(struct net_device *dev, int sset)
10094 {
10095         switch (sset) {
10096         case ETH_SS_TEST:
10097                 return TG3_NUM_TEST;
10098         case ETH_SS_STATS:
10099                 return TG3_NUM_STATS;
10100         default:
10101                 return -EOPNOTSUPP;
10102         }
10103 }
10104
10105 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
10106 {
10107         switch (stringset) {
10108         case ETH_SS_STATS:
10109                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10110                 break;
10111         case ETH_SS_TEST:
10112                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10113                 break;
10114         default:
10115                 WARN_ON(1);     /* we need a WARN() */
10116                 break;
10117         }
10118 }
10119
10120 static int tg3_phys_id(struct net_device *dev, u32 data)
10121 {
10122         struct tg3 *tp = netdev_priv(dev);
10123         int i;
10124
10125         if (!netif_running(tp->dev))
10126                 return -EAGAIN;
10127
10128         if (data == 0)
10129                 data = UINT_MAX / 2;
10130
10131         for (i = 0; i < (data * 2); i++) {
10132                 if ((i % 2) == 0)
10133                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10134                                            LED_CTRL_1000MBPS_ON |
10135                                            LED_CTRL_100MBPS_ON |
10136                                            LED_CTRL_10MBPS_ON |
10137                                            LED_CTRL_TRAFFIC_OVERRIDE |
10138                                            LED_CTRL_TRAFFIC_BLINK |
10139                                            LED_CTRL_TRAFFIC_LED);
10140
10141                 else
10142                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10143                                            LED_CTRL_TRAFFIC_OVERRIDE);
10144
10145                 if (msleep_interruptible(500))
10146                         break;
10147         }
10148         tw32(MAC_LED_CTRL, tp->led_ctrl);
10149         return 0;
10150 }
10151
10152 static void tg3_get_ethtool_stats(struct net_device *dev,
10153                                    struct ethtool_stats *estats, u64 *tmp_stats)
10154 {
10155         struct tg3 *tp = netdev_priv(dev);
10156         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10157 }
10158
10159 #define NVRAM_TEST_SIZE 0x100
10160 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
10161 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
10162 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
10163 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10164 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10165
10166 static int tg3_test_nvram(struct tg3 *tp)
10167 {
10168         u32 csum, magic;
10169         __be32 *buf;
10170         int i, j, k, err = 0, size;
10171
10172         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10173                 return 0;
10174
10175         if (tg3_nvram_read(tp, 0, &magic) != 0)
10176                 return -EIO;
10177
10178         if (magic == TG3_EEPROM_MAGIC)
10179                 size = NVRAM_TEST_SIZE;
10180         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10181                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10182                     TG3_EEPROM_SB_FORMAT_1) {
10183                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10184                         case TG3_EEPROM_SB_REVISION_0:
10185                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10186                                 break;
10187                         case TG3_EEPROM_SB_REVISION_2:
10188                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10189                                 break;
10190                         case TG3_EEPROM_SB_REVISION_3:
10191                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10192                                 break;
10193                         default:
10194                                 return 0;
10195                         }
10196                 } else
10197                         return 0;
10198         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10199                 size = NVRAM_SELFBOOT_HW_SIZE;
10200         else
10201                 return -EIO;
10202
10203         buf = kmalloc(size, GFP_KERNEL);
10204         if (buf == NULL)
10205                 return -ENOMEM;
10206
10207         err = -EIO;
10208         for (i = 0, j = 0; i < size; i += 4, j++) {
10209                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10210                 if (err)
10211                         break;
10212         }
10213         if (i < size)
10214                 goto out;
10215
10216         /* Selfboot format */
10217         magic = be32_to_cpu(buf[0]);
10218         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10219             TG3_EEPROM_MAGIC_FW) {
10220                 u8 *buf8 = (u8 *) buf, csum8 = 0;
10221
10222                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10223                     TG3_EEPROM_SB_REVISION_2) {
10224                         /* For rev 2, the csum doesn't include the MBA. */
10225                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10226                                 csum8 += buf8[i];
10227                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10228                                 csum8 += buf8[i];
10229                 } else {
10230                         for (i = 0; i < size; i++)
10231                                 csum8 += buf8[i];
10232                 }
10233
10234                 if (csum8 == 0) {
10235                         err = 0;
10236                         goto out;
10237                 }
10238
10239                 err = -EIO;
10240                 goto out;
10241         }
10242
10243         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10244             TG3_EEPROM_MAGIC_HW) {
10245                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10246                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10247                 u8 *buf8 = (u8 *) buf;
10248
10249                 /* Separate the parity bits and the data bytes.  */
10250                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10251                         if ((i == 0) || (i == 8)) {
10252                                 int l;
10253                                 u8 msk;
10254
10255                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10256                                         parity[k++] = buf8[i] & msk;
10257                                 i++;
10258                         } else if (i == 16) {
10259                                 int l;
10260                                 u8 msk;
10261
10262                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10263                                         parity[k++] = buf8[i] & msk;
10264                                 i++;
10265
10266                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10267                                         parity[k++] = buf8[i] & msk;
10268                                 i++;
10269                         }
10270                         data[j++] = buf8[i];
10271                 }
10272
10273                 err = -EIO;
10274                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10275                         u8 hw8 = hweight8(data[i]);
10276
10277                         if ((hw8 & 0x1) && parity[i])
10278                                 goto out;
10279                         else if (!(hw8 & 0x1) && !parity[i])
10280                                 goto out;
10281                 }
10282                 err = 0;
10283                 goto out;
10284         }
10285
10286         /* Bootstrap checksum at offset 0x10 */
10287         csum = calc_crc((unsigned char *) buf, 0x10);
10288         if (csum != be32_to_cpu(buf[0x10/4]))
10289                 goto out;
10290
10291         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10292         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10293         if (csum != be32_to_cpu(buf[0xfc/4]))
10294                 goto out;
10295
10296         err = 0;
10297
10298 out:
10299         kfree(buf);
10300         return err;
10301 }
10302
10303 #define TG3_SERDES_TIMEOUT_SEC  2
10304 #define TG3_COPPER_TIMEOUT_SEC  6
10305
10306 static int tg3_test_link(struct tg3 *tp)
10307 {
10308         int i, max;
10309
10310         if (!netif_running(tp->dev))
10311                 return -ENODEV;
10312
10313         if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
10314                 max = TG3_SERDES_TIMEOUT_SEC;
10315         else
10316                 max = TG3_COPPER_TIMEOUT_SEC;
10317
10318         for (i = 0; i < max; i++) {
10319                 if (netif_carrier_ok(tp->dev))
10320                         return 0;
10321
10322                 if (msleep_interruptible(1000))
10323                         break;
10324         }
10325
10326         return -EIO;
10327 }
10328
10329 /* Only test the commonly used registers */
10330 static int tg3_test_registers(struct tg3 *tp)
10331 {
10332         int i, is_5705, is_5750;
10333         u32 offset, read_mask, write_mask, val, save_val, read_val;
10334         static struct {
10335                 u16 offset;
10336                 u16 flags;
10337 #define TG3_FL_5705     0x1
10338 #define TG3_FL_NOT_5705 0x2
10339 #define TG3_FL_NOT_5788 0x4
10340 #define TG3_FL_NOT_5750 0x8
10341                 u32 read_mask;
10342                 u32 write_mask;
10343         } reg_tbl[] = {
10344                 /* MAC Control Registers */
10345                 { MAC_MODE, TG3_FL_NOT_5705,
10346                         0x00000000, 0x00ef6f8c },
10347                 { MAC_MODE, TG3_FL_5705,
10348                         0x00000000, 0x01ef6b8c },
10349                 { MAC_STATUS, TG3_FL_NOT_5705,
10350                         0x03800107, 0x00000000 },
10351                 { MAC_STATUS, TG3_FL_5705,
10352                         0x03800100, 0x00000000 },
10353                 { MAC_ADDR_0_HIGH, 0x0000,
10354                         0x00000000, 0x0000ffff },
10355                 { MAC_ADDR_0_LOW, 0x0000,
10356                         0x00000000, 0xffffffff },
10357                 { MAC_RX_MTU_SIZE, 0x0000,
10358                         0x00000000, 0x0000ffff },
10359                 { MAC_TX_MODE, 0x0000,
10360                         0x00000000, 0x00000070 },
10361                 { MAC_TX_LENGTHS, 0x0000,
10362                         0x00000000, 0x00003fff },
10363                 { MAC_RX_MODE, TG3_FL_NOT_5705,
10364                         0x00000000, 0x000007fc },
10365                 { MAC_RX_MODE, TG3_FL_5705,
10366                         0x00000000, 0x000007dc },
10367                 { MAC_HASH_REG_0, 0x0000,
10368                         0x00000000, 0xffffffff },
10369                 { MAC_HASH_REG_1, 0x0000,
10370                         0x00000000, 0xffffffff },
10371                 { MAC_HASH_REG_2, 0x0000,
10372                         0x00000000, 0xffffffff },
10373                 { MAC_HASH_REG_3, 0x0000,
10374                         0x00000000, 0xffffffff },
10375
10376                 /* Receive Data and Receive BD Initiator Control Registers. */
10377                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10378                         0x00000000, 0xffffffff },
10379                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10380                         0x00000000, 0xffffffff },
10381                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10382                         0x00000000, 0x00000003 },
10383                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10384                         0x00000000, 0xffffffff },
10385                 { RCVDBDI_STD_BD+0, 0x0000,
10386                         0x00000000, 0xffffffff },
10387                 { RCVDBDI_STD_BD+4, 0x0000,
10388                         0x00000000, 0xffffffff },
10389                 { RCVDBDI_STD_BD+8, 0x0000,
10390                         0x00000000, 0xffff0002 },
10391                 { RCVDBDI_STD_BD+0xc, 0x0000,
10392                         0x00000000, 0xffffffff },
10393
10394                 /* Receive BD Initiator Control Registers. */
10395                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10396                         0x00000000, 0xffffffff },
10397                 { RCVBDI_STD_THRESH, TG3_FL_5705,
10398                         0x00000000, 0x000003ff },
10399                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10400                         0x00000000, 0xffffffff },
10401
10402                 /* Host Coalescing Control Registers. */
10403                 { HOSTCC_MODE, TG3_FL_NOT_5705,
10404                         0x00000000, 0x00000004 },
10405                 { HOSTCC_MODE, TG3_FL_5705,
10406                         0x00000000, 0x000000f6 },
10407                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10408                         0x00000000, 0xffffffff },
10409                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10410                         0x00000000, 0x000003ff },
10411                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10412                         0x00000000, 0xffffffff },
10413                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10414                         0x00000000, 0x000003ff },
10415                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10416                         0x00000000, 0xffffffff },
10417                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10418                         0x00000000, 0x000000ff },
10419                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10420                         0x00000000, 0xffffffff },
10421                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10422                         0x00000000, 0x000000ff },
10423                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10424                         0x00000000, 0xffffffff },
10425                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10426                         0x00000000, 0xffffffff },
10427                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10428                         0x00000000, 0xffffffff },
10429                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10430                         0x00000000, 0x000000ff },
10431                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10432                         0x00000000, 0xffffffff },
10433                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10434                         0x00000000, 0x000000ff },
10435                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10436                         0x00000000, 0xffffffff },
10437                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10438                         0x00000000, 0xffffffff },
10439                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10440                         0x00000000, 0xffffffff },
10441                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10442                         0x00000000, 0xffffffff },
10443                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10444                         0x00000000, 0xffffffff },
10445                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10446                         0xffffffff, 0x00000000 },
10447                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10448                         0xffffffff, 0x00000000 },
10449
10450                 /* Buffer Manager Control Registers. */
10451                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10452                         0x00000000, 0x007fff80 },
10453                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10454                         0x00000000, 0x007fffff },
10455                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10456                         0x00000000, 0x0000003f },
10457                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10458                         0x00000000, 0x000001ff },
10459                 { BUFMGR_MB_HIGH_WATER, 0x0000,
10460                         0x00000000, 0x000001ff },
10461                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10462                         0xffffffff, 0x00000000 },
10463                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10464                         0xffffffff, 0x00000000 },
10465
10466                 /* Mailbox Registers */
10467                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10468                         0x00000000, 0x000001ff },
10469                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10470                         0x00000000, 0x000001ff },
10471                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10472                         0x00000000, 0x000007ff },
10473                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10474                         0x00000000, 0x000001ff },
10475
10476                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10477         };
10478
10479         is_5705 = is_5750 = 0;
10480         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10481                 is_5705 = 1;
10482                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10483                         is_5750 = 1;
10484         }
10485
10486         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10487                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10488                         continue;
10489
10490                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10491                         continue;
10492
10493                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10494                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
10495                         continue;
10496
10497                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10498                         continue;
10499
10500                 offset = (u32) reg_tbl[i].offset;
10501                 read_mask = reg_tbl[i].read_mask;
10502                 write_mask = reg_tbl[i].write_mask;
10503
10504                 /* Save the original register content */
10505                 save_val = tr32(offset);
10506
10507                 /* Determine the read-only value. */
10508                 read_val = save_val & read_mask;
10509
10510                 /* Write zero to the register, then make sure the read-only bits
10511                  * are not changed and the read/write bits are all zeros.
10512                  */
10513                 tw32(offset, 0);
10514
10515                 val = tr32(offset);
10516
10517                 /* Test the read-only and read/write bits. */
10518                 if (((val & read_mask) != read_val) || (val & write_mask))
10519                         goto out;
10520
10521                 /* Write ones to all the bits defined by RdMask and WrMask, then
10522                  * make sure the read-only bits are not changed and the
10523                  * read/write bits are all ones.
10524                  */
10525                 tw32(offset, read_mask | write_mask);
10526
10527                 val = tr32(offset);
10528
10529                 /* Test the read-only bits. */
10530                 if ((val & read_mask) != read_val)
10531                         goto out;
10532
10533                 /* Test the read/write bits. */
10534                 if ((val & write_mask) != write_mask)
10535                         goto out;
10536
10537                 tw32(offset, save_val);
10538         }
10539
10540         return 0;
10541
10542 out:
10543         if (netif_msg_hw(tp))
10544                 netdev_err(tp->dev,
10545                            "Register test failed at offset %x\n", offset);
10546         tw32(offset, save_val);
10547         return -EIO;
10548 }
10549
10550 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10551 {
10552         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10553         int i;
10554         u32 j;
10555
10556         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10557                 for (j = 0; j < len; j += 4) {
10558                         u32 val;
10559
10560                         tg3_write_mem(tp, offset + j, test_pattern[i]);
10561                         tg3_read_mem(tp, offset + j, &val);
10562                         if (val != test_pattern[i])
10563                                 return -EIO;
10564                 }
10565         }
10566         return 0;
10567 }
10568
10569 static int tg3_test_memory(struct tg3 *tp)
10570 {
10571         static struct mem_entry {
10572                 u32 offset;
10573                 u32 len;
10574         } mem_tbl_570x[] = {
10575                 { 0x00000000, 0x00b50},
10576                 { 0x00002000, 0x1c000},
10577                 { 0xffffffff, 0x00000}
10578         }, mem_tbl_5705[] = {
10579                 { 0x00000100, 0x0000c},
10580                 { 0x00000200, 0x00008},
10581                 { 0x00004000, 0x00800},
10582                 { 0x00006000, 0x01000},
10583                 { 0x00008000, 0x02000},
10584                 { 0x00010000, 0x0e000},
10585                 { 0xffffffff, 0x00000}
10586         }, mem_tbl_5755[] = {
10587                 { 0x00000200, 0x00008},
10588                 { 0x00004000, 0x00800},
10589                 { 0x00006000, 0x00800},
10590                 { 0x00008000, 0x02000},
10591                 { 0x00010000, 0x0c000},
10592                 { 0xffffffff, 0x00000}
10593         }, mem_tbl_5906[] = {
10594                 { 0x00000200, 0x00008},
10595                 { 0x00004000, 0x00400},
10596                 { 0x00006000, 0x00400},
10597                 { 0x00008000, 0x01000},
10598                 { 0x00010000, 0x01000},
10599                 { 0xffffffff, 0x00000}
10600         }, mem_tbl_5717[] = {
10601                 { 0x00000200, 0x00008},
10602                 { 0x00010000, 0x0a000},
10603                 { 0x00020000, 0x13c00},
10604                 { 0xffffffff, 0x00000}
10605         }, mem_tbl_57765[] = {
10606                 { 0x00000200, 0x00008},
10607                 { 0x00004000, 0x00800},
10608                 { 0x00006000, 0x09800},
10609                 { 0x00010000, 0x0a000},
10610                 { 0xffffffff, 0x00000}
10611         };
10612         struct mem_entry *mem_tbl;
10613         int err = 0;
10614         int i;
10615
10616         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
10617             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
10618                 mem_tbl = mem_tbl_5717;
10619         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10620                 mem_tbl = mem_tbl_57765;
10621         else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10622                 mem_tbl = mem_tbl_5755;
10623         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10624                 mem_tbl = mem_tbl_5906;
10625         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10626                 mem_tbl = mem_tbl_5705;
10627         else
10628                 mem_tbl = mem_tbl_570x;
10629
10630         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10631                 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
10632                 if (err)
10633                         break;
10634         }
10635
10636         return err;
10637 }
10638
10639 #define TG3_MAC_LOOPBACK        0
10640 #define TG3_PHY_LOOPBACK        1
10641
10642 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10643 {
10644         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10645         u32 desc_idx, coal_now;
10646         struct sk_buff *skb, *rx_skb;
10647         u8 *tx_data;
10648         dma_addr_t map;
10649         int num_pkts, tx_len, rx_len, i, err;
10650         struct tg3_rx_buffer_desc *desc;
10651         struct tg3_napi *tnapi, *rnapi;
10652         struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
10653
10654         tnapi = &tp->napi[0];
10655         rnapi = &tp->napi[0];
10656         if (tp->irq_cnt > 1) {
10657                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
10658                         rnapi = &tp->napi[1];
10659                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
10660                         tnapi = &tp->napi[1];
10661         }
10662         coal_now = tnapi->coal_now | rnapi->coal_now;
10663
10664         if (loopback_mode == TG3_MAC_LOOPBACK) {
10665                 /* HW errata - mac loopback fails in some cases on 5780.
10666                  * Normal traffic and PHY loopback are not affected by
10667                  * errata.
10668                  */
10669                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10670                         return 0;
10671
10672                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10673                            MAC_MODE_PORT_INT_LPBACK;
10674                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10675                         mac_mode |= MAC_MODE_LINK_POLARITY;
10676                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
10677                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10678                 else
10679                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10680                 tw32(MAC_MODE, mac_mode);
10681         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10682                 u32 val;
10683
10684                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10685                         tg3_phy_fet_toggle_apd(tp, false);
10686                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10687                 } else
10688                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10689
10690                 tg3_phy_toggle_automdix(tp, 0);
10691
10692                 tg3_writephy(tp, MII_BMCR, val);
10693                 udelay(40);
10694
10695                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10696                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10697                         tg3_writephy(tp, MII_TG3_FET_PTEST,
10698                                      MII_TG3_FET_PTEST_FRC_TX_LINK |
10699                                      MII_TG3_FET_PTEST_FRC_TX_LOCK);
10700                         /* The write needs to be flushed for the AC131 */
10701                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10702                                 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
10703                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10704                 } else
10705                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10706
10707                 /* reset to prevent losing 1st rx packet intermittently */
10708                 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10709                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10710                         udelay(10);
10711                         tw32_f(MAC_RX_MODE, tp->rx_mode);
10712                 }
10713                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10714                         u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
10715                         if (masked_phy_id == TG3_PHY_ID_BCM5401)
10716                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10717                         else if (masked_phy_id == TG3_PHY_ID_BCM5411)
10718                                 mac_mode |= MAC_MODE_LINK_POLARITY;
10719                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
10720                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10721                 }
10722                 tw32(MAC_MODE, mac_mode);
10723         } else {
10724                 return -EINVAL;
10725         }
10726
10727         err = -EIO;
10728
10729         tx_len = 1514;
10730         skb = netdev_alloc_skb(tp->dev, tx_len);
10731         if (!skb)
10732                 return -ENOMEM;
10733
10734         tx_data = skb_put(skb, tx_len);
10735         memcpy(tx_data, tp->dev->dev_addr, 6);
10736         memset(tx_data + 6, 0x0, 8);
10737
10738         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10739
10740         for (i = 14; i < tx_len; i++)
10741                 tx_data[i] = (u8) (i & 0xff);
10742
10743         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10744         if (pci_dma_mapping_error(tp->pdev, map)) {
10745                 dev_kfree_skb(skb);
10746                 return -EIO;
10747         }
10748
10749         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10750                rnapi->coal_now);
10751
10752         udelay(10);
10753
10754         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10755
10756         num_pkts = 0;
10757
10758         tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10759
10760         tnapi->tx_prod++;
10761         num_pkts++;
10762
10763         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10764         tr32_mailbox(tnapi->prodmbox);
10765
10766         udelay(10);
10767
10768         /* 350 usec to allow enough time on some 10/100 Mbps devices.  */
10769         for (i = 0; i < 35; i++) {
10770                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10771                        coal_now);
10772
10773                 udelay(10);
10774
10775                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10776                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10777                 if ((tx_idx == tnapi->tx_prod) &&
10778                     (rx_idx == (rx_start_idx + num_pkts)))
10779                         break;
10780         }
10781
10782         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10783         dev_kfree_skb(skb);
10784
10785         if (tx_idx != tnapi->tx_prod)
10786                 goto out;
10787
10788         if (rx_idx != rx_start_idx + num_pkts)
10789                 goto out;
10790
10791         desc = &rnapi->rx_rcb[rx_start_idx];
10792         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10793         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10794         if (opaque_key != RXD_OPAQUE_RING_STD)
10795                 goto out;
10796
10797         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10798             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10799                 goto out;
10800
10801         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10802         if (rx_len != tx_len)
10803                 goto out;
10804
10805         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10806
10807         map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10808         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10809
10810         for (i = 14; i < tx_len; i++) {
10811                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10812                         goto out;
10813         }
10814         err = 0;
10815
10816         /* tg3_free_rings will unmap and free the rx_skb */
10817 out:
10818         return err;
10819 }
10820
10821 #define TG3_MAC_LOOPBACK_FAILED         1
10822 #define TG3_PHY_LOOPBACK_FAILED         2
10823 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
10824                                          TG3_PHY_LOOPBACK_FAILED)
10825
10826 static int tg3_test_loopback(struct tg3 *tp)
10827 {
10828         int err = 0;
10829         u32 cpmuctrl = 0;
10830
10831         if (!netif_running(tp->dev))
10832                 return TG3_LOOPBACK_FAILED;
10833
10834         err = tg3_reset_hw(tp, 1);
10835         if (err)
10836                 return TG3_LOOPBACK_FAILED;
10837
10838         /* Turn off gphy autopowerdown. */
10839         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
10840                 tg3_phy_toggle_apd(tp, false);
10841
10842         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10843                 int i;
10844                 u32 status;
10845
10846                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10847
10848                 /* Wait for up to 40 microseconds to acquire lock. */
10849                 for (i = 0; i < 4; i++) {
10850                         status = tr32(TG3_CPMU_MUTEX_GNT);
10851                         if (status == CPMU_MUTEX_GNT_DRIVER)
10852                                 break;
10853                         udelay(10);
10854                 }
10855
10856                 if (status != CPMU_MUTEX_GNT_DRIVER)
10857                         return TG3_LOOPBACK_FAILED;
10858
10859                 /* Turn off link-based power management. */
10860                 cpmuctrl = tr32(TG3_CPMU_CTRL);
10861                 tw32(TG3_CPMU_CTRL,
10862                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10863                                   CPMU_CTRL_LINK_AWARE_MODE));
10864         }
10865
10866         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10867                 err |= TG3_MAC_LOOPBACK_FAILED;
10868
10869         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10870                 tw32(TG3_CPMU_CTRL, cpmuctrl);
10871
10872                 /* Release the mutex */
10873                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10874         }
10875
10876         if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10877             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10878                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10879                         err |= TG3_PHY_LOOPBACK_FAILED;
10880         }
10881
10882         /* Re-enable gphy autopowerdown. */
10883         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
10884                 tg3_phy_toggle_apd(tp, true);
10885
10886         return err;
10887 }
10888
10889 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10890                           u64 *data)
10891 {
10892         struct tg3 *tp = netdev_priv(dev);
10893
10894         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10895                 tg3_set_power_state(tp, PCI_D0);
10896
10897         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10898
10899         if (tg3_test_nvram(tp) != 0) {
10900                 etest->flags |= ETH_TEST_FL_FAILED;
10901                 data[0] = 1;
10902         }
10903         if (tg3_test_link(tp) != 0) {
10904                 etest->flags |= ETH_TEST_FL_FAILED;
10905                 data[1] = 1;
10906         }
10907         if (etest->flags & ETH_TEST_FL_OFFLINE) {
10908                 int err, err2 = 0, irq_sync = 0;
10909
10910                 if (netif_running(dev)) {
10911                         tg3_phy_stop(tp);
10912                         tg3_netif_stop(tp);
10913                         irq_sync = 1;
10914                 }
10915
10916                 tg3_full_lock(tp, irq_sync);
10917
10918                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10919                 err = tg3_nvram_lock(tp);
10920                 tg3_halt_cpu(tp, RX_CPU_BASE);
10921                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10922                         tg3_halt_cpu(tp, TX_CPU_BASE);
10923                 if (!err)
10924                         tg3_nvram_unlock(tp);
10925
10926                 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
10927                         tg3_phy_reset(tp);
10928
10929                 if (tg3_test_registers(tp) != 0) {
10930                         etest->flags |= ETH_TEST_FL_FAILED;
10931                         data[2] = 1;
10932                 }
10933                 if (tg3_test_memory(tp) != 0) {
10934                         etest->flags |= ETH_TEST_FL_FAILED;
10935                         data[3] = 1;
10936                 }
10937                 if ((data[4] = tg3_test_loopback(tp)) != 0)
10938                         etest->flags |= ETH_TEST_FL_FAILED;
10939
10940                 tg3_full_unlock(tp);
10941
10942                 if (tg3_test_interrupt(tp) != 0) {
10943                         etest->flags |= ETH_TEST_FL_FAILED;
10944                         data[5] = 1;
10945                 }
10946
10947                 tg3_full_lock(tp, 0);
10948
10949                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10950                 if (netif_running(dev)) {
10951                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10952                         err2 = tg3_restart_hw(tp, 1);
10953                         if (!err2)
10954                                 tg3_netif_start(tp);
10955                 }
10956
10957                 tg3_full_unlock(tp);
10958
10959                 if (irq_sync && !err2)
10960                         tg3_phy_start(tp);
10961         }
10962         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10963                 tg3_set_power_state(tp, PCI_D3hot);
10964
10965 }
10966
10967 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10968 {
10969         struct mii_ioctl_data *data = if_mii(ifr);
10970         struct tg3 *tp = netdev_priv(dev);
10971         int err;
10972
10973         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10974                 struct phy_device *phydev;
10975                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10976                         return -EAGAIN;
10977                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10978                 return phy_mii_ioctl(phydev, ifr, cmd);
10979         }
10980
10981         switch (cmd) {
10982         case SIOCGMIIPHY:
10983                 data->phy_id = tp->phy_addr;
10984
10985                 /* fallthru */
10986         case SIOCGMIIREG: {
10987                 u32 mii_regval;
10988
10989                 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
10990                         break;                  /* We have no PHY */
10991
10992                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10993                         return -EAGAIN;
10994
10995                 spin_lock_bh(&tp->lock);
10996                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10997                 spin_unlock_bh(&tp->lock);
10998
10999                 data->val_out = mii_regval;
11000
11001                 return err;
11002         }
11003
11004         case SIOCSMIIREG:
11005                 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11006                         break;                  /* We have no PHY */
11007
11008                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11009                         return -EAGAIN;
11010
11011                 spin_lock_bh(&tp->lock);
11012                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
11013                 spin_unlock_bh(&tp->lock);
11014
11015                 return err;
11016
11017         default:
11018                 /* do nothing */
11019                 break;
11020         }
11021         return -EOPNOTSUPP;
11022 }
11023
11024 #if TG3_VLAN_TAG_USED
11025 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
11026 {
11027         struct tg3 *tp = netdev_priv(dev);
11028
11029         if (!netif_running(dev)) {
11030                 tp->vlgrp = grp;
11031                 return;
11032         }
11033
11034         tg3_netif_stop(tp);
11035
11036         tg3_full_lock(tp, 0);
11037
11038         tp->vlgrp = grp;
11039
11040         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11041         __tg3_set_rx_mode(dev);
11042
11043         tg3_netif_start(tp);
11044
11045         tg3_full_unlock(tp);
11046 }
11047 #endif
11048
11049 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11050 {
11051         struct tg3 *tp = netdev_priv(dev);
11052
11053         memcpy(ec, &tp->coal, sizeof(*ec));
11054         return 0;
11055 }
11056
11057 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11058 {
11059         struct tg3 *tp = netdev_priv(dev);
11060         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11061         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11062
11063         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11064                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11065                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11066                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11067                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11068         }
11069
11070         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11071             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11072             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11073             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11074             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11075             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11076             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11077             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11078             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11079             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11080                 return -EINVAL;
11081
11082         /* No rx interrupts will be generated if both are zero */
11083         if ((ec->rx_coalesce_usecs == 0) &&
11084             (ec->rx_max_coalesced_frames == 0))
11085                 return -EINVAL;
11086
11087         /* No tx interrupts will be generated if both are zero */
11088         if ((ec->tx_coalesce_usecs == 0) &&
11089             (ec->tx_max_coalesced_frames == 0))
11090                 return -EINVAL;
11091
11092         /* Only copy relevant parameters, ignore all others. */
11093         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11094         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11095         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11096         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11097         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11098         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11099         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11100         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11101         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11102
11103         if (netif_running(dev)) {
11104                 tg3_full_lock(tp, 0);
11105                 __tg3_set_coalesce(tp, &tp->coal);
11106                 tg3_full_unlock(tp);
11107         }
11108         return 0;
11109 }
11110
11111 static const struct ethtool_ops tg3_ethtool_ops = {
11112         .get_settings           = tg3_get_settings,
11113         .set_settings           = tg3_set_settings,
11114         .get_drvinfo            = tg3_get_drvinfo,
11115         .get_regs_len           = tg3_get_regs_len,
11116         .get_regs               = tg3_get_regs,
11117         .get_wol                = tg3_get_wol,
11118         .set_wol                = tg3_set_wol,
11119         .get_msglevel           = tg3_get_msglevel,
11120         .set_msglevel           = tg3_set_msglevel,
11121         .nway_reset             = tg3_nway_reset,
11122         .get_link               = ethtool_op_get_link,
11123         .get_eeprom_len         = tg3_get_eeprom_len,
11124         .get_eeprom             = tg3_get_eeprom,
11125         .set_eeprom             = tg3_set_eeprom,
11126         .get_ringparam          = tg3_get_ringparam,
11127         .set_ringparam          = tg3_set_ringparam,
11128         .get_pauseparam         = tg3_get_pauseparam,
11129         .set_pauseparam         = tg3_set_pauseparam,
11130         .get_rx_csum            = tg3_get_rx_csum,
11131         .set_rx_csum            = tg3_set_rx_csum,
11132         .set_tx_csum            = tg3_set_tx_csum,
11133         .set_sg                 = ethtool_op_set_sg,
11134         .set_tso                = tg3_set_tso,
11135         .self_test              = tg3_self_test,
11136         .get_strings            = tg3_get_strings,
11137         .phys_id                = tg3_phys_id,
11138         .get_ethtool_stats      = tg3_get_ethtool_stats,
11139         .get_coalesce           = tg3_get_coalesce,
11140         .set_coalesce           = tg3_set_coalesce,
11141         .get_sset_count         = tg3_get_sset_count,
11142 };
11143
11144 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11145 {
11146         u32 cursize, val, magic;
11147
11148         tp->nvram_size = EEPROM_CHIP_SIZE;
11149
11150         if (tg3_nvram_read(tp, 0, &magic) != 0)
11151                 return;
11152
11153         if ((magic != TG3_EEPROM_MAGIC) &&
11154             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11155             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11156                 return;
11157
11158         /*
11159          * Size the chip by reading offsets at increasing powers of two.
11160          * When we encounter our validation signature, we know the addressing
11161          * has wrapped around, and thus have our chip size.
11162          */
11163         cursize = 0x10;
11164
11165         while (cursize < tp->nvram_size) {
11166                 if (tg3_nvram_read(tp, cursize, &val) != 0)
11167                         return;
11168
11169                 if (val == magic)
11170                         break;
11171
11172                 cursize <<= 1;
11173         }
11174
11175         tp->nvram_size = cursize;
11176 }
11177
11178 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11179 {
11180         u32 val;
11181
11182         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11183             tg3_nvram_read(tp, 0, &val) != 0)
11184                 return;
11185
11186         /* Selfboot format */
11187         if (val != TG3_EEPROM_MAGIC) {
11188                 tg3_get_eeprom_size(tp);
11189                 return;
11190         }
11191
11192         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11193                 if (val != 0) {
11194                         /* This is confusing.  We want to operate on the
11195                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
11196                          * call will read from NVRAM and byteswap the data
11197                          * according to the byteswapping settings for all
11198                          * other register accesses.  This ensures the data we
11199                          * want will always reside in the lower 16-bits.
11200                          * However, the data in NVRAM is in LE format, which
11201                          * means the data from the NVRAM read will always be
11202                          * opposite the endianness of the CPU.  The 16-bit
11203                          * byteswap then brings the data to CPU endianness.
11204                          */
11205                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11206                         return;
11207                 }
11208         }
11209         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11210 }
11211
11212 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11213 {
11214         u32 nvcfg1;
11215
11216         nvcfg1 = tr32(NVRAM_CFG1);
11217         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11218                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11219         } else {
11220                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11221                 tw32(NVRAM_CFG1, nvcfg1);
11222         }
11223
11224         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11225             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11226                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11227                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11228                         tp->nvram_jedecnum = JEDEC_ATMEL;
11229                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11230                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11231                         break;
11232                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11233                         tp->nvram_jedecnum = JEDEC_ATMEL;
11234                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11235                         break;
11236                 case FLASH_VENDOR_ATMEL_EEPROM:
11237                         tp->nvram_jedecnum = JEDEC_ATMEL;
11238                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11239                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11240                         break;
11241                 case FLASH_VENDOR_ST:
11242                         tp->nvram_jedecnum = JEDEC_ST;
11243                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11244                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11245                         break;
11246                 case FLASH_VENDOR_SAIFUN:
11247                         tp->nvram_jedecnum = JEDEC_SAIFUN;
11248                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11249                         break;
11250                 case FLASH_VENDOR_SST_SMALL:
11251                 case FLASH_VENDOR_SST_LARGE:
11252                         tp->nvram_jedecnum = JEDEC_SST;
11253                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11254                         break;
11255                 }
11256         } else {
11257                 tp->nvram_jedecnum = JEDEC_ATMEL;
11258                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11259                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11260         }
11261 }
11262
11263 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11264 {
11265         switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11266         case FLASH_5752PAGE_SIZE_256:
11267                 tp->nvram_pagesize = 256;
11268                 break;
11269         case FLASH_5752PAGE_SIZE_512:
11270                 tp->nvram_pagesize = 512;
11271                 break;
11272         case FLASH_5752PAGE_SIZE_1K:
11273                 tp->nvram_pagesize = 1024;
11274                 break;
11275         case FLASH_5752PAGE_SIZE_2K:
11276                 tp->nvram_pagesize = 2048;
11277                 break;
11278         case FLASH_5752PAGE_SIZE_4K:
11279                 tp->nvram_pagesize = 4096;
11280                 break;
11281         case FLASH_5752PAGE_SIZE_264:
11282                 tp->nvram_pagesize = 264;
11283                 break;
11284         case FLASH_5752PAGE_SIZE_528:
11285                 tp->nvram_pagesize = 528;
11286                 break;
11287         }
11288 }
11289
11290 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11291 {
11292         u32 nvcfg1;
11293
11294         nvcfg1 = tr32(NVRAM_CFG1);
11295
11296         /* NVRAM protection for TPM */
11297         if (nvcfg1 & (1 << 27))
11298                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11299
11300         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11301         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11302         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11303                 tp->nvram_jedecnum = JEDEC_ATMEL;
11304                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11305                 break;
11306         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11307                 tp->nvram_jedecnum = JEDEC_ATMEL;
11308                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11309                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11310                 break;
11311         case FLASH_5752VENDOR_ST_M45PE10:
11312         case FLASH_5752VENDOR_ST_M45PE20:
11313         case FLASH_5752VENDOR_ST_M45PE40:
11314                 tp->nvram_jedecnum = JEDEC_ST;
11315                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11316                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11317                 break;
11318         }
11319
11320         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11321                 tg3_nvram_get_pagesize(tp, nvcfg1);
11322         } else {
11323                 /* For eeprom, set pagesize to maximum eeprom size */
11324                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11325
11326                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11327                 tw32(NVRAM_CFG1, nvcfg1);
11328         }
11329 }
11330
11331 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11332 {
11333         u32 nvcfg1, protect = 0;
11334
11335         nvcfg1 = tr32(NVRAM_CFG1);
11336
11337         /* NVRAM protection for TPM */
11338         if (nvcfg1 & (1 << 27)) {
11339                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11340                 protect = 1;
11341         }
11342
11343         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11344         switch (nvcfg1) {
11345         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11346         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11347         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11348         case FLASH_5755VENDOR_ATMEL_FLASH_5:
11349                 tp->nvram_jedecnum = JEDEC_ATMEL;
11350                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11351                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11352                 tp->nvram_pagesize = 264;
11353                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11354                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11355                         tp->nvram_size = (protect ? 0x3e200 :
11356                                           TG3_NVRAM_SIZE_512KB);
11357                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11358                         tp->nvram_size = (protect ? 0x1f200 :
11359                                           TG3_NVRAM_SIZE_256KB);
11360                 else
11361                         tp->nvram_size = (protect ? 0x1f200 :
11362                                           TG3_NVRAM_SIZE_128KB);
11363                 break;
11364         case FLASH_5752VENDOR_ST_M45PE10:
11365         case FLASH_5752VENDOR_ST_M45PE20:
11366         case FLASH_5752VENDOR_ST_M45PE40:
11367                 tp->nvram_jedecnum = JEDEC_ST;
11368                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11369                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11370                 tp->nvram_pagesize = 256;
11371                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11372                         tp->nvram_size = (protect ?
11373                                           TG3_NVRAM_SIZE_64KB :
11374                                           TG3_NVRAM_SIZE_128KB);
11375                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11376                         tp->nvram_size = (protect ?
11377                                           TG3_NVRAM_SIZE_64KB :
11378                                           TG3_NVRAM_SIZE_256KB);
11379                 else
11380                         tp->nvram_size = (protect ?
11381                                           TG3_NVRAM_SIZE_128KB :
11382                                           TG3_NVRAM_SIZE_512KB);
11383                 break;
11384         }
11385 }
11386
11387 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11388 {
11389         u32 nvcfg1;
11390
11391         nvcfg1 = tr32(NVRAM_CFG1);
11392
11393         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11394         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11395         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11396         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11397         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11398                 tp->nvram_jedecnum = JEDEC_ATMEL;
11399                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11400                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11401
11402                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11403                 tw32(NVRAM_CFG1, nvcfg1);
11404                 break;
11405         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11406         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11407         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11408         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11409                 tp->nvram_jedecnum = JEDEC_ATMEL;
11410                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11411                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11412                 tp->nvram_pagesize = 264;
11413                 break;
11414         case FLASH_5752VENDOR_ST_M45PE10:
11415         case FLASH_5752VENDOR_ST_M45PE20:
11416         case FLASH_5752VENDOR_ST_M45PE40:
11417                 tp->nvram_jedecnum = JEDEC_ST;
11418                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11419                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11420                 tp->nvram_pagesize = 256;
11421                 break;
11422         }
11423 }
11424
11425 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11426 {
11427         u32 nvcfg1, protect = 0;
11428
11429         nvcfg1 = tr32(NVRAM_CFG1);
11430
11431         /* NVRAM protection for TPM */
11432         if (nvcfg1 & (1 << 27)) {
11433                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11434                 protect = 1;
11435         }
11436
11437         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11438         switch (nvcfg1) {
11439         case FLASH_5761VENDOR_ATMEL_ADB021D:
11440         case FLASH_5761VENDOR_ATMEL_ADB041D:
11441         case FLASH_5761VENDOR_ATMEL_ADB081D:
11442         case FLASH_5761VENDOR_ATMEL_ADB161D:
11443         case FLASH_5761VENDOR_ATMEL_MDB021D:
11444         case FLASH_5761VENDOR_ATMEL_MDB041D:
11445         case FLASH_5761VENDOR_ATMEL_MDB081D:
11446         case FLASH_5761VENDOR_ATMEL_MDB161D:
11447                 tp->nvram_jedecnum = JEDEC_ATMEL;
11448                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11449                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11450                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11451                 tp->nvram_pagesize = 256;
11452                 break;
11453         case FLASH_5761VENDOR_ST_A_M45PE20:
11454         case FLASH_5761VENDOR_ST_A_M45PE40:
11455         case FLASH_5761VENDOR_ST_A_M45PE80:
11456         case FLASH_5761VENDOR_ST_A_M45PE16:
11457         case FLASH_5761VENDOR_ST_M_M45PE20:
11458         case FLASH_5761VENDOR_ST_M_M45PE40:
11459         case FLASH_5761VENDOR_ST_M_M45PE80:
11460         case FLASH_5761VENDOR_ST_M_M45PE16:
11461                 tp->nvram_jedecnum = JEDEC_ST;
11462                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11463                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11464                 tp->nvram_pagesize = 256;
11465                 break;
11466         }
11467
11468         if (protect) {
11469                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11470         } else {
11471                 switch (nvcfg1) {
11472                 case FLASH_5761VENDOR_ATMEL_ADB161D:
11473                 case FLASH_5761VENDOR_ATMEL_MDB161D:
11474                 case FLASH_5761VENDOR_ST_A_M45PE16:
11475                 case FLASH_5761VENDOR_ST_M_M45PE16:
11476                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11477                         break;
11478                 case FLASH_5761VENDOR_ATMEL_ADB081D:
11479                 case FLASH_5761VENDOR_ATMEL_MDB081D:
11480                 case FLASH_5761VENDOR_ST_A_M45PE80:
11481                 case FLASH_5761VENDOR_ST_M_M45PE80:
11482                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11483                         break;
11484                 case FLASH_5761VENDOR_ATMEL_ADB041D:
11485                 case FLASH_5761VENDOR_ATMEL_MDB041D:
11486                 case FLASH_5761VENDOR_ST_A_M45PE40:
11487                 case FLASH_5761VENDOR_ST_M_M45PE40:
11488                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11489                         break;
11490                 case FLASH_5761VENDOR_ATMEL_ADB021D:
11491                 case FLASH_5761VENDOR_ATMEL_MDB021D:
11492                 case FLASH_5761VENDOR_ST_A_M45PE20:
11493                 case FLASH_5761VENDOR_ST_M_M45PE20:
11494                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11495                         break;
11496                 }
11497         }
11498 }
11499
11500 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11501 {
11502         tp->nvram_jedecnum = JEDEC_ATMEL;
11503         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11504         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11505 }
11506
11507 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11508 {
11509         u32 nvcfg1;
11510
11511         nvcfg1 = tr32(NVRAM_CFG1);
11512
11513         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11514         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11515         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11516                 tp->nvram_jedecnum = JEDEC_ATMEL;
11517                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11518                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11519
11520                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11521                 tw32(NVRAM_CFG1, nvcfg1);
11522                 return;
11523         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11524         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11525         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11526         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11527         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11528         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11529         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11530                 tp->nvram_jedecnum = JEDEC_ATMEL;
11531                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11532                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11533
11534                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11535                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11536                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11537                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11538                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11539                         break;
11540                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11541                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11542                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11543                         break;
11544                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11545                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11546                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11547                         break;
11548                 }
11549                 break;
11550         case FLASH_5752VENDOR_ST_M45PE10:
11551         case FLASH_5752VENDOR_ST_M45PE20:
11552         case FLASH_5752VENDOR_ST_M45PE40:
11553                 tp->nvram_jedecnum = JEDEC_ST;
11554                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11555                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11556
11557                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11558                 case FLASH_5752VENDOR_ST_M45PE10:
11559                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11560                         break;
11561                 case FLASH_5752VENDOR_ST_M45PE20:
11562                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11563                         break;
11564                 case FLASH_5752VENDOR_ST_M45PE40:
11565                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11566                         break;
11567                 }
11568                 break;
11569         default:
11570                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11571                 return;
11572         }
11573
11574         tg3_nvram_get_pagesize(tp, nvcfg1);
11575         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11576                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11577 }
11578
11579
11580 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11581 {
11582         u32 nvcfg1;
11583
11584         nvcfg1 = tr32(NVRAM_CFG1);
11585
11586         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11587         case FLASH_5717VENDOR_ATMEL_EEPROM:
11588         case FLASH_5717VENDOR_MICRO_EEPROM:
11589                 tp->nvram_jedecnum = JEDEC_ATMEL;
11590                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11591                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11592
11593                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11594                 tw32(NVRAM_CFG1, nvcfg1);
11595                 return;
11596         case FLASH_5717VENDOR_ATMEL_MDB011D:
11597         case FLASH_5717VENDOR_ATMEL_ADB011B:
11598         case FLASH_5717VENDOR_ATMEL_ADB011D:
11599         case FLASH_5717VENDOR_ATMEL_MDB021D:
11600         case FLASH_5717VENDOR_ATMEL_ADB021B:
11601         case FLASH_5717VENDOR_ATMEL_ADB021D:
11602         case FLASH_5717VENDOR_ATMEL_45USPT:
11603                 tp->nvram_jedecnum = JEDEC_ATMEL;
11604                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11605                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11606
11607                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11608                 case FLASH_5717VENDOR_ATMEL_MDB021D:
11609                 case FLASH_5717VENDOR_ATMEL_ADB021B:
11610                 case FLASH_5717VENDOR_ATMEL_ADB021D:
11611                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11612                         break;
11613                 default:
11614                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11615                         break;
11616                 }
11617                 break;
11618         case FLASH_5717VENDOR_ST_M_M25PE10:
11619         case FLASH_5717VENDOR_ST_A_M25PE10:
11620         case FLASH_5717VENDOR_ST_M_M45PE10:
11621         case FLASH_5717VENDOR_ST_A_M45PE10:
11622         case FLASH_5717VENDOR_ST_M_M25PE20:
11623         case FLASH_5717VENDOR_ST_A_M25PE20:
11624         case FLASH_5717VENDOR_ST_M_M45PE20:
11625         case FLASH_5717VENDOR_ST_A_M45PE20:
11626         case FLASH_5717VENDOR_ST_25USPT:
11627         case FLASH_5717VENDOR_ST_45USPT:
11628                 tp->nvram_jedecnum = JEDEC_ST;
11629                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11630                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11631
11632                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11633                 case FLASH_5717VENDOR_ST_M_M25PE20:
11634                 case FLASH_5717VENDOR_ST_A_M25PE20:
11635                 case FLASH_5717VENDOR_ST_M_M45PE20:
11636                 case FLASH_5717VENDOR_ST_A_M45PE20:
11637                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11638                         break;
11639                 default:
11640                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11641                         break;
11642                 }
11643                 break;
11644         default:
11645                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11646                 return;
11647         }
11648
11649         tg3_nvram_get_pagesize(tp, nvcfg1);
11650         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11651                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11652 }
11653
11654 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11655 static void __devinit tg3_nvram_init(struct tg3 *tp)
11656 {
11657         tw32_f(GRC_EEPROM_ADDR,
11658              (EEPROM_ADDR_FSM_RESET |
11659               (EEPROM_DEFAULT_CLOCK_PERIOD <<
11660                EEPROM_ADDR_CLKPERD_SHIFT)));
11661
11662         msleep(1);
11663
11664         /* Enable seeprom accesses. */
11665         tw32_f(GRC_LOCAL_CTRL,
11666              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11667         udelay(100);
11668
11669         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11670             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11671                 tp->tg3_flags |= TG3_FLAG_NVRAM;
11672
11673                 if (tg3_nvram_lock(tp)) {
11674                         netdev_warn(tp->dev,
11675                                     "Cannot get nvram lock, %s failed\n",
11676                                     __func__);
11677                         return;
11678                 }
11679                 tg3_enable_nvram_access(tp);
11680
11681                 tp->nvram_size = 0;
11682
11683                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11684                         tg3_get_5752_nvram_info(tp);
11685                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11686                         tg3_get_5755_nvram_info(tp);
11687                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11688                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11689                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11690                         tg3_get_5787_nvram_info(tp);
11691                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11692                         tg3_get_5761_nvram_info(tp);
11693                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11694                         tg3_get_5906_nvram_info(tp);
11695                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11696                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11697                         tg3_get_57780_nvram_info(tp);
11698                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
11699                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
11700                         tg3_get_5717_nvram_info(tp);
11701                 else
11702                         tg3_get_nvram_info(tp);
11703
11704                 if (tp->nvram_size == 0)
11705                         tg3_get_nvram_size(tp);
11706
11707                 tg3_disable_nvram_access(tp);
11708                 tg3_nvram_unlock(tp);
11709
11710         } else {
11711                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11712
11713                 tg3_get_eeprom_size(tp);
11714         }
11715 }
11716
11717 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11718                                     u32 offset, u32 len, u8 *buf)
11719 {
11720         int i, j, rc = 0;
11721         u32 val;
11722
11723         for (i = 0; i < len; i += 4) {
11724                 u32 addr;
11725                 __be32 data;
11726
11727                 addr = offset + i;
11728
11729                 memcpy(&data, buf + i, 4);
11730
11731                 /*
11732                  * The SEEPROM interface expects the data to always be opposite
11733                  * the native endian format.  We accomplish this by reversing
11734                  * all the operations that would have been performed on the
11735                  * data from a call to tg3_nvram_read_be32().
11736                  */
11737                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11738
11739                 val = tr32(GRC_EEPROM_ADDR);
11740                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11741
11742                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11743                         EEPROM_ADDR_READ);
11744                 tw32(GRC_EEPROM_ADDR, val |
11745                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
11746                         (addr & EEPROM_ADDR_ADDR_MASK) |
11747                         EEPROM_ADDR_START |
11748                         EEPROM_ADDR_WRITE);
11749
11750                 for (j = 0; j < 1000; j++) {
11751                         val = tr32(GRC_EEPROM_ADDR);
11752
11753                         if (val & EEPROM_ADDR_COMPLETE)
11754                                 break;
11755                         msleep(1);
11756                 }
11757                 if (!(val & EEPROM_ADDR_COMPLETE)) {
11758                         rc = -EBUSY;
11759                         break;
11760                 }
11761         }
11762
11763         return rc;
11764 }
11765
11766 /* offset and length are dword aligned */
11767 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11768                 u8 *buf)
11769 {
11770         int ret = 0;
11771         u32 pagesize = tp->nvram_pagesize;
11772         u32 pagemask = pagesize - 1;
11773         u32 nvram_cmd;
11774         u8 *tmp;
11775
11776         tmp = kmalloc(pagesize, GFP_KERNEL);
11777         if (tmp == NULL)
11778                 return -ENOMEM;
11779
11780         while (len) {
11781                 int j;
11782                 u32 phy_addr, page_off, size;
11783
11784                 phy_addr = offset & ~pagemask;
11785
11786                 for (j = 0; j < pagesize; j += 4) {
11787                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
11788                                                   (__be32 *) (tmp + j));
11789                         if (ret)
11790                                 break;
11791                 }
11792                 if (ret)
11793                         break;
11794
11795                 page_off = offset & pagemask;
11796                 size = pagesize;
11797                 if (len < size)
11798                         size = len;
11799
11800                 len -= size;
11801
11802                 memcpy(tmp + page_off, buf, size);
11803
11804                 offset = offset + (pagesize - page_off);
11805
11806                 tg3_enable_nvram_access(tp);
11807
11808                 /*
11809                  * Before we can erase the flash page, we need
11810                  * to issue a special "write enable" command.
11811                  */
11812                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11813
11814                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11815                         break;
11816
11817                 /* Erase the target page */
11818                 tw32(NVRAM_ADDR, phy_addr);
11819
11820                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11821                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11822
11823                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11824                         break;
11825
11826                 /* Issue another write enable to start the write. */
11827                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11828
11829                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11830                         break;
11831
11832                 for (j = 0; j < pagesize; j += 4) {
11833                         __be32 data;
11834
11835                         data = *((__be32 *) (tmp + j));
11836
11837                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
11838
11839                         tw32(NVRAM_ADDR, phy_addr + j);
11840
11841                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11842                                 NVRAM_CMD_WR;
11843
11844                         if (j == 0)
11845                                 nvram_cmd |= NVRAM_CMD_FIRST;
11846                         else if (j == (pagesize - 4))
11847                                 nvram_cmd |= NVRAM_CMD_LAST;
11848
11849                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11850                                 break;
11851                 }
11852                 if (ret)
11853                         break;
11854         }
11855
11856         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11857         tg3_nvram_exec_cmd(tp, nvram_cmd);
11858
11859         kfree(tmp);
11860
11861         return ret;
11862 }
11863
11864 /* offset and length are dword aligned */
11865 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11866                 u8 *buf)
11867 {
11868         int i, ret = 0;
11869
11870         for (i = 0; i < len; i += 4, offset += 4) {
11871                 u32 page_off, phy_addr, nvram_cmd;
11872                 __be32 data;
11873
11874                 memcpy(&data, buf + i, 4);
11875                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11876
11877                 page_off = offset % tp->nvram_pagesize;
11878
11879                 phy_addr = tg3_nvram_phys_addr(tp, offset);
11880
11881                 tw32(NVRAM_ADDR, phy_addr);
11882
11883                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11884
11885                 if (page_off == 0 || i == 0)
11886                         nvram_cmd |= NVRAM_CMD_FIRST;
11887                 if (page_off == (tp->nvram_pagesize - 4))
11888                         nvram_cmd |= NVRAM_CMD_LAST;
11889
11890                 if (i == (len - 4))
11891                         nvram_cmd |= NVRAM_CMD_LAST;
11892
11893                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11894                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11895                     (tp->nvram_jedecnum == JEDEC_ST) &&
11896                     (nvram_cmd & NVRAM_CMD_FIRST)) {
11897
11898                         if ((ret = tg3_nvram_exec_cmd(tp,
11899                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11900                                 NVRAM_CMD_DONE)))
11901
11902                                 break;
11903                 }
11904                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11905                         /* We always do complete word writes to eeprom. */
11906                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11907                 }
11908
11909                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11910                         break;
11911         }
11912         return ret;
11913 }
11914
11915 /* offset and length are dword aligned */
11916 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11917 {
11918         int ret;
11919
11920         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11921                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11922                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
11923                 udelay(40);
11924         }
11925
11926         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11927                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11928         } else {
11929                 u32 grc_mode;
11930
11931                 ret = tg3_nvram_lock(tp);
11932                 if (ret)
11933                         return ret;
11934
11935                 tg3_enable_nvram_access(tp);
11936                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11937                     !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
11938                         tw32(NVRAM_WRITE1, 0x406);
11939
11940                 grc_mode = tr32(GRC_MODE);
11941                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11942
11943                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11944                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11945
11946                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
11947                                 buf);
11948                 } else {
11949                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11950                                 buf);
11951                 }
11952
11953                 grc_mode = tr32(GRC_MODE);
11954                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11955
11956                 tg3_disable_nvram_access(tp);
11957                 tg3_nvram_unlock(tp);
11958         }
11959
11960         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11961                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11962                 udelay(40);
11963         }
11964
11965         return ret;
11966 }
11967
11968 struct subsys_tbl_ent {
11969         u16 subsys_vendor, subsys_devid;
11970         u32 phy_id;
11971 };
11972
11973 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
11974         /* Broadcom boards. */
11975         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11976           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
11977         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11978           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
11979         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11980           TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
11981         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11982           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
11983         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11984           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
11985         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11986           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
11987         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11988           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
11989         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11990           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
11991         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11992           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
11993         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11994           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
11995         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11996           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
11997
11998         /* 3com boards. */
11999         { TG3PCI_SUBVENDOR_ID_3COM,
12000           TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
12001         { TG3PCI_SUBVENDOR_ID_3COM,
12002           TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
12003         { TG3PCI_SUBVENDOR_ID_3COM,
12004           TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
12005         { TG3PCI_SUBVENDOR_ID_3COM,
12006           TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
12007         { TG3PCI_SUBVENDOR_ID_3COM,
12008           TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
12009
12010         /* DELL boards. */
12011         { TG3PCI_SUBVENDOR_ID_DELL,
12012           TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
12013         { TG3PCI_SUBVENDOR_ID_DELL,
12014           TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
12015         { TG3PCI_SUBVENDOR_ID_DELL,
12016           TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
12017         { TG3PCI_SUBVENDOR_ID_DELL,
12018           TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
12019
12020         /* Compaq boards. */
12021         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12022           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
12023         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12024           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
12025         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12026           TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
12027         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12028           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
12029         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12030           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
12031
12032         /* IBM boards. */
12033         { TG3PCI_SUBVENDOR_ID_IBM,
12034           TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
12035 };
12036
12037 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
12038 {
12039         int i;
12040
12041         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12042                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12043                      tp->pdev->subsystem_vendor) &&
12044                     (subsys_id_to_phy_id[i].subsys_devid ==
12045                      tp->pdev->subsystem_device))
12046                         return &subsys_id_to_phy_id[i];
12047         }
12048         return NULL;
12049 }
12050
12051 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12052 {
12053         u32 val;
12054         u16 pmcsr;
12055
12056         /* On some early chips the SRAM cannot be accessed in D3hot state,
12057          * so need make sure we're in D0.
12058          */
12059         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12060         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12061         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12062         msleep(1);
12063
12064         /* Make sure register accesses (indirect or otherwise)
12065          * will function correctly.
12066          */
12067         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12068                                tp->misc_host_ctrl);
12069
12070         /* The memory arbiter has to be enabled in order for SRAM accesses
12071          * to succeed.  Normally on powerup the tg3 chip firmware will make
12072          * sure it is enabled, but other entities such as system netboot
12073          * code might disable it.
12074          */
12075         val = tr32(MEMARB_MODE);
12076         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12077
12078         tp->phy_id = TG3_PHY_ID_INVALID;
12079         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12080
12081         /* Assume an onboard device and WOL capable by default.  */
12082         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12083
12084         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12085                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12086                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12087                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12088                 }
12089                 val = tr32(VCPU_CFGSHDW);
12090                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12091                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12092                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12093                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
12094                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12095                 goto done;
12096         }
12097
12098         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12099         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12100                 u32 nic_cfg, led_cfg;
12101                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12102                 int eeprom_phy_serdes = 0;
12103
12104                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12105                 tp->nic_sram_data_cfg = nic_cfg;
12106
12107                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12108                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12109                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12110                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12111                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12112                     (ver > 0) && (ver < 0x100))
12113                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12114
12115                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12116                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12117
12118                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12119                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12120                         eeprom_phy_serdes = 1;
12121
12122                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12123                 if (nic_phy_id != 0) {
12124                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12125                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12126
12127                         eeprom_phy_id  = (id1 >> 16) << 10;
12128                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
12129                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
12130                 } else
12131                         eeprom_phy_id = 0;
12132
12133                 tp->phy_id = eeprom_phy_id;
12134                 if (eeprom_phy_serdes) {
12135                         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12136                                 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12137                         else
12138                                 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
12139                 }
12140
12141                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12142                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12143                                     SHASTA_EXT_LED_MODE_MASK);
12144                 else
12145                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12146
12147                 switch (led_cfg) {
12148                 default:
12149                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12150                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12151                         break;
12152
12153                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12154                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12155                         break;
12156
12157                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12158                         tp->led_ctrl = LED_CTRL_MODE_MAC;
12159
12160                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12161                          * read on some older 5700/5701 bootcode.
12162                          */
12163                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12164                             ASIC_REV_5700 ||
12165                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
12166                             ASIC_REV_5701)
12167                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12168
12169                         break;
12170
12171                 case SHASTA_EXT_LED_SHARED:
12172                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
12173                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12174                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12175                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12176                                                  LED_CTRL_MODE_PHY_2);
12177                         break;
12178
12179                 case SHASTA_EXT_LED_MAC:
12180                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12181                         break;
12182
12183                 case SHASTA_EXT_LED_COMBO:
12184                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
12185                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12186                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12187                                                  LED_CTRL_MODE_PHY_2);
12188                         break;
12189
12190                 }
12191
12192                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12193                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12194                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12195                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12196
12197                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12198                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12199
12200                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12201                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12202                         if ((tp->pdev->subsystem_vendor ==
12203                              PCI_VENDOR_ID_ARIMA) &&
12204                             (tp->pdev->subsystem_device == 0x205a ||
12205                              tp->pdev->subsystem_device == 0x2063))
12206                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12207                 } else {
12208                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12209                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12210                 }
12211
12212                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12213                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12214                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12215                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12216                 }
12217
12218                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12219                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12220                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12221
12222                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
12223                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12224                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12225
12226                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12227                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12228                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12229
12230                 if (cfg2 & (1 << 17))
12231                         tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
12232
12233                 /* serdes signal pre-emphasis in register 0x590 set by */
12234                 /* bootcode if bit 18 is set */
12235                 if (cfg2 & (1 << 18))
12236                         tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
12237
12238                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12239                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
12240                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12241                         tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
12242
12243                 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12244                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12245                     !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
12246                         u32 cfg3;
12247
12248                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12249                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12250                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12251                 }
12252
12253                 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12254                         tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
12255                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12256                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12257                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12258                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12259         }
12260 done:
12261         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12262         device_set_wakeup_enable(&tp->pdev->dev,
12263                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12264 }
12265
12266 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12267 {
12268         int i;
12269         u32 val;
12270
12271         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12272         tw32(OTP_CTRL, cmd);
12273
12274         /* Wait for up to 1 ms for command to execute. */
12275         for (i = 0; i < 100; i++) {
12276                 val = tr32(OTP_STATUS);
12277                 if (val & OTP_STATUS_CMD_DONE)
12278                         break;
12279                 udelay(10);
12280         }
12281
12282         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12283 }
12284
12285 /* Read the gphy configuration from the OTP region of the chip.  The gphy
12286  * configuration is a 32-bit value that straddles the alignment boundary.
12287  * We do two 32-bit reads and then shift and merge the results.
12288  */
12289 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12290 {
12291         u32 bhalf_otp, thalf_otp;
12292
12293         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12294
12295         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12296                 return 0;
12297
12298         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12299
12300         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12301                 return 0;
12302
12303         thalf_otp = tr32(OTP_READ_DATA);
12304
12305         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12306
12307         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12308                 return 0;
12309
12310         bhalf_otp = tr32(OTP_READ_DATA);
12311
12312         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12313 }
12314
12315 static int __devinit tg3_phy_probe(struct tg3 *tp)
12316 {
12317         u32 hw_phy_id_1, hw_phy_id_2;
12318         u32 hw_phy_id, hw_phy_id_masked;
12319         int err;
12320
12321         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12322                 return tg3_phy_init(tp);
12323
12324         /* Reading the PHY ID register can conflict with ASF
12325          * firmware access to the PHY hardware.
12326          */
12327         err = 0;
12328         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12329             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12330                 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
12331         } else {
12332                 /* Now read the physical PHY_ID from the chip and verify
12333                  * that it is sane.  If it doesn't look good, we fall back
12334                  * to either the hard-coded table based PHY_ID and failing
12335                  * that the value found in the eeprom area.
12336                  */
12337                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12338                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12339
12340                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
12341                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12342                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
12343
12344                 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
12345         }
12346
12347         if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
12348                 tp->phy_id = hw_phy_id;
12349                 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
12350                         tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12351                 else
12352                         tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
12353         } else {
12354                 if (tp->phy_id != TG3_PHY_ID_INVALID) {
12355                         /* Do nothing, phy ID already set up in
12356                          * tg3_get_eeprom_hw_cfg().
12357                          */
12358                 } else {
12359                         struct subsys_tbl_ent *p;
12360
12361                         /* No eeprom signature?  Try the hardcoded
12362                          * subsys device table.
12363                          */
12364                         p = tg3_lookup_by_subsys(tp);
12365                         if (!p)
12366                                 return -ENODEV;
12367
12368                         tp->phy_id = p->phy_id;
12369                         if (!tp->phy_id ||
12370                             tp->phy_id == TG3_PHY_ID_BCM8002)
12371                                 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12372                 }
12373         }
12374
12375         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
12376             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12377             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12378                 u32 bmsr, adv_reg, tg3_ctrl, mask;
12379
12380                 tg3_readphy(tp, MII_BMSR, &bmsr);
12381                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12382                     (bmsr & BMSR_LSTATUS))
12383                         goto skip_phy_reset;
12384
12385                 err = tg3_phy_reset(tp);
12386                 if (err)
12387                         return err;
12388
12389                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12390                            ADVERTISE_100HALF | ADVERTISE_100FULL |
12391                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12392                 tg3_ctrl = 0;
12393                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
12394                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12395                                     MII_TG3_CTRL_ADV_1000_FULL);
12396                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12397                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12398                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12399                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
12400                 }
12401
12402                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12403                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12404                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12405                 if (!tg3_copper_is_advertising_all(tp, mask)) {
12406                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12407
12408                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12409                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12410
12411                         tg3_writephy(tp, MII_BMCR,
12412                                      BMCR_ANENABLE | BMCR_ANRESTART);
12413                 }
12414                 tg3_phy_set_wirespeed(tp);
12415
12416                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12417                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12418                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12419         }
12420
12421 skip_phy_reset:
12422         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
12423                 err = tg3_init_5401phy_dsp(tp);
12424                 if (err)
12425                         return err;
12426
12427                 err = tg3_init_5401phy_dsp(tp);
12428         }
12429
12430         if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
12431                 tp->link_config.advertising =
12432                         (ADVERTISED_1000baseT_Half |
12433                          ADVERTISED_1000baseT_Full |
12434                          ADVERTISED_Autoneg |
12435                          ADVERTISED_FIBRE);
12436         if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
12437                 tp->link_config.advertising &=
12438                         ~(ADVERTISED_1000baseT_Half |
12439                           ADVERTISED_1000baseT_Full);
12440
12441         return err;
12442 }
12443
12444 static void __devinit tg3_read_vpd(struct tg3 *tp)
12445 {
12446         u8 *vpd_data;
12447         unsigned int block_end, rosize, len;
12448         int j, i = 0;
12449         u32 magic;
12450
12451         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12452             tg3_nvram_read(tp, 0x0, &magic))
12453                 goto out_no_vpd;
12454
12455         vpd_data = kmalloc(TG3_NVM_VPD_LEN, GFP_KERNEL);
12456         if (!vpd_data)
12457                 goto out_no_vpd;
12458
12459         if (magic == TG3_EEPROM_MAGIC) {
12460                 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12461                         u32 tmp;
12462
12463                         /* The data is in little-endian format in NVRAM.
12464                          * Use the big-endian read routines to preserve
12465                          * the byte order as it exists in NVRAM.
12466                          */
12467                         if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12468                                 goto out_not_found;
12469
12470                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12471                 }
12472         } else {
12473                 ssize_t cnt;
12474                 unsigned int pos = 0;
12475
12476                 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12477                         cnt = pci_read_vpd(tp->pdev, pos,
12478                                            TG3_NVM_VPD_LEN - pos,
12479                                            &vpd_data[pos]);
12480                         if (cnt == -ETIMEDOUT || -EINTR)
12481                                 cnt = 0;
12482                         else if (cnt < 0)
12483                                 goto out_not_found;
12484                 }
12485                 if (pos != TG3_NVM_VPD_LEN)
12486                         goto out_not_found;
12487         }
12488
12489         i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
12490                              PCI_VPD_LRDT_RO_DATA);
12491         if (i < 0)
12492                 goto out_not_found;
12493
12494         rosize = pci_vpd_lrdt_size(&vpd_data[i]);
12495         block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
12496         i += PCI_VPD_LRDT_TAG_SIZE;
12497
12498         if (block_end > TG3_NVM_VPD_LEN)
12499                 goto out_not_found;
12500
12501         j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12502                                       PCI_VPD_RO_KEYWORD_MFR_ID);
12503         if (j > 0) {
12504                 len = pci_vpd_info_field_size(&vpd_data[j]);
12505
12506                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12507                 if (j + len > block_end || len != 4 ||
12508                     memcmp(&vpd_data[j], "1028", 4))
12509                         goto partno;
12510
12511                 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12512                                               PCI_VPD_RO_KEYWORD_VENDOR0);
12513                 if (j < 0)
12514                         goto partno;
12515
12516                 len = pci_vpd_info_field_size(&vpd_data[j]);
12517
12518                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12519                 if (j + len > block_end)
12520                         goto partno;
12521
12522                 memcpy(tp->fw_ver, &vpd_data[j], len);
12523                 strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
12524         }
12525
12526 partno:
12527         i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12528                                       PCI_VPD_RO_KEYWORD_PARTNO);
12529         if (i < 0)
12530                 goto out_not_found;
12531
12532         len = pci_vpd_info_field_size(&vpd_data[i]);
12533
12534         i += PCI_VPD_INFO_FLD_HDR_SIZE;
12535         if (len > TG3_BPN_SIZE ||
12536             (len + i) > TG3_NVM_VPD_LEN)
12537                 goto out_not_found;
12538
12539         memcpy(tp->board_part_number, &vpd_data[i], len);
12540
12541 out_not_found:
12542         kfree(vpd_data);
12543         if (tp->board_part_number[0])
12544                 return;
12545
12546 out_no_vpd:
12547         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
12548                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717)
12549                         strcpy(tp->board_part_number, "BCM5717");
12550                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
12551                         strcpy(tp->board_part_number, "BCM5718");
12552                 else
12553                         goto nomatch;
12554         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
12555                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12556                         strcpy(tp->board_part_number, "BCM57780");
12557                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12558                         strcpy(tp->board_part_number, "BCM57760");
12559                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12560                         strcpy(tp->board_part_number, "BCM57790");
12561                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12562                         strcpy(tp->board_part_number, "BCM57788");
12563                 else
12564                         goto nomatch;
12565         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
12566                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
12567                         strcpy(tp->board_part_number, "BCM57761");
12568                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
12569                         strcpy(tp->board_part_number, "BCM57765");
12570                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
12571                         strcpy(tp->board_part_number, "BCM57781");
12572                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
12573                         strcpy(tp->board_part_number, "BCM57785");
12574                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
12575                         strcpy(tp->board_part_number, "BCM57791");
12576                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12577                         strcpy(tp->board_part_number, "BCM57795");
12578                 else
12579                         goto nomatch;
12580         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12581                 strcpy(tp->board_part_number, "BCM95906");
12582         } else {
12583 nomatch:
12584                 strcpy(tp->board_part_number, "none");
12585         }
12586 }
12587
12588 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12589 {
12590         u32 val;
12591
12592         if (tg3_nvram_read(tp, offset, &val) ||
12593             (val & 0xfc000000) != 0x0c000000 ||
12594             tg3_nvram_read(tp, offset + 4, &val) ||
12595             val != 0)
12596                 return 0;
12597
12598         return 1;
12599 }
12600
12601 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12602 {
12603         u32 val, offset, start, ver_offset;
12604         int i, dst_off;
12605         bool newver = false;
12606
12607         if (tg3_nvram_read(tp, 0xc, &offset) ||
12608             tg3_nvram_read(tp, 0x4, &start))
12609                 return;
12610
12611         offset = tg3_nvram_logical_addr(tp, offset);
12612
12613         if (tg3_nvram_read(tp, offset, &val))
12614                 return;
12615
12616         if ((val & 0xfc000000) == 0x0c000000) {
12617                 if (tg3_nvram_read(tp, offset + 4, &val))
12618                         return;
12619
12620                 if (val == 0)
12621                         newver = true;
12622         }
12623
12624         dst_off = strlen(tp->fw_ver);
12625
12626         if (newver) {
12627                 if (TG3_VER_SIZE - dst_off < 16 ||
12628                     tg3_nvram_read(tp, offset + 8, &ver_offset))
12629                         return;
12630
12631                 offset = offset + ver_offset - start;
12632                 for (i = 0; i < 16; i += 4) {
12633                         __be32 v;
12634                         if (tg3_nvram_read_be32(tp, offset + i, &v))
12635                                 return;
12636
12637                         memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
12638                 }
12639         } else {
12640                 u32 major, minor;
12641
12642                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12643                         return;
12644
12645                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12646                         TG3_NVM_BCVER_MAJSFT;
12647                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12648                 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
12649                          "v%d.%02d", major, minor);
12650         }
12651 }
12652
12653 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12654 {
12655         u32 val, major, minor;
12656
12657         /* Use native endian representation */
12658         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12659                 return;
12660
12661         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12662                 TG3_NVM_HWSB_CFG1_MAJSFT;
12663         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12664                 TG3_NVM_HWSB_CFG1_MINSFT;
12665
12666         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12667 }
12668
12669 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12670 {
12671         u32 offset, major, minor, build;
12672
12673         strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
12674
12675         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12676                 return;
12677
12678         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12679         case TG3_EEPROM_SB_REVISION_0:
12680                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12681                 break;
12682         case TG3_EEPROM_SB_REVISION_2:
12683                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12684                 break;
12685         case TG3_EEPROM_SB_REVISION_3:
12686                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12687                 break;
12688         case TG3_EEPROM_SB_REVISION_4:
12689                 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
12690                 break;
12691         case TG3_EEPROM_SB_REVISION_5:
12692                 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
12693                 break;
12694         default:
12695                 return;
12696         }
12697
12698         if (tg3_nvram_read(tp, offset, &val))
12699                 return;
12700
12701         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12702                 TG3_EEPROM_SB_EDH_BLD_SHFT;
12703         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12704                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12705         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
12706
12707         if (minor > 99 || build > 26)
12708                 return;
12709
12710         offset = strlen(tp->fw_ver);
12711         snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
12712                  " v%d.%02d", major, minor);
12713
12714         if (build > 0) {
12715                 offset = strlen(tp->fw_ver);
12716                 if (offset < TG3_VER_SIZE - 1)
12717                         tp->fw_ver[offset] = 'a' + build - 1;
12718         }
12719 }
12720
12721 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12722 {
12723         u32 val, offset, start;
12724         int i, vlen;
12725
12726         for (offset = TG3_NVM_DIR_START;
12727              offset < TG3_NVM_DIR_END;
12728              offset += TG3_NVM_DIRENT_SIZE) {
12729                 if (tg3_nvram_read(tp, offset, &val))
12730                         return;
12731
12732                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12733                         break;
12734         }
12735
12736         if (offset == TG3_NVM_DIR_END)
12737                 return;
12738
12739         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12740                 start = 0x08000000;
12741         else if (tg3_nvram_read(tp, offset - 4, &start))
12742                 return;
12743
12744         if (tg3_nvram_read(tp, offset + 4, &offset) ||
12745             !tg3_fw_img_is_valid(tp, offset) ||
12746             tg3_nvram_read(tp, offset + 8, &val))
12747                 return;
12748
12749         offset += val - start;
12750
12751         vlen = strlen(tp->fw_ver);
12752
12753         tp->fw_ver[vlen++] = ',';
12754         tp->fw_ver[vlen++] = ' ';
12755
12756         for (i = 0; i < 4; i++) {
12757                 __be32 v;
12758                 if (tg3_nvram_read_be32(tp, offset, &v))
12759                         return;
12760
12761                 offset += sizeof(v);
12762
12763                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12764                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12765                         break;
12766                 }
12767
12768                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12769                 vlen += sizeof(v);
12770         }
12771 }
12772
12773 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12774 {
12775         int vlen;
12776         u32 apedata;
12777         char *fwtype;
12778
12779         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12780             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
12781                 return;
12782
12783         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12784         if (apedata != APE_SEG_SIG_MAGIC)
12785                 return;
12786
12787         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12788         if (!(apedata & APE_FW_STATUS_READY))
12789                 return;
12790
12791         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12792
12793         if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) {
12794                 tp->tg3_flags3 |= TG3_FLG3_APE_HAS_NCSI;
12795                 fwtype = "NCSI";
12796         } else {
12797                 fwtype = "DASH";
12798         }
12799
12800         vlen = strlen(tp->fw_ver);
12801
12802         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
12803                  fwtype,
12804                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12805                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12806                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12807                  (apedata & APE_FW_VERSION_BLDMSK));
12808 }
12809
12810 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12811 {
12812         u32 val;
12813         bool vpd_vers = false;
12814
12815         if (tp->fw_ver[0] != 0)
12816                 vpd_vers = true;
12817
12818         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12819                 strcat(tp->fw_ver, "sb");
12820                 return;
12821         }
12822
12823         if (tg3_nvram_read(tp, 0, &val))
12824                 return;
12825
12826         if (val == TG3_EEPROM_MAGIC)
12827                 tg3_read_bc_ver(tp);
12828         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12829                 tg3_read_sb_ver(tp, val);
12830         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12831                 tg3_read_hwsb_ver(tp);
12832         else
12833                 return;
12834
12835         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12836              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
12837                 goto done;
12838
12839         tg3_read_mgmtfw_ver(tp);
12840
12841 done:
12842         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12843 }
12844
12845 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12846
12847 static void inline vlan_features_add(struct net_device *dev, unsigned long flags)
12848 {
12849 #if TG3_VLAN_TAG_USED
12850         dev->vlan_features |= flags;
12851 #endif
12852 }
12853
12854 static int __devinit tg3_get_invariants(struct tg3 *tp)
12855 {
12856         static struct pci_device_id write_reorder_chipsets[] = {
12857                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12858                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12859                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12860                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12861                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12862                              PCI_DEVICE_ID_VIA_8385_0) },
12863                 { },
12864         };
12865         u32 misc_ctrl_reg;
12866         u32 pci_state_reg, grc_misc_cfg;
12867         u32 val;
12868         u16 pci_cmd;
12869         int err;
12870
12871         /* Force memory write invalidate off.  If we leave it on,
12872          * then on 5700_BX chips we have to enable a workaround.
12873          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12874          * to match the cacheline size.  The Broadcom driver have this
12875          * workaround but turns MWI off all the times so never uses
12876          * it.  This seems to suggest that the workaround is insufficient.
12877          */
12878         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12879         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12880         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12881
12882         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12883          * has the register indirect write enable bit set before
12884          * we try to access any of the MMIO registers.  It is also
12885          * critical that the PCI-X hw workaround situation is decided
12886          * before that as well.
12887          */
12888         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12889                               &misc_ctrl_reg);
12890
12891         tp->pci_chip_rev_id = (misc_ctrl_reg >>
12892                                MISC_HOST_CTRL_CHIPREV_SHIFT);
12893         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12894                 u32 prod_id_asic_rev;
12895
12896                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12897                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12898                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719)
12899                         pci_read_config_dword(tp->pdev,
12900                                               TG3PCI_GEN2_PRODID_ASICREV,
12901                                               &prod_id_asic_rev);
12902                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
12903                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
12904                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
12905                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
12906                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
12907                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12908                         pci_read_config_dword(tp->pdev,
12909                                               TG3PCI_GEN15_PRODID_ASICREV,
12910                                               &prod_id_asic_rev);
12911                 else
12912                         pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12913                                               &prod_id_asic_rev);
12914
12915                 tp->pci_chip_rev_id = prod_id_asic_rev;
12916         }
12917
12918         /* Wrong chip ID in 5752 A0. This code can be removed later
12919          * as A0 is not in production.
12920          */
12921         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12922                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12923
12924         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12925          * we need to disable memory and use config. cycles
12926          * only to access all registers. The 5702/03 chips
12927          * can mistakenly decode the special cycles from the
12928          * ICH chipsets as memory write cycles, causing corruption
12929          * of register and memory space. Only certain ICH bridges
12930          * will drive special cycles with non-zero data during the
12931          * address phase which can fall within the 5703's address
12932          * range. This is not an ICH bug as the PCI spec allows
12933          * non-zero address during special cycles. However, only
12934          * these ICH bridges are known to drive non-zero addresses
12935          * during special cycles.
12936          *
12937          * Since special cycles do not cross PCI bridges, we only
12938          * enable this workaround if the 5703 is on the secondary
12939          * bus of these ICH bridges.
12940          */
12941         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12942             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12943                 static struct tg3_dev_id {
12944                         u32     vendor;
12945                         u32     device;
12946                         u32     rev;
12947                 } ich_chipsets[] = {
12948                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12949                           PCI_ANY_ID },
12950                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12951                           PCI_ANY_ID },
12952                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12953                           0xa },
12954                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12955                           PCI_ANY_ID },
12956                         { },
12957                 };
12958                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12959                 struct pci_dev *bridge = NULL;
12960
12961                 while (pci_id->vendor != 0) {
12962                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
12963                                                 bridge);
12964                         if (!bridge) {
12965                                 pci_id++;
12966                                 continue;
12967                         }
12968                         if (pci_id->rev != PCI_ANY_ID) {
12969                                 if (bridge->revision > pci_id->rev)
12970                                         continue;
12971                         }
12972                         if (bridge->subordinate &&
12973                             (bridge->subordinate->number ==
12974                              tp->pdev->bus->number)) {
12975
12976                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12977                                 pci_dev_put(bridge);
12978                                 break;
12979                         }
12980                 }
12981         }
12982
12983         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12984                 static struct tg3_dev_id {
12985                         u32     vendor;
12986                         u32     device;
12987                 } bridge_chipsets[] = {
12988                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12989                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12990                         { },
12991                 };
12992                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12993                 struct pci_dev *bridge = NULL;
12994
12995                 while (pci_id->vendor != 0) {
12996                         bridge = pci_get_device(pci_id->vendor,
12997                                                 pci_id->device,
12998                                                 bridge);
12999                         if (!bridge) {
13000                                 pci_id++;
13001                                 continue;
13002                         }
13003                         if (bridge->subordinate &&
13004                             (bridge->subordinate->number <=
13005                              tp->pdev->bus->number) &&
13006                             (bridge->subordinate->subordinate >=
13007                              tp->pdev->bus->number)) {
13008                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
13009                                 pci_dev_put(bridge);
13010                                 break;
13011                         }
13012                 }
13013         }
13014
13015         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
13016          * DMA addresses > 40-bit. This bridge may have other additional
13017          * 57xx devices behind it in some 4-port NIC designs for example.
13018          * Any tg3 device found behind the bridge will also need the 40-bit
13019          * DMA workaround.
13020          */
13021         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
13022             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13023                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
13024                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13025                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
13026         } else {
13027                 struct pci_dev *bridge = NULL;
13028
13029                 do {
13030                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
13031                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
13032                                                 bridge);
13033                         if (bridge && bridge->subordinate &&
13034                             (bridge->subordinate->number <=
13035                              tp->pdev->bus->number) &&
13036                             (bridge->subordinate->subordinate >=
13037                              tp->pdev->bus->number)) {
13038                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13039                                 pci_dev_put(bridge);
13040                                 break;
13041                         }
13042                 } while (bridge);
13043         }
13044
13045         /* Initialize misc host control in PCI block. */
13046         tp->misc_host_ctrl |= (misc_ctrl_reg &
13047                                MISC_HOST_CTRL_CHIPREV);
13048         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13049                                tp->misc_host_ctrl);
13050
13051         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13052             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13053             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13054                 tp->pdev_peer = tg3_find_peer(tp);
13055
13056         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13057             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13058             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13059                 tp->tg3_flags3 |= TG3_FLG3_5717_PLUS;
13060
13061         /* Intentionally exclude ASIC_REV_5906 */
13062         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13063             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13064             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13065             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13066             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13067             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13068             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13069                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13070
13071         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13072             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13073             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13074             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13075             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13076                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13077
13078         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13079             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13080                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13081
13082         /* 5700 B0 chips do not support checksumming correctly due
13083          * to hardware bugs.
13084          */
13085         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13086                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13087         else {
13088                 unsigned long features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_GRO;
13089
13090                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13091                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13092                         features |= NETIF_F_IPV6_CSUM;
13093                 tp->dev->features |= features;
13094                 vlan_features_add(tp->dev, features);
13095         }
13096
13097         /* Determine TSO capabilities */
13098         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13099                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13100         else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13101                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13102                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13103         else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13104                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13105                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13106                     tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13107                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13108         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13109                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13110                    tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13111                 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13112                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13113                         tp->fw_needed = FIRMWARE_TG3TSO5;
13114                 else
13115                         tp->fw_needed = FIRMWARE_TG3TSO;
13116         }
13117
13118         tp->irq_max = 1;
13119
13120         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13121                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13122                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13123                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13124                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13125                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13126                      tp->pdev_peer == tp->pdev))
13127                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13128
13129                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13130                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13131                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13132                 }
13133
13134                 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
13135                         tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13136                         tp->irq_max = TG3_IRQ_MAX_VECS;
13137                 }
13138         }
13139
13140         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13141             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13142             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13143                 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13144         else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13145                 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13146                 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13147         }
13148
13149         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13150                 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13151
13152         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13153             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13154             (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13155                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13156
13157         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13158                               &pci_state_reg);
13159
13160         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13161         if (tp->pcie_cap != 0) {
13162                 u16 lnkctl;
13163
13164                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13165
13166                 pcie_set_readrq(tp->pdev, 4096);
13167
13168                 pci_read_config_word(tp->pdev,
13169                                      tp->pcie_cap + PCI_EXP_LNKCTL,
13170                                      &lnkctl);
13171                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13172                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13173                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13174                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13175                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13176                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13177                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13178                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13179                 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13180                         tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13181                 }
13182         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13183                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13184         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13185                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13186                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13187                 if (!tp->pcix_cap) {
13188                         dev_err(&tp->pdev->dev,
13189                                 "Cannot find PCI-X capability, aborting\n");
13190                         return -EIO;
13191                 }
13192
13193                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13194                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13195         }
13196
13197         /* If we have an AMD 762 or VIA K8T800 chipset, write
13198          * reordering to the mailbox registers done by the host
13199          * controller can cause major troubles.  We read back from
13200          * every mailbox register write to force the writes to be
13201          * posted to the chip in order.
13202          */
13203         if (pci_dev_present(write_reorder_chipsets) &&
13204             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13205                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13206
13207         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13208                              &tp->pci_cacheline_sz);
13209         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13210                              &tp->pci_lat_timer);
13211         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13212             tp->pci_lat_timer < 64) {
13213                 tp->pci_lat_timer = 64;
13214                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13215                                       tp->pci_lat_timer);
13216         }
13217
13218         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13219                 /* 5700 BX chips need to have their TX producer index
13220                  * mailboxes written twice to workaround a bug.
13221                  */
13222                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13223
13224                 /* If we are in PCI-X mode, enable register write workaround.
13225                  *
13226                  * The workaround is to use indirect register accesses
13227                  * for all chip writes not to mailbox registers.
13228                  */
13229                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13230                         u32 pm_reg;
13231
13232                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13233
13234                         /* The chip can have it's power management PCI config
13235                          * space registers clobbered due to this bug.
13236                          * So explicitly force the chip into D0 here.
13237                          */
13238                         pci_read_config_dword(tp->pdev,
13239                                               tp->pm_cap + PCI_PM_CTRL,
13240                                               &pm_reg);
13241                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13242                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13243                         pci_write_config_dword(tp->pdev,
13244                                                tp->pm_cap + PCI_PM_CTRL,
13245                                                pm_reg);
13246
13247                         /* Also, force SERR#/PERR# in PCI command. */
13248                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13249                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13250                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13251                 }
13252         }
13253
13254         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13255                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13256         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13257                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13258
13259         /* Chip-specific fixup from Broadcom driver */
13260         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13261             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13262                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13263                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13264         }
13265
13266         /* Default fast path register access methods */
13267         tp->read32 = tg3_read32;
13268         tp->write32 = tg3_write32;
13269         tp->read32_mbox = tg3_read32;
13270         tp->write32_mbox = tg3_write32;
13271         tp->write32_tx_mbox = tg3_write32;
13272         tp->write32_rx_mbox = tg3_write32;
13273
13274         /* Various workaround register access methods */
13275         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13276                 tp->write32 = tg3_write_indirect_reg32;
13277         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13278                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13279                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13280                 /*
13281                  * Back to back register writes can cause problems on these
13282                  * chips, the workaround is to read back all reg writes
13283                  * except those to mailbox regs.
13284                  *
13285                  * See tg3_write_indirect_reg32().
13286                  */
13287                 tp->write32 = tg3_write_flush_reg32;
13288         }
13289
13290         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13291             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13292                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13293                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13294                         tp->write32_rx_mbox = tg3_write_flush_reg32;
13295         }
13296
13297         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13298                 tp->read32 = tg3_read_indirect_reg32;
13299                 tp->write32 = tg3_write_indirect_reg32;
13300                 tp->read32_mbox = tg3_read_indirect_mbox;
13301                 tp->write32_mbox = tg3_write_indirect_mbox;
13302                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13303                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13304
13305                 iounmap(tp->regs);
13306                 tp->regs = NULL;
13307
13308                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13309                 pci_cmd &= ~PCI_COMMAND_MEMORY;
13310                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13311         }
13312         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13313                 tp->read32_mbox = tg3_read32_mbox_5906;
13314                 tp->write32_mbox = tg3_write32_mbox_5906;
13315                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13316                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13317         }
13318
13319         if (tp->write32 == tg3_write_indirect_reg32 ||
13320             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13321              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13322               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13323                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13324
13325         /* Get eeprom hw config before calling tg3_set_power_state().
13326          * In particular, the TG3_FLG2_IS_NIC flag must be
13327          * determined before calling tg3_set_power_state() so that
13328          * we know whether or not to switch out of Vaux power.
13329          * When the flag is set, it means that GPIO1 is used for eeprom
13330          * write protect and also implies that it is a LOM where GPIOs
13331          * are not used to switch power.
13332          */
13333         tg3_get_eeprom_hw_cfg(tp);
13334
13335         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13336                 /* Allow reads and writes to the
13337                  * APE register and memory space.
13338                  */
13339                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13340                                  PCISTATE_ALLOW_APE_SHMEM_WR |
13341                                  PCISTATE_ALLOW_APE_PSPACE_WR;
13342                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13343                                        pci_state_reg);
13344         }
13345
13346         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13347             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13348             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13349             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13350             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13351                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13352
13353         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13354          * GPIO1 driven high will bring 5700's external PHY out of reset.
13355          * It is also used as eeprom write protect on LOMs.
13356          */
13357         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13358         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13359             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13360                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13361                                        GRC_LCLCTRL_GPIO_OUTPUT1);
13362         /* Unused GPIO3 must be driven as output on 5752 because there
13363          * are no pull-up resistors on unused GPIO pins.
13364          */
13365         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13366                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13367
13368         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13369             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13370             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13371                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13372
13373         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13374             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13375                 /* Turn off the debug UART. */
13376                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13377                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13378                         /* Keep VMain power. */
13379                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13380                                               GRC_LCLCTRL_GPIO_OUTPUT0;
13381         }
13382
13383         /* Force the chip into D0. */
13384         err = tg3_set_power_state(tp, PCI_D0);
13385         if (err) {
13386                 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
13387                 return err;
13388         }
13389
13390         /* Derive initial jumbo mode from MTU assigned in
13391          * ether_setup() via the alloc_etherdev() call
13392          */
13393         if (tp->dev->mtu > ETH_DATA_LEN &&
13394             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13395                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13396
13397         /* Determine WakeOnLan speed to use. */
13398         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13399             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13400             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13401             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13402                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13403         } else {
13404                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13405         }
13406
13407         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13408                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
13409
13410         /* A few boards don't want Ethernet@WireSpeed phy feature */
13411         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13412             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13413              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13414              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13415             (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
13416             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
13417                 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
13418
13419         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13420             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13421                 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
13422         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13423                 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
13424
13425         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13426             !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
13427             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13428             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13429             !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
13430                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13431                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13432                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13433                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13434                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13435                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13436                                 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
13437                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13438                                 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
13439                 } else
13440                         tp->phy_flags |= TG3_PHYFLG_BER_BUG;
13441         }
13442
13443         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13444             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13445                 tp->phy_otp = tg3_read_otp_phycfg(tp);
13446                 if (tp->phy_otp == 0)
13447                         tp->phy_otp = TG3_OTP_DEFAULT;
13448         }
13449
13450         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13451                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13452         else
13453                 tp->mi_mode = MAC_MI_MODE_BASE;
13454
13455         tp->coalesce_mode = 0;
13456         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13457             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13458                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13459
13460         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13461             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13462                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13463
13464         err = tg3_mdio_init(tp);
13465         if (err)
13466                 return err;
13467
13468         /* Initialize data/descriptor byte/word swapping. */
13469         val = tr32(GRC_MODE);
13470         val &= GRC_MODE_HOST_STACKUP;
13471         tw32(GRC_MODE, val | tp->grc_mode);
13472
13473         tg3_switch_clocks(tp);
13474
13475         /* Clear this out for sanity. */
13476         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13477
13478         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13479                               &pci_state_reg);
13480         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13481             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13482                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13483
13484                 if (chiprevid == CHIPREV_ID_5701_A0 ||
13485                     chiprevid == CHIPREV_ID_5701_B0 ||
13486                     chiprevid == CHIPREV_ID_5701_B2 ||
13487                     chiprevid == CHIPREV_ID_5701_B5) {
13488                         void __iomem *sram_base;
13489
13490                         /* Write some dummy words into the SRAM status block
13491                          * area, see if it reads back correctly.  If the return
13492                          * value is bad, force enable the PCIX workaround.
13493                          */
13494                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13495
13496                         writel(0x00000000, sram_base);
13497                         writel(0x00000000, sram_base + 4);
13498                         writel(0xffffffff, sram_base + 4);
13499                         if (readl(sram_base) != 0x00000000)
13500                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13501                 }
13502         }
13503
13504         udelay(50);
13505         tg3_nvram_init(tp);
13506
13507         grc_misc_cfg = tr32(GRC_MISC_CFG);
13508         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13509
13510         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13511             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13512              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13513                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13514
13515         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13516             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13517                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13518         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13519                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13520                                       HOSTCC_MODE_CLRTICK_TXBD);
13521
13522                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13523                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13524                                        tp->misc_host_ctrl);
13525         }
13526
13527         /* Preserve the APE MAC_MODE bits */
13528         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13529                 tp->mac_mode = tr32(MAC_MODE) |
13530                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13531         else
13532                 tp->mac_mode = TG3_DEF_MAC_MODE;
13533
13534         /* these are limited to 10/100 only */
13535         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13536              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13537             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13538              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13539              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13540               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13541               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13542             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13543              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13544               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13545               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13546             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13547             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13548             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
13549             (tp->phy_flags & TG3_PHYFLG_IS_FET))
13550                 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
13551
13552         err = tg3_phy_probe(tp);
13553         if (err) {
13554                 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
13555                 /* ... but do not return immediately ... */
13556                 tg3_mdio_fini(tp);
13557         }
13558
13559         tg3_read_vpd(tp);
13560         tg3_read_fw_ver(tp);
13561
13562         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
13563                 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
13564         } else {
13565                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13566                         tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
13567                 else
13568                         tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
13569         }
13570
13571         /* 5700 {AX,BX} chips have a broken status block link
13572          * change bit implementation, so we must use the
13573          * status register in those cases.
13574          */
13575         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13576                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13577         else
13578                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13579
13580         /* The led_ctrl is set during tg3_phy_probe, here we might
13581          * have to force the link status polling mechanism based
13582          * upon subsystem IDs.
13583          */
13584         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13585             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13586             !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
13587                 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
13588                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13589         }
13590
13591         /* For all SERDES we poll the MAC status register. */
13592         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
13593                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13594         else
13595                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13596
13597         tp->rx_offset = NET_IP_ALIGN + TG3_RX_HEADROOM;
13598         tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
13599         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13600             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
13601                 tp->rx_offset -= NET_IP_ALIGN;
13602 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
13603                 tp->rx_copy_thresh = ~(u16)0;
13604 #endif
13605         }
13606
13607         tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
13608         tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
13609         tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
13610
13611         /* Increment the rx prod index on the rx std ring by at most
13612          * 8 for these chips to workaround hw errata.
13613          */
13614         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13615             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13616             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13617                 tp->rx_std_max_post = 8;
13618
13619         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13620                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13621                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
13622
13623         return err;
13624 }
13625
13626 #ifdef CONFIG_SPARC
13627 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13628 {
13629         struct net_device *dev = tp->dev;
13630         struct pci_dev *pdev = tp->pdev;
13631         struct device_node *dp = pci_device_to_OF_node(pdev);
13632         const unsigned char *addr;
13633         int len;
13634
13635         addr = of_get_property(dp, "local-mac-address", &len);
13636         if (addr && len == 6) {
13637                 memcpy(dev->dev_addr, addr, 6);
13638                 memcpy(dev->perm_addr, dev->dev_addr, 6);
13639                 return 0;
13640         }
13641         return -ENODEV;
13642 }
13643
13644 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13645 {
13646         struct net_device *dev = tp->dev;
13647
13648         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13649         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13650         return 0;
13651 }
13652 #endif
13653
13654 static int __devinit tg3_get_device_address(struct tg3 *tp)
13655 {
13656         struct net_device *dev = tp->dev;
13657         u32 hi, lo, mac_offset;
13658         int addr_ok = 0;
13659
13660 #ifdef CONFIG_SPARC
13661         if (!tg3_get_macaddr_sparc(tp))
13662                 return 0;
13663 #endif
13664
13665         mac_offset = 0x7c;
13666         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13667             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13668                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13669                         mac_offset = 0xcc;
13670                 if (tg3_nvram_lock(tp))
13671                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13672                 else
13673                         tg3_nvram_unlock(tp);
13674         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13675                    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
13676                 if (PCI_FUNC(tp->pdev->devfn) & 1)
13677                         mac_offset = 0xcc;
13678                 if (PCI_FUNC(tp->pdev->devfn) > 1)
13679                         mac_offset += 0x18c;
13680         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13681                 mac_offset = 0x10;
13682
13683         /* First try to get it from MAC address mailbox. */
13684         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13685         if ((hi >> 16) == 0x484b) {
13686                 dev->dev_addr[0] = (hi >>  8) & 0xff;
13687                 dev->dev_addr[1] = (hi >>  0) & 0xff;
13688
13689                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13690                 dev->dev_addr[2] = (lo >> 24) & 0xff;
13691                 dev->dev_addr[3] = (lo >> 16) & 0xff;
13692                 dev->dev_addr[4] = (lo >>  8) & 0xff;
13693                 dev->dev_addr[5] = (lo >>  0) & 0xff;
13694
13695                 /* Some old bootcode may report a 0 MAC address in SRAM */
13696                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13697         }
13698         if (!addr_ok) {
13699                 /* Next, try NVRAM. */
13700                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13701                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13702                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13703                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13704                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13705                 }
13706                 /* Finally just fetch it out of the MAC control regs. */
13707                 else {
13708                         hi = tr32(MAC_ADDR_0_HIGH);
13709                         lo = tr32(MAC_ADDR_0_LOW);
13710
13711                         dev->dev_addr[5] = lo & 0xff;
13712                         dev->dev_addr[4] = (lo >> 8) & 0xff;
13713                         dev->dev_addr[3] = (lo >> 16) & 0xff;
13714                         dev->dev_addr[2] = (lo >> 24) & 0xff;
13715                         dev->dev_addr[1] = hi & 0xff;
13716                         dev->dev_addr[0] = (hi >> 8) & 0xff;
13717                 }
13718         }
13719
13720         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13721 #ifdef CONFIG_SPARC
13722                 if (!tg3_get_default_macaddr_sparc(tp))
13723                         return 0;
13724 #endif
13725                 return -EINVAL;
13726         }
13727         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13728         return 0;
13729 }
13730
13731 #define BOUNDARY_SINGLE_CACHELINE       1
13732 #define BOUNDARY_MULTI_CACHELINE        2
13733
13734 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13735 {
13736         int cacheline_size;
13737         u8 byte;
13738         int goal;
13739
13740         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13741         if (byte == 0)
13742                 cacheline_size = 1024;
13743         else
13744                 cacheline_size = (int) byte * 4;
13745
13746         /* On 5703 and later chips, the boundary bits have no
13747          * effect.
13748          */
13749         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13750             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13751             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13752                 goto out;
13753
13754 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13755         goal = BOUNDARY_MULTI_CACHELINE;
13756 #else
13757 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13758         goal = BOUNDARY_SINGLE_CACHELINE;
13759 #else
13760         goal = 0;
13761 #endif
13762 #endif
13763
13764         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
13765                 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13766                 goto out;
13767         }
13768
13769         if (!goal)
13770                 goto out;
13771
13772         /* PCI controllers on most RISC systems tend to disconnect
13773          * when a device tries to burst across a cache-line boundary.
13774          * Therefore, letting tg3 do so just wastes PCI bandwidth.
13775          *
13776          * Unfortunately, for PCI-E there are only limited
13777          * write-side controls for this, and thus for reads
13778          * we will still get the disconnects.  We'll also waste
13779          * these PCI cycles for both read and write for chips
13780          * other than 5700 and 5701 which do not implement the
13781          * boundary bits.
13782          */
13783         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13784             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13785                 switch (cacheline_size) {
13786                 case 16:
13787                 case 32:
13788                 case 64:
13789                 case 128:
13790                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13791                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13792                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13793                         } else {
13794                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13795                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13796                         }
13797                         break;
13798
13799                 case 256:
13800                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13801                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13802                         break;
13803
13804                 default:
13805                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13806                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13807                         break;
13808                 }
13809         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13810                 switch (cacheline_size) {
13811                 case 16:
13812                 case 32:
13813                 case 64:
13814                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13815                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13816                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13817                                 break;
13818                         }
13819                         /* fallthrough */
13820                 case 128:
13821                 default:
13822                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13823                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13824                         break;
13825                 }
13826         } else {
13827                 switch (cacheline_size) {
13828                 case 16:
13829                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13830                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13831                                         DMA_RWCTRL_WRITE_BNDRY_16);
13832                                 break;
13833                         }
13834                         /* fallthrough */
13835                 case 32:
13836                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13837                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13838                                         DMA_RWCTRL_WRITE_BNDRY_32);
13839                                 break;
13840                         }
13841                         /* fallthrough */
13842                 case 64:
13843                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13844                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13845                                         DMA_RWCTRL_WRITE_BNDRY_64);
13846                                 break;
13847                         }
13848                         /* fallthrough */
13849                 case 128:
13850                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13851                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13852                                         DMA_RWCTRL_WRITE_BNDRY_128);
13853                                 break;
13854                         }
13855                         /* fallthrough */
13856                 case 256:
13857                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
13858                                 DMA_RWCTRL_WRITE_BNDRY_256);
13859                         break;
13860                 case 512:
13861                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
13862                                 DMA_RWCTRL_WRITE_BNDRY_512);
13863                         break;
13864                 case 1024:
13865                 default:
13866                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13867                                 DMA_RWCTRL_WRITE_BNDRY_1024);
13868                         break;
13869                 }
13870         }
13871
13872 out:
13873         return val;
13874 }
13875
13876 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13877 {
13878         struct tg3_internal_buffer_desc test_desc;
13879         u32 sram_dma_descs;
13880         int i, ret;
13881
13882         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13883
13884         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13885         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13886         tw32(RDMAC_STATUS, 0);
13887         tw32(WDMAC_STATUS, 0);
13888
13889         tw32(BUFMGR_MODE, 0);
13890         tw32(FTQ_RESET, 0);
13891
13892         test_desc.addr_hi = ((u64) buf_dma) >> 32;
13893         test_desc.addr_lo = buf_dma & 0xffffffff;
13894         test_desc.nic_mbuf = 0x00002100;
13895         test_desc.len = size;
13896
13897         /*
13898          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13899          * the *second* time the tg3 driver was getting loaded after an
13900          * initial scan.
13901          *
13902          * Broadcom tells me:
13903          *   ...the DMA engine is connected to the GRC block and a DMA
13904          *   reset may affect the GRC block in some unpredictable way...
13905          *   The behavior of resets to individual blocks has not been tested.
13906          *
13907          * Broadcom noted the GRC reset will also reset all sub-components.
13908          */
13909         if (to_device) {
13910                 test_desc.cqid_sqid = (13 << 8) | 2;
13911
13912                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13913                 udelay(40);
13914         } else {
13915                 test_desc.cqid_sqid = (16 << 8) | 7;
13916
13917                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13918                 udelay(40);
13919         }
13920         test_desc.flags = 0x00000005;
13921
13922         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13923                 u32 val;
13924
13925                 val = *(((u32 *)&test_desc) + i);
13926                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13927                                        sram_dma_descs + (i * sizeof(u32)));
13928                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13929         }
13930         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13931
13932         if (to_device)
13933                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13934         else
13935                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13936
13937         ret = -ENODEV;
13938         for (i = 0; i < 40; i++) {
13939                 u32 val;
13940
13941                 if (to_device)
13942                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13943                 else
13944                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13945                 if ((val & 0xffff) == sram_dma_descs) {
13946                         ret = 0;
13947                         break;
13948                 }
13949
13950                 udelay(100);
13951         }
13952
13953         return ret;
13954 }
13955
13956 #define TEST_BUFFER_SIZE        0x2000
13957
13958 static int __devinit tg3_test_dma(struct tg3 *tp)
13959 {
13960         dma_addr_t buf_dma;
13961         u32 *buf, saved_dma_rwctrl;
13962         int ret = 0;
13963
13964         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13965         if (!buf) {
13966                 ret = -ENOMEM;
13967                 goto out_nofree;
13968         }
13969
13970         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13971                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13972
13973         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13974
13975         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13976                 goto out;
13977
13978         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13979                 /* DMA read watermark not used on PCIE */
13980                 tp->dma_rwctrl |= 0x00180000;
13981         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
13982                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13983                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
13984                         tp->dma_rwctrl |= 0x003f0000;
13985                 else
13986                         tp->dma_rwctrl |= 0x003f000f;
13987         } else {
13988                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13989                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13990                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
13991                         u32 read_water = 0x7;
13992
13993                         /* If the 5704 is behind the EPB bridge, we can
13994                          * do the less restrictive ONE_DMA workaround for
13995                          * better performance.
13996                          */
13997                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13998                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13999                                 tp->dma_rwctrl |= 0x8000;
14000                         else if (ccval == 0x6 || ccval == 0x7)
14001                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
14002
14003                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
14004                                 read_water = 4;
14005                         /* Set bit 23 to enable PCIX hw bug fix */
14006                         tp->dma_rwctrl |=
14007                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
14008                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
14009                                 (1 << 23);
14010                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
14011                         /* 5780 always in PCIX mode */
14012                         tp->dma_rwctrl |= 0x00144000;
14013                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
14014                         /* 5714 always in PCIX mode */
14015                         tp->dma_rwctrl |= 0x00148000;
14016                 } else {
14017                         tp->dma_rwctrl |= 0x001b000f;
14018                 }
14019         }
14020
14021         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14022             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14023                 tp->dma_rwctrl &= 0xfffffff0;
14024
14025         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14026             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
14027                 /* Remove this if it causes problems for some boards. */
14028                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
14029
14030                 /* On 5700/5701 chips, we need to set this bit.
14031                  * Otherwise the chip will issue cacheline transactions
14032                  * to streamable DMA memory with not all the byte
14033                  * enables turned on.  This is an error on several
14034                  * RISC PCI controllers, in particular sparc64.
14035                  *
14036                  * On 5703/5704 chips, this bit has been reassigned
14037                  * a different meaning.  In particular, it is used
14038                  * on those chips to enable a PCI-X workaround.
14039                  */
14040                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
14041         }
14042
14043         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14044
14045 #if 0
14046         /* Unneeded, already done by tg3_get_invariants.  */
14047         tg3_switch_clocks(tp);
14048 #endif
14049
14050         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14051             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14052                 goto out;
14053
14054         /* It is best to perform DMA test with maximum write burst size
14055          * to expose the 5700/5701 write DMA bug.
14056          */
14057         saved_dma_rwctrl = tp->dma_rwctrl;
14058         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14059         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14060
14061         while (1) {
14062                 u32 *p = buf, i;
14063
14064                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14065                         p[i] = i;
14066
14067                 /* Send the buffer to the chip. */
14068                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14069                 if (ret) {
14070                         dev_err(&tp->pdev->dev,
14071                                 "%s: Buffer write failed. err = %d\n",
14072                                 __func__, ret);
14073                         break;
14074                 }
14075
14076 #if 0
14077                 /* validate data reached card RAM correctly. */
14078                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14079                         u32 val;
14080                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
14081                         if (le32_to_cpu(val) != p[i]) {
14082                                 dev_err(&tp->pdev->dev,
14083                                         "%s: Buffer corrupted on device! "
14084                                         "(%d != %d)\n", __func__, val, i);
14085                                 /* ret = -ENODEV here? */
14086                         }
14087                         p[i] = 0;
14088                 }
14089 #endif
14090                 /* Now read it back. */
14091                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14092                 if (ret) {
14093                         dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
14094                                 "err = %d\n", __func__, ret);
14095                         break;
14096                 }
14097
14098                 /* Verify it. */
14099                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14100                         if (p[i] == i)
14101                                 continue;
14102
14103                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14104                             DMA_RWCTRL_WRITE_BNDRY_16) {
14105                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14106                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14107                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14108                                 break;
14109                         } else {
14110                                 dev_err(&tp->pdev->dev,
14111                                         "%s: Buffer corrupted on read back! "
14112                                         "(%d != %d)\n", __func__, p[i], i);
14113                                 ret = -ENODEV;
14114                                 goto out;
14115                         }
14116                 }
14117
14118                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14119                         /* Success. */
14120                         ret = 0;
14121                         break;
14122                 }
14123         }
14124         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14125             DMA_RWCTRL_WRITE_BNDRY_16) {
14126                 static struct pci_device_id dma_wait_state_chipsets[] = {
14127                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14128                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14129                         { },
14130                 };
14131
14132                 /* DMA test passed without adjusting DMA boundary,
14133                  * now look for chipsets that are known to expose the
14134                  * DMA bug without failing the test.
14135                  */
14136                 if (pci_dev_present(dma_wait_state_chipsets)) {
14137                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14138                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14139                 } else {
14140                         /* Safe to use the calculated DMA boundary. */
14141                         tp->dma_rwctrl = saved_dma_rwctrl;
14142                 }
14143
14144                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14145         }
14146
14147 out:
14148         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14149 out_nofree:
14150         return ret;
14151 }
14152
14153 static void __devinit tg3_init_link_config(struct tg3 *tp)
14154 {
14155         tp->link_config.advertising =
14156                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14157                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14158                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14159                  ADVERTISED_Autoneg | ADVERTISED_MII);
14160         tp->link_config.speed = SPEED_INVALID;
14161         tp->link_config.duplex = DUPLEX_INVALID;
14162         tp->link_config.autoneg = AUTONEG_ENABLE;
14163         tp->link_config.active_speed = SPEED_INVALID;
14164         tp->link_config.active_duplex = DUPLEX_INVALID;
14165         tp->link_config.orig_speed = SPEED_INVALID;
14166         tp->link_config.orig_duplex = DUPLEX_INVALID;
14167         tp->link_config.orig_autoneg = AUTONEG_INVALID;
14168 }
14169
14170 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14171 {
14172         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
14173                 tp->bufmgr_config.mbuf_read_dma_low_water =
14174                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14175                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14176                         DEFAULT_MB_MACRX_LOW_WATER_57765;
14177                 tp->bufmgr_config.mbuf_high_water =
14178                         DEFAULT_MB_HIGH_WATER_57765;
14179
14180                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14181                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14182                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14183                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14184                 tp->bufmgr_config.mbuf_high_water_jumbo =
14185                         DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14186         } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14187                 tp->bufmgr_config.mbuf_read_dma_low_water =
14188                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14189                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14190                         DEFAULT_MB_MACRX_LOW_WATER_5705;
14191                 tp->bufmgr_config.mbuf_high_water =
14192                         DEFAULT_MB_HIGH_WATER_5705;
14193                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14194                         tp->bufmgr_config.mbuf_mac_rx_low_water =
14195                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
14196                         tp->bufmgr_config.mbuf_high_water =
14197                                 DEFAULT_MB_HIGH_WATER_5906;
14198                 }
14199
14200                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14201                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14202                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14203                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14204                 tp->bufmgr_config.mbuf_high_water_jumbo =
14205                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14206         } else {
14207                 tp->bufmgr_config.mbuf_read_dma_low_water =
14208                         DEFAULT_MB_RDMA_LOW_WATER;
14209                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14210                         DEFAULT_MB_MACRX_LOW_WATER;
14211                 tp->bufmgr_config.mbuf_high_water =
14212                         DEFAULT_MB_HIGH_WATER;
14213
14214                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14215                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14216                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14217                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14218                 tp->bufmgr_config.mbuf_high_water_jumbo =
14219                         DEFAULT_MB_HIGH_WATER_JUMBO;
14220         }
14221
14222         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14223         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14224 }
14225
14226 static char * __devinit tg3_phy_string(struct tg3 *tp)
14227 {
14228         switch (tp->phy_id & TG3_PHY_ID_MASK) {
14229         case TG3_PHY_ID_BCM5400:        return "5400";
14230         case TG3_PHY_ID_BCM5401:        return "5401";
14231         case TG3_PHY_ID_BCM5411:        return "5411";
14232         case TG3_PHY_ID_BCM5701:        return "5701";
14233         case TG3_PHY_ID_BCM5703:        return "5703";
14234         case TG3_PHY_ID_BCM5704:        return "5704";
14235         case TG3_PHY_ID_BCM5705:        return "5705";
14236         case TG3_PHY_ID_BCM5750:        return "5750";
14237         case TG3_PHY_ID_BCM5752:        return "5752";
14238         case TG3_PHY_ID_BCM5714:        return "5714";
14239         case TG3_PHY_ID_BCM5780:        return "5780";
14240         case TG3_PHY_ID_BCM5755:        return "5755";
14241         case TG3_PHY_ID_BCM5787:        return "5787";
14242         case TG3_PHY_ID_BCM5784:        return "5784";
14243         case TG3_PHY_ID_BCM5756:        return "5722/5756";
14244         case TG3_PHY_ID_BCM5906:        return "5906";
14245         case TG3_PHY_ID_BCM5761:        return "5761";
14246         case TG3_PHY_ID_BCM5718C:       return "5718C";
14247         case TG3_PHY_ID_BCM5718S:       return "5718S";
14248         case TG3_PHY_ID_BCM57765:       return "57765";
14249         case TG3_PHY_ID_BCM5719C:       return "5719C";
14250         case TG3_PHY_ID_BCM8002:        return "8002/serdes";
14251         case 0:                 return "serdes";
14252         default:                return "unknown";
14253         }
14254 }
14255
14256 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14257 {
14258         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14259                 strcpy(str, "PCI Express");
14260                 return str;
14261         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14262                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14263
14264                 strcpy(str, "PCIX:");
14265
14266                 if ((clock_ctrl == 7) ||
14267                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14268                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14269                         strcat(str, "133MHz");
14270                 else if (clock_ctrl == 0)
14271                         strcat(str, "33MHz");
14272                 else if (clock_ctrl == 2)
14273                         strcat(str, "50MHz");
14274                 else if (clock_ctrl == 4)
14275                         strcat(str, "66MHz");
14276                 else if (clock_ctrl == 6)
14277                         strcat(str, "100MHz");
14278         } else {
14279                 strcpy(str, "PCI:");
14280                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14281                         strcat(str, "66MHz");
14282                 else
14283                         strcat(str, "33MHz");
14284         }
14285         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14286                 strcat(str, ":32-bit");
14287         else
14288                 strcat(str, ":64-bit");
14289         return str;
14290 }
14291
14292 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14293 {
14294         struct pci_dev *peer;
14295         unsigned int func, devnr = tp->pdev->devfn & ~7;
14296
14297         for (func = 0; func < 8; func++) {
14298                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14299                 if (peer && peer != tp->pdev)
14300                         break;
14301                 pci_dev_put(peer);
14302         }
14303         /* 5704 can be configured in single-port mode, set peer to
14304          * tp->pdev in that case.
14305          */
14306         if (!peer) {
14307                 peer = tp->pdev;
14308                 return peer;
14309         }
14310
14311         /*
14312          * We don't need to keep the refcount elevated; there's no way
14313          * to remove one half of this device without removing the other
14314          */
14315         pci_dev_put(peer);
14316
14317         return peer;
14318 }
14319
14320 static void __devinit tg3_init_coal(struct tg3 *tp)
14321 {
14322         struct ethtool_coalesce *ec = &tp->coal;
14323
14324         memset(ec, 0, sizeof(*ec));
14325         ec->cmd = ETHTOOL_GCOALESCE;
14326         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14327         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14328         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14329         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14330         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14331         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14332         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14333         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14334         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14335
14336         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14337                                  HOSTCC_MODE_CLRTICK_TXBD)) {
14338                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14339                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14340                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14341                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14342         }
14343
14344         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14345                 ec->rx_coalesce_usecs_irq = 0;
14346                 ec->tx_coalesce_usecs_irq = 0;
14347                 ec->stats_block_coalesce_usecs = 0;
14348         }
14349 }
14350
14351 static const struct net_device_ops tg3_netdev_ops = {
14352         .ndo_open               = tg3_open,
14353         .ndo_stop               = tg3_close,
14354         .ndo_start_xmit         = tg3_start_xmit,
14355         .ndo_get_stats64        = tg3_get_stats64,
14356         .ndo_validate_addr      = eth_validate_addr,
14357         .ndo_set_multicast_list = tg3_set_rx_mode,
14358         .ndo_set_mac_address    = tg3_set_mac_addr,
14359         .ndo_do_ioctl           = tg3_ioctl,
14360         .ndo_tx_timeout         = tg3_tx_timeout,
14361         .ndo_change_mtu         = tg3_change_mtu,
14362 #if TG3_VLAN_TAG_USED
14363         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14364 #endif
14365 #ifdef CONFIG_NET_POLL_CONTROLLER
14366         .ndo_poll_controller    = tg3_poll_controller,
14367 #endif
14368 };
14369
14370 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14371         .ndo_open               = tg3_open,
14372         .ndo_stop               = tg3_close,
14373         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
14374         .ndo_get_stats64        = tg3_get_stats64,
14375         .ndo_validate_addr      = eth_validate_addr,
14376         .ndo_set_multicast_list = tg3_set_rx_mode,
14377         .ndo_set_mac_address    = tg3_set_mac_addr,
14378         .ndo_do_ioctl           = tg3_ioctl,
14379         .ndo_tx_timeout         = tg3_tx_timeout,
14380         .ndo_change_mtu         = tg3_change_mtu,
14381 #if TG3_VLAN_TAG_USED
14382         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14383 #endif
14384 #ifdef CONFIG_NET_POLL_CONTROLLER
14385         .ndo_poll_controller    = tg3_poll_controller,
14386 #endif
14387 };
14388
14389 static int __devinit tg3_init_one(struct pci_dev *pdev,
14390                                   const struct pci_device_id *ent)
14391 {
14392         struct net_device *dev;
14393         struct tg3 *tp;
14394         int i, err, pm_cap;
14395         u32 sndmbx, rcvmbx, intmbx;
14396         char str[40];
14397         u64 dma_mask, persist_dma_mask;
14398
14399         printk_once(KERN_INFO "%s\n", version);
14400
14401         err = pci_enable_device(pdev);
14402         if (err) {
14403                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
14404                 return err;
14405         }
14406
14407         err = pci_request_regions(pdev, DRV_MODULE_NAME);
14408         if (err) {
14409                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
14410                 goto err_out_disable_pdev;
14411         }
14412
14413         pci_set_master(pdev);
14414
14415         /* Find power-management capability. */
14416         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14417         if (pm_cap == 0) {
14418                 dev_err(&pdev->dev,
14419                         "Cannot find Power Management capability, aborting\n");
14420                 err = -EIO;
14421                 goto err_out_free_res;
14422         }
14423
14424         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14425         if (!dev) {
14426                 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
14427                 err = -ENOMEM;
14428                 goto err_out_free_res;
14429         }
14430
14431         SET_NETDEV_DEV(dev, &pdev->dev);
14432
14433 #if TG3_VLAN_TAG_USED
14434         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14435 #endif
14436
14437         tp = netdev_priv(dev);
14438         tp->pdev = pdev;
14439         tp->dev = dev;
14440         tp->pm_cap = pm_cap;
14441         tp->rx_mode = TG3_DEF_RX_MODE;
14442         tp->tx_mode = TG3_DEF_TX_MODE;
14443
14444         if (tg3_debug > 0)
14445                 tp->msg_enable = tg3_debug;
14446         else
14447                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14448
14449         /* The word/byte swap controls here control register access byte
14450          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
14451          * setting below.
14452          */
14453         tp->misc_host_ctrl =
14454                 MISC_HOST_CTRL_MASK_PCI_INT |
14455                 MISC_HOST_CTRL_WORD_SWAP |
14456                 MISC_HOST_CTRL_INDIR_ACCESS |
14457                 MISC_HOST_CTRL_PCISTATE_RW;
14458
14459         /* The NONFRM (non-frame) byte/word swap controls take effect
14460          * on descriptor entries, anything which isn't packet data.
14461          *
14462          * The StrongARM chips on the board (one for tx, one for rx)
14463          * are running in big-endian mode.
14464          */
14465         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14466                         GRC_MODE_WSWAP_NONFRM_DATA);
14467 #ifdef __BIG_ENDIAN
14468         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14469 #endif
14470         spin_lock_init(&tp->lock);
14471         spin_lock_init(&tp->indirect_lock);
14472         INIT_WORK(&tp->reset_task, tg3_reset_task);
14473
14474         tp->regs = pci_ioremap_bar(pdev, BAR_0);
14475         if (!tp->regs) {
14476                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
14477                 err = -ENOMEM;
14478                 goto err_out_free_dev;
14479         }
14480
14481         tg3_init_link_config(tp);
14482
14483         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14484         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14485
14486         dev->ethtool_ops = &tg3_ethtool_ops;
14487         dev->watchdog_timeo = TG3_TX_TIMEOUT;
14488         dev->irq = pdev->irq;
14489
14490         err = tg3_get_invariants(tp);
14491         if (err) {
14492                 dev_err(&pdev->dev,
14493                         "Problem fetching invariants of chip, aborting\n");
14494                 goto err_out_iounmap;
14495         }
14496
14497         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14498             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
14499             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
14500                 dev->netdev_ops = &tg3_netdev_ops;
14501         else
14502                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14503
14504
14505         /* The EPB bridge inside 5714, 5715, and 5780 and any
14506          * device behind the EPB cannot support DMA addresses > 40-bit.
14507          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14508          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14509          * do DMA address check in tg3_start_xmit().
14510          */
14511         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14512                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14513         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14514                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14515 #ifdef CONFIG_HIGHMEM
14516                 dma_mask = DMA_BIT_MASK(64);
14517 #endif
14518         } else
14519                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14520
14521         /* Configure DMA attributes. */
14522         if (dma_mask > DMA_BIT_MASK(32)) {
14523                 err = pci_set_dma_mask(pdev, dma_mask);
14524                 if (!err) {
14525                         dev->features |= NETIF_F_HIGHDMA;
14526                         err = pci_set_consistent_dma_mask(pdev,
14527                                                           persist_dma_mask);
14528                         if (err < 0) {
14529                                 dev_err(&pdev->dev, "Unable to obtain 64 bit "
14530                                         "DMA for consistent allocations\n");
14531                                 goto err_out_iounmap;
14532                         }
14533                 }
14534         }
14535         if (err || dma_mask == DMA_BIT_MASK(32)) {
14536                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14537                 if (err) {
14538                         dev_err(&pdev->dev,
14539                                 "No usable DMA configuration, aborting\n");
14540                         goto err_out_iounmap;
14541                 }
14542         }
14543
14544         tg3_init_bufmgr_config(tp);
14545
14546         /* Selectively allow TSO based on operating conditions */
14547         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14548             (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14549                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14550         else {
14551                 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14552                 tp->fw_needed = NULL;
14553         }
14554
14555         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14556                 tp->fw_needed = FIRMWARE_TG3;
14557
14558         /* TSO is on by default on chips that support hardware TSO.
14559          * Firmware TSO on older chips gives lower performance, so it
14560          * is off by default, but can be enabled using ethtool.
14561          */
14562         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14563             (dev->features & NETIF_F_IP_CSUM)) {
14564                 dev->features |= NETIF_F_TSO;
14565                 vlan_features_add(dev, NETIF_F_TSO);
14566         }
14567         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14568             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14569                 if (dev->features & NETIF_F_IPV6_CSUM) {
14570                         dev->features |= NETIF_F_TSO6;
14571                         vlan_features_add(dev, NETIF_F_TSO6);
14572                 }
14573                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14574                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14575                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14576                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14577                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14578                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
14579                         dev->features |= NETIF_F_TSO_ECN;
14580                         vlan_features_add(dev, NETIF_F_TSO_ECN);
14581                 }
14582         }
14583
14584         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14585             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14586             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14587                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14588                 tp->rx_pending = 63;
14589         }
14590
14591         err = tg3_get_device_address(tp);
14592         if (err) {
14593                 dev_err(&pdev->dev,
14594                         "Could not obtain valid ethernet address, aborting\n");
14595                 goto err_out_iounmap;
14596         }
14597
14598         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14599                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14600                 if (!tp->aperegs) {
14601                         dev_err(&pdev->dev,
14602                                 "Cannot map APE registers, aborting\n");
14603                         err = -ENOMEM;
14604                         goto err_out_iounmap;
14605                 }
14606
14607                 tg3_ape_lock_init(tp);
14608
14609                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14610                         tg3_read_dash_ver(tp);
14611         }
14612
14613         /*
14614          * Reset chip in case UNDI or EFI driver did not shutdown
14615          * DMA self test will enable WDMAC and we'll see (spurious)
14616          * pending DMA on the PCI bus at that point.
14617          */
14618         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14619             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14620                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14621                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14622         }
14623
14624         err = tg3_test_dma(tp);
14625         if (err) {
14626                 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
14627                 goto err_out_apeunmap;
14628         }
14629
14630         /* flow control autonegotiation is default behavior */
14631         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14632         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14633
14634         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14635         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14636         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14637         for (i = 0; i < tp->irq_max; i++) {
14638                 struct tg3_napi *tnapi = &tp->napi[i];
14639
14640                 tnapi->tp = tp;
14641                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14642
14643                 tnapi->int_mbox = intmbx;
14644                 if (i < 4)
14645                         intmbx += 0x8;
14646                 else
14647                         intmbx += 0x4;
14648
14649                 tnapi->consmbox = rcvmbx;
14650                 tnapi->prodmbox = sndmbx;
14651
14652                 if (i)
14653                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14654                 else
14655                         tnapi->coal_now = HOSTCC_MODE_NOW;
14656
14657                 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14658                         break;
14659
14660                 /*
14661                  * If we support MSIX, we'll be using RSS.  If we're using
14662                  * RSS, the first vector only handles link interrupts and the
14663                  * remaining vectors handle rx and tx interrupts.  Reuse the
14664                  * mailbox values for the next iteration.  The values we setup
14665                  * above are still useful for the single vectored mode.
14666                  */
14667                 if (!i)
14668                         continue;
14669
14670                 rcvmbx += 0x8;
14671
14672                 if (sndmbx & 0x4)
14673                         sndmbx -= 0x4;
14674                 else
14675                         sndmbx += 0xc;
14676         }
14677
14678         tg3_init_coal(tp);
14679
14680         pci_set_drvdata(pdev, dev);
14681
14682         err = register_netdev(dev);
14683         if (err) {
14684                 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
14685                 goto err_out_apeunmap;
14686         }
14687
14688         netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14689                     tp->board_part_number,
14690                     tp->pci_chip_rev_id,
14691                     tg3_bus_string(tp, str),
14692                     dev->dev_addr);
14693
14694         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
14695                 struct phy_device *phydev;
14696                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14697                 netdev_info(dev,
14698                             "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14699                             phydev->drv->name, dev_name(&phydev->dev));
14700         } else {
14701                 char *ethtype;
14702
14703                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
14704                         ethtype = "10/100Base-TX";
14705                 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
14706                         ethtype = "1000Base-SX";
14707                 else
14708                         ethtype = "10/100/1000Base-T";
14709
14710                 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
14711                             "(WireSpeed[%d])\n", tg3_phy_string(tp), ethtype,
14712                           (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0);
14713         }
14714
14715         netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14716                     (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14717                     (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14718                     (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
14719                     (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14720                     (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14721         netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14722                     tp->dma_rwctrl,
14723                     pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
14724                     ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
14725
14726         return 0;
14727
14728 err_out_apeunmap:
14729         if (tp->aperegs) {
14730                 iounmap(tp->aperegs);
14731                 tp->aperegs = NULL;
14732         }
14733
14734 err_out_iounmap:
14735         if (tp->regs) {
14736                 iounmap(tp->regs);
14737                 tp->regs = NULL;
14738         }
14739
14740 err_out_free_dev:
14741         free_netdev(dev);
14742
14743 err_out_free_res:
14744         pci_release_regions(pdev);
14745
14746 err_out_disable_pdev:
14747         pci_disable_device(pdev);
14748         pci_set_drvdata(pdev, NULL);
14749         return err;
14750 }
14751
14752 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14753 {
14754         struct net_device *dev = pci_get_drvdata(pdev);
14755
14756         if (dev) {
14757                 struct tg3 *tp = netdev_priv(dev);
14758
14759                 if (tp->fw)
14760                         release_firmware(tp->fw);
14761
14762                 flush_scheduled_work();
14763
14764                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14765                         tg3_phy_fini(tp);
14766                         tg3_mdio_fini(tp);
14767                 }
14768
14769                 unregister_netdev(dev);
14770                 if (tp->aperegs) {
14771                         iounmap(tp->aperegs);
14772                         tp->aperegs = NULL;
14773                 }
14774                 if (tp->regs) {
14775                         iounmap(tp->regs);
14776                         tp->regs = NULL;
14777                 }
14778                 free_netdev(dev);
14779                 pci_release_regions(pdev);
14780                 pci_disable_device(pdev);
14781                 pci_set_drvdata(pdev, NULL);
14782         }
14783 }
14784
14785 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14786 {
14787         struct net_device *dev = pci_get_drvdata(pdev);
14788         struct tg3 *tp = netdev_priv(dev);
14789         pci_power_t target_state;
14790         int err;
14791
14792         /* PCI register 4 needs to be saved whether netif_running() or not.
14793          * MSI address and data need to be saved if using MSI and
14794          * netif_running().
14795          */
14796         pci_save_state(pdev);
14797
14798         if (!netif_running(dev))
14799                 return 0;
14800
14801         flush_scheduled_work();
14802         tg3_phy_stop(tp);
14803         tg3_netif_stop(tp);
14804
14805         del_timer_sync(&tp->timer);
14806
14807         tg3_full_lock(tp, 1);
14808         tg3_disable_ints(tp);
14809         tg3_full_unlock(tp);
14810
14811         netif_device_detach(dev);
14812
14813         tg3_full_lock(tp, 0);
14814         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14815         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14816         tg3_full_unlock(tp);
14817
14818         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14819
14820         err = tg3_set_power_state(tp, target_state);
14821         if (err) {
14822                 int err2;
14823
14824                 tg3_full_lock(tp, 0);
14825
14826                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14827                 err2 = tg3_restart_hw(tp, 1);
14828                 if (err2)
14829                         goto out;
14830
14831                 tp->timer.expires = jiffies + tp->timer_offset;
14832                 add_timer(&tp->timer);
14833
14834                 netif_device_attach(dev);
14835                 tg3_netif_start(tp);
14836
14837 out:
14838                 tg3_full_unlock(tp);
14839
14840                 if (!err2)
14841                         tg3_phy_start(tp);
14842         }
14843
14844         return err;
14845 }
14846
14847 static int tg3_resume(struct pci_dev *pdev)
14848 {
14849         struct net_device *dev = pci_get_drvdata(pdev);
14850         struct tg3 *tp = netdev_priv(dev);
14851         int err;
14852
14853         pci_restore_state(tp->pdev);
14854
14855         if (!netif_running(dev))
14856                 return 0;
14857
14858         err = tg3_set_power_state(tp, PCI_D0);
14859         if (err)
14860                 return err;
14861
14862         netif_device_attach(dev);
14863
14864         tg3_full_lock(tp, 0);
14865
14866         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14867         err = tg3_restart_hw(tp, 1);
14868         if (err)
14869                 goto out;
14870
14871         tp->timer.expires = jiffies + tp->timer_offset;
14872         add_timer(&tp->timer);
14873
14874         tg3_netif_start(tp);
14875
14876 out:
14877         tg3_full_unlock(tp);
14878
14879         if (!err)
14880                 tg3_phy_start(tp);
14881
14882         return err;
14883 }
14884
14885 static struct pci_driver tg3_driver = {
14886         .name           = DRV_MODULE_NAME,
14887         .id_table       = tg3_pci_tbl,
14888         .probe          = tg3_init_one,
14889         .remove         = __devexit_p(tg3_remove_one),
14890         .suspend        = tg3_suspend,
14891         .resume         = tg3_resume
14892 };
14893
14894 static int __init tg3_init(void)
14895 {
14896         return pci_register_driver(&tg3_driver);
14897 }
14898
14899 static void __exit tg3_cleanup(void)
14900 {
14901         pci_unregister_driver(&tg3_driver);
14902 }
14903
14904 module_init(tg3_init);
14905 module_exit(tg3_cleanup);