2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2010 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
28 #include <linux/init.h>
29 #include <linux/ioport.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/ethtool.h>
35 #include <linux/mii.h>
36 #include <linux/phy.h>
37 #include <linux/brcmphy.h>
38 #include <linux/if_vlan.h>
40 #include <linux/tcp.h>
41 #include <linux/workqueue.h>
42 #include <linux/prefetch.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/firmware.h>
46 #include <net/checksum.h>
49 #include <asm/system.h>
51 #include <asm/byteorder.h>
52 #include <asm/uaccess.h>
55 #include <asm/idprom.h>
62 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
63 #define TG3_VLAN_TAG_USED 1
65 #define TG3_VLAN_TAG_USED 0
70 #define DRV_MODULE_NAME "tg3"
72 #define TG3_MIN_NUM 112
73 #define DRV_MODULE_VERSION \
74 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
75 #define DRV_MODULE_RELDATE "July 11, 2010"
77 #define TG3_DEF_MAC_MODE 0
78 #define TG3_DEF_RX_MODE 0
79 #define TG3_DEF_TX_MODE 0
80 #define TG3_DEF_MSG_ENABLE \
90 /* length of time before we decide the hardware is borked,
91 * and dev->tx_timeout() should be called to fix the problem
93 #define TG3_TX_TIMEOUT (5 * HZ)
95 /* hardware minimum and maximum for a single frame's data payload */
96 #define TG3_MIN_MTU 60
97 #define TG3_MAX_MTU(tp) \
98 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
100 /* These numbers seem to be hard coded in the NIC firmware somehow.
101 * You can't change the ring sizes, but you can change where you place
102 * them in the NIC onboard memory.
104 #define TG3_RX_RING_SIZE 512
105 #define TG3_DEF_RX_RING_PENDING 200
106 #define TG3_RX_JUMBO_RING_SIZE 256
107 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
108 #define TG3_RSS_INDIR_TBL_SIZE 128
110 /* Do not place this n-ring entries value into the tp struct itself,
111 * we really want to expose these constants to GCC so that modulo et
112 * al. operations are done with shifts and masks instead of with
113 * hw multiply/modulo instructions. Another solution would be to
114 * replace things like '% foo' with '& (foo - 1)'.
116 #define TG3_RX_RCB_RING_SIZE(tp) \
117 (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
118 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
120 #define TG3_TX_RING_SIZE 512
121 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
123 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
125 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
126 TG3_RX_JUMBO_RING_SIZE)
127 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
128 TG3_RX_RCB_RING_SIZE(tp))
129 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
131 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
133 #define TG3_RX_DMA_ALIGN 16
134 #define TG3_RX_HEADROOM ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
136 #define TG3_DMA_BYTE_ENAB 64
138 #define TG3_RX_STD_DMA_SZ 1536
139 #define TG3_RX_JMB_DMA_SZ 9046
141 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
143 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
144 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
146 #define TG3_RX_STD_BUFF_RING_SIZE \
147 (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
149 #define TG3_RX_JMB_BUFF_RING_SIZE \
150 (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
152 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
153 * that are at least dword aligned when used in PCIX mode. The driver
154 * works around this bug by double copying the packet. This workaround
155 * is built into the normal double copy length check for efficiency.
157 * However, the double copy is only necessary on those architectures
158 * where unaligned memory accesses are inefficient. For those architectures
159 * where unaligned memory accesses incur little penalty, we can reintegrate
160 * the 5701 in the normal rx path. Doing so saves a device structure
161 * dereference by hardcoding the double copy threshold in place.
163 #define TG3_RX_COPY_THRESHOLD 256
164 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
165 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
167 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
170 /* minimum number of free TX descriptors required to wake up TX process */
171 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
173 #define TG3_RAW_IP_ALIGN 2
175 /* number of ETHTOOL_GSTATS u64's */
176 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
178 #define TG3_NUM_TEST 6
180 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
182 #define FIRMWARE_TG3 "tigon/tg3.bin"
183 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
184 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
186 static char version[] __devinitdata =
187 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
189 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
190 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
191 MODULE_LICENSE("GPL");
192 MODULE_VERSION(DRV_MODULE_VERSION);
193 MODULE_FIRMWARE(FIRMWARE_TG3);
194 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
195 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
197 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
198 module_param(tg3_debug, int, 0);
199 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
201 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
260 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
261 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
264 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
267 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
268 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
275 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
276 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
277 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
278 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
279 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
280 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
281 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
285 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
287 static const struct {
288 const char string[ETH_GSTRING_LEN];
289 } ethtool_stats_keys[TG3_NUM_STATS] = {
292 { "rx_ucast_packets" },
293 { "rx_mcast_packets" },
294 { "rx_bcast_packets" },
296 { "rx_align_errors" },
297 { "rx_xon_pause_rcvd" },
298 { "rx_xoff_pause_rcvd" },
299 { "rx_mac_ctrl_rcvd" },
300 { "rx_xoff_entered" },
301 { "rx_frame_too_long_errors" },
303 { "rx_undersize_packets" },
304 { "rx_in_length_errors" },
305 { "rx_out_length_errors" },
306 { "rx_64_or_less_octet_packets" },
307 { "rx_65_to_127_octet_packets" },
308 { "rx_128_to_255_octet_packets" },
309 { "rx_256_to_511_octet_packets" },
310 { "rx_512_to_1023_octet_packets" },
311 { "rx_1024_to_1522_octet_packets" },
312 { "rx_1523_to_2047_octet_packets" },
313 { "rx_2048_to_4095_octet_packets" },
314 { "rx_4096_to_8191_octet_packets" },
315 { "rx_8192_to_9022_octet_packets" },
322 { "tx_flow_control" },
324 { "tx_single_collisions" },
325 { "tx_mult_collisions" },
327 { "tx_excessive_collisions" },
328 { "tx_late_collisions" },
329 { "tx_collide_2times" },
330 { "tx_collide_3times" },
331 { "tx_collide_4times" },
332 { "tx_collide_5times" },
333 { "tx_collide_6times" },
334 { "tx_collide_7times" },
335 { "tx_collide_8times" },
336 { "tx_collide_9times" },
337 { "tx_collide_10times" },
338 { "tx_collide_11times" },
339 { "tx_collide_12times" },
340 { "tx_collide_13times" },
341 { "tx_collide_14times" },
342 { "tx_collide_15times" },
343 { "tx_ucast_packets" },
344 { "tx_mcast_packets" },
345 { "tx_bcast_packets" },
346 { "tx_carrier_sense_errors" },
350 { "dma_writeq_full" },
351 { "dma_write_prioq_full" },
355 { "rx_threshold_hit" },
357 { "dma_readq_full" },
358 { "dma_read_prioq_full" },
359 { "tx_comp_queue_full" },
361 { "ring_set_send_prod_index" },
362 { "ring_status_update" },
364 { "nic_avoided_irqs" },
365 { "nic_tx_threshold_hit" }
368 static const struct {
369 const char string[ETH_GSTRING_LEN];
370 } ethtool_test_keys[TG3_NUM_TEST] = {
371 { "nvram test (online) " },
372 { "link test (online) " },
373 { "register test (offline)" },
374 { "memory test (offline)" },
375 { "loopback test (offline)" },
376 { "interrupt test (offline)" },
379 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
381 writel(val, tp->regs + off);
384 static u32 tg3_read32(struct tg3 *tp, u32 off)
386 return readl(tp->regs + off);
389 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
391 writel(val, tp->aperegs + off);
394 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
396 return readl(tp->aperegs + off);
399 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
403 spin_lock_irqsave(&tp->indirect_lock, flags);
404 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
405 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
406 spin_unlock_irqrestore(&tp->indirect_lock, flags);
409 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
411 writel(val, tp->regs + off);
412 readl(tp->regs + off);
415 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
420 spin_lock_irqsave(&tp->indirect_lock, flags);
421 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
422 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
423 spin_unlock_irqrestore(&tp->indirect_lock, flags);
427 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
431 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
432 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
433 TG3_64BIT_REG_LOW, val);
436 if (off == TG3_RX_STD_PROD_IDX_REG) {
437 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
438 TG3_64BIT_REG_LOW, val);
442 spin_lock_irqsave(&tp->indirect_lock, flags);
443 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
444 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
445 spin_unlock_irqrestore(&tp->indirect_lock, flags);
447 /* In indirect mode when disabling interrupts, we also need
448 * to clear the interrupt bit in the GRC local ctrl register.
450 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
452 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
453 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
457 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
462 spin_lock_irqsave(&tp->indirect_lock, flags);
463 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
464 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
465 spin_unlock_irqrestore(&tp->indirect_lock, flags);
469 /* usec_wait specifies the wait time in usec when writing to certain registers
470 * where it is unsafe to read back the register without some delay.
471 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
472 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
474 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
476 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
477 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
478 /* Non-posted methods */
479 tp->write32(tp, off, val);
482 tg3_write32(tp, off, val);
487 /* Wait again after the read for the posted method to guarantee that
488 * the wait time is met.
494 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
496 tp->write32_mbox(tp, off, val);
497 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
498 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
499 tp->read32_mbox(tp, off);
502 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
504 void __iomem *mbox = tp->regs + off;
506 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
508 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
512 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
514 return readl(tp->regs + off + GRCMBOX_BASE);
517 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
519 writel(val, tp->regs + off + GRCMBOX_BASE);
522 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
523 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
524 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
525 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
526 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
528 #define tw32(reg, val) tp->write32(tp, reg, val)
529 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
530 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
531 #define tr32(reg) tp->read32(tp, reg)
533 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
537 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
538 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
541 spin_lock_irqsave(&tp->indirect_lock, flags);
542 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
543 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
544 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
546 /* Always leave this as zero. */
547 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
549 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
550 tw32_f(TG3PCI_MEM_WIN_DATA, val);
552 /* Always leave this as zero. */
553 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
555 spin_unlock_irqrestore(&tp->indirect_lock, flags);
558 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
562 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
563 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
568 spin_lock_irqsave(&tp->indirect_lock, flags);
569 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
570 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
571 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
573 /* Always leave this as zero. */
574 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
576 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
577 *val = tr32(TG3PCI_MEM_WIN_DATA);
579 /* Always leave this as zero. */
580 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
582 spin_unlock_irqrestore(&tp->indirect_lock, flags);
585 static void tg3_ape_lock_init(struct tg3 *tp)
590 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
591 regbase = TG3_APE_LOCK_GRANT;
593 regbase = TG3_APE_PER_LOCK_GRANT;
595 /* Make sure the driver hasn't any stale locks. */
596 for (i = 0; i < 8; i++)
597 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
600 static int tg3_ape_lock(struct tg3 *tp, int locknum)
604 u32 status, req, gnt;
606 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
610 case TG3_APE_LOCK_GRC:
611 case TG3_APE_LOCK_MEM:
617 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
618 req = TG3_APE_LOCK_REQ;
619 gnt = TG3_APE_LOCK_GRANT;
621 req = TG3_APE_PER_LOCK_REQ;
622 gnt = TG3_APE_PER_LOCK_GRANT;
627 tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
629 /* Wait for up to 1 millisecond to acquire lock. */
630 for (i = 0; i < 100; i++) {
631 status = tg3_ape_read32(tp, gnt + off);
632 if (status == APE_LOCK_GRANT_DRIVER)
637 if (status != APE_LOCK_GRANT_DRIVER) {
638 /* Revoke the lock request. */
639 tg3_ape_write32(tp, gnt + off,
640 APE_LOCK_GRANT_DRIVER);
648 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
652 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
656 case TG3_APE_LOCK_GRC:
657 case TG3_APE_LOCK_MEM:
663 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
664 gnt = TG3_APE_LOCK_GRANT;
666 gnt = TG3_APE_PER_LOCK_GRANT;
668 tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
671 static void tg3_disable_ints(struct tg3 *tp)
675 tw32(TG3PCI_MISC_HOST_CTRL,
676 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
677 for (i = 0; i < tp->irq_max; i++)
678 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
681 static void tg3_enable_ints(struct tg3 *tp)
688 tw32(TG3PCI_MISC_HOST_CTRL,
689 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
691 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
692 for (i = 0; i < tp->irq_cnt; i++) {
693 struct tg3_napi *tnapi = &tp->napi[i];
695 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
696 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
697 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
699 tp->coal_now |= tnapi->coal_now;
702 /* Force an initial interrupt */
703 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
704 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
705 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
707 tw32(HOSTCC_MODE, tp->coal_now);
709 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
712 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
714 struct tg3 *tp = tnapi->tp;
715 struct tg3_hw_status *sblk = tnapi->hw_status;
716 unsigned int work_exists = 0;
718 /* check for phy events */
719 if (!(tp->tg3_flags &
720 (TG3_FLAG_USE_LINKCHG_REG |
721 TG3_FLAG_POLL_SERDES))) {
722 if (sblk->status & SD_STATUS_LINK_CHG)
725 /* check for RX/TX work to do */
726 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
727 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
734 * similar to tg3_enable_ints, but it accurately determines whether there
735 * is new work pending and can return without flushing the PIO write
736 * which reenables interrupts
738 static void tg3_int_reenable(struct tg3_napi *tnapi)
740 struct tg3 *tp = tnapi->tp;
742 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
745 /* When doing tagged status, this work check is unnecessary.
746 * The last_tag we write above tells the chip which piece of
747 * work we've completed.
749 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
751 tw32(HOSTCC_MODE, tp->coalesce_mode |
752 HOSTCC_MODE_ENABLE | tnapi->coal_now);
755 static void tg3_napi_disable(struct tg3 *tp)
759 for (i = tp->irq_cnt - 1; i >= 0; i--)
760 napi_disable(&tp->napi[i].napi);
763 static void tg3_napi_enable(struct tg3 *tp)
767 for (i = 0; i < tp->irq_cnt; i++)
768 napi_enable(&tp->napi[i].napi);
771 static inline void tg3_netif_stop(struct tg3 *tp)
773 tp->dev->trans_start = jiffies; /* prevent tx timeout */
774 tg3_napi_disable(tp);
775 netif_tx_disable(tp->dev);
778 static inline void tg3_netif_start(struct tg3 *tp)
780 /* NOTE: unconditional netif_tx_wake_all_queues is only
781 * appropriate so long as all callers are assured to
782 * have free tx slots (such as after tg3_init_hw)
784 netif_tx_wake_all_queues(tp->dev);
787 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
791 static void tg3_switch_clocks(struct tg3 *tp)
796 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
797 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
800 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
802 orig_clock_ctrl = clock_ctrl;
803 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
804 CLOCK_CTRL_CLKRUN_OENABLE |
806 tp->pci_clock_ctrl = clock_ctrl;
808 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
809 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
810 tw32_wait_f(TG3PCI_CLOCK_CTRL,
811 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
813 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
814 tw32_wait_f(TG3PCI_CLOCK_CTRL,
816 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
818 tw32_wait_f(TG3PCI_CLOCK_CTRL,
819 clock_ctrl | (CLOCK_CTRL_ALTCLK),
822 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
825 #define PHY_BUSY_LOOPS 5000
827 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
833 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
835 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
841 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
842 MI_COM_PHY_ADDR_MASK);
843 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
844 MI_COM_REG_ADDR_MASK);
845 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
847 tw32_f(MAC_MI_COM, frame_val);
849 loops = PHY_BUSY_LOOPS;
852 frame_val = tr32(MAC_MI_COM);
854 if ((frame_val & MI_COM_BUSY) == 0) {
856 frame_val = tr32(MAC_MI_COM);
864 *val = frame_val & MI_COM_DATA_MASK;
868 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
869 tw32_f(MAC_MI_MODE, tp->mi_mode);
876 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
882 if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
883 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
886 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
888 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
892 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
893 MI_COM_PHY_ADDR_MASK);
894 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
895 MI_COM_REG_ADDR_MASK);
896 frame_val |= (val & MI_COM_DATA_MASK);
897 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
899 tw32_f(MAC_MI_COM, frame_val);
901 loops = PHY_BUSY_LOOPS;
904 frame_val = tr32(MAC_MI_COM);
905 if ((frame_val & MI_COM_BUSY) == 0) {
907 frame_val = tr32(MAC_MI_COM);
917 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
918 tw32_f(MAC_MI_MODE, tp->mi_mode);
925 static int tg3_bmcr_reset(struct tg3 *tp)
930 /* OK, reset it, and poll the BMCR_RESET bit until it
931 * clears or we time out.
933 phy_control = BMCR_RESET;
934 err = tg3_writephy(tp, MII_BMCR, phy_control);
940 err = tg3_readphy(tp, MII_BMCR, &phy_control);
944 if ((phy_control & BMCR_RESET) == 0) {
956 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
958 struct tg3 *tp = bp->priv;
961 spin_lock_bh(&tp->lock);
963 if (tg3_readphy(tp, reg, &val))
966 spin_unlock_bh(&tp->lock);
971 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
973 struct tg3 *tp = bp->priv;
976 spin_lock_bh(&tp->lock);
978 if (tg3_writephy(tp, reg, val))
981 spin_unlock_bh(&tp->lock);
986 static int tg3_mdio_reset(struct mii_bus *bp)
991 static void tg3_mdio_config_5785(struct tg3 *tp)
994 struct phy_device *phydev;
996 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
997 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
998 case PHY_ID_BCM50610:
999 case PHY_ID_BCM50610M:
1000 val = MAC_PHYCFG2_50610_LED_MODES;
1002 case PHY_ID_BCMAC131:
1003 val = MAC_PHYCFG2_AC131_LED_MODES;
1005 case PHY_ID_RTL8211C:
1006 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1008 case PHY_ID_RTL8201E:
1009 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1015 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1016 tw32(MAC_PHYCFG2, val);
1018 val = tr32(MAC_PHYCFG1);
1019 val &= ~(MAC_PHYCFG1_RGMII_INT |
1020 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1021 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1022 tw32(MAC_PHYCFG1, val);
1027 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
1028 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1029 MAC_PHYCFG2_FMODE_MASK_MASK |
1030 MAC_PHYCFG2_GMODE_MASK_MASK |
1031 MAC_PHYCFG2_ACT_MASK_MASK |
1032 MAC_PHYCFG2_QUAL_MASK_MASK |
1033 MAC_PHYCFG2_INBAND_ENABLE;
1035 tw32(MAC_PHYCFG2, val);
1037 val = tr32(MAC_PHYCFG1);
1038 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1039 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1040 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1041 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1042 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1043 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1044 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1046 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1047 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1048 tw32(MAC_PHYCFG1, val);
1050 val = tr32(MAC_EXT_RGMII_MODE);
1051 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1052 MAC_RGMII_MODE_RX_QUALITY |
1053 MAC_RGMII_MODE_RX_ACTIVITY |
1054 MAC_RGMII_MODE_RX_ENG_DET |
1055 MAC_RGMII_MODE_TX_ENABLE |
1056 MAC_RGMII_MODE_TX_LOWPWR |
1057 MAC_RGMII_MODE_TX_RESET);
1058 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1059 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1060 val |= MAC_RGMII_MODE_RX_INT_B |
1061 MAC_RGMII_MODE_RX_QUALITY |
1062 MAC_RGMII_MODE_RX_ACTIVITY |
1063 MAC_RGMII_MODE_RX_ENG_DET;
1064 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1065 val |= MAC_RGMII_MODE_TX_ENABLE |
1066 MAC_RGMII_MODE_TX_LOWPWR |
1067 MAC_RGMII_MODE_TX_RESET;
1069 tw32(MAC_EXT_RGMII_MODE, val);
1072 static void tg3_mdio_start(struct tg3 *tp)
1074 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1075 tw32_f(MAC_MI_MODE, tp->mi_mode);
1078 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1079 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1080 tg3_mdio_config_5785(tp);
1083 static int tg3_mdio_init(struct tg3 *tp)
1087 struct phy_device *phydev;
1089 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1090 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
1093 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1095 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1096 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1098 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1099 TG3_CPMU_PHY_STRAP_IS_SERDES;
1103 tp->phy_addr = TG3_PHY_MII_ADDR;
1107 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1108 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1111 tp->mdio_bus = mdiobus_alloc();
1112 if (tp->mdio_bus == NULL)
1115 tp->mdio_bus->name = "tg3 mdio bus";
1116 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1117 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1118 tp->mdio_bus->priv = tp;
1119 tp->mdio_bus->parent = &tp->pdev->dev;
1120 tp->mdio_bus->read = &tg3_mdio_read;
1121 tp->mdio_bus->write = &tg3_mdio_write;
1122 tp->mdio_bus->reset = &tg3_mdio_reset;
1123 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1124 tp->mdio_bus->irq = &tp->mdio_irq[0];
1126 for (i = 0; i < PHY_MAX_ADDR; i++)
1127 tp->mdio_bus->irq[i] = PHY_POLL;
1129 /* The bus registration will look for all the PHYs on the mdio bus.
1130 * Unfortunately, it does not ensure the PHY is powered up before
1131 * accessing the PHY ID registers. A chip reset is the
1132 * quickest way to bring the device back to an operational state..
1134 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN))
1137 i = mdiobus_register(tp->mdio_bus);
1139 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1140 mdiobus_free(tp->mdio_bus);
1144 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1146 if (!phydev || !phydev->drv) {
1147 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1148 mdiobus_unregister(tp->mdio_bus);
1149 mdiobus_free(tp->mdio_bus);
1153 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1154 case PHY_ID_BCM57780:
1155 phydev->interface = PHY_INTERFACE_MODE_GMII;
1156 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1158 case PHY_ID_BCM50610:
1159 case PHY_ID_BCM50610M:
1160 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1161 PHY_BRCM_RX_REFCLK_UNUSED |
1162 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1163 PHY_BRCM_AUTO_PWRDWN_ENABLE;
1164 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1165 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1166 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1167 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1168 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1169 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1171 case PHY_ID_RTL8211C:
1172 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1174 case PHY_ID_RTL8201E:
1175 case PHY_ID_BCMAC131:
1176 phydev->interface = PHY_INTERFACE_MODE_MII;
1177 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1178 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1182 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1184 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1185 tg3_mdio_config_5785(tp);
1190 static void tg3_mdio_fini(struct tg3 *tp)
1192 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1193 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1194 mdiobus_unregister(tp->mdio_bus);
1195 mdiobus_free(tp->mdio_bus);
1199 /* tp->lock is held. */
1200 static inline void tg3_generate_fw_event(struct tg3 *tp)
1204 val = tr32(GRC_RX_CPU_EVENT);
1205 val |= GRC_RX_CPU_DRIVER_EVENT;
1206 tw32_f(GRC_RX_CPU_EVENT, val);
1208 tp->last_event_jiffies = jiffies;
1211 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1213 /* tp->lock is held. */
1214 static void tg3_wait_for_event_ack(struct tg3 *tp)
1217 unsigned int delay_cnt;
1220 /* If enough time has passed, no wait is necessary. */
1221 time_remain = (long)(tp->last_event_jiffies + 1 +
1222 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1224 if (time_remain < 0)
1227 /* Check if we can shorten the wait time. */
1228 delay_cnt = jiffies_to_usecs(time_remain);
1229 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1230 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1231 delay_cnt = (delay_cnt >> 3) + 1;
1233 for (i = 0; i < delay_cnt; i++) {
1234 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1240 /* tp->lock is held. */
1241 static void tg3_ump_link_report(struct tg3 *tp)
1246 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1247 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1250 tg3_wait_for_event_ack(tp);
1252 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1254 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1257 if (!tg3_readphy(tp, MII_BMCR, ®))
1259 if (!tg3_readphy(tp, MII_BMSR, ®))
1260 val |= (reg & 0xffff);
1261 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1264 if (!tg3_readphy(tp, MII_ADVERTISE, ®))
1266 if (!tg3_readphy(tp, MII_LPA, ®))
1267 val |= (reg & 0xffff);
1268 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1271 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1272 if (!tg3_readphy(tp, MII_CTRL1000, ®))
1274 if (!tg3_readphy(tp, MII_STAT1000, ®))
1275 val |= (reg & 0xffff);
1277 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1279 if (!tg3_readphy(tp, MII_PHYADDR, ®))
1283 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1285 tg3_generate_fw_event(tp);
1288 static void tg3_link_report(struct tg3 *tp)
1290 if (!netif_carrier_ok(tp->dev)) {
1291 netif_info(tp, link, tp->dev, "Link is down\n");
1292 tg3_ump_link_report(tp);
1293 } else if (netif_msg_link(tp)) {
1294 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1295 (tp->link_config.active_speed == SPEED_1000 ?
1297 (tp->link_config.active_speed == SPEED_100 ?
1299 (tp->link_config.active_duplex == DUPLEX_FULL ?
1302 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1303 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1305 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1307 tg3_ump_link_report(tp);
1311 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1315 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1316 miireg = ADVERTISE_PAUSE_CAP;
1317 else if (flow_ctrl & FLOW_CTRL_TX)
1318 miireg = ADVERTISE_PAUSE_ASYM;
1319 else if (flow_ctrl & FLOW_CTRL_RX)
1320 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1327 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1331 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1332 miireg = ADVERTISE_1000XPAUSE;
1333 else if (flow_ctrl & FLOW_CTRL_TX)
1334 miireg = ADVERTISE_1000XPSE_ASYM;
1335 else if (flow_ctrl & FLOW_CTRL_RX)
1336 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1343 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1347 if (lcladv & ADVERTISE_1000XPAUSE) {
1348 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1349 if (rmtadv & LPA_1000XPAUSE)
1350 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1351 else if (rmtadv & LPA_1000XPAUSE_ASYM)
1354 if (rmtadv & LPA_1000XPAUSE)
1355 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1357 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1358 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1365 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1369 u32 old_rx_mode = tp->rx_mode;
1370 u32 old_tx_mode = tp->tx_mode;
1372 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1373 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1375 autoneg = tp->link_config.autoneg;
1377 if (autoneg == AUTONEG_ENABLE &&
1378 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1379 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1380 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1382 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1384 flowctrl = tp->link_config.flowctrl;
1386 tp->link_config.active_flowctrl = flowctrl;
1388 if (flowctrl & FLOW_CTRL_RX)
1389 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1391 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1393 if (old_rx_mode != tp->rx_mode)
1394 tw32_f(MAC_RX_MODE, tp->rx_mode);
1396 if (flowctrl & FLOW_CTRL_TX)
1397 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1399 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1401 if (old_tx_mode != tp->tx_mode)
1402 tw32_f(MAC_TX_MODE, tp->tx_mode);
1405 static void tg3_adjust_link(struct net_device *dev)
1407 u8 oldflowctrl, linkmesg = 0;
1408 u32 mac_mode, lcl_adv, rmt_adv;
1409 struct tg3 *tp = netdev_priv(dev);
1410 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1412 spin_lock_bh(&tp->lock);
1414 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1415 MAC_MODE_HALF_DUPLEX);
1417 oldflowctrl = tp->link_config.active_flowctrl;
1423 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1424 mac_mode |= MAC_MODE_PORT_MODE_MII;
1425 else if (phydev->speed == SPEED_1000 ||
1426 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1427 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1429 mac_mode |= MAC_MODE_PORT_MODE_MII;
1431 if (phydev->duplex == DUPLEX_HALF)
1432 mac_mode |= MAC_MODE_HALF_DUPLEX;
1434 lcl_adv = tg3_advert_flowctrl_1000T(
1435 tp->link_config.flowctrl);
1438 rmt_adv = LPA_PAUSE_CAP;
1439 if (phydev->asym_pause)
1440 rmt_adv |= LPA_PAUSE_ASYM;
1443 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1445 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1447 if (mac_mode != tp->mac_mode) {
1448 tp->mac_mode = mac_mode;
1449 tw32_f(MAC_MODE, tp->mac_mode);
1453 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1454 if (phydev->speed == SPEED_10)
1456 MAC_MI_STAT_10MBPS_MODE |
1457 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1459 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1462 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1463 tw32(MAC_TX_LENGTHS,
1464 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1465 (6 << TX_LENGTHS_IPG_SHIFT) |
1466 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1468 tw32(MAC_TX_LENGTHS,
1469 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1470 (6 << TX_LENGTHS_IPG_SHIFT) |
1471 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1473 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1474 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1475 phydev->speed != tp->link_config.active_speed ||
1476 phydev->duplex != tp->link_config.active_duplex ||
1477 oldflowctrl != tp->link_config.active_flowctrl)
1480 tp->link_config.active_speed = phydev->speed;
1481 tp->link_config.active_duplex = phydev->duplex;
1483 spin_unlock_bh(&tp->lock);
1486 tg3_link_report(tp);
1489 static int tg3_phy_init(struct tg3 *tp)
1491 struct phy_device *phydev;
1493 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1496 /* Bring the PHY back to a known state. */
1499 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1501 /* Attach the MAC to the PHY. */
1502 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1503 phydev->dev_flags, phydev->interface);
1504 if (IS_ERR(phydev)) {
1505 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1506 return PTR_ERR(phydev);
1509 /* Mask with MAC supported features. */
1510 switch (phydev->interface) {
1511 case PHY_INTERFACE_MODE_GMII:
1512 case PHY_INTERFACE_MODE_RGMII:
1513 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1514 phydev->supported &= (PHY_GBIT_FEATURES |
1516 SUPPORTED_Asym_Pause);
1520 case PHY_INTERFACE_MODE_MII:
1521 phydev->supported &= (PHY_BASIC_FEATURES |
1523 SUPPORTED_Asym_Pause);
1526 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1530 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1532 phydev->advertising = phydev->supported;
1537 static void tg3_phy_start(struct tg3 *tp)
1539 struct phy_device *phydev;
1541 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1544 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1546 if (tp->link_config.phy_is_low_power) {
1547 tp->link_config.phy_is_low_power = 0;
1548 phydev->speed = tp->link_config.orig_speed;
1549 phydev->duplex = tp->link_config.orig_duplex;
1550 phydev->autoneg = tp->link_config.orig_autoneg;
1551 phydev->advertising = tp->link_config.orig_advertising;
1556 phy_start_aneg(phydev);
1559 static void tg3_phy_stop(struct tg3 *tp)
1561 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1564 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1567 static void tg3_phy_fini(struct tg3 *tp)
1569 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1570 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1571 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1575 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1579 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1581 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1586 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1590 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1593 tg3_writephy(tp, MII_TG3_FET_TEST,
1594 phytest | MII_TG3_FET_SHADOW_EN);
1595 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1597 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1599 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1600 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1602 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1606 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1610 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1611 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1612 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1613 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1616 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1617 tg3_phy_fet_toggle_apd(tp, enable);
1621 reg = MII_TG3_MISC_SHDW_WREN |
1622 MII_TG3_MISC_SHDW_SCR5_SEL |
1623 MII_TG3_MISC_SHDW_SCR5_LPED |
1624 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1625 MII_TG3_MISC_SHDW_SCR5_SDTL |
1626 MII_TG3_MISC_SHDW_SCR5_C125OE;
1627 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1628 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1630 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1633 reg = MII_TG3_MISC_SHDW_WREN |
1634 MII_TG3_MISC_SHDW_APD_SEL |
1635 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1637 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1639 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1642 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1646 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1647 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1650 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1653 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1654 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1656 tg3_writephy(tp, MII_TG3_FET_TEST,
1657 ephy | MII_TG3_FET_SHADOW_EN);
1658 if (!tg3_readphy(tp, reg, &phy)) {
1660 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1662 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1663 tg3_writephy(tp, reg, phy);
1665 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1668 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1669 MII_TG3_AUXCTL_SHDWSEL_MISC;
1670 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1671 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1673 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1675 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1676 phy |= MII_TG3_AUXCTL_MISC_WREN;
1677 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1682 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1686 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1689 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1690 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1691 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1692 (val | (1 << 15) | (1 << 4)));
1695 static void tg3_phy_apply_otp(struct tg3 *tp)
1704 /* Enable SM_DSP clock and tx 6dB coding. */
1705 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1706 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1707 MII_TG3_AUXCTL_ACTL_TX_6DB;
1708 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1710 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1711 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1712 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1714 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1715 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1716 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1718 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1719 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1720 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1722 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1723 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1725 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1726 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1728 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1729 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1730 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1732 /* Turn off SM_DSP clock. */
1733 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1734 MII_TG3_AUXCTL_ACTL_TX_6DB;
1735 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1738 static int tg3_wait_macro_done(struct tg3 *tp)
1745 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1746 if ((tmp32 & 0x1000) == 0)
1756 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1758 static const u32 test_pat[4][6] = {
1759 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1760 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1761 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1762 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1766 for (chan = 0; chan < 4; chan++) {
1769 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1770 (chan * 0x2000) | 0x0200);
1771 tg3_writephy(tp, 0x16, 0x0002);
1773 for (i = 0; i < 6; i++)
1774 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1777 tg3_writephy(tp, 0x16, 0x0202);
1778 if (tg3_wait_macro_done(tp)) {
1783 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1784 (chan * 0x2000) | 0x0200);
1785 tg3_writephy(tp, 0x16, 0x0082);
1786 if (tg3_wait_macro_done(tp)) {
1791 tg3_writephy(tp, 0x16, 0x0802);
1792 if (tg3_wait_macro_done(tp)) {
1797 for (i = 0; i < 6; i += 2) {
1800 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1801 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1802 tg3_wait_macro_done(tp)) {
1808 if (low != test_pat[chan][i] ||
1809 high != test_pat[chan][i+1]) {
1810 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1811 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1812 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1822 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1826 for (chan = 0; chan < 4; chan++) {
1829 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1830 (chan * 0x2000) | 0x0200);
1831 tg3_writephy(tp, 0x16, 0x0002);
1832 for (i = 0; i < 6; i++)
1833 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1834 tg3_writephy(tp, 0x16, 0x0202);
1835 if (tg3_wait_macro_done(tp))
1842 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1844 u32 reg32, phy9_orig;
1845 int retries, do_phy_reset, err;
1851 err = tg3_bmcr_reset(tp);
1857 /* Disable transmitter and interrupt. */
1858 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
1862 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1864 /* Set full-duplex, 1000 mbps. */
1865 tg3_writephy(tp, MII_BMCR,
1866 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1868 /* Set to master mode. */
1869 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1872 tg3_writephy(tp, MII_TG3_CTRL,
1873 (MII_TG3_CTRL_AS_MASTER |
1874 MII_TG3_CTRL_ENABLE_AS_MASTER));
1876 /* Enable SM_DSP_CLOCK and 6dB. */
1877 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1879 /* Block the PHY control access. */
1880 tg3_phydsp_write(tp, 0x8005, 0x0800);
1882 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1885 } while (--retries);
1887 err = tg3_phy_reset_chanpat(tp);
1891 tg3_phydsp_write(tp, 0x8005, 0x0000);
1893 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1894 tg3_writephy(tp, 0x16, 0x0000);
1896 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1897 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1898 /* Set Extended packet length bit for jumbo frames */
1899 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1901 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1904 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1906 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) {
1908 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1915 /* This will reset the tigon3 PHY if there is no valid
1916 * link unless the FORCE argument is non-zero.
1918 static int tg3_phy_reset(struct tg3 *tp)
1924 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1927 val = tr32(GRC_MISC_CFG);
1928 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1931 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1932 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1936 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1937 netif_carrier_off(tp->dev);
1938 tg3_link_report(tp);
1941 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1942 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1943 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1944 err = tg3_phy_reset_5703_4_5(tp);
1951 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1952 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1953 cpmuctrl = tr32(TG3_CPMU_CTRL);
1954 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1956 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1959 err = tg3_bmcr_reset(tp);
1963 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1966 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1967 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1969 tw32(TG3_CPMU_CTRL, cpmuctrl);
1972 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1973 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1976 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1977 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1978 CPMU_LSPD_1000MB_MACCLK_12_5) {
1979 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1981 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1985 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1986 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1987 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES))
1990 tg3_phy_apply_otp(tp);
1992 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1993 tg3_phy_toggle_apd(tp, true);
1995 tg3_phy_toggle_apd(tp, false);
1998 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1999 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2000 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2001 tg3_phydsp_write(tp, 0x000a, 0x0323);
2002 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2004 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
2005 tg3_writephy(tp, 0x1c, 0x8d68);
2006 tg3_writephy(tp, 0x1c, 0x8d68);
2008 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
2009 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2010 tg3_phydsp_write(tp, 0x000a, 0x310b);
2011 tg3_phydsp_write(tp, 0x201f, 0x9506);
2012 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2013 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2014 } else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
2015 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2016 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2017 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
2018 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2019 tg3_writephy(tp, MII_TG3_TEST1,
2020 MII_TG3_TEST1_TRIM_EN | 0x4);
2022 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2023 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2025 /* Set Extended packet length bit (bit 14) on all chips that */
2026 /* support jumbo frames */
2027 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2028 /* Cannot do read-modify-write on 5401 */
2029 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2030 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2033 /* Set bit 14 with read-modify-write to preserve other bits */
2034 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2035 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
2036 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
2039 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2040 * jumbo frames transmission.
2042 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2045 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
2046 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2047 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2050 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2051 /* adjust output voltage */
2052 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2055 tg3_phy_toggle_automdix(tp, 1);
2056 tg3_phy_set_wirespeed(tp);
2060 static void tg3_frob_aux_power(struct tg3 *tp)
2062 struct tg3 *tp_peer = tp;
2064 /* The GPIOs do something completely different on 57765. */
2065 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2066 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2067 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2070 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2071 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2072 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2073 struct net_device *dev_peer;
2075 dev_peer = pci_get_drvdata(tp->pdev_peer);
2076 /* remove_one() may have been run on the peer. */
2080 tp_peer = netdev_priv(dev_peer);
2083 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2084 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2085 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2086 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2087 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2088 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2089 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2090 (GRC_LCLCTRL_GPIO_OE0 |
2091 GRC_LCLCTRL_GPIO_OE1 |
2092 GRC_LCLCTRL_GPIO_OE2 |
2093 GRC_LCLCTRL_GPIO_OUTPUT0 |
2094 GRC_LCLCTRL_GPIO_OUTPUT1),
2096 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2097 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2098 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2099 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2100 GRC_LCLCTRL_GPIO_OE1 |
2101 GRC_LCLCTRL_GPIO_OE2 |
2102 GRC_LCLCTRL_GPIO_OUTPUT0 |
2103 GRC_LCLCTRL_GPIO_OUTPUT1 |
2105 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2107 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2108 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2110 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2111 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2114 u32 grc_local_ctrl = 0;
2116 if (tp_peer != tp &&
2117 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2120 /* Workaround to prevent overdrawing Amps. */
2121 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2123 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2124 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2125 grc_local_ctrl, 100);
2128 /* On 5753 and variants, GPIO2 cannot be used. */
2129 no_gpio2 = tp->nic_sram_data_cfg &
2130 NIC_SRAM_DATA_CFG_NO_GPIO2;
2132 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2133 GRC_LCLCTRL_GPIO_OE1 |
2134 GRC_LCLCTRL_GPIO_OE2 |
2135 GRC_LCLCTRL_GPIO_OUTPUT1 |
2136 GRC_LCLCTRL_GPIO_OUTPUT2;
2138 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2139 GRC_LCLCTRL_GPIO_OUTPUT2);
2141 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2142 grc_local_ctrl, 100);
2144 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2146 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2147 grc_local_ctrl, 100);
2150 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2151 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2152 grc_local_ctrl, 100);
2156 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2157 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2158 if (tp_peer != tp &&
2159 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2162 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2163 (GRC_LCLCTRL_GPIO_OE1 |
2164 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2166 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2167 GRC_LCLCTRL_GPIO_OE1, 100);
2169 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2170 (GRC_LCLCTRL_GPIO_OE1 |
2171 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2176 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2178 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2180 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2181 if (speed != SPEED_10)
2183 } else if (speed == SPEED_10)
2189 static int tg3_setup_phy(struct tg3 *, int);
2191 #define RESET_KIND_SHUTDOWN 0
2192 #define RESET_KIND_INIT 1
2193 #define RESET_KIND_SUSPEND 2
2195 static void tg3_write_sig_post_reset(struct tg3 *, int);
2196 static int tg3_halt_cpu(struct tg3 *, u32);
2198 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2202 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2203 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2204 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2205 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2208 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2209 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2210 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2215 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2217 val = tr32(GRC_MISC_CFG);
2218 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2221 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2223 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2226 tg3_writephy(tp, MII_ADVERTISE, 0);
2227 tg3_writephy(tp, MII_BMCR,
2228 BMCR_ANENABLE | BMCR_ANRESTART);
2230 tg3_writephy(tp, MII_TG3_FET_TEST,
2231 phytest | MII_TG3_FET_SHADOW_EN);
2232 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2233 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2235 MII_TG3_FET_SHDW_AUXMODE4,
2238 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2241 } else if (do_low_power) {
2242 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2243 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2245 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2246 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2247 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2248 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2249 MII_TG3_AUXCTL_PCTL_VREG_11V);
2252 /* The PHY should not be powered down on some chips because
2255 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2256 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2257 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2258 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2261 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2262 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2263 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2264 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2265 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2266 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2269 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2272 /* tp->lock is held. */
2273 static int tg3_nvram_lock(struct tg3 *tp)
2275 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2278 if (tp->nvram_lock_cnt == 0) {
2279 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2280 for (i = 0; i < 8000; i++) {
2281 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2286 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2290 tp->nvram_lock_cnt++;
2295 /* tp->lock is held. */
2296 static void tg3_nvram_unlock(struct tg3 *tp)
2298 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2299 if (tp->nvram_lock_cnt > 0)
2300 tp->nvram_lock_cnt--;
2301 if (tp->nvram_lock_cnt == 0)
2302 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2306 /* tp->lock is held. */
2307 static void tg3_enable_nvram_access(struct tg3 *tp)
2309 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2310 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2311 u32 nvaccess = tr32(NVRAM_ACCESS);
2313 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2317 /* tp->lock is held. */
2318 static void tg3_disable_nvram_access(struct tg3 *tp)
2320 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2321 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2322 u32 nvaccess = tr32(NVRAM_ACCESS);
2324 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2328 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2329 u32 offset, u32 *val)
2334 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2337 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2338 EEPROM_ADDR_DEVID_MASK |
2340 tw32(GRC_EEPROM_ADDR,
2342 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2343 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2344 EEPROM_ADDR_ADDR_MASK) |
2345 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2347 for (i = 0; i < 1000; i++) {
2348 tmp = tr32(GRC_EEPROM_ADDR);
2350 if (tmp & EEPROM_ADDR_COMPLETE)
2354 if (!(tmp & EEPROM_ADDR_COMPLETE))
2357 tmp = tr32(GRC_EEPROM_DATA);
2360 * The data will always be opposite the native endian
2361 * format. Perform a blind byteswap to compensate.
2368 #define NVRAM_CMD_TIMEOUT 10000
2370 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2374 tw32(NVRAM_CMD, nvram_cmd);
2375 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2377 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2383 if (i == NVRAM_CMD_TIMEOUT)
2389 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2391 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2392 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2393 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2394 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2395 (tp->nvram_jedecnum == JEDEC_ATMEL))
2397 addr = ((addr / tp->nvram_pagesize) <<
2398 ATMEL_AT45DB0X1B_PAGE_POS) +
2399 (addr % tp->nvram_pagesize);
2404 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2406 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2407 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2408 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2409 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2410 (tp->nvram_jedecnum == JEDEC_ATMEL))
2412 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2413 tp->nvram_pagesize) +
2414 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2419 /* NOTE: Data read in from NVRAM is byteswapped according to
2420 * the byteswapping settings for all other register accesses.
2421 * tg3 devices are BE devices, so on a BE machine, the data
2422 * returned will be exactly as it is seen in NVRAM. On a LE
2423 * machine, the 32-bit value will be byteswapped.
2425 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2429 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2430 return tg3_nvram_read_using_eeprom(tp, offset, val);
2432 offset = tg3_nvram_phys_addr(tp, offset);
2434 if (offset > NVRAM_ADDR_MSK)
2437 ret = tg3_nvram_lock(tp);
2441 tg3_enable_nvram_access(tp);
2443 tw32(NVRAM_ADDR, offset);
2444 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2445 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2448 *val = tr32(NVRAM_RDDATA);
2450 tg3_disable_nvram_access(tp);
2452 tg3_nvram_unlock(tp);
2457 /* Ensures NVRAM data is in bytestream format. */
2458 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2461 int res = tg3_nvram_read(tp, offset, &v);
2463 *val = cpu_to_be32(v);
2467 /* tp->lock is held. */
2468 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2470 u32 addr_high, addr_low;
2473 addr_high = ((tp->dev->dev_addr[0] << 8) |
2474 tp->dev->dev_addr[1]);
2475 addr_low = ((tp->dev->dev_addr[2] << 24) |
2476 (tp->dev->dev_addr[3] << 16) |
2477 (tp->dev->dev_addr[4] << 8) |
2478 (tp->dev->dev_addr[5] << 0));
2479 for (i = 0; i < 4; i++) {
2480 if (i == 1 && skip_mac_1)
2482 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2483 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2486 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2487 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2488 for (i = 0; i < 12; i++) {
2489 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2490 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2494 addr_high = (tp->dev->dev_addr[0] +
2495 tp->dev->dev_addr[1] +
2496 tp->dev->dev_addr[2] +
2497 tp->dev->dev_addr[3] +
2498 tp->dev->dev_addr[4] +
2499 tp->dev->dev_addr[5]) &
2500 TX_BACKOFF_SEED_MASK;
2501 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2504 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2507 bool device_should_wake, do_low_power;
2509 /* Make sure register accesses (indirect or otherwise)
2510 * will function correctly.
2512 pci_write_config_dword(tp->pdev,
2513 TG3PCI_MISC_HOST_CTRL,
2514 tp->misc_host_ctrl);
2518 pci_enable_wake(tp->pdev, state, false);
2519 pci_set_power_state(tp->pdev, PCI_D0);
2521 /* Switch out of Vaux if it is a NIC */
2522 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2523 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2533 netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
2538 /* Restore the CLKREQ setting. */
2539 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2542 pci_read_config_word(tp->pdev,
2543 tp->pcie_cap + PCI_EXP_LNKCTL,
2545 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2546 pci_write_config_word(tp->pdev,
2547 tp->pcie_cap + PCI_EXP_LNKCTL,
2551 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2552 tw32(TG3PCI_MISC_HOST_CTRL,
2553 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2555 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2556 device_may_wakeup(&tp->pdev->dev) &&
2557 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2559 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2560 do_low_power = false;
2561 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2562 !tp->link_config.phy_is_low_power) {
2563 struct phy_device *phydev;
2564 u32 phyid, advertising;
2566 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2568 tp->link_config.phy_is_low_power = 1;
2570 tp->link_config.orig_speed = phydev->speed;
2571 tp->link_config.orig_duplex = phydev->duplex;
2572 tp->link_config.orig_autoneg = phydev->autoneg;
2573 tp->link_config.orig_advertising = phydev->advertising;
2575 advertising = ADVERTISED_TP |
2577 ADVERTISED_Autoneg |
2578 ADVERTISED_10baseT_Half;
2580 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2581 device_should_wake) {
2582 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2584 ADVERTISED_100baseT_Half |
2585 ADVERTISED_100baseT_Full |
2586 ADVERTISED_10baseT_Full;
2588 advertising |= ADVERTISED_10baseT_Full;
2591 phydev->advertising = advertising;
2593 phy_start_aneg(phydev);
2595 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2596 if (phyid != PHY_ID_BCMAC131) {
2597 phyid &= PHY_BCM_OUI_MASK;
2598 if (phyid == PHY_BCM_OUI_1 ||
2599 phyid == PHY_BCM_OUI_2 ||
2600 phyid == PHY_BCM_OUI_3)
2601 do_low_power = true;
2605 do_low_power = true;
2607 if (tp->link_config.phy_is_low_power == 0) {
2608 tp->link_config.phy_is_low_power = 1;
2609 tp->link_config.orig_speed = tp->link_config.speed;
2610 tp->link_config.orig_duplex = tp->link_config.duplex;
2611 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2614 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2615 tp->link_config.speed = SPEED_10;
2616 tp->link_config.duplex = DUPLEX_HALF;
2617 tp->link_config.autoneg = AUTONEG_ENABLE;
2618 tg3_setup_phy(tp, 0);
2622 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2625 val = tr32(GRC_VCPU_EXT_CTRL);
2626 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2627 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2631 for (i = 0; i < 200; i++) {
2632 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2633 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2638 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2639 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2640 WOL_DRV_STATE_SHUTDOWN |
2644 if (device_should_wake) {
2647 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2649 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2653 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2654 mac_mode = MAC_MODE_PORT_MODE_GMII;
2656 mac_mode = MAC_MODE_PORT_MODE_MII;
2658 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2659 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2661 u32 speed = (tp->tg3_flags &
2662 TG3_FLAG_WOL_SPEED_100MB) ?
2663 SPEED_100 : SPEED_10;
2664 if (tg3_5700_link_polarity(tp, speed))
2665 mac_mode |= MAC_MODE_LINK_POLARITY;
2667 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2670 mac_mode = MAC_MODE_PORT_MODE_TBI;
2673 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2674 tw32(MAC_LED_CTRL, tp->led_ctrl);
2676 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2677 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2678 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2679 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2680 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2681 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2683 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2684 mac_mode |= tp->mac_mode &
2685 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2686 if (mac_mode & MAC_MODE_APE_TX_EN)
2687 mac_mode |= MAC_MODE_TDE_ENABLE;
2690 tw32_f(MAC_MODE, mac_mode);
2693 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2697 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2698 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2699 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2702 base_val = tp->pci_clock_ctrl;
2703 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2704 CLOCK_CTRL_TXCLK_DISABLE);
2706 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2707 CLOCK_CTRL_PWRDOWN_PLL133, 40);
2708 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2709 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2710 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2712 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2713 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2714 u32 newbits1, newbits2;
2716 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2717 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2718 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2719 CLOCK_CTRL_TXCLK_DISABLE |
2721 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2722 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2723 newbits1 = CLOCK_CTRL_625_CORE;
2724 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2726 newbits1 = CLOCK_CTRL_ALTCLK;
2727 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2730 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2733 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2736 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2739 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2740 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2741 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2742 CLOCK_CTRL_TXCLK_DISABLE |
2743 CLOCK_CTRL_44MHZ_CORE);
2745 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2748 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2749 tp->pci_clock_ctrl | newbits3, 40);
2753 if (!(device_should_wake) &&
2754 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2755 tg3_power_down_phy(tp, do_low_power);
2757 tg3_frob_aux_power(tp);
2759 /* Workaround for unstable PLL clock */
2760 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2761 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2762 u32 val = tr32(0x7d00);
2764 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2766 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2769 err = tg3_nvram_lock(tp);
2770 tg3_halt_cpu(tp, RX_CPU_BASE);
2772 tg3_nvram_unlock(tp);
2776 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2778 if (device_should_wake)
2779 pci_enable_wake(tp->pdev, state, true);
2781 /* Finally, set the new power state. */
2782 pci_set_power_state(tp->pdev, state);
2787 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2789 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2790 case MII_TG3_AUX_STAT_10HALF:
2792 *duplex = DUPLEX_HALF;
2795 case MII_TG3_AUX_STAT_10FULL:
2797 *duplex = DUPLEX_FULL;
2800 case MII_TG3_AUX_STAT_100HALF:
2802 *duplex = DUPLEX_HALF;
2805 case MII_TG3_AUX_STAT_100FULL:
2807 *duplex = DUPLEX_FULL;
2810 case MII_TG3_AUX_STAT_1000HALF:
2811 *speed = SPEED_1000;
2812 *duplex = DUPLEX_HALF;
2815 case MII_TG3_AUX_STAT_1000FULL:
2816 *speed = SPEED_1000;
2817 *duplex = DUPLEX_FULL;
2821 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2822 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2824 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2828 *speed = SPEED_INVALID;
2829 *duplex = DUPLEX_INVALID;
2834 static void tg3_phy_copper_begin(struct tg3 *tp)
2839 if (tp->link_config.phy_is_low_power) {
2840 /* Entering low power mode. Disable gigabit and
2841 * 100baseT advertisements.
2843 tg3_writephy(tp, MII_TG3_CTRL, 0);
2845 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2846 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2847 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2848 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2850 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2851 } else if (tp->link_config.speed == SPEED_INVALID) {
2852 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2853 tp->link_config.advertising &=
2854 ~(ADVERTISED_1000baseT_Half |
2855 ADVERTISED_1000baseT_Full);
2857 new_adv = ADVERTISE_CSMA;
2858 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2859 new_adv |= ADVERTISE_10HALF;
2860 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2861 new_adv |= ADVERTISE_10FULL;
2862 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2863 new_adv |= ADVERTISE_100HALF;
2864 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2865 new_adv |= ADVERTISE_100FULL;
2867 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2869 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2871 if (tp->link_config.advertising &
2872 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2874 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2875 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2876 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2877 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2878 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2879 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2880 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2881 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2882 MII_TG3_CTRL_ENABLE_AS_MASTER);
2883 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2885 tg3_writephy(tp, MII_TG3_CTRL, 0);
2888 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2889 new_adv |= ADVERTISE_CSMA;
2891 /* Asking for a specific link mode. */
2892 if (tp->link_config.speed == SPEED_1000) {
2893 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2895 if (tp->link_config.duplex == DUPLEX_FULL)
2896 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2898 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2899 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2900 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2901 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2902 MII_TG3_CTRL_ENABLE_AS_MASTER);
2904 if (tp->link_config.speed == SPEED_100) {
2905 if (tp->link_config.duplex == DUPLEX_FULL)
2906 new_adv |= ADVERTISE_100FULL;
2908 new_adv |= ADVERTISE_100HALF;
2910 if (tp->link_config.duplex == DUPLEX_FULL)
2911 new_adv |= ADVERTISE_10FULL;
2913 new_adv |= ADVERTISE_10HALF;
2915 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2920 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2923 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2924 tp->link_config.speed != SPEED_INVALID) {
2925 u32 bmcr, orig_bmcr;
2927 tp->link_config.active_speed = tp->link_config.speed;
2928 tp->link_config.active_duplex = tp->link_config.duplex;
2931 switch (tp->link_config.speed) {
2937 bmcr |= BMCR_SPEED100;
2941 bmcr |= TG3_BMCR_SPEED1000;
2945 if (tp->link_config.duplex == DUPLEX_FULL)
2946 bmcr |= BMCR_FULLDPLX;
2948 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2949 (bmcr != orig_bmcr)) {
2950 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2951 for (i = 0; i < 1500; i++) {
2955 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2956 tg3_readphy(tp, MII_BMSR, &tmp))
2958 if (!(tmp & BMSR_LSTATUS)) {
2963 tg3_writephy(tp, MII_BMCR, bmcr);
2967 tg3_writephy(tp, MII_BMCR,
2968 BMCR_ANENABLE | BMCR_ANRESTART);
2972 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2976 /* Turn off tap power management. */
2977 /* Set Extended packet length bit */
2978 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2980 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
2981 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
2982 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
2983 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
2984 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
2991 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2993 u32 adv_reg, all_mask = 0;
2995 if (mask & ADVERTISED_10baseT_Half)
2996 all_mask |= ADVERTISE_10HALF;
2997 if (mask & ADVERTISED_10baseT_Full)
2998 all_mask |= ADVERTISE_10FULL;
2999 if (mask & ADVERTISED_100baseT_Half)
3000 all_mask |= ADVERTISE_100HALF;
3001 if (mask & ADVERTISED_100baseT_Full)
3002 all_mask |= ADVERTISE_100FULL;
3004 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3007 if ((adv_reg & all_mask) != all_mask)
3009 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
3013 if (mask & ADVERTISED_1000baseT_Half)
3014 all_mask |= ADVERTISE_1000HALF;
3015 if (mask & ADVERTISED_1000baseT_Full)
3016 all_mask |= ADVERTISE_1000FULL;
3018 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3021 if ((tg3_ctrl & all_mask) != all_mask)
3027 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3031 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3034 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3035 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3037 if (tp->link_config.active_duplex == DUPLEX_FULL) {
3038 if (curadv != reqadv)
3041 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3042 tg3_readphy(tp, MII_LPA, rmtadv);
3044 /* Reprogram the advertisement register, even if it
3045 * does not affect the current link. If the link
3046 * gets renegotiated in the future, we can save an
3047 * additional renegotiation cycle by advertising
3048 * it correctly in the first place.
3050 if (curadv != reqadv) {
3051 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3052 ADVERTISE_PAUSE_ASYM);
3053 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3060 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3062 int current_link_up;
3064 u32 lcl_adv, rmt_adv;
3072 (MAC_STATUS_SYNC_CHANGED |
3073 MAC_STATUS_CFG_CHANGED |
3074 MAC_STATUS_MI_COMPLETION |
3075 MAC_STATUS_LNKSTATE_CHANGED));
3078 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3080 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3084 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3086 /* Some third-party PHYs need to be reset on link going
3089 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3090 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3091 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3092 netif_carrier_ok(tp->dev)) {
3093 tg3_readphy(tp, MII_BMSR, &bmsr);
3094 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3095 !(bmsr & BMSR_LSTATUS))
3101 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3102 tg3_readphy(tp, MII_BMSR, &bmsr);
3103 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3104 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3107 if (!(bmsr & BMSR_LSTATUS)) {
3108 err = tg3_init_5401phy_dsp(tp);
3112 tg3_readphy(tp, MII_BMSR, &bmsr);
3113 for (i = 0; i < 1000; i++) {
3115 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3116 (bmsr & BMSR_LSTATUS)) {
3122 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3123 TG3_PHY_REV_BCM5401_B0 &&
3124 !(bmsr & BMSR_LSTATUS) &&
3125 tp->link_config.active_speed == SPEED_1000) {
3126 err = tg3_phy_reset(tp);
3128 err = tg3_init_5401phy_dsp(tp);
3133 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3134 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3135 /* 5701 {A0,B0} CRC bug workaround */
3136 tg3_writephy(tp, 0x15, 0x0a75);
3137 tg3_writephy(tp, 0x1c, 0x8c68);
3138 tg3_writephy(tp, 0x1c, 0x8d68);
3139 tg3_writephy(tp, 0x1c, 0x8c68);
3142 /* Clear pending interrupts... */
3143 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3144 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3146 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3147 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3148 else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3149 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3151 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3152 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3153 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3154 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3155 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3157 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3160 current_link_up = 0;
3161 current_speed = SPEED_INVALID;
3162 current_duplex = DUPLEX_INVALID;
3164 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3167 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3168 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3169 if (!(val & (1 << 10))) {
3171 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3177 for (i = 0; i < 100; i++) {
3178 tg3_readphy(tp, MII_BMSR, &bmsr);
3179 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3180 (bmsr & BMSR_LSTATUS))
3185 if (bmsr & BMSR_LSTATUS) {
3188 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3189 for (i = 0; i < 2000; i++) {
3191 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3196 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3201 for (i = 0; i < 200; i++) {
3202 tg3_readphy(tp, MII_BMCR, &bmcr);
3203 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3205 if (bmcr && bmcr != 0x7fff)
3213 tp->link_config.active_speed = current_speed;
3214 tp->link_config.active_duplex = current_duplex;
3216 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3217 if ((bmcr & BMCR_ANENABLE) &&
3218 tg3_copper_is_advertising_all(tp,
3219 tp->link_config.advertising)) {
3220 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3222 current_link_up = 1;
3225 if (!(bmcr & BMCR_ANENABLE) &&
3226 tp->link_config.speed == current_speed &&
3227 tp->link_config.duplex == current_duplex &&
3228 tp->link_config.flowctrl ==
3229 tp->link_config.active_flowctrl) {
3230 current_link_up = 1;
3234 if (current_link_up == 1 &&
3235 tp->link_config.active_duplex == DUPLEX_FULL)
3236 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3240 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3243 tg3_phy_copper_begin(tp);
3245 tg3_readphy(tp, MII_BMSR, &tmp);
3246 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3247 (tmp & BMSR_LSTATUS))
3248 current_link_up = 1;
3251 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3252 if (current_link_up == 1) {
3253 if (tp->link_config.active_speed == SPEED_100 ||
3254 tp->link_config.active_speed == SPEED_10)
3255 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3257 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3258 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3259 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3261 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3263 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3264 if (tp->link_config.active_duplex == DUPLEX_HALF)
3265 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3267 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3268 if (current_link_up == 1 &&
3269 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3270 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3272 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3275 /* ??? Without this setting Netgear GA302T PHY does not
3276 * ??? send/receive packets...
3278 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3279 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3280 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3281 tw32_f(MAC_MI_MODE, tp->mi_mode);
3285 tw32_f(MAC_MODE, tp->mac_mode);
3288 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3289 /* Polled via timer. */
3290 tw32_f(MAC_EVENT, 0);
3292 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3296 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3297 current_link_up == 1 &&
3298 tp->link_config.active_speed == SPEED_1000 &&
3299 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3300 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3303 (MAC_STATUS_SYNC_CHANGED |
3304 MAC_STATUS_CFG_CHANGED));
3307 NIC_SRAM_FIRMWARE_MBOX,
3308 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3311 /* Prevent send BD corruption. */
3312 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3313 u16 oldlnkctl, newlnkctl;
3315 pci_read_config_word(tp->pdev,
3316 tp->pcie_cap + PCI_EXP_LNKCTL,
3318 if (tp->link_config.active_speed == SPEED_100 ||
3319 tp->link_config.active_speed == SPEED_10)
3320 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3322 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3323 if (newlnkctl != oldlnkctl)
3324 pci_write_config_word(tp->pdev,
3325 tp->pcie_cap + PCI_EXP_LNKCTL,
3329 if (current_link_up != netif_carrier_ok(tp->dev)) {
3330 if (current_link_up)
3331 netif_carrier_on(tp->dev);
3333 netif_carrier_off(tp->dev);
3334 tg3_link_report(tp);
3340 struct tg3_fiber_aneginfo {
3342 #define ANEG_STATE_UNKNOWN 0
3343 #define ANEG_STATE_AN_ENABLE 1
3344 #define ANEG_STATE_RESTART_INIT 2
3345 #define ANEG_STATE_RESTART 3
3346 #define ANEG_STATE_DISABLE_LINK_OK 4
3347 #define ANEG_STATE_ABILITY_DETECT_INIT 5
3348 #define ANEG_STATE_ABILITY_DETECT 6
3349 #define ANEG_STATE_ACK_DETECT_INIT 7
3350 #define ANEG_STATE_ACK_DETECT 8
3351 #define ANEG_STATE_COMPLETE_ACK_INIT 9
3352 #define ANEG_STATE_COMPLETE_ACK 10
3353 #define ANEG_STATE_IDLE_DETECT_INIT 11
3354 #define ANEG_STATE_IDLE_DETECT 12
3355 #define ANEG_STATE_LINK_OK 13
3356 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3357 #define ANEG_STATE_NEXT_PAGE_WAIT 15
3360 #define MR_AN_ENABLE 0x00000001
3361 #define MR_RESTART_AN 0x00000002
3362 #define MR_AN_COMPLETE 0x00000004
3363 #define MR_PAGE_RX 0x00000008
3364 #define MR_NP_LOADED 0x00000010
3365 #define MR_TOGGLE_TX 0x00000020
3366 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
3367 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
3368 #define MR_LP_ADV_SYM_PAUSE 0x00000100
3369 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
3370 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3371 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3372 #define MR_LP_ADV_NEXT_PAGE 0x00001000
3373 #define MR_TOGGLE_RX 0x00002000
3374 #define MR_NP_RX 0x00004000
3376 #define MR_LINK_OK 0x80000000
3378 unsigned long link_time, cur_time;
3380 u32 ability_match_cfg;
3381 int ability_match_count;
3383 char ability_match, idle_match, ack_match;
3385 u32 txconfig, rxconfig;
3386 #define ANEG_CFG_NP 0x00000080
3387 #define ANEG_CFG_ACK 0x00000040
3388 #define ANEG_CFG_RF2 0x00000020
3389 #define ANEG_CFG_RF1 0x00000010
3390 #define ANEG_CFG_PS2 0x00000001
3391 #define ANEG_CFG_PS1 0x00008000
3392 #define ANEG_CFG_HD 0x00004000
3393 #define ANEG_CFG_FD 0x00002000
3394 #define ANEG_CFG_INVAL 0x00001f06
3399 #define ANEG_TIMER_ENAB 2
3400 #define ANEG_FAILED -1
3402 #define ANEG_STATE_SETTLE_TIME 10000
3404 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3405 struct tg3_fiber_aneginfo *ap)
3408 unsigned long delta;
3412 if (ap->state == ANEG_STATE_UNKNOWN) {
3416 ap->ability_match_cfg = 0;
3417 ap->ability_match_count = 0;
3418 ap->ability_match = 0;
3424 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3425 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3427 if (rx_cfg_reg != ap->ability_match_cfg) {
3428 ap->ability_match_cfg = rx_cfg_reg;
3429 ap->ability_match = 0;
3430 ap->ability_match_count = 0;
3432 if (++ap->ability_match_count > 1) {
3433 ap->ability_match = 1;
3434 ap->ability_match_cfg = rx_cfg_reg;
3437 if (rx_cfg_reg & ANEG_CFG_ACK)
3445 ap->ability_match_cfg = 0;
3446 ap->ability_match_count = 0;
3447 ap->ability_match = 0;
3453 ap->rxconfig = rx_cfg_reg;
3456 switch (ap->state) {
3457 case ANEG_STATE_UNKNOWN:
3458 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3459 ap->state = ANEG_STATE_AN_ENABLE;
3462 case ANEG_STATE_AN_ENABLE:
3463 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3464 if (ap->flags & MR_AN_ENABLE) {
3467 ap->ability_match_cfg = 0;
3468 ap->ability_match_count = 0;
3469 ap->ability_match = 0;
3473 ap->state = ANEG_STATE_RESTART_INIT;
3475 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3479 case ANEG_STATE_RESTART_INIT:
3480 ap->link_time = ap->cur_time;
3481 ap->flags &= ~(MR_NP_LOADED);
3483 tw32(MAC_TX_AUTO_NEG, 0);
3484 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3485 tw32_f(MAC_MODE, tp->mac_mode);
3488 ret = ANEG_TIMER_ENAB;
3489 ap->state = ANEG_STATE_RESTART;
3492 case ANEG_STATE_RESTART:
3493 delta = ap->cur_time - ap->link_time;
3494 if (delta > ANEG_STATE_SETTLE_TIME)
3495 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3497 ret = ANEG_TIMER_ENAB;
3500 case ANEG_STATE_DISABLE_LINK_OK:
3504 case ANEG_STATE_ABILITY_DETECT_INIT:
3505 ap->flags &= ~(MR_TOGGLE_TX);
3506 ap->txconfig = ANEG_CFG_FD;
3507 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3508 if (flowctrl & ADVERTISE_1000XPAUSE)
3509 ap->txconfig |= ANEG_CFG_PS1;
3510 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3511 ap->txconfig |= ANEG_CFG_PS2;
3512 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3513 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3514 tw32_f(MAC_MODE, tp->mac_mode);
3517 ap->state = ANEG_STATE_ABILITY_DETECT;
3520 case ANEG_STATE_ABILITY_DETECT:
3521 if (ap->ability_match != 0 && ap->rxconfig != 0)
3522 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3525 case ANEG_STATE_ACK_DETECT_INIT:
3526 ap->txconfig |= ANEG_CFG_ACK;
3527 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3528 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3529 tw32_f(MAC_MODE, tp->mac_mode);
3532 ap->state = ANEG_STATE_ACK_DETECT;
3535 case ANEG_STATE_ACK_DETECT:
3536 if (ap->ack_match != 0) {
3537 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3538 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3539 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3541 ap->state = ANEG_STATE_AN_ENABLE;
3543 } else if (ap->ability_match != 0 &&
3544 ap->rxconfig == 0) {
3545 ap->state = ANEG_STATE_AN_ENABLE;
3549 case ANEG_STATE_COMPLETE_ACK_INIT:
3550 if (ap->rxconfig & ANEG_CFG_INVAL) {
3554 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3555 MR_LP_ADV_HALF_DUPLEX |
3556 MR_LP_ADV_SYM_PAUSE |
3557 MR_LP_ADV_ASYM_PAUSE |
3558 MR_LP_ADV_REMOTE_FAULT1 |
3559 MR_LP_ADV_REMOTE_FAULT2 |
3560 MR_LP_ADV_NEXT_PAGE |
3563 if (ap->rxconfig & ANEG_CFG_FD)
3564 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3565 if (ap->rxconfig & ANEG_CFG_HD)
3566 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3567 if (ap->rxconfig & ANEG_CFG_PS1)
3568 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3569 if (ap->rxconfig & ANEG_CFG_PS2)
3570 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3571 if (ap->rxconfig & ANEG_CFG_RF1)
3572 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3573 if (ap->rxconfig & ANEG_CFG_RF2)
3574 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3575 if (ap->rxconfig & ANEG_CFG_NP)
3576 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3578 ap->link_time = ap->cur_time;
3580 ap->flags ^= (MR_TOGGLE_TX);
3581 if (ap->rxconfig & 0x0008)
3582 ap->flags |= MR_TOGGLE_RX;
3583 if (ap->rxconfig & ANEG_CFG_NP)
3584 ap->flags |= MR_NP_RX;
3585 ap->flags |= MR_PAGE_RX;
3587 ap->state = ANEG_STATE_COMPLETE_ACK;
3588 ret = ANEG_TIMER_ENAB;
3591 case ANEG_STATE_COMPLETE_ACK:
3592 if (ap->ability_match != 0 &&
3593 ap->rxconfig == 0) {
3594 ap->state = ANEG_STATE_AN_ENABLE;
3597 delta = ap->cur_time - ap->link_time;
3598 if (delta > ANEG_STATE_SETTLE_TIME) {
3599 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3600 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3602 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3603 !(ap->flags & MR_NP_RX)) {
3604 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3612 case ANEG_STATE_IDLE_DETECT_INIT:
3613 ap->link_time = ap->cur_time;
3614 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3615 tw32_f(MAC_MODE, tp->mac_mode);
3618 ap->state = ANEG_STATE_IDLE_DETECT;
3619 ret = ANEG_TIMER_ENAB;
3622 case ANEG_STATE_IDLE_DETECT:
3623 if (ap->ability_match != 0 &&
3624 ap->rxconfig == 0) {
3625 ap->state = ANEG_STATE_AN_ENABLE;
3628 delta = ap->cur_time - ap->link_time;
3629 if (delta > ANEG_STATE_SETTLE_TIME) {
3630 /* XXX another gem from the Broadcom driver :( */
3631 ap->state = ANEG_STATE_LINK_OK;
3635 case ANEG_STATE_LINK_OK:
3636 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3640 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3641 /* ??? unimplemented */
3644 case ANEG_STATE_NEXT_PAGE_WAIT:
3645 /* ??? unimplemented */
3656 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3659 struct tg3_fiber_aneginfo aninfo;
3660 int status = ANEG_FAILED;
3664 tw32_f(MAC_TX_AUTO_NEG, 0);
3666 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3667 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3670 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3673 memset(&aninfo, 0, sizeof(aninfo));
3674 aninfo.flags |= MR_AN_ENABLE;
3675 aninfo.state = ANEG_STATE_UNKNOWN;
3676 aninfo.cur_time = 0;
3678 while (++tick < 195000) {
3679 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3680 if (status == ANEG_DONE || status == ANEG_FAILED)
3686 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3687 tw32_f(MAC_MODE, tp->mac_mode);
3690 *txflags = aninfo.txconfig;
3691 *rxflags = aninfo.flags;
3693 if (status == ANEG_DONE &&
3694 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3695 MR_LP_ADV_FULL_DUPLEX)))
3701 static void tg3_init_bcm8002(struct tg3 *tp)
3703 u32 mac_status = tr32(MAC_STATUS);
3706 /* Reset when initting first time or we have a link. */
3707 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3708 !(mac_status & MAC_STATUS_PCS_SYNCED))
3711 /* Set PLL lock range. */
3712 tg3_writephy(tp, 0x16, 0x8007);
3715 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3717 /* Wait for reset to complete. */
3718 /* XXX schedule_timeout() ... */
3719 for (i = 0; i < 500; i++)
3722 /* Config mode; select PMA/Ch 1 regs. */
3723 tg3_writephy(tp, 0x10, 0x8411);
3725 /* Enable auto-lock and comdet, select txclk for tx. */
3726 tg3_writephy(tp, 0x11, 0x0a10);
3728 tg3_writephy(tp, 0x18, 0x00a0);
3729 tg3_writephy(tp, 0x16, 0x41ff);
3731 /* Assert and deassert POR. */
3732 tg3_writephy(tp, 0x13, 0x0400);
3734 tg3_writephy(tp, 0x13, 0x0000);
3736 tg3_writephy(tp, 0x11, 0x0a50);
3738 tg3_writephy(tp, 0x11, 0x0a10);
3740 /* Wait for signal to stabilize */
3741 /* XXX schedule_timeout() ... */
3742 for (i = 0; i < 15000; i++)
3745 /* Deselect the channel register so we can read the PHYID
3748 tg3_writephy(tp, 0x10, 0x8011);
3751 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3754 u32 sg_dig_ctrl, sg_dig_status;
3755 u32 serdes_cfg, expected_sg_dig_ctrl;
3756 int workaround, port_a;
3757 int current_link_up;
3760 expected_sg_dig_ctrl = 0;
3763 current_link_up = 0;
3765 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3766 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3768 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3771 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3772 /* preserve bits 20-23 for voltage regulator */
3773 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3776 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3778 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3779 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3781 u32 val = serdes_cfg;
3787 tw32_f(MAC_SERDES_CFG, val);
3790 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3792 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3793 tg3_setup_flow_control(tp, 0, 0);
3794 current_link_up = 1;
3799 /* Want auto-negotiation. */
3800 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3802 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3803 if (flowctrl & ADVERTISE_1000XPAUSE)
3804 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3805 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3806 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3808 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3809 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3810 tp->serdes_counter &&
3811 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3812 MAC_STATUS_RCVD_CFG)) ==
3813 MAC_STATUS_PCS_SYNCED)) {
3814 tp->serdes_counter--;
3815 current_link_up = 1;
3820 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3821 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3823 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3825 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3826 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3827 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3828 MAC_STATUS_SIGNAL_DET)) {
3829 sg_dig_status = tr32(SG_DIG_STATUS);
3830 mac_status = tr32(MAC_STATUS);
3832 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3833 (mac_status & MAC_STATUS_PCS_SYNCED)) {
3834 u32 local_adv = 0, remote_adv = 0;
3836 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3837 local_adv |= ADVERTISE_1000XPAUSE;
3838 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3839 local_adv |= ADVERTISE_1000XPSE_ASYM;
3841 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3842 remote_adv |= LPA_1000XPAUSE;
3843 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3844 remote_adv |= LPA_1000XPAUSE_ASYM;
3846 tg3_setup_flow_control(tp, local_adv, remote_adv);
3847 current_link_up = 1;
3848 tp->serdes_counter = 0;
3849 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3850 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3851 if (tp->serdes_counter)
3852 tp->serdes_counter--;
3855 u32 val = serdes_cfg;
3862 tw32_f(MAC_SERDES_CFG, val);
3865 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3868 /* Link parallel detection - link is up */
3869 /* only if we have PCS_SYNC and not */
3870 /* receiving config code words */
3871 mac_status = tr32(MAC_STATUS);
3872 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3873 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3874 tg3_setup_flow_control(tp, 0, 0);
3875 current_link_up = 1;
3877 TG3_FLG2_PARALLEL_DETECT;
3878 tp->serdes_counter =
3879 SERDES_PARALLEL_DET_TIMEOUT;
3881 goto restart_autoneg;
3885 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3886 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3890 return current_link_up;
3893 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3895 int current_link_up = 0;
3897 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3900 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3901 u32 txflags, rxflags;
3904 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3905 u32 local_adv = 0, remote_adv = 0;
3907 if (txflags & ANEG_CFG_PS1)
3908 local_adv |= ADVERTISE_1000XPAUSE;
3909 if (txflags & ANEG_CFG_PS2)
3910 local_adv |= ADVERTISE_1000XPSE_ASYM;
3912 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3913 remote_adv |= LPA_1000XPAUSE;
3914 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3915 remote_adv |= LPA_1000XPAUSE_ASYM;
3917 tg3_setup_flow_control(tp, local_adv, remote_adv);
3919 current_link_up = 1;
3921 for (i = 0; i < 30; i++) {
3924 (MAC_STATUS_SYNC_CHANGED |
3925 MAC_STATUS_CFG_CHANGED));
3927 if ((tr32(MAC_STATUS) &
3928 (MAC_STATUS_SYNC_CHANGED |
3929 MAC_STATUS_CFG_CHANGED)) == 0)
3933 mac_status = tr32(MAC_STATUS);
3934 if (current_link_up == 0 &&
3935 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3936 !(mac_status & MAC_STATUS_RCVD_CFG))
3937 current_link_up = 1;
3939 tg3_setup_flow_control(tp, 0, 0);
3941 /* Forcing 1000FD link up. */
3942 current_link_up = 1;
3944 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3947 tw32_f(MAC_MODE, tp->mac_mode);
3952 return current_link_up;
3955 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3958 u16 orig_active_speed;
3959 u8 orig_active_duplex;
3961 int current_link_up;
3964 orig_pause_cfg = tp->link_config.active_flowctrl;
3965 orig_active_speed = tp->link_config.active_speed;
3966 orig_active_duplex = tp->link_config.active_duplex;
3968 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3969 netif_carrier_ok(tp->dev) &&
3970 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3971 mac_status = tr32(MAC_STATUS);
3972 mac_status &= (MAC_STATUS_PCS_SYNCED |
3973 MAC_STATUS_SIGNAL_DET |
3974 MAC_STATUS_CFG_CHANGED |
3975 MAC_STATUS_RCVD_CFG);
3976 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3977 MAC_STATUS_SIGNAL_DET)) {
3978 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3979 MAC_STATUS_CFG_CHANGED));
3984 tw32_f(MAC_TX_AUTO_NEG, 0);
3986 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3987 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3988 tw32_f(MAC_MODE, tp->mac_mode);
3991 if (tp->phy_id == TG3_PHY_ID_BCM8002)
3992 tg3_init_bcm8002(tp);
3994 /* Enable link change event even when serdes polling. */
3995 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3998 current_link_up = 0;
3999 mac_status = tr32(MAC_STATUS);
4001 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
4002 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4004 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4006 tp->napi[0].hw_status->status =
4007 (SD_STATUS_UPDATED |
4008 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4010 for (i = 0; i < 100; i++) {
4011 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4012 MAC_STATUS_CFG_CHANGED));
4014 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4015 MAC_STATUS_CFG_CHANGED |
4016 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4020 mac_status = tr32(MAC_STATUS);
4021 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4022 current_link_up = 0;
4023 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4024 tp->serdes_counter == 0) {
4025 tw32_f(MAC_MODE, (tp->mac_mode |
4026 MAC_MODE_SEND_CONFIGS));
4028 tw32_f(MAC_MODE, tp->mac_mode);
4032 if (current_link_up == 1) {
4033 tp->link_config.active_speed = SPEED_1000;
4034 tp->link_config.active_duplex = DUPLEX_FULL;
4035 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4036 LED_CTRL_LNKLED_OVERRIDE |
4037 LED_CTRL_1000MBPS_ON));
4039 tp->link_config.active_speed = SPEED_INVALID;
4040 tp->link_config.active_duplex = DUPLEX_INVALID;
4041 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4042 LED_CTRL_LNKLED_OVERRIDE |
4043 LED_CTRL_TRAFFIC_OVERRIDE));
4046 if (current_link_up != netif_carrier_ok(tp->dev)) {
4047 if (current_link_up)
4048 netif_carrier_on(tp->dev);
4050 netif_carrier_off(tp->dev);
4051 tg3_link_report(tp);
4053 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4054 if (orig_pause_cfg != now_pause_cfg ||
4055 orig_active_speed != tp->link_config.active_speed ||
4056 orig_active_duplex != tp->link_config.active_duplex)
4057 tg3_link_report(tp);
4063 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4065 int current_link_up, err = 0;
4069 u32 local_adv, remote_adv;
4071 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4072 tw32_f(MAC_MODE, tp->mac_mode);
4078 (MAC_STATUS_SYNC_CHANGED |
4079 MAC_STATUS_CFG_CHANGED |
4080 MAC_STATUS_MI_COMPLETION |
4081 MAC_STATUS_LNKSTATE_CHANGED));
4087 current_link_up = 0;
4088 current_speed = SPEED_INVALID;
4089 current_duplex = DUPLEX_INVALID;
4091 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4092 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4093 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4094 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4095 bmsr |= BMSR_LSTATUS;
4097 bmsr &= ~BMSR_LSTATUS;
4100 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4102 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4103 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4104 /* do nothing, just check for link up at the end */
4105 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4108 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4109 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4110 ADVERTISE_1000XPAUSE |
4111 ADVERTISE_1000XPSE_ASYM |
4114 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4116 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4117 new_adv |= ADVERTISE_1000XHALF;
4118 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4119 new_adv |= ADVERTISE_1000XFULL;
4121 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4122 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4123 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4124 tg3_writephy(tp, MII_BMCR, bmcr);
4126 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4127 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4128 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4135 bmcr &= ~BMCR_SPEED1000;
4136 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4138 if (tp->link_config.duplex == DUPLEX_FULL)
4139 new_bmcr |= BMCR_FULLDPLX;
4141 if (new_bmcr != bmcr) {
4142 /* BMCR_SPEED1000 is a reserved bit that needs
4143 * to be set on write.
4145 new_bmcr |= BMCR_SPEED1000;
4147 /* Force a linkdown */
4148 if (netif_carrier_ok(tp->dev)) {
4151 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4152 adv &= ~(ADVERTISE_1000XFULL |
4153 ADVERTISE_1000XHALF |
4155 tg3_writephy(tp, MII_ADVERTISE, adv);
4156 tg3_writephy(tp, MII_BMCR, bmcr |
4160 netif_carrier_off(tp->dev);
4162 tg3_writephy(tp, MII_BMCR, new_bmcr);
4164 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4165 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4166 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4168 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4169 bmsr |= BMSR_LSTATUS;
4171 bmsr &= ~BMSR_LSTATUS;
4173 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4177 if (bmsr & BMSR_LSTATUS) {
4178 current_speed = SPEED_1000;
4179 current_link_up = 1;
4180 if (bmcr & BMCR_FULLDPLX)
4181 current_duplex = DUPLEX_FULL;
4183 current_duplex = DUPLEX_HALF;
4188 if (bmcr & BMCR_ANENABLE) {
4191 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4192 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4193 common = local_adv & remote_adv;
4194 if (common & (ADVERTISE_1000XHALF |
4195 ADVERTISE_1000XFULL)) {
4196 if (common & ADVERTISE_1000XFULL)
4197 current_duplex = DUPLEX_FULL;
4199 current_duplex = DUPLEX_HALF;
4200 } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4201 /* Link is up via parallel detect */
4203 current_link_up = 0;
4208 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4209 tg3_setup_flow_control(tp, local_adv, remote_adv);
4211 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4212 if (tp->link_config.active_duplex == DUPLEX_HALF)
4213 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4215 tw32_f(MAC_MODE, tp->mac_mode);
4218 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4220 tp->link_config.active_speed = current_speed;
4221 tp->link_config.active_duplex = current_duplex;
4223 if (current_link_up != netif_carrier_ok(tp->dev)) {
4224 if (current_link_up)
4225 netif_carrier_on(tp->dev);
4227 netif_carrier_off(tp->dev);
4228 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4230 tg3_link_report(tp);
4235 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4237 if (tp->serdes_counter) {
4238 /* Give autoneg time to complete. */
4239 tp->serdes_counter--;
4243 if (!netif_carrier_ok(tp->dev) &&
4244 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4247 tg3_readphy(tp, MII_BMCR, &bmcr);
4248 if (bmcr & BMCR_ANENABLE) {
4251 /* Select shadow register 0x1f */
4252 tg3_writephy(tp, 0x1c, 0x7c00);
4253 tg3_readphy(tp, 0x1c, &phy1);
4255 /* Select expansion interrupt status register */
4256 tg3_writephy(tp, 0x17, 0x0f01);
4257 tg3_readphy(tp, 0x15, &phy2);
4258 tg3_readphy(tp, 0x15, &phy2);
4260 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4261 /* We have signal detect and not receiving
4262 * config code words, link is up by parallel
4266 bmcr &= ~BMCR_ANENABLE;
4267 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4268 tg3_writephy(tp, MII_BMCR, bmcr);
4269 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4272 } else if (netif_carrier_ok(tp->dev) &&
4273 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4274 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4277 /* Select expansion interrupt status register */
4278 tg3_writephy(tp, 0x17, 0x0f01);
4279 tg3_readphy(tp, 0x15, &phy2);
4283 /* Config code words received, turn on autoneg. */
4284 tg3_readphy(tp, MII_BMCR, &bmcr);
4285 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4287 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4293 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4297 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
4298 err = tg3_setup_fiber_phy(tp, force_reset);
4299 else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
4300 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4302 err = tg3_setup_copper_phy(tp, force_reset);
4304 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4307 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4308 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4310 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4315 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4316 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4317 tw32(GRC_MISC_CFG, val);
4320 if (tp->link_config.active_speed == SPEED_1000 &&
4321 tp->link_config.active_duplex == DUPLEX_HALF)
4322 tw32(MAC_TX_LENGTHS,
4323 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4324 (6 << TX_LENGTHS_IPG_SHIFT) |
4325 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4327 tw32(MAC_TX_LENGTHS,
4328 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4329 (6 << TX_LENGTHS_IPG_SHIFT) |
4330 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4332 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4333 if (netif_carrier_ok(tp->dev)) {
4334 tw32(HOSTCC_STAT_COAL_TICKS,
4335 tp->coal.stats_block_coalesce_usecs);
4337 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4341 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4342 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4343 if (!netif_carrier_ok(tp->dev))
4344 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4347 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4348 tw32(PCIE_PWR_MGMT_THRESH, val);
4354 /* This is called whenever we suspect that the system chipset is re-
4355 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4356 * is bogus tx completions. We try to recover by setting the
4357 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4360 static void tg3_tx_recover(struct tg3 *tp)
4362 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4363 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4365 netdev_warn(tp->dev,
4366 "The system may be re-ordering memory-mapped I/O "
4367 "cycles to the network device, attempting to recover. "
4368 "Please report the problem to the driver maintainer "
4369 "and include system chipset information.\n");
4371 spin_lock(&tp->lock);
4372 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4373 spin_unlock(&tp->lock);
4376 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4378 /* Tell compiler to fetch tx indices from memory. */
4380 return tnapi->tx_pending -
4381 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4384 /* Tigon3 never reports partial packet sends. So we do not
4385 * need special logic to handle SKBs that have not had all
4386 * of their frags sent yet, like SunGEM does.
4388 static void tg3_tx(struct tg3_napi *tnapi)
4390 struct tg3 *tp = tnapi->tp;
4391 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4392 u32 sw_idx = tnapi->tx_cons;
4393 struct netdev_queue *txq;
4394 int index = tnapi - tp->napi;
4396 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4399 txq = netdev_get_tx_queue(tp->dev, index);
4401 while (sw_idx != hw_idx) {
4402 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4403 struct sk_buff *skb = ri->skb;
4406 if (unlikely(skb == NULL)) {
4411 pci_unmap_single(tp->pdev,
4412 dma_unmap_addr(ri, mapping),
4418 sw_idx = NEXT_TX(sw_idx);
4420 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4421 ri = &tnapi->tx_buffers[sw_idx];
4422 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4425 pci_unmap_page(tp->pdev,
4426 dma_unmap_addr(ri, mapping),
4427 skb_shinfo(skb)->frags[i].size,
4429 sw_idx = NEXT_TX(sw_idx);
4434 if (unlikely(tx_bug)) {
4440 tnapi->tx_cons = sw_idx;
4442 /* Need to make the tx_cons update visible to tg3_start_xmit()
4443 * before checking for netif_queue_stopped(). Without the
4444 * memory barrier, there is a small possibility that tg3_start_xmit()
4445 * will miss it and cause the queue to be stopped forever.
4449 if (unlikely(netif_tx_queue_stopped(txq) &&
4450 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4451 __netif_tx_lock(txq, smp_processor_id());
4452 if (netif_tx_queue_stopped(txq) &&
4453 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4454 netif_tx_wake_queue(txq);
4455 __netif_tx_unlock(txq);
4459 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4464 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4465 map_sz, PCI_DMA_FROMDEVICE);
4466 dev_kfree_skb_any(ri->skb);
4470 /* Returns size of skb allocated or < 0 on error.
4472 * We only need to fill in the address because the other members
4473 * of the RX descriptor are invariant, see tg3_init_rings.
4475 * Note the purposeful assymetry of cpu vs. chip accesses. For
4476 * posting buffers we only dirty the first cache line of the RX
4477 * descriptor (containing the address). Whereas for the RX status
4478 * buffers the cpu only reads the last cacheline of the RX descriptor
4479 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4481 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4482 u32 opaque_key, u32 dest_idx_unmasked)
4484 struct tg3_rx_buffer_desc *desc;
4485 struct ring_info *map, *src_map;
4486 struct sk_buff *skb;
4488 int skb_size, dest_idx;
4491 switch (opaque_key) {
4492 case RXD_OPAQUE_RING_STD:
4493 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4494 desc = &tpr->rx_std[dest_idx];
4495 map = &tpr->rx_std_buffers[dest_idx];
4496 skb_size = tp->rx_pkt_map_sz;
4499 case RXD_OPAQUE_RING_JUMBO:
4500 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4501 desc = &tpr->rx_jmb[dest_idx].std;
4502 map = &tpr->rx_jmb_buffers[dest_idx];
4503 skb_size = TG3_RX_JMB_MAP_SZ;
4510 /* Do not overwrite any of the map or rp information
4511 * until we are sure we can commit to a new buffer.
4513 * Callers depend upon this behavior and assume that
4514 * we leave everything unchanged if we fail.
4516 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4520 skb_reserve(skb, tp->rx_offset);
4522 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4523 PCI_DMA_FROMDEVICE);
4524 if (pci_dma_mapping_error(tp->pdev, mapping)) {
4530 dma_unmap_addr_set(map, mapping, mapping);
4532 desc->addr_hi = ((u64)mapping >> 32);
4533 desc->addr_lo = ((u64)mapping & 0xffffffff);
4538 /* We only need to move over in the address because the other
4539 * members of the RX descriptor are invariant. See notes above
4540 * tg3_alloc_rx_skb for full details.
4542 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4543 struct tg3_rx_prodring_set *dpr,
4544 u32 opaque_key, int src_idx,
4545 u32 dest_idx_unmasked)
4547 struct tg3 *tp = tnapi->tp;
4548 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4549 struct ring_info *src_map, *dest_map;
4550 struct tg3_rx_prodring_set *spr = &tp->prodring[0];
4553 switch (opaque_key) {
4554 case RXD_OPAQUE_RING_STD:
4555 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4556 dest_desc = &dpr->rx_std[dest_idx];
4557 dest_map = &dpr->rx_std_buffers[dest_idx];
4558 src_desc = &spr->rx_std[src_idx];
4559 src_map = &spr->rx_std_buffers[src_idx];
4562 case RXD_OPAQUE_RING_JUMBO:
4563 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4564 dest_desc = &dpr->rx_jmb[dest_idx].std;
4565 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4566 src_desc = &spr->rx_jmb[src_idx].std;
4567 src_map = &spr->rx_jmb_buffers[src_idx];
4574 dest_map->skb = src_map->skb;
4575 dma_unmap_addr_set(dest_map, mapping,
4576 dma_unmap_addr(src_map, mapping));
4577 dest_desc->addr_hi = src_desc->addr_hi;
4578 dest_desc->addr_lo = src_desc->addr_lo;
4580 /* Ensure that the update to the skb happens after the physical
4581 * addresses have been transferred to the new BD location.
4585 src_map->skb = NULL;
4588 /* The RX ring scheme is composed of multiple rings which post fresh
4589 * buffers to the chip, and one special ring the chip uses to report
4590 * status back to the host.
4592 * The special ring reports the status of received packets to the
4593 * host. The chip does not write into the original descriptor the
4594 * RX buffer was obtained from. The chip simply takes the original
4595 * descriptor as provided by the host, updates the status and length
4596 * field, then writes this into the next status ring entry.
4598 * Each ring the host uses to post buffers to the chip is described
4599 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4600 * it is first placed into the on-chip ram. When the packet's length
4601 * is known, it walks down the TG3_BDINFO entries to select the ring.
4602 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4603 * which is within the range of the new packet's length is chosen.
4605 * The "separate ring for rx status" scheme may sound queer, but it makes
4606 * sense from a cache coherency perspective. If only the host writes
4607 * to the buffer post rings, and only the chip writes to the rx status
4608 * rings, then cache lines never move beyond shared-modified state.
4609 * If both the host and chip were to write into the same ring, cache line
4610 * eviction could occur since both entities want it in an exclusive state.
4612 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4614 struct tg3 *tp = tnapi->tp;
4615 u32 work_mask, rx_std_posted = 0;
4616 u32 std_prod_idx, jmb_prod_idx;
4617 u32 sw_idx = tnapi->rx_rcb_ptr;
4620 struct tg3_rx_prodring_set *tpr = tnapi->prodring;
4622 hw_idx = *(tnapi->rx_rcb_prod_idx);
4624 * We need to order the read of hw_idx and the read of
4625 * the opaque cookie.
4630 std_prod_idx = tpr->rx_std_prod_idx;
4631 jmb_prod_idx = tpr->rx_jmb_prod_idx;
4632 while (sw_idx != hw_idx && budget > 0) {
4633 struct ring_info *ri;
4634 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4636 struct sk_buff *skb;
4637 dma_addr_t dma_addr;
4638 u32 opaque_key, desc_idx, *post_ptr;
4639 bool hw_vlan __maybe_unused = false;
4640 u16 vtag __maybe_unused = 0;
4642 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4643 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4644 if (opaque_key == RXD_OPAQUE_RING_STD) {
4645 ri = &tp->prodring[0].rx_std_buffers[desc_idx];
4646 dma_addr = dma_unmap_addr(ri, mapping);
4648 post_ptr = &std_prod_idx;
4650 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4651 ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
4652 dma_addr = dma_unmap_addr(ri, mapping);
4654 post_ptr = &jmb_prod_idx;
4656 goto next_pkt_nopost;
4658 work_mask |= opaque_key;
4660 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4661 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4663 tg3_recycle_rx(tnapi, tpr, opaque_key,
4664 desc_idx, *post_ptr);
4666 /* Other statistics kept track of by card. */
4667 tp->net_stats.rx_dropped++;
4671 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4674 if (len > TG3_RX_COPY_THRESH(tp)) {
4677 skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4682 pci_unmap_single(tp->pdev, dma_addr, skb_size,
4683 PCI_DMA_FROMDEVICE);
4685 /* Ensure that the update to the skb happens
4686 * after the usage of the old DMA mapping.
4694 struct sk_buff *copy_skb;
4696 tg3_recycle_rx(tnapi, tpr, opaque_key,
4697 desc_idx, *post_ptr);
4699 copy_skb = netdev_alloc_skb(tp->dev, len + VLAN_HLEN +
4701 if (copy_skb == NULL)
4702 goto drop_it_no_recycle;
4704 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN + VLAN_HLEN);
4705 skb_put(copy_skb, len);
4706 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4707 skb_copy_from_linear_data(skb, copy_skb->data, len);
4708 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4710 /* We'll reuse the original ring buffer. */
4714 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4715 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4716 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4717 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4718 skb->ip_summed = CHECKSUM_UNNECESSARY;
4720 skb->ip_summed = CHECKSUM_NONE;
4722 skb->protocol = eth_type_trans(skb, tp->dev);
4724 if (len > (tp->dev->mtu + ETH_HLEN) &&
4725 skb->protocol != htons(ETH_P_8021Q)) {
4730 if (desc->type_flags & RXD_FLAG_VLAN &&
4731 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) {
4732 vtag = desc->err_vlan & RXD_VLAN_MASK;
4733 #if TG3_VLAN_TAG_USED
4739 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
4740 __skb_push(skb, VLAN_HLEN);
4742 memmove(ve, skb->data + VLAN_HLEN,
4744 ve->h_vlan_proto = htons(ETH_P_8021Q);
4745 ve->h_vlan_TCI = htons(vtag);
4749 #if TG3_VLAN_TAG_USED
4751 vlan_gro_receive(&tnapi->napi, tp->vlgrp, vtag, skb);
4754 napi_gro_receive(&tnapi->napi, skb);
4762 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4763 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4764 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4765 tpr->rx_std_prod_idx);
4766 work_mask &= ~RXD_OPAQUE_RING_STD;
4771 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4773 /* Refresh hw_idx to see if there is new work */
4774 if (sw_idx == hw_idx) {
4775 hw_idx = *(tnapi->rx_rcb_prod_idx);
4780 /* ACK the status ring. */
4781 tnapi->rx_rcb_ptr = sw_idx;
4782 tw32_rx_mbox(tnapi->consmbox, sw_idx);
4784 /* Refill RX ring(s). */
4785 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4786 if (work_mask & RXD_OPAQUE_RING_STD) {
4787 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4788 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4789 tpr->rx_std_prod_idx);
4791 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4792 tpr->rx_jmb_prod_idx = jmb_prod_idx %
4793 TG3_RX_JUMBO_RING_SIZE;
4794 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4795 tpr->rx_jmb_prod_idx);
4798 } else if (work_mask) {
4799 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4800 * updated before the producer indices can be updated.
4804 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4805 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
4807 if (tnapi != &tp->napi[1])
4808 napi_schedule(&tp->napi[1].napi);
4814 static void tg3_poll_link(struct tg3 *tp)
4816 /* handle link change and other phy events */
4817 if (!(tp->tg3_flags &
4818 (TG3_FLAG_USE_LINKCHG_REG |
4819 TG3_FLAG_POLL_SERDES))) {
4820 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4822 if (sblk->status & SD_STATUS_LINK_CHG) {
4823 sblk->status = SD_STATUS_UPDATED |
4824 (sblk->status & ~SD_STATUS_LINK_CHG);
4825 spin_lock(&tp->lock);
4826 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4828 (MAC_STATUS_SYNC_CHANGED |
4829 MAC_STATUS_CFG_CHANGED |
4830 MAC_STATUS_MI_COMPLETION |
4831 MAC_STATUS_LNKSTATE_CHANGED));
4834 tg3_setup_phy(tp, 0);
4835 spin_unlock(&tp->lock);
4840 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4841 struct tg3_rx_prodring_set *dpr,
4842 struct tg3_rx_prodring_set *spr)
4844 u32 si, di, cpycnt, src_prod_idx;
4848 src_prod_idx = spr->rx_std_prod_idx;
4850 /* Make sure updates to the rx_std_buffers[] entries and the
4851 * standard producer index are seen in the correct order.
4855 if (spr->rx_std_cons_idx == src_prod_idx)
4858 if (spr->rx_std_cons_idx < src_prod_idx)
4859 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4861 cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4863 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4865 si = spr->rx_std_cons_idx;
4866 di = dpr->rx_std_prod_idx;
4868 for (i = di; i < di + cpycnt; i++) {
4869 if (dpr->rx_std_buffers[i].skb) {
4879 /* Ensure that updates to the rx_std_buffers ring and the
4880 * shadowed hardware producer ring from tg3_recycle_skb() are
4881 * ordered correctly WRT the skb check above.
4885 memcpy(&dpr->rx_std_buffers[di],
4886 &spr->rx_std_buffers[si],
4887 cpycnt * sizeof(struct ring_info));
4889 for (i = 0; i < cpycnt; i++, di++, si++) {
4890 struct tg3_rx_buffer_desc *sbd, *dbd;
4891 sbd = &spr->rx_std[si];
4892 dbd = &dpr->rx_std[di];
4893 dbd->addr_hi = sbd->addr_hi;
4894 dbd->addr_lo = sbd->addr_lo;
4897 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4899 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4904 src_prod_idx = spr->rx_jmb_prod_idx;
4906 /* Make sure updates to the rx_jmb_buffers[] entries and
4907 * the jumbo producer index are seen in the correct order.
4911 if (spr->rx_jmb_cons_idx == src_prod_idx)
4914 if (spr->rx_jmb_cons_idx < src_prod_idx)
4915 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4917 cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4919 cpycnt = min(cpycnt,
4920 TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4922 si = spr->rx_jmb_cons_idx;
4923 di = dpr->rx_jmb_prod_idx;
4925 for (i = di; i < di + cpycnt; i++) {
4926 if (dpr->rx_jmb_buffers[i].skb) {
4936 /* Ensure that updates to the rx_jmb_buffers ring and the
4937 * shadowed hardware producer ring from tg3_recycle_skb() are
4938 * ordered correctly WRT the skb check above.
4942 memcpy(&dpr->rx_jmb_buffers[di],
4943 &spr->rx_jmb_buffers[si],
4944 cpycnt * sizeof(struct ring_info));
4946 for (i = 0; i < cpycnt; i++, di++, si++) {
4947 struct tg3_rx_buffer_desc *sbd, *dbd;
4948 sbd = &spr->rx_jmb[si].std;
4949 dbd = &dpr->rx_jmb[di].std;
4950 dbd->addr_hi = sbd->addr_hi;
4951 dbd->addr_lo = sbd->addr_lo;
4954 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4955 TG3_RX_JUMBO_RING_SIZE;
4956 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4957 TG3_RX_JUMBO_RING_SIZE;
4963 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4965 struct tg3 *tp = tnapi->tp;
4967 /* run TX completion thread */
4968 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4970 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4974 /* run RX thread, within the bounds set by NAPI.
4975 * All RX "locking" is done by ensuring outside
4976 * code synchronizes with tg3->napi.poll()
4978 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4979 work_done += tg3_rx(tnapi, budget - work_done);
4981 if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4982 struct tg3_rx_prodring_set *dpr = &tp->prodring[0];
4984 u32 std_prod_idx = dpr->rx_std_prod_idx;
4985 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
4987 for (i = 1; i < tp->irq_cnt; i++)
4988 err |= tg3_rx_prodring_xfer(tp, dpr,
4989 tp->napi[i].prodring);
4993 if (std_prod_idx != dpr->rx_std_prod_idx)
4994 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4995 dpr->rx_std_prod_idx);
4997 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
4998 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4999 dpr->rx_jmb_prod_idx);
5004 tw32_f(HOSTCC_MODE, tp->coal_now);
5010 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5012 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5013 struct tg3 *tp = tnapi->tp;
5015 struct tg3_hw_status *sblk = tnapi->hw_status;
5018 work_done = tg3_poll_work(tnapi, work_done, budget);
5020 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5023 if (unlikely(work_done >= budget))
5026 /* tp->last_tag is used in tg3_int_reenable() below
5027 * to tell the hw how much work has been processed,
5028 * so we must read it before checking for more work.
5030 tnapi->last_tag = sblk->status_tag;
5031 tnapi->last_irq_tag = tnapi->last_tag;
5034 /* check for RX/TX work to do */
5035 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5036 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5037 napi_complete(napi);
5038 /* Reenable interrupts. */
5039 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5048 /* work_done is guaranteed to be less than budget. */
5049 napi_complete(napi);
5050 schedule_work(&tp->reset_task);
5054 static int tg3_poll(struct napi_struct *napi, int budget)
5056 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5057 struct tg3 *tp = tnapi->tp;
5059 struct tg3_hw_status *sblk = tnapi->hw_status;
5064 work_done = tg3_poll_work(tnapi, work_done, budget);
5066 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5069 if (unlikely(work_done >= budget))
5072 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5073 /* tp->last_tag is used in tg3_int_reenable() below
5074 * to tell the hw how much work has been processed,
5075 * so we must read it before checking for more work.
5077 tnapi->last_tag = sblk->status_tag;
5078 tnapi->last_irq_tag = tnapi->last_tag;
5081 sblk->status &= ~SD_STATUS_UPDATED;
5083 if (likely(!tg3_has_work(tnapi))) {
5084 napi_complete(napi);
5085 tg3_int_reenable(tnapi);
5093 /* work_done is guaranteed to be less than budget. */
5094 napi_complete(napi);
5095 schedule_work(&tp->reset_task);
5099 static void tg3_irq_quiesce(struct tg3 *tp)
5103 BUG_ON(tp->irq_sync);
5108 for (i = 0; i < tp->irq_cnt; i++)
5109 synchronize_irq(tp->napi[i].irq_vec);
5112 static inline int tg3_irq_sync(struct tg3 *tp)
5114 return tp->irq_sync;
5117 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5118 * If irq_sync is non-zero, then the IRQ handler must be synchronized
5119 * with as well. Most of the time, this is not necessary except when
5120 * shutting down the device.
5122 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5124 spin_lock_bh(&tp->lock);
5126 tg3_irq_quiesce(tp);
5129 static inline void tg3_full_unlock(struct tg3 *tp)
5131 spin_unlock_bh(&tp->lock);
5134 /* One-shot MSI handler - Chip automatically disables interrupt
5135 * after sending MSI so driver doesn't have to do it.
5137 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5139 struct tg3_napi *tnapi = dev_id;
5140 struct tg3 *tp = tnapi->tp;
5142 prefetch(tnapi->hw_status);
5144 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5146 if (likely(!tg3_irq_sync(tp)))
5147 napi_schedule(&tnapi->napi);
5152 /* MSI ISR - No need to check for interrupt sharing and no need to
5153 * flush status block and interrupt mailbox. PCI ordering rules
5154 * guarantee that MSI will arrive after the status block.
5156 static irqreturn_t tg3_msi(int irq, void *dev_id)
5158 struct tg3_napi *tnapi = dev_id;
5159 struct tg3 *tp = tnapi->tp;
5161 prefetch(tnapi->hw_status);
5163 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5165 * Writing any value to intr-mbox-0 clears PCI INTA# and
5166 * chip-internal interrupt pending events.
5167 * Writing non-zero to intr-mbox-0 additional tells the
5168 * NIC to stop sending us irqs, engaging "in-intr-handler"
5171 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5172 if (likely(!tg3_irq_sync(tp)))
5173 napi_schedule(&tnapi->napi);
5175 return IRQ_RETVAL(1);
5178 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5180 struct tg3_napi *tnapi = dev_id;
5181 struct tg3 *tp = tnapi->tp;
5182 struct tg3_hw_status *sblk = tnapi->hw_status;
5183 unsigned int handled = 1;
5185 /* In INTx mode, it is possible for the interrupt to arrive at
5186 * the CPU before the status block posted prior to the interrupt.
5187 * Reading the PCI State register will confirm whether the
5188 * interrupt is ours and will flush the status block.
5190 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5191 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5192 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5199 * Writing any value to intr-mbox-0 clears PCI INTA# and
5200 * chip-internal interrupt pending events.
5201 * Writing non-zero to intr-mbox-0 additional tells the
5202 * NIC to stop sending us irqs, engaging "in-intr-handler"
5205 * Flush the mailbox to de-assert the IRQ immediately to prevent
5206 * spurious interrupts. The flush impacts performance but
5207 * excessive spurious interrupts can be worse in some cases.
5209 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5210 if (tg3_irq_sync(tp))
5212 sblk->status &= ~SD_STATUS_UPDATED;
5213 if (likely(tg3_has_work(tnapi))) {
5214 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5215 napi_schedule(&tnapi->napi);
5217 /* No work, shared interrupt perhaps? re-enable
5218 * interrupts, and flush that PCI write
5220 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5224 return IRQ_RETVAL(handled);
5227 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5229 struct tg3_napi *tnapi = dev_id;
5230 struct tg3 *tp = tnapi->tp;
5231 struct tg3_hw_status *sblk = tnapi->hw_status;
5232 unsigned int handled = 1;
5234 /* In INTx mode, it is possible for the interrupt to arrive at
5235 * the CPU before the status block posted prior to the interrupt.
5236 * Reading the PCI State register will confirm whether the
5237 * interrupt is ours and will flush the status block.
5239 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5240 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5241 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5248 * writing any value to intr-mbox-0 clears PCI INTA# and
5249 * chip-internal interrupt pending events.
5250 * writing non-zero to intr-mbox-0 additional tells the
5251 * NIC to stop sending us irqs, engaging "in-intr-handler"
5254 * Flush the mailbox to de-assert the IRQ immediately to prevent
5255 * spurious interrupts. The flush impacts performance but
5256 * excessive spurious interrupts can be worse in some cases.
5258 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5261 * In a shared interrupt configuration, sometimes other devices'
5262 * interrupts will scream. We record the current status tag here
5263 * so that the above check can report that the screaming interrupts
5264 * are unhandled. Eventually they will be silenced.
5266 tnapi->last_irq_tag = sblk->status_tag;
5268 if (tg3_irq_sync(tp))
5271 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5273 napi_schedule(&tnapi->napi);
5276 return IRQ_RETVAL(handled);
5279 /* ISR for interrupt test */
5280 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5282 struct tg3_napi *tnapi = dev_id;
5283 struct tg3 *tp = tnapi->tp;
5284 struct tg3_hw_status *sblk = tnapi->hw_status;
5286 if ((sblk->status & SD_STATUS_UPDATED) ||
5287 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5288 tg3_disable_ints(tp);
5289 return IRQ_RETVAL(1);
5291 return IRQ_RETVAL(0);
5294 static int tg3_init_hw(struct tg3 *, int);
5295 static int tg3_halt(struct tg3 *, int, int);
5297 /* Restart hardware after configuration changes, self-test, etc.
5298 * Invoked with tp->lock held.
5300 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5301 __releases(tp->lock)
5302 __acquires(tp->lock)
5306 err = tg3_init_hw(tp, reset_phy);
5309 "Failed to re-initialize device, aborting\n");
5310 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5311 tg3_full_unlock(tp);
5312 del_timer_sync(&tp->timer);
5314 tg3_napi_enable(tp);
5316 tg3_full_lock(tp, 0);
5321 #ifdef CONFIG_NET_POLL_CONTROLLER
5322 static void tg3_poll_controller(struct net_device *dev)
5325 struct tg3 *tp = netdev_priv(dev);
5327 for (i = 0; i < tp->irq_cnt; i++)
5328 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5332 static void tg3_reset_task(struct work_struct *work)
5334 struct tg3 *tp = container_of(work, struct tg3, reset_task);
5336 unsigned int restart_timer;
5338 tg3_full_lock(tp, 0);
5340 if (!netif_running(tp->dev)) {
5341 tg3_full_unlock(tp);
5345 tg3_full_unlock(tp);
5351 tg3_full_lock(tp, 1);
5353 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5354 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5356 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5357 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5358 tp->write32_rx_mbox = tg3_write_flush_reg32;
5359 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5360 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5363 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5364 err = tg3_init_hw(tp, 1);
5368 tg3_netif_start(tp);
5371 mod_timer(&tp->timer, jiffies + 1);
5374 tg3_full_unlock(tp);
5380 static void tg3_dump_short_state(struct tg3 *tp)
5382 netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5383 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5384 netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5385 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5388 static void tg3_tx_timeout(struct net_device *dev)
5390 struct tg3 *tp = netdev_priv(dev);
5392 if (netif_msg_tx_err(tp)) {
5393 netdev_err(dev, "transmit timed out, resetting\n");
5394 tg3_dump_short_state(tp);
5397 schedule_work(&tp->reset_task);
5400 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5401 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5403 u32 base = (u32) mapping & 0xffffffff;
5405 return ((base > 0xffffdcc0) &&
5406 (base + len + 8 < base));
5409 /* Test for DMA addresses > 40-bit */
5410 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5413 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5414 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5415 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5422 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5424 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5425 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5426 struct sk_buff *skb, u32 last_plus_one,
5427 u32 *start, u32 base_flags, u32 mss)
5429 struct tg3 *tp = tnapi->tp;
5430 struct sk_buff *new_skb;
5431 dma_addr_t new_addr = 0;
5435 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5436 new_skb = skb_copy(skb, GFP_ATOMIC);
5438 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5440 new_skb = skb_copy_expand(skb,
5441 skb_headroom(skb) + more_headroom,
5442 skb_tailroom(skb), GFP_ATOMIC);
5448 /* New SKB is guaranteed to be linear. */
5450 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5452 /* Make sure the mapping succeeded */
5453 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5455 dev_kfree_skb(new_skb);
5458 /* Make sure new skb does not cross any 4G boundaries.
5459 * Drop the packet if it does.
5461 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5462 tg3_4g_overflow_test(new_addr, new_skb->len)) {
5463 pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5466 dev_kfree_skb(new_skb);
5469 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5470 base_flags, 1 | (mss << 1));
5471 *start = NEXT_TX(entry);
5475 /* Now clean up the sw ring entries. */
5477 while (entry != last_plus_one) {
5481 len = skb_headlen(skb);
5483 len = skb_shinfo(skb)->frags[i-1].size;
5485 pci_unmap_single(tp->pdev,
5486 dma_unmap_addr(&tnapi->tx_buffers[entry],
5488 len, PCI_DMA_TODEVICE);
5490 tnapi->tx_buffers[entry].skb = new_skb;
5491 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5494 tnapi->tx_buffers[entry].skb = NULL;
5496 entry = NEXT_TX(entry);
5505 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5506 dma_addr_t mapping, int len, u32 flags,
5509 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5510 int is_end = (mss_and_is_end & 0x1);
5511 u32 mss = (mss_and_is_end >> 1);
5515 flags |= TXD_FLAG_END;
5516 if (flags & TXD_FLAG_VLAN) {
5517 vlan_tag = flags >> 16;
5520 vlan_tag |= (mss << TXD_MSS_SHIFT);
5522 txd->addr_hi = ((u64) mapping >> 32);
5523 txd->addr_lo = ((u64) mapping & 0xffffffff);
5524 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5525 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5528 /* hard_start_xmit for devices that don't have any bugs and
5529 * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5531 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5532 struct net_device *dev)
5534 struct tg3 *tp = netdev_priv(dev);
5535 u32 len, entry, base_flags, mss;
5537 struct tg3_napi *tnapi;
5538 struct netdev_queue *txq;
5539 unsigned int i, last;
5541 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5542 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5543 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5546 /* We are running in BH disabled context with netif_tx_lock
5547 * and TX reclaim runs via tp->napi.poll inside of a software
5548 * interrupt. Furthermore, IRQ processing runs lockless so we have
5549 * no IRQ context deadlocks to worry about either. Rejoice!
5551 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5552 if (!netif_tx_queue_stopped(txq)) {
5553 netif_tx_stop_queue(txq);
5555 /* This is a hard error, log it. */
5557 "BUG! Tx Ring full when queue awake!\n");
5559 return NETDEV_TX_BUSY;
5562 entry = tnapi->tx_prod;
5564 mss = skb_shinfo(skb)->gso_size;
5566 int tcp_opt_len, ip_tcp_len;
5569 if (skb_header_cloned(skb) &&
5570 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5575 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5576 hdrlen = skb_headlen(skb) - ETH_HLEN;
5578 struct iphdr *iph = ip_hdr(skb);
5580 tcp_opt_len = tcp_optlen(skb);
5581 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5584 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5585 hdrlen = ip_tcp_len + tcp_opt_len;
5588 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5589 mss |= (hdrlen & 0xc) << 12;
5591 base_flags |= 0x00000010;
5592 base_flags |= (hdrlen & 0x3e0) << 5;
5596 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5597 TXD_FLAG_CPU_POST_DMA);
5599 tcp_hdr(skb)->check = 0;
5601 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5602 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5605 #if TG3_VLAN_TAG_USED
5606 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5607 base_flags |= (TXD_FLAG_VLAN |
5608 (vlan_tx_tag_get(skb) << 16));
5611 len = skb_headlen(skb);
5613 /* Queue skb data, a.k.a. the main skb fragment. */
5614 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5615 if (pci_dma_mapping_error(tp->pdev, mapping)) {
5620 tnapi->tx_buffers[entry].skb = skb;
5621 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5623 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5624 !mss && skb->len > ETH_DATA_LEN)
5625 base_flags |= TXD_FLAG_JMB_PKT;
5627 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5628 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5630 entry = NEXT_TX(entry);
5632 /* Now loop through additional data fragments, and queue them. */
5633 if (skb_shinfo(skb)->nr_frags > 0) {
5634 last = skb_shinfo(skb)->nr_frags - 1;
5635 for (i = 0; i <= last; i++) {
5636 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5639 mapping = pci_map_page(tp->pdev,
5642 len, PCI_DMA_TODEVICE);
5643 if (pci_dma_mapping_error(tp->pdev, mapping))
5646 tnapi->tx_buffers[entry].skb = NULL;
5647 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5650 tg3_set_txd(tnapi, entry, mapping, len,
5651 base_flags, (i == last) | (mss << 1));
5653 entry = NEXT_TX(entry);
5657 /* Packets are ready, update Tx producer idx local and on card. */
5658 tw32_tx_mbox(tnapi->prodmbox, entry);
5660 tnapi->tx_prod = entry;
5661 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5662 netif_tx_stop_queue(txq);
5664 /* netif_tx_stop_queue() must be done before checking
5665 * checking tx index in tg3_tx_avail() below, because in
5666 * tg3_tx(), we update tx index before checking for
5667 * netif_tx_queue_stopped().
5670 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5671 netif_tx_wake_queue(txq);
5677 return NETDEV_TX_OK;
5681 entry = tnapi->tx_prod;
5682 tnapi->tx_buffers[entry].skb = NULL;
5683 pci_unmap_single(tp->pdev,
5684 dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5687 for (i = 0; i <= last; i++) {
5688 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5689 entry = NEXT_TX(entry);
5691 pci_unmap_page(tp->pdev,
5692 dma_unmap_addr(&tnapi->tx_buffers[entry],
5694 frag->size, PCI_DMA_TODEVICE);
5698 return NETDEV_TX_OK;
5701 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5702 struct net_device *);
5704 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5705 * TSO header is greater than 80 bytes.
5707 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5709 struct sk_buff *segs, *nskb;
5710 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5712 /* Estimate the number of fragments in the worst case */
5713 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5714 netif_stop_queue(tp->dev);
5716 /* netif_tx_stop_queue() must be done before checking
5717 * checking tx index in tg3_tx_avail() below, because in
5718 * tg3_tx(), we update tx index before checking for
5719 * netif_tx_queue_stopped().
5722 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5723 return NETDEV_TX_BUSY;
5725 netif_wake_queue(tp->dev);
5728 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5730 goto tg3_tso_bug_end;
5736 tg3_start_xmit_dma_bug(nskb, tp->dev);
5742 return NETDEV_TX_OK;
5745 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5746 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5748 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5749 struct net_device *dev)
5751 struct tg3 *tp = netdev_priv(dev);
5752 u32 len, entry, base_flags, mss;
5753 int would_hit_hwbug;
5755 struct tg3_napi *tnapi;
5756 struct netdev_queue *txq;
5757 unsigned int i, last;
5759 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5760 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5761 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5764 /* We are running in BH disabled context with netif_tx_lock
5765 * and TX reclaim runs via tp->napi.poll inside of a software
5766 * interrupt. Furthermore, IRQ processing runs lockless so we have
5767 * no IRQ context deadlocks to worry about either. Rejoice!
5769 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5770 if (!netif_tx_queue_stopped(txq)) {
5771 netif_tx_stop_queue(txq);
5773 /* This is a hard error, log it. */
5775 "BUG! Tx Ring full when queue awake!\n");
5777 return NETDEV_TX_BUSY;
5780 entry = tnapi->tx_prod;
5782 if (skb->ip_summed == CHECKSUM_PARTIAL)
5783 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5785 mss = skb_shinfo(skb)->gso_size;
5788 u32 tcp_opt_len, hdr_len;
5790 if (skb_header_cloned(skb) &&
5791 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5797 tcp_opt_len = tcp_optlen(skb);
5799 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
5800 hdr_len = skb_headlen(skb) - ETH_HLEN;
5804 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5805 hdr_len = ip_tcp_len + tcp_opt_len;
5808 iph->tot_len = htons(mss + hdr_len);
5811 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5812 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5813 return tg3_tso_bug(tp, skb);
5815 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5816 TXD_FLAG_CPU_POST_DMA);
5818 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5819 tcp_hdr(skb)->check = 0;
5820 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5822 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5827 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5828 mss |= (hdr_len & 0xc) << 12;
5830 base_flags |= 0x00000010;
5831 base_flags |= (hdr_len & 0x3e0) << 5;
5832 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5833 mss |= hdr_len << 9;
5834 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5835 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5836 if (tcp_opt_len || iph->ihl > 5) {
5839 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5840 mss |= (tsflags << 11);
5843 if (tcp_opt_len || iph->ihl > 5) {
5846 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5847 base_flags |= tsflags << 12;
5851 #if TG3_VLAN_TAG_USED
5852 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5853 base_flags |= (TXD_FLAG_VLAN |
5854 (vlan_tx_tag_get(skb) << 16));
5857 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5858 !mss && skb->len > ETH_DATA_LEN)
5859 base_flags |= TXD_FLAG_JMB_PKT;
5861 len = skb_headlen(skb);
5863 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5864 if (pci_dma_mapping_error(tp->pdev, mapping)) {
5869 tnapi->tx_buffers[entry].skb = skb;
5870 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5872 would_hit_hwbug = 0;
5874 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5875 would_hit_hwbug = 1;
5877 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5878 tg3_4g_overflow_test(mapping, len))
5879 would_hit_hwbug = 1;
5881 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5882 tg3_40bit_overflow_test(tp, mapping, len))
5883 would_hit_hwbug = 1;
5885 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5886 would_hit_hwbug = 1;
5888 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5889 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5891 entry = NEXT_TX(entry);
5893 /* Now loop through additional data fragments, and queue them. */
5894 if (skb_shinfo(skb)->nr_frags > 0) {
5895 last = skb_shinfo(skb)->nr_frags - 1;
5896 for (i = 0; i <= last; i++) {
5897 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5900 mapping = pci_map_page(tp->pdev,
5903 len, PCI_DMA_TODEVICE);
5905 tnapi->tx_buffers[entry].skb = NULL;
5906 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5908 if (pci_dma_mapping_error(tp->pdev, mapping))
5911 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5913 would_hit_hwbug = 1;
5915 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5916 tg3_4g_overflow_test(mapping, len))
5917 would_hit_hwbug = 1;
5919 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5920 tg3_40bit_overflow_test(tp, mapping, len))
5921 would_hit_hwbug = 1;
5923 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5924 tg3_set_txd(tnapi, entry, mapping, len,
5925 base_flags, (i == last)|(mss << 1));
5927 tg3_set_txd(tnapi, entry, mapping, len,
5928 base_flags, (i == last));
5930 entry = NEXT_TX(entry);
5934 if (would_hit_hwbug) {
5935 u32 last_plus_one = entry;
5938 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5939 start &= (TG3_TX_RING_SIZE - 1);
5941 /* If the workaround fails due to memory/mapping
5942 * failure, silently drop this packet.
5944 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
5945 &start, base_flags, mss))
5951 /* Packets are ready, update Tx producer idx local and on card. */
5952 tw32_tx_mbox(tnapi->prodmbox, entry);
5954 tnapi->tx_prod = entry;
5955 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5956 netif_tx_stop_queue(txq);
5958 /* netif_tx_stop_queue() must be done before checking
5959 * checking tx index in tg3_tx_avail() below, because in
5960 * tg3_tx(), we update tx index before checking for
5961 * netif_tx_queue_stopped().
5964 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5965 netif_tx_wake_queue(txq);
5971 return NETDEV_TX_OK;
5975 entry = tnapi->tx_prod;
5976 tnapi->tx_buffers[entry].skb = NULL;
5977 pci_unmap_single(tp->pdev,
5978 dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5981 for (i = 0; i <= last; i++) {
5982 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5983 entry = NEXT_TX(entry);
5985 pci_unmap_page(tp->pdev,
5986 dma_unmap_addr(&tnapi->tx_buffers[entry],
5988 frag->size, PCI_DMA_TODEVICE);
5992 return NETDEV_TX_OK;
5995 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
6000 if (new_mtu > ETH_DATA_LEN) {
6001 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6002 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
6003 ethtool_op_set_tso(dev, 0);
6005 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
6008 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6009 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
6010 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
6014 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
6016 struct tg3 *tp = netdev_priv(dev);
6019 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
6022 if (!netif_running(dev)) {
6023 /* We'll just catch it later when the
6026 tg3_set_mtu(dev, tp, new_mtu);
6034 tg3_full_lock(tp, 1);
6036 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6038 tg3_set_mtu(dev, tp, new_mtu);
6040 err = tg3_restart_hw(tp, 0);
6043 tg3_netif_start(tp);
6045 tg3_full_unlock(tp);
6053 static void tg3_rx_prodring_free(struct tg3 *tp,
6054 struct tg3_rx_prodring_set *tpr)
6058 if (tpr != &tp->prodring[0]) {
6059 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
6060 i = (i + 1) % TG3_RX_RING_SIZE)
6061 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6064 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6065 for (i = tpr->rx_jmb_cons_idx;
6066 i != tpr->rx_jmb_prod_idx;
6067 i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
6068 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6076 for (i = 0; i < TG3_RX_RING_SIZE; i++)
6077 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6080 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6081 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
6082 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6087 /* Initialize rx rings for packet processing.
6089 * The chip has been shut down and the driver detached from
6090 * the networking, so no interrupts or new tx packets will
6091 * end up in the driver. tp->{tx,}lock are held and thus
6094 static int tg3_rx_prodring_alloc(struct tg3 *tp,
6095 struct tg3_rx_prodring_set *tpr)
6097 u32 i, rx_pkt_dma_sz;
6099 tpr->rx_std_cons_idx = 0;
6100 tpr->rx_std_prod_idx = 0;
6101 tpr->rx_jmb_cons_idx = 0;
6102 tpr->rx_jmb_prod_idx = 0;
6104 if (tpr != &tp->prodring[0]) {
6105 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
6106 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
6107 memset(&tpr->rx_jmb_buffers[0], 0,
6108 TG3_RX_JMB_BUFF_RING_SIZE);
6112 /* Zero out all descriptors. */
6113 memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
6115 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6116 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
6117 tp->dev->mtu > ETH_DATA_LEN)
6118 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6119 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6121 /* Initialize invariants of the rings, we only set this
6122 * stuff once. This works because the card does not
6123 * write into the rx buffer posting rings.
6125 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
6126 struct tg3_rx_buffer_desc *rxd;
6128 rxd = &tpr->rx_std[i];
6129 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6130 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6131 rxd->opaque = (RXD_OPAQUE_RING_STD |
6132 (i << RXD_OPAQUE_INDEX_SHIFT));
6135 /* Now allocate fresh SKBs for each rx ring. */
6136 for (i = 0; i < tp->rx_pending; i++) {
6137 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6138 netdev_warn(tp->dev,
6139 "Using a smaller RX standard ring. Only "
6140 "%d out of %d buffers were allocated "
6141 "successfully\n", i, tp->rx_pending);
6149 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6152 memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
6154 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
6157 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
6158 struct tg3_rx_buffer_desc *rxd;
6160 rxd = &tpr->rx_jmb[i].std;
6161 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6162 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6164 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6165 (i << RXD_OPAQUE_INDEX_SHIFT));
6168 for (i = 0; i < tp->rx_jumbo_pending; i++) {
6169 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
6170 netdev_warn(tp->dev,
6171 "Using a smaller RX jumbo ring. Only %d "
6172 "out of %d buffers were allocated "
6173 "successfully\n", i, tp->rx_jumbo_pending);
6176 tp->rx_jumbo_pending = i;
6185 tg3_rx_prodring_free(tp, tpr);
6189 static void tg3_rx_prodring_fini(struct tg3 *tp,
6190 struct tg3_rx_prodring_set *tpr)
6192 kfree(tpr->rx_std_buffers);
6193 tpr->rx_std_buffers = NULL;
6194 kfree(tpr->rx_jmb_buffers);
6195 tpr->rx_jmb_buffers = NULL;
6197 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
6198 tpr->rx_std, tpr->rx_std_mapping);
6202 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
6203 tpr->rx_jmb, tpr->rx_jmb_mapping);
6208 static int tg3_rx_prodring_init(struct tg3 *tp,
6209 struct tg3_rx_prodring_set *tpr)
6211 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
6212 if (!tpr->rx_std_buffers)
6215 tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6216 &tpr->rx_std_mapping);
6220 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6221 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
6223 if (!tpr->rx_jmb_buffers)
6226 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6227 TG3_RX_JUMBO_RING_BYTES,
6228 &tpr->rx_jmb_mapping);
6236 tg3_rx_prodring_fini(tp, tpr);
6240 /* Free up pending packets in all rx/tx rings.
6242 * The chip has been shut down and the driver detached from
6243 * the networking, so no interrupts or new tx packets will
6244 * end up in the driver. tp->{tx,}lock is not held and we are not
6245 * in an interrupt context and thus may sleep.
6247 static void tg3_free_rings(struct tg3 *tp)
6251 for (j = 0; j < tp->irq_cnt; j++) {
6252 struct tg3_napi *tnapi = &tp->napi[j];
6254 tg3_rx_prodring_free(tp, &tp->prodring[j]);
6256 if (!tnapi->tx_buffers)
6259 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6260 struct ring_info *txp;
6261 struct sk_buff *skb;
6264 txp = &tnapi->tx_buffers[i];
6272 pci_unmap_single(tp->pdev,
6273 dma_unmap_addr(txp, mapping),
6280 for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6281 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6282 pci_unmap_page(tp->pdev,
6283 dma_unmap_addr(txp, mapping),
6284 skb_shinfo(skb)->frags[k].size,
6289 dev_kfree_skb_any(skb);
6294 /* Initialize tx/rx rings for packet processing.
6296 * The chip has been shut down and the driver detached from
6297 * the networking, so no interrupts or new tx packets will
6298 * end up in the driver. tp->{tx,}lock are held and thus
6301 static int tg3_init_rings(struct tg3 *tp)
6305 /* Free up all the SKBs. */
6308 for (i = 0; i < tp->irq_cnt; i++) {
6309 struct tg3_napi *tnapi = &tp->napi[i];
6311 tnapi->last_tag = 0;
6312 tnapi->last_irq_tag = 0;
6313 tnapi->hw_status->status = 0;
6314 tnapi->hw_status->status_tag = 0;
6315 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6320 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6322 tnapi->rx_rcb_ptr = 0;
6324 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6326 if (tg3_rx_prodring_alloc(tp, &tp->prodring[i])) {
6336 * Must not be invoked with interrupt sources disabled and
6337 * the hardware shutdown down.
6339 static void tg3_free_consistent(struct tg3 *tp)
6343 for (i = 0; i < tp->irq_cnt; i++) {
6344 struct tg3_napi *tnapi = &tp->napi[i];
6346 if (tnapi->tx_ring) {
6347 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6348 tnapi->tx_ring, tnapi->tx_desc_mapping);
6349 tnapi->tx_ring = NULL;
6352 kfree(tnapi->tx_buffers);
6353 tnapi->tx_buffers = NULL;
6355 if (tnapi->rx_rcb) {
6356 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6358 tnapi->rx_rcb_mapping);
6359 tnapi->rx_rcb = NULL;
6362 if (tnapi->hw_status) {
6363 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6365 tnapi->status_mapping);
6366 tnapi->hw_status = NULL;
6371 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6372 tp->hw_stats, tp->stats_mapping);
6373 tp->hw_stats = NULL;
6376 for (i = 0; i < tp->irq_cnt; i++)
6377 tg3_rx_prodring_fini(tp, &tp->prodring[i]);
6381 * Must not be invoked with interrupt sources disabled and
6382 * the hardware shutdown down. Can sleep.
6384 static int tg3_alloc_consistent(struct tg3 *tp)
6388 for (i = 0; i < tp->irq_cnt; i++) {
6389 if (tg3_rx_prodring_init(tp, &tp->prodring[i]))
6393 tp->hw_stats = pci_alloc_consistent(tp->pdev,
6394 sizeof(struct tg3_hw_stats),
6395 &tp->stats_mapping);
6399 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6401 for (i = 0; i < tp->irq_cnt; i++) {
6402 struct tg3_napi *tnapi = &tp->napi[i];
6403 struct tg3_hw_status *sblk;
6405 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6407 &tnapi->status_mapping);
6408 if (!tnapi->hw_status)
6411 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6412 sblk = tnapi->hw_status;
6414 /* If multivector TSS is enabled, vector 0 does not handle
6415 * tx interrupts. Don't allocate any resources for it.
6417 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6418 (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6419 tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6422 if (!tnapi->tx_buffers)
6425 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6427 &tnapi->tx_desc_mapping);
6428 if (!tnapi->tx_ring)
6433 * When RSS is enabled, the status block format changes
6434 * slightly. The "rx_jumbo_consumer", "reserved",
6435 * and "rx_mini_consumer" members get mapped to the
6436 * other three rx return ring producer indexes.
6440 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6443 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6446 tnapi->rx_rcb_prod_idx = &sblk->reserved;
6449 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6453 tnapi->prodring = &tp->prodring[i];
6456 * If multivector RSS is enabled, vector 0 does not handle
6457 * rx or tx interrupts. Don't allocate any resources for it.
6459 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6462 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6463 TG3_RX_RCB_RING_BYTES(tp),
6464 &tnapi->rx_rcb_mapping);
6468 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6474 tg3_free_consistent(tp);
6478 #define MAX_WAIT_CNT 1000
6480 /* To stop a block, clear the enable bit and poll till it
6481 * clears. tp->lock is held.
6483 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6488 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6495 /* We can't enable/disable these bits of the
6496 * 5705/5750, just say success.
6509 for (i = 0; i < MAX_WAIT_CNT; i++) {
6512 if ((val & enable_bit) == 0)
6516 if (i == MAX_WAIT_CNT && !silent) {
6517 dev_err(&tp->pdev->dev,
6518 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6526 /* tp->lock is held. */
6527 static int tg3_abort_hw(struct tg3 *tp, int silent)
6531 tg3_disable_ints(tp);
6533 tp->rx_mode &= ~RX_MODE_ENABLE;
6534 tw32_f(MAC_RX_MODE, tp->rx_mode);
6537 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6538 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6539 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6540 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6541 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6542 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6544 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6545 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6546 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6547 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6548 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6549 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6550 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6552 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6553 tw32_f(MAC_MODE, tp->mac_mode);
6556 tp->tx_mode &= ~TX_MODE_ENABLE;
6557 tw32_f(MAC_TX_MODE, tp->tx_mode);
6559 for (i = 0; i < MAX_WAIT_CNT; i++) {
6561 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6564 if (i >= MAX_WAIT_CNT) {
6565 dev_err(&tp->pdev->dev,
6566 "%s timed out, TX_MODE_ENABLE will not clear "
6567 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
6571 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6572 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6573 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6575 tw32(FTQ_RESET, 0xffffffff);
6576 tw32(FTQ_RESET, 0x00000000);
6578 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6579 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6581 for (i = 0; i < tp->irq_cnt; i++) {
6582 struct tg3_napi *tnapi = &tp->napi[i];
6583 if (tnapi->hw_status)
6584 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6587 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6592 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6597 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6598 if (apedata != APE_SEG_SIG_MAGIC)
6601 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6602 if (!(apedata & APE_FW_STATUS_READY))
6605 /* Wait for up to 1 millisecond for APE to service previous event. */
6606 for (i = 0; i < 10; i++) {
6607 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6610 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6612 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6613 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6614 event | APE_EVENT_STATUS_EVENT_PENDING);
6616 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6618 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6624 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6625 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6628 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6633 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6637 case RESET_KIND_INIT:
6638 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6639 APE_HOST_SEG_SIG_MAGIC);
6640 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6641 APE_HOST_SEG_LEN_MAGIC);
6642 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6643 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6644 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6645 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
6646 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6647 APE_HOST_BEHAV_NO_PHYLOCK);
6649 event = APE_EVENT_STATUS_STATE_START;
6651 case RESET_KIND_SHUTDOWN:
6652 /* With the interface we are currently using,
6653 * APE does not track driver state. Wiping
6654 * out the HOST SEGMENT SIGNATURE forces
6655 * the APE to assume OS absent status.
6657 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6659 event = APE_EVENT_STATUS_STATE_UNLOAD;
6661 case RESET_KIND_SUSPEND:
6662 event = APE_EVENT_STATUS_STATE_SUSPEND;
6668 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6670 tg3_ape_send_event(tp, event);
6673 /* tp->lock is held. */
6674 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6676 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6677 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6679 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6681 case RESET_KIND_INIT:
6682 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6686 case RESET_KIND_SHUTDOWN:
6687 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6691 case RESET_KIND_SUSPEND:
6692 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6701 if (kind == RESET_KIND_INIT ||
6702 kind == RESET_KIND_SUSPEND)
6703 tg3_ape_driver_state_change(tp, kind);
6706 /* tp->lock is held. */
6707 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6709 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6711 case RESET_KIND_INIT:
6712 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6713 DRV_STATE_START_DONE);
6716 case RESET_KIND_SHUTDOWN:
6717 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6718 DRV_STATE_UNLOAD_DONE);
6726 if (kind == RESET_KIND_SHUTDOWN)
6727 tg3_ape_driver_state_change(tp, kind);
6730 /* tp->lock is held. */
6731 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6733 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6735 case RESET_KIND_INIT:
6736 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6740 case RESET_KIND_SHUTDOWN:
6741 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6745 case RESET_KIND_SUSPEND:
6746 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6756 static int tg3_poll_fw(struct tg3 *tp)
6761 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6762 /* Wait up to 20ms for init done. */
6763 for (i = 0; i < 200; i++) {
6764 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6771 /* Wait for firmware initialization to complete. */
6772 for (i = 0; i < 100000; i++) {
6773 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6774 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6779 /* Chip might not be fitted with firmware. Some Sun onboard
6780 * parts are configured like that. So don't signal the timeout
6781 * of the above loop as an error, but do report the lack of
6782 * running firmware once.
6785 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6786 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6788 netdev_info(tp->dev, "No firmware running\n");
6791 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6792 /* The 57765 A0 needs a little more
6793 * time to do some important work.
6801 /* Save PCI command register before chip reset */
6802 static void tg3_save_pci_state(struct tg3 *tp)
6804 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6807 /* Restore PCI state after chip reset */
6808 static void tg3_restore_pci_state(struct tg3 *tp)
6812 /* Re-enable indirect register accesses. */
6813 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6814 tp->misc_host_ctrl);
6816 /* Set MAX PCI retry to zero. */
6817 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6818 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6819 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6820 val |= PCISTATE_RETRY_SAME_DMA;
6821 /* Allow reads and writes to the APE register and memory space. */
6822 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6823 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6824 PCISTATE_ALLOW_APE_SHMEM_WR |
6825 PCISTATE_ALLOW_APE_PSPACE_WR;
6826 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6828 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6830 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6831 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6832 pcie_set_readrq(tp->pdev, 4096);
6834 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6835 tp->pci_cacheline_sz);
6836 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6841 /* Make sure PCI-X relaxed ordering bit is clear. */
6842 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6845 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6847 pcix_cmd &= ~PCI_X_CMD_ERO;
6848 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6852 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6854 /* Chip reset on 5780 will reset MSI enable bit,
6855 * so need to restore it.
6857 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6860 pci_read_config_word(tp->pdev,
6861 tp->msi_cap + PCI_MSI_FLAGS,
6863 pci_write_config_word(tp->pdev,
6864 tp->msi_cap + PCI_MSI_FLAGS,
6865 ctrl | PCI_MSI_FLAGS_ENABLE);
6866 val = tr32(MSGINT_MODE);
6867 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6872 static void tg3_stop_fw(struct tg3 *);
6874 /* tp->lock is held. */
6875 static int tg3_chip_reset(struct tg3 *tp)
6878 void (*write_op)(struct tg3 *, u32, u32);
6883 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6885 /* No matching tg3_nvram_unlock() after this because
6886 * chip reset below will undo the nvram lock.
6888 tp->nvram_lock_cnt = 0;
6890 /* GRC_MISC_CFG core clock reset will clear the memory
6891 * enable bit in PCI register 4 and the MSI enable bit
6892 * on some chips, so we save relevant registers here.
6894 tg3_save_pci_state(tp);
6896 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6897 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6898 tw32(GRC_FASTBOOT_PC, 0);
6901 * We must avoid the readl() that normally takes place.
6902 * It locks machines, causes machine checks, and other
6903 * fun things. So, temporarily disable the 5701
6904 * hardware workaround, while we do the reset.
6906 write_op = tp->write32;
6907 if (write_op == tg3_write_flush_reg32)
6908 tp->write32 = tg3_write32;
6910 /* Prevent the irq handler from reading or writing PCI registers
6911 * during chip reset when the memory enable bit in the PCI command
6912 * register may be cleared. The chip does not generate interrupt
6913 * at this time, but the irq handler may still be called due to irq
6914 * sharing or irqpoll.
6916 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6917 for (i = 0; i < tp->irq_cnt; i++) {
6918 struct tg3_napi *tnapi = &tp->napi[i];
6919 if (tnapi->hw_status) {
6920 tnapi->hw_status->status = 0;
6921 tnapi->hw_status->status_tag = 0;
6923 tnapi->last_tag = 0;
6924 tnapi->last_irq_tag = 0;
6928 for (i = 0; i < tp->irq_cnt; i++)
6929 synchronize_irq(tp->napi[i].irq_vec);
6931 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6932 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6933 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6937 val = GRC_MISC_CFG_CORECLK_RESET;
6939 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6940 /* Force PCIe 1.0a mode */
6941 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
6942 !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
6943 tr32(TG3_PCIE_PHY_TSTCTL) ==
6944 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
6945 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
6947 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6948 tw32(GRC_MISC_CFG, (1 << 29));
6953 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6954 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6955 tw32(GRC_VCPU_EXT_CTRL,
6956 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6959 /* Manage gphy power for all CPMU absent PCIe devices. */
6960 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6961 !(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
6962 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6964 tw32(GRC_MISC_CFG, val);
6966 /* restore 5701 hardware bug workaround write method */
6967 tp->write32 = write_op;
6969 /* Unfortunately, we have to delay before the PCI read back.
6970 * Some 575X chips even will not respond to a PCI cfg access
6971 * when the reset command is given to the chip.
6973 * How do these hardware designers expect things to work
6974 * properly if the PCI write is posted for a long period
6975 * of time? It is always necessary to have some method by
6976 * which a register read back can occur to push the write
6977 * out which does the reset.
6979 * For most tg3 variants the trick below was working.
6984 /* Flush PCI posted writes. The normal MMIO registers
6985 * are inaccessible at this time so this is the only
6986 * way to make this reliably (actually, this is no longer
6987 * the case, see above). I tried to use indirect
6988 * register read/write but this upset some 5701 variants.
6990 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6994 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6997 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
7001 /* Wait for link training to complete. */
7002 for (i = 0; i < 5000; i++)
7005 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
7006 pci_write_config_dword(tp->pdev, 0xc4,
7007 cfg_val | (1 << 15));
7010 /* Clear the "no snoop" and "relaxed ordering" bits. */
7011 pci_read_config_word(tp->pdev,
7012 tp->pcie_cap + PCI_EXP_DEVCTL,
7014 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
7015 PCI_EXP_DEVCTL_NOSNOOP_EN);
7017 * Older PCIe devices only support the 128 byte
7018 * MPS setting. Enforce the restriction.
7020 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7021 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
7022 pci_write_config_word(tp->pdev,
7023 tp->pcie_cap + PCI_EXP_DEVCTL,
7026 pcie_set_readrq(tp->pdev, 4096);
7028 /* Clear error status */
7029 pci_write_config_word(tp->pdev,
7030 tp->pcie_cap + PCI_EXP_DEVSTA,
7031 PCI_EXP_DEVSTA_CED |
7032 PCI_EXP_DEVSTA_NFED |
7033 PCI_EXP_DEVSTA_FED |
7034 PCI_EXP_DEVSTA_URD);
7037 tg3_restore_pci_state(tp);
7039 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
7042 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
7043 val = tr32(MEMARB_MODE);
7044 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7046 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7048 tw32(0x5000, 0x400);
7051 tw32(GRC_MODE, tp->grc_mode);
7053 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
7056 tw32(0xc4, val | (1 << 15));
7059 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7060 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7061 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7062 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7063 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7064 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7067 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7068 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
7069 tw32_f(MAC_MODE, tp->mac_mode);
7070 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7071 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
7072 tw32_f(MAC_MODE, tp->mac_mode);
7073 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7074 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
7075 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
7076 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
7077 tw32_f(MAC_MODE, tp->mac_mode);
7079 tw32_f(MAC_MODE, 0);
7082 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7084 err = tg3_poll_fw(tp);
7090 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
7091 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7092 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7093 !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
7096 tw32(0x7c00, val | (1 << 25));
7099 /* Reprobe ASF enable state. */
7100 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7101 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7102 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7103 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7106 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7107 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7108 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7109 tp->last_event_jiffies = jiffies;
7110 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7111 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7118 /* tp->lock is held. */
7119 static void tg3_stop_fw(struct tg3 *tp)
7121 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7122 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7123 /* Wait for RX cpu to ACK the previous event. */
7124 tg3_wait_for_event_ack(tp);
7126 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7128 tg3_generate_fw_event(tp);
7130 /* Wait for RX cpu to ACK this event. */
7131 tg3_wait_for_event_ack(tp);
7135 /* tp->lock is held. */
7136 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7142 tg3_write_sig_pre_reset(tp, kind);
7144 tg3_abort_hw(tp, silent);
7145 err = tg3_chip_reset(tp);
7147 __tg3_set_mac_addr(tp, 0);
7149 tg3_write_sig_legacy(tp, kind);
7150 tg3_write_sig_post_reset(tp, kind);
7158 #define RX_CPU_SCRATCH_BASE 0x30000
7159 #define RX_CPU_SCRATCH_SIZE 0x04000
7160 #define TX_CPU_SCRATCH_BASE 0x34000
7161 #define TX_CPU_SCRATCH_SIZE 0x04000
7163 /* tp->lock is held. */
7164 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7168 BUG_ON(offset == TX_CPU_BASE &&
7169 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7171 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7172 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7174 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7177 if (offset == RX_CPU_BASE) {
7178 for (i = 0; i < 10000; i++) {
7179 tw32(offset + CPU_STATE, 0xffffffff);
7180 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7181 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7185 tw32(offset + CPU_STATE, 0xffffffff);
7186 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
7189 for (i = 0; i < 10000; i++) {
7190 tw32(offset + CPU_STATE, 0xffffffff);
7191 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7192 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7198 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7199 __func__, offset == RX_CPU_BASE ? "RX" : "TX");
7203 /* Clear firmware's nvram arbitration. */
7204 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7205 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7210 unsigned int fw_base;
7211 unsigned int fw_len;
7212 const __be32 *fw_data;
7215 /* tp->lock is held. */
7216 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7217 int cpu_scratch_size, struct fw_info *info)
7219 int err, lock_err, i;
7220 void (*write_op)(struct tg3 *, u32, u32);
7222 if (cpu_base == TX_CPU_BASE &&
7223 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7225 "%s: Trying to load TX cpu firmware which is 5705\n",
7230 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7231 write_op = tg3_write_mem;
7233 write_op = tg3_write_indirect_reg32;
7235 /* It is possible that bootcode is still loading at this point.
7236 * Get the nvram lock first before halting the cpu.
7238 lock_err = tg3_nvram_lock(tp);
7239 err = tg3_halt_cpu(tp, cpu_base);
7241 tg3_nvram_unlock(tp);
7245 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7246 write_op(tp, cpu_scratch_base + i, 0);
7247 tw32(cpu_base + CPU_STATE, 0xffffffff);
7248 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7249 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7250 write_op(tp, (cpu_scratch_base +
7251 (info->fw_base & 0xffff) +
7253 be32_to_cpu(info->fw_data[i]));
7261 /* tp->lock is held. */
7262 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7264 struct fw_info info;
7265 const __be32 *fw_data;
7268 fw_data = (void *)tp->fw->data;
7270 /* Firmware blob starts with version numbers, followed by
7271 start address and length. We are setting complete length.
7272 length = end_address_of_bss - start_address_of_text.
7273 Remainder is the blob to be loaded contiguously
7274 from start address. */
7276 info.fw_base = be32_to_cpu(fw_data[1]);
7277 info.fw_len = tp->fw->size - 12;
7278 info.fw_data = &fw_data[3];
7280 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7281 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7286 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7287 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7292 /* Now startup only the RX cpu. */
7293 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7294 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7296 for (i = 0; i < 5; i++) {
7297 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7299 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7300 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
7301 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7305 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7306 "should be %08x\n", __func__,
7307 tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
7310 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7311 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
7316 /* 5705 needs a special version of the TSO firmware. */
7318 /* tp->lock is held. */
7319 static int tg3_load_tso_firmware(struct tg3 *tp)
7321 struct fw_info info;
7322 const __be32 *fw_data;
7323 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7326 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7329 fw_data = (void *)tp->fw->data;
7331 /* Firmware blob starts with version numbers, followed by
7332 start address and length. We are setting complete length.
7333 length = end_address_of_bss - start_address_of_text.
7334 Remainder is the blob to be loaded contiguously
7335 from start address. */
7337 info.fw_base = be32_to_cpu(fw_data[1]);
7338 cpu_scratch_size = tp->fw_len;
7339 info.fw_len = tp->fw->size - 12;
7340 info.fw_data = &fw_data[3];
7342 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7343 cpu_base = RX_CPU_BASE;
7344 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7346 cpu_base = TX_CPU_BASE;
7347 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7348 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7351 err = tg3_load_firmware_cpu(tp, cpu_base,
7352 cpu_scratch_base, cpu_scratch_size,
7357 /* Now startup the cpu. */
7358 tw32(cpu_base + CPU_STATE, 0xffffffff);
7359 tw32_f(cpu_base + CPU_PC, info.fw_base);
7361 for (i = 0; i < 5; i++) {
7362 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7364 tw32(cpu_base + CPU_STATE, 0xffffffff);
7365 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
7366 tw32_f(cpu_base + CPU_PC, info.fw_base);
7371 "%s fails to set CPU PC, is %08x should be %08x\n",
7372 __func__, tr32(cpu_base + CPU_PC), info.fw_base);
7375 tw32(cpu_base + CPU_STATE, 0xffffffff);
7376 tw32_f(cpu_base + CPU_MODE, 0x00000000);
7381 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7383 struct tg3 *tp = netdev_priv(dev);
7384 struct sockaddr *addr = p;
7385 int err = 0, skip_mac_1 = 0;
7387 if (!is_valid_ether_addr(addr->sa_data))
7390 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7392 if (!netif_running(dev))
7395 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7396 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7398 addr0_high = tr32(MAC_ADDR_0_HIGH);
7399 addr0_low = tr32(MAC_ADDR_0_LOW);
7400 addr1_high = tr32(MAC_ADDR_1_HIGH);
7401 addr1_low = tr32(MAC_ADDR_1_LOW);
7403 /* Skip MAC addr 1 if ASF is using it. */
7404 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7405 !(addr1_high == 0 && addr1_low == 0))
7408 spin_lock_bh(&tp->lock);
7409 __tg3_set_mac_addr(tp, skip_mac_1);
7410 spin_unlock_bh(&tp->lock);
7415 /* tp->lock is held. */
7416 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7417 dma_addr_t mapping, u32 maxlen_flags,
7421 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7422 ((u64) mapping >> 32));
7424 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7425 ((u64) mapping & 0xffffffff));
7427 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7430 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7432 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7436 static void __tg3_set_rx_mode(struct net_device *);
7437 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7441 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7442 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7443 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7444 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7446 tw32(HOSTCC_TXCOL_TICKS, 0);
7447 tw32(HOSTCC_TXMAX_FRAMES, 0);
7448 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7451 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
7452 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7453 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7454 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7456 tw32(HOSTCC_RXCOL_TICKS, 0);
7457 tw32(HOSTCC_RXMAX_FRAMES, 0);
7458 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7461 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7462 u32 val = ec->stats_block_coalesce_usecs;
7464 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7465 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7467 if (!netif_carrier_ok(tp->dev))
7470 tw32(HOSTCC_STAT_COAL_TICKS, val);
7473 for (i = 0; i < tp->irq_cnt - 1; i++) {
7476 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7477 tw32(reg, ec->rx_coalesce_usecs);
7478 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7479 tw32(reg, ec->rx_max_coalesced_frames);
7480 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7481 tw32(reg, ec->rx_max_coalesced_frames_irq);
7483 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7484 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7485 tw32(reg, ec->tx_coalesce_usecs);
7486 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7487 tw32(reg, ec->tx_max_coalesced_frames);
7488 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7489 tw32(reg, ec->tx_max_coalesced_frames_irq);
7493 for (; i < tp->irq_max - 1; i++) {
7494 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7495 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7496 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7498 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7499 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7500 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7501 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7506 /* tp->lock is held. */
7507 static void tg3_rings_reset(struct tg3 *tp)
7510 u32 stblk, txrcb, rxrcb, limit;
7511 struct tg3_napi *tnapi = &tp->napi[0];
7513 /* Disable all transmit rings but the first. */
7514 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7515 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7516 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7517 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7519 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7521 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7522 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7523 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7524 BDINFO_FLAGS_DISABLED);
7527 /* Disable all receive return rings but the first. */
7528 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7529 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7530 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7531 else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7532 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7533 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7534 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7535 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7537 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7539 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7540 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7541 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7542 BDINFO_FLAGS_DISABLED);
7544 /* Disable interrupts */
7545 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7547 /* Zero mailbox registers. */
7548 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7549 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7550 tp->napi[i].tx_prod = 0;
7551 tp->napi[i].tx_cons = 0;
7552 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7553 tw32_mailbox(tp->napi[i].prodmbox, 0);
7554 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7555 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7557 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7558 tw32_mailbox(tp->napi[0].prodmbox, 0);
7560 tp->napi[0].tx_prod = 0;
7561 tp->napi[0].tx_cons = 0;
7562 tw32_mailbox(tp->napi[0].prodmbox, 0);
7563 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7566 /* Make sure the NIC-based send BD rings are disabled. */
7567 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7568 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7569 for (i = 0; i < 16; i++)
7570 tw32_tx_mbox(mbox + i * 8, 0);
7573 txrcb = NIC_SRAM_SEND_RCB;
7574 rxrcb = NIC_SRAM_RCV_RET_RCB;
7576 /* Clear status block in ram. */
7577 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7579 /* Set status block DMA address */
7580 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7581 ((u64) tnapi->status_mapping >> 32));
7582 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7583 ((u64) tnapi->status_mapping & 0xffffffff));
7585 if (tnapi->tx_ring) {
7586 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7587 (TG3_TX_RING_SIZE <<
7588 BDINFO_FLAGS_MAXLEN_SHIFT),
7589 NIC_SRAM_TX_BUFFER_DESC);
7590 txrcb += TG3_BDINFO_SIZE;
7593 if (tnapi->rx_rcb) {
7594 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7595 (TG3_RX_RCB_RING_SIZE(tp) <<
7596 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7597 rxrcb += TG3_BDINFO_SIZE;
7600 stblk = HOSTCC_STATBLCK_RING1;
7602 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7603 u64 mapping = (u64)tnapi->status_mapping;
7604 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7605 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7607 /* Clear status block in ram. */
7608 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7610 if (tnapi->tx_ring) {
7611 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7612 (TG3_TX_RING_SIZE <<
7613 BDINFO_FLAGS_MAXLEN_SHIFT),
7614 NIC_SRAM_TX_BUFFER_DESC);
7615 txrcb += TG3_BDINFO_SIZE;
7618 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7619 (TG3_RX_RCB_RING_SIZE(tp) <<
7620 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7623 rxrcb += TG3_BDINFO_SIZE;
7627 /* tp->lock is held. */
7628 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7630 u32 val, rdmac_mode;
7632 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
7634 tg3_disable_ints(tp);
7638 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7640 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
7641 tg3_abort_hw(tp, 1);
7646 err = tg3_chip_reset(tp);
7650 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7652 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7653 val = tr32(TG3_CPMU_CTRL);
7654 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7655 tw32(TG3_CPMU_CTRL, val);
7657 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7658 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7659 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7660 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7662 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7663 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7664 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7665 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7667 val = tr32(TG3_CPMU_HST_ACC);
7668 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7669 val |= CPMU_HST_ACC_MACCLK_6_25;
7670 tw32(TG3_CPMU_HST_ACC, val);
7673 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7674 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7675 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7676 PCIE_PWR_MGMT_L1_THRESH_4MS;
7677 tw32(PCIE_PWR_MGMT_THRESH, val);
7679 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7680 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7682 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7684 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7685 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7688 if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7689 u32 grc_mode = tr32(GRC_MODE);
7691 /* Access the lower 1K of PL PCIE block registers. */
7692 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7693 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7695 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7696 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7697 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7699 tw32(GRC_MODE, grc_mode);
7702 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
7703 u32 grc_mode = tr32(GRC_MODE);
7705 /* Access the lower 1K of PL PCIE block registers. */
7706 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7707 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7709 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5);
7710 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
7711 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
7713 tw32(GRC_MODE, grc_mode);
7715 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7716 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7717 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7718 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7721 /* This works around an issue with Athlon chipsets on
7722 * B3 tigon3 silicon. This bit has no effect on any
7723 * other revision. But do not set this on PCI Express
7724 * chips and don't even touch the clocks if the CPMU is present.
7726 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7727 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7728 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7729 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7732 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7733 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7734 val = tr32(TG3PCI_PCISTATE);
7735 val |= PCISTATE_RETRY_SAME_DMA;
7736 tw32(TG3PCI_PCISTATE, val);
7739 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7740 /* Allow reads and writes to the
7741 * APE register and memory space.
7743 val = tr32(TG3PCI_PCISTATE);
7744 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7745 PCISTATE_ALLOW_APE_SHMEM_WR |
7746 PCISTATE_ALLOW_APE_PSPACE_WR;
7747 tw32(TG3PCI_PCISTATE, val);
7750 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7751 /* Enable some hw fixes. */
7752 val = tr32(TG3PCI_MSI_DATA);
7753 val |= (1 << 26) | (1 << 28) | (1 << 29);
7754 tw32(TG3PCI_MSI_DATA, val);
7757 /* Descriptor ring init may make accesses to the
7758 * NIC SRAM area to setup the TX descriptors, so we
7759 * can only do this after the hardware has been
7760 * successfully reset.
7762 err = tg3_init_rings(tp);
7766 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
7767 val = tr32(TG3PCI_DMA_RW_CTRL) &
7768 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7769 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
7770 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
7771 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7772 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7773 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7774 /* This value is determined during the probe time DMA
7775 * engine test, tg3_test_dma.
7777 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7780 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7781 GRC_MODE_4X_NIC_SEND_RINGS |
7782 GRC_MODE_NO_TX_PHDR_CSUM |
7783 GRC_MODE_NO_RX_PHDR_CSUM);
7784 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7786 /* Pseudo-header checksum is done by hardware logic and not
7787 * the offload processers, so make the chip do the pseudo-
7788 * header checksums on receive. For transmit it is more
7789 * convenient to do the pseudo-header checksum in software
7790 * as Linux does that on transmit for us in all cases.
7792 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7796 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7798 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7799 val = tr32(GRC_MISC_CFG);
7801 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7802 tw32(GRC_MISC_CFG, val);
7804 /* Initialize MBUF/DESC pool. */
7805 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7807 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7808 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7809 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7810 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7812 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7813 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7814 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7815 } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7818 fw_len = tp->fw_len;
7819 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7820 tw32(BUFMGR_MB_POOL_ADDR,
7821 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7822 tw32(BUFMGR_MB_POOL_SIZE,
7823 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7826 if (tp->dev->mtu <= ETH_DATA_LEN) {
7827 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7828 tp->bufmgr_config.mbuf_read_dma_low_water);
7829 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7830 tp->bufmgr_config.mbuf_mac_rx_low_water);
7831 tw32(BUFMGR_MB_HIGH_WATER,
7832 tp->bufmgr_config.mbuf_high_water);
7834 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7835 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7836 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7837 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7838 tw32(BUFMGR_MB_HIGH_WATER,
7839 tp->bufmgr_config.mbuf_high_water_jumbo);
7841 tw32(BUFMGR_DMA_LOW_WATER,
7842 tp->bufmgr_config.dma_low_water);
7843 tw32(BUFMGR_DMA_HIGH_WATER,
7844 tp->bufmgr_config.dma_high_water);
7846 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7847 for (i = 0; i < 2000; i++) {
7848 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7853 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
7857 /* Setup replenish threshold. */
7858 val = tp->rx_pending / 8;
7861 else if (val > tp->rx_std_max_post)
7862 val = tp->rx_std_max_post;
7863 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7864 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7865 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7867 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7868 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7871 tw32(RCVBDI_STD_THRESH, val);
7873 /* Initialize TG3_BDINFO's at:
7874 * RCVDBDI_STD_BD: standard eth size rx ring
7875 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7876 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7879 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7880 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7881 * ring attribute flags
7882 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7884 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7885 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7887 * The size of each ring is fixed in the firmware, but the location is
7890 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7891 ((u64) tpr->rx_std_mapping >> 32));
7892 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7893 ((u64) tpr->rx_std_mapping & 0xffffffff));
7894 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
7895 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
7896 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7897 NIC_SRAM_RX_BUFFER_DESC);
7899 /* Disable the mini ring */
7900 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7901 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7902 BDINFO_FLAGS_DISABLED);
7904 /* Program the jumbo buffer descriptor ring control
7905 * blocks on those devices that have them.
7907 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7908 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7909 /* Setup replenish threshold. */
7910 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7912 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7913 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7914 ((u64) tpr->rx_jmb_mapping >> 32));
7915 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7916 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7917 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7918 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7919 BDINFO_FLAGS_USE_EXT_RECV);
7920 if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) ||
7921 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7922 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7923 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7925 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7926 BDINFO_FLAGS_DISABLED);
7929 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
7930 val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7931 (TG3_RX_STD_DMA_SZ << 2);
7933 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
7935 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7937 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7939 tpr->rx_std_prod_idx = tp->rx_pending;
7940 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
7942 tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7943 tp->rx_jumbo_pending : 0;
7944 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
7946 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
7947 tw32(STD_REPLENISH_LWM, 32);
7948 tw32(JMB_REPLENISH_LWM, 16);
7951 tg3_rings_reset(tp);
7953 /* Initialize MAC address and backoff seed. */
7954 __tg3_set_mac_addr(tp, 0);
7956 /* MTU + ethernet header + FCS + optional VLAN tag */
7957 tw32(MAC_RX_MTU_SIZE,
7958 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7960 /* The slot time is changed by tg3_setup_phy if we
7961 * run at gigabit with half duplex.
7963 tw32(MAC_TX_LENGTHS,
7964 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7965 (6 << TX_LENGTHS_IPG_SHIFT) |
7966 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7968 /* Receive rules. */
7969 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7970 tw32(RCVLPC_CONFIG, 0x0181);
7972 /* Calculate RDMAC_MODE setting early, we need it to determine
7973 * the RCVLPC_STATE_ENABLE mask.
7975 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7976 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7977 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7978 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7979 RDMAC_MODE_LNGREAD_ENAB);
7981 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7982 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7983 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
7985 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7986 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7987 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7988 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7989 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7990 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7992 /* If statement applies to 5705 and 5750 PCI devices only */
7993 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7994 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7995 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7996 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7997 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7998 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7999 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8000 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
8001 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8005 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
8006 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8008 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8009 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8011 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
8012 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8013 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8014 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
8016 /* Receive/send statistics. */
8017 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
8018 val = tr32(RCVLPC_STATS_ENABLE);
8019 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8020 tw32(RCVLPC_STATS_ENABLE, val);
8021 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8022 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8023 val = tr32(RCVLPC_STATS_ENABLE);
8024 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8025 tw32(RCVLPC_STATS_ENABLE, val);
8027 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8029 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8030 tw32(SNDDATAI_STATSENAB, 0xffffff);
8031 tw32(SNDDATAI_STATSCTRL,
8032 (SNDDATAI_SCTRL_ENABLE |
8033 SNDDATAI_SCTRL_FASTUPD));
8035 /* Setup host coalescing engine. */
8036 tw32(HOSTCC_MODE, 0);
8037 for (i = 0; i < 2000; i++) {
8038 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8043 __tg3_set_coalesce(tp, &tp->coal);
8045 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8046 /* Status/statistics block address. See tg3_timer,
8047 * the tg3_periodic_fetch_stats call there, and
8048 * tg3_get_stats to see how this works for 5705/5750 chips.
8050 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8051 ((u64) tp->stats_mapping >> 32));
8052 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8053 ((u64) tp->stats_mapping & 0xffffffff));
8054 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8056 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
8058 /* Clear statistics and status block memory areas */
8059 for (i = NIC_SRAM_STATS_BLK;
8060 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8062 tg3_write_mem(tp, i, 0);
8067 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8069 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8070 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8071 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8072 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8074 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8075 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
8076 /* reset to prevent losing 1st rx packet intermittently */
8077 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8081 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8082 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8085 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8086 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
8087 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8088 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8089 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8090 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8091 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8094 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8095 * If TG3_FLG2_IS_NIC is zero, we should read the
8096 * register to preserve the GPIO settings for LOMs. The GPIOs,
8097 * whether used as inputs or outputs, are set by boot code after
8100 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
8103 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8104 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8105 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8107 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8108 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8109 GRC_LCLCTRL_GPIO_OUTPUT3;
8111 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8112 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8114 tp->grc_local_ctrl &= ~gpio_mask;
8115 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8117 /* GPIO1 must be driven high for eeprom write protect */
8118 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8119 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8120 GRC_LCLCTRL_GPIO_OUTPUT1);
8122 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8125 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
8126 val = tr32(MSGINT_MODE);
8127 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8128 tw32(MSGINT_MODE, val);
8131 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8132 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8136 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8137 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8138 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8139 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8140 WDMAC_MODE_LNGREAD_ENAB);
8142 /* If statement applies to 5705 and 5750 PCI devices only */
8143 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8144 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8145 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
8146 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8147 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8148 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8150 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8151 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8152 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8153 val |= WDMAC_MODE_RX_ACCEL;
8157 /* Enable host coalescing bug fix */
8158 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8159 val |= WDMAC_MODE_STATUS_TAG_FIX;
8161 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8162 val |= WDMAC_MODE_BURST_ALL_DATA;
8164 tw32_f(WDMAC_MODE, val);
8167 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8170 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8172 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8173 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8174 pcix_cmd |= PCI_X_CMD_READ_2K;
8175 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8176 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8177 pcix_cmd |= PCI_X_CMD_READ_2K;
8179 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8183 tw32_f(RDMAC_MODE, rdmac_mode);
8186 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8187 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8188 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8190 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8192 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8194 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8196 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8197 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8198 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8199 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8200 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8201 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8202 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8203 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8204 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8205 tw32(SNDBDI_MODE, val);
8206 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8208 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8209 err = tg3_load_5701_a0_firmware_fix(tp);
8214 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8215 err = tg3_load_tso_firmware(tp);
8220 tp->tx_mode = TX_MODE_ENABLE;
8221 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
8222 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8223 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
8224 tw32_f(MAC_TX_MODE, tp->tx_mode);
8227 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8228 u32 reg = MAC_RSS_INDIR_TBL_0;
8229 u8 *ent = (u8 *)&val;
8231 /* Setup the indirection table */
8232 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8233 int idx = i % sizeof(val);
8235 ent[idx] = i % (tp->irq_cnt - 1);
8236 if (idx == sizeof(val) - 1) {
8242 /* Setup the "secret" hash key. */
8243 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8244 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8245 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8246 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8247 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8248 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8249 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8250 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8251 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8252 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8255 tp->rx_mode = RX_MODE_ENABLE;
8256 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8257 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8259 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8260 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8261 RX_MODE_RSS_ITBL_HASH_BITS_7 |
8262 RX_MODE_RSS_IPV6_HASH_EN |
8263 RX_MODE_RSS_TCP_IPV6_HASH_EN |
8264 RX_MODE_RSS_IPV4_HASH_EN |
8265 RX_MODE_RSS_TCP_IPV4_HASH_EN;
8267 tw32_f(MAC_RX_MODE, tp->rx_mode);
8270 tw32(MAC_LED_CTRL, tp->led_ctrl);
8272 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8273 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8274 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8277 tw32_f(MAC_RX_MODE, tp->rx_mode);
8280 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8281 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8282 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
8283 /* Set drive transmission level to 1.2V */
8284 /* only if the signal pre-emphasis bit is not set */
8285 val = tr32(MAC_SERDES_CFG);
8288 tw32(MAC_SERDES_CFG, val);
8290 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8291 tw32(MAC_SERDES_CFG, 0x616000);
8294 /* Prevent chip from dropping frames when flow control
8297 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8301 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8303 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8304 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8305 /* Use hardware link auto-negotiation */
8306 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8309 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8310 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8313 tmp = tr32(SERDES_RX_CTRL);
8314 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8315 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8316 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8317 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8320 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8321 if (tp->link_config.phy_is_low_power) {
8322 tp->link_config.phy_is_low_power = 0;
8323 tp->link_config.speed = tp->link_config.orig_speed;
8324 tp->link_config.duplex = tp->link_config.orig_duplex;
8325 tp->link_config.autoneg = tp->link_config.orig_autoneg;
8328 err = tg3_setup_phy(tp, 0);
8332 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8333 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
8336 /* Clear CRC stats. */
8337 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8338 tg3_writephy(tp, MII_TG3_TEST1,
8339 tmp | MII_TG3_TEST1_CRC_EN);
8340 tg3_readphy(tp, 0x14, &tmp);
8345 __tg3_set_rx_mode(tp->dev);
8347 /* Initialize receive rules. */
8348 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
8349 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8350 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
8351 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8353 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8354 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8358 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8362 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
8364 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
8366 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
8368 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
8370 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
8372 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
8374 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
8376 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
8378 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
8380 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
8382 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
8384 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
8386 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
8388 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
8396 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8397 /* Write our heartbeat update interval to APE. */
8398 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8399 APE_HOST_HEARTBEAT_INT_DISABLE);
8401 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8406 /* Called at device open time to get the chip ready for
8407 * packet processing. Invoked with tp->lock held.
8409 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8411 tg3_switch_clocks(tp);
8413 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8415 return tg3_reset_hw(tp, reset_phy);
8418 #define TG3_STAT_ADD32(PSTAT, REG) \
8419 do { u32 __val = tr32(REG); \
8420 (PSTAT)->low += __val; \
8421 if ((PSTAT)->low < __val) \
8422 (PSTAT)->high += 1; \
8425 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8427 struct tg3_hw_stats *sp = tp->hw_stats;
8429 if (!netif_carrier_ok(tp->dev))
8432 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8433 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8434 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8435 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8436 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8437 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8438 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8439 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8440 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8441 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8442 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8443 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8444 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8446 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8447 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8448 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8449 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8450 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8451 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8452 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8453 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8454 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8455 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8456 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8457 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8458 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8459 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8461 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8462 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8463 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8466 static void tg3_timer(unsigned long __opaque)
8468 struct tg3 *tp = (struct tg3 *) __opaque;
8473 spin_lock(&tp->lock);
8475 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8476 /* All of this garbage is because when using non-tagged
8477 * IRQ status the mailbox/status_block protocol the chip
8478 * uses with the cpu is race prone.
8480 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8481 tw32(GRC_LOCAL_CTRL,
8482 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8484 tw32(HOSTCC_MODE, tp->coalesce_mode |
8485 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8488 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8489 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8490 spin_unlock(&tp->lock);
8491 schedule_work(&tp->reset_task);
8496 /* This part only runs once per second. */
8497 if (!--tp->timer_counter) {
8498 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8499 tg3_periodic_fetch_stats(tp);
8501 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8505 mac_stat = tr32(MAC_STATUS);
8508 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8509 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8511 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8515 tg3_setup_phy(tp, 0);
8516 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8517 u32 mac_stat = tr32(MAC_STATUS);
8520 if (netif_carrier_ok(tp->dev) &&
8521 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8524 if (!netif_carrier_ok(tp->dev) &&
8525 (mac_stat & (MAC_STATUS_PCS_SYNCED |
8526 MAC_STATUS_SIGNAL_DET))) {
8530 if (!tp->serdes_counter) {
8533 ~MAC_MODE_PORT_MODE_MASK));
8535 tw32_f(MAC_MODE, tp->mac_mode);
8538 tg3_setup_phy(tp, 0);
8540 } else if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8541 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8542 tg3_serdes_parallel_detect(tp);
8545 tp->timer_counter = tp->timer_multiplier;
8548 /* Heartbeat is only sent once every 2 seconds.
8550 * The heartbeat is to tell the ASF firmware that the host
8551 * driver is still alive. In the event that the OS crashes,
8552 * ASF needs to reset the hardware to free up the FIFO space
8553 * that may be filled with rx packets destined for the host.
8554 * If the FIFO is full, ASF will no longer function properly.
8556 * Unintended resets have been reported on real time kernels
8557 * where the timer doesn't run on time. Netpoll will also have
8560 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8561 * to check the ring condition when the heartbeat is expiring
8562 * before doing the reset. This will prevent most unintended
8565 if (!--tp->asf_counter) {
8566 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8567 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8568 tg3_wait_for_event_ack(tp);
8570 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8571 FWCMD_NICDRV_ALIVE3);
8572 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8573 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
8574 TG3_FW_UPDATE_TIMEOUT_SEC);
8576 tg3_generate_fw_event(tp);
8578 tp->asf_counter = tp->asf_multiplier;
8581 spin_unlock(&tp->lock);
8584 tp->timer.expires = jiffies + tp->timer_offset;
8585 add_timer(&tp->timer);
8588 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8591 unsigned long flags;
8593 struct tg3_napi *tnapi = &tp->napi[irq_num];
8595 if (tp->irq_cnt == 1)
8596 name = tp->dev->name;
8598 name = &tnapi->irq_lbl[0];
8599 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8600 name[IFNAMSIZ-1] = 0;
8603 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8605 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8607 flags = IRQF_SAMPLE_RANDOM;
8610 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8611 fn = tg3_interrupt_tagged;
8612 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8615 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8618 static int tg3_test_interrupt(struct tg3 *tp)
8620 struct tg3_napi *tnapi = &tp->napi[0];
8621 struct net_device *dev = tp->dev;
8622 int err, i, intr_ok = 0;
8625 if (!netif_running(dev))
8628 tg3_disable_ints(tp);
8630 free_irq(tnapi->irq_vec, tnapi);
8633 * Turn off MSI one shot mode. Otherwise this test has no
8634 * observable way to know whether the interrupt was delivered.
8636 if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8637 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8638 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8639 tw32(MSGINT_MODE, val);
8642 err = request_irq(tnapi->irq_vec, tg3_test_isr,
8643 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8647 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8648 tg3_enable_ints(tp);
8650 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8653 for (i = 0; i < 5; i++) {
8654 u32 int_mbox, misc_host_ctrl;
8656 int_mbox = tr32_mailbox(tnapi->int_mbox);
8657 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8659 if ((int_mbox != 0) ||
8660 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8668 tg3_disable_ints(tp);
8670 free_irq(tnapi->irq_vec, tnapi);
8672 err = tg3_request_irq(tp, 0);
8678 /* Reenable MSI one shot mode. */
8679 if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8680 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8681 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8682 tw32(MSGINT_MODE, val);
8690 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8691 * successfully restored
8693 static int tg3_test_msi(struct tg3 *tp)
8698 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8701 /* Turn off SERR reporting in case MSI terminates with Master
8704 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8705 pci_write_config_word(tp->pdev, PCI_COMMAND,
8706 pci_cmd & ~PCI_COMMAND_SERR);
8708 err = tg3_test_interrupt(tp);
8710 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8715 /* other failures */
8719 /* MSI test failed, go back to INTx mode */
8720 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
8721 "to INTx mode. Please report this failure to the PCI "
8722 "maintainer and include system chipset information\n");
8724 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8726 pci_disable_msi(tp->pdev);
8728 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8729 tp->napi[0].irq_vec = tp->pdev->irq;
8731 err = tg3_request_irq(tp, 0);
8735 /* Need to reset the chip because the MSI cycle may have terminated
8736 * with Master Abort.
8738 tg3_full_lock(tp, 1);
8740 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8741 err = tg3_init_hw(tp, 1);
8743 tg3_full_unlock(tp);
8746 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8751 static int tg3_request_firmware(struct tg3 *tp)
8753 const __be32 *fw_data;
8755 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8756 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
8761 fw_data = (void *)tp->fw->data;
8763 /* Firmware blob starts with version numbers, followed by
8764 * start address and _full_ length including BSS sections
8765 * (which must be longer than the actual data, of course
8768 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
8769 if (tp->fw_len < (tp->fw->size - 12)) {
8770 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
8771 tp->fw_len, tp->fw_needed);
8772 release_firmware(tp->fw);
8777 /* We no longer need firmware; we have it. */
8778 tp->fw_needed = NULL;
8782 static bool tg3_enable_msix(struct tg3 *tp)
8784 int i, rc, cpus = num_online_cpus();
8785 struct msix_entry msix_ent[tp->irq_max];
8788 /* Just fallback to the simpler MSI mode. */
8792 * We want as many rx rings enabled as there are cpus.
8793 * The first MSIX vector only deals with link interrupts, etc,
8794 * so we add one to the number of vectors we are requesting.
8796 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8798 for (i = 0; i < tp->irq_max; i++) {
8799 msix_ent[i].entry = i;
8800 msix_ent[i].vector = 0;
8803 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8806 } else if (rc != 0) {
8807 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8809 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
8814 for (i = 0; i < tp->irq_max; i++)
8815 tp->napi[i].irq_vec = msix_ent[i].vector;
8817 tp->dev->real_num_tx_queues = 1;
8818 if (tp->irq_cnt > 1) {
8819 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8821 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8822 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
8823 tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
8824 tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8831 static void tg3_ints_init(struct tg3 *tp)
8833 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8834 !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8835 /* All MSI supporting chips should support tagged
8836 * status. Assert that this is the case.
8838 netdev_warn(tp->dev,
8839 "MSI without TAGGED_STATUS? Not using MSI\n");
8843 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8844 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8845 else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8846 pci_enable_msi(tp->pdev) == 0)
8847 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8849 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8850 u32 msi_mode = tr32(MSGINT_MODE);
8851 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8852 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8853 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8856 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8858 tp->napi[0].irq_vec = tp->pdev->irq;
8859 tp->dev->real_num_tx_queues = 1;
8863 static void tg3_ints_fini(struct tg3 *tp)
8865 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8866 pci_disable_msix(tp->pdev);
8867 else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8868 pci_disable_msi(tp->pdev);
8869 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8870 tp->tg3_flags3 &= ~(TG3_FLG3_ENABLE_RSS | TG3_FLG3_ENABLE_TSS);
8873 static int tg3_open(struct net_device *dev)
8875 struct tg3 *tp = netdev_priv(dev);
8878 if (tp->fw_needed) {
8879 err = tg3_request_firmware(tp);
8880 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8884 netdev_warn(tp->dev, "TSO capability disabled\n");
8885 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8886 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8887 netdev_notice(tp->dev, "TSO capability restored\n");
8888 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8892 netif_carrier_off(tp->dev);
8894 err = tg3_set_power_state(tp, PCI_D0);
8898 tg3_full_lock(tp, 0);
8900 tg3_disable_ints(tp);
8901 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8903 tg3_full_unlock(tp);
8906 * Setup interrupts first so we know how
8907 * many NAPI resources to allocate
8911 /* The placement of this call is tied
8912 * to the setup and use of Host TX descriptors.
8914 err = tg3_alloc_consistent(tp);
8918 tg3_napi_enable(tp);
8920 for (i = 0; i < tp->irq_cnt; i++) {
8921 struct tg3_napi *tnapi = &tp->napi[i];
8922 err = tg3_request_irq(tp, i);
8924 for (i--; i >= 0; i--)
8925 free_irq(tnapi->irq_vec, tnapi);
8933 tg3_full_lock(tp, 0);
8935 err = tg3_init_hw(tp, 1);
8937 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8940 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8941 tp->timer_offset = HZ;
8943 tp->timer_offset = HZ / 10;
8945 BUG_ON(tp->timer_offset > HZ);
8946 tp->timer_counter = tp->timer_multiplier =
8947 (HZ / tp->timer_offset);
8948 tp->asf_counter = tp->asf_multiplier =
8949 ((HZ / tp->timer_offset) * 2);
8951 init_timer(&tp->timer);
8952 tp->timer.expires = jiffies + tp->timer_offset;
8953 tp->timer.data = (unsigned long) tp;
8954 tp->timer.function = tg3_timer;
8957 tg3_full_unlock(tp);
8962 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8963 err = tg3_test_msi(tp);
8966 tg3_full_lock(tp, 0);
8967 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8969 tg3_full_unlock(tp);
8974 if (!(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8975 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8976 u32 val = tr32(PCIE_TRANSACTION_CFG);
8978 tw32(PCIE_TRANSACTION_CFG,
8979 val | PCIE_TRANS_CFG_1SHOT_MSI);
8985 tg3_full_lock(tp, 0);
8987 add_timer(&tp->timer);
8988 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8989 tg3_enable_ints(tp);
8991 tg3_full_unlock(tp);
8993 netif_tx_start_all_queues(dev);
8998 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8999 struct tg3_napi *tnapi = &tp->napi[i];
9000 free_irq(tnapi->irq_vec, tnapi);
9004 tg3_napi_disable(tp);
9005 tg3_free_consistent(tp);
9012 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
9013 struct rtnl_link_stats64 *);
9014 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9016 static int tg3_close(struct net_device *dev)
9019 struct tg3 *tp = netdev_priv(dev);
9021 tg3_napi_disable(tp);
9022 cancel_work_sync(&tp->reset_task);
9024 netif_tx_stop_all_queues(dev);
9026 del_timer_sync(&tp->timer);
9030 tg3_full_lock(tp, 1);
9032 tg3_disable_ints(tp);
9034 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9036 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9038 tg3_full_unlock(tp);
9040 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9041 struct tg3_napi *tnapi = &tp->napi[i];
9042 free_irq(tnapi->irq_vec, tnapi);
9047 tg3_get_stats64(tp->dev, &tp->net_stats_prev);
9049 memcpy(&tp->estats_prev, tg3_get_estats(tp),
9050 sizeof(tp->estats_prev));
9052 tg3_free_consistent(tp);
9054 tg3_set_power_state(tp, PCI_D3hot);
9056 netif_carrier_off(tp->dev);
9061 static inline u64 get_stat64(tg3_stat64_t *val)
9063 return ((u64)val->high << 32) | ((u64)val->low);
9066 static u64 calc_crc_errors(struct tg3 *tp)
9068 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9070 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9071 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9072 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9075 spin_lock_bh(&tp->lock);
9076 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9077 tg3_writephy(tp, MII_TG3_TEST1,
9078 val | MII_TG3_TEST1_CRC_EN);
9079 tg3_readphy(tp, 0x14, &val);
9082 spin_unlock_bh(&tp->lock);
9084 tp->phy_crc_errors += val;
9086 return tp->phy_crc_errors;
9089 return get_stat64(&hw_stats->rx_fcs_errors);
9092 #define ESTAT_ADD(member) \
9093 estats->member = old_estats->member + \
9094 get_stat64(&hw_stats->member)
9096 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9098 struct tg3_ethtool_stats *estats = &tp->estats;
9099 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9100 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9105 ESTAT_ADD(rx_octets);
9106 ESTAT_ADD(rx_fragments);
9107 ESTAT_ADD(rx_ucast_packets);
9108 ESTAT_ADD(rx_mcast_packets);
9109 ESTAT_ADD(rx_bcast_packets);
9110 ESTAT_ADD(rx_fcs_errors);
9111 ESTAT_ADD(rx_align_errors);
9112 ESTAT_ADD(rx_xon_pause_rcvd);
9113 ESTAT_ADD(rx_xoff_pause_rcvd);
9114 ESTAT_ADD(rx_mac_ctrl_rcvd);
9115 ESTAT_ADD(rx_xoff_entered);
9116 ESTAT_ADD(rx_frame_too_long_errors);
9117 ESTAT_ADD(rx_jabbers);
9118 ESTAT_ADD(rx_undersize_packets);
9119 ESTAT_ADD(rx_in_length_errors);
9120 ESTAT_ADD(rx_out_length_errors);
9121 ESTAT_ADD(rx_64_or_less_octet_packets);
9122 ESTAT_ADD(rx_65_to_127_octet_packets);
9123 ESTAT_ADD(rx_128_to_255_octet_packets);
9124 ESTAT_ADD(rx_256_to_511_octet_packets);
9125 ESTAT_ADD(rx_512_to_1023_octet_packets);
9126 ESTAT_ADD(rx_1024_to_1522_octet_packets);
9127 ESTAT_ADD(rx_1523_to_2047_octet_packets);
9128 ESTAT_ADD(rx_2048_to_4095_octet_packets);
9129 ESTAT_ADD(rx_4096_to_8191_octet_packets);
9130 ESTAT_ADD(rx_8192_to_9022_octet_packets);
9132 ESTAT_ADD(tx_octets);
9133 ESTAT_ADD(tx_collisions);
9134 ESTAT_ADD(tx_xon_sent);
9135 ESTAT_ADD(tx_xoff_sent);
9136 ESTAT_ADD(tx_flow_control);
9137 ESTAT_ADD(tx_mac_errors);
9138 ESTAT_ADD(tx_single_collisions);
9139 ESTAT_ADD(tx_mult_collisions);
9140 ESTAT_ADD(tx_deferred);
9141 ESTAT_ADD(tx_excessive_collisions);
9142 ESTAT_ADD(tx_late_collisions);
9143 ESTAT_ADD(tx_collide_2times);
9144 ESTAT_ADD(tx_collide_3times);
9145 ESTAT_ADD(tx_collide_4times);
9146 ESTAT_ADD(tx_collide_5times);
9147 ESTAT_ADD(tx_collide_6times);
9148 ESTAT_ADD(tx_collide_7times);
9149 ESTAT_ADD(tx_collide_8times);
9150 ESTAT_ADD(tx_collide_9times);
9151 ESTAT_ADD(tx_collide_10times);
9152 ESTAT_ADD(tx_collide_11times);
9153 ESTAT_ADD(tx_collide_12times);
9154 ESTAT_ADD(tx_collide_13times);
9155 ESTAT_ADD(tx_collide_14times);
9156 ESTAT_ADD(tx_collide_15times);
9157 ESTAT_ADD(tx_ucast_packets);
9158 ESTAT_ADD(tx_mcast_packets);
9159 ESTAT_ADD(tx_bcast_packets);
9160 ESTAT_ADD(tx_carrier_sense_errors);
9161 ESTAT_ADD(tx_discards);
9162 ESTAT_ADD(tx_errors);
9164 ESTAT_ADD(dma_writeq_full);
9165 ESTAT_ADD(dma_write_prioq_full);
9166 ESTAT_ADD(rxbds_empty);
9167 ESTAT_ADD(rx_discards);
9168 ESTAT_ADD(rx_errors);
9169 ESTAT_ADD(rx_threshold_hit);
9171 ESTAT_ADD(dma_readq_full);
9172 ESTAT_ADD(dma_read_prioq_full);
9173 ESTAT_ADD(tx_comp_queue_full);
9175 ESTAT_ADD(ring_set_send_prod_index);
9176 ESTAT_ADD(ring_status_update);
9177 ESTAT_ADD(nic_irqs);
9178 ESTAT_ADD(nic_avoided_irqs);
9179 ESTAT_ADD(nic_tx_threshold_hit);
9184 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
9185 struct rtnl_link_stats64 *stats)
9187 struct tg3 *tp = netdev_priv(dev);
9188 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
9189 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9194 stats->rx_packets = old_stats->rx_packets +
9195 get_stat64(&hw_stats->rx_ucast_packets) +
9196 get_stat64(&hw_stats->rx_mcast_packets) +
9197 get_stat64(&hw_stats->rx_bcast_packets);
9199 stats->tx_packets = old_stats->tx_packets +
9200 get_stat64(&hw_stats->tx_ucast_packets) +
9201 get_stat64(&hw_stats->tx_mcast_packets) +
9202 get_stat64(&hw_stats->tx_bcast_packets);
9204 stats->rx_bytes = old_stats->rx_bytes +
9205 get_stat64(&hw_stats->rx_octets);
9206 stats->tx_bytes = old_stats->tx_bytes +
9207 get_stat64(&hw_stats->tx_octets);
9209 stats->rx_errors = old_stats->rx_errors +
9210 get_stat64(&hw_stats->rx_errors);
9211 stats->tx_errors = old_stats->tx_errors +
9212 get_stat64(&hw_stats->tx_errors) +
9213 get_stat64(&hw_stats->tx_mac_errors) +
9214 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9215 get_stat64(&hw_stats->tx_discards);
9217 stats->multicast = old_stats->multicast +
9218 get_stat64(&hw_stats->rx_mcast_packets);
9219 stats->collisions = old_stats->collisions +
9220 get_stat64(&hw_stats->tx_collisions);
9222 stats->rx_length_errors = old_stats->rx_length_errors +
9223 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9224 get_stat64(&hw_stats->rx_undersize_packets);
9226 stats->rx_over_errors = old_stats->rx_over_errors +
9227 get_stat64(&hw_stats->rxbds_empty);
9228 stats->rx_frame_errors = old_stats->rx_frame_errors +
9229 get_stat64(&hw_stats->rx_align_errors);
9230 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9231 get_stat64(&hw_stats->tx_discards);
9232 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9233 get_stat64(&hw_stats->tx_carrier_sense_errors);
9235 stats->rx_crc_errors = old_stats->rx_crc_errors +
9236 calc_crc_errors(tp);
9238 stats->rx_missed_errors = old_stats->rx_missed_errors +
9239 get_stat64(&hw_stats->rx_discards);
9244 static inline u32 calc_crc(unsigned char *buf, int len)
9252 for (j = 0; j < len; j++) {
9255 for (k = 0; k < 8; k++) {
9268 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9270 /* accept or reject all multicast frames */
9271 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9272 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9273 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9274 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9277 static void __tg3_set_rx_mode(struct net_device *dev)
9279 struct tg3 *tp = netdev_priv(dev);
9282 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9283 RX_MODE_KEEP_VLAN_TAG);
9285 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9288 #if TG3_VLAN_TAG_USED
9290 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9291 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9293 /* By definition, VLAN is disabled always in this
9296 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9297 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9300 if (dev->flags & IFF_PROMISC) {
9301 /* Promiscuous mode. */
9302 rx_mode |= RX_MODE_PROMISC;
9303 } else if (dev->flags & IFF_ALLMULTI) {
9304 /* Accept all multicast. */
9305 tg3_set_multi(tp, 1);
9306 } else if (netdev_mc_empty(dev)) {
9307 /* Reject all multicast. */
9308 tg3_set_multi(tp, 0);
9310 /* Accept one or more multicast(s). */
9311 struct netdev_hw_addr *ha;
9312 u32 mc_filter[4] = { 0, };
9317 netdev_for_each_mc_addr(ha, dev) {
9318 crc = calc_crc(ha->addr, ETH_ALEN);
9320 regidx = (bit & 0x60) >> 5;
9322 mc_filter[regidx] |= (1 << bit);
9325 tw32(MAC_HASH_REG_0, mc_filter[0]);
9326 tw32(MAC_HASH_REG_1, mc_filter[1]);
9327 tw32(MAC_HASH_REG_2, mc_filter[2]);
9328 tw32(MAC_HASH_REG_3, mc_filter[3]);
9331 if (rx_mode != tp->rx_mode) {
9332 tp->rx_mode = rx_mode;
9333 tw32_f(MAC_RX_MODE, rx_mode);
9338 static void tg3_set_rx_mode(struct net_device *dev)
9340 struct tg3 *tp = netdev_priv(dev);
9342 if (!netif_running(dev))
9345 tg3_full_lock(tp, 0);
9346 __tg3_set_rx_mode(dev);
9347 tg3_full_unlock(tp);
9350 #define TG3_REGDUMP_LEN (32 * 1024)
9352 static int tg3_get_regs_len(struct net_device *dev)
9354 return TG3_REGDUMP_LEN;
9357 static void tg3_get_regs(struct net_device *dev,
9358 struct ethtool_regs *regs, void *_p)
9361 struct tg3 *tp = netdev_priv(dev);
9367 memset(p, 0, TG3_REGDUMP_LEN);
9369 if (tp->link_config.phy_is_low_power)
9372 tg3_full_lock(tp, 0);
9374 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
9375 #define GET_REG32_LOOP(base, len) \
9376 do { p = (u32 *)(orig_p + (base)); \
9377 for (i = 0; i < len; i += 4) \
9378 __GET_REG32((base) + i); \
9380 #define GET_REG32_1(reg) \
9381 do { p = (u32 *)(orig_p + (reg)); \
9382 __GET_REG32((reg)); \
9385 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9386 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9387 GET_REG32_LOOP(MAC_MODE, 0x4f0);
9388 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9389 GET_REG32_1(SNDDATAC_MODE);
9390 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9391 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9392 GET_REG32_1(SNDBDC_MODE);
9393 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9394 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9395 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9396 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9397 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9398 GET_REG32_1(RCVDCC_MODE);
9399 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9400 GET_REG32_LOOP(RCVCC_MODE, 0x14);
9401 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9402 GET_REG32_1(MBFREE_MODE);
9403 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9404 GET_REG32_LOOP(MEMARB_MODE, 0x10);
9405 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9406 GET_REG32_LOOP(RDMAC_MODE, 0x08);
9407 GET_REG32_LOOP(WDMAC_MODE, 0x08);
9408 GET_REG32_1(RX_CPU_MODE);
9409 GET_REG32_1(RX_CPU_STATE);
9410 GET_REG32_1(RX_CPU_PGMCTR);
9411 GET_REG32_1(RX_CPU_HWBKPT);
9412 GET_REG32_1(TX_CPU_MODE);
9413 GET_REG32_1(TX_CPU_STATE);
9414 GET_REG32_1(TX_CPU_PGMCTR);
9415 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9416 GET_REG32_LOOP(FTQ_RESET, 0x120);
9417 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9418 GET_REG32_1(DMAC_MODE);
9419 GET_REG32_LOOP(GRC_MODE, 0x4c);
9420 if (tp->tg3_flags & TG3_FLAG_NVRAM)
9421 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9424 #undef GET_REG32_LOOP
9427 tg3_full_unlock(tp);
9430 static int tg3_get_eeprom_len(struct net_device *dev)
9432 struct tg3 *tp = netdev_priv(dev);
9434 return tp->nvram_size;
9437 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9439 struct tg3 *tp = netdev_priv(dev);
9442 u32 i, offset, len, b_offset, b_count;
9445 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9448 if (tp->link_config.phy_is_low_power)
9451 offset = eeprom->offset;
9455 eeprom->magic = TG3_EEPROM_MAGIC;
9458 /* adjustments to start on required 4 byte boundary */
9459 b_offset = offset & 3;
9460 b_count = 4 - b_offset;
9461 if (b_count > len) {
9462 /* i.e. offset=1 len=2 */
9465 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9468 memcpy(data, ((char *)&val) + b_offset, b_count);
9471 eeprom->len += b_count;
9474 /* read bytes upto the last 4 byte boundary */
9475 pd = &data[eeprom->len];
9476 for (i = 0; i < (len - (len & 3)); i += 4) {
9477 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9482 memcpy(pd + i, &val, 4);
9487 /* read last bytes not ending on 4 byte boundary */
9488 pd = &data[eeprom->len];
9490 b_offset = offset + len - b_count;
9491 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9494 memcpy(pd, &val, b_count);
9495 eeprom->len += b_count;
9500 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9502 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9504 struct tg3 *tp = netdev_priv(dev);
9506 u32 offset, len, b_offset, odd_len;
9510 if (tp->link_config.phy_is_low_power)
9513 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9514 eeprom->magic != TG3_EEPROM_MAGIC)
9517 offset = eeprom->offset;
9520 if ((b_offset = (offset & 3))) {
9521 /* adjustments to start on required 4 byte boundary */
9522 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9533 /* adjustments to end on required 4 byte boundary */
9535 len = (len + 3) & ~3;
9536 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9542 if (b_offset || odd_len) {
9543 buf = kmalloc(len, GFP_KERNEL);
9547 memcpy(buf, &start, 4);
9549 memcpy(buf+len-4, &end, 4);
9550 memcpy(buf + b_offset, data, eeprom->len);
9553 ret = tg3_nvram_write_block(tp, offset, len, buf);
9561 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9563 struct tg3 *tp = netdev_priv(dev);
9565 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9566 struct phy_device *phydev;
9567 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9569 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9570 return phy_ethtool_gset(phydev, cmd);
9573 cmd->supported = (SUPPORTED_Autoneg);
9575 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9576 cmd->supported |= (SUPPORTED_1000baseT_Half |
9577 SUPPORTED_1000baseT_Full);
9579 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
9580 cmd->supported |= (SUPPORTED_100baseT_Half |
9581 SUPPORTED_100baseT_Full |
9582 SUPPORTED_10baseT_Half |
9583 SUPPORTED_10baseT_Full |
9585 cmd->port = PORT_TP;
9587 cmd->supported |= SUPPORTED_FIBRE;
9588 cmd->port = PORT_FIBRE;
9591 cmd->advertising = tp->link_config.advertising;
9592 if (netif_running(dev)) {
9593 cmd->speed = tp->link_config.active_speed;
9594 cmd->duplex = tp->link_config.active_duplex;
9596 cmd->phy_address = tp->phy_addr;
9597 cmd->transceiver = XCVR_INTERNAL;
9598 cmd->autoneg = tp->link_config.autoneg;
9604 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9606 struct tg3 *tp = netdev_priv(dev);
9608 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9609 struct phy_device *phydev;
9610 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9612 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9613 return phy_ethtool_sset(phydev, cmd);
9616 if (cmd->autoneg != AUTONEG_ENABLE &&
9617 cmd->autoneg != AUTONEG_DISABLE)
9620 if (cmd->autoneg == AUTONEG_DISABLE &&
9621 cmd->duplex != DUPLEX_FULL &&
9622 cmd->duplex != DUPLEX_HALF)
9625 if (cmd->autoneg == AUTONEG_ENABLE) {
9626 u32 mask = ADVERTISED_Autoneg |
9628 ADVERTISED_Asym_Pause;
9630 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9631 mask |= ADVERTISED_1000baseT_Half |
9632 ADVERTISED_1000baseT_Full;
9634 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9635 mask |= ADVERTISED_100baseT_Half |
9636 ADVERTISED_100baseT_Full |
9637 ADVERTISED_10baseT_Half |
9638 ADVERTISED_10baseT_Full |
9641 mask |= ADVERTISED_FIBRE;
9643 if (cmd->advertising & ~mask)
9646 mask &= (ADVERTISED_1000baseT_Half |
9647 ADVERTISED_1000baseT_Full |
9648 ADVERTISED_100baseT_Half |
9649 ADVERTISED_100baseT_Full |
9650 ADVERTISED_10baseT_Half |
9651 ADVERTISED_10baseT_Full);
9653 cmd->advertising &= mask;
9655 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9656 if (cmd->speed != SPEED_1000)
9659 if (cmd->duplex != DUPLEX_FULL)
9662 if (cmd->speed != SPEED_100 &&
9663 cmd->speed != SPEED_10)
9668 tg3_full_lock(tp, 0);
9670 tp->link_config.autoneg = cmd->autoneg;
9671 if (cmd->autoneg == AUTONEG_ENABLE) {
9672 tp->link_config.advertising = (cmd->advertising |
9673 ADVERTISED_Autoneg);
9674 tp->link_config.speed = SPEED_INVALID;
9675 tp->link_config.duplex = DUPLEX_INVALID;
9677 tp->link_config.advertising = 0;
9678 tp->link_config.speed = cmd->speed;
9679 tp->link_config.duplex = cmd->duplex;
9682 tp->link_config.orig_speed = tp->link_config.speed;
9683 tp->link_config.orig_duplex = tp->link_config.duplex;
9684 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9686 if (netif_running(dev))
9687 tg3_setup_phy(tp, 1);
9689 tg3_full_unlock(tp);
9694 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9696 struct tg3 *tp = netdev_priv(dev);
9698 strcpy(info->driver, DRV_MODULE_NAME);
9699 strcpy(info->version, DRV_MODULE_VERSION);
9700 strcpy(info->fw_version, tp->fw_ver);
9701 strcpy(info->bus_info, pci_name(tp->pdev));
9704 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9706 struct tg3 *tp = netdev_priv(dev);
9708 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9709 device_can_wakeup(&tp->pdev->dev))
9710 wol->supported = WAKE_MAGIC;
9714 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9715 device_can_wakeup(&tp->pdev->dev))
9716 wol->wolopts = WAKE_MAGIC;
9717 memset(&wol->sopass, 0, sizeof(wol->sopass));
9720 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9722 struct tg3 *tp = netdev_priv(dev);
9723 struct device *dp = &tp->pdev->dev;
9725 if (wol->wolopts & ~WAKE_MAGIC)
9727 if ((wol->wolopts & WAKE_MAGIC) &&
9728 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9731 spin_lock_bh(&tp->lock);
9732 if (wol->wolopts & WAKE_MAGIC) {
9733 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9734 device_set_wakeup_enable(dp, true);
9736 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9737 device_set_wakeup_enable(dp, false);
9739 spin_unlock_bh(&tp->lock);
9744 static u32 tg3_get_msglevel(struct net_device *dev)
9746 struct tg3 *tp = netdev_priv(dev);
9747 return tp->msg_enable;
9750 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9752 struct tg3 *tp = netdev_priv(dev);
9753 tp->msg_enable = value;
9756 static int tg3_set_tso(struct net_device *dev, u32 value)
9758 struct tg3 *tp = netdev_priv(dev);
9760 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9765 if ((dev->features & NETIF_F_IPV6_CSUM) &&
9766 ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9767 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9769 dev->features |= NETIF_F_TSO6;
9770 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9771 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9772 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9773 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9774 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9775 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9776 dev->features |= NETIF_F_TSO_ECN;
9778 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9780 return ethtool_op_set_tso(dev, value);
9783 static int tg3_nway_reset(struct net_device *dev)
9785 struct tg3 *tp = netdev_priv(dev);
9788 if (!netif_running(dev))
9791 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9794 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9795 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9797 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9801 spin_lock_bh(&tp->lock);
9803 tg3_readphy(tp, MII_BMCR, &bmcr);
9804 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9805 ((bmcr & BMCR_ANENABLE) ||
9806 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9807 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9811 spin_unlock_bh(&tp->lock);
9817 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9819 struct tg3 *tp = netdev_priv(dev);
9821 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9822 ering->rx_mini_max_pending = 0;
9823 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9824 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9826 ering->rx_jumbo_max_pending = 0;
9828 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9830 ering->rx_pending = tp->rx_pending;
9831 ering->rx_mini_pending = 0;
9832 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9833 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9835 ering->rx_jumbo_pending = 0;
9837 ering->tx_pending = tp->napi[0].tx_pending;
9840 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9842 struct tg3 *tp = netdev_priv(dev);
9843 int i, irq_sync = 0, err = 0;
9845 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9846 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9847 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9848 (ering->tx_pending <= MAX_SKB_FRAGS) ||
9849 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9850 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9853 if (netif_running(dev)) {
9859 tg3_full_lock(tp, irq_sync);
9861 tp->rx_pending = ering->rx_pending;
9863 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9864 tp->rx_pending > 63)
9865 tp->rx_pending = 63;
9866 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9868 for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9869 tp->napi[i].tx_pending = ering->tx_pending;
9871 if (netif_running(dev)) {
9872 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9873 err = tg3_restart_hw(tp, 1);
9875 tg3_netif_start(tp);
9878 tg3_full_unlock(tp);
9880 if (irq_sync && !err)
9886 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9888 struct tg3 *tp = netdev_priv(dev);
9890 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9892 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9893 epause->rx_pause = 1;
9895 epause->rx_pause = 0;
9897 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9898 epause->tx_pause = 1;
9900 epause->tx_pause = 0;
9903 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9905 struct tg3 *tp = netdev_priv(dev);
9908 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9910 struct phy_device *phydev;
9912 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9914 if (!(phydev->supported & SUPPORTED_Pause) ||
9915 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
9916 ((epause->rx_pause && !epause->tx_pause) ||
9917 (!epause->rx_pause && epause->tx_pause))))
9920 tp->link_config.flowctrl = 0;
9921 if (epause->rx_pause) {
9922 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9924 if (epause->tx_pause) {
9925 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9926 newadv = ADVERTISED_Pause;
9928 newadv = ADVERTISED_Pause |
9929 ADVERTISED_Asym_Pause;
9930 } else if (epause->tx_pause) {
9931 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9932 newadv = ADVERTISED_Asym_Pause;
9936 if (epause->autoneg)
9937 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9939 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9941 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9942 u32 oldadv = phydev->advertising &
9943 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
9944 if (oldadv != newadv) {
9945 phydev->advertising &=
9946 ~(ADVERTISED_Pause |
9947 ADVERTISED_Asym_Pause);
9948 phydev->advertising |= newadv;
9949 if (phydev->autoneg) {
9951 * Always renegotiate the link to
9952 * inform our link partner of our
9953 * flow control settings, even if the
9954 * flow control is forced. Let
9955 * tg3_adjust_link() do the final
9956 * flow control setup.
9958 return phy_start_aneg(phydev);
9962 if (!epause->autoneg)
9963 tg3_setup_flow_control(tp, 0, 0);
9965 tp->link_config.orig_advertising &=
9966 ~(ADVERTISED_Pause |
9967 ADVERTISED_Asym_Pause);
9968 tp->link_config.orig_advertising |= newadv;
9973 if (netif_running(dev)) {
9978 tg3_full_lock(tp, irq_sync);
9980 if (epause->autoneg)
9981 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9983 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9984 if (epause->rx_pause)
9985 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9987 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9988 if (epause->tx_pause)
9989 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9991 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9993 if (netif_running(dev)) {
9994 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9995 err = tg3_restart_hw(tp, 1);
9997 tg3_netif_start(tp);
10000 tg3_full_unlock(tp);
10006 static u32 tg3_get_rx_csum(struct net_device *dev)
10008 struct tg3 *tp = netdev_priv(dev);
10009 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10012 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10014 struct tg3 *tp = netdev_priv(dev);
10016 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10022 spin_lock_bh(&tp->lock);
10024 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10026 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10027 spin_unlock_bh(&tp->lock);
10032 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10034 struct tg3 *tp = netdev_priv(dev);
10036 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10042 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10043 ethtool_op_set_tx_ipv6_csum(dev, data);
10045 ethtool_op_set_tx_csum(dev, data);
10050 static int tg3_get_sset_count(struct net_device *dev, int sset)
10054 return TG3_NUM_TEST;
10056 return TG3_NUM_STATS;
10058 return -EOPNOTSUPP;
10062 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
10064 switch (stringset) {
10066 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
10069 memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys));
10072 WARN_ON(1); /* we need a WARN() */
10077 static int tg3_phys_id(struct net_device *dev, u32 data)
10079 struct tg3 *tp = netdev_priv(dev);
10082 if (!netif_running(tp->dev))
10086 data = UINT_MAX / 2;
10088 for (i = 0; i < (data * 2); i++) {
10090 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10091 LED_CTRL_1000MBPS_ON |
10092 LED_CTRL_100MBPS_ON |
10093 LED_CTRL_10MBPS_ON |
10094 LED_CTRL_TRAFFIC_OVERRIDE |
10095 LED_CTRL_TRAFFIC_BLINK |
10096 LED_CTRL_TRAFFIC_LED);
10099 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10100 LED_CTRL_TRAFFIC_OVERRIDE);
10102 if (msleep_interruptible(500))
10105 tw32(MAC_LED_CTRL, tp->led_ctrl);
10109 static void tg3_get_ethtool_stats(struct net_device *dev,
10110 struct ethtool_stats *estats, u64 *tmp_stats)
10112 struct tg3 *tp = netdev_priv(dev);
10113 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10116 #define NVRAM_TEST_SIZE 0x100
10117 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10118 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10119 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
10120 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10121 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10123 static int tg3_test_nvram(struct tg3 *tp)
10127 int i, j, k, err = 0, size;
10129 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10132 if (tg3_nvram_read(tp, 0, &magic) != 0)
10135 if (magic == TG3_EEPROM_MAGIC)
10136 size = NVRAM_TEST_SIZE;
10137 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10138 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10139 TG3_EEPROM_SB_FORMAT_1) {
10140 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10141 case TG3_EEPROM_SB_REVISION_0:
10142 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10144 case TG3_EEPROM_SB_REVISION_2:
10145 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10147 case TG3_EEPROM_SB_REVISION_3:
10148 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10155 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10156 size = NVRAM_SELFBOOT_HW_SIZE;
10160 buf = kmalloc(size, GFP_KERNEL);
10165 for (i = 0, j = 0; i < size; i += 4, j++) {
10166 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10173 /* Selfboot format */
10174 magic = be32_to_cpu(buf[0]);
10175 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10176 TG3_EEPROM_MAGIC_FW) {
10177 u8 *buf8 = (u8 *) buf, csum8 = 0;
10179 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10180 TG3_EEPROM_SB_REVISION_2) {
10181 /* For rev 2, the csum doesn't include the MBA. */
10182 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10184 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10187 for (i = 0; i < size; i++)
10200 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10201 TG3_EEPROM_MAGIC_HW) {
10202 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10203 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10204 u8 *buf8 = (u8 *) buf;
10206 /* Separate the parity bits and the data bytes. */
10207 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10208 if ((i == 0) || (i == 8)) {
10212 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10213 parity[k++] = buf8[i] & msk;
10215 } else if (i == 16) {
10219 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10220 parity[k++] = buf8[i] & msk;
10223 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10224 parity[k++] = buf8[i] & msk;
10227 data[j++] = buf8[i];
10231 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10232 u8 hw8 = hweight8(data[i]);
10234 if ((hw8 & 0x1) && parity[i])
10236 else if (!(hw8 & 0x1) && !parity[i])
10243 /* Bootstrap checksum at offset 0x10 */
10244 csum = calc_crc((unsigned char *) buf, 0x10);
10245 if (csum != be32_to_cpu(buf[0x10/4]))
10248 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10249 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10250 if (csum != be32_to_cpu(buf[0xfc/4]))
10260 #define TG3_SERDES_TIMEOUT_SEC 2
10261 #define TG3_COPPER_TIMEOUT_SEC 6
10263 static int tg3_test_link(struct tg3 *tp)
10267 if (!netif_running(tp->dev))
10270 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10271 max = TG3_SERDES_TIMEOUT_SEC;
10273 max = TG3_COPPER_TIMEOUT_SEC;
10275 for (i = 0; i < max; i++) {
10276 if (netif_carrier_ok(tp->dev))
10279 if (msleep_interruptible(1000))
10286 /* Only test the commonly used registers */
10287 static int tg3_test_registers(struct tg3 *tp)
10289 int i, is_5705, is_5750;
10290 u32 offset, read_mask, write_mask, val, save_val, read_val;
10294 #define TG3_FL_5705 0x1
10295 #define TG3_FL_NOT_5705 0x2
10296 #define TG3_FL_NOT_5788 0x4
10297 #define TG3_FL_NOT_5750 0x8
10301 /* MAC Control Registers */
10302 { MAC_MODE, TG3_FL_NOT_5705,
10303 0x00000000, 0x00ef6f8c },
10304 { MAC_MODE, TG3_FL_5705,
10305 0x00000000, 0x01ef6b8c },
10306 { MAC_STATUS, TG3_FL_NOT_5705,
10307 0x03800107, 0x00000000 },
10308 { MAC_STATUS, TG3_FL_5705,
10309 0x03800100, 0x00000000 },
10310 { MAC_ADDR_0_HIGH, 0x0000,
10311 0x00000000, 0x0000ffff },
10312 { MAC_ADDR_0_LOW, 0x0000,
10313 0x00000000, 0xffffffff },
10314 { MAC_RX_MTU_SIZE, 0x0000,
10315 0x00000000, 0x0000ffff },
10316 { MAC_TX_MODE, 0x0000,
10317 0x00000000, 0x00000070 },
10318 { MAC_TX_LENGTHS, 0x0000,
10319 0x00000000, 0x00003fff },
10320 { MAC_RX_MODE, TG3_FL_NOT_5705,
10321 0x00000000, 0x000007fc },
10322 { MAC_RX_MODE, TG3_FL_5705,
10323 0x00000000, 0x000007dc },
10324 { MAC_HASH_REG_0, 0x0000,
10325 0x00000000, 0xffffffff },
10326 { MAC_HASH_REG_1, 0x0000,
10327 0x00000000, 0xffffffff },
10328 { MAC_HASH_REG_2, 0x0000,
10329 0x00000000, 0xffffffff },
10330 { MAC_HASH_REG_3, 0x0000,
10331 0x00000000, 0xffffffff },
10333 /* Receive Data and Receive BD Initiator Control Registers. */
10334 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10335 0x00000000, 0xffffffff },
10336 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10337 0x00000000, 0xffffffff },
10338 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10339 0x00000000, 0x00000003 },
10340 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10341 0x00000000, 0xffffffff },
10342 { RCVDBDI_STD_BD+0, 0x0000,
10343 0x00000000, 0xffffffff },
10344 { RCVDBDI_STD_BD+4, 0x0000,
10345 0x00000000, 0xffffffff },
10346 { RCVDBDI_STD_BD+8, 0x0000,
10347 0x00000000, 0xffff0002 },
10348 { RCVDBDI_STD_BD+0xc, 0x0000,
10349 0x00000000, 0xffffffff },
10351 /* Receive BD Initiator Control Registers. */
10352 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10353 0x00000000, 0xffffffff },
10354 { RCVBDI_STD_THRESH, TG3_FL_5705,
10355 0x00000000, 0x000003ff },
10356 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10357 0x00000000, 0xffffffff },
10359 /* Host Coalescing Control Registers. */
10360 { HOSTCC_MODE, TG3_FL_NOT_5705,
10361 0x00000000, 0x00000004 },
10362 { HOSTCC_MODE, TG3_FL_5705,
10363 0x00000000, 0x000000f6 },
10364 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10365 0x00000000, 0xffffffff },
10366 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10367 0x00000000, 0x000003ff },
10368 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10369 0x00000000, 0xffffffff },
10370 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10371 0x00000000, 0x000003ff },
10372 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10373 0x00000000, 0xffffffff },
10374 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10375 0x00000000, 0x000000ff },
10376 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10377 0x00000000, 0xffffffff },
10378 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10379 0x00000000, 0x000000ff },
10380 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10381 0x00000000, 0xffffffff },
10382 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10383 0x00000000, 0xffffffff },
10384 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10385 0x00000000, 0xffffffff },
10386 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10387 0x00000000, 0x000000ff },
10388 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10389 0x00000000, 0xffffffff },
10390 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10391 0x00000000, 0x000000ff },
10392 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10393 0x00000000, 0xffffffff },
10394 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10395 0x00000000, 0xffffffff },
10396 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10397 0x00000000, 0xffffffff },
10398 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10399 0x00000000, 0xffffffff },
10400 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10401 0x00000000, 0xffffffff },
10402 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10403 0xffffffff, 0x00000000 },
10404 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10405 0xffffffff, 0x00000000 },
10407 /* Buffer Manager Control Registers. */
10408 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10409 0x00000000, 0x007fff80 },
10410 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10411 0x00000000, 0x007fffff },
10412 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10413 0x00000000, 0x0000003f },
10414 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10415 0x00000000, 0x000001ff },
10416 { BUFMGR_MB_HIGH_WATER, 0x0000,
10417 0x00000000, 0x000001ff },
10418 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10419 0xffffffff, 0x00000000 },
10420 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10421 0xffffffff, 0x00000000 },
10423 /* Mailbox Registers */
10424 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10425 0x00000000, 0x000001ff },
10426 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10427 0x00000000, 0x000001ff },
10428 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10429 0x00000000, 0x000007ff },
10430 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10431 0x00000000, 0x000001ff },
10433 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10436 is_5705 = is_5750 = 0;
10437 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10439 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10443 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10444 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10447 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10450 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10451 (reg_tbl[i].flags & TG3_FL_NOT_5788))
10454 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10457 offset = (u32) reg_tbl[i].offset;
10458 read_mask = reg_tbl[i].read_mask;
10459 write_mask = reg_tbl[i].write_mask;
10461 /* Save the original register content */
10462 save_val = tr32(offset);
10464 /* Determine the read-only value. */
10465 read_val = save_val & read_mask;
10467 /* Write zero to the register, then make sure the read-only bits
10468 * are not changed and the read/write bits are all zeros.
10472 val = tr32(offset);
10474 /* Test the read-only and read/write bits. */
10475 if (((val & read_mask) != read_val) || (val & write_mask))
10478 /* Write ones to all the bits defined by RdMask and WrMask, then
10479 * make sure the read-only bits are not changed and the
10480 * read/write bits are all ones.
10482 tw32(offset, read_mask | write_mask);
10484 val = tr32(offset);
10486 /* Test the read-only bits. */
10487 if ((val & read_mask) != read_val)
10490 /* Test the read/write bits. */
10491 if ((val & write_mask) != write_mask)
10494 tw32(offset, save_val);
10500 if (netif_msg_hw(tp))
10501 netdev_err(tp->dev,
10502 "Register test failed at offset %x\n", offset);
10503 tw32(offset, save_val);
10507 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10509 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10513 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10514 for (j = 0; j < len; j += 4) {
10517 tg3_write_mem(tp, offset + j, test_pattern[i]);
10518 tg3_read_mem(tp, offset + j, &val);
10519 if (val != test_pattern[i])
10526 static int tg3_test_memory(struct tg3 *tp)
10528 static struct mem_entry {
10531 } mem_tbl_570x[] = {
10532 { 0x00000000, 0x00b50},
10533 { 0x00002000, 0x1c000},
10534 { 0xffffffff, 0x00000}
10535 }, mem_tbl_5705[] = {
10536 { 0x00000100, 0x0000c},
10537 { 0x00000200, 0x00008},
10538 { 0x00004000, 0x00800},
10539 { 0x00006000, 0x01000},
10540 { 0x00008000, 0x02000},
10541 { 0x00010000, 0x0e000},
10542 { 0xffffffff, 0x00000}
10543 }, mem_tbl_5755[] = {
10544 { 0x00000200, 0x00008},
10545 { 0x00004000, 0x00800},
10546 { 0x00006000, 0x00800},
10547 { 0x00008000, 0x02000},
10548 { 0x00010000, 0x0c000},
10549 { 0xffffffff, 0x00000}
10550 }, mem_tbl_5906[] = {
10551 { 0x00000200, 0x00008},
10552 { 0x00004000, 0x00400},
10553 { 0x00006000, 0x00400},
10554 { 0x00008000, 0x01000},
10555 { 0x00010000, 0x01000},
10556 { 0xffffffff, 0x00000}
10557 }, mem_tbl_5717[] = {
10558 { 0x00000200, 0x00008},
10559 { 0x00010000, 0x0a000},
10560 { 0x00020000, 0x13c00},
10561 { 0xffffffff, 0x00000}
10562 }, mem_tbl_57765[] = {
10563 { 0x00000200, 0x00008},
10564 { 0x00004000, 0x00800},
10565 { 0x00006000, 0x09800},
10566 { 0x00010000, 0x0a000},
10567 { 0xffffffff, 0x00000}
10569 struct mem_entry *mem_tbl;
10573 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
10574 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
10575 mem_tbl = mem_tbl_5717;
10576 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10577 mem_tbl = mem_tbl_57765;
10578 else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10579 mem_tbl = mem_tbl_5755;
10580 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10581 mem_tbl = mem_tbl_5906;
10582 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10583 mem_tbl = mem_tbl_5705;
10585 mem_tbl = mem_tbl_570x;
10587 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10588 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
10596 #define TG3_MAC_LOOPBACK 0
10597 #define TG3_PHY_LOOPBACK 1
10599 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10601 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10602 u32 desc_idx, coal_now;
10603 struct sk_buff *skb, *rx_skb;
10606 int num_pkts, tx_len, rx_len, i, err;
10607 struct tg3_rx_buffer_desc *desc;
10608 struct tg3_napi *tnapi, *rnapi;
10609 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
10611 tnapi = &tp->napi[0];
10612 rnapi = &tp->napi[0];
10613 if (tp->irq_cnt > 1) {
10614 rnapi = &tp->napi[1];
10615 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
10616 tnapi = &tp->napi[1];
10618 coal_now = tnapi->coal_now | rnapi->coal_now;
10620 if (loopback_mode == TG3_MAC_LOOPBACK) {
10621 /* HW errata - mac loopback fails in some cases on 5780.
10622 * Normal traffic and PHY loopback are not affected by
10625 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10628 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10629 MAC_MODE_PORT_INT_LPBACK;
10630 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10631 mac_mode |= MAC_MODE_LINK_POLARITY;
10632 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10633 mac_mode |= MAC_MODE_PORT_MODE_MII;
10635 mac_mode |= MAC_MODE_PORT_MODE_GMII;
10636 tw32(MAC_MODE, mac_mode);
10637 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10640 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10641 tg3_phy_fet_toggle_apd(tp, false);
10642 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10644 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10646 tg3_phy_toggle_automdix(tp, 0);
10648 tg3_writephy(tp, MII_BMCR, val);
10651 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10652 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10653 tg3_writephy(tp, MII_TG3_FET_PTEST,
10654 MII_TG3_FET_PTEST_FRC_TX_LINK |
10655 MII_TG3_FET_PTEST_FRC_TX_LOCK);
10656 /* The write needs to be flushed for the AC131 */
10657 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10658 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
10659 mac_mode |= MAC_MODE_PORT_MODE_MII;
10661 mac_mode |= MAC_MODE_PORT_MODE_GMII;
10663 /* reset to prevent losing 1st rx packet intermittently */
10664 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10665 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10667 tw32_f(MAC_RX_MODE, tp->rx_mode);
10669 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10670 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
10671 if (masked_phy_id == TG3_PHY_ID_BCM5401)
10672 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10673 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
10674 mac_mode |= MAC_MODE_LINK_POLARITY;
10675 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10676 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10678 tw32(MAC_MODE, mac_mode);
10686 skb = netdev_alloc_skb(tp->dev, tx_len);
10690 tx_data = skb_put(skb, tx_len);
10691 memcpy(tx_data, tp->dev->dev_addr, 6);
10692 memset(tx_data + 6, 0x0, 8);
10694 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10696 for (i = 14; i < tx_len; i++)
10697 tx_data[i] = (u8) (i & 0xff);
10699 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10700 if (pci_dma_mapping_error(tp->pdev, map)) {
10701 dev_kfree_skb(skb);
10705 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10710 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10714 tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10719 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10720 tr32_mailbox(tnapi->prodmbox);
10724 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
10725 for (i = 0; i < 35; i++) {
10726 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10731 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10732 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10733 if ((tx_idx == tnapi->tx_prod) &&
10734 (rx_idx == (rx_start_idx + num_pkts)))
10738 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10739 dev_kfree_skb(skb);
10741 if (tx_idx != tnapi->tx_prod)
10744 if (rx_idx != rx_start_idx + num_pkts)
10747 desc = &rnapi->rx_rcb[rx_start_idx];
10748 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10749 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10750 if (opaque_key != RXD_OPAQUE_RING_STD)
10753 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10754 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10757 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10758 if (rx_len != tx_len)
10761 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10763 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10764 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10766 for (i = 14; i < tx_len; i++) {
10767 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10772 /* tg3_free_rings will unmap and free the rx_skb */
10777 #define TG3_MAC_LOOPBACK_FAILED 1
10778 #define TG3_PHY_LOOPBACK_FAILED 2
10779 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10780 TG3_PHY_LOOPBACK_FAILED)
10782 static int tg3_test_loopback(struct tg3 *tp)
10787 if (!netif_running(tp->dev))
10788 return TG3_LOOPBACK_FAILED;
10790 err = tg3_reset_hw(tp, 1);
10792 return TG3_LOOPBACK_FAILED;
10794 /* Turn off gphy autopowerdown. */
10795 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10796 tg3_phy_toggle_apd(tp, false);
10798 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10802 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10804 /* Wait for up to 40 microseconds to acquire lock. */
10805 for (i = 0; i < 4; i++) {
10806 status = tr32(TG3_CPMU_MUTEX_GNT);
10807 if (status == CPMU_MUTEX_GNT_DRIVER)
10812 if (status != CPMU_MUTEX_GNT_DRIVER)
10813 return TG3_LOOPBACK_FAILED;
10815 /* Turn off link-based power management. */
10816 cpmuctrl = tr32(TG3_CPMU_CTRL);
10817 tw32(TG3_CPMU_CTRL,
10818 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10819 CPMU_CTRL_LINK_AWARE_MODE));
10822 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10823 err |= TG3_MAC_LOOPBACK_FAILED;
10825 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10826 tw32(TG3_CPMU_CTRL, cpmuctrl);
10828 /* Release the mutex */
10829 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10832 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10833 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10834 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10835 err |= TG3_PHY_LOOPBACK_FAILED;
10838 /* Re-enable gphy autopowerdown. */
10839 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10840 tg3_phy_toggle_apd(tp, true);
10845 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10848 struct tg3 *tp = netdev_priv(dev);
10850 if (tp->link_config.phy_is_low_power)
10851 tg3_set_power_state(tp, PCI_D0);
10853 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10855 if (tg3_test_nvram(tp) != 0) {
10856 etest->flags |= ETH_TEST_FL_FAILED;
10859 if (tg3_test_link(tp) != 0) {
10860 etest->flags |= ETH_TEST_FL_FAILED;
10863 if (etest->flags & ETH_TEST_FL_OFFLINE) {
10864 int err, err2 = 0, irq_sync = 0;
10866 if (netif_running(dev)) {
10868 tg3_netif_stop(tp);
10872 tg3_full_lock(tp, irq_sync);
10874 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10875 err = tg3_nvram_lock(tp);
10876 tg3_halt_cpu(tp, RX_CPU_BASE);
10877 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10878 tg3_halt_cpu(tp, TX_CPU_BASE);
10880 tg3_nvram_unlock(tp);
10882 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10885 if (tg3_test_registers(tp) != 0) {
10886 etest->flags |= ETH_TEST_FL_FAILED;
10889 if (tg3_test_memory(tp) != 0) {
10890 etest->flags |= ETH_TEST_FL_FAILED;
10893 if ((data[4] = tg3_test_loopback(tp)) != 0)
10894 etest->flags |= ETH_TEST_FL_FAILED;
10896 tg3_full_unlock(tp);
10898 if (tg3_test_interrupt(tp) != 0) {
10899 etest->flags |= ETH_TEST_FL_FAILED;
10903 tg3_full_lock(tp, 0);
10905 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10906 if (netif_running(dev)) {
10907 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10908 err2 = tg3_restart_hw(tp, 1);
10910 tg3_netif_start(tp);
10913 tg3_full_unlock(tp);
10915 if (irq_sync && !err2)
10918 if (tp->link_config.phy_is_low_power)
10919 tg3_set_power_state(tp, PCI_D3hot);
10923 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10925 struct mii_ioctl_data *data = if_mii(ifr);
10926 struct tg3 *tp = netdev_priv(dev);
10929 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10930 struct phy_device *phydev;
10931 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10933 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10934 return phy_mii_ioctl(phydev, ifr, cmd);
10939 data->phy_id = tp->phy_addr;
10942 case SIOCGMIIREG: {
10945 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10946 break; /* We have no PHY */
10948 if (tp->link_config.phy_is_low_power)
10951 spin_lock_bh(&tp->lock);
10952 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10953 spin_unlock_bh(&tp->lock);
10955 data->val_out = mii_regval;
10961 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10962 break; /* We have no PHY */
10964 if (tp->link_config.phy_is_low_power)
10967 spin_lock_bh(&tp->lock);
10968 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10969 spin_unlock_bh(&tp->lock);
10977 return -EOPNOTSUPP;
10980 #if TG3_VLAN_TAG_USED
10981 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10983 struct tg3 *tp = netdev_priv(dev);
10985 if (!netif_running(dev)) {
10990 tg3_netif_stop(tp);
10992 tg3_full_lock(tp, 0);
10996 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10997 __tg3_set_rx_mode(dev);
10999 tg3_netif_start(tp);
11001 tg3_full_unlock(tp);
11005 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11007 struct tg3 *tp = netdev_priv(dev);
11009 memcpy(ec, &tp->coal, sizeof(*ec));
11013 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11015 struct tg3 *tp = netdev_priv(dev);
11016 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11017 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11019 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11020 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11021 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11022 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11023 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11026 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11027 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11028 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11029 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11030 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11031 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11032 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11033 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11034 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11035 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11038 /* No rx interrupts will be generated if both are zero */
11039 if ((ec->rx_coalesce_usecs == 0) &&
11040 (ec->rx_max_coalesced_frames == 0))
11043 /* No tx interrupts will be generated if both are zero */
11044 if ((ec->tx_coalesce_usecs == 0) &&
11045 (ec->tx_max_coalesced_frames == 0))
11048 /* Only copy relevant parameters, ignore all others. */
11049 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11050 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11051 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11052 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11053 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11054 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11055 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11056 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11057 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11059 if (netif_running(dev)) {
11060 tg3_full_lock(tp, 0);
11061 __tg3_set_coalesce(tp, &tp->coal);
11062 tg3_full_unlock(tp);
11067 static const struct ethtool_ops tg3_ethtool_ops = {
11068 .get_settings = tg3_get_settings,
11069 .set_settings = tg3_set_settings,
11070 .get_drvinfo = tg3_get_drvinfo,
11071 .get_regs_len = tg3_get_regs_len,
11072 .get_regs = tg3_get_regs,
11073 .get_wol = tg3_get_wol,
11074 .set_wol = tg3_set_wol,
11075 .get_msglevel = tg3_get_msglevel,
11076 .set_msglevel = tg3_set_msglevel,
11077 .nway_reset = tg3_nway_reset,
11078 .get_link = ethtool_op_get_link,
11079 .get_eeprom_len = tg3_get_eeprom_len,
11080 .get_eeprom = tg3_get_eeprom,
11081 .set_eeprom = tg3_set_eeprom,
11082 .get_ringparam = tg3_get_ringparam,
11083 .set_ringparam = tg3_set_ringparam,
11084 .get_pauseparam = tg3_get_pauseparam,
11085 .set_pauseparam = tg3_set_pauseparam,
11086 .get_rx_csum = tg3_get_rx_csum,
11087 .set_rx_csum = tg3_set_rx_csum,
11088 .set_tx_csum = tg3_set_tx_csum,
11089 .set_sg = ethtool_op_set_sg,
11090 .set_tso = tg3_set_tso,
11091 .self_test = tg3_self_test,
11092 .get_strings = tg3_get_strings,
11093 .phys_id = tg3_phys_id,
11094 .get_ethtool_stats = tg3_get_ethtool_stats,
11095 .get_coalesce = tg3_get_coalesce,
11096 .set_coalesce = tg3_set_coalesce,
11097 .get_sset_count = tg3_get_sset_count,
11100 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11102 u32 cursize, val, magic;
11104 tp->nvram_size = EEPROM_CHIP_SIZE;
11106 if (tg3_nvram_read(tp, 0, &magic) != 0)
11109 if ((magic != TG3_EEPROM_MAGIC) &&
11110 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11111 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11115 * Size the chip by reading offsets at increasing powers of two.
11116 * When we encounter our validation signature, we know the addressing
11117 * has wrapped around, and thus have our chip size.
11121 while (cursize < tp->nvram_size) {
11122 if (tg3_nvram_read(tp, cursize, &val) != 0)
11131 tp->nvram_size = cursize;
11134 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11138 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11139 tg3_nvram_read(tp, 0, &val) != 0)
11142 /* Selfboot format */
11143 if (val != TG3_EEPROM_MAGIC) {
11144 tg3_get_eeprom_size(tp);
11148 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11150 /* This is confusing. We want to operate on the
11151 * 16-bit value at offset 0xf2. The tg3_nvram_read()
11152 * call will read from NVRAM and byteswap the data
11153 * according to the byteswapping settings for all
11154 * other register accesses. This ensures the data we
11155 * want will always reside in the lower 16-bits.
11156 * However, the data in NVRAM is in LE format, which
11157 * means the data from the NVRAM read will always be
11158 * opposite the endianness of the CPU. The 16-bit
11159 * byteswap then brings the data to CPU endianness.
11161 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11165 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11168 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11172 nvcfg1 = tr32(NVRAM_CFG1);
11173 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11174 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11176 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11177 tw32(NVRAM_CFG1, nvcfg1);
11180 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11181 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11182 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11183 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11184 tp->nvram_jedecnum = JEDEC_ATMEL;
11185 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11186 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11188 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11189 tp->nvram_jedecnum = JEDEC_ATMEL;
11190 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11192 case FLASH_VENDOR_ATMEL_EEPROM:
11193 tp->nvram_jedecnum = JEDEC_ATMEL;
11194 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11195 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11197 case FLASH_VENDOR_ST:
11198 tp->nvram_jedecnum = JEDEC_ST;
11199 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11200 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11202 case FLASH_VENDOR_SAIFUN:
11203 tp->nvram_jedecnum = JEDEC_SAIFUN;
11204 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11206 case FLASH_VENDOR_SST_SMALL:
11207 case FLASH_VENDOR_SST_LARGE:
11208 tp->nvram_jedecnum = JEDEC_SST;
11209 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11213 tp->nvram_jedecnum = JEDEC_ATMEL;
11214 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11215 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11219 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11221 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11222 case FLASH_5752PAGE_SIZE_256:
11223 tp->nvram_pagesize = 256;
11225 case FLASH_5752PAGE_SIZE_512:
11226 tp->nvram_pagesize = 512;
11228 case FLASH_5752PAGE_SIZE_1K:
11229 tp->nvram_pagesize = 1024;
11231 case FLASH_5752PAGE_SIZE_2K:
11232 tp->nvram_pagesize = 2048;
11234 case FLASH_5752PAGE_SIZE_4K:
11235 tp->nvram_pagesize = 4096;
11237 case FLASH_5752PAGE_SIZE_264:
11238 tp->nvram_pagesize = 264;
11240 case FLASH_5752PAGE_SIZE_528:
11241 tp->nvram_pagesize = 528;
11246 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11250 nvcfg1 = tr32(NVRAM_CFG1);
11252 /* NVRAM protection for TPM */
11253 if (nvcfg1 & (1 << 27))
11254 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11256 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11257 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11258 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11259 tp->nvram_jedecnum = JEDEC_ATMEL;
11260 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11262 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11263 tp->nvram_jedecnum = JEDEC_ATMEL;
11264 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11265 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11267 case FLASH_5752VENDOR_ST_M45PE10:
11268 case FLASH_5752VENDOR_ST_M45PE20:
11269 case FLASH_5752VENDOR_ST_M45PE40:
11270 tp->nvram_jedecnum = JEDEC_ST;
11271 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11272 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11276 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11277 tg3_nvram_get_pagesize(tp, nvcfg1);
11279 /* For eeprom, set pagesize to maximum eeprom size */
11280 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11282 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11283 tw32(NVRAM_CFG1, nvcfg1);
11287 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11289 u32 nvcfg1, protect = 0;
11291 nvcfg1 = tr32(NVRAM_CFG1);
11293 /* NVRAM protection for TPM */
11294 if (nvcfg1 & (1 << 27)) {
11295 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11299 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11301 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11302 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11303 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11304 case FLASH_5755VENDOR_ATMEL_FLASH_5:
11305 tp->nvram_jedecnum = JEDEC_ATMEL;
11306 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11307 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11308 tp->nvram_pagesize = 264;
11309 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11310 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11311 tp->nvram_size = (protect ? 0x3e200 :
11312 TG3_NVRAM_SIZE_512KB);
11313 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11314 tp->nvram_size = (protect ? 0x1f200 :
11315 TG3_NVRAM_SIZE_256KB);
11317 tp->nvram_size = (protect ? 0x1f200 :
11318 TG3_NVRAM_SIZE_128KB);
11320 case FLASH_5752VENDOR_ST_M45PE10:
11321 case FLASH_5752VENDOR_ST_M45PE20:
11322 case FLASH_5752VENDOR_ST_M45PE40:
11323 tp->nvram_jedecnum = JEDEC_ST;
11324 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11325 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11326 tp->nvram_pagesize = 256;
11327 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11328 tp->nvram_size = (protect ?
11329 TG3_NVRAM_SIZE_64KB :
11330 TG3_NVRAM_SIZE_128KB);
11331 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11332 tp->nvram_size = (protect ?
11333 TG3_NVRAM_SIZE_64KB :
11334 TG3_NVRAM_SIZE_256KB);
11336 tp->nvram_size = (protect ?
11337 TG3_NVRAM_SIZE_128KB :
11338 TG3_NVRAM_SIZE_512KB);
11343 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11347 nvcfg1 = tr32(NVRAM_CFG1);
11349 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11350 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11351 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11352 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11353 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11354 tp->nvram_jedecnum = JEDEC_ATMEL;
11355 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11356 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11358 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11359 tw32(NVRAM_CFG1, nvcfg1);
11361 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11362 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11363 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11364 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11365 tp->nvram_jedecnum = JEDEC_ATMEL;
11366 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11367 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11368 tp->nvram_pagesize = 264;
11370 case FLASH_5752VENDOR_ST_M45PE10:
11371 case FLASH_5752VENDOR_ST_M45PE20:
11372 case FLASH_5752VENDOR_ST_M45PE40:
11373 tp->nvram_jedecnum = JEDEC_ST;
11374 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11375 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11376 tp->nvram_pagesize = 256;
11381 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11383 u32 nvcfg1, protect = 0;
11385 nvcfg1 = tr32(NVRAM_CFG1);
11387 /* NVRAM protection for TPM */
11388 if (nvcfg1 & (1 << 27)) {
11389 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11393 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11395 case FLASH_5761VENDOR_ATMEL_ADB021D:
11396 case FLASH_5761VENDOR_ATMEL_ADB041D:
11397 case FLASH_5761VENDOR_ATMEL_ADB081D:
11398 case FLASH_5761VENDOR_ATMEL_ADB161D:
11399 case FLASH_5761VENDOR_ATMEL_MDB021D:
11400 case FLASH_5761VENDOR_ATMEL_MDB041D:
11401 case FLASH_5761VENDOR_ATMEL_MDB081D:
11402 case FLASH_5761VENDOR_ATMEL_MDB161D:
11403 tp->nvram_jedecnum = JEDEC_ATMEL;
11404 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11405 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11406 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11407 tp->nvram_pagesize = 256;
11409 case FLASH_5761VENDOR_ST_A_M45PE20:
11410 case FLASH_5761VENDOR_ST_A_M45PE40:
11411 case FLASH_5761VENDOR_ST_A_M45PE80:
11412 case FLASH_5761VENDOR_ST_A_M45PE16:
11413 case FLASH_5761VENDOR_ST_M_M45PE20:
11414 case FLASH_5761VENDOR_ST_M_M45PE40:
11415 case FLASH_5761VENDOR_ST_M_M45PE80:
11416 case FLASH_5761VENDOR_ST_M_M45PE16:
11417 tp->nvram_jedecnum = JEDEC_ST;
11418 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11419 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11420 tp->nvram_pagesize = 256;
11425 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11428 case FLASH_5761VENDOR_ATMEL_ADB161D:
11429 case FLASH_5761VENDOR_ATMEL_MDB161D:
11430 case FLASH_5761VENDOR_ST_A_M45PE16:
11431 case FLASH_5761VENDOR_ST_M_M45PE16:
11432 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11434 case FLASH_5761VENDOR_ATMEL_ADB081D:
11435 case FLASH_5761VENDOR_ATMEL_MDB081D:
11436 case FLASH_5761VENDOR_ST_A_M45PE80:
11437 case FLASH_5761VENDOR_ST_M_M45PE80:
11438 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11440 case FLASH_5761VENDOR_ATMEL_ADB041D:
11441 case FLASH_5761VENDOR_ATMEL_MDB041D:
11442 case FLASH_5761VENDOR_ST_A_M45PE40:
11443 case FLASH_5761VENDOR_ST_M_M45PE40:
11444 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11446 case FLASH_5761VENDOR_ATMEL_ADB021D:
11447 case FLASH_5761VENDOR_ATMEL_MDB021D:
11448 case FLASH_5761VENDOR_ST_A_M45PE20:
11449 case FLASH_5761VENDOR_ST_M_M45PE20:
11450 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11456 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11458 tp->nvram_jedecnum = JEDEC_ATMEL;
11459 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11460 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11463 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11467 nvcfg1 = tr32(NVRAM_CFG1);
11469 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11470 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11471 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11472 tp->nvram_jedecnum = JEDEC_ATMEL;
11473 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11474 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11476 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11477 tw32(NVRAM_CFG1, nvcfg1);
11479 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11480 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11481 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11482 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11483 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11484 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11485 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11486 tp->nvram_jedecnum = JEDEC_ATMEL;
11487 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11488 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11490 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11491 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11492 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11493 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11494 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11496 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11497 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11498 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11500 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11501 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11502 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11506 case FLASH_5752VENDOR_ST_M45PE10:
11507 case FLASH_5752VENDOR_ST_M45PE20:
11508 case FLASH_5752VENDOR_ST_M45PE40:
11509 tp->nvram_jedecnum = JEDEC_ST;
11510 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11511 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11513 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11514 case FLASH_5752VENDOR_ST_M45PE10:
11515 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11517 case FLASH_5752VENDOR_ST_M45PE20:
11518 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11520 case FLASH_5752VENDOR_ST_M45PE40:
11521 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11526 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11530 tg3_nvram_get_pagesize(tp, nvcfg1);
11531 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11532 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11536 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11540 nvcfg1 = tr32(NVRAM_CFG1);
11542 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11543 case FLASH_5717VENDOR_ATMEL_EEPROM:
11544 case FLASH_5717VENDOR_MICRO_EEPROM:
11545 tp->nvram_jedecnum = JEDEC_ATMEL;
11546 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11547 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11549 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11550 tw32(NVRAM_CFG1, nvcfg1);
11552 case FLASH_5717VENDOR_ATMEL_MDB011D:
11553 case FLASH_5717VENDOR_ATMEL_ADB011B:
11554 case FLASH_5717VENDOR_ATMEL_ADB011D:
11555 case FLASH_5717VENDOR_ATMEL_MDB021D:
11556 case FLASH_5717VENDOR_ATMEL_ADB021B:
11557 case FLASH_5717VENDOR_ATMEL_ADB021D:
11558 case FLASH_5717VENDOR_ATMEL_45USPT:
11559 tp->nvram_jedecnum = JEDEC_ATMEL;
11560 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11561 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11563 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11564 case FLASH_5717VENDOR_ATMEL_MDB021D:
11565 case FLASH_5717VENDOR_ATMEL_ADB021B:
11566 case FLASH_5717VENDOR_ATMEL_ADB021D:
11567 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11570 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11574 case FLASH_5717VENDOR_ST_M_M25PE10:
11575 case FLASH_5717VENDOR_ST_A_M25PE10:
11576 case FLASH_5717VENDOR_ST_M_M45PE10:
11577 case FLASH_5717VENDOR_ST_A_M45PE10:
11578 case FLASH_5717VENDOR_ST_M_M25PE20:
11579 case FLASH_5717VENDOR_ST_A_M25PE20:
11580 case FLASH_5717VENDOR_ST_M_M45PE20:
11581 case FLASH_5717VENDOR_ST_A_M45PE20:
11582 case FLASH_5717VENDOR_ST_25USPT:
11583 case FLASH_5717VENDOR_ST_45USPT:
11584 tp->nvram_jedecnum = JEDEC_ST;
11585 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11586 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11588 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11589 case FLASH_5717VENDOR_ST_M_M25PE20:
11590 case FLASH_5717VENDOR_ST_A_M25PE20:
11591 case FLASH_5717VENDOR_ST_M_M45PE20:
11592 case FLASH_5717VENDOR_ST_A_M45PE20:
11593 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11596 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11601 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11605 tg3_nvram_get_pagesize(tp, nvcfg1);
11606 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11607 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11610 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11611 static void __devinit tg3_nvram_init(struct tg3 *tp)
11613 tw32_f(GRC_EEPROM_ADDR,
11614 (EEPROM_ADDR_FSM_RESET |
11615 (EEPROM_DEFAULT_CLOCK_PERIOD <<
11616 EEPROM_ADDR_CLKPERD_SHIFT)));
11620 /* Enable seeprom accesses. */
11621 tw32_f(GRC_LOCAL_CTRL,
11622 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11625 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11626 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11627 tp->tg3_flags |= TG3_FLAG_NVRAM;
11629 if (tg3_nvram_lock(tp)) {
11630 netdev_warn(tp->dev,
11631 "Cannot get nvram lock, %s failed\n",
11635 tg3_enable_nvram_access(tp);
11637 tp->nvram_size = 0;
11639 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11640 tg3_get_5752_nvram_info(tp);
11641 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11642 tg3_get_5755_nvram_info(tp);
11643 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11644 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11645 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11646 tg3_get_5787_nvram_info(tp);
11647 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11648 tg3_get_5761_nvram_info(tp);
11649 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11650 tg3_get_5906_nvram_info(tp);
11651 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11652 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11653 tg3_get_57780_nvram_info(tp);
11654 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
11655 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
11656 tg3_get_5717_nvram_info(tp);
11658 tg3_get_nvram_info(tp);
11660 if (tp->nvram_size == 0)
11661 tg3_get_nvram_size(tp);
11663 tg3_disable_nvram_access(tp);
11664 tg3_nvram_unlock(tp);
11667 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11669 tg3_get_eeprom_size(tp);
11673 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11674 u32 offset, u32 len, u8 *buf)
11679 for (i = 0; i < len; i += 4) {
11685 memcpy(&data, buf + i, 4);
11688 * The SEEPROM interface expects the data to always be opposite
11689 * the native endian format. We accomplish this by reversing
11690 * all the operations that would have been performed on the
11691 * data from a call to tg3_nvram_read_be32().
11693 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11695 val = tr32(GRC_EEPROM_ADDR);
11696 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11698 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11700 tw32(GRC_EEPROM_ADDR, val |
11701 (0 << EEPROM_ADDR_DEVID_SHIFT) |
11702 (addr & EEPROM_ADDR_ADDR_MASK) |
11703 EEPROM_ADDR_START |
11704 EEPROM_ADDR_WRITE);
11706 for (j = 0; j < 1000; j++) {
11707 val = tr32(GRC_EEPROM_ADDR);
11709 if (val & EEPROM_ADDR_COMPLETE)
11713 if (!(val & EEPROM_ADDR_COMPLETE)) {
11722 /* offset and length are dword aligned */
11723 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11727 u32 pagesize = tp->nvram_pagesize;
11728 u32 pagemask = pagesize - 1;
11732 tmp = kmalloc(pagesize, GFP_KERNEL);
11738 u32 phy_addr, page_off, size;
11740 phy_addr = offset & ~pagemask;
11742 for (j = 0; j < pagesize; j += 4) {
11743 ret = tg3_nvram_read_be32(tp, phy_addr + j,
11744 (__be32 *) (tmp + j));
11751 page_off = offset & pagemask;
11758 memcpy(tmp + page_off, buf, size);
11760 offset = offset + (pagesize - page_off);
11762 tg3_enable_nvram_access(tp);
11765 * Before we can erase the flash page, we need
11766 * to issue a special "write enable" command.
11768 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11770 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11773 /* Erase the target page */
11774 tw32(NVRAM_ADDR, phy_addr);
11776 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11777 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11779 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11782 /* Issue another write enable to start the write. */
11783 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11785 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11788 for (j = 0; j < pagesize; j += 4) {
11791 data = *((__be32 *) (tmp + j));
11793 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11795 tw32(NVRAM_ADDR, phy_addr + j);
11797 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11801 nvram_cmd |= NVRAM_CMD_FIRST;
11802 else if (j == (pagesize - 4))
11803 nvram_cmd |= NVRAM_CMD_LAST;
11805 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11812 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11813 tg3_nvram_exec_cmd(tp, nvram_cmd);
11820 /* offset and length are dword aligned */
11821 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11826 for (i = 0; i < len; i += 4, offset += 4) {
11827 u32 page_off, phy_addr, nvram_cmd;
11830 memcpy(&data, buf + i, 4);
11831 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11833 page_off = offset % tp->nvram_pagesize;
11835 phy_addr = tg3_nvram_phys_addr(tp, offset);
11837 tw32(NVRAM_ADDR, phy_addr);
11839 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11841 if (page_off == 0 || i == 0)
11842 nvram_cmd |= NVRAM_CMD_FIRST;
11843 if (page_off == (tp->nvram_pagesize - 4))
11844 nvram_cmd |= NVRAM_CMD_LAST;
11846 if (i == (len - 4))
11847 nvram_cmd |= NVRAM_CMD_LAST;
11849 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11850 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11851 (tp->nvram_jedecnum == JEDEC_ST) &&
11852 (nvram_cmd & NVRAM_CMD_FIRST)) {
11854 if ((ret = tg3_nvram_exec_cmd(tp,
11855 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11860 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11861 /* We always do complete word writes to eeprom. */
11862 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11865 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11871 /* offset and length are dword aligned */
11872 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11876 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11877 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11878 ~GRC_LCLCTRL_GPIO_OUTPUT1);
11882 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11883 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11887 ret = tg3_nvram_lock(tp);
11891 tg3_enable_nvram_access(tp);
11892 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11893 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
11894 tw32(NVRAM_WRITE1, 0x406);
11896 grc_mode = tr32(GRC_MODE);
11897 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11899 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11900 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11902 ret = tg3_nvram_write_block_buffered(tp, offset, len,
11905 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11909 grc_mode = tr32(GRC_MODE);
11910 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11912 tg3_disable_nvram_access(tp);
11913 tg3_nvram_unlock(tp);
11916 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11917 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11924 struct subsys_tbl_ent {
11925 u16 subsys_vendor, subsys_devid;
11929 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
11930 /* Broadcom boards. */
11931 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11932 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
11933 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11934 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
11935 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11936 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
11937 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11938 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
11939 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11940 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
11941 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11942 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
11943 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11944 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
11945 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11946 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
11947 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11948 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
11949 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11950 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
11951 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11952 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
11955 { TG3PCI_SUBVENDOR_ID_3COM,
11956 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
11957 { TG3PCI_SUBVENDOR_ID_3COM,
11958 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
11959 { TG3PCI_SUBVENDOR_ID_3COM,
11960 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
11961 { TG3PCI_SUBVENDOR_ID_3COM,
11962 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
11963 { TG3PCI_SUBVENDOR_ID_3COM,
11964 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
11967 { TG3PCI_SUBVENDOR_ID_DELL,
11968 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
11969 { TG3PCI_SUBVENDOR_ID_DELL,
11970 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
11971 { TG3PCI_SUBVENDOR_ID_DELL,
11972 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
11973 { TG3PCI_SUBVENDOR_ID_DELL,
11974 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
11976 /* Compaq boards. */
11977 { TG3PCI_SUBVENDOR_ID_COMPAQ,
11978 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
11979 { TG3PCI_SUBVENDOR_ID_COMPAQ,
11980 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
11981 { TG3PCI_SUBVENDOR_ID_COMPAQ,
11982 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
11983 { TG3PCI_SUBVENDOR_ID_COMPAQ,
11984 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
11985 { TG3PCI_SUBVENDOR_ID_COMPAQ,
11986 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
11989 { TG3PCI_SUBVENDOR_ID_IBM,
11990 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
11993 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
11997 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11998 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11999 tp->pdev->subsystem_vendor) &&
12000 (subsys_id_to_phy_id[i].subsys_devid ==
12001 tp->pdev->subsystem_device))
12002 return &subsys_id_to_phy_id[i];
12007 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12012 /* On some early chips the SRAM cannot be accessed in D3hot state,
12013 * so need make sure we're in D0.
12015 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12016 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12017 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12020 /* Make sure register accesses (indirect or otherwise)
12021 * will function correctly.
12023 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12024 tp->misc_host_ctrl);
12026 /* The memory arbiter has to be enabled in order for SRAM accesses
12027 * to succeed. Normally on powerup the tg3 chip firmware will make
12028 * sure it is enabled, but other entities such as system netboot
12029 * code might disable it.
12031 val = tr32(MEMARB_MODE);
12032 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12034 tp->phy_id = TG3_PHY_ID_INVALID;
12035 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12037 /* Assume an onboard device and WOL capable by default. */
12038 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12040 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12041 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12042 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12043 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12045 val = tr32(VCPU_CFGSHDW);
12046 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12047 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12048 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12049 (val & VCPU_CFGSHDW_WOL_MAGPKT))
12050 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12054 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12055 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12056 u32 nic_cfg, led_cfg;
12057 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12058 int eeprom_phy_serdes = 0;
12060 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12061 tp->nic_sram_data_cfg = nic_cfg;
12063 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12064 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12065 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12066 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12067 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12068 (ver > 0) && (ver < 0x100))
12069 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12071 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12072 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12074 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12075 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12076 eeprom_phy_serdes = 1;
12078 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12079 if (nic_phy_id != 0) {
12080 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12081 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12083 eeprom_phy_id = (id1 >> 16) << 10;
12084 eeprom_phy_id |= (id2 & 0xfc00) << 16;
12085 eeprom_phy_id |= (id2 & 0x03ff) << 0;
12089 tp->phy_id = eeprom_phy_id;
12090 if (eeprom_phy_serdes) {
12091 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12092 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12094 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
12097 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12098 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12099 SHASTA_EXT_LED_MODE_MASK);
12101 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12105 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12106 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12109 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12110 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12113 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12114 tp->led_ctrl = LED_CTRL_MODE_MAC;
12116 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12117 * read on some older 5700/5701 bootcode.
12119 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12121 GET_ASIC_REV(tp->pci_chip_rev_id) ==
12123 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12127 case SHASTA_EXT_LED_SHARED:
12128 tp->led_ctrl = LED_CTRL_MODE_SHARED;
12129 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12130 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12131 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12132 LED_CTRL_MODE_PHY_2);
12135 case SHASTA_EXT_LED_MAC:
12136 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12139 case SHASTA_EXT_LED_COMBO:
12140 tp->led_ctrl = LED_CTRL_MODE_COMBO;
12141 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12142 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12143 LED_CTRL_MODE_PHY_2);
12148 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12149 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12150 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12151 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12153 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12154 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12156 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12157 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12158 if ((tp->pdev->subsystem_vendor ==
12159 PCI_VENDOR_ID_ARIMA) &&
12160 (tp->pdev->subsystem_device == 0x205a ||
12161 tp->pdev->subsystem_device == 0x2063))
12162 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12164 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12165 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12168 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12169 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12170 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12171 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12174 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12175 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12176 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12178 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
12179 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12180 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12182 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12183 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12184 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12186 if (cfg2 & (1 << 17))
12187 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
12189 /* serdes signal pre-emphasis in register 0x590 set by */
12190 /* bootcode if bit 18 is set */
12191 if (cfg2 & (1 << 18))
12192 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
12194 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12195 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
12196 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12197 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
12199 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12200 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12201 !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
12204 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12205 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12206 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12209 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12210 tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
12211 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12212 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12213 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12214 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12217 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12218 device_set_wakeup_enable(&tp->pdev->dev,
12219 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12222 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12227 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12228 tw32(OTP_CTRL, cmd);
12230 /* Wait for up to 1 ms for command to execute. */
12231 for (i = 0; i < 100; i++) {
12232 val = tr32(OTP_STATUS);
12233 if (val & OTP_STATUS_CMD_DONE)
12238 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12241 /* Read the gphy configuration from the OTP region of the chip. The gphy
12242 * configuration is a 32-bit value that straddles the alignment boundary.
12243 * We do two 32-bit reads and then shift and merge the results.
12245 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12247 u32 bhalf_otp, thalf_otp;
12249 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12251 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12254 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12256 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12259 thalf_otp = tr32(OTP_READ_DATA);
12261 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12263 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12266 bhalf_otp = tr32(OTP_READ_DATA);
12268 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12271 static int __devinit tg3_phy_probe(struct tg3 *tp)
12273 u32 hw_phy_id_1, hw_phy_id_2;
12274 u32 hw_phy_id, hw_phy_id_masked;
12277 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12278 return tg3_phy_init(tp);
12280 /* Reading the PHY ID register can conflict with ASF
12281 * firmware access to the PHY hardware.
12284 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12285 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12286 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
12288 /* Now read the physical PHY_ID from the chip and verify
12289 * that it is sane. If it doesn't look good, we fall back
12290 * to either the hard-coded table based PHY_ID and failing
12291 * that the value found in the eeprom area.
12293 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12294 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12296 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
12297 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12298 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
12300 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
12303 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
12304 tp->phy_id = hw_phy_id;
12305 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
12306 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12308 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
12310 if (tp->phy_id != TG3_PHY_ID_INVALID) {
12311 /* Do nothing, phy ID already set up in
12312 * tg3_get_eeprom_hw_cfg().
12315 struct subsys_tbl_ent *p;
12317 /* No eeprom signature? Try the hardcoded
12318 * subsys device table.
12320 p = tg3_lookup_by_subsys(tp);
12324 tp->phy_id = p->phy_id;
12326 tp->phy_id == TG3_PHY_ID_BCM8002)
12327 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12331 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
12332 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12333 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12334 u32 bmsr, adv_reg, tg3_ctrl, mask;
12336 tg3_readphy(tp, MII_BMSR, &bmsr);
12337 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12338 (bmsr & BMSR_LSTATUS))
12339 goto skip_phy_reset;
12341 err = tg3_phy_reset(tp);
12345 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12346 ADVERTISE_100HALF | ADVERTISE_100FULL |
12347 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12349 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12350 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12351 MII_TG3_CTRL_ADV_1000_FULL);
12352 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12353 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12354 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12355 MII_TG3_CTRL_ENABLE_AS_MASTER);
12358 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12359 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12360 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12361 if (!tg3_copper_is_advertising_all(tp, mask)) {
12362 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12364 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12365 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12367 tg3_writephy(tp, MII_BMCR,
12368 BMCR_ANENABLE | BMCR_ANRESTART);
12370 tg3_phy_set_wirespeed(tp);
12372 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12373 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12374 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12378 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
12379 err = tg3_init_5401phy_dsp(tp);
12383 err = tg3_init_5401phy_dsp(tp);
12386 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
12387 tp->link_config.advertising =
12388 (ADVERTISED_1000baseT_Half |
12389 ADVERTISED_1000baseT_Full |
12390 ADVERTISED_Autoneg |
12392 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12393 tp->link_config.advertising &=
12394 ~(ADVERTISED_1000baseT_Half |
12395 ADVERTISED_1000baseT_Full);
12400 static void __devinit tg3_read_vpd(struct tg3 *tp)
12402 u8 vpd_data[TG3_NVM_VPD_LEN];
12403 unsigned int block_end, rosize, len;
12407 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12408 tg3_nvram_read(tp, 0x0, &magic))
12409 goto out_not_found;
12411 if (magic == TG3_EEPROM_MAGIC) {
12412 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12415 /* The data is in little-endian format in NVRAM.
12416 * Use the big-endian read routines to preserve
12417 * the byte order as it exists in NVRAM.
12419 if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12420 goto out_not_found;
12422 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12426 unsigned int pos = 0;
12428 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12429 cnt = pci_read_vpd(tp->pdev, pos,
12430 TG3_NVM_VPD_LEN - pos,
12432 if (cnt == -ETIMEDOUT || -EINTR)
12435 goto out_not_found;
12437 if (pos != TG3_NVM_VPD_LEN)
12438 goto out_not_found;
12441 i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
12442 PCI_VPD_LRDT_RO_DATA);
12444 goto out_not_found;
12446 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
12447 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
12448 i += PCI_VPD_LRDT_TAG_SIZE;
12450 if (block_end > TG3_NVM_VPD_LEN)
12451 goto out_not_found;
12453 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12454 PCI_VPD_RO_KEYWORD_MFR_ID);
12456 len = pci_vpd_info_field_size(&vpd_data[j]);
12458 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12459 if (j + len > block_end || len != 4 ||
12460 memcmp(&vpd_data[j], "1028", 4))
12463 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12464 PCI_VPD_RO_KEYWORD_VENDOR0);
12468 len = pci_vpd_info_field_size(&vpd_data[j]);
12470 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12471 if (j + len > block_end)
12474 memcpy(tp->fw_ver, &vpd_data[j], len);
12475 strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
12479 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12480 PCI_VPD_RO_KEYWORD_PARTNO);
12482 goto out_not_found;
12484 len = pci_vpd_info_field_size(&vpd_data[i]);
12486 i += PCI_VPD_INFO_FLD_HDR_SIZE;
12487 if (len > TG3_BPN_SIZE ||
12488 (len + i) > TG3_NVM_VPD_LEN)
12489 goto out_not_found;
12491 memcpy(tp->board_part_number, &vpd_data[i], len);
12496 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12497 strcpy(tp->board_part_number, "BCM95906");
12498 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12499 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12500 strcpy(tp->board_part_number, "BCM57780");
12501 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12502 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12503 strcpy(tp->board_part_number, "BCM57760");
12504 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12505 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12506 strcpy(tp->board_part_number, "BCM57790");
12507 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12508 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12509 strcpy(tp->board_part_number, "BCM57788");
12510 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12511 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
12512 strcpy(tp->board_part_number, "BCM57761");
12513 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12514 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
12515 strcpy(tp->board_part_number, "BCM57765");
12516 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12517 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
12518 strcpy(tp->board_part_number, "BCM57781");
12519 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12520 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
12521 strcpy(tp->board_part_number, "BCM57785");
12522 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12523 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
12524 strcpy(tp->board_part_number, "BCM57791");
12525 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12526 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12527 strcpy(tp->board_part_number, "BCM57795");
12529 strcpy(tp->board_part_number, "none");
12532 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12536 if (tg3_nvram_read(tp, offset, &val) ||
12537 (val & 0xfc000000) != 0x0c000000 ||
12538 tg3_nvram_read(tp, offset + 4, &val) ||
12545 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12547 u32 val, offset, start, ver_offset;
12549 bool newver = false;
12551 if (tg3_nvram_read(tp, 0xc, &offset) ||
12552 tg3_nvram_read(tp, 0x4, &start))
12555 offset = tg3_nvram_logical_addr(tp, offset);
12557 if (tg3_nvram_read(tp, offset, &val))
12560 if ((val & 0xfc000000) == 0x0c000000) {
12561 if (tg3_nvram_read(tp, offset + 4, &val))
12568 dst_off = strlen(tp->fw_ver);
12571 if (TG3_VER_SIZE - dst_off < 16 ||
12572 tg3_nvram_read(tp, offset + 8, &ver_offset))
12575 offset = offset + ver_offset - start;
12576 for (i = 0; i < 16; i += 4) {
12578 if (tg3_nvram_read_be32(tp, offset + i, &v))
12581 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
12586 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12589 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12590 TG3_NVM_BCVER_MAJSFT;
12591 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12592 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
12593 "v%d.%02d", major, minor);
12597 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12599 u32 val, major, minor;
12601 /* Use native endian representation */
12602 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12605 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12606 TG3_NVM_HWSB_CFG1_MAJSFT;
12607 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12608 TG3_NVM_HWSB_CFG1_MINSFT;
12610 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12613 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12615 u32 offset, major, minor, build;
12617 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
12619 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12622 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12623 case TG3_EEPROM_SB_REVISION_0:
12624 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12626 case TG3_EEPROM_SB_REVISION_2:
12627 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12629 case TG3_EEPROM_SB_REVISION_3:
12630 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12632 case TG3_EEPROM_SB_REVISION_4:
12633 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
12635 case TG3_EEPROM_SB_REVISION_5:
12636 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
12642 if (tg3_nvram_read(tp, offset, &val))
12645 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12646 TG3_EEPROM_SB_EDH_BLD_SHFT;
12647 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12648 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12649 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
12651 if (minor > 99 || build > 26)
12654 offset = strlen(tp->fw_ver);
12655 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
12656 " v%d.%02d", major, minor);
12659 offset = strlen(tp->fw_ver);
12660 if (offset < TG3_VER_SIZE - 1)
12661 tp->fw_ver[offset] = 'a' + build - 1;
12665 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12667 u32 val, offset, start;
12670 for (offset = TG3_NVM_DIR_START;
12671 offset < TG3_NVM_DIR_END;
12672 offset += TG3_NVM_DIRENT_SIZE) {
12673 if (tg3_nvram_read(tp, offset, &val))
12676 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12680 if (offset == TG3_NVM_DIR_END)
12683 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12684 start = 0x08000000;
12685 else if (tg3_nvram_read(tp, offset - 4, &start))
12688 if (tg3_nvram_read(tp, offset + 4, &offset) ||
12689 !tg3_fw_img_is_valid(tp, offset) ||
12690 tg3_nvram_read(tp, offset + 8, &val))
12693 offset += val - start;
12695 vlen = strlen(tp->fw_ver);
12697 tp->fw_ver[vlen++] = ',';
12698 tp->fw_ver[vlen++] = ' ';
12700 for (i = 0; i < 4; i++) {
12702 if (tg3_nvram_read_be32(tp, offset, &v))
12705 offset += sizeof(v);
12707 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12708 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12712 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12717 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12723 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12724 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
12727 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12728 if (apedata != APE_SEG_SIG_MAGIC)
12731 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12732 if (!(apedata & APE_FW_STATUS_READY))
12735 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12737 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI)
12742 vlen = strlen(tp->fw_ver);
12744 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
12746 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12747 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12748 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12749 (apedata & APE_FW_VERSION_BLDMSK));
12752 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12755 bool vpd_vers = false;
12757 if (tp->fw_ver[0] != 0)
12760 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12761 strcat(tp->fw_ver, "sb");
12765 if (tg3_nvram_read(tp, 0, &val))
12768 if (val == TG3_EEPROM_MAGIC)
12769 tg3_read_bc_ver(tp);
12770 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12771 tg3_read_sb_ver(tp, val);
12772 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12773 tg3_read_hwsb_ver(tp);
12777 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12778 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
12781 tg3_read_mgmtfw_ver(tp);
12784 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12787 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12789 static void inline vlan_features_add(struct net_device *dev, unsigned long flags)
12791 #if TG3_VLAN_TAG_USED
12792 dev->vlan_features |= flags;
12796 static int __devinit tg3_get_invariants(struct tg3 *tp)
12798 static struct pci_device_id write_reorder_chipsets[] = {
12799 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12800 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12801 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12802 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12803 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12804 PCI_DEVICE_ID_VIA_8385_0) },
12808 u32 pci_state_reg, grc_misc_cfg;
12813 /* Force memory write invalidate off. If we leave it on,
12814 * then on 5700_BX chips we have to enable a workaround.
12815 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12816 * to match the cacheline size. The Broadcom driver have this
12817 * workaround but turns MWI off all the times so never uses
12818 * it. This seems to suggest that the workaround is insufficient.
12820 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12821 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12822 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12824 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12825 * has the register indirect write enable bit set before
12826 * we try to access any of the MMIO registers. It is also
12827 * critical that the PCI-X hw workaround situation is decided
12828 * before that as well.
12830 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12833 tp->pci_chip_rev_id = (misc_ctrl_reg >>
12834 MISC_HOST_CTRL_CHIPREV_SHIFT);
12835 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12836 u32 prod_id_asic_rev;
12838 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12839 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12840 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724 ||
12841 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719)
12842 pci_read_config_dword(tp->pdev,
12843 TG3PCI_GEN2_PRODID_ASICREV,
12844 &prod_id_asic_rev);
12845 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
12846 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
12847 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
12848 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
12849 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
12850 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12851 pci_read_config_dword(tp->pdev,
12852 TG3PCI_GEN15_PRODID_ASICREV,
12853 &prod_id_asic_rev);
12855 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12856 &prod_id_asic_rev);
12858 tp->pci_chip_rev_id = prod_id_asic_rev;
12861 /* Wrong chip ID in 5752 A0. This code can be removed later
12862 * as A0 is not in production.
12864 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12865 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12867 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12868 * we need to disable memory and use config. cycles
12869 * only to access all registers. The 5702/03 chips
12870 * can mistakenly decode the special cycles from the
12871 * ICH chipsets as memory write cycles, causing corruption
12872 * of register and memory space. Only certain ICH bridges
12873 * will drive special cycles with non-zero data during the
12874 * address phase which can fall within the 5703's address
12875 * range. This is not an ICH bug as the PCI spec allows
12876 * non-zero address during special cycles. However, only
12877 * these ICH bridges are known to drive non-zero addresses
12878 * during special cycles.
12880 * Since special cycles do not cross PCI bridges, we only
12881 * enable this workaround if the 5703 is on the secondary
12882 * bus of these ICH bridges.
12884 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12885 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12886 static struct tg3_dev_id {
12890 } ich_chipsets[] = {
12891 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12893 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12895 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12897 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12901 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12902 struct pci_dev *bridge = NULL;
12904 while (pci_id->vendor != 0) {
12905 bridge = pci_get_device(pci_id->vendor, pci_id->device,
12911 if (pci_id->rev != PCI_ANY_ID) {
12912 if (bridge->revision > pci_id->rev)
12915 if (bridge->subordinate &&
12916 (bridge->subordinate->number ==
12917 tp->pdev->bus->number)) {
12919 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12920 pci_dev_put(bridge);
12926 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12927 static struct tg3_dev_id {
12930 } bridge_chipsets[] = {
12931 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12932 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12935 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12936 struct pci_dev *bridge = NULL;
12938 while (pci_id->vendor != 0) {
12939 bridge = pci_get_device(pci_id->vendor,
12946 if (bridge->subordinate &&
12947 (bridge->subordinate->number <=
12948 tp->pdev->bus->number) &&
12949 (bridge->subordinate->subordinate >=
12950 tp->pdev->bus->number)) {
12951 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12952 pci_dev_put(bridge);
12958 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12959 * DMA addresses > 40-bit. This bridge may have other additional
12960 * 57xx devices behind it in some 4-port NIC designs for example.
12961 * Any tg3 device found behind the bridge will also need the 40-bit
12964 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12965 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12966 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
12967 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12968 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
12970 struct pci_dev *bridge = NULL;
12973 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12974 PCI_DEVICE_ID_SERVERWORKS_EPB,
12976 if (bridge && bridge->subordinate &&
12977 (bridge->subordinate->number <=
12978 tp->pdev->bus->number) &&
12979 (bridge->subordinate->subordinate >=
12980 tp->pdev->bus->number)) {
12981 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12982 pci_dev_put(bridge);
12988 /* Initialize misc host control in PCI block. */
12989 tp->misc_host_ctrl |= (misc_ctrl_reg &
12990 MISC_HOST_CTRL_CHIPREV);
12991 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12992 tp->misc_host_ctrl);
12994 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
12995 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
12996 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12997 tp->pdev_peer = tg3_find_peer(tp);
12999 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13000 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13001 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13002 tp->tg3_flags3 |= TG3_FLG3_5717_PLUS;
13004 /* Intentionally exclude ASIC_REV_5906 */
13005 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13006 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13007 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13008 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13009 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13010 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13011 (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13012 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13014 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13015 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13016 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13017 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13018 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13019 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13021 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13022 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13023 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13025 /* 5700 B0 chips do not support checksumming correctly due
13026 * to hardware bugs.
13028 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13029 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13031 unsigned long features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_GRO;
13033 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13034 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13035 features |= NETIF_F_IPV6_CSUM;
13036 tp->dev->features |= features;
13037 vlan_features_add(tp->dev, features);
13040 /* Determine TSO capabilities */
13041 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13042 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13043 else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13044 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13045 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13046 else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13047 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13048 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13049 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13050 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13051 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13052 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13053 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13054 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13055 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13056 tp->fw_needed = FIRMWARE_TG3TSO5;
13058 tp->fw_needed = FIRMWARE_TG3TSO;
13063 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13064 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13065 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13066 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13067 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13068 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13069 tp->pdev_peer == tp->pdev))
13070 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13072 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13073 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13074 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13077 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
13078 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13079 tp->irq_max = TG3_IRQ_MAX_VECS;
13083 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13084 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13085 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13086 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13087 else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13088 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13089 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13092 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13093 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13095 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13096 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13097 (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13098 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13100 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13103 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13104 if (tp->pcie_cap != 0) {
13107 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13109 pcie_set_readrq(tp->pdev, 4096);
13111 pci_read_config_word(tp->pdev,
13112 tp->pcie_cap + PCI_EXP_LNKCTL,
13114 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13115 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13116 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13117 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13118 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13119 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13120 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13121 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13122 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13123 tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13125 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13126 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13127 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13128 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13129 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13130 if (!tp->pcix_cap) {
13131 dev_err(&tp->pdev->dev,
13132 "Cannot find PCI-X capability, aborting\n");
13136 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13137 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13140 /* If we have an AMD 762 or VIA K8T800 chipset, write
13141 * reordering to the mailbox registers done by the host
13142 * controller can cause major troubles. We read back from
13143 * every mailbox register write to force the writes to be
13144 * posted to the chip in order.
13146 if (pci_dev_present(write_reorder_chipsets) &&
13147 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13148 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13150 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13151 &tp->pci_cacheline_sz);
13152 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13153 &tp->pci_lat_timer);
13154 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13155 tp->pci_lat_timer < 64) {
13156 tp->pci_lat_timer = 64;
13157 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13158 tp->pci_lat_timer);
13161 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13162 /* 5700 BX chips need to have their TX producer index
13163 * mailboxes written twice to workaround a bug.
13165 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13167 /* If we are in PCI-X mode, enable register write workaround.
13169 * The workaround is to use indirect register accesses
13170 * for all chip writes not to mailbox registers.
13172 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13175 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13177 /* The chip can have it's power management PCI config
13178 * space registers clobbered due to this bug.
13179 * So explicitly force the chip into D0 here.
13181 pci_read_config_dword(tp->pdev,
13182 tp->pm_cap + PCI_PM_CTRL,
13184 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13185 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13186 pci_write_config_dword(tp->pdev,
13187 tp->pm_cap + PCI_PM_CTRL,
13190 /* Also, force SERR#/PERR# in PCI command. */
13191 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13192 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13193 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13197 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13198 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13199 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13200 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13202 /* Chip-specific fixup from Broadcom driver */
13203 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13204 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13205 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13206 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13209 /* Default fast path register access methods */
13210 tp->read32 = tg3_read32;
13211 tp->write32 = tg3_write32;
13212 tp->read32_mbox = tg3_read32;
13213 tp->write32_mbox = tg3_write32;
13214 tp->write32_tx_mbox = tg3_write32;
13215 tp->write32_rx_mbox = tg3_write32;
13217 /* Various workaround register access methods */
13218 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13219 tp->write32 = tg3_write_indirect_reg32;
13220 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13221 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13222 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13224 * Back to back register writes can cause problems on these
13225 * chips, the workaround is to read back all reg writes
13226 * except those to mailbox regs.
13228 * See tg3_write_indirect_reg32().
13230 tp->write32 = tg3_write_flush_reg32;
13233 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13234 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13235 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13236 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13237 tp->write32_rx_mbox = tg3_write_flush_reg32;
13240 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13241 tp->read32 = tg3_read_indirect_reg32;
13242 tp->write32 = tg3_write_indirect_reg32;
13243 tp->read32_mbox = tg3_read_indirect_mbox;
13244 tp->write32_mbox = tg3_write_indirect_mbox;
13245 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13246 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13251 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13252 pci_cmd &= ~PCI_COMMAND_MEMORY;
13253 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13255 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13256 tp->read32_mbox = tg3_read32_mbox_5906;
13257 tp->write32_mbox = tg3_write32_mbox_5906;
13258 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13259 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13262 if (tp->write32 == tg3_write_indirect_reg32 ||
13263 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13264 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13265 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13266 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13268 /* Get eeprom hw config before calling tg3_set_power_state().
13269 * In particular, the TG3_FLG2_IS_NIC flag must be
13270 * determined before calling tg3_set_power_state() so that
13271 * we know whether or not to switch out of Vaux power.
13272 * When the flag is set, it means that GPIO1 is used for eeprom
13273 * write protect and also implies that it is a LOM where GPIOs
13274 * are not used to switch power.
13276 tg3_get_eeprom_hw_cfg(tp);
13278 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13279 /* Allow reads and writes to the
13280 * APE register and memory space.
13282 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13283 PCISTATE_ALLOW_APE_SHMEM_WR |
13284 PCISTATE_ALLOW_APE_PSPACE_WR;
13285 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13289 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13290 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13291 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13292 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13293 (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13294 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13296 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13297 * GPIO1 driven high will bring 5700's external PHY out of reset.
13298 * It is also used as eeprom write protect on LOMs.
13300 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13301 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13302 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13303 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13304 GRC_LCLCTRL_GPIO_OUTPUT1);
13305 /* Unused GPIO3 must be driven as output on 5752 because there
13306 * are no pull-up resistors on unused GPIO pins.
13308 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13309 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13311 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13312 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13313 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13314 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13316 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13317 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13318 /* Turn off the debug UART. */
13319 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13320 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13321 /* Keep VMain power. */
13322 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13323 GRC_LCLCTRL_GPIO_OUTPUT0;
13326 /* Force the chip into D0. */
13327 err = tg3_set_power_state(tp, PCI_D0);
13329 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
13333 /* Derive initial jumbo mode from MTU assigned in
13334 * ether_setup() via the alloc_etherdev() call
13336 if (tp->dev->mtu > ETH_DATA_LEN &&
13337 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13338 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13340 /* Determine WakeOnLan speed to use. */
13341 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13342 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13343 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13344 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13345 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13347 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13350 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13351 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
13353 /* A few boards don't want Ethernet@WireSpeed phy feature */
13354 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13355 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13356 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13357 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13358 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
13359 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
13360 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
13362 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13363 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13364 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
13365 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13366 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
13368 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13369 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
13370 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13371 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13372 !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
13373 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13374 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13375 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13376 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13377 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13378 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13379 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
13380 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13381 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
13383 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
13386 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13387 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13388 tp->phy_otp = tg3_read_otp_phycfg(tp);
13389 if (tp->phy_otp == 0)
13390 tp->phy_otp = TG3_OTP_DEFAULT;
13393 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13394 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13396 tp->mi_mode = MAC_MI_MODE_BASE;
13398 tp->coalesce_mode = 0;
13399 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13400 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13401 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13403 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13404 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13405 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13407 err = tg3_mdio_init(tp);
13411 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
13412 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
13415 /* Initialize data/descriptor byte/word swapping. */
13416 val = tr32(GRC_MODE);
13417 val &= GRC_MODE_HOST_STACKUP;
13418 tw32(GRC_MODE, val | tp->grc_mode);
13420 tg3_switch_clocks(tp);
13422 /* Clear this out for sanity. */
13423 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13425 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13427 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13428 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13429 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13431 if (chiprevid == CHIPREV_ID_5701_A0 ||
13432 chiprevid == CHIPREV_ID_5701_B0 ||
13433 chiprevid == CHIPREV_ID_5701_B2 ||
13434 chiprevid == CHIPREV_ID_5701_B5) {
13435 void __iomem *sram_base;
13437 /* Write some dummy words into the SRAM status block
13438 * area, see if it reads back correctly. If the return
13439 * value is bad, force enable the PCIX workaround.
13441 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13443 writel(0x00000000, sram_base);
13444 writel(0x00000000, sram_base + 4);
13445 writel(0xffffffff, sram_base + 4);
13446 if (readl(sram_base) != 0x00000000)
13447 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13452 tg3_nvram_init(tp);
13454 grc_misc_cfg = tr32(GRC_MISC_CFG);
13455 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13457 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13458 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13459 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13460 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13462 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13463 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13464 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13465 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13466 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13467 HOSTCC_MODE_CLRTICK_TXBD);
13469 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13470 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13471 tp->misc_host_ctrl);
13474 /* Preserve the APE MAC_MODE bits */
13475 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13476 tp->mac_mode = tr32(MAC_MODE) |
13477 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13479 tp->mac_mode = TG3_DEF_MAC_MODE;
13481 /* these are limited to 10/100 only */
13482 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13483 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13484 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13485 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13486 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13487 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13488 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13489 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13490 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13491 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13492 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13493 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13494 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13495 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
13496 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
13497 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13499 err = tg3_phy_probe(tp);
13501 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
13502 /* ... but do not return immediately ... */
13507 tg3_read_fw_ver(tp);
13509 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13510 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13512 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13513 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13515 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13518 /* 5700 {AX,BX} chips have a broken status block link
13519 * change bit implementation, so we must use the
13520 * status register in those cases.
13522 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13523 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13525 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13527 /* The led_ctrl is set during tg3_phy_probe, here we might
13528 * have to force the link status polling mechanism based
13529 * upon subsystem IDs.
13531 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13532 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13533 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13534 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13535 TG3_FLAG_USE_LINKCHG_REG);
13538 /* For all SERDES we poll the MAC status register. */
13539 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13540 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13542 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13544 tp->rx_offset = NET_IP_ALIGN + TG3_RX_HEADROOM;
13545 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
13546 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13547 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
13548 tp->rx_offset -= NET_IP_ALIGN;
13549 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
13550 tp->rx_copy_thresh = ~(u16)0;
13554 tp->rx_std_max_post = TG3_RX_RING_SIZE;
13556 /* Increment the rx prod index on the rx std ring by at most
13557 * 8 for these chips to workaround hw errata.
13559 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13560 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13561 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13562 tp->rx_std_max_post = 8;
13564 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13565 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13566 PCIE_PWR_MGMT_L1_THRESH_MSK;
13571 #ifdef CONFIG_SPARC
13572 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13574 struct net_device *dev = tp->dev;
13575 struct pci_dev *pdev = tp->pdev;
13576 struct device_node *dp = pci_device_to_OF_node(pdev);
13577 const unsigned char *addr;
13580 addr = of_get_property(dp, "local-mac-address", &len);
13581 if (addr && len == 6) {
13582 memcpy(dev->dev_addr, addr, 6);
13583 memcpy(dev->perm_addr, dev->dev_addr, 6);
13589 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13591 struct net_device *dev = tp->dev;
13593 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13594 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13599 static int __devinit tg3_get_device_address(struct tg3 *tp)
13601 struct net_device *dev = tp->dev;
13602 u32 hi, lo, mac_offset;
13605 #ifdef CONFIG_SPARC
13606 if (!tg3_get_macaddr_sparc(tp))
13611 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13612 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13613 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13615 if (tg3_nvram_lock(tp))
13616 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13618 tg3_nvram_unlock(tp);
13619 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13620 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
13621 if (PCI_FUNC(tp->pdev->devfn) & 1)
13623 if (PCI_FUNC(tp->pdev->devfn) > 1)
13624 mac_offset += 0x18c;
13625 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13628 /* First try to get it from MAC address mailbox. */
13629 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13630 if ((hi >> 16) == 0x484b) {
13631 dev->dev_addr[0] = (hi >> 8) & 0xff;
13632 dev->dev_addr[1] = (hi >> 0) & 0xff;
13634 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13635 dev->dev_addr[2] = (lo >> 24) & 0xff;
13636 dev->dev_addr[3] = (lo >> 16) & 0xff;
13637 dev->dev_addr[4] = (lo >> 8) & 0xff;
13638 dev->dev_addr[5] = (lo >> 0) & 0xff;
13640 /* Some old bootcode may report a 0 MAC address in SRAM */
13641 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13644 /* Next, try NVRAM. */
13645 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13646 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13647 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13648 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13649 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13651 /* Finally just fetch it out of the MAC control regs. */
13653 hi = tr32(MAC_ADDR_0_HIGH);
13654 lo = tr32(MAC_ADDR_0_LOW);
13656 dev->dev_addr[5] = lo & 0xff;
13657 dev->dev_addr[4] = (lo >> 8) & 0xff;
13658 dev->dev_addr[3] = (lo >> 16) & 0xff;
13659 dev->dev_addr[2] = (lo >> 24) & 0xff;
13660 dev->dev_addr[1] = hi & 0xff;
13661 dev->dev_addr[0] = (hi >> 8) & 0xff;
13665 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13666 #ifdef CONFIG_SPARC
13667 if (!tg3_get_default_macaddr_sparc(tp))
13672 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13676 #define BOUNDARY_SINGLE_CACHELINE 1
13677 #define BOUNDARY_MULTI_CACHELINE 2
13679 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13681 int cacheline_size;
13685 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13687 cacheline_size = 1024;
13689 cacheline_size = (int) byte * 4;
13691 /* On 5703 and later chips, the boundary bits have no
13694 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13695 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13696 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13699 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13700 goal = BOUNDARY_MULTI_CACHELINE;
13702 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13703 goal = BOUNDARY_SINGLE_CACHELINE;
13709 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
13710 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13717 /* PCI controllers on most RISC systems tend to disconnect
13718 * when a device tries to burst across a cache-line boundary.
13719 * Therefore, letting tg3 do so just wastes PCI bandwidth.
13721 * Unfortunately, for PCI-E there are only limited
13722 * write-side controls for this, and thus for reads
13723 * we will still get the disconnects. We'll also waste
13724 * these PCI cycles for both read and write for chips
13725 * other than 5700 and 5701 which do not implement the
13728 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13729 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13730 switch (cacheline_size) {
13735 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13736 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13737 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13739 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13740 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13745 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13746 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13750 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13751 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13754 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13755 switch (cacheline_size) {
13759 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13760 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13761 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13767 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13768 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13772 switch (cacheline_size) {
13774 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13775 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13776 DMA_RWCTRL_WRITE_BNDRY_16);
13781 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13782 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13783 DMA_RWCTRL_WRITE_BNDRY_32);
13788 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13789 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13790 DMA_RWCTRL_WRITE_BNDRY_64);
13795 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13796 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13797 DMA_RWCTRL_WRITE_BNDRY_128);
13802 val |= (DMA_RWCTRL_READ_BNDRY_256 |
13803 DMA_RWCTRL_WRITE_BNDRY_256);
13806 val |= (DMA_RWCTRL_READ_BNDRY_512 |
13807 DMA_RWCTRL_WRITE_BNDRY_512);
13811 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13812 DMA_RWCTRL_WRITE_BNDRY_1024);
13821 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13823 struct tg3_internal_buffer_desc test_desc;
13824 u32 sram_dma_descs;
13827 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13829 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13830 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13831 tw32(RDMAC_STATUS, 0);
13832 tw32(WDMAC_STATUS, 0);
13834 tw32(BUFMGR_MODE, 0);
13835 tw32(FTQ_RESET, 0);
13837 test_desc.addr_hi = ((u64) buf_dma) >> 32;
13838 test_desc.addr_lo = buf_dma & 0xffffffff;
13839 test_desc.nic_mbuf = 0x00002100;
13840 test_desc.len = size;
13843 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13844 * the *second* time the tg3 driver was getting loaded after an
13847 * Broadcom tells me:
13848 * ...the DMA engine is connected to the GRC block and a DMA
13849 * reset may affect the GRC block in some unpredictable way...
13850 * The behavior of resets to individual blocks has not been tested.
13852 * Broadcom noted the GRC reset will also reset all sub-components.
13855 test_desc.cqid_sqid = (13 << 8) | 2;
13857 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13860 test_desc.cqid_sqid = (16 << 8) | 7;
13862 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13865 test_desc.flags = 0x00000005;
13867 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13870 val = *(((u32 *)&test_desc) + i);
13871 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13872 sram_dma_descs + (i * sizeof(u32)));
13873 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13875 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13878 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13880 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13883 for (i = 0; i < 40; i++) {
13887 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13889 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13890 if ((val & 0xffff) == sram_dma_descs) {
13901 #define TEST_BUFFER_SIZE 0x2000
13903 static int __devinit tg3_test_dma(struct tg3 *tp)
13905 dma_addr_t buf_dma;
13906 u32 *buf, saved_dma_rwctrl;
13909 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13915 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13916 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13918 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13920 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13923 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13924 /* DMA read watermark not used on PCIE */
13925 tp->dma_rwctrl |= 0x00180000;
13926 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
13927 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13928 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
13929 tp->dma_rwctrl |= 0x003f0000;
13931 tp->dma_rwctrl |= 0x003f000f;
13933 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13934 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13935 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
13936 u32 read_water = 0x7;
13938 /* If the 5704 is behind the EPB bridge, we can
13939 * do the less restrictive ONE_DMA workaround for
13940 * better performance.
13942 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13943 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13944 tp->dma_rwctrl |= 0x8000;
13945 else if (ccval == 0x6 || ccval == 0x7)
13946 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13948 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13950 /* Set bit 23 to enable PCIX hw bug fix */
13952 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13953 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13955 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13956 /* 5780 always in PCIX mode */
13957 tp->dma_rwctrl |= 0x00144000;
13958 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13959 /* 5714 always in PCIX mode */
13960 tp->dma_rwctrl |= 0x00148000;
13962 tp->dma_rwctrl |= 0x001b000f;
13966 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13967 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13968 tp->dma_rwctrl &= 0xfffffff0;
13970 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13971 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13972 /* Remove this if it causes problems for some boards. */
13973 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13975 /* On 5700/5701 chips, we need to set this bit.
13976 * Otherwise the chip will issue cacheline transactions
13977 * to streamable DMA memory with not all the byte
13978 * enables turned on. This is an error on several
13979 * RISC PCI controllers, in particular sparc64.
13981 * On 5703/5704 chips, this bit has been reassigned
13982 * a different meaning. In particular, it is used
13983 * on those chips to enable a PCI-X workaround.
13985 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13988 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13991 /* Unneeded, already done by tg3_get_invariants. */
13992 tg3_switch_clocks(tp);
13995 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13996 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13999 /* It is best to perform DMA test with maximum write burst size
14000 * to expose the 5700/5701 write DMA bug.
14002 saved_dma_rwctrl = tp->dma_rwctrl;
14003 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14004 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14009 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14012 /* Send the buffer to the chip. */
14013 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14015 dev_err(&tp->pdev->dev,
14016 "%s: Buffer write failed. err = %d\n",
14022 /* validate data reached card RAM correctly. */
14023 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14025 tg3_read_mem(tp, 0x2100 + (i*4), &val);
14026 if (le32_to_cpu(val) != p[i]) {
14027 dev_err(&tp->pdev->dev,
14028 "%s: Buffer corrupted on device! "
14029 "(%d != %d)\n", __func__, val, i);
14030 /* ret = -ENODEV here? */
14035 /* Now read it back. */
14036 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14038 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
14039 "err = %d\n", __func__, ret);
14044 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14048 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14049 DMA_RWCTRL_WRITE_BNDRY_16) {
14050 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14051 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14052 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14055 dev_err(&tp->pdev->dev,
14056 "%s: Buffer corrupted on read back! "
14057 "(%d != %d)\n", __func__, p[i], i);
14063 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14069 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14070 DMA_RWCTRL_WRITE_BNDRY_16) {
14071 static struct pci_device_id dma_wait_state_chipsets[] = {
14072 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14073 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14077 /* DMA test passed without adjusting DMA boundary,
14078 * now look for chipsets that are known to expose the
14079 * DMA bug without failing the test.
14081 if (pci_dev_present(dma_wait_state_chipsets)) {
14082 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14083 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14085 /* Safe to use the calculated DMA boundary. */
14086 tp->dma_rwctrl = saved_dma_rwctrl;
14089 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14093 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14098 static void __devinit tg3_init_link_config(struct tg3 *tp)
14100 tp->link_config.advertising =
14101 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14102 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14103 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14104 ADVERTISED_Autoneg | ADVERTISED_MII);
14105 tp->link_config.speed = SPEED_INVALID;
14106 tp->link_config.duplex = DUPLEX_INVALID;
14107 tp->link_config.autoneg = AUTONEG_ENABLE;
14108 tp->link_config.active_speed = SPEED_INVALID;
14109 tp->link_config.active_duplex = DUPLEX_INVALID;
14110 tp->link_config.phy_is_low_power = 0;
14111 tp->link_config.orig_speed = SPEED_INVALID;
14112 tp->link_config.orig_duplex = DUPLEX_INVALID;
14113 tp->link_config.orig_autoneg = AUTONEG_INVALID;
14116 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14118 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
14119 tp->bufmgr_config.mbuf_read_dma_low_water =
14120 DEFAULT_MB_RDMA_LOW_WATER_5705;
14121 tp->bufmgr_config.mbuf_mac_rx_low_water =
14122 DEFAULT_MB_MACRX_LOW_WATER_57765;
14123 tp->bufmgr_config.mbuf_high_water =
14124 DEFAULT_MB_HIGH_WATER_57765;
14126 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14127 DEFAULT_MB_RDMA_LOW_WATER_5705;
14128 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14129 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14130 tp->bufmgr_config.mbuf_high_water_jumbo =
14131 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14132 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14133 tp->bufmgr_config.mbuf_read_dma_low_water =
14134 DEFAULT_MB_RDMA_LOW_WATER_5705;
14135 tp->bufmgr_config.mbuf_mac_rx_low_water =
14136 DEFAULT_MB_MACRX_LOW_WATER_5705;
14137 tp->bufmgr_config.mbuf_high_water =
14138 DEFAULT_MB_HIGH_WATER_5705;
14139 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14140 tp->bufmgr_config.mbuf_mac_rx_low_water =
14141 DEFAULT_MB_MACRX_LOW_WATER_5906;
14142 tp->bufmgr_config.mbuf_high_water =
14143 DEFAULT_MB_HIGH_WATER_5906;
14146 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14147 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14148 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14149 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14150 tp->bufmgr_config.mbuf_high_water_jumbo =
14151 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14153 tp->bufmgr_config.mbuf_read_dma_low_water =
14154 DEFAULT_MB_RDMA_LOW_WATER;
14155 tp->bufmgr_config.mbuf_mac_rx_low_water =
14156 DEFAULT_MB_MACRX_LOW_WATER;
14157 tp->bufmgr_config.mbuf_high_water =
14158 DEFAULT_MB_HIGH_WATER;
14160 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14161 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14162 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14163 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14164 tp->bufmgr_config.mbuf_high_water_jumbo =
14165 DEFAULT_MB_HIGH_WATER_JUMBO;
14168 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14169 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14172 static char * __devinit tg3_phy_string(struct tg3 *tp)
14174 switch (tp->phy_id & TG3_PHY_ID_MASK) {
14175 case TG3_PHY_ID_BCM5400: return "5400";
14176 case TG3_PHY_ID_BCM5401: return "5401";
14177 case TG3_PHY_ID_BCM5411: return "5411";
14178 case TG3_PHY_ID_BCM5701: return "5701";
14179 case TG3_PHY_ID_BCM5703: return "5703";
14180 case TG3_PHY_ID_BCM5704: return "5704";
14181 case TG3_PHY_ID_BCM5705: return "5705";
14182 case TG3_PHY_ID_BCM5750: return "5750";
14183 case TG3_PHY_ID_BCM5752: return "5752";
14184 case TG3_PHY_ID_BCM5714: return "5714";
14185 case TG3_PHY_ID_BCM5780: return "5780";
14186 case TG3_PHY_ID_BCM5755: return "5755";
14187 case TG3_PHY_ID_BCM5787: return "5787";
14188 case TG3_PHY_ID_BCM5784: return "5784";
14189 case TG3_PHY_ID_BCM5756: return "5722/5756";
14190 case TG3_PHY_ID_BCM5906: return "5906";
14191 case TG3_PHY_ID_BCM5761: return "5761";
14192 case TG3_PHY_ID_BCM5718C: return "5718C";
14193 case TG3_PHY_ID_BCM5718S: return "5718S";
14194 case TG3_PHY_ID_BCM57765: return "57765";
14195 case TG3_PHY_ID_BCM5719C: return "5719C";
14196 case TG3_PHY_ID_BCM8002: return "8002/serdes";
14197 case 0: return "serdes";
14198 default: return "unknown";
14202 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14204 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14205 strcpy(str, "PCI Express");
14207 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14208 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14210 strcpy(str, "PCIX:");
14212 if ((clock_ctrl == 7) ||
14213 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14214 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14215 strcat(str, "133MHz");
14216 else if (clock_ctrl == 0)
14217 strcat(str, "33MHz");
14218 else if (clock_ctrl == 2)
14219 strcat(str, "50MHz");
14220 else if (clock_ctrl == 4)
14221 strcat(str, "66MHz");
14222 else if (clock_ctrl == 6)
14223 strcat(str, "100MHz");
14225 strcpy(str, "PCI:");
14226 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14227 strcat(str, "66MHz");
14229 strcat(str, "33MHz");
14231 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14232 strcat(str, ":32-bit");
14234 strcat(str, ":64-bit");
14238 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14240 struct pci_dev *peer;
14241 unsigned int func, devnr = tp->pdev->devfn & ~7;
14243 for (func = 0; func < 8; func++) {
14244 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14245 if (peer && peer != tp->pdev)
14249 /* 5704 can be configured in single-port mode, set peer to
14250 * tp->pdev in that case.
14258 * We don't need to keep the refcount elevated; there's no way
14259 * to remove one half of this device without removing the other
14266 static void __devinit tg3_init_coal(struct tg3 *tp)
14268 struct ethtool_coalesce *ec = &tp->coal;
14270 memset(ec, 0, sizeof(*ec));
14271 ec->cmd = ETHTOOL_GCOALESCE;
14272 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14273 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14274 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14275 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14276 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14277 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14278 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14279 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14280 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14282 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14283 HOSTCC_MODE_CLRTICK_TXBD)) {
14284 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14285 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14286 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14287 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14290 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14291 ec->rx_coalesce_usecs_irq = 0;
14292 ec->tx_coalesce_usecs_irq = 0;
14293 ec->stats_block_coalesce_usecs = 0;
14297 static const struct net_device_ops tg3_netdev_ops = {
14298 .ndo_open = tg3_open,
14299 .ndo_stop = tg3_close,
14300 .ndo_start_xmit = tg3_start_xmit,
14301 .ndo_get_stats64 = tg3_get_stats64,
14302 .ndo_validate_addr = eth_validate_addr,
14303 .ndo_set_multicast_list = tg3_set_rx_mode,
14304 .ndo_set_mac_address = tg3_set_mac_addr,
14305 .ndo_do_ioctl = tg3_ioctl,
14306 .ndo_tx_timeout = tg3_tx_timeout,
14307 .ndo_change_mtu = tg3_change_mtu,
14308 #if TG3_VLAN_TAG_USED
14309 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14311 #ifdef CONFIG_NET_POLL_CONTROLLER
14312 .ndo_poll_controller = tg3_poll_controller,
14316 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14317 .ndo_open = tg3_open,
14318 .ndo_stop = tg3_close,
14319 .ndo_start_xmit = tg3_start_xmit_dma_bug,
14320 .ndo_get_stats64 = tg3_get_stats64,
14321 .ndo_validate_addr = eth_validate_addr,
14322 .ndo_set_multicast_list = tg3_set_rx_mode,
14323 .ndo_set_mac_address = tg3_set_mac_addr,
14324 .ndo_do_ioctl = tg3_ioctl,
14325 .ndo_tx_timeout = tg3_tx_timeout,
14326 .ndo_change_mtu = tg3_change_mtu,
14327 #if TG3_VLAN_TAG_USED
14328 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14330 #ifdef CONFIG_NET_POLL_CONTROLLER
14331 .ndo_poll_controller = tg3_poll_controller,
14335 static int __devinit tg3_init_one(struct pci_dev *pdev,
14336 const struct pci_device_id *ent)
14338 struct net_device *dev;
14340 int i, err, pm_cap;
14341 u32 sndmbx, rcvmbx, intmbx;
14343 u64 dma_mask, persist_dma_mask;
14345 printk_once(KERN_INFO "%s\n", version);
14347 err = pci_enable_device(pdev);
14349 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
14353 err = pci_request_regions(pdev, DRV_MODULE_NAME);
14355 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
14356 goto err_out_disable_pdev;
14359 pci_set_master(pdev);
14361 /* Find power-management capability. */
14362 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14364 dev_err(&pdev->dev,
14365 "Cannot find Power Management capability, aborting\n");
14367 goto err_out_free_res;
14370 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14372 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
14374 goto err_out_free_res;
14377 SET_NETDEV_DEV(dev, &pdev->dev);
14379 #if TG3_VLAN_TAG_USED
14380 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14383 tp = netdev_priv(dev);
14386 tp->pm_cap = pm_cap;
14387 tp->rx_mode = TG3_DEF_RX_MODE;
14388 tp->tx_mode = TG3_DEF_TX_MODE;
14391 tp->msg_enable = tg3_debug;
14393 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14395 /* The word/byte swap controls here control register access byte
14396 * swapping. DMA data byte swapping is controlled in the GRC_MODE
14399 tp->misc_host_ctrl =
14400 MISC_HOST_CTRL_MASK_PCI_INT |
14401 MISC_HOST_CTRL_WORD_SWAP |
14402 MISC_HOST_CTRL_INDIR_ACCESS |
14403 MISC_HOST_CTRL_PCISTATE_RW;
14405 /* The NONFRM (non-frame) byte/word swap controls take effect
14406 * on descriptor entries, anything which isn't packet data.
14408 * The StrongARM chips on the board (one for tx, one for rx)
14409 * are running in big-endian mode.
14411 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14412 GRC_MODE_WSWAP_NONFRM_DATA);
14413 #ifdef __BIG_ENDIAN
14414 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14416 spin_lock_init(&tp->lock);
14417 spin_lock_init(&tp->indirect_lock);
14418 INIT_WORK(&tp->reset_task, tg3_reset_task);
14420 tp->regs = pci_ioremap_bar(pdev, BAR_0);
14422 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
14424 goto err_out_free_dev;
14427 tg3_init_link_config(tp);
14429 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14430 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14432 dev->ethtool_ops = &tg3_ethtool_ops;
14433 dev->watchdog_timeo = TG3_TX_TIMEOUT;
14434 dev->irq = pdev->irq;
14436 err = tg3_get_invariants(tp);
14438 dev_err(&pdev->dev,
14439 "Problem fetching invariants of chip, aborting\n");
14440 goto err_out_iounmap;
14443 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14444 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0 &&
14445 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
14446 dev->netdev_ops = &tg3_netdev_ops;
14448 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14451 /* The EPB bridge inside 5714, 5715, and 5780 and any
14452 * device behind the EPB cannot support DMA addresses > 40-bit.
14453 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14454 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14455 * do DMA address check in tg3_start_xmit().
14457 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14458 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14459 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14460 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14461 #ifdef CONFIG_HIGHMEM
14462 dma_mask = DMA_BIT_MASK(64);
14465 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14467 /* Configure DMA attributes. */
14468 if (dma_mask > DMA_BIT_MASK(32)) {
14469 err = pci_set_dma_mask(pdev, dma_mask);
14471 dev->features |= NETIF_F_HIGHDMA;
14472 err = pci_set_consistent_dma_mask(pdev,
14475 dev_err(&pdev->dev, "Unable to obtain 64 bit "
14476 "DMA for consistent allocations\n");
14477 goto err_out_iounmap;
14481 if (err || dma_mask == DMA_BIT_MASK(32)) {
14482 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14484 dev_err(&pdev->dev,
14485 "No usable DMA configuration, aborting\n");
14486 goto err_out_iounmap;
14490 tg3_init_bufmgr_config(tp);
14492 /* Selectively allow TSO based on operating conditions */
14493 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14494 (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14495 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14497 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14498 tp->fw_needed = NULL;
14501 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14502 tp->fw_needed = FIRMWARE_TG3;
14504 /* TSO is on by default on chips that support hardware TSO.
14505 * Firmware TSO on older chips gives lower performance, so it
14506 * is off by default, but can be enabled using ethtool.
14508 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14509 (dev->features & NETIF_F_IP_CSUM)) {
14510 dev->features |= NETIF_F_TSO;
14511 vlan_features_add(dev, NETIF_F_TSO);
14513 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14514 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14515 if (dev->features & NETIF_F_IPV6_CSUM) {
14516 dev->features |= NETIF_F_TSO6;
14517 vlan_features_add(dev, NETIF_F_TSO6);
14519 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14520 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14521 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14522 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14523 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14524 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
14525 dev->features |= NETIF_F_TSO_ECN;
14526 vlan_features_add(dev, NETIF_F_TSO_ECN);
14530 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14531 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14532 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14533 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14534 tp->rx_pending = 63;
14537 err = tg3_get_device_address(tp);
14539 dev_err(&pdev->dev,
14540 "Could not obtain valid ethernet address, aborting\n");
14541 goto err_out_iounmap;
14544 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14545 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14546 if (!tp->aperegs) {
14547 dev_err(&pdev->dev,
14548 "Cannot map APE registers, aborting\n");
14550 goto err_out_iounmap;
14553 tg3_ape_lock_init(tp);
14555 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14556 tg3_read_dash_ver(tp);
14560 * Reset chip in case UNDI or EFI driver did not shutdown
14561 * DMA self test will enable WDMAC and we'll see (spurious)
14562 * pending DMA on the PCI bus at that point.
14564 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14565 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14566 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14567 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14570 err = tg3_test_dma(tp);
14572 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
14573 goto err_out_apeunmap;
14576 /* flow control autonegotiation is default behavior */
14577 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14578 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14580 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14581 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14582 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14583 for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14584 struct tg3_napi *tnapi = &tp->napi[i];
14587 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14589 tnapi->int_mbox = intmbx;
14595 tnapi->consmbox = rcvmbx;
14596 tnapi->prodmbox = sndmbx;
14599 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14600 netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14602 tnapi->coal_now = HOSTCC_MODE_NOW;
14603 netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14606 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14610 * If we support MSIX, we'll be using RSS. If we're using
14611 * RSS, the first vector only handles link interrupts and the
14612 * remaining vectors handle rx and tx interrupts. Reuse the
14613 * mailbox values for the next iteration. The values we setup
14614 * above are still useful for the single vectored mode.
14629 pci_set_drvdata(pdev, dev);
14631 err = register_netdev(dev);
14633 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
14634 goto err_out_apeunmap;
14637 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14638 tp->board_part_number,
14639 tp->pci_chip_rev_id,
14640 tg3_bus_string(tp, str),
14643 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14644 struct phy_device *phydev;
14645 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14647 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14648 phydev->drv->name, dev_name(&phydev->dev));
14650 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
14651 "(WireSpeed[%d])\n", tg3_phy_string(tp),
14652 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14653 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14654 "10/100/1000Base-T")),
14655 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14657 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14658 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14659 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14660 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14661 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14662 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14663 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14665 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
14666 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
14672 iounmap(tp->aperegs);
14673 tp->aperegs = NULL;
14686 pci_release_regions(pdev);
14688 err_out_disable_pdev:
14689 pci_disable_device(pdev);
14690 pci_set_drvdata(pdev, NULL);
14694 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14696 struct net_device *dev = pci_get_drvdata(pdev);
14699 struct tg3 *tp = netdev_priv(dev);
14702 release_firmware(tp->fw);
14704 flush_scheduled_work();
14706 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14711 unregister_netdev(dev);
14713 iounmap(tp->aperegs);
14714 tp->aperegs = NULL;
14721 pci_release_regions(pdev);
14722 pci_disable_device(pdev);
14723 pci_set_drvdata(pdev, NULL);
14727 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14729 struct net_device *dev = pci_get_drvdata(pdev);
14730 struct tg3 *tp = netdev_priv(dev);
14731 pci_power_t target_state;
14734 /* PCI register 4 needs to be saved whether netif_running() or not.
14735 * MSI address and data need to be saved if using MSI and
14738 pci_save_state(pdev);
14740 if (!netif_running(dev))
14743 flush_scheduled_work();
14745 tg3_netif_stop(tp);
14747 del_timer_sync(&tp->timer);
14749 tg3_full_lock(tp, 1);
14750 tg3_disable_ints(tp);
14751 tg3_full_unlock(tp);
14753 netif_device_detach(dev);
14755 tg3_full_lock(tp, 0);
14756 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14757 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14758 tg3_full_unlock(tp);
14760 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14762 err = tg3_set_power_state(tp, target_state);
14766 tg3_full_lock(tp, 0);
14768 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14769 err2 = tg3_restart_hw(tp, 1);
14773 tp->timer.expires = jiffies + tp->timer_offset;
14774 add_timer(&tp->timer);
14776 netif_device_attach(dev);
14777 tg3_netif_start(tp);
14780 tg3_full_unlock(tp);
14789 static int tg3_resume(struct pci_dev *pdev)
14791 struct net_device *dev = pci_get_drvdata(pdev);
14792 struct tg3 *tp = netdev_priv(dev);
14795 pci_restore_state(tp->pdev);
14797 if (!netif_running(dev))
14800 err = tg3_set_power_state(tp, PCI_D0);
14804 netif_device_attach(dev);
14806 tg3_full_lock(tp, 0);
14808 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14809 err = tg3_restart_hw(tp, 1);
14813 tp->timer.expires = jiffies + tp->timer_offset;
14814 add_timer(&tp->timer);
14816 tg3_netif_start(tp);
14819 tg3_full_unlock(tp);
14827 static struct pci_driver tg3_driver = {
14828 .name = DRV_MODULE_NAME,
14829 .id_table = tg3_pci_tbl,
14830 .probe = tg3_init_one,
14831 .remove = __devexit_p(tg3_remove_one),
14832 .suspend = tg3_suspend,
14833 .resume = tg3_resume
14836 static int __init tg3_init(void)
14838 return pci_register_driver(&tg3_driver);
14841 static void __exit tg3_cleanup(void)
14843 pci_unregister_driver(&tg3_driver);
14846 module_init(tg3_init);
14847 module_exit(tg3_cleanup);