drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2010 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/stringify.h>
  22 #include <linux/kernel.h>
  23 #include <linux/types.h>
  24 #include <linux/compiler.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/in.h>
  28 #include <linux/init.h>
  29 #include <linux/ioport.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/ethtool.h>
  35 #include <linux/mii.h>
  36 #include <linux/phy.h>
  37 #include <linux/brcmphy.h>
  38 #include <linux/if_vlan.h>
  39 #include <linux/ip.h>
  40 #include <linux/tcp.h>
  41 #include <linux/workqueue.h>
  42 #include <linux/prefetch.h>
  43 #include <linux/dma-mapping.h>
  44 #include <linux/firmware.h>
  45
  46 #include <net/checksum.h>
  47 #include <net/ip.h>
  48
  49 #include <asm/system.h>
  50 #include <asm/io.h>
  51 #include <asm/byteorder.h>
  52 #include <asm/uaccess.h>
  53
  54 #ifdef CONFIG_SPARC
  55 #include <asm/idprom.h>
  56 #include <asm/prom.h>
  57 #endif
  58
  59 #define BAR_0   0
  60 #define BAR_2   2
  61
  62 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  63 #define TG3_VLAN_TAG_USED 1
  64 #else
  65 #define TG3_VLAN_TAG_USED 0
  66 #endif
  67
  68 #include "tg3.h"
  69
  70 #define DRV_MODULE_NAME         "tg3"
  71 #define TG3_MAJ_NUM                     3
  72 #define TG3_MIN_NUM                     113
  73 #define DRV_MODULE_VERSION      \
  74         __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
  75 #define DRV_MODULE_RELDATE      "August 2, 2010"
  76
  77 #define TG3_DEF_MAC_MODE        0
  78 #define TG3_DEF_RX_MODE         0
  79 #define TG3_DEF_TX_MODE         0
  80 #define TG3_DEF_MSG_ENABLE        \
  81         (NETIF_MSG_DRV          | \
  82          NETIF_MSG_PROBE        | \
  83          NETIF_MSG_LINK         | \
  84          NETIF_MSG_TIMER        | \
  85          NETIF_MSG_IFDOWN       | \
  86          NETIF_MSG_IFUP         | \
  87          NETIF_MSG_RX_ERR       | \
  88          NETIF_MSG_TX_ERR)
  89
  90 /* length of time before we decide the hardware is borked,
  91  * and dev->tx_timeout() should be called to fix the problem
  92  */
  93 #define TG3_TX_TIMEOUT                  (5 * HZ)
  94
  95 /* hardware minimum and maximum for a single frame's data payload */
  96 #define TG3_MIN_MTU                     60
  97 #define TG3_MAX_MTU(tp) \
  98         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  99
 100 /* These numbers seem to be hard coded in the NIC firmware somehow.
 101  * You can't change the ring sizes, but you can change where you place
 102  * them in the NIC onboard memory.
 103  */
 104 #define TG3_RX_RING_SIZE                512
 105 #define TG3_DEF_RX_RING_PENDING         200
 106 #define TG3_RX_JUMBO_RING_SIZE          256
 107 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 108 #define TG3_RSS_INDIR_TBL_SIZE          128
 109
 110 /* Do not place this n-ring entries value into the tp struct itself,
 111  * we really want to expose these constants to GCC so that modulo et
 112  * al.  operations are done with shifts and masks instead of with
 113  * hw multiply/modulo instructions.  Another solution would be to
 114  * replace things like '% foo' with '& (foo - 1)'.
 115  */
 116 #define TG3_RX_RCB_RING_SIZE(tp)        \
 117         (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
 118           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
 119
 120 #define TG3_TX_RING_SIZE                512
 121 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 122
 123 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 124                                  TG3_RX_RING_SIZE)
 125 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
 126                                  TG3_RX_JUMBO_RING_SIZE)
 127 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 128                                  TG3_RX_RCB_RING_SIZE(tp))
 129 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 130                                  TG3_TX_RING_SIZE)
 131 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 132
 133 #define TG3_RX_DMA_ALIGN                16
 134 #define TG3_RX_HEADROOM                 ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
 135
 136 #define TG3_DMA_BYTE_ENAB               64
 137
 138 #define TG3_RX_STD_DMA_SZ               1536
 139 #define TG3_RX_JMB_DMA_SZ               9046
 140
 141 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 142
 143 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 144 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 145
 146 #define TG3_RX_STD_BUFF_RING_SIZE \
 147         (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
 148
 149 #define TG3_RX_JMB_BUFF_RING_SIZE \
 150         (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
 151
 152 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
 153  * that are at least dword aligned when used in PCIX mode.  The driver
 154  * works around this bug by double copying the packet.  This workaround
 155  * is built into the normal double copy length check for efficiency.
 156  *
 157  * However, the double copy is only necessary on those architectures
 158  * where unaligned memory accesses are inefficient.  For those architectures
 159  * where unaligned memory accesses incur little penalty, we can reintegrate
 160  * the 5701 in the normal rx path.  Doing so saves a device structure
 161  * dereference by hardcoding the double copy threshold in place.
 162  */
 163 #define TG3_RX_COPY_THRESHOLD           256
 164 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
 165         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
 166 #else
 167         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
 168 #endif
 169
 170 /* minimum number of free TX descriptors required to wake up TX process */
 171 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 172
 173 #define TG3_RAW_IP_ALIGN 2
 174
 175 /* number of ETHTOOL_GSTATS u64's */
 176 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 177
 178 #define TG3_NUM_TEST            6
 179
 180 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
 181
 182 #define FIRMWARE_TG3            "tigon/tg3.bin"
 183 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 184 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 185
 186 static char version[] __devinitdata =
 187         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
 188
 189 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 190 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 191 MODULE_LICENSE("GPL");
 192 MODULE_VERSION(DRV_MODULE_VERSION);
 193 MODULE_FIRMWARE(FIRMWARE_TG3);
 194 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 195 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 196
 197 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 198 module_param(tg3_debug, int, 0);
 199 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 200
 201 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 255         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 256         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 257         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 258         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 259         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 260         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 261         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 262         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 263         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 264         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 265         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
 266         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
 267         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
 268         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
 269         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
 270         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
 271         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
 272         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
 273         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
 274         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
 275         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 276         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 277         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 278         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 279         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 280         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 281         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 282         {}
 283 };
 284
 285 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 286
 287 static const struct {
 288         const char string[ETH_GSTRING_LEN];
 289 } ethtool_stats_keys[TG3_NUM_STATS] = {
 290         { "rx_octets" },
 291         { "rx_fragments" },
 292         { "rx_ucast_packets" },
 293         { "rx_mcast_packets" },
 294         { "rx_bcast_packets" },
 295         { "rx_fcs_errors" },
 296         { "rx_align_errors" },
 297         { "rx_xon_pause_rcvd" },
 298         { "rx_xoff_pause_rcvd" },
 299         { "rx_mac_ctrl_rcvd" },
 300         { "rx_xoff_entered" },
 301         { "rx_frame_too_long_errors" },
 302         { "rx_jabbers" },
 303         { "rx_undersize_packets" },
 304         { "rx_in_length_errors" },
 305         { "rx_out_length_errors" },
 306         { "rx_64_or_less_octet_packets" },
 307         { "rx_65_to_127_octet_packets" },
 308         { "rx_128_to_255_octet_packets" },
 309         { "rx_256_to_511_octet_packets" },
 310         { "rx_512_to_1023_octet_packets" },
 311         { "rx_1024_to_1522_octet_packets" },
 312         { "rx_1523_to_2047_octet_packets" },
 313         { "rx_2048_to_4095_octet_packets" },
 314         { "rx_4096_to_8191_octet_packets" },
 315         { "rx_8192_to_9022_octet_packets" },
 316
 317         { "tx_octets" },
 318         { "tx_collisions" },
 319
 320         { "tx_xon_sent" },
 321         { "tx_xoff_sent" },
 322         { "tx_flow_control" },
 323         { "tx_mac_errors" },
 324         { "tx_single_collisions" },
 325         { "tx_mult_collisions" },
 326         { "tx_deferred" },
 327         { "tx_excessive_collisions" },
 328         { "tx_late_collisions" },
 329         { "tx_collide_2times" },
 330         { "tx_collide_3times" },
 331         { "tx_collide_4times" },
 332         { "tx_collide_5times" },
 333         { "tx_collide_6times" },
 334         { "tx_collide_7times" },
 335         { "tx_collide_8times" },
 336         { "tx_collide_9times" },
 337         { "tx_collide_10times" },
 338         { "tx_collide_11times" },
 339         { "tx_collide_12times" },
 340         { "tx_collide_13times" },
 341         { "tx_collide_14times" },
 342         { "tx_collide_15times" },
 343         { "tx_ucast_packets" },
 344         { "tx_mcast_packets" },
 345         { "tx_bcast_packets" },
 346         { "tx_carrier_sense_errors" },
 347         { "tx_discards" },
 348         { "tx_errors" },
 349
 350         { "dma_writeq_full" },
 351         { "dma_write_prioq_full" },
 352         { "rxbds_empty" },
 353         { "rx_discards" },
 354         { "rx_errors" },
 355         { "rx_threshold_hit" },
 356
 357         { "dma_readq_full" },
 358         { "dma_read_prioq_full" },
 359         { "tx_comp_queue_full" },
 360
 361         { "ring_set_send_prod_index" },
 362         { "ring_status_update" },
 363         { "nic_irqs" },
 364         { "nic_avoided_irqs" },
 365         { "nic_tx_threshold_hit" }
 366 };
 367
 368 static const struct {
 369         const char string[ETH_GSTRING_LEN];
 370 } ethtool_test_keys[TG3_NUM_TEST] = {
 371         { "nvram test     (online) " },
 372         { "link test      (online) " },
 373         { "register test  (offline)" },
 374         { "memory test    (offline)" },
 375         { "loopback test  (offline)" },
 376         { "interrupt test (offline)" },
 377 };
 378
 379 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 380 {
 381         writel(val, tp->regs + off);
 382 }
 383
 384 static u32 tg3_read32(struct tg3 *tp, u32 off)
 385 {
 386         return readl(tp->regs + off);
 387 }
 388
 389 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 390 {
 391         writel(val, tp->aperegs + off);
 392 }
 393
 394 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 395 {
 396         return readl(tp->aperegs + off);
 397 }
 398
 399 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 400 {
 401         unsigned long flags;
 402
 403         spin_lock_irqsave(&tp->indirect_lock, flags);
 404         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 405         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 406         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 407 }
 408
 409 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 410 {
 411         writel(val, tp->regs + off);
 412         readl(tp->regs + off);
 413 }
 414
 415 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 416 {
 417         unsigned long flags;
 418         u32 val;
 419
 420         spin_lock_irqsave(&tp->indirect_lock, flags);
 421         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 422         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 423         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 424         return val;
 425 }
 426
 427 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 428 {
 429         unsigned long flags;
 430
 431         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 432                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 433                                        TG3_64BIT_REG_LOW, val);
 434                 return;
 435         }
 436         if (off == TG3_RX_STD_PROD_IDX_REG) {
 437                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 438                                        TG3_64BIT_REG_LOW, val);
 439                 return;
 440         }
 441
 442         spin_lock_irqsave(&tp->indirect_lock, flags);
 443         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 444         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 445         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 446
 447         /* In indirect mode when disabling interrupts, we also need
 448          * to clear the interrupt bit in the GRC local ctrl register.
 449          */
 450         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 451             (val == 0x1)) {
 452                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 453                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 454         }
 455 }
 456
 457 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 458 {
 459         unsigned long flags;
 460         u32 val;
 461
 462         spin_lock_irqsave(&tp->indirect_lock, flags);
 463         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 464         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 465         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 466         return val;
 467 }
 468
 469 /* usec_wait specifies the wait time in usec when writing to certain registers
 470  * where it is unsafe to read back the register without some delay.
 471  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 472  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 473  */
 474 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 475 {
 476         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 477             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 478                 /* Non-posted methods */
 479                 tp->write32(tp, off, val);
 480         else {
 481                 /* Posted method */
 482                 tg3_write32(tp, off, val);
 483                 if (usec_wait)
 484                         udelay(usec_wait);
 485                 tp->read32(tp, off);
 486         }
 487         /* Wait again after the read for the posted method to guarantee that
 488          * the wait time is met.
 489          */
 490         if (usec_wait)
 491                 udelay(usec_wait);
 492 }
 493
 494 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 495 {
 496         tp->write32_mbox(tp, off, val);
 497         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 498             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 499                 tp->read32_mbox(tp, off);
 500 }
 501
 502 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 503 {
 504         void __iomem *mbox = tp->regs + off;
 505         writel(val, mbox);
 506         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 507                 writel(val, mbox);
 508         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 509                 readl(mbox);
 510 }
 511
 512 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 513 {
 514         return readl(tp->regs + off + GRCMBOX_BASE);
 515 }
 516
 517 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 518 {
 519         writel(val, tp->regs + off + GRCMBOX_BASE);
 520 }
 521
 522 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
 523 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 524 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
 525 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
 526 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
 527
 528 #define tw32(reg, val)                  tp->write32(tp, reg, val)
 529 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
 530 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
 531 #define tr32(reg)                       tp->read32(tp, reg)
 532
 533 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 534 {
 535         unsigned long flags;
 536
 537         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 538             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 539                 return;
 540
 541         spin_lock_irqsave(&tp->indirect_lock, flags);
 542         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 543                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 544                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 545
 546                 /* Always leave this as zero. */
 547                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 548         } else {
 549                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 550                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 551
 552                 /* Always leave this as zero. */
 553                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 554         }
 555         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 556 }
 557
 558 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 559 {
 560         unsigned long flags;
 561
 562         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 563             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 564                 *val = 0;
 565                 return;
 566         }
 567
 568         spin_lock_irqsave(&tp->indirect_lock, flags);
 569         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 570                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 571                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 572
 573                 /* Always leave this as zero. */
 574                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 575         } else {
 576                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 577                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 578
 579                 /* Always leave this as zero. */
 580                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 581         }
 582         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 583 }
 584
 585 static void tg3_ape_lock_init(struct tg3 *tp)
 586 {
 587         int i;
 588         u32 regbase;
 589
 590         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 591                 regbase = TG3_APE_LOCK_GRANT;
 592         else
 593                 regbase = TG3_APE_PER_LOCK_GRANT;
 594
 595         /* Make sure the driver hasn't any stale locks. */
 596         for (i = 0; i < 8; i++)
 597                 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
 598 }
 599
 600 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 601 {
 602         int i, off;
 603         int ret = 0;
 604         u32 status, req, gnt;
 605
 606         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 607                 return 0;
 608
 609         switch (locknum) {
 610         case TG3_APE_LOCK_GRC:
 611         case TG3_APE_LOCK_MEM:
 612                 break;
 613         default:
 614                 return -EINVAL;
 615         }
 616
 617         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
 618                 req = TG3_APE_LOCK_REQ;
 619                 gnt = TG3_APE_LOCK_GRANT;
 620         } else {
 621                 req = TG3_APE_PER_LOCK_REQ;
 622                 gnt = TG3_APE_PER_LOCK_GRANT;
 623         }
 624
 625         off = 4 * locknum;
 626
 627         tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
 628
 629         /* Wait for up to 1 millisecond to acquire lock. */
 630         for (i = 0; i < 100; i++) {
 631                 status = tg3_ape_read32(tp, gnt + off);
 632                 if (status == APE_LOCK_GRANT_DRIVER)
 633                         break;
 634                 udelay(10);
 635         }
 636
 637         if (status != APE_LOCK_GRANT_DRIVER) {
 638                 /* Revoke the lock request. */
 639                 tg3_ape_write32(tp, gnt + off,
 640                                 APE_LOCK_GRANT_DRIVER);
 641
 642                 ret = -EBUSY;
 643         }
 644
 645         return ret;
 646 }
 647
 648 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 649 {
 650         u32 gnt;
 651
 652         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 653                 return;
 654
 655         switch (locknum) {
 656         case TG3_APE_LOCK_GRC:
 657         case TG3_APE_LOCK_MEM:
 658                 break;
 659         default:
 660                 return;
 661         }
 662
 663         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 664                 gnt = TG3_APE_LOCK_GRANT;
 665         else
 666                 gnt = TG3_APE_PER_LOCK_GRANT;
 667
 668         tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
 669 }
 670
 671 static void tg3_disable_ints(struct tg3 *tp)
 672 {
 673         int i;
 674
 675         tw32(TG3PCI_MISC_HOST_CTRL,
 676              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 677         for (i = 0; i < tp->irq_max; i++)
 678                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 679 }
 680
 681 static void tg3_enable_ints(struct tg3 *tp)
 682 {
 683         int i;
 684
 685         tp->irq_sync = 0;
 686         wmb();
 687
 688         tw32(TG3PCI_MISC_HOST_CTRL,
 689              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 690
 691         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
 692         for (i = 0; i < tp->irq_cnt; i++) {
 693                 struct tg3_napi *tnapi = &tp->napi[i];
 694
 695                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 696                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 697                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 698
 699                 tp->coal_now |= tnapi->coal_now;
 700         }
 701
 702         /* Force an initial interrupt */
 703         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 704             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 705                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 706         else
 707                 tw32(HOSTCC_MODE, tp->coal_now);
 708
 709         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
 710 }
 711
 712 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 713 {
 714         struct tg3 *tp = tnapi->tp;
 715         struct tg3_hw_status *sblk = tnapi->hw_status;
 716         unsigned int work_exists = 0;
 717
 718         /* check for phy events */
 719         if (!(tp->tg3_flags &
 720               (TG3_FLAG_USE_LINKCHG_REG |
 721                TG3_FLAG_POLL_SERDES))) {
 722                 if (sblk->status & SD_STATUS_LINK_CHG)
 723                         work_exists = 1;
 724         }
 725         /* check for RX/TX work to do */
 726         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 727             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
 728                 work_exists = 1;
 729
 730         return work_exists;
 731 }
 732
 733 /* tg3_int_reenable
 734  *  similar to tg3_enable_ints, but it accurately determines whether there
 735  *  is new work pending and can return without flushing the PIO write
 736  *  which reenables interrupts
 737  */
 738 static void tg3_int_reenable(struct tg3_napi *tnapi)
 739 {
 740         struct tg3 *tp = tnapi->tp;
 741
 742         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 743         mmiowb();
 744
 745         /* When doing tagged status, this work check is unnecessary.
 746          * The last_tag we write above tells the chip which piece of
 747          * work we've completed.
 748          */
 749         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 750             tg3_has_work(tnapi))
 751                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 752                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 753 }
 754
 755 static void tg3_switch_clocks(struct tg3 *tp)
 756 {
 757         u32 clock_ctrl;
 758         u32 orig_clock_ctrl;
 759
 760         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 761             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 762                 return;
 763
 764         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 765
 766         orig_clock_ctrl = clock_ctrl;
 767         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 768                        CLOCK_CTRL_CLKRUN_OENABLE |
 769                        0x1f);
 770         tp->pci_clock_ctrl = clock_ctrl;
 771
 772         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 773                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 774                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 775                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 776                 }
 777         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 778                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 779                             clock_ctrl |
 780                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 781                             40);
 782                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 783                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 784                             40);
 785         }
 786         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 787 }
 788
 789 #define PHY_BUSY_LOOPS  5000
 790
 791 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 792 {
 793         u32 frame_val;
 794         unsigned int loops;
 795         int ret;
 796
 797         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 798                 tw32_f(MAC_MI_MODE,
 799                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 800                 udelay(80);
 801         }
 802
 803         *val = 0x0;
 804
 805         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 806                       MI_COM_PHY_ADDR_MASK);
 807         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 808                       MI_COM_REG_ADDR_MASK);
 809         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 810
 811         tw32_f(MAC_MI_COM, frame_val);
 812
 813         loops = PHY_BUSY_LOOPS;
 814         while (loops != 0) {
 815                 udelay(10);
 816                 frame_val = tr32(MAC_MI_COM);
 817
 818                 if ((frame_val & MI_COM_BUSY) == 0) {
 819                         udelay(5);
 820                         frame_val = tr32(MAC_MI_COM);
 821                         break;
 822                 }
 823                 loops -= 1;
 824         }
 825
 826         ret = -EBUSY;
 827         if (loops != 0) {
 828                 *val = frame_val & MI_COM_DATA_MASK;
 829                 ret = 0;
 830         }
 831
 832         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 833                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 834                 udelay(80);
 835         }
 836
 837         return ret;
 838 }
 839
 840 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 841 {
 842         u32 frame_val;
 843         unsigned int loops;
 844         int ret;
 845
 846         if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
 847             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 848                 return 0;
 849
 850         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 851                 tw32_f(MAC_MI_MODE,
 852                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 853                 udelay(80);
 854         }
 855
 856         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 857                       MI_COM_PHY_ADDR_MASK);
 858         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 859                       MI_COM_REG_ADDR_MASK);
 860         frame_val |= (val & MI_COM_DATA_MASK);
 861         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 862
 863         tw32_f(MAC_MI_COM, frame_val);
 864
 865         loops = PHY_BUSY_LOOPS;
 866         while (loops != 0) {
 867                 udelay(10);
 868                 frame_val = tr32(MAC_MI_COM);
 869                 if ((frame_val & MI_COM_BUSY) == 0) {
 870                         udelay(5);
 871                         frame_val = tr32(MAC_MI_COM);
 872                         break;
 873                 }
 874                 loops -= 1;
 875         }
 876
 877         ret = -EBUSY;
 878         if (loops != 0)
 879                 ret = 0;
 880
 881         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 882                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 883                 udelay(80);
 884         }
 885
 886         return ret;
 887 }
 888
 889 static int tg3_bmcr_reset(struct tg3 *tp)
 890 {
 891         u32 phy_control;
 892         int limit, err;
 893
 894         /* OK, reset it, and poll the BMCR_RESET bit until it
 895          * clears or we time out.
 896          */
 897         phy_control = BMCR_RESET;
 898         err = tg3_writephy(tp, MII_BMCR, phy_control);
 899         if (err != 0)
 900                 return -EBUSY;
 901
 902         limit = 5000;
 903         while (limit--) {
 904                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 905                 if (err != 0)
 906                         return -EBUSY;
 907
 908                 if ((phy_control & BMCR_RESET) == 0) {
 909                         udelay(40);
 910                         break;
 911                 }
 912                 udelay(10);
 913         }
 914         if (limit < 0)
 915                 return -EBUSY;
 916
 917         return 0;
 918 }
 919
 920 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 921 {
 922         struct tg3 *tp = bp->priv;
 923         u32 val;
 924
 925         spin_lock_bh(&tp->lock);
 926
 927         if (tg3_readphy(tp, reg, &val))
 928                 val = -EIO;
 929
 930         spin_unlock_bh(&tp->lock);
 931
 932         return val;
 933 }
 934
 935 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 936 {
 937         struct tg3 *tp = bp->priv;
 938         u32 ret = 0;
 939
 940         spin_lock_bh(&tp->lock);
 941
 942         if (tg3_writephy(tp, reg, val))
 943                 ret = -EIO;
 944
 945         spin_unlock_bh(&tp->lock);
 946
 947         return ret;
 948 }
 949
 950 static int tg3_mdio_reset(struct mii_bus *bp)
 951 {
 952         return 0;
 953 }
 954
 955 static void tg3_mdio_config_5785(struct tg3 *tp)
 956 {
 957         u32 val;
 958         struct phy_device *phydev;
 959
 960         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
 961         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 962         case PHY_ID_BCM50610:
 963         case PHY_ID_BCM50610M:
 964                 val = MAC_PHYCFG2_50610_LED_MODES;
 965                 break;
 966         case PHY_ID_BCMAC131:
 967                 val = MAC_PHYCFG2_AC131_LED_MODES;
 968                 break;
 969         case PHY_ID_RTL8211C:
 970                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
 971                 break;
 972         case PHY_ID_RTL8201E:
 973                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
 974                 break;
 975         default:
 976                 return;
 977         }
 978
 979         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
 980                 tw32(MAC_PHYCFG2, val);
 981
 982                 val = tr32(MAC_PHYCFG1);
 983                 val &= ~(MAC_PHYCFG1_RGMII_INT |
 984                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
 985                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
 986                 tw32(MAC_PHYCFG1, val);
 987
 988                 return;
 989         }
 990
 991         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
 992                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
 993                        MAC_PHYCFG2_FMODE_MASK_MASK |
 994                        MAC_PHYCFG2_GMODE_MASK_MASK |
 995                        MAC_PHYCFG2_ACT_MASK_MASK   |
 996                        MAC_PHYCFG2_QUAL_MASK_MASK |
 997                        MAC_PHYCFG2_INBAND_ENABLE;
 998
 999         tw32(MAC_PHYCFG2, val);
1000
1001         val = tr32(MAC_PHYCFG1);
1002         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1003                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1004         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1005                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1006                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1007                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1008                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1009         }
1010         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1011                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1012         tw32(MAC_PHYCFG1, val);
1013
1014         val = tr32(MAC_EXT_RGMII_MODE);
1015         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1016                  MAC_RGMII_MODE_RX_QUALITY |
1017                  MAC_RGMII_MODE_RX_ACTIVITY |
1018                  MAC_RGMII_MODE_RX_ENG_DET |
1019                  MAC_RGMII_MODE_TX_ENABLE |
1020                  MAC_RGMII_MODE_TX_LOWPWR |
1021                  MAC_RGMII_MODE_TX_RESET);
1022         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1023                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1024                         val |= MAC_RGMII_MODE_RX_INT_B |
1025                                MAC_RGMII_MODE_RX_QUALITY |
1026                                MAC_RGMII_MODE_RX_ACTIVITY |
1027                                MAC_RGMII_MODE_RX_ENG_DET;
1028                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1029                         val |= MAC_RGMII_MODE_TX_ENABLE |
1030                                MAC_RGMII_MODE_TX_LOWPWR |
1031                                MAC_RGMII_MODE_TX_RESET;
1032         }
1033         tw32(MAC_EXT_RGMII_MODE, val);
1034 }
1035
1036 static void tg3_mdio_start(struct tg3 *tp)
1037 {
1038         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1039         tw32_f(MAC_MI_MODE, tp->mi_mode);
1040         udelay(80);
1041
1042         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1043             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1044                 tg3_mdio_config_5785(tp);
1045 }
1046
1047 static int tg3_mdio_init(struct tg3 *tp)
1048 {
1049         int i;
1050         u32 reg;
1051         struct phy_device *phydev;
1052
1053         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1054             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
1055                 u32 is_serdes;
1056
1057                 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1058
1059                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1060                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1061                 else
1062                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1063                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1064                 if (is_serdes)
1065                         tp->phy_addr += 7;
1066         } else
1067                 tp->phy_addr = TG3_PHY_MII_ADDR;
1068
1069         tg3_mdio_start(tp);
1070
1071         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1072             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1073                 return 0;
1074
1075         tp->mdio_bus = mdiobus_alloc();
1076         if (tp->mdio_bus == NULL)
1077                 return -ENOMEM;
1078
1079         tp->mdio_bus->name     = "tg3 mdio bus";
1080         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1081                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1082         tp->mdio_bus->priv     = tp;
1083         tp->mdio_bus->parent   = &tp->pdev->dev;
1084         tp->mdio_bus->read     = &tg3_mdio_read;
1085         tp->mdio_bus->write    = &tg3_mdio_write;
1086         tp->mdio_bus->reset    = &tg3_mdio_reset;
1087         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1088         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1089
1090         for (i = 0; i < PHY_MAX_ADDR; i++)
1091                 tp->mdio_bus->irq[i] = PHY_POLL;
1092
1093         /* The bus registration will look for all the PHYs on the mdio bus.
1094          * Unfortunately, it does not ensure the PHY is powered up before
1095          * accessing the PHY ID registers.  A chip reset is the
1096          * quickest way to bring the device back to an operational state..
1097          */
1098         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1099                 tg3_bmcr_reset(tp);
1100
1101         i = mdiobus_register(tp->mdio_bus);
1102         if (i) {
1103                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1104                 mdiobus_free(tp->mdio_bus);
1105                 return i;
1106         }
1107
1108         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1109
1110         if (!phydev || !phydev->drv) {
1111                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1112                 mdiobus_unregister(tp->mdio_bus);
1113                 mdiobus_free(tp->mdio_bus);
1114                 return -ENODEV;
1115         }
1116
1117         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1118         case PHY_ID_BCM57780:
1119                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1120                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1121                 break;
1122         case PHY_ID_BCM50610:
1123         case PHY_ID_BCM50610M:
1124                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1125                                      PHY_BRCM_RX_REFCLK_UNUSED |
1126                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1127                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1128                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1129                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1130                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1131                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1132                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1133                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1134                 /* fallthru */
1135         case PHY_ID_RTL8211C:
1136                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1137                 break;
1138         case PHY_ID_RTL8201E:
1139         case PHY_ID_BCMAC131:
1140                 phydev->interface = PHY_INTERFACE_MODE_MII;
1141                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1142                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1143                 break;
1144         }
1145
1146         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1147
1148         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1149                 tg3_mdio_config_5785(tp);
1150
1151         return 0;
1152 }
1153
1154 static void tg3_mdio_fini(struct tg3 *tp)
1155 {
1156         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1157                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1158                 mdiobus_unregister(tp->mdio_bus);
1159                 mdiobus_free(tp->mdio_bus);
1160         }
1161 }
1162
1163 /* tp->lock is held. */
1164 static inline void tg3_generate_fw_event(struct tg3 *tp)
1165 {
1166         u32 val;
1167
1168         val = tr32(GRC_RX_CPU_EVENT);
1169         val |= GRC_RX_CPU_DRIVER_EVENT;
1170         tw32_f(GRC_RX_CPU_EVENT, val);
1171
1172         tp->last_event_jiffies = jiffies;
1173 }
1174
1175 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1176
1177 /* tp->lock is held. */
1178 static void tg3_wait_for_event_ack(struct tg3 *tp)
1179 {
1180         int i;
1181         unsigned int delay_cnt;
1182         long time_remain;
1183
1184         /* If enough time has passed, no wait is necessary. */
1185         time_remain = (long)(tp->last_event_jiffies + 1 +
1186                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1187                       (long)jiffies;
1188         if (time_remain < 0)
1189                 return;
1190
1191         /* Check if we can shorten the wait time. */
1192         delay_cnt = jiffies_to_usecs(time_remain);
1193         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1194                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1195         delay_cnt = (delay_cnt >> 3) + 1;
1196
1197         for (i = 0; i < delay_cnt; i++) {
1198                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1199                         break;
1200                 udelay(8);
1201         }
1202 }
1203
1204 /* tp->lock is held. */
1205 static void tg3_ump_link_report(struct tg3 *tp)
1206 {
1207         u32 reg;
1208         u32 val;
1209
1210         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1211             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1212                 return;
1213
1214         tg3_wait_for_event_ack(tp);
1215
1216         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1217
1218         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1219
1220         val = 0;
1221         if (!tg3_readphy(tp, MII_BMCR, &reg))
1222                 val = reg << 16;
1223         if (!tg3_readphy(tp, MII_BMSR, &reg))
1224                 val |= (reg & 0xffff);
1225         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1226
1227         val = 0;
1228         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1229                 val = reg << 16;
1230         if (!tg3_readphy(tp, MII_LPA, &reg))
1231                 val |= (reg & 0xffff);
1232         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1233
1234         val = 0;
1235         if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1236                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1237                         val = reg << 16;
1238                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1239                         val |= (reg & 0xffff);
1240         }
1241         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1242
1243         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1244                 val = reg << 16;
1245         else
1246                 val = 0;
1247         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1248
1249         tg3_generate_fw_event(tp);
1250 }
1251
1252 static void tg3_link_report(struct tg3 *tp)
1253 {
1254         if (!netif_carrier_ok(tp->dev)) {
1255                 netif_info(tp, link, tp->dev, "Link is down\n");
1256                 tg3_ump_link_report(tp);
1257         } else if (netif_msg_link(tp)) {
1258                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1259                             (tp->link_config.active_speed == SPEED_1000 ?
1260                              1000 :
1261                              (tp->link_config.active_speed == SPEED_100 ?
1262                               100 : 10)),
1263                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1264                              "full" : "half"));
1265
1266                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1267                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1268                             "on" : "off",
1269                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1270                             "on" : "off");
1271                 tg3_ump_link_report(tp);
1272         }
1273 }
1274
1275 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1276 {
1277         u16 miireg;
1278
1279         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1280                 miireg = ADVERTISE_PAUSE_CAP;
1281         else if (flow_ctrl & FLOW_CTRL_TX)
1282                 miireg = ADVERTISE_PAUSE_ASYM;
1283         else if (flow_ctrl & FLOW_CTRL_RX)
1284                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1285         else
1286                 miireg = 0;
1287
1288         return miireg;
1289 }
1290
1291 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1292 {
1293         u16 miireg;
1294
1295         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1296                 miireg = ADVERTISE_1000XPAUSE;
1297         else if (flow_ctrl & FLOW_CTRL_TX)
1298                 miireg = ADVERTISE_1000XPSE_ASYM;
1299         else if (flow_ctrl & FLOW_CTRL_RX)
1300                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1301         else
1302                 miireg = 0;
1303
1304         return miireg;
1305 }
1306
1307 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1308 {
1309         u8 cap = 0;
1310
1311         if (lcladv & ADVERTISE_1000XPAUSE) {
1312                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1313                         if (rmtadv & LPA_1000XPAUSE)
1314                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1315                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1316                                 cap = FLOW_CTRL_RX;
1317                 } else {
1318                         if (rmtadv & LPA_1000XPAUSE)
1319                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1320                 }
1321         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1322                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1323                         cap = FLOW_CTRL_TX;
1324         }
1325
1326         return cap;
1327 }
1328
1329 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1330 {
1331         u8 autoneg;
1332         u8 flowctrl = 0;
1333         u32 old_rx_mode = tp->rx_mode;
1334         u32 old_tx_mode = tp->tx_mode;
1335
1336         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1337                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1338         else
1339                 autoneg = tp->link_config.autoneg;
1340
1341         if (autoneg == AUTONEG_ENABLE &&
1342             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1343                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1344                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1345                 else
1346                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1347         } else
1348                 flowctrl = tp->link_config.flowctrl;
1349
1350         tp->link_config.active_flowctrl = flowctrl;
1351
1352         if (flowctrl & FLOW_CTRL_RX)
1353                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1354         else
1355                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1356
1357         if (old_rx_mode != tp->rx_mode)
1358                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1359
1360         if (flowctrl & FLOW_CTRL_TX)
1361                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1362         else
1363                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1364
1365         if (old_tx_mode != tp->tx_mode)
1366                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1367 }
1368
1369 static void tg3_adjust_link(struct net_device *dev)
1370 {
1371         u8 oldflowctrl, linkmesg = 0;
1372         u32 mac_mode, lcl_adv, rmt_adv;
1373         struct tg3 *tp = netdev_priv(dev);
1374         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1375
1376         spin_lock_bh(&tp->lock);
1377
1378         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1379                                     MAC_MODE_HALF_DUPLEX);
1380
1381         oldflowctrl = tp->link_config.active_flowctrl;
1382
1383         if (phydev->link) {
1384                 lcl_adv = 0;
1385                 rmt_adv = 0;
1386
1387                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1388                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1389                 else if (phydev->speed == SPEED_1000 ||
1390                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1391                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1392                 else
1393                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1394
1395                 if (phydev->duplex == DUPLEX_HALF)
1396                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1397                 else {
1398                         lcl_adv = tg3_advert_flowctrl_1000T(
1399                                   tp->link_config.flowctrl);
1400
1401                         if (phydev->pause)
1402                                 rmt_adv = LPA_PAUSE_CAP;
1403                         if (phydev->asym_pause)
1404                                 rmt_adv |= LPA_PAUSE_ASYM;
1405                 }
1406
1407                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1408         } else
1409                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1410
1411         if (mac_mode != tp->mac_mode) {
1412                 tp->mac_mode = mac_mode;
1413                 tw32_f(MAC_MODE, tp->mac_mode);
1414                 udelay(40);
1415         }
1416
1417         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1418                 if (phydev->speed == SPEED_10)
1419                         tw32(MAC_MI_STAT,
1420                              MAC_MI_STAT_10MBPS_MODE |
1421                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1422                 else
1423                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1424         }
1425
1426         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1427                 tw32(MAC_TX_LENGTHS,
1428                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1429                       (6 << TX_LENGTHS_IPG_SHIFT) |
1430                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1431         else
1432                 tw32(MAC_TX_LENGTHS,
1433                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1434                       (6 << TX_LENGTHS_IPG_SHIFT) |
1435                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1436
1437         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1438             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1439             phydev->speed != tp->link_config.active_speed ||
1440             phydev->duplex != tp->link_config.active_duplex ||
1441             oldflowctrl != tp->link_config.active_flowctrl)
1442                 linkmesg = 1;
1443
1444         tp->link_config.active_speed = phydev->speed;
1445         tp->link_config.active_duplex = phydev->duplex;
1446
1447         spin_unlock_bh(&tp->lock);
1448
1449         if (linkmesg)
1450                 tg3_link_report(tp);
1451 }
1452
1453 static int tg3_phy_init(struct tg3 *tp)
1454 {
1455         struct phy_device *phydev;
1456
1457         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1458                 return 0;
1459
1460         /* Bring the PHY back to a known state. */
1461         tg3_bmcr_reset(tp);
1462
1463         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1464
1465         /* Attach the MAC to the PHY. */
1466         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1467                              phydev->dev_flags, phydev->interface);
1468         if (IS_ERR(phydev)) {
1469                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1470                 return PTR_ERR(phydev);
1471         }
1472
1473         /* Mask with MAC supported features. */
1474         switch (phydev->interface) {
1475         case PHY_INTERFACE_MODE_GMII:
1476         case PHY_INTERFACE_MODE_RGMII:
1477                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1478                         phydev->supported &= (PHY_GBIT_FEATURES |
1479                                               SUPPORTED_Pause |
1480                                               SUPPORTED_Asym_Pause);
1481                         break;
1482                 }
1483                 /* fallthru */
1484         case PHY_INTERFACE_MODE_MII:
1485                 phydev->supported &= (PHY_BASIC_FEATURES |
1486                                       SUPPORTED_Pause |
1487                                       SUPPORTED_Asym_Pause);
1488                 break;
1489         default:
1490                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1491                 return -EINVAL;
1492         }
1493
1494         tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1495
1496         phydev->advertising = phydev->supported;
1497
1498         return 0;
1499 }
1500
1501 static void tg3_phy_start(struct tg3 *tp)
1502 {
1503         struct phy_device *phydev;
1504
1505         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1506                 return;
1507
1508         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1509
1510         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1511                 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1512                 phydev->speed = tp->link_config.orig_speed;
1513                 phydev->duplex = tp->link_config.orig_duplex;
1514                 phydev->autoneg = tp->link_config.orig_autoneg;
1515                 phydev->advertising = tp->link_config.orig_advertising;
1516         }
1517
1518         phy_start(phydev);
1519
1520         phy_start_aneg(phydev);
1521 }
1522
1523 static void tg3_phy_stop(struct tg3 *tp)
1524 {
1525         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1526                 return;
1527
1528         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1529 }
1530
1531 static void tg3_phy_fini(struct tg3 *tp)
1532 {
1533         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1534                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1535                 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1536         }
1537 }
1538
1539 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1540 {
1541         int err;
1542
1543         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1544         if (!err)
1545                 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1546
1547         return err;
1548 }
1549
1550 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1551 {
1552         u32 phytest;
1553
1554         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1555                 u32 phy;
1556
1557                 tg3_writephy(tp, MII_TG3_FET_TEST,
1558                              phytest | MII_TG3_FET_SHADOW_EN);
1559                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1560                         if (enable)
1561                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1562                         else
1563                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1564                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1565                 }
1566                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1567         }
1568 }
1569
1570 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1571 {
1572         u32 reg;
1573
1574         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1575             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1576               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1577              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1578                 return;
1579
1580         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1581                 tg3_phy_fet_toggle_apd(tp, enable);
1582                 return;
1583         }
1584
1585         reg = MII_TG3_MISC_SHDW_WREN |
1586               MII_TG3_MISC_SHDW_SCR5_SEL |
1587               MII_TG3_MISC_SHDW_SCR5_LPED |
1588               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1589               MII_TG3_MISC_SHDW_SCR5_SDTL |
1590               MII_TG3_MISC_SHDW_SCR5_C125OE;
1591         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1592                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1593
1594         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1595
1596
1597         reg = MII_TG3_MISC_SHDW_WREN |
1598               MII_TG3_MISC_SHDW_APD_SEL |
1599               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1600         if (enable)
1601                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1602
1603         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1604 }
1605
1606 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1607 {
1608         u32 phy;
1609
1610         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1611             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
1612                 return;
1613
1614         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1615                 u32 ephy;
1616
1617                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1618                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1619
1620                         tg3_writephy(tp, MII_TG3_FET_TEST,
1621                                      ephy | MII_TG3_FET_SHADOW_EN);
1622                         if (!tg3_readphy(tp, reg, &phy)) {
1623                                 if (enable)
1624                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1625                                 else
1626                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1627                                 tg3_writephy(tp, reg, phy);
1628                         }
1629                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1630                 }
1631         } else {
1632                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1633                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1634                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1635                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1636                         if (enable)
1637                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1638                         else
1639                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1640                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1641                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1642                 }
1643         }
1644 }
1645
1646 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1647 {
1648         u32 val;
1649
1650         if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1651                 return;
1652
1653         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1654             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1655                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1656                              (val | (1 << 15) | (1 << 4)));
1657 }
1658
1659 static void tg3_phy_apply_otp(struct tg3 *tp)
1660 {
1661         u32 otp, phy;
1662
1663         if (!tp->phy_otp)
1664                 return;
1665
1666         otp = tp->phy_otp;
1667
1668         /* Enable SM_DSP clock and tx 6dB coding. */
1669         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1670               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1671               MII_TG3_AUXCTL_ACTL_TX_6DB;
1672         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1673
1674         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1675         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1676         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1677
1678         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1679               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1680         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1681
1682         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1683         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1684         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1685
1686         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1687         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1688
1689         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1690         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1691
1692         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1693               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1694         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1695
1696         /* Turn off SM_DSP clock. */
1697         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1698               MII_TG3_AUXCTL_ACTL_TX_6DB;
1699         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1700 }
1701
1702 static int tg3_wait_macro_done(struct tg3 *tp)
1703 {
1704         int limit = 100;
1705
1706         while (limit--) {
1707                 u32 tmp32;
1708
1709                 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1710                         if ((tmp32 & 0x1000) == 0)
1711                                 break;
1712                 }
1713         }
1714         if (limit < 0)
1715                 return -EBUSY;
1716
1717         return 0;
1718 }
1719
1720 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1721 {
1722         static const u32 test_pat[4][6] = {
1723         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1724         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1725         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1726         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1727         };
1728         int chan;
1729
1730         for (chan = 0; chan < 4; chan++) {
1731                 int i;
1732
1733                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1734                              (chan * 0x2000) | 0x0200);
1735                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1736
1737                 for (i = 0; i < 6; i++)
1738                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1739                                      test_pat[chan][i]);
1740
1741                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1742                 if (tg3_wait_macro_done(tp)) {
1743                         *resetp = 1;
1744                         return -EBUSY;
1745                 }
1746
1747                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1748                              (chan * 0x2000) | 0x0200);
1749                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1750                 if (tg3_wait_macro_done(tp)) {
1751                         *resetp = 1;
1752                         return -EBUSY;
1753                 }
1754
1755                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1756                 if (tg3_wait_macro_done(tp)) {
1757                         *resetp = 1;
1758                         return -EBUSY;
1759                 }
1760
1761                 for (i = 0; i < 6; i += 2) {
1762                         u32 low, high;
1763
1764                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1765                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1766                             tg3_wait_macro_done(tp)) {
1767                                 *resetp = 1;
1768                                 return -EBUSY;
1769                         }
1770                         low &= 0x7fff;
1771                         high &= 0x000f;
1772                         if (low != test_pat[chan][i] ||
1773                             high != test_pat[chan][i+1]) {
1774                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1775                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1776                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1777
1778                                 return -EBUSY;
1779                         }
1780                 }
1781         }
1782
1783         return 0;
1784 }
1785
1786 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1787 {
1788         int chan;
1789
1790         for (chan = 0; chan < 4; chan++) {
1791                 int i;
1792
1793                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1794                              (chan * 0x2000) | 0x0200);
1795                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1796                 for (i = 0; i < 6; i++)
1797                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1798                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1799                 if (tg3_wait_macro_done(tp))
1800                         return -EBUSY;
1801         }
1802
1803         return 0;
1804 }
1805
1806 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1807 {
1808         u32 reg32, phy9_orig;
1809         int retries, do_phy_reset, err;
1810
1811         retries = 10;
1812         do_phy_reset = 1;
1813         do {
1814                 if (do_phy_reset) {
1815                         err = tg3_bmcr_reset(tp);
1816                         if (err)
1817                                 return err;
1818                         do_phy_reset = 0;
1819                 }
1820
1821                 /* Disable transmitter and interrupt.  */
1822                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1823                         continue;
1824
1825                 reg32 |= 0x3000;
1826                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1827
1828                 /* Set full-duplex, 1000 mbps.  */
1829                 tg3_writephy(tp, MII_BMCR,
1830                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1831
1832                 /* Set to master mode.  */
1833                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1834                         continue;
1835
1836                 tg3_writephy(tp, MII_TG3_CTRL,
1837                              (MII_TG3_CTRL_AS_MASTER |
1838                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1839
1840                 /* Enable SM_DSP_CLOCK and 6dB.  */
1841                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1842
1843                 /* Block the PHY control access.  */
1844                 tg3_phydsp_write(tp, 0x8005, 0x0800);
1845
1846                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1847                 if (!err)
1848                         break;
1849         } while (--retries);
1850
1851         err = tg3_phy_reset_chanpat(tp);
1852         if (err)
1853                 return err;
1854
1855         tg3_phydsp_write(tp, 0x8005, 0x0000);
1856
1857         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1858         tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1859
1860         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1861             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1862                 /* Set Extended packet length bit for jumbo frames */
1863                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1864         } else {
1865                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1866         }
1867
1868         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1869
1870         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1871                 reg32 &= ~0x3000;
1872                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1873         } else if (!err)
1874                 err = -EBUSY;
1875
1876         return err;
1877 }
1878
1879 /* This will reset the tigon3 PHY if there is no valid
1880  * link unless the FORCE argument is non-zero.
1881  */
1882 static int tg3_phy_reset(struct tg3 *tp)
1883 {
1884         u32 val, cpmuctrl;
1885         int err;
1886
1887         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1888                 val = tr32(GRC_MISC_CFG);
1889                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1890                 udelay(40);
1891         }
1892         err  = tg3_readphy(tp, MII_BMSR, &val);
1893         err |= tg3_readphy(tp, MII_BMSR, &val);
1894         if (err != 0)
1895                 return -EBUSY;
1896
1897         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1898                 netif_carrier_off(tp->dev);
1899                 tg3_link_report(tp);
1900         }
1901
1902         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1903             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1904             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1905                 err = tg3_phy_reset_5703_4_5(tp);
1906                 if (err)
1907                         return err;
1908                 goto out;
1909         }
1910
1911         cpmuctrl = 0;
1912         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1913             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1914                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1915                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1916                         tw32(TG3_CPMU_CTRL,
1917                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1918         }
1919
1920         err = tg3_bmcr_reset(tp);
1921         if (err)
1922                 return err;
1923
1924         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1925                 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1926                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
1927
1928                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1929         }
1930
1931         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1932             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1933                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1934                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1935                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1936                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1937                         udelay(40);
1938                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1939                 }
1940         }
1941
1942         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1943              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1944             (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
1945                 return 0;
1946
1947         tg3_phy_apply_otp(tp);
1948
1949         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
1950                 tg3_phy_toggle_apd(tp, true);
1951         else
1952                 tg3_phy_toggle_apd(tp, false);
1953
1954 out:
1955         if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) {
1956                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1957                 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
1958                 tg3_phydsp_write(tp, 0x000a, 0x0323);
1959                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1960         }
1961         if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
1962                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
1963                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
1964         }
1965         if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
1966                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1967                 tg3_phydsp_write(tp, 0x000a, 0x310b);
1968                 tg3_phydsp_write(tp, 0x201f, 0x9506);
1969                 tg3_phydsp_write(tp, 0x401f, 0x14e2);
1970                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1971         } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
1972                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1973                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1974                 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
1975                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1976                         tg3_writephy(tp, MII_TG3_TEST1,
1977                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1978                 } else
1979                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1980                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1981         }
1982         /* Set Extended packet length bit (bit 14) on all chips that */
1983         /* support jumbo frames */
1984         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1985                 /* Cannot do read-modify-write on 5401 */
1986                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1987         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1988                 /* Set bit 14 with read-modify-write to preserve other bits */
1989                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1990                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1991                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val | 0x4000);
1992         }
1993
1994         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1995          * jumbo frames transmission.
1996          */
1997         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1998                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
1999                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2000                                      val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2001         }
2002
2003         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2004                 /* adjust output voltage */
2005                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2006         }
2007
2008         tg3_phy_toggle_automdix(tp, 1);
2009         tg3_phy_set_wirespeed(tp);
2010         return 0;
2011 }
2012
2013 static void tg3_frob_aux_power(struct tg3 *tp)
2014 {
2015         struct tg3 *tp_peer = tp;
2016
2017         /* The GPIOs do something completely different on 57765. */
2018         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2019             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2020             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2021                 return;
2022
2023         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2024             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2025             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2026                 struct net_device *dev_peer;
2027
2028                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2029                 /* remove_one() may have been run on the peer. */
2030                 if (!dev_peer)
2031                         tp_peer = tp;
2032                 else
2033                         tp_peer = netdev_priv(dev_peer);
2034         }
2035
2036         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2037             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2038             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2039             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2040                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2041                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2042                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2043                                     (GRC_LCLCTRL_GPIO_OE0 |
2044                                      GRC_LCLCTRL_GPIO_OE1 |
2045                                      GRC_LCLCTRL_GPIO_OE2 |
2046                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2047                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2048                                     100);
2049                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2050                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2051                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2052                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2053                                              GRC_LCLCTRL_GPIO_OE1 |
2054                                              GRC_LCLCTRL_GPIO_OE2 |
2055                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2056                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2057                                              tp->grc_local_ctrl;
2058                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2059
2060                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2061                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2062
2063                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2064                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2065                 } else {
2066                         u32 no_gpio2;
2067                         u32 grc_local_ctrl = 0;
2068
2069                         if (tp_peer != tp &&
2070                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2071                                 return;
2072
2073                         /* Workaround to prevent overdrawing Amps. */
2074                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2075                             ASIC_REV_5714) {
2076                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2077                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2078                                             grc_local_ctrl, 100);
2079                         }
2080
2081                         /* On 5753 and variants, GPIO2 cannot be used. */
2082                         no_gpio2 = tp->nic_sram_data_cfg &
2083                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2084
2085                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2086                                          GRC_LCLCTRL_GPIO_OE1 |
2087                                          GRC_LCLCTRL_GPIO_OE2 |
2088                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2089                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2090                         if (no_gpio2) {
2091                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2092                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2093                         }
2094                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2095                                                     grc_local_ctrl, 100);
2096
2097                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2098
2099                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2100                                                     grc_local_ctrl, 100);
2101
2102                         if (!no_gpio2) {
2103                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2104                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2105                                             grc_local_ctrl, 100);
2106                         }
2107                 }
2108         } else {
2109                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2110                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2111                         if (tp_peer != tp &&
2112                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2113                                 return;
2114
2115                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2116                                     (GRC_LCLCTRL_GPIO_OE1 |
2117                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2118
2119                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2120                                     GRC_LCLCTRL_GPIO_OE1, 100);
2121
2122                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2123                                     (GRC_LCLCTRL_GPIO_OE1 |
2124                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2125                 }
2126         }
2127 }
2128
2129 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2130 {
2131         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2132                 return 1;
2133         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2134                 if (speed != SPEED_10)
2135                         return 1;
2136         } else if (speed == SPEED_10)
2137                 return 1;
2138
2139         return 0;
2140 }
2141
2142 static int tg3_setup_phy(struct tg3 *, int);
2143
2144 #define RESET_KIND_SHUTDOWN     0
2145 #define RESET_KIND_INIT         1
2146 #define RESET_KIND_SUSPEND      2
2147
2148 static void tg3_write_sig_post_reset(struct tg3 *, int);
2149 static int tg3_halt_cpu(struct tg3 *, u32);
2150
2151 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2152 {
2153         u32 val;
2154
2155         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2156                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2157                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2158                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2159
2160                         sg_dig_ctrl |=
2161                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2162                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2163                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2164                 }
2165                 return;
2166         }
2167
2168         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2169                 tg3_bmcr_reset(tp);
2170                 val = tr32(GRC_MISC_CFG);
2171                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2172                 udelay(40);
2173                 return;
2174         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2175                 u32 phytest;
2176                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2177                         u32 phy;
2178
2179                         tg3_writephy(tp, MII_ADVERTISE, 0);
2180                         tg3_writephy(tp, MII_BMCR,
2181                                      BMCR_ANENABLE | BMCR_ANRESTART);
2182
2183                         tg3_writephy(tp, MII_TG3_FET_TEST,
2184                                      phytest | MII_TG3_FET_SHADOW_EN);
2185                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2186                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2187                                 tg3_writephy(tp,
2188                                              MII_TG3_FET_SHDW_AUXMODE4,
2189                                              phy);
2190                         }
2191                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2192                 }
2193                 return;
2194         } else if (do_low_power) {
2195                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2196                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2197
2198                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2199                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2200                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2201                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2202                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2203         }
2204
2205         /* The PHY should not be powered down on some chips because
2206          * of bugs.
2207          */
2208         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2209             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2210             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2211              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2212                 return;
2213
2214         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2215             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2216                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2217                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2218                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2219                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2220         }
2221
2222         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2223 }
2224
2225 /* tp->lock is held. */
2226 static int tg3_nvram_lock(struct tg3 *tp)
2227 {
2228         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2229                 int i;
2230
2231                 if (tp->nvram_lock_cnt == 0) {
2232                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2233                         for (i = 0; i < 8000; i++) {
2234                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2235                                         break;
2236                                 udelay(20);
2237                         }
2238                         if (i == 8000) {
2239                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2240                                 return -ENODEV;
2241                         }
2242                 }
2243                 tp->nvram_lock_cnt++;
2244         }
2245         return 0;
2246 }
2247
2248 /* tp->lock is held. */
2249 static void tg3_nvram_unlock(struct tg3 *tp)
2250 {
2251         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2252                 if (tp->nvram_lock_cnt > 0)
2253                         tp->nvram_lock_cnt--;
2254                 if (tp->nvram_lock_cnt == 0)
2255                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2256         }
2257 }
2258
2259 /* tp->lock is held. */
2260 static void tg3_enable_nvram_access(struct tg3 *tp)
2261 {
2262         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2263             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2264                 u32 nvaccess = tr32(NVRAM_ACCESS);
2265
2266                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2267         }
2268 }
2269
2270 /* tp->lock is held. */
2271 static void tg3_disable_nvram_access(struct tg3 *tp)
2272 {
2273         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2274             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2275                 u32 nvaccess = tr32(NVRAM_ACCESS);
2276
2277                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2278         }
2279 }
2280
2281 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2282                                         u32 offset, u32 *val)
2283 {
2284         u32 tmp;
2285         int i;
2286
2287         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2288                 return -EINVAL;
2289
2290         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2291                                         EEPROM_ADDR_DEVID_MASK |
2292                                         EEPROM_ADDR_READ);
2293         tw32(GRC_EEPROM_ADDR,
2294              tmp |
2295              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2296              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2297               EEPROM_ADDR_ADDR_MASK) |
2298              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2299
2300         for (i = 0; i < 1000; i++) {
2301                 tmp = tr32(GRC_EEPROM_ADDR);
2302
2303                 if (tmp & EEPROM_ADDR_COMPLETE)
2304                         break;
2305                 msleep(1);
2306         }
2307         if (!(tmp & EEPROM_ADDR_COMPLETE))
2308                 return -EBUSY;
2309
2310         tmp = tr32(GRC_EEPROM_DATA);
2311
2312         /*
2313          * The data will always be opposite the native endian
2314          * format.  Perform a blind byteswap to compensate.
2315          */
2316         *val = swab32(tmp);
2317
2318         return 0;
2319 }
2320
2321 #define NVRAM_CMD_TIMEOUT 10000
2322
2323 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2324 {
2325         int i;
2326
2327         tw32(NVRAM_CMD, nvram_cmd);
2328         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2329                 udelay(10);
2330                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2331                         udelay(10);
2332                         break;
2333                 }
2334         }
2335
2336         if (i == NVRAM_CMD_TIMEOUT)
2337                 return -EBUSY;
2338
2339         return 0;
2340 }
2341
2342 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2343 {
2344         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2345             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2346             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2347            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2348             (tp->nvram_jedecnum == JEDEC_ATMEL))
2349
2350                 addr = ((addr / tp->nvram_pagesize) <<
2351                         ATMEL_AT45DB0X1B_PAGE_POS) +
2352                        (addr % tp->nvram_pagesize);
2353
2354         return addr;
2355 }
2356
2357 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2358 {
2359         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2360             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2361             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2362            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2363             (tp->nvram_jedecnum == JEDEC_ATMEL))
2364
2365                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2366                         tp->nvram_pagesize) +
2367                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2368
2369         return addr;
2370 }
2371
2372 /* NOTE: Data read in from NVRAM is byteswapped according to
2373  * the byteswapping settings for all other register accesses.
2374  * tg3 devices are BE devices, so on a BE machine, the data
2375  * returned will be exactly as it is seen in NVRAM.  On a LE
2376  * machine, the 32-bit value will be byteswapped.
2377  */
2378 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2379 {
2380         int ret;
2381
2382         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2383                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2384
2385         offset = tg3_nvram_phys_addr(tp, offset);
2386
2387         if (offset > NVRAM_ADDR_MSK)
2388                 return -EINVAL;
2389
2390         ret = tg3_nvram_lock(tp);
2391         if (ret)
2392                 return ret;
2393
2394         tg3_enable_nvram_access(tp);
2395
2396         tw32(NVRAM_ADDR, offset);
2397         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2398                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2399
2400         if (ret == 0)
2401                 *val = tr32(NVRAM_RDDATA);
2402
2403         tg3_disable_nvram_access(tp);
2404
2405         tg3_nvram_unlock(tp);
2406
2407         return ret;
2408 }
2409
2410 /* Ensures NVRAM data is in bytestream format. */
2411 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2412 {
2413         u32 v;
2414         int res = tg3_nvram_read(tp, offset, &v);
2415         if (!res)
2416                 *val = cpu_to_be32(v);
2417         return res;
2418 }
2419
2420 /* tp->lock is held. */
2421 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2422 {
2423         u32 addr_high, addr_low;
2424         int i;
2425
2426         addr_high = ((tp->dev->dev_addr[0] << 8) |
2427                      tp->dev->dev_addr[1]);
2428         addr_low = ((tp->dev->dev_addr[2] << 24) |
2429                     (tp->dev->dev_addr[3] << 16) |
2430                     (tp->dev->dev_addr[4] <<  8) |
2431                     (tp->dev->dev_addr[5] <<  0));
2432         for (i = 0; i < 4; i++) {
2433                 if (i == 1 && skip_mac_1)
2434                         continue;
2435                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2436                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2437         }
2438
2439         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2440             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2441                 for (i = 0; i < 12; i++) {
2442                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2443                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2444                 }
2445         }
2446
2447         addr_high = (tp->dev->dev_addr[0] +
2448                      tp->dev->dev_addr[1] +
2449                      tp->dev->dev_addr[2] +
2450                      tp->dev->dev_addr[3] +
2451                      tp->dev->dev_addr[4] +
2452                      tp->dev->dev_addr[5]) &
2453                 TX_BACKOFF_SEED_MASK;
2454         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2455 }
2456
2457 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2458 {
2459         u32 misc_host_ctrl;
2460         bool device_should_wake, do_low_power;
2461
2462         /* Make sure register accesses (indirect or otherwise)
2463          * will function correctly.
2464          */
2465         pci_write_config_dword(tp->pdev,
2466                                TG3PCI_MISC_HOST_CTRL,
2467                                tp->misc_host_ctrl);
2468
2469         switch (state) {
2470         case PCI_D0:
2471                 pci_enable_wake(tp->pdev, state, false);
2472                 pci_set_power_state(tp->pdev, PCI_D0);
2473
2474                 /* Switch out of Vaux if it is a NIC */
2475                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2476                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2477
2478                 return 0;
2479
2480         case PCI_D1:
2481         case PCI_D2:
2482         case PCI_D3hot:
2483                 break;
2484
2485         default:
2486                 netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
2487                            state);
2488                 return -EINVAL;
2489         }
2490
2491         /* Restore the CLKREQ setting. */
2492         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2493                 u16 lnkctl;
2494
2495                 pci_read_config_word(tp->pdev,
2496                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2497                                      &lnkctl);
2498                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2499                 pci_write_config_word(tp->pdev,
2500                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2501                                       lnkctl);
2502         }
2503
2504         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2505         tw32(TG3PCI_MISC_HOST_CTRL,
2506              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2507
2508         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2509                              device_may_wakeup(&tp->pdev->dev) &&
2510                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2511
2512         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2513                 do_low_power = false;
2514                 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
2515                     !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2516                         struct phy_device *phydev;
2517                         u32 phyid, advertising;
2518
2519                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2520
2521                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2522
2523                         tp->link_config.orig_speed = phydev->speed;
2524                         tp->link_config.orig_duplex = phydev->duplex;
2525                         tp->link_config.orig_autoneg = phydev->autoneg;
2526                         tp->link_config.orig_advertising = phydev->advertising;
2527
2528                         advertising = ADVERTISED_TP |
2529                                       ADVERTISED_Pause |
2530                                       ADVERTISED_Autoneg |
2531                                       ADVERTISED_10baseT_Half;
2532
2533                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2534                             device_should_wake) {
2535                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2536                                         advertising |=
2537                                                 ADVERTISED_100baseT_Half |
2538                                                 ADVERTISED_100baseT_Full |
2539                                                 ADVERTISED_10baseT_Full;
2540                                 else
2541                                         advertising |= ADVERTISED_10baseT_Full;
2542                         }
2543
2544                         phydev->advertising = advertising;
2545
2546                         phy_start_aneg(phydev);
2547
2548                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2549                         if (phyid != PHY_ID_BCMAC131) {
2550                                 phyid &= PHY_BCM_OUI_MASK;
2551                                 if (phyid == PHY_BCM_OUI_1 ||
2552                                     phyid == PHY_BCM_OUI_2 ||
2553                                     phyid == PHY_BCM_OUI_3)
2554                                         do_low_power = true;
2555                         }
2556                 }
2557         } else {
2558                 do_low_power = true;
2559
2560                 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2561                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2562                         tp->link_config.orig_speed = tp->link_config.speed;
2563                         tp->link_config.orig_duplex = tp->link_config.duplex;
2564                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2565                 }
2566
2567                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
2568                         tp->link_config.speed = SPEED_10;
2569                         tp->link_config.duplex = DUPLEX_HALF;
2570                         tp->link_config.autoneg = AUTONEG_ENABLE;
2571                         tg3_setup_phy(tp, 0);
2572                 }
2573         }
2574
2575         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2576                 u32 val;
2577
2578                 val = tr32(GRC_VCPU_EXT_CTRL);
2579                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2580         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2581                 int i;
2582                 u32 val;
2583
2584                 for (i = 0; i < 200; i++) {
2585                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2586                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2587                                 break;
2588                         msleep(1);
2589                 }
2590         }
2591         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2592                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2593                                                      WOL_DRV_STATE_SHUTDOWN |
2594                                                      WOL_DRV_WOL |
2595                                                      WOL_SET_MAGIC_PKT);
2596
2597         if (device_should_wake) {
2598                 u32 mac_mode;
2599
2600                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
2601                         if (do_low_power) {
2602                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2603                                 udelay(40);
2604                         }
2605
2606                         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
2607                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2608                         else
2609                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2610
2611                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2612                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2613                             ASIC_REV_5700) {
2614                                 u32 speed = (tp->tg3_flags &
2615                                              TG3_FLAG_WOL_SPEED_100MB) ?
2616                                              SPEED_100 : SPEED_10;
2617                                 if (tg3_5700_link_polarity(tp, speed))
2618                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2619                                 else
2620                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2621                         }
2622                 } else {
2623                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2624                 }
2625
2626                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2627                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2628
2629                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2630                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2631                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2632                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2633                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2634                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2635
2636                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2637                         mac_mode |= tp->mac_mode &
2638                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2639                         if (mac_mode & MAC_MODE_APE_TX_EN)
2640                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2641                 }
2642
2643                 tw32_f(MAC_MODE, mac_mode);
2644                 udelay(100);
2645
2646                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2647                 udelay(10);
2648         }
2649
2650         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2651             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2652              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2653                 u32 base_val;
2654
2655                 base_val = tp->pci_clock_ctrl;
2656                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2657                              CLOCK_CTRL_TXCLK_DISABLE);
2658
2659                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2660                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2661         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2662                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2663                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2664                 /* do nothing */
2665         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2666                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2667                 u32 newbits1, newbits2;
2668
2669                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2670                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2671                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2672                                     CLOCK_CTRL_TXCLK_DISABLE |
2673                                     CLOCK_CTRL_ALTCLK);
2674                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2675                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2676                         newbits1 = CLOCK_CTRL_625_CORE;
2677                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2678                 } else {
2679                         newbits1 = CLOCK_CTRL_ALTCLK;
2680                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2681                 }
2682
2683                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2684                             40);
2685
2686                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2687                             40);
2688
2689                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2690                         u32 newbits3;
2691
2692                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2693                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2694                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2695                                             CLOCK_CTRL_TXCLK_DISABLE |
2696                                             CLOCK_CTRL_44MHZ_CORE);
2697                         } else {
2698                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2699                         }
2700
2701                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2702                                     tp->pci_clock_ctrl | newbits3, 40);
2703                 }
2704         }
2705
2706         if (!(device_should_wake) &&
2707             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2708                 tg3_power_down_phy(tp, do_low_power);
2709
2710         tg3_frob_aux_power(tp);
2711
2712         /* Workaround for unstable PLL clock */
2713         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2714             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2715                 u32 val = tr32(0x7d00);
2716
2717                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2718                 tw32(0x7d00, val);
2719                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2720                         int err;
2721
2722                         err = tg3_nvram_lock(tp);
2723                         tg3_halt_cpu(tp, RX_CPU_BASE);
2724                         if (!err)
2725                                 tg3_nvram_unlock(tp);
2726                 }
2727         }
2728
2729         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2730
2731         if (device_should_wake)
2732                 pci_enable_wake(tp->pdev, state, true);
2733
2734         /* Finally, set the new power state. */
2735         pci_set_power_state(tp->pdev, state);
2736
2737         return 0;
2738 }
2739
2740 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2741 {
2742         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2743         case MII_TG3_AUX_STAT_10HALF:
2744                 *speed = SPEED_10;
2745                 *duplex = DUPLEX_HALF;
2746                 break;
2747
2748         case MII_TG3_AUX_STAT_10FULL:
2749                 *speed = SPEED_10;
2750                 *duplex = DUPLEX_FULL;
2751                 break;
2752
2753         case MII_TG3_AUX_STAT_100HALF:
2754                 *speed = SPEED_100;
2755                 *duplex = DUPLEX_HALF;
2756                 break;
2757
2758         case MII_TG3_AUX_STAT_100FULL:
2759                 *speed = SPEED_100;
2760                 *duplex = DUPLEX_FULL;
2761                 break;
2762
2763         case MII_TG3_AUX_STAT_1000HALF:
2764                 *speed = SPEED_1000;
2765                 *duplex = DUPLEX_HALF;
2766                 break;
2767
2768         case MII_TG3_AUX_STAT_1000FULL:
2769                 *speed = SPEED_1000;
2770                 *duplex = DUPLEX_FULL;
2771                 break;
2772
2773         default:
2774                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2775                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2776                                  SPEED_10;
2777                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2778                                   DUPLEX_HALF;
2779                         break;
2780                 }
2781                 *speed = SPEED_INVALID;
2782                 *duplex = DUPLEX_INVALID;
2783                 break;
2784         }
2785 }
2786
2787 static void tg3_phy_copper_begin(struct tg3 *tp)
2788 {
2789         u32 new_adv;
2790         int i;
2791
2792         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2793                 /* Entering low power mode.  Disable gigabit and
2794                  * 100baseT advertisements.
2795                  */
2796                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2797
2798                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2799                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2800                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2801                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2802
2803                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2804         } else if (tp->link_config.speed == SPEED_INVALID) {
2805                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
2806                         tp->link_config.advertising &=
2807                                 ~(ADVERTISED_1000baseT_Half |
2808                                   ADVERTISED_1000baseT_Full);
2809
2810                 new_adv = ADVERTISE_CSMA;
2811                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2812                         new_adv |= ADVERTISE_10HALF;
2813                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2814                         new_adv |= ADVERTISE_10FULL;
2815                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2816                         new_adv |= ADVERTISE_100HALF;
2817                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2818                         new_adv |= ADVERTISE_100FULL;
2819
2820                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2821
2822                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2823
2824                 if (tp->link_config.advertising &
2825                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2826                         new_adv = 0;
2827                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2828                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2829                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2830                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2831                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) &&
2832                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2833                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2834                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2835                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2836                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2837                 } else {
2838                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2839                 }
2840         } else {
2841                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2842                 new_adv |= ADVERTISE_CSMA;
2843
2844                 /* Asking for a specific link mode. */
2845                 if (tp->link_config.speed == SPEED_1000) {
2846                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2847
2848                         if (tp->link_config.duplex == DUPLEX_FULL)
2849                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2850                         else
2851                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2852                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2853                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2854                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2855                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2856                 } else {
2857                         if (tp->link_config.speed == SPEED_100) {
2858                                 if (tp->link_config.duplex == DUPLEX_FULL)
2859                                         new_adv |= ADVERTISE_100FULL;
2860                                 else
2861                                         new_adv |= ADVERTISE_100HALF;
2862                         } else {
2863                                 if (tp->link_config.duplex == DUPLEX_FULL)
2864                                         new_adv |= ADVERTISE_10FULL;
2865                                 else
2866                                         new_adv |= ADVERTISE_10HALF;
2867                         }
2868                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2869
2870                         new_adv = 0;
2871                 }
2872
2873                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2874         }
2875
2876         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2877             tp->link_config.speed != SPEED_INVALID) {
2878                 u32 bmcr, orig_bmcr;
2879
2880                 tp->link_config.active_speed = tp->link_config.speed;
2881                 tp->link_config.active_duplex = tp->link_config.duplex;
2882
2883                 bmcr = 0;
2884                 switch (tp->link_config.speed) {
2885                 default:
2886                 case SPEED_10:
2887                         break;
2888
2889                 case SPEED_100:
2890                         bmcr |= BMCR_SPEED100;
2891                         break;
2892
2893                 case SPEED_1000:
2894                         bmcr |= TG3_BMCR_SPEED1000;
2895                         break;
2896                 }
2897
2898                 if (tp->link_config.duplex == DUPLEX_FULL)
2899                         bmcr |= BMCR_FULLDPLX;
2900
2901                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2902                     (bmcr != orig_bmcr)) {
2903                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2904                         for (i = 0; i < 1500; i++) {
2905                                 u32 tmp;
2906
2907                                 udelay(10);
2908                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2909                                     tg3_readphy(tp, MII_BMSR, &tmp))
2910                                         continue;
2911                                 if (!(tmp & BMSR_LSTATUS)) {
2912                                         udelay(40);
2913                                         break;
2914                                 }
2915                         }
2916                         tg3_writephy(tp, MII_BMCR, bmcr);
2917                         udelay(40);
2918                 }
2919         } else {
2920                 tg3_writephy(tp, MII_BMCR,
2921                              BMCR_ANENABLE | BMCR_ANRESTART);
2922         }
2923 }
2924
2925 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2926 {
2927         int err;
2928
2929         /* Turn off tap power management. */
2930         /* Set Extended packet length bit */
2931         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2932
2933         err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
2934         err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
2935         err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
2936         err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
2937         err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
2938
2939         udelay(40);
2940
2941         return err;
2942 }
2943
2944 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2945 {
2946         u32 adv_reg, all_mask = 0;
2947
2948         if (mask & ADVERTISED_10baseT_Half)
2949                 all_mask |= ADVERTISE_10HALF;
2950         if (mask & ADVERTISED_10baseT_Full)
2951                 all_mask |= ADVERTISE_10FULL;
2952         if (mask & ADVERTISED_100baseT_Half)
2953                 all_mask |= ADVERTISE_100HALF;
2954         if (mask & ADVERTISED_100baseT_Full)
2955                 all_mask |= ADVERTISE_100FULL;
2956
2957         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2958                 return 0;
2959
2960         if ((adv_reg & all_mask) != all_mask)
2961                 return 0;
2962         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
2963                 u32 tg3_ctrl;
2964
2965                 all_mask = 0;
2966                 if (mask & ADVERTISED_1000baseT_Half)
2967                         all_mask |= ADVERTISE_1000HALF;
2968                 if (mask & ADVERTISED_1000baseT_Full)
2969                         all_mask |= ADVERTISE_1000FULL;
2970
2971                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2972                         return 0;
2973
2974                 if ((tg3_ctrl & all_mask) != all_mask)
2975                         return 0;
2976         }
2977         return 1;
2978 }
2979
2980 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2981 {
2982         u32 curadv, reqadv;
2983
2984         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2985                 return 1;
2986
2987         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2988         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2989
2990         if (tp->link_config.active_duplex == DUPLEX_FULL) {
2991                 if (curadv != reqadv)
2992                         return 0;
2993
2994                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2995                         tg3_readphy(tp, MII_LPA, rmtadv);
2996         } else {
2997                 /* Reprogram the advertisement register, even if it
2998                  * does not affect the current link.  If the link
2999                  * gets renegotiated in the future, we can save an
3000                  * additional renegotiation cycle by advertising
3001                  * it correctly in the first place.
3002                  */
3003                 if (curadv != reqadv) {
3004                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3005                                      ADVERTISE_PAUSE_ASYM);
3006                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3007                 }
3008         }
3009
3010         return 1;
3011 }
3012
3013 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3014 {
3015         int current_link_up;
3016         u32 bmsr, val;
3017         u32 lcl_adv, rmt_adv;
3018         u16 current_speed;
3019         u8 current_duplex;
3020         int i, err;
3021
3022         tw32(MAC_EVENT, 0);
3023
3024         tw32_f(MAC_STATUS,
3025              (MAC_STATUS_SYNC_CHANGED |
3026               MAC_STATUS_CFG_CHANGED |
3027               MAC_STATUS_MI_COMPLETION |
3028               MAC_STATUS_LNKSTATE_CHANGED));
3029         udelay(40);
3030
3031         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3032                 tw32_f(MAC_MI_MODE,
3033                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3034                 udelay(80);
3035         }
3036
3037         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3038
3039         /* Some third-party PHYs need to be reset on link going
3040          * down.
3041          */
3042         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3043              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3044              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3045             netif_carrier_ok(tp->dev)) {
3046                 tg3_readphy(tp, MII_BMSR, &bmsr);
3047                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3048                     !(bmsr & BMSR_LSTATUS))
3049                         force_reset = 1;
3050         }
3051         if (force_reset)
3052                 tg3_phy_reset(tp);
3053
3054         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3055                 tg3_readphy(tp, MII_BMSR, &bmsr);
3056                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3057                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3058                         bmsr = 0;
3059
3060                 if (!(bmsr & BMSR_LSTATUS)) {
3061                         err = tg3_init_5401phy_dsp(tp);
3062                         if (err)
3063                                 return err;
3064
3065                         tg3_readphy(tp, MII_BMSR, &bmsr);
3066                         for (i = 0; i < 1000; i++) {
3067                                 udelay(10);
3068                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3069                                     (bmsr & BMSR_LSTATUS)) {
3070                                         udelay(40);
3071                                         break;
3072                                 }
3073                         }
3074
3075                         if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3076                             TG3_PHY_REV_BCM5401_B0 &&
3077                             !(bmsr & BMSR_LSTATUS) &&
3078                             tp->link_config.active_speed == SPEED_1000) {
3079                                 err = tg3_phy_reset(tp);
3080                                 if (!err)
3081                                         err = tg3_init_5401phy_dsp(tp);
3082                                 if (err)
3083                                         return err;
3084                         }
3085                 }
3086         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3087                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3088                 /* 5701 {A0,B0} CRC bug workaround */
3089                 tg3_writephy(tp, 0x15, 0x0a75);
3090                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3091                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3092                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3093         }
3094
3095         /* Clear pending interrupts... */
3096         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3097         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3098
3099         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3100                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3101         else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3102                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3103
3104         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3105             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3106                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3107                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3108                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3109                 else
3110                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3111         }
3112
3113         current_link_up = 0;
3114         current_speed = SPEED_INVALID;
3115         current_duplex = DUPLEX_INVALID;
3116
3117         if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3118                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3119                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3120                 if (!(val & (1 << 10))) {
3121                         val |= (1 << 10);
3122                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3123                         goto relink;
3124                 }
3125         }
3126
3127         bmsr = 0;
3128         for (i = 0; i < 100; i++) {
3129                 tg3_readphy(tp, MII_BMSR, &bmsr);
3130                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3131                     (bmsr & BMSR_LSTATUS))
3132                         break;
3133                 udelay(40);
3134         }
3135
3136         if (bmsr & BMSR_LSTATUS) {
3137                 u32 aux_stat, bmcr;
3138
3139                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3140                 for (i = 0; i < 2000; i++) {
3141                         udelay(10);
3142                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3143                             aux_stat)
3144                                 break;
3145                 }
3146
3147                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3148                                              &current_speed,
3149                                              &current_duplex);
3150
3151                 bmcr = 0;
3152                 for (i = 0; i < 200; i++) {
3153                         tg3_readphy(tp, MII_BMCR, &bmcr);
3154                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3155                                 continue;
3156                         if (bmcr && bmcr != 0x7fff)
3157                                 break;
3158                         udelay(10);
3159                 }
3160
3161                 lcl_adv = 0;
3162                 rmt_adv = 0;
3163
3164                 tp->link_config.active_speed = current_speed;
3165                 tp->link_config.active_duplex = current_duplex;
3166
3167                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3168                         if ((bmcr & BMCR_ANENABLE) &&
3169                             tg3_copper_is_advertising_all(tp,
3170                                                 tp->link_config.advertising)) {
3171                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3172                                                                   &rmt_adv))
3173                                         current_link_up = 1;
3174                         }
3175                 } else {
3176                         if (!(bmcr & BMCR_ANENABLE) &&
3177                             tp->link_config.speed == current_speed &&
3178                             tp->link_config.duplex == current_duplex &&
3179                             tp->link_config.flowctrl ==
3180                             tp->link_config.active_flowctrl) {
3181                                 current_link_up = 1;
3182                         }
3183                 }
3184
3185                 if (current_link_up == 1 &&
3186                     tp->link_config.active_duplex == DUPLEX_FULL)
3187                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3188         }
3189
3190 relink:
3191         if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3192                 tg3_phy_copper_begin(tp);
3193
3194                 tg3_readphy(tp, MII_BMSR, &bmsr);
3195                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3196                     (bmsr & BMSR_LSTATUS))
3197                         current_link_up = 1;
3198         }
3199
3200         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3201         if (current_link_up == 1) {
3202                 if (tp->link_config.active_speed == SPEED_100 ||
3203                     tp->link_config.active_speed == SPEED_10)
3204                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3205                 else
3206                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3207         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
3208                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3209         else
3210                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3211
3212         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3213         if (tp->link_config.active_duplex == DUPLEX_HALF)
3214                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3215
3216         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3217                 if (current_link_up == 1 &&
3218                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3219                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3220                 else
3221                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3222         }
3223
3224         /* ??? Without this setting Netgear GA302T PHY does not
3225          * ??? send/receive packets...
3226          */
3227         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3228             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3229                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3230                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3231                 udelay(80);
3232         }
3233
3234         tw32_f(MAC_MODE, tp->mac_mode);
3235         udelay(40);
3236
3237         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3238                 /* Polled via timer. */
3239                 tw32_f(MAC_EVENT, 0);
3240         } else {
3241                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3242         }
3243         udelay(40);
3244
3245         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3246             current_link_up == 1 &&
3247             tp->link_config.active_speed == SPEED_1000 &&
3248             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3249              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3250                 udelay(120);
3251                 tw32_f(MAC_STATUS,
3252                      (MAC_STATUS_SYNC_CHANGED |
3253                       MAC_STATUS_CFG_CHANGED));
3254                 udelay(40);
3255                 tg3_write_mem(tp,
3256                               NIC_SRAM_FIRMWARE_MBOX,
3257                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3258         }
3259
3260         /* Prevent send BD corruption. */
3261         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3262                 u16 oldlnkctl, newlnkctl;
3263
3264                 pci_read_config_word(tp->pdev,
3265                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3266                                      &oldlnkctl);
3267                 if (tp->link_config.active_speed == SPEED_100 ||
3268                     tp->link_config.active_speed == SPEED_10)
3269                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3270                 else
3271                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3272                 if (newlnkctl != oldlnkctl)
3273                         pci_write_config_word(tp->pdev,
3274                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3275                                               newlnkctl);
3276         }
3277
3278         if (current_link_up != netif_carrier_ok(tp->dev)) {
3279                 if (current_link_up)
3280                         netif_carrier_on(tp->dev);
3281                 else
3282                         netif_carrier_off(tp->dev);
3283                 tg3_link_report(tp);
3284         }
3285
3286         return 0;
3287 }
3288
3289 struct tg3_fiber_aneginfo {
3290         int state;
3291 #define ANEG_STATE_UNKNOWN              0
3292 #define ANEG_STATE_AN_ENABLE            1
3293 #define ANEG_STATE_RESTART_INIT         2
3294 #define ANEG_STATE_RESTART              3
3295 #define ANEG_STATE_DISABLE_LINK_OK      4
3296 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3297 #define ANEG_STATE_ABILITY_DETECT       6
3298 #define ANEG_STATE_ACK_DETECT_INIT      7
3299 #define ANEG_STATE_ACK_DETECT           8
3300 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3301 #define ANEG_STATE_COMPLETE_ACK         10
3302 #define ANEG_STATE_IDLE_DETECT_INIT     11
3303 #define ANEG_STATE_IDLE_DETECT          12
3304 #define ANEG_STATE_LINK_OK              13
3305 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3306 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3307
3308         u32 flags;
3309 #define MR_AN_ENABLE            0x00000001
3310 #define MR_RESTART_AN           0x00000002
3311 #define MR_AN_COMPLETE          0x00000004
3312 #define MR_PAGE_RX              0x00000008
3313 #define MR_NP_LOADED            0x00000010
3314 #define MR_TOGGLE_TX            0x00000020
3315 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3316 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3317 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3318 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3319 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3320 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3321 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3322 #define MR_TOGGLE_RX            0x00002000
3323 #define MR_NP_RX                0x00004000
3324
3325 #define MR_LINK_OK              0x80000000
3326
3327         unsigned long link_time, cur_time;
3328
3329         u32 ability_match_cfg;
3330         int ability_match_count;
3331
3332         char ability_match, idle_match, ack_match;
3333
3334         u32 txconfig, rxconfig;
3335 #define ANEG_CFG_NP             0x00000080
3336 #define ANEG_CFG_ACK            0x00000040
3337 #define ANEG_CFG_RF2            0x00000020
3338 #define ANEG_CFG_RF1            0x00000010
3339 #define ANEG_CFG_PS2            0x00000001
3340 #define ANEG_CFG_PS1            0x00008000
3341 #define ANEG_CFG_HD             0x00004000
3342 #define ANEG_CFG_FD             0x00002000
3343 #define ANEG_CFG_INVAL          0x00001f06
3344
3345 };
3346 #define ANEG_OK         0
3347 #define ANEG_DONE       1
3348 #define ANEG_TIMER_ENAB 2
3349 #define ANEG_FAILED     -1
3350
3351 #define ANEG_STATE_SETTLE_TIME  10000
3352
3353 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3354                                    struct tg3_fiber_aneginfo *ap)
3355 {
3356         u16 flowctrl;
3357         unsigned long delta;
3358         u32 rx_cfg_reg;
3359         int ret;
3360
3361         if (ap->state == ANEG_STATE_UNKNOWN) {
3362                 ap->rxconfig = 0;
3363                 ap->link_time = 0;
3364                 ap->cur_time = 0;
3365                 ap->ability_match_cfg = 0;
3366                 ap->ability_match_count = 0;
3367                 ap->ability_match = 0;
3368                 ap->idle_match = 0;
3369                 ap->ack_match = 0;
3370         }
3371         ap->cur_time++;
3372
3373         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3374                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3375
3376                 if (rx_cfg_reg != ap->ability_match_cfg) {
3377                         ap->ability_match_cfg = rx_cfg_reg;
3378                         ap->ability_match = 0;
3379                         ap->ability_match_count = 0;
3380                 } else {
3381                         if (++ap->ability_match_count > 1) {
3382                                 ap->ability_match = 1;
3383                                 ap->ability_match_cfg = rx_cfg_reg;
3384                         }
3385                 }
3386                 if (rx_cfg_reg & ANEG_CFG_ACK)
3387                         ap->ack_match = 1;
3388                 else
3389                         ap->ack_match = 0;
3390
3391                 ap->idle_match = 0;
3392         } else {
3393                 ap->idle_match = 1;
3394                 ap->ability_match_cfg = 0;
3395                 ap->ability_match_count = 0;
3396                 ap->ability_match = 0;
3397                 ap->ack_match = 0;
3398
3399                 rx_cfg_reg = 0;
3400         }
3401
3402         ap->rxconfig = rx_cfg_reg;
3403         ret = ANEG_OK;
3404
3405         switch (ap->state) {
3406         case ANEG_STATE_UNKNOWN:
3407                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3408                         ap->state = ANEG_STATE_AN_ENABLE;
3409
3410                 /* fallthru */
3411         case ANEG_STATE_AN_ENABLE:
3412                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3413                 if (ap->flags & MR_AN_ENABLE) {
3414                         ap->link_time = 0;
3415                         ap->cur_time = 0;
3416                         ap->ability_match_cfg = 0;
3417                         ap->ability_match_count = 0;
3418                         ap->ability_match = 0;
3419                         ap->idle_match = 0;
3420                         ap->ack_match = 0;
3421
3422                         ap->state = ANEG_STATE_RESTART_INIT;
3423                 } else {
3424                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3425                 }
3426                 break;
3427
3428         case ANEG_STATE_RESTART_INIT:
3429                 ap->link_time = ap->cur_time;
3430                 ap->flags &= ~(MR_NP_LOADED);
3431                 ap->txconfig = 0;
3432                 tw32(MAC_TX_AUTO_NEG, 0);
3433                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3434                 tw32_f(MAC_MODE, tp->mac_mode);
3435                 udelay(40);
3436
3437                 ret = ANEG_TIMER_ENAB;
3438                 ap->state = ANEG_STATE_RESTART;
3439
3440                 /* fallthru */
3441         case ANEG_STATE_RESTART:
3442                 delta = ap->cur_time - ap->link_time;
3443                 if (delta > ANEG_STATE_SETTLE_TIME)
3444                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3445                 else
3446                         ret = ANEG_TIMER_ENAB;
3447                 break;
3448
3449         case ANEG_STATE_DISABLE_LINK_OK:
3450                 ret = ANEG_DONE;
3451                 break;
3452
3453         case ANEG_STATE_ABILITY_DETECT_INIT:
3454                 ap->flags &= ~(MR_TOGGLE_TX);
3455                 ap->txconfig = ANEG_CFG_FD;
3456                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3457                 if (flowctrl & ADVERTISE_1000XPAUSE)
3458                         ap->txconfig |= ANEG_CFG_PS1;
3459                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3460                         ap->txconfig |= ANEG_CFG_PS2;
3461                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3462                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3463                 tw32_f(MAC_MODE, tp->mac_mode);
3464                 udelay(40);
3465
3466                 ap->state = ANEG_STATE_ABILITY_DETECT;
3467                 break;
3468
3469         case ANEG_STATE_ABILITY_DETECT:
3470                 if (ap->ability_match != 0 && ap->rxconfig != 0)
3471                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3472                 break;
3473
3474         case ANEG_STATE_ACK_DETECT_INIT:
3475                 ap->txconfig |= ANEG_CFG_ACK;
3476                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3477                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3478                 tw32_f(MAC_MODE, tp->mac_mode);
3479                 udelay(40);
3480
3481                 ap->state = ANEG_STATE_ACK_DETECT;
3482
3483                 /* fallthru */
3484         case ANEG_STATE_ACK_DETECT:
3485                 if (ap->ack_match != 0) {
3486                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3487                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3488                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3489                         } else {
3490                                 ap->state = ANEG_STATE_AN_ENABLE;
3491                         }
3492                 } else if (ap->ability_match != 0 &&
3493                            ap->rxconfig == 0) {
3494                         ap->state = ANEG_STATE_AN_ENABLE;
3495                 }
3496                 break;
3497
3498         case ANEG_STATE_COMPLETE_ACK_INIT:
3499                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3500                         ret = ANEG_FAILED;
3501                         break;
3502                 }
3503                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3504                                MR_LP_ADV_HALF_DUPLEX |
3505                                MR_LP_ADV_SYM_PAUSE |
3506                                MR_LP_ADV_ASYM_PAUSE |
3507                                MR_LP_ADV_REMOTE_FAULT1 |
3508                                MR_LP_ADV_REMOTE_FAULT2 |
3509                                MR_LP_ADV_NEXT_PAGE |
3510                                MR_TOGGLE_RX |
3511                                MR_NP_RX);
3512                 if (ap->rxconfig & ANEG_CFG_FD)
3513                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3514                 if (ap->rxconfig & ANEG_CFG_HD)
3515                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3516                 if (ap->rxconfig & ANEG_CFG_PS1)
3517                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3518                 if (ap->rxconfig & ANEG_CFG_PS2)
3519                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3520                 if (ap->rxconfig & ANEG_CFG_RF1)
3521                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3522                 if (ap->rxconfig & ANEG_CFG_RF2)
3523                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3524                 if (ap->rxconfig & ANEG_CFG_NP)
3525                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3526
3527                 ap->link_time = ap->cur_time;
3528
3529                 ap->flags ^= (MR_TOGGLE_TX);
3530                 if (ap->rxconfig & 0x0008)
3531                         ap->flags |= MR_TOGGLE_RX;
3532                 if (ap->rxconfig & ANEG_CFG_NP)
3533                         ap->flags |= MR_NP_RX;
3534                 ap->flags |= MR_PAGE_RX;
3535
3536                 ap->state = ANEG_STATE_COMPLETE_ACK;
3537                 ret = ANEG_TIMER_ENAB;
3538                 break;
3539
3540         case ANEG_STATE_COMPLETE_ACK:
3541                 if (ap->ability_match != 0 &&
3542                     ap->rxconfig == 0) {
3543                         ap->state = ANEG_STATE_AN_ENABLE;
3544                         break;
3545                 }
3546                 delta = ap->cur_time - ap->link_time;
3547                 if (delta > ANEG_STATE_SETTLE_TIME) {
3548                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3549                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3550                         } else {
3551                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3552                                     !(ap->flags & MR_NP_RX)) {
3553                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3554                                 } else {
3555                                         ret = ANEG_FAILED;
3556                                 }
3557                         }
3558                 }
3559                 break;
3560
3561         case ANEG_STATE_IDLE_DETECT_INIT:
3562                 ap->link_time = ap->cur_time;
3563                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3564                 tw32_f(MAC_MODE, tp->mac_mode);
3565                 udelay(40);
3566
3567                 ap->state = ANEG_STATE_IDLE_DETECT;
3568                 ret = ANEG_TIMER_ENAB;
3569                 break;
3570
3571         case ANEG_STATE_IDLE_DETECT:
3572                 if (ap->ability_match != 0 &&
3573                     ap->rxconfig == 0) {
3574                         ap->state = ANEG_STATE_AN_ENABLE;
3575                         break;
3576                 }
3577                 delta = ap->cur_time - ap->link_time;
3578                 if (delta > ANEG_STATE_SETTLE_TIME) {
3579                         /* XXX another gem from the Broadcom driver :( */
3580                         ap->state = ANEG_STATE_LINK_OK;
3581                 }
3582                 break;
3583
3584         case ANEG_STATE_LINK_OK:
3585                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3586                 ret = ANEG_DONE;
3587                 break;
3588
3589         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3590                 /* ??? unimplemented */
3591                 break;
3592
3593         case ANEG_STATE_NEXT_PAGE_WAIT:
3594                 /* ??? unimplemented */
3595                 break;
3596
3597         default:
3598                 ret = ANEG_FAILED;
3599                 break;
3600         }
3601
3602         return ret;
3603 }
3604
3605 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3606 {
3607         int res = 0;
3608         struct tg3_fiber_aneginfo aninfo;
3609         int status = ANEG_FAILED;
3610         unsigned int tick;
3611         u32 tmp;
3612
3613         tw32_f(MAC_TX_AUTO_NEG, 0);
3614
3615         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3616         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3617         udelay(40);
3618
3619         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3620         udelay(40);
3621
3622         memset(&aninfo, 0, sizeof(aninfo));
3623         aninfo.flags |= MR_AN_ENABLE;
3624         aninfo.state = ANEG_STATE_UNKNOWN;
3625         aninfo.cur_time = 0;
3626         tick = 0;
3627         while (++tick < 195000) {
3628                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3629                 if (status == ANEG_DONE || status == ANEG_FAILED)
3630                         break;
3631
3632                 udelay(1);
3633         }
3634
3635         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3636         tw32_f(MAC_MODE, tp->mac_mode);
3637         udelay(40);
3638
3639         *txflags = aninfo.txconfig;
3640         *rxflags = aninfo.flags;
3641
3642         if (status == ANEG_DONE &&
3643             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3644                              MR_LP_ADV_FULL_DUPLEX)))
3645                 res = 1;
3646
3647         return res;
3648 }
3649
3650 static void tg3_init_bcm8002(struct tg3 *tp)
3651 {
3652         u32 mac_status = tr32(MAC_STATUS);
3653         int i;
3654
3655         /* Reset when initting first time or we have a link. */
3656         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3657             !(mac_status & MAC_STATUS_PCS_SYNCED))
3658                 return;
3659
3660         /* Set PLL lock range. */
3661         tg3_writephy(tp, 0x16, 0x8007);
3662
3663         /* SW reset */
3664         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3665
3666         /* Wait for reset to complete. */
3667         /* XXX schedule_timeout() ... */
3668         for (i = 0; i < 500; i++)
3669                 udelay(10);
3670
3671         /* Config mode; select PMA/Ch 1 regs. */
3672         tg3_writephy(tp, 0x10, 0x8411);
3673
3674         /* Enable auto-lock and comdet, select txclk for tx. */
3675         tg3_writephy(tp, 0x11, 0x0a10);
3676
3677         tg3_writephy(tp, 0x18, 0x00a0);
3678         tg3_writephy(tp, 0x16, 0x41ff);
3679
3680         /* Assert and deassert POR. */
3681         tg3_writephy(tp, 0x13, 0x0400);
3682         udelay(40);
3683         tg3_writephy(tp, 0x13, 0x0000);
3684
3685         tg3_writephy(tp, 0x11, 0x0a50);
3686         udelay(40);
3687         tg3_writephy(tp, 0x11, 0x0a10);
3688
3689         /* Wait for signal to stabilize */
3690         /* XXX schedule_timeout() ... */
3691         for (i = 0; i < 15000; i++)
3692                 udelay(10);
3693
3694         /* Deselect the channel register so we can read the PHYID
3695          * later.
3696          */
3697         tg3_writephy(tp, 0x10, 0x8011);
3698 }
3699
3700 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3701 {
3702         u16 flowctrl;
3703         u32 sg_dig_ctrl, sg_dig_status;
3704         u32 serdes_cfg, expected_sg_dig_ctrl;
3705         int workaround, port_a;
3706         int current_link_up;
3707
3708         serdes_cfg = 0;
3709         expected_sg_dig_ctrl = 0;
3710         workaround = 0;
3711         port_a = 1;
3712         current_link_up = 0;
3713
3714         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3715             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3716                 workaround = 1;
3717                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3718                         port_a = 0;
3719
3720                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3721                 /* preserve bits 20-23 for voltage regulator */
3722                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3723         }
3724
3725         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3726
3727         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3728                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3729                         if (workaround) {
3730                                 u32 val = serdes_cfg;
3731
3732                                 if (port_a)
3733                                         val |= 0xc010000;
3734                                 else
3735                                         val |= 0x4010000;
3736                                 tw32_f(MAC_SERDES_CFG, val);
3737                         }
3738
3739                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3740                 }
3741                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3742                         tg3_setup_flow_control(tp, 0, 0);
3743                         current_link_up = 1;
3744                 }
3745                 goto out;
3746         }
3747
3748         /* Want auto-negotiation.  */
3749         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3750
3751         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3752         if (flowctrl & ADVERTISE_1000XPAUSE)
3753                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3754         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3755                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3756
3757         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3758                 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3759                     tp->serdes_counter &&
3760                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3761                                     MAC_STATUS_RCVD_CFG)) ==
3762                      MAC_STATUS_PCS_SYNCED)) {
3763                         tp->serdes_counter--;
3764                         current_link_up = 1;
3765                         goto out;
3766                 }
3767 restart_autoneg:
3768                 if (workaround)
3769                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3770                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3771                 udelay(5);
3772                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3773
3774                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3775                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3776         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3777                                  MAC_STATUS_SIGNAL_DET)) {
3778                 sg_dig_status = tr32(SG_DIG_STATUS);
3779                 mac_status = tr32(MAC_STATUS);
3780
3781                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3782                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3783                         u32 local_adv = 0, remote_adv = 0;
3784
3785                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3786                                 local_adv |= ADVERTISE_1000XPAUSE;
3787                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3788                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3789
3790                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3791                                 remote_adv |= LPA_1000XPAUSE;
3792                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3793                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3794
3795                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3796                         current_link_up = 1;
3797                         tp->serdes_counter = 0;
3798                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3799                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3800                         if (tp->serdes_counter)
3801                                 tp->serdes_counter--;
3802                         else {
3803                                 if (workaround) {
3804                                         u32 val = serdes_cfg;
3805
3806                                         if (port_a)
3807                                                 val |= 0xc010000;
3808                                         else
3809                                                 val |= 0x4010000;
3810
3811                                         tw32_f(MAC_SERDES_CFG, val);
3812                                 }
3813
3814                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3815                                 udelay(40);
3816
3817                                 /* Link parallel detection - link is up */
3818                                 /* only if we have PCS_SYNC and not */
3819                                 /* receiving config code words */
3820                                 mac_status = tr32(MAC_STATUS);
3821                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3822                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3823                                         tg3_setup_flow_control(tp, 0, 0);
3824                                         current_link_up = 1;
3825                                         tp->phy_flags |=
3826                                                 TG3_PHYFLG_PARALLEL_DETECT;
3827                                         tp->serdes_counter =
3828                                                 SERDES_PARALLEL_DET_TIMEOUT;
3829                                 } else
3830                                         goto restart_autoneg;
3831                         }
3832                 }
3833         } else {
3834                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3835                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3836         }
3837
3838 out:
3839         return current_link_up;
3840 }
3841
3842 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3843 {
3844         int current_link_up = 0;
3845
3846         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3847                 goto out;
3848
3849         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3850                 u32 txflags, rxflags;
3851                 int i;
3852
3853                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3854                         u32 local_adv = 0, remote_adv = 0;
3855
3856                         if (txflags & ANEG_CFG_PS1)
3857                                 local_adv |= ADVERTISE_1000XPAUSE;
3858                         if (txflags & ANEG_CFG_PS2)
3859                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3860
3861                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3862                                 remote_adv |= LPA_1000XPAUSE;
3863                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3864                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3865
3866                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3867
3868                         current_link_up = 1;
3869                 }
3870                 for (i = 0; i < 30; i++) {
3871                         udelay(20);
3872                         tw32_f(MAC_STATUS,
3873                                (MAC_STATUS_SYNC_CHANGED |
3874                                 MAC_STATUS_CFG_CHANGED));
3875                         udelay(40);
3876                         if ((tr32(MAC_STATUS) &
3877                              (MAC_STATUS_SYNC_CHANGED |
3878                               MAC_STATUS_CFG_CHANGED)) == 0)
3879                                 break;
3880                 }
3881
3882                 mac_status = tr32(MAC_STATUS);
3883                 if (current_link_up == 0 &&
3884                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3885                     !(mac_status & MAC_STATUS_RCVD_CFG))
3886                         current_link_up = 1;
3887         } else {
3888                 tg3_setup_flow_control(tp, 0, 0);
3889
3890                 /* Forcing 1000FD link up. */
3891                 current_link_up = 1;
3892
3893                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3894                 udelay(40);
3895
3896                 tw32_f(MAC_MODE, tp->mac_mode);
3897                 udelay(40);
3898         }
3899
3900 out:
3901         return current_link_up;
3902 }
3903
3904 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3905 {
3906         u32 orig_pause_cfg;
3907         u16 orig_active_speed;
3908         u8 orig_active_duplex;
3909         u32 mac_status;
3910         int current_link_up;
3911         int i;
3912
3913         orig_pause_cfg = tp->link_config.active_flowctrl;
3914         orig_active_speed = tp->link_config.active_speed;
3915         orig_active_duplex = tp->link_config.active_duplex;
3916
3917         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3918             netif_carrier_ok(tp->dev) &&
3919             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3920                 mac_status = tr32(MAC_STATUS);
3921                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3922                                MAC_STATUS_SIGNAL_DET |
3923                                MAC_STATUS_CFG_CHANGED |
3924                                MAC_STATUS_RCVD_CFG);
3925                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3926                                    MAC_STATUS_SIGNAL_DET)) {
3927                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3928                                             MAC_STATUS_CFG_CHANGED));
3929                         return 0;
3930                 }
3931         }
3932
3933         tw32_f(MAC_TX_AUTO_NEG, 0);
3934
3935         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3936         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3937         tw32_f(MAC_MODE, tp->mac_mode);
3938         udelay(40);
3939
3940         if (tp->phy_id == TG3_PHY_ID_BCM8002)
3941                 tg3_init_bcm8002(tp);
3942
3943         /* Enable link change event even when serdes polling.  */
3944         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3945         udelay(40);
3946
3947         current_link_up = 0;
3948         mac_status = tr32(MAC_STATUS);
3949
3950         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3951                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3952         else
3953                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3954
3955         tp->napi[0].hw_status->status =
3956                 (SD_STATUS_UPDATED |
3957                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3958
3959         for (i = 0; i < 100; i++) {
3960                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3961                                     MAC_STATUS_CFG_CHANGED));
3962                 udelay(5);
3963                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3964                                          MAC_STATUS_CFG_CHANGED |
3965                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3966                         break;
3967         }
3968
3969         mac_status = tr32(MAC_STATUS);
3970         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3971                 current_link_up = 0;
3972                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3973                     tp->serdes_counter == 0) {
3974                         tw32_f(MAC_MODE, (tp->mac_mode |
3975                                           MAC_MODE_SEND_CONFIGS));
3976                         udelay(1);
3977                         tw32_f(MAC_MODE, tp->mac_mode);
3978                 }
3979         }
3980
3981         if (current_link_up == 1) {
3982                 tp->link_config.active_speed = SPEED_1000;
3983                 tp->link_config.active_duplex = DUPLEX_FULL;
3984                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3985                                     LED_CTRL_LNKLED_OVERRIDE |
3986                                     LED_CTRL_1000MBPS_ON));
3987         } else {
3988                 tp->link_config.active_speed = SPEED_INVALID;
3989                 tp->link_config.active_duplex = DUPLEX_INVALID;
3990                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3991                                     LED_CTRL_LNKLED_OVERRIDE |
3992                                     LED_CTRL_TRAFFIC_OVERRIDE));
3993         }
3994
3995         if (current_link_up != netif_carrier_ok(tp->dev)) {
3996                 if (current_link_up)
3997                         netif_carrier_on(tp->dev);
3998                 else
3999                         netif_carrier_off(tp->dev);
4000                 tg3_link_report(tp);
4001         } else {
4002                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4003                 if (orig_pause_cfg != now_pause_cfg ||
4004                     orig_active_speed != tp->link_config.active_speed ||
4005                     orig_active_duplex != tp->link_config.active_duplex)
4006                         tg3_link_report(tp);
4007         }
4008
4009         return 0;
4010 }
4011
4012 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4013 {
4014         int current_link_up, err = 0;
4015         u32 bmsr, bmcr;
4016         u16 current_speed;
4017         u8 current_duplex;
4018         u32 local_adv, remote_adv;
4019
4020         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4021         tw32_f(MAC_MODE, tp->mac_mode);
4022         udelay(40);
4023
4024         tw32(MAC_EVENT, 0);
4025
4026         tw32_f(MAC_STATUS,
4027              (MAC_STATUS_SYNC_CHANGED |
4028               MAC_STATUS_CFG_CHANGED |
4029               MAC_STATUS_MI_COMPLETION |
4030               MAC_STATUS_LNKSTATE_CHANGED));
4031         udelay(40);
4032
4033         if (force_reset)
4034                 tg3_phy_reset(tp);
4035
4036         current_link_up = 0;
4037         current_speed = SPEED_INVALID;
4038         current_duplex = DUPLEX_INVALID;
4039
4040         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4041         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4042         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4043                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4044                         bmsr |= BMSR_LSTATUS;
4045                 else
4046                         bmsr &= ~BMSR_LSTATUS;
4047         }
4048
4049         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4050
4051         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4052             (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4053                 /* do nothing, just check for link up at the end */
4054         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4055                 u32 adv, new_adv;
4056
4057                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4058                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4059                                   ADVERTISE_1000XPAUSE |
4060                                   ADVERTISE_1000XPSE_ASYM |
4061                                   ADVERTISE_SLCT);
4062
4063                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4064
4065                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4066                         new_adv |= ADVERTISE_1000XHALF;
4067                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4068                         new_adv |= ADVERTISE_1000XFULL;
4069
4070                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4071                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4072                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4073                         tg3_writephy(tp, MII_BMCR, bmcr);
4074
4075                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4076                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4077                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4078
4079                         return err;
4080                 }
4081         } else {
4082                 u32 new_bmcr;
4083
4084                 bmcr &= ~BMCR_SPEED1000;
4085                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4086
4087                 if (tp->link_config.duplex == DUPLEX_FULL)
4088                         new_bmcr |= BMCR_FULLDPLX;
4089
4090                 if (new_bmcr != bmcr) {
4091                         /* BMCR_SPEED1000 is a reserved bit that needs
4092                          * to be set on write.
4093                          */
4094                         new_bmcr |= BMCR_SPEED1000;
4095
4096                         /* Force a linkdown */
4097                         if (netif_carrier_ok(tp->dev)) {
4098                                 u32 adv;
4099
4100                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4101                                 adv &= ~(ADVERTISE_1000XFULL |
4102                                          ADVERTISE_1000XHALF |
4103                                          ADVERTISE_SLCT);
4104                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4105                                 tg3_writephy(tp, MII_BMCR, bmcr |
4106                                                            BMCR_ANRESTART |
4107                                                            BMCR_ANENABLE);
4108                                 udelay(10);
4109                                 netif_carrier_off(tp->dev);
4110                         }
4111                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4112                         bmcr = new_bmcr;
4113                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4114                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4115                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4116                             ASIC_REV_5714) {
4117                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4118                                         bmsr |= BMSR_LSTATUS;
4119                                 else
4120                                         bmsr &= ~BMSR_LSTATUS;
4121                         }
4122                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4123                 }
4124         }
4125
4126         if (bmsr & BMSR_LSTATUS) {
4127                 current_speed = SPEED_1000;
4128                 current_link_up = 1;
4129                 if (bmcr & BMCR_FULLDPLX)
4130                         current_duplex = DUPLEX_FULL;
4131                 else
4132                         current_duplex = DUPLEX_HALF;
4133
4134                 local_adv = 0;
4135                 remote_adv = 0;
4136
4137                 if (bmcr & BMCR_ANENABLE) {
4138                         u32 common;
4139
4140                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4141                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4142                         common = local_adv & remote_adv;
4143                         if (common & (ADVERTISE_1000XHALF |
4144                                       ADVERTISE_1000XFULL)) {
4145                                 if (common & ADVERTISE_1000XFULL)
4146                                         current_duplex = DUPLEX_FULL;
4147                                 else
4148                                         current_duplex = DUPLEX_HALF;
4149                         } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4150                                 /* Link is up via parallel detect */
4151                         } else {
4152                                 current_link_up = 0;
4153                         }
4154                 }
4155         }
4156
4157         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4158                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4159
4160         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4161         if (tp->link_config.active_duplex == DUPLEX_HALF)
4162                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4163
4164         tw32_f(MAC_MODE, tp->mac_mode);
4165         udelay(40);
4166
4167         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4168
4169         tp->link_config.active_speed = current_speed;
4170         tp->link_config.active_duplex = current_duplex;
4171
4172         if (current_link_up != netif_carrier_ok(tp->dev)) {
4173                 if (current_link_up)
4174                         netif_carrier_on(tp->dev);
4175                 else {
4176                         netif_carrier_off(tp->dev);
4177                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4178                 }
4179                 tg3_link_report(tp);
4180         }
4181         return err;
4182 }
4183
4184 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4185 {
4186         if (tp->serdes_counter) {
4187                 /* Give autoneg time to complete. */
4188                 tp->serdes_counter--;
4189                 return;
4190         }
4191
4192         if (!netif_carrier_ok(tp->dev) &&
4193             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4194                 u32 bmcr;
4195
4196                 tg3_readphy(tp, MII_BMCR, &bmcr);
4197                 if (bmcr & BMCR_ANENABLE) {
4198                         u32 phy1, phy2;
4199
4200                         /* Select shadow register 0x1f */
4201                         tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
4202                         tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
4203
4204                         /* Select expansion interrupt status register */
4205                         tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4206                                          MII_TG3_DSP_EXP1_INT_STAT);
4207                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4208                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4209
4210                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4211                                 /* We have signal detect and not receiving
4212                                  * config code words, link is up by parallel
4213                                  * detection.
4214                                  */
4215
4216                                 bmcr &= ~BMCR_ANENABLE;
4217                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4218                                 tg3_writephy(tp, MII_BMCR, bmcr);
4219                                 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
4220                         }
4221                 }
4222         } else if (netif_carrier_ok(tp->dev) &&
4223                    (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4224                    (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4225                 u32 phy2;
4226
4227                 /* Select expansion interrupt status register */
4228                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4229                                  MII_TG3_DSP_EXP1_INT_STAT);
4230                 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4231                 if (phy2 & 0x20) {
4232                         u32 bmcr;
4233
4234                         /* Config code words received, turn on autoneg. */
4235                         tg3_readphy(tp, MII_BMCR, &bmcr);
4236                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4237
4238                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4239
4240                 }
4241         }
4242 }
4243
4244 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4245 {
4246         int err;
4247
4248         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
4249                 err = tg3_setup_fiber_phy(tp, force_reset);
4250         else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4251                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4252         else
4253                 err = tg3_setup_copper_phy(tp, force_reset);
4254
4255         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4256                 u32 val, scale;
4257
4258                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4259                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4260                         scale = 65;
4261                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4262                         scale = 6;
4263                 else
4264                         scale = 12;
4265
4266                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4267                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4268                 tw32(GRC_MISC_CFG, val);
4269         }
4270
4271         if (tp->link_config.active_speed == SPEED_1000 &&
4272             tp->link_config.active_duplex == DUPLEX_HALF)
4273                 tw32(MAC_TX_LENGTHS,
4274                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4275                       (6 << TX_LENGTHS_IPG_SHIFT) |
4276                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4277         else
4278                 tw32(MAC_TX_LENGTHS,
4279                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4280                       (6 << TX_LENGTHS_IPG_SHIFT) |
4281                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4282
4283         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4284                 if (netif_carrier_ok(tp->dev)) {
4285                         tw32(HOSTCC_STAT_COAL_TICKS,
4286                              tp->coal.stats_block_coalesce_usecs);
4287                 } else {
4288                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4289                 }
4290         }
4291
4292         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4293                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4294                 if (!netif_carrier_ok(tp->dev))
4295                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4296                               tp->pwrmgmt_thresh;
4297                 else
4298                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4299                 tw32(PCIE_PWR_MGMT_THRESH, val);
4300         }
4301
4302         return err;
4303 }
4304
4305 static inline int tg3_irq_sync(struct tg3 *tp)
4306 {
4307         return tp->irq_sync;
4308 }
4309
4310 /* This is called whenever we suspect that the system chipset is re-
4311  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4312  * is bogus tx completions. We try to recover by setting the
4313  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4314  * in the workqueue.
4315  */
4316 static void tg3_tx_recover(struct tg3 *tp)
4317 {
4318         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4319                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4320
4321         netdev_warn(tp->dev,
4322                     "The system may be re-ordering memory-mapped I/O "
4323                     "cycles to the network device, attempting to recover. "
4324                     "Please report the problem to the driver maintainer "
4325                     "and include system chipset information.\n");
4326
4327         spin_lock(&tp->lock);
4328         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4329         spin_unlock(&tp->lock);
4330 }
4331
4332 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4333 {
4334         /* Tell compiler to fetch tx indices from memory. */
4335         barrier();
4336         return tnapi->tx_pending -
4337                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4338 }
4339
4340 /* Tigon3 never reports partial packet sends.  So we do not
4341  * need special logic to handle SKBs that have not had all
4342  * of their frags sent yet, like SunGEM does.
4343  */
4344 static void tg3_tx(struct tg3_napi *tnapi)
4345 {
4346         struct tg3 *tp = tnapi->tp;
4347         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4348         u32 sw_idx = tnapi->tx_cons;
4349         struct netdev_queue *txq;
4350         int index = tnapi - tp->napi;
4351
4352         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4353                 index--;
4354
4355         txq = netdev_get_tx_queue(tp->dev, index);
4356
4357         while (sw_idx != hw_idx) {
4358                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4359                 struct sk_buff *skb = ri->skb;
4360                 int i, tx_bug = 0;
4361
4362                 if (unlikely(skb == NULL)) {
4363                         tg3_tx_recover(tp);
4364                         return;
4365                 }
4366
4367                 pci_unmap_single(tp->pdev,
4368                                  dma_unmap_addr(ri, mapping),
4369                                  skb_headlen(skb),
4370                                  PCI_DMA_TODEVICE);
4371
4372                 ri->skb = NULL;
4373
4374                 sw_idx = NEXT_TX(sw_idx);
4375
4376                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4377                         ri = &tnapi->tx_buffers[sw_idx];
4378                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4379                                 tx_bug = 1;
4380
4381                         pci_unmap_page(tp->pdev,
4382                                        dma_unmap_addr(ri, mapping),
4383                                        skb_shinfo(skb)->frags[i].size,
4384                                        PCI_DMA_TODEVICE);
4385                         sw_idx = NEXT_TX(sw_idx);
4386                 }
4387
4388                 dev_kfree_skb(skb);
4389
4390                 if (unlikely(tx_bug)) {
4391                         tg3_tx_recover(tp);
4392                         return;
4393                 }
4394         }
4395
4396         tnapi->tx_cons = sw_idx;
4397
4398         /* Need to make the tx_cons update visible to tg3_start_xmit()
4399          * before checking for netif_queue_stopped().  Without the
4400          * memory barrier, there is a small possibility that tg3_start_xmit()
4401          * will miss it and cause the queue to be stopped forever.
4402          */
4403         smp_mb();
4404
4405         if (unlikely(netif_tx_queue_stopped(txq) &&
4406                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4407                 __netif_tx_lock(txq, smp_processor_id());
4408                 if (netif_tx_queue_stopped(txq) &&
4409                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4410                         netif_tx_wake_queue(txq);
4411                 __netif_tx_unlock(txq);
4412         }
4413 }
4414
4415 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4416 {
4417         if (!ri->skb)
4418                 return;
4419
4420         pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4421                          map_sz, PCI_DMA_FROMDEVICE);
4422         dev_kfree_skb_any(ri->skb);
4423         ri->skb = NULL;
4424 }
4425
4426 /* Returns size of skb allocated or < 0 on error.
4427  *
4428  * We only need to fill in the address because the other members
4429  * of the RX descriptor are invariant, see tg3_init_rings.
4430  *
4431  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4432  * posting buffers we only dirty the first cache line of the RX
4433  * descriptor (containing the address).  Whereas for the RX status
4434  * buffers the cpu only reads the last cacheline of the RX descriptor
4435  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4436  */
4437 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4438                             u32 opaque_key, u32 dest_idx_unmasked)
4439 {
4440         struct tg3_rx_buffer_desc *desc;
4441         struct ring_info *map, *src_map;
4442         struct sk_buff *skb;
4443         dma_addr_t mapping;
4444         int skb_size, dest_idx;
4445
4446         src_map = NULL;
4447         switch (opaque_key) {
4448         case RXD_OPAQUE_RING_STD:
4449                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4450                 desc = &tpr->rx_std[dest_idx];
4451                 map = &tpr->rx_std_buffers[dest_idx];
4452                 skb_size = tp->rx_pkt_map_sz;
4453                 break;
4454
4455         case RXD_OPAQUE_RING_JUMBO:
4456                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4457                 desc = &tpr->rx_jmb[dest_idx].std;
4458                 map = &tpr->rx_jmb_buffers[dest_idx];
4459                 skb_size = TG3_RX_JMB_MAP_SZ;
4460                 break;
4461
4462         default:
4463                 return -EINVAL;
4464         }
4465
4466         /* Do not overwrite any of the map or rp information
4467          * until we are sure we can commit to a new buffer.
4468          *
4469          * Callers depend upon this behavior and assume that
4470          * we leave everything unchanged if we fail.
4471          */
4472         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4473         if (skb == NULL)
4474                 return -ENOMEM;
4475
4476         skb_reserve(skb, tp->rx_offset);
4477
4478         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4479                                  PCI_DMA_FROMDEVICE);
4480         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4481                 dev_kfree_skb(skb);
4482                 return -EIO;
4483         }
4484
4485         map->skb = skb;
4486         dma_unmap_addr_set(map, mapping, mapping);
4487
4488         desc->addr_hi = ((u64)mapping >> 32);
4489         desc->addr_lo = ((u64)mapping & 0xffffffff);
4490
4491         return skb_size;
4492 }
4493
4494 /* We only need to move over in the address because the other
4495  * members of the RX descriptor are invariant.  See notes above
4496  * tg3_alloc_rx_skb for full details.
4497  */
4498 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4499                            struct tg3_rx_prodring_set *dpr,
4500                            u32 opaque_key, int src_idx,
4501                            u32 dest_idx_unmasked)
4502 {
4503         struct tg3 *tp = tnapi->tp;
4504         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4505         struct ring_info *src_map, *dest_map;
4506         struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
4507         int dest_idx;
4508
4509         switch (opaque_key) {
4510         case RXD_OPAQUE_RING_STD:
4511                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4512                 dest_desc = &dpr->rx_std[dest_idx];
4513                 dest_map = &dpr->rx_std_buffers[dest_idx];
4514                 src_desc = &spr->rx_std[src_idx];
4515                 src_map = &spr->rx_std_buffers[src_idx];
4516                 break;
4517
4518         case RXD_OPAQUE_RING_JUMBO:
4519                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4520                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4521                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4522                 src_desc = &spr->rx_jmb[src_idx].std;
4523                 src_map = &spr->rx_jmb_buffers[src_idx];
4524                 break;
4525
4526         default:
4527                 return;
4528         }
4529
4530         dest_map->skb = src_map->skb;
4531         dma_unmap_addr_set(dest_map, mapping,
4532                            dma_unmap_addr(src_map, mapping));
4533         dest_desc->addr_hi = src_desc->addr_hi;
4534         dest_desc->addr_lo = src_desc->addr_lo;
4535
4536         /* Ensure that the update to the skb happens after the physical
4537          * addresses have been transferred to the new BD location.
4538          */
4539         smp_wmb();
4540
4541         src_map->skb = NULL;
4542 }
4543
4544 /* The RX ring scheme is composed of multiple rings which post fresh
4545  * buffers to the chip, and one special ring the chip uses to report
4546  * status back to the host.
4547  *
4548  * The special ring reports the status of received packets to the
4549  * host.  The chip does not write into the original descriptor the
4550  * RX buffer was obtained from.  The chip simply takes the original
4551  * descriptor as provided by the host, updates the status and length
4552  * field, then writes this into the next status ring entry.
4553  *
4554  * Each ring the host uses to post buffers to the chip is described
4555  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4556  * it is first placed into the on-chip ram.  When the packet's length
4557  * is known, it walks down the TG3_BDINFO entries to select the ring.
4558  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4559  * which is within the range of the new packet's length is chosen.
4560  *
4561  * The "separate ring for rx status" scheme may sound queer, but it makes
4562  * sense from a cache coherency perspective.  If only the host writes
4563  * to the buffer post rings, and only the chip writes to the rx status
4564  * rings, then cache lines never move beyond shared-modified state.
4565  * If both the host and chip were to write into the same ring, cache line
4566  * eviction could occur since both entities want it in an exclusive state.
4567  */
4568 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4569 {
4570         struct tg3 *tp = tnapi->tp;
4571         u32 work_mask, rx_std_posted = 0;
4572         u32 std_prod_idx, jmb_prod_idx;
4573         u32 sw_idx = tnapi->rx_rcb_ptr;
4574         u16 hw_idx;
4575         int received;
4576         struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
4577
4578         hw_idx = *(tnapi->rx_rcb_prod_idx);
4579         /*
4580          * We need to order the read of hw_idx and the read of
4581          * the opaque cookie.
4582          */
4583         rmb();
4584         work_mask = 0;
4585         received = 0;
4586         std_prod_idx = tpr->rx_std_prod_idx;
4587         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4588         while (sw_idx != hw_idx && budget > 0) {
4589                 struct ring_info *ri;
4590                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4591                 unsigned int len;
4592                 struct sk_buff *skb;
4593                 dma_addr_t dma_addr;
4594                 u32 opaque_key, desc_idx, *post_ptr;
4595                 bool hw_vlan __maybe_unused = false;
4596                 u16 vtag __maybe_unused = 0;
4597
4598                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4599                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4600                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4601                         ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4602                         dma_addr = dma_unmap_addr(ri, mapping);
4603                         skb = ri->skb;
4604                         post_ptr = &std_prod_idx;
4605                         rx_std_posted++;
4606                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4607                         ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4608                         dma_addr = dma_unmap_addr(ri, mapping);
4609                         skb = ri->skb;
4610                         post_ptr = &jmb_prod_idx;
4611                 } else
4612                         goto next_pkt_nopost;
4613
4614                 work_mask |= opaque_key;
4615
4616                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4617                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4618                 drop_it:
4619                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4620                                        desc_idx, *post_ptr);
4621                 drop_it_no_recycle:
4622                         /* Other statistics kept track of by card. */
4623                         tp->net_stats.rx_dropped++;
4624                         goto next_pkt;
4625                 }
4626
4627                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4628                       ETH_FCS_LEN;
4629
4630                 if (len > TG3_RX_COPY_THRESH(tp)) {
4631                         int skb_size;
4632
4633                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4634                                                     *post_ptr);
4635                         if (skb_size < 0)
4636                                 goto drop_it;
4637
4638                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4639                                          PCI_DMA_FROMDEVICE);
4640
4641                         /* Ensure that the update to the skb happens
4642                          * after the usage of the old DMA mapping.
4643                          */
4644                         smp_wmb();
4645
4646                         ri->skb = NULL;
4647
4648                         skb_put(skb, len);
4649                 } else {
4650                         struct sk_buff *copy_skb;
4651
4652                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4653                                        desc_idx, *post_ptr);
4654
4655                         copy_skb = netdev_alloc_skb(tp->dev, len + VLAN_HLEN +
4656                                                     TG3_RAW_IP_ALIGN);
4657                         if (copy_skb == NULL)
4658                                 goto drop_it_no_recycle;
4659
4660                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN + VLAN_HLEN);
4661                         skb_put(copy_skb, len);
4662                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4663                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4664                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4665
4666                         /* We'll reuse the original ring buffer. */
4667                         skb = copy_skb;
4668                 }
4669
4670                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4671                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4672                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4673                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4674                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4675                 else
4676                         skb_checksum_none_assert(skb);
4677
4678                 skb->protocol = eth_type_trans(skb, tp->dev);
4679
4680                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4681                     skb->protocol != htons(ETH_P_8021Q)) {
4682                         dev_kfree_skb(skb);
4683                         goto next_pkt;
4684                 }
4685
4686                 if (desc->type_flags & RXD_FLAG_VLAN &&
4687                     !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) {
4688                         vtag = desc->err_vlan & RXD_VLAN_MASK;
4689 #if TG3_VLAN_TAG_USED
4690                         if (tp->vlgrp)
4691                                 hw_vlan = true;
4692                         else
4693 #endif
4694                         {
4695                                 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
4696                                                     __skb_push(skb, VLAN_HLEN);
4697
4698                                 memmove(ve, skb->data + VLAN_HLEN,
4699                                         ETH_ALEN * 2);
4700                                 ve->h_vlan_proto = htons(ETH_P_8021Q);
4701                                 ve->h_vlan_TCI = htons(vtag);
4702                         }
4703                 }
4704
4705 #if TG3_VLAN_TAG_USED
4706                 if (hw_vlan)
4707                         vlan_gro_receive(&tnapi->napi, tp->vlgrp, vtag, skb);
4708                 else
4709 #endif
4710                         napi_gro_receive(&tnapi->napi, skb);
4711
4712                 received++;
4713                 budget--;
4714
4715 next_pkt:
4716                 (*post_ptr)++;
4717
4718                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4719                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4720                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4721                                      tpr->rx_std_prod_idx);
4722                         work_mask &= ~RXD_OPAQUE_RING_STD;
4723                         rx_std_posted = 0;
4724                 }
4725 next_pkt_nopost:
4726                 sw_idx++;
4727                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4728
4729                 /* Refresh hw_idx to see if there is new work */
4730                 if (sw_idx == hw_idx) {
4731                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4732                         rmb();
4733                 }
4734         }
4735
4736         /* ACK the status ring. */
4737         tnapi->rx_rcb_ptr = sw_idx;
4738         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4739
4740         /* Refill RX ring(s). */
4741         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4742                 if (work_mask & RXD_OPAQUE_RING_STD) {
4743                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4744                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4745                                      tpr->rx_std_prod_idx);
4746                 }
4747                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4748                         tpr->rx_jmb_prod_idx = jmb_prod_idx %
4749                                                TG3_RX_JUMBO_RING_SIZE;
4750                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4751                                      tpr->rx_jmb_prod_idx);
4752                 }
4753                 mmiowb();
4754         } else if (work_mask) {
4755                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4756                  * updated before the producer indices can be updated.
4757                  */
4758                 smp_wmb();
4759
4760                 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4761                 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
4762
4763                 if (tnapi != &tp->napi[1])
4764                         napi_schedule(&tp->napi[1].napi);
4765         }
4766
4767         return received;
4768 }
4769
4770 static void tg3_poll_link(struct tg3 *tp)
4771 {
4772         /* handle link change and other phy events */
4773         if (!(tp->tg3_flags &
4774               (TG3_FLAG_USE_LINKCHG_REG |
4775                TG3_FLAG_POLL_SERDES))) {
4776                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4777
4778                 if (sblk->status & SD_STATUS_LINK_CHG) {
4779                         sblk->status = SD_STATUS_UPDATED |
4780                                        (sblk->status & ~SD_STATUS_LINK_CHG);
4781                         spin_lock(&tp->lock);
4782                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4783                                 tw32_f(MAC_STATUS,
4784                                      (MAC_STATUS_SYNC_CHANGED |
4785                                       MAC_STATUS_CFG_CHANGED |
4786                                       MAC_STATUS_MI_COMPLETION |
4787                                       MAC_STATUS_LNKSTATE_CHANGED));
4788                                 udelay(40);
4789                         } else
4790                                 tg3_setup_phy(tp, 0);
4791                         spin_unlock(&tp->lock);
4792                 }
4793         }
4794 }
4795
4796 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4797                                 struct tg3_rx_prodring_set *dpr,
4798                                 struct tg3_rx_prodring_set *spr)
4799 {
4800         u32 si, di, cpycnt, src_prod_idx;
4801         int i, err = 0;
4802
4803         while (1) {
4804                 src_prod_idx = spr->rx_std_prod_idx;
4805
4806                 /* Make sure updates to the rx_std_buffers[] entries and the
4807                  * standard producer index are seen in the correct order.
4808                  */
4809                 smp_rmb();
4810
4811                 if (spr->rx_std_cons_idx == src_prod_idx)
4812                         break;
4813
4814                 if (spr->rx_std_cons_idx < src_prod_idx)
4815                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4816                 else
4817                         cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4818
4819                 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4820
4821                 si = spr->rx_std_cons_idx;
4822                 di = dpr->rx_std_prod_idx;
4823
4824                 for (i = di; i < di + cpycnt; i++) {
4825                         if (dpr->rx_std_buffers[i].skb) {
4826                                 cpycnt = i - di;
4827                                 err = -ENOSPC;
4828                                 break;
4829                         }
4830                 }
4831
4832                 if (!cpycnt)
4833                         break;
4834
4835                 /* Ensure that updates to the rx_std_buffers ring and the
4836                  * shadowed hardware producer ring from tg3_recycle_skb() are
4837                  * ordered correctly WRT the skb check above.
4838                  */
4839                 smp_rmb();
4840
4841                 memcpy(&dpr->rx_std_buffers[di],
4842                        &spr->rx_std_buffers[si],
4843                        cpycnt * sizeof(struct ring_info));
4844
4845                 for (i = 0; i < cpycnt; i++, di++, si++) {
4846                         struct tg3_rx_buffer_desc *sbd, *dbd;
4847                         sbd = &spr->rx_std[si];
4848                         dbd = &dpr->rx_std[di];
4849                         dbd->addr_hi = sbd->addr_hi;
4850                         dbd->addr_lo = sbd->addr_lo;
4851                 }
4852
4853                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4854                                        TG3_RX_RING_SIZE;
4855                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4856                                        TG3_RX_RING_SIZE;
4857         }
4858
4859         while (1) {
4860                 src_prod_idx = spr->rx_jmb_prod_idx;
4861
4862                 /* Make sure updates to the rx_jmb_buffers[] entries and
4863                  * the jumbo producer index are seen in the correct order.
4864                  */
4865                 smp_rmb();
4866
4867                 if (spr->rx_jmb_cons_idx == src_prod_idx)
4868                         break;
4869
4870                 if (spr->rx_jmb_cons_idx < src_prod_idx)
4871                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4872                 else
4873                         cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4874
4875                 cpycnt = min(cpycnt,
4876                              TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4877
4878                 si = spr->rx_jmb_cons_idx;
4879                 di = dpr->rx_jmb_prod_idx;
4880
4881                 for (i = di; i < di + cpycnt; i++) {
4882                         if (dpr->rx_jmb_buffers[i].skb) {
4883                                 cpycnt = i - di;
4884                                 err = -ENOSPC;
4885                                 break;
4886                         }
4887                 }
4888
4889                 if (!cpycnt)
4890                         break;
4891
4892                 /* Ensure that updates to the rx_jmb_buffers ring and the
4893                  * shadowed hardware producer ring from tg3_recycle_skb() are
4894                  * ordered correctly WRT the skb check above.
4895                  */
4896                 smp_rmb();
4897
4898                 memcpy(&dpr->rx_jmb_buffers[di],
4899                        &spr->rx_jmb_buffers[si],
4900                        cpycnt * sizeof(struct ring_info));
4901
4902                 for (i = 0; i < cpycnt; i++, di++, si++) {
4903                         struct tg3_rx_buffer_desc *sbd, *dbd;
4904                         sbd = &spr->rx_jmb[si].std;
4905                         dbd = &dpr->rx_jmb[di].std;
4906                         dbd->addr_hi = sbd->addr_hi;
4907                         dbd->addr_lo = sbd->addr_lo;
4908                 }
4909
4910                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4911                                        TG3_RX_JUMBO_RING_SIZE;
4912                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4913                                        TG3_RX_JUMBO_RING_SIZE;
4914         }
4915
4916         return err;
4917 }
4918
4919 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4920 {
4921         struct tg3 *tp = tnapi->tp;
4922
4923         /* run TX completion thread */
4924         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4925                 tg3_tx(tnapi);
4926                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4927                         return work_done;
4928         }
4929
4930         /* run RX thread, within the bounds set by NAPI.
4931          * All RX "locking" is done by ensuring outside
4932          * code synchronizes with tg3->napi.poll()
4933          */
4934         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4935                 work_done += tg3_rx(tnapi, budget - work_done);
4936
4937         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4938                 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
4939                 int i, err = 0;
4940                 u32 std_prod_idx = dpr->rx_std_prod_idx;
4941                 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
4942
4943                 for (i = 1; i < tp->irq_cnt; i++)
4944                         err |= tg3_rx_prodring_xfer(tp, dpr,
4945                                                     &tp->napi[i].prodring);
4946
4947                 wmb();
4948
4949                 if (std_prod_idx != dpr->rx_std_prod_idx)
4950                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4951                                      dpr->rx_std_prod_idx);
4952
4953                 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
4954                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4955                                      dpr->rx_jmb_prod_idx);
4956
4957                 mmiowb();
4958
4959                 if (err)
4960                         tw32_f(HOSTCC_MODE, tp->coal_now);
4961         }
4962
4963         return work_done;
4964 }
4965
4966 static int tg3_poll_msix(struct napi_struct *napi, int budget)
4967 {
4968         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4969         struct tg3 *tp = tnapi->tp;
4970         int work_done = 0;
4971         struct tg3_hw_status *sblk = tnapi->hw_status;
4972
4973         while (1) {
4974                 work_done = tg3_poll_work(tnapi, work_done, budget);
4975
4976                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4977                         goto tx_recovery;
4978
4979                 if (unlikely(work_done >= budget))
4980                         break;
4981
4982                 /* tp->last_tag is used in tg3_int_reenable() below
4983                  * to tell the hw how much work has been processed,
4984                  * so we must read it before checking for more work.
4985                  */
4986                 tnapi->last_tag = sblk->status_tag;
4987                 tnapi->last_irq_tag = tnapi->last_tag;
4988                 rmb();
4989
4990                 /* check for RX/TX work to do */
4991                 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
4992                            *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
4993                         napi_complete(napi);
4994                         /* Reenable interrupts. */
4995                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
4996                         mmiowb();
4997                         break;
4998                 }
4999         }
5000
5001         return work_done;
5002
5003 tx_recovery:
5004         /* work_done is guaranteed to be less than budget. */
5005         napi_complete(napi);
5006         schedule_work(&tp->reset_task);
5007         return work_done;
5008 }
5009
5010 static int tg3_poll(struct napi_struct *napi, int budget)
5011 {
5012         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5013         struct tg3 *tp = tnapi->tp;
5014         int work_done = 0;
5015         struct tg3_hw_status *sblk = tnapi->hw_status;
5016
5017         while (1) {
5018                 tg3_poll_link(tp);
5019
5020                 work_done = tg3_poll_work(tnapi, work_done, budget);
5021
5022                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5023                         goto tx_recovery;
5024
5025                 if (unlikely(work_done >= budget))
5026                         break;
5027
5028                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5029                         /* tp->last_tag is used in tg3_int_reenable() below
5030                          * to tell the hw how much work has been processed,
5031                          * so we must read it before checking for more work.
5032                          */
5033                         tnapi->last_tag = sblk->status_tag;
5034                         tnapi->last_irq_tag = tnapi->last_tag;
5035                         rmb();
5036                 } else
5037                         sblk->status &= ~SD_STATUS_UPDATED;
5038
5039                 if (likely(!tg3_has_work(tnapi))) {
5040                         napi_complete(napi);
5041                         tg3_int_reenable(tnapi);
5042                         break;
5043                 }
5044         }
5045
5046         return work_done;
5047
5048 tx_recovery:
5049         /* work_done is guaranteed to be less than budget. */
5050         napi_complete(napi);
5051         schedule_work(&tp->reset_task);
5052         return work_done;
5053 }
5054
5055 static void tg3_napi_disable(struct tg3 *tp)
5056 {
5057         int i;
5058
5059         for (i = tp->irq_cnt - 1; i >= 0; i--)
5060                 napi_disable(&tp->napi[i].napi);
5061 }
5062
5063 static void tg3_napi_enable(struct tg3 *tp)
5064 {
5065         int i;
5066
5067         for (i = 0; i < tp->irq_cnt; i++)
5068                 napi_enable(&tp->napi[i].napi);
5069 }
5070
5071 static void tg3_napi_init(struct tg3 *tp)
5072 {
5073         int i;
5074
5075         netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
5076         for (i = 1; i < tp->irq_cnt; i++)
5077                 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
5078 }
5079
5080 static void tg3_napi_fini(struct tg3 *tp)
5081 {
5082         int i;
5083
5084         for (i = 0; i < tp->irq_cnt; i++)
5085                 netif_napi_del(&tp->napi[i].napi);
5086 }
5087
5088 static inline void tg3_netif_stop(struct tg3 *tp)
5089 {
5090         tp->dev->trans_start = jiffies; /* prevent tx timeout */
5091         tg3_napi_disable(tp);
5092         netif_tx_disable(tp->dev);
5093 }
5094
5095 static inline void tg3_netif_start(struct tg3 *tp)
5096 {
5097         /* NOTE: unconditional netif_tx_wake_all_queues is only
5098          * appropriate so long as all callers are assured to
5099          * have free tx slots (such as after tg3_init_hw)
5100          */
5101         netif_tx_wake_all_queues(tp->dev);
5102
5103         tg3_napi_enable(tp);
5104         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
5105         tg3_enable_ints(tp);
5106 }
5107
5108 static void tg3_irq_quiesce(struct tg3 *tp)
5109 {
5110         int i;
5111
5112         BUG_ON(tp->irq_sync);
5113
5114         tp->irq_sync = 1;
5115         smp_mb();
5116
5117         for (i = 0; i < tp->irq_cnt; i++)
5118                 synchronize_irq(tp->napi[i].irq_vec);
5119 }
5120
5121 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5122  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5123  * with as well.  Most of the time, this is not necessary except when
5124  * shutting down the device.
5125  */
5126 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5127 {
5128         spin_lock_bh(&tp->lock);
5129         if (irq_sync)
5130                 tg3_irq_quiesce(tp);
5131 }
5132
5133 static inline void tg3_full_unlock(struct tg3 *tp)
5134 {
5135         spin_unlock_bh(&tp->lock);
5136 }
5137
5138 /* One-shot MSI handler - Chip automatically disables interrupt
5139  * after sending MSI so driver doesn't have to do it.
5140  */
5141 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5142 {
5143         struct tg3_napi *tnapi = dev_id;
5144         struct tg3 *tp = tnapi->tp;
5145
5146         prefetch(tnapi->hw_status);
5147         if (tnapi->rx_rcb)
5148                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5149
5150         if (likely(!tg3_irq_sync(tp)))
5151                 napi_schedule(&tnapi->napi);
5152
5153         return IRQ_HANDLED;
5154 }
5155
5156 /* MSI ISR - No need to check for interrupt sharing and no need to
5157  * flush status block and interrupt mailbox. PCI ordering rules
5158  * guarantee that MSI will arrive after the status block.
5159  */
5160 static irqreturn_t tg3_msi(int irq, void *dev_id)
5161 {
5162         struct tg3_napi *tnapi = dev_id;
5163         struct tg3 *tp = tnapi->tp;
5164
5165         prefetch(tnapi->hw_status);
5166         if (tnapi->rx_rcb)
5167                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5168         /*
5169          * Writing any value to intr-mbox-0 clears PCI INTA# and
5170          * chip-internal interrupt pending events.
5171          * Writing non-zero to intr-mbox-0 additional tells the
5172          * NIC to stop sending us irqs, engaging "in-intr-handler"
5173          * event coalescing.
5174          */
5175         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5176         if (likely(!tg3_irq_sync(tp)))
5177                 napi_schedule(&tnapi->napi);
5178
5179         return IRQ_RETVAL(1);
5180 }
5181
5182 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5183 {
5184         struct tg3_napi *tnapi = dev_id;
5185         struct tg3 *tp = tnapi->tp;
5186         struct tg3_hw_status *sblk = tnapi->hw_status;
5187         unsigned int handled = 1;
5188
5189         /* In INTx mode, it is possible for the interrupt to arrive at
5190          * the CPU before the status block posted prior to the interrupt.
5191          * Reading the PCI State register will confirm whether the
5192          * interrupt is ours and will flush the status block.
5193          */
5194         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5195                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5196                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5197                         handled = 0;
5198                         goto out;
5199                 }
5200         }
5201
5202         /*
5203          * Writing any value to intr-mbox-0 clears PCI INTA# and
5204          * chip-internal interrupt pending events.
5205          * Writing non-zero to intr-mbox-0 additional tells the
5206          * NIC to stop sending us irqs, engaging "in-intr-handler"
5207          * event coalescing.
5208          *
5209          * Flush the mailbox to de-assert the IRQ immediately to prevent
5210          * spurious interrupts.  The flush impacts performance but
5211          * excessive spurious interrupts can be worse in some cases.
5212          */
5213         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5214         if (tg3_irq_sync(tp))
5215                 goto out;
5216         sblk->status &= ~SD_STATUS_UPDATED;
5217         if (likely(tg3_has_work(tnapi))) {
5218                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5219                 napi_schedule(&tnapi->napi);
5220         } else {
5221                 /* No work, shared interrupt perhaps?  re-enable
5222                  * interrupts, and flush that PCI write
5223                  */
5224                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5225                                0x00000000);
5226         }
5227 out:
5228         return IRQ_RETVAL(handled);
5229 }
5230
5231 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5232 {
5233         struct tg3_napi *tnapi = dev_id;
5234         struct tg3 *tp = tnapi->tp;
5235         struct tg3_hw_status *sblk = tnapi->hw_status;
5236         unsigned int handled = 1;
5237
5238         /* In INTx mode, it is possible for the interrupt to arrive at
5239          * the CPU before the status block posted prior to the interrupt.
5240          * Reading the PCI State register will confirm whether the
5241          * interrupt is ours and will flush the status block.
5242          */
5243         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5244                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5245                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5246                         handled = 0;
5247                         goto out;
5248                 }
5249         }
5250
5251         /*
5252          * writing any value to intr-mbox-0 clears PCI INTA# and
5253          * chip-internal interrupt pending events.
5254          * writing non-zero to intr-mbox-0 additional tells the
5255          * NIC to stop sending us irqs, engaging "in-intr-handler"
5256          * event coalescing.
5257          *
5258          * Flush the mailbox to de-assert the IRQ immediately to prevent
5259          * spurious interrupts.  The flush impacts performance but
5260          * excessive spurious interrupts can be worse in some cases.
5261          */
5262         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5263
5264         /*
5265          * In a shared interrupt configuration, sometimes other devices'
5266          * interrupts will scream.  We record the current status tag here
5267          * so that the above check can report that the screaming interrupts
5268          * are unhandled.  Eventually they will be silenced.
5269          */
5270         tnapi->last_irq_tag = sblk->status_tag;
5271
5272         if (tg3_irq_sync(tp))
5273                 goto out;
5274
5275         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5276
5277         napi_schedule(&tnapi->napi);
5278
5279 out:
5280         return IRQ_RETVAL(handled);
5281 }
5282
5283 /* ISR for interrupt test */
5284 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5285 {
5286         struct tg3_napi *tnapi = dev_id;
5287         struct tg3 *tp = tnapi->tp;
5288         struct tg3_hw_status *sblk = tnapi->hw_status;
5289
5290         if ((sblk->status & SD_STATUS_UPDATED) ||
5291             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5292                 tg3_disable_ints(tp);
5293                 return IRQ_RETVAL(1);
5294         }
5295         return IRQ_RETVAL(0);
5296 }
5297
5298 static int tg3_init_hw(struct tg3 *, int);
5299 static int tg3_halt(struct tg3 *, int, int);
5300
5301 /* Restart hardware after configuration changes, self-test, etc.
5302  * Invoked with tp->lock held.
5303  */
5304 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5305         __releases(tp->lock)
5306         __acquires(tp->lock)
5307 {
5308         int err;
5309
5310         err = tg3_init_hw(tp, reset_phy);
5311         if (err) {
5312                 netdev_err(tp->dev,
5313                            "Failed to re-initialize device, aborting\n");
5314                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5315                 tg3_full_unlock(tp);
5316                 del_timer_sync(&tp->timer);
5317                 tp->irq_sync = 0;
5318                 tg3_napi_enable(tp);
5319                 dev_close(tp->dev);
5320                 tg3_full_lock(tp, 0);
5321         }
5322         return err;
5323 }
5324
5325 #ifdef CONFIG_NET_POLL_CONTROLLER
5326 static void tg3_poll_controller(struct net_device *dev)
5327 {
5328         int i;
5329         struct tg3 *tp = netdev_priv(dev);
5330
5331         for (i = 0; i < tp->irq_cnt; i++)
5332                 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5333 }
5334 #endif
5335
5336 static void tg3_reset_task(struct work_struct *work)
5337 {
5338         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5339         int err;
5340         unsigned int restart_timer;
5341
5342         tg3_full_lock(tp, 0);
5343
5344         if (!netif_running(tp->dev)) {
5345                 tg3_full_unlock(tp);
5346                 return;
5347         }
5348
5349         tg3_full_unlock(tp);
5350
5351         tg3_phy_stop(tp);
5352
5353         tg3_netif_stop(tp);
5354
5355         tg3_full_lock(tp, 1);
5356
5357         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5358         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5359
5360         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5361                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5362                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5363                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5364                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5365         }
5366
5367         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5368         err = tg3_init_hw(tp, 1);
5369         if (err)
5370                 goto out;
5371
5372         tg3_netif_start(tp);
5373
5374         if (restart_timer)
5375                 mod_timer(&tp->timer, jiffies + 1);
5376
5377 out:
5378         tg3_full_unlock(tp);
5379
5380         if (!err)
5381                 tg3_phy_start(tp);
5382 }
5383
5384 static void tg3_dump_short_state(struct tg3 *tp)
5385 {
5386         netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5387                    tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5388         netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5389                    tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5390 }
5391
5392 static void tg3_tx_timeout(struct net_device *dev)
5393 {
5394         struct tg3 *tp = netdev_priv(dev);
5395
5396         if (netif_msg_tx_err(tp)) {
5397                 netdev_err(dev, "transmit timed out, resetting\n");
5398                 tg3_dump_short_state(tp);
5399         }
5400
5401         schedule_work(&tp->reset_task);
5402 }
5403
5404 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5405 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5406 {
5407         u32 base = (u32) mapping & 0xffffffff;
5408
5409         return (base > 0xffffdcc0) && (base + len + 8 < base);
5410 }
5411
5412 /* Test for DMA addresses > 40-bit */
5413 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5414                                           int len)
5415 {
5416 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5417         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5418                 return ((u64) mapping + len) > DMA_BIT_MASK(40);
5419         return 0;
5420 #else
5421         return 0;
5422 #endif
5423 }
5424
5425 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5426
5427 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5428 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5429                                        struct sk_buff *skb, u32 last_plus_one,
5430                                        u32 *start, u32 base_flags, u32 mss)
5431 {
5432         struct tg3 *tp = tnapi->tp;
5433         struct sk_buff *new_skb;
5434         dma_addr_t new_addr = 0;
5435         u32 entry = *start;
5436         int i, ret = 0;
5437
5438         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5439                 new_skb = skb_copy(skb, GFP_ATOMIC);
5440         else {
5441                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5442
5443                 new_skb = skb_copy_expand(skb,
5444                                           skb_headroom(skb) + more_headroom,
5445                                           skb_tailroom(skb), GFP_ATOMIC);
5446         }
5447
5448         if (!new_skb) {
5449                 ret = -1;
5450         } else {
5451                 /* New SKB is guaranteed to be linear. */
5452                 entry = *start;
5453                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5454                                           PCI_DMA_TODEVICE);
5455                 /* Make sure the mapping succeeded */
5456                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5457                         ret = -1;
5458                         dev_kfree_skb(new_skb);
5459                         new_skb = NULL;
5460
5461                 /* Make sure new skb does not cross any 4G boundaries.
5462                  * Drop the packet if it does.
5463                  */
5464                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5465                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5466                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5467                                          PCI_DMA_TODEVICE);
5468                         ret = -1;
5469                         dev_kfree_skb(new_skb);
5470                         new_skb = NULL;
5471                 } else {
5472                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5473                                     base_flags, 1 | (mss << 1));
5474                         *start = NEXT_TX(entry);
5475                 }
5476         }
5477
5478         /* Now clean up the sw ring entries. */
5479         i = 0;
5480         while (entry != last_plus_one) {
5481                 int len;
5482
5483                 if (i == 0)
5484                         len = skb_headlen(skb);
5485                 else
5486                         len = skb_shinfo(skb)->frags[i-1].size;
5487
5488                 pci_unmap_single(tp->pdev,
5489                                  dma_unmap_addr(&tnapi->tx_buffers[entry],
5490                                                 mapping),
5491                                  len, PCI_DMA_TODEVICE);
5492                 if (i == 0) {
5493                         tnapi->tx_buffers[entry].skb = new_skb;
5494                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5495                                            new_addr);
5496                 } else {
5497                         tnapi->tx_buffers[entry].skb = NULL;
5498                 }
5499                 entry = NEXT_TX(entry);
5500                 i++;
5501         }
5502
5503         dev_kfree_skb(skb);
5504
5505         return ret;
5506 }
5507
5508 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5509                         dma_addr_t mapping, int len, u32 flags,
5510                         u32 mss_and_is_end)
5511 {
5512         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5513         int is_end = (mss_and_is_end & 0x1);
5514         u32 mss = (mss_and_is_end >> 1);
5515         u32 vlan_tag = 0;
5516
5517         if (is_end)
5518                 flags |= TXD_FLAG_END;
5519         if (flags & TXD_FLAG_VLAN) {
5520                 vlan_tag = flags >> 16;
5521                 flags &= 0xffff;
5522         }
5523         vlan_tag |= (mss << TXD_MSS_SHIFT);
5524
5525         txd->addr_hi = ((u64) mapping >> 32);
5526         txd->addr_lo = ((u64) mapping & 0xffffffff);
5527         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5528         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5529 }
5530
5531 /* hard_start_xmit for devices that don't have any bugs and
5532  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5533  */
5534 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5535                                   struct net_device *dev)
5536 {
5537         struct tg3 *tp = netdev_priv(dev);
5538         u32 len, entry, base_flags, mss;
5539         dma_addr_t mapping;
5540         struct tg3_napi *tnapi;
5541         struct netdev_queue *txq;
5542         unsigned int i, last;
5543
5544         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5545         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5546         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5547                 tnapi++;
5548
5549         /* We are running in BH disabled context with netif_tx_lock
5550          * and TX reclaim runs via tp->napi.poll inside of a software
5551          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5552          * no IRQ context deadlocks to worry about either.  Rejoice!
5553          */
5554         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5555                 if (!netif_tx_queue_stopped(txq)) {
5556                         netif_tx_stop_queue(txq);
5557
5558                         /* This is a hard error, log it. */
5559                         netdev_err(dev,
5560                                    "BUG! Tx Ring full when queue awake!\n");
5561                 }
5562                 return NETDEV_TX_BUSY;
5563         }
5564
5565         entry = tnapi->tx_prod;
5566         base_flags = 0;
5567         mss = skb_shinfo(skb)->gso_size;
5568         if (mss) {
5569                 int tcp_opt_len, ip_tcp_len;
5570                 u32 hdrlen;
5571
5572                 if (skb_header_cloned(skb) &&
5573                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5574                         dev_kfree_skb(skb);
5575                         goto out_unlock;
5576                 }
5577
5578                 if (skb_is_gso_v6(skb)) {
5579                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5580                 } else {
5581                         struct iphdr *iph = ip_hdr(skb);
5582
5583                         tcp_opt_len = tcp_optlen(skb);
5584                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5585
5586                         iph->check = 0;
5587                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5588                         hdrlen = ip_tcp_len + tcp_opt_len;
5589                 }
5590
5591                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5592                         mss |= (hdrlen & 0xc) << 12;
5593                         if (hdrlen & 0x10)
5594                                 base_flags |= 0x00000010;
5595                         base_flags |= (hdrlen & 0x3e0) << 5;
5596                 } else
5597                         mss |= hdrlen << 9;
5598
5599                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5600                                TXD_FLAG_CPU_POST_DMA);
5601
5602                 tcp_hdr(skb)->check = 0;
5603
5604         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5605                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5606         }
5607
5608 #if TG3_VLAN_TAG_USED
5609         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5610                 base_flags |= (TXD_FLAG_VLAN |
5611                                (vlan_tx_tag_get(skb) << 16));
5612 #endif
5613
5614         len = skb_headlen(skb);
5615
5616         /* Queue skb data, a.k.a. the main skb fragment. */
5617         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5618         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5619                 dev_kfree_skb(skb);
5620                 goto out_unlock;
5621         }
5622
5623         tnapi->tx_buffers[entry].skb = skb;
5624         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5625
5626         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5627             !mss && skb->len > ETH_DATA_LEN)
5628                 base_flags |= TXD_FLAG_JMB_PKT;
5629
5630         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5631                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5632
5633         entry = NEXT_TX(entry);
5634
5635         /* Now loop through additional data fragments, and queue them. */
5636         if (skb_shinfo(skb)->nr_frags > 0) {
5637                 last = skb_shinfo(skb)->nr_frags - 1;
5638                 for (i = 0; i <= last; i++) {
5639                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5640
5641                         len = frag->size;
5642                         mapping = pci_map_page(tp->pdev,
5643                                                frag->page,
5644                                                frag->page_offset,
5645                                                len, PCI_DMA_TODEVICE);
5646                         if (pci_dma_mapping_error(tp->pdev, mapping))
5647                                 goto dma_error;
5648
5649                         tnapi->tx_buffers[entry].skb = NULL;
5650                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5651                                            mapping);
5652
5653                         tg3_set_txd(tnapi, entry, mapping, len,
5654                                     base_flags, (i == last) | (mss << 1));
5655
5656                         entry = NEXT_TX(entry);
5657                 }
5658         }
5659
5660         /* Packets are ready, update Tx producer idx local and on card. */
5661         tw32_tx_mbox(tnapi->prodmbox, entry);
5662
5663         tnapi->tx_prod = entry;
5664         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5665                 netif_tx_stop_queue(txq);
5666
5667                 /* netif_tx_stop_queue() must be done before checking
5668                  * checking tx index in tg3_tx_avail() below, because in
5669                  * tg3_tx(), we update tx index before checking for
5670                  * netif_tx_queue_stopped().
5671                  */
5672                 smp_mb();
5673                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5674                         netif_tx_wake_queue(txq);
5675         }
5676
5677 out_unlock:
5678         mmiowb();
5679
5680         return NETDEV_TX_OK;
5681
5682 dma_error:
5683         last = i;
5684         entry = tnapi->tx_prod;
5685         tnapi->tx_buffers[entry].skb = NULL;
5686         pci_unmap_single(tp->pdev,
5687                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5688                          skb_headlen(skb),
5689                          PCI_DMA_TODEVICE);
5690         for (i = 0; i <= last; i++) {
5691                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5692                 entry = NEXT_TX(entry);
5693
5694                 pci_unmap_page(tp->pdev,
5695                                dma_unmap_addr(&tnapi->tx_buffers[entry],
5696                                               mapping),
5697                                frag->size, PCI_DMA_TODEVICE);
5698         }
5699
5700         dev_kfree_skb(skb);
5701         return NETDEV_TX_OK;
5702 }
5703
5704 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5705                                           struct net_device *);
5706
5707 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5708  * TSO header is greater than 80 bytes.
5709  */
5710 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5711 {
5712         struct sk_buff *segs, *nskb;
5713         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5714
5715         /* Estimate the number of fragments in the worst case */
5716         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5717                 netif_stop_queue(tp->dev);
5718
5719                 /* netif_tx_stop_queue() must be done before checking
5720                  * checking tx index in tg3_tx_avail() below, because in
5721                  * tg3_tx(), we update tx index before checking for
5722                  * netif_tx_queue_stopped().
5723                  */
5724                 smp_mb();
5725                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5726                         return NETDEV_TX_BUSY;
5727
5728                 netif_wake_queue(tp->dev);
5729         }
5730
5731         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5732         if (IS_ERR(segs))
5733                 goto tg3_tso_bug_end;
5734
5735         do {
5736                 nskb = segs;
5737                 segs = segs->next;
5738                 nskb->next = NULL;
5739                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5740         } while (segs);
5741
5742 tg3_tso_bug_end:
5743         dev_kfree_skb(skb);
5744
5745         return NETDEV_TX_OK;
5746 }
5747
5748 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5749  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5750  */
5751 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5752                                           struct net_device *dev)
5753 {
5754         struct tg3 *tp = netdev_priv(dev);
5755         u32 len, entry, base_flags, mss;
5756         int would_hit_hwbug;
5757         dma_addr_t mapping;
5758         struct tg3_napi *tnapi;
5759         struct netdev_queue *txq;
5760         unsigned int i, last;
5761
5762         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5763         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5764         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5765                 tnapi++;
5766
5767         /* We are running in BH disabled context with netif_tx_lock
5768          * and TX reclaim runs via tp->napi.poll inside of a software
5769          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5770          * no IRQ context deadlocks to worry about either.  Rejoice!
5771          */
5772         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5773                 if (!netif_tx_queue_stopped(txq)) {
5774                         netif_tx_stop_queue(txq);
5775
5776                         /* This is a hard error, log it. */
5777                         netdev_err(dev,
5778                                    "BUG! Tx Ring full when queue awake!\n");
5779                 }
5780                 return NETDEV_TX_BUSY;
5781         }
5782
5783         entry = tnapi->tx_prod;
5784         base_flags = 0;
5785         if (skb->ip_summed == CHECKSUM_PARTIAL)
5786                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5787
5788         mss = skb_shinfo(skb)->gso_size;
5789         if (mss) {
5790                 struct iphdr *iph;
5791                 u32 tcp_opt_len, hdr_len;
5792
5793                 if (skb_header_cloned(skb) &&
5794                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5795                         dev_kfree_skb(skb);
5796                         goto out_unlock;
5797                 }
5798
5799                 iph = ip_hdr(skb);
5800                 tcp_opt_len = tcp_optlen(skb);
5801
5802                 if (skb_is_gso_v6(skb)) {
5803                         hdr_len = skb_headlen(skb) - ETH_HLEN;
5804                 } else {
5805                         u32 ip_tcp_len;
5806
5807                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5808                         hdr_len = ip_tcp_len + tcp_opt_len;
5809
5810                         iph->check = 0;
5811                         iph->tot_len = htons(mss + hdr_len);
5812                 }
5813
5814                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5815                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5816                         return tg3_tso_bug(tp, skb);
5817
5818                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5819                                TXD_FLAG_CPU_POST_DMA);
5820
5821                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5822                         tcp_hdr(skb)->check = 0;
5823                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5824                 } else
5825                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5826                                                                  iph->daddr, 0,
5827                                                                  IPPROTO_TCP,
5828                                                                  0);
5829
5830                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5831                         mss |= (hdr_len & 0xc) << 12;
5832                         if (hdr_len & 0x10)
5833                                 base_flags |= 0x00000010;
5834                         base_flags |= (hdr_len & 0x3e0) << 5;
5835                 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5836                         mss |= hdr_len << 9;
5837                 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5838                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5839                         if (tcp_opt_len || iph->ihl > 5) {
5840                                 int tsflags;
5841
5842                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5843                                 mss |= (tsflags << 11);
5844                         }
5845                 } else {
5846                         if (tcp_opt_len || iph->ihl > 5) {
5847                                 int tsflags;
5848
5849                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5850                                 base_flags |= tsflags << 12;
5851                         }
5852                 }
5853         }
5854 #if TG3_VLAN_TAG_USED
5855         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5856                 base_flags |= (TXD_FLAG_VLAN |
5857                                (vlan_tx_tag_get(skb) << 16));
5858 #endif
5859
5860         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5861             !mss && skb->len > ETH_DATA_LEN)
5862                 base_flags |= TXD_FLAG_JMB_PKT;
5863
5864         len = skb_headlen(skb);
5865
5866         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5867         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5868                 dev_kfree_skb(skb);
5869                 goto out_unlock;
5870         }
5871
5872         tnapi->tx_buffers[entry].skb = skb;
5873         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5874
5875         would_hit_hwbug = 0;
5876
5877         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5878                 would_hit_hwbug = 1;
5879
5880         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5881             tg3_4g_overflow_test(mapping, len))
5882                 would_hit_hwbug = 1;
5883
5884         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5885             tg3_40bit_overflow_test(tp, mapping, len))
5886                 would_hit_hwbug = 1;
5887
5888         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5889                 would_hit_hwbug = 1;
5890
5891         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5892                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5893
5894         entry = NEXT_TX(entry);
5895
5896         /* Now loop through additional data fragments, and queue them. */
5897         if (skb_shinfo(skb)->nr_frags > 0) {
5898                 last = skb_shinfo(skb)->nr_frags - 1;
5899                 for (i = 0; i <= last; i++) {
5900                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5901
5902                         len = frag->size;
5903                         mapping = pci_map_page(tp->pdev,
5904                                                frag->page,
5905                                                frag->page_offset,
5906                                                len, PCI_DMA_TODEVICE);
5907
5908                         tnapi->tx_buffers[entry].skb = NULL;
5909                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5910                                            mapping);
5911                         if (pci_dma_mapping_error(tp->pdev, mapping))
5912                                 goto dma_error;
5913
5914                         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5915                             len <= 8)
5916                                 would_hit_hwbug = 1;
5917
5918                         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5919                             tg3_4g_overflow_test(mapping, len))
5920                                 would_hit_hwbug = 1;
5921
5922                         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5923                             tg3_40bit_overflow_test(tp, mapping, len))
5924                                 would_hit_hwbug = 1;
5925
5926                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5927                                 tg3_set_txd(tnapi, entry, mapping, len,
5928                                             base_flags, (i == last)|(mss << 1));
5929                         else
5930                                 tg3_set_txd(tnapi, entry, mapping, len,
5931                                             base_flags, (i == last));
5932
5933                         entry = NEXT_TX(entry);
5934                 }
5935         }
5936
5937         if (would_hit_hwbug) {
5938                 u32 last_plus_one = entry;
5939                 u32 start;
5940
5941                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5942                 start &= (TG3_TX_RING_SIZE - 1);
5943
5944                 /* If the workaround fails due to memory/mapping
5945                  * failure, silently drop this packet.
5946                  */
5947                 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
5948                                                 &start, base_flags, mss))
5949                         goto out_unlock;
5950
5951                 entry = start;
5952         }
5953
5954         /* Packets are ready, update Tx producer idx local and on card. */
5955         tw32_tx_mbox(tnapi->prodmbox, entry);
5956
5957         tnapi->tx_prod = entry;
5958         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5959                 netif_tx_stop_queue(txq);
5960
5961                 /* netif_tx_stop_queue() must be done before checking
5962                  * checking tx index in tg3_tx_avail() below, because in
5963                  * tg3_tx(), we update tx index before checking for
5964                  * netif_tx_queue_stopped().
5965                  */
5966                 smp_mb();
5967                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5968                         netif_tx_wake_queue(txq);
5969         }
5970
5971 out_unlock:
5972         mmiowb();
5973
5974         return NETDEV_TX_OK;
5975
5976 dma_error:
5977         last = i;
5978         entry = tnapi->tx_prod;
5979         tnapi->tx_buffers[entry].skb = NULL;
5980         pci_unmap_single(tp->pdev,
5981                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5982                          skb_headlen(skb),
5983                          PCI_DMA_TODEVICE);
5984         for (i = 0; i <= last; i++) {
5985                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5986                 entry = NEXT_TX(entry);
5987
5988                 pci_unmap_page(tp->pdev,
5989                                dma_unmap_addr(&tnapi->tx_buffers[entry],
5990                                               mapping),
5991                                frag->size, PCI_DMA_TODEVICE);
5992         }
5993
5994         dev_kfree_skb(skb);
5995         return NETDEV_TX_OK;
5996 }
5997
5998 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5999                                int new_mtu)
6000 {
6001         dev->mtu = new_mtu;
6002
6003         if (new_mtu > ETH_DATA_LEN) {
6004                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6005                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
6006                         ethtool_op_set_tso(dev, 0);
6007                 } else {
6008                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
6009                 }
6010         } else {
6011                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6012                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
6013                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
6014         }
6015 }
6016
6017 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
6018 {
6019         struct tg3 *tp = netdev_priv(dev);
6020         int err;
6021
6022         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
6023                 return -EINVAL;
6024
6025         if (!netif_running(dev)) {
6026                 /* We'll just catch it later when the
6027                  * device is up'd.
6028                  */
6029                 tg3_set_mtu(dev, tp, new_mtu);
6030                 return 0;
6031         }
6032
6033         tg3_phy_stop(tp);
6034
6035         tg3_netif_stop(tp);
6036
6037         tg3_full_lock(tp, 1);
6038
6039         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6040
6041         tg3_set_mtu(dev, tp, new_mtu);
6042
6043         err = tg3_restart_hw(tp, 0);
6044
6045         if (!err)
6046                 tg3_netif_start(tp);
6047
6048         tg3_full_unlock(tp);
6049
6050         if (!err)
6051                 tg3_phy_start(tp);
6052
6053         return err;
6054 }
6055
6056 static void tg3_rx_prodring_free(struct tg3 *tp,
6057                                  struct tg3_rx_prodring_set *tpr)
6058 {
6059         int i;
6060
6061         if (tpr != &tp->napi[0].prodring) {
6062                 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
6063                      i = (i + 1) % TG3_RX_RING_SIZE)
6064                         tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6065                                         tp->rx_pkt_map_sz);
6066
6067                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6068                         for (i = tpr->rx_jmb_cons_idx;
6069                              i != tpr->rx_jmb_prod_idx;
6070                              i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
6071                                 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6072                                                 TG3_RX_JMB_MAP_SZ);
6073                         }
6074                 }
6075
6076                 return;
6077         }
6078
6079         for (i = 0; i < TG3_RX_RING_SIZE; i++)
6080                 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6081                                 tp->rx_pkt_map_sz);
6082
6083         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6084                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
6085                         tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6086                                         TG3_RX_JMB_MAP_SZ);
6087         }
6088 }
6089
6090 /* Initialize rx rings for packet processing.
6091  *
6092  * The chip has been shut down and the driver detached from
6093  * the networking, so no interrupts or new tx packets will
6094  * end up in the driver.  tp->{tx,}lock are held and thus
6095  * we may not sleep.
6096  */
6097 static int tg3_rx_prodring_alloc(struct tg3 *tp,
6098                                  struct tg3_rx_prodring_set *tpr)
6099 {
6100         u32 i, rx_pkt_dma_sz;
6101
6102         tpr->rx_std_cons_idx = 0;
6103         tpr->rx_std_prod_idx = 0;
6104         tpr->rx_jmb_cons_idx = 0;
6105         tpr->rx_jmb_prod_idx = 0;
6106
6107         if (tpr != &tp->napi[0].prodring) {
6108                 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
6109                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
6110                         memset(&tpr->rx_jmb_buffers[0], 0,
6111                                TG3_RX_JMB_BUFF_RING_SIZE);
6112                 goto done;
6113         }
6114
6115         /* Zero out all descriptors. */
6116         memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
6117
6118         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6119         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
6120             tp->dev->mtu > ETH_DATA_LEN)
6121                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6122         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6123
6124         /* Initialize invariants of the rings, we only set this
6125          * stuff once.  This works because the card does not
6126          * write into the rx buffer posting rings.
6127          */
6128         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
6129                 struct tg3_rx_buffer_desc *rxd;
6130
6131                 rxd = &tpr->rx_std[i];
6132                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6133                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6134                 rxd->opaque = (RXD_OPAQUE_RING_STD |
6135                                (i << RXD_OPAQUE_INDEX_SHIFT));
6136         }
6137
6138         /* Now allocate fresh SKBs for each rx ring. */
6139         for (i = 0; i < tp->rx_pending; i++) {
6140                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6141                         netdev_warn(tp->dev,
6142                                     "Using a smaller RX standard ring. Only "
6143                                     "%d out of %d buffers were allocated "
6144                                     "successfully\n", i, tp->rx_pending);
6145                         if (i == 0)
6146                                 goto initfail;
6147                         tp->rx_pending = i;
6148                         break;
6149                 }
6150         }
6151
6152         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6153                 goto done;
6154
6155         memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
6156
6157         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
6158                 goto done;
6159
6160         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
6161                 struct tg3_rx_buffer_desc *rxd;
6162
6163                 rxd = &tpr->rx_jmb[i].std;
6164                 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6165                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6166                                   RXD_FLAG_JUMBO;
6167                 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6168                        (i << RXD_OPAQUE_INDEX_SHIFT));
6169         }
6170
6171         for (i = 0; i < tp->rx_jumbo_pending; i++) {
6172                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
6173                         netdev_warn(tp->dev,
6174                                     "Using a smaller RX jumbo ring. Only %d "
6175                                     "out of %d buffers were allocated "
6176                                     "successfully\n", i, tp->rx_jumbo_pending);
6177                         if (i == 0)
6178                                 goto initfail;
6179                         tp->rx_jumbo_pending = i;
6180                         break;
6181                 }
6182         }
6183
6184 done:
6185         return 0;
6186
6187 initfail:
6188         tg3_rx_prodring_free(tp, tpr);
6189         return -ENOMEM;
6190 }
6191
6192 static void tg3_rx_prodring_fini(struct tg3 *tp,
6193                                  struct tg3_rx_prodring_set *tpr)
6194 {
6195         kfree(tpr->rx_std_buffers);
6196         tpr->rx_std_buffers = NULL;
6197         kfree(tpr->rx_jmb_buffers);
6198         tpr->rx_jmb_buffers = NULL;
6199         if (tpr->rx_std) {
6200                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
6201                                     tpr->rx_std, tpr->rx_std_mapping);
6202                 tpr->rx_std = NULL;
6203         }
6204         if (tpr->rx_jmb) {
6205                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
6206                                     tpr->rx_jmb, tpr->rx_jmb_mapping);
6207                 tpr->rx_jmb = NULL;
6208         }
6209 }
6210
6211 static int tg3_rx_prodring_init(struct tg3 *tp,
6212                                 struct tg3_rx_prodring_set *tpr)
6213 {
6214         tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
6215         if (!tpr->rx_std_buffers)
6216                 return -ENOMEM;
6217
6218         tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6219                                            &tpr->rx_std_mapping);
6220         if (!tpr->rx_std)
6221                 goto err_out;
6222
6223         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6224                 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
6225                                               GFP_KERNEL);
6226                 if (!tpr->rx_jmb_buffers)
6227                         goto err_out;
6228
6229                 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6230                                                    TG3_RX_JUMBO_RING_BYTES,
6231                                                    &tpr->rx_jmb_mapping);
6232                 if (!tpr->rx_jmb)
6233                         goto err_out;
6234         }
6235
6236         return 0;
6237
6238 err_out:
6239         tg3_rx_prodring_fini(tp, tpr);
6240         return -ENOMEM;
6241 }
6242
6243 /* Free up pending packets in all rx/tx rings.
6244  *
6245  * The chip has been shut down and the driver detached from
6246  * the networking, so no interrupts or new tx packets will
6247  * end up in the driver.  tp->{tx,}lock is not held and we are not
6248  * in an interrupt context and thus may sleep.
6249  */
6250 static void tg3_free_rings(struct tg3 *tp)
6251 {
6252         int i, j;
6253
6254         for (j = 0; j < tp->irq_cnt; j++) {
6255                 struct tg3_napi *tnapi = &tp->napi[j];
6256
6257                 tg3_rx_prodring_free(tp, &tnapi->prodring);
6258
6259                 if (!tnapi->tx_buffers)
6260                         continue;
6261
6262                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6263                         struct ring_info *txp;
6264                         struct sk_buff *skb;
6265                         unsigned int k;
6266
6267                         txp = &tnapi->tx_buffers[i];
6268                         skb = txp->skb;
6269
6270                         if (skb == NULL) {
6271                                 i++;
6272                                 continue;
6273                         }
6274
6275                         pci_unmap_single(tp->pdev,
6276                                          dma_unmap_addr(txp, mapping),
6277                                          skb_headlen(skb),
6278                                          PCI_DMA_TODEVICE);
6279                         txp->skb = NULL;
6280
6281                         i++;
6282
6283                         for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6284                                 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6285                                 pci_unmap_page(tp->pdev,
6286                                                dma_unmap_addr(txp, mapping),
6287                                                skb_shinfo(skb)->frags[k].size,
6288                                                PCI_DMA_TODEVICE);
6289                                 i++;
6290                         }
6291
6292                         dev_kfree_skb_any(skb);
6293                 }
6294         }
6295 }
6296
6297 /* Initialize tx/rx rings for packet processing.
6298  *
6299  * The chip has been shut down and the driver detached from
6300  * the networking, so no interrupts or new tx packets will
6301  * end up in the driver.  tp->{tx,}lock are held and thus
6302  * we may not sleep.
6303  */
6304 static int tg3_init_rings(struct tg3 *tp)
6305 {
6306         int i;
6307
6308         /* Free up all the SKBs. */
6309         tg3_free_rings(tp);
6310
6311         for (i = 0; i < tp->irq_cnt; i++) {
6312                 struct tg3_napi *tnapi = &tp->napi[i];
6313
6314                 tnapi->last_tag = 0;
6315                 tnapi->last_irq_tag = 0;
6316                 tnapi->hw_status->status = 0;
6317                 tnapi->hw_status->status_tag = 0;
6318                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6319
6320                 tnapi->tx_prod = 0;
6321                 tnapi->tx_cons = 0;
6322                 if (tnapi->tx_ring)
6323                         memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6324
6325                 tnapi->rx_rcb_ptr = 0;
6326                 if (tnapi->rx_rcb)
6327                         memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6328
6329                 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
6330                         tg3_free_rings(tp);
6331                         return -ENOMEM;
6332                 }
6333         }
6334
6335         return 0;
6336 }
6337
6338 /*
6339  * Must not be invoked with interrupt sources disabled and
6340  * the hardware shutdown down.
6341  */
6342 static void tg3_free_consistent(struct tg3 *tp)
6343 {
6344         int i;
6345
6346         for (i = 0; i < tp->irq_cnt; i++) {
6347                 struct tg3_napi *tnapi = &tp->napi[i];
6348
6349                 if (tnapi->tx_ring) {
6350                         pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6351                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
6352                         tnapi->tx_ring = NULL;
6353                 }
6354
6355                 kfree(tnapi->tx_buffers);
6356                 tnapi->tx_buffers = NULL;
6357
6358                 if (tnapi->rx_rcb) {
6359                         pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6360                                             tnapi->rx_rcb,
6361                                             tnapi->rx_rcb_mapping);
6362                         tnapi->rx_rcb = NULL;
6363                 }
6364
6365                 tg3_rx_prodring_fini(tp, &tnapi->prodring);
6366
6367                 if (tnapi->hw_status) {
6368                         pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6369                                             tnapi->hw_status,
6370                                             tnapi->status_mapping);
6371                         tnapi->hw_status = NULL;
6372                 }
6373         }
6374
6375         if (tp->hw_stats) {
6376                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6377                                     tp->hw_stats, tp->stats_mapping);
6378                 tp->hw_stats = NULL;
6379         }
6380 }
6381
6382 /*
6383  * Must not be invoked with interrupt sources disabled and
6384  * the hardware shutdown down.  Can sleep.
6385  */
6386 static int tg3_alloc_consistent(struct tg3 *tp)
6387 {
6388         int i;
6389
6390         tp->hw_stats = pci_alloc_consistent(tp->pdev,
6391                                             sizeof(struct tg3_hw_stats),
6392                                             &tp->stats_mapping);
6393         if (!tp->hw_stats)
6394                 goto err_out;
6395
6396         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6397
6398         for (i = 0; i < tp->irq_cnt; i++) {
6399                 struct tg3_napi *tnapi = &tp->napi[i];
6400                 struct tg3_hw_status *sblk;
6401
6402                 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6403                                                         TG3_HW_STATUS_SIZE,
6404                                                         &tnapi->status_mapping);
6405                 if (!tnapi->hw_status)
6406                         goto err_out;
6407
6408                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6409                 sblk = tnapi->hw_status;
6410
6411                 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
6412                         goto err_out;
6413
6414                 /* If multivector TSS is enabled, vector 0 does not handle
6415                  * tx interrupts.  Don't allocate any resources for it.
6416                  */
6417                 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6418                     (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6419                         tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6420                                                     TG3_TX_RING_SIZE,
6421                                                     GFP_KERNEL);
6422                         if (!tnapi->tx_buffers)
6423                                 goto err_out;
6424
6425                         tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6426                                                               TG3_TX_RING_BYTES,
6427                                                        &tnapi->tx_desc_mapping);
6428                         if (!tnapi->tx_ring)
6429                                 goto err_out;
6430                 }
6431
6432                 /*
6433                  * When RSS is enabled, the status block format changes
6434                  * slightly.  The "rx_jumbo_consumer", "reserved",
6435                  * and "rx_mini_consumer" members get mapped to the
6436                  * other three rx return ring producer indexes.
6437                  */
6438                 switch (i) {
6439                 default:
6440                         tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6441                         break;
6442                 case 2:
6443                         tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6444                         break;
6445                 case 3:
6446                         tnapi->rx_rcb_prod_idx = &sblk->reserved;
6447                         break;
6448                 case 4:
6449                         tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6450                         break;
6451                 }
6452
6453                 /*
6454                  * If multivector RSS is enabled, vector 0 does not handle
6455                  * rx or tx interrupts.  Don't allocate any resources for it.
6456                  */
6457                 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6458                         continue;
6459
6460                 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6461                                                      TG3_RX_RCB_RING_BYTES(tp),
6462                                                      &tnapi->rx_rcb_mapping);
6463                 if (!tnapi->rx_rcb)
6464                         goto err_out;
6465
6466                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6467         }
6468
6469         return 0;
6470
6471 err_out:
6472         tg3_free_consistent(tp);
6473         return -ENOMEM;
6474 }
6475
6476 #define MAX_WAIT_CNT 1000
6477
6478 /* To stop a block, clear the enable bit and poll till it
6479  * clears.  tp->lock is held.
6480  */
6481 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6482 {
6483         unsigned int i;
6484         u32 val;
6485
6486         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6487                 switch (ofs) {
6488                 case RCVLSC_MODE:
6489                 case DMAC_MODE:
6490                 case MBFREE_MODE:
6491                 case BUFMGR_MODE:
6492                 case MEMARB_MODE:
6493                         /* We can't enable/disable these bits of the
6494                          * 5705/5750, just say success.
6495                          */
6496                         return 0;
6497
6498                 default:
6499                         break;
6500                 }
6501         }
6502
6503         val = tr32(ofs);
6504         val &= ~enable_bit;
6505         tw32_f(ofs, val);
6506
6507         for (i = 0; i < MAX_WAIT_CNT; i++) {
6508                 udelay(100);
6509                 val = tr32(ofs);
6510                 if ((val & enable_bit) == 0)
6511                         break;
6512         }
6513
6514         if (i == MAX_WAIT_CNT && !silent) {
6515                 dev_err(&tp->pdev->dev,
6516                         "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6517                         ofs, enable_bit);
6518                 return -ENODEV;
6519         }
6520
6521         return 0;
6522 }
6523
6524 /* tp->lock is held. */
6525 static int tg3_abort_hw(struct tg3 *tp, int silent)
6526 {
6527         int i, err;
6528
6529         tg3_disable_ints(tp);
6530
6531         tp->rx_mode &= ~RX_MODE_ENABLE;
6532         tw32_f(MAC_RX_MODE, tp->rx_mode);
6533         udelay(10);
6534
6535         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6536         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6537         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6538         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6539         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6540         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6541
6542         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6543         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6544         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6545         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6546         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6547         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6548         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6549
6550         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6551         tw32_f(MAC_MODE, tp->mac_mode);
6552         udelay(40);
6553
6554         tp->tx_mode &= ~TX_MODE_ENABLE;
6555         tw32_f(MAC_TX_MODE, tp->tx_mode);
6556
6557         for (i = 0; i < MAX_WAIT_CNT; i++) {
6558                 udelay(100);
6559                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6560                         break;
6561         }
6562         if (i >= MAX_WAIT_CNT) {
6563                 dev_err(&tp->pdev->dev,
6564                         "%s timed out, TX_MODE_ENABLE will not clear "
6565                         "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
6566                 err |= -ENODEV;
6567         }
6568
6569         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6570         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6571         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6572
6573         tw32(FTQ_RESET, 0xffffffff);
6574         tw32(FTQ_RESET, 0x00000000);
6575
6576         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6577         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6578
6579         for (i = 0; i < tp->irq_cnt; i++) {
6580                 struct tg3_napi *tnapi = &tp->napi[i];
6581                 if (tnapi->hw_status)
6582                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6583         }
6584         if (tp->hw_stats)
6585                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6586
6587         return err;
6588 }
6589
6590 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6591 {
6592         int i;
6593         u32 apedata;
6594
6595         /* NCSI does not support APE events */
6596         if (tp->tg3_flags3 & TG3_FLG3_APE_HAS_NCSI)
6597                 return;
6598
6599         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6600         if (apedata != APE_SEG_SIG_MAGIC)
6601                 return;
6602
6603         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6604         if (!(apedata & APE_FW_STATUS_READY))
6605                 return;
6606
6607         /* Wait for up to 1 millisecond for APE to service previous event. */
6608         for (i = 0; i < 10; i++) {
6609                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6610                         return;
6611
6612                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6613
6614                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6615                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6616                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6617
6618                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6619
6620                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6621                         break;
6622
6623                 udelay(100);
6624         }
6625
6626         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6627                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6628 }
6629
6630 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6631 {
6632         u32 event;
6633         u32 apedata;
6634
6635         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6636                 return;
6637
6638         switch (kind) {
6639         case RESET_KIND_INIT:
6640                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6641                                 APE_HOST_SEG_SIG_MAGIC);
6642                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6643                                 APE_HOST_SEG_LEN_MAGIC);
6644                 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6645                 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6646                 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6647                         APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
6648                 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6649                                 APE_HOST_BEHAV_NO_PHYLOCK);
6650                 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
6651                                     TG3_APE_HOST_DRVR_STATE_START);
6652
6653                 event = APE_EVENT_STATUS_STATE_START;
6654                 break;
6655         case RESET_KIND_SHUTDOWN:
6656                 /* With the interface we are currently using,
6657                  * APE does not track driver state.  Wiping
6658                  * out the HOST SEGMENT SIGNATURE forces
6659                  * the APE to assume OS absent status.
6660                  */
6661                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6662
6663                 if (device_may_wakeup(&tp->pdev->dev) &&
6664                     (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) {
6665                         tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
6666                                             TG3_APE_HOST_WOL_SPEED_AUTO);
6667                         apedata = TG3_APE_HOST_DRVR_STATE_WOL;
6668                 } else
6669                         apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
6670
6671                 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
6672
6673                 event = APE_EVENT_STATUS_STATE_UNLOAD;
6674                 break;
6675         case RESET_KIND_SUSPEND:
6676                 event = APE_EVENT_STATUS_STATE_SUSPEND;
6677                 break;
6678         default:
6679                 return;
6680         }
6681
6682         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6683
6684         tg3_ape_send_event(tp, event);
6685 }
6686
6687 /* tp->lock is held. */
6688 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6689 {
6690         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6691                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6692
6693         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6694                 switch (kind) {
6695                 case RESET_KIND_INIT:
6696                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6697                                       DRV_STATE_START);
6698                         break;
6699
6700                 case RESET_KIND_SHUTDOWN:
6701                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6702                                       DRV_STATE_UNLOAD);
6703                         break;
6704
6705                 case RESET_KIND_SUSPEND:
6706                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6707                                       DRV_STATE_SUSPEND);
6708                         break;
6709
6710                 default:
6711                         break;
6712                 }
6713         }
6714
6715         if (kind == RESET_KIND_INIT ||
6716             kind == RESET_KIND_SUSPEND)
6717                 tg3_ape_driver_state_change(tp, kind);
6718 }
6719
6720 /* tp->lock is held. */
6721 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6722 {
6723         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6724                 switch (kind) {
6725                 case RESET_KIND_INIT:
6726                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6727                                       DRV_STATE_START_DONE);
6728                         break;
6729
6730                 case RESET_KIND_SHUTDOWN:
6731                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6732                                       DRV_STATE_UNLOAD_DONE);
6733                         break;
6734
6735                 default:
6736                         break;
6737                 }
6738         }
6739
6740         if (kind == RESET_KIND_SHUTDOWN)
6741                 tg3_ape_driver_state_change(tp, kind);
6742 }
6743
6744 /* tp->lock is held. */
6745 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6746 {
6747         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6748                 switch (kind) {
6749                 case RESET_KIND_INIT:
6750                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6751                                       DRV_STATE_START);
6752                         break;
6753
6754                 case RESET_KIND_SHUTDOWN:
6755                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6756                                       DRV_STATE_UNLOAD);
6757                         break;
6758
6759                 case RESET_KIND_SUSPEND:
6760                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6761                                       DRV_STATE_SUSPEND);
6762                         break;
6763
6764                 default:
6765                         break;
6766                 }
6767         }
6768 }
6769
6770 static int tg3_poll_fw(struct tg3 *tp)
6771 {
6772         int i;
6773         u32 val;
6774
6775         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6776                 /* Wait up to 20ms for init done. */
6777                 for (i = 0; i < 200; i++) {
6778                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6779                                 return 0;
6780                         udelay(100);
6781                 }
6782                 return -ENODEV;
6783         }
6784
6785         /* Wait for firmware initialization to complete. */
6786         for (i = 0; i < 100000; i++) {
6787                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6788                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6789                         break;
6790                 udelay(10);
6791         }
6792
6793         /* Chip might not be fitted with firmware.  Some Sun onboard
6794          * parts are configured like that.  So don't signal the timeout
6795          * of the above loop as an error, but do report the lack of
6796          * running firmware once.
6797          */
6798         if (i >= 100000 &&
6799             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6800                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6801
6802                 netdev_info(tp->dev, "No firmware running\n");
6803         }
6804
6805         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6806                 /* The 57765 A0 needs a little more
6807                  * time to do some important work.
6808                  */
6809                 mdelay(10);
6810         }
6811
6812         return 0;
6813 }
6814
6815 /* Save PCI command register before chip reset */
6816 static void tg3_save_pci_state(struct tg3 *tp)
6817 {
6818         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6819 }
6820
6821 /* Restore PCI state after chip reset */
6822 static void tg3_restore_pci_state(struct tg3 *tp)
6823 {
6824         u32 val;
6825
6826         /* Re-enable indirect register accesses. */
6827         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6828                                tp->misc_host_ctrl);
6829
6830         /* Set MAX PCI retry to zero. */
6831         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6832         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6833             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6834                 val |= PCISTATE_RETRY_SAME_DMA;
6835         /* Allow reads and writes to the APE register and memory space. */
6836         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6837                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6838                        PCISTATE_ALLOW_APE_SHMEM_WR |
6839                        PCISTATE_ALLOW_APE_PSPACE_WR;
6840         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6841
6842         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6843
6844         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6845                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6846                         pcie_set_readrq(tp->pdev, 4096);
6847                 else {
6848                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6849                                               tp->pci_cacheline_sz);
6850                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6851                                               tp->pci_lat_timer);
6852                 }
6853         }
6854
6855         /* Make sure PCI-X relaxed ordering bit is clear. */
6856         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6857                 u16 pcix_cmd;
6858
6859                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6860                                      &pcix_cmd);
6861                 pcix_cmd &= ~PCI_X_CMD_ERO;
6862                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6863                                       pcix_cmd);
6864         }
6865
6866         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6867
6868                 /* Chip reset on 5780 will reset MSI enable bit,
6869                  * so need to restore it.
6870                  */
6871                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6872                         u16 ctrl;
6873
6874                         pci_read_config_word(tp->pdev,
6875                                              tp->msi_cap + PCI_MSI_FLAGS,
6876                                              &ctrl);
6877                         pci_write_config_word(tp->pdev,
6878                                               tp->msi_cap + PCI_MSI_FLAGS,
6879                                               ctrl | PCI_MSI_FLAGS_ENABLE);
6880                         val = tr32(MSGINT_MODE);
6881                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6882                 }
6883         }
6884 }
6885
6886 static void tg3_stop_fw(struct tg3 *);
6887
6888 /* tp->lock is held. */
6889 static int tg3_chip_reset(struct tg3 *tp)
6890 {
6891         u32 val;
6892         void (*write_op)(struct tg3 *, u32, u32);
6893         int i, err;
6894
6895         tg3_nvram_lock(tp);
6896
6897         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6898
6899         /* No matching tg3_nvram_unlock() after this because
6900          * chip reset below will undo the nvram lock.
6901          */
6902         tp->nvram_lock_cnt = 0;
6903
6904         /* GRC_MISC_CFG core clock reset will clear the memory
6905          * enable bit in PCI register 4 and the MSI enable bit
6906          * on some chips, so we save relevant registers here.
6907          */
6908         tg3_save_pci_state(tp);
6909
6910         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6911             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6912                 tw32(GRC_FASTBOOT_PC, 0);
6913
6914         /*
6915          * We must avoid the readl() that normally takes place.
6916          * It locks machines, causes machine checks, and other
6917          * fun things.  So, temporarily disable the 5701
6918          * hardware workaround, while we do the reset.
6919          */
6920         write_op = tp->write32;
6921         if (write_op == tg3_write_flush_reg32)
6922                 tp->write32 = tg3_write32;
6923
6924         /* Prevent the irq handler from reading or writing PCI registers
6925          * during chip reset when the memory enable bit in the PCI command
6926          * register may be cleared.  The chip does not generate interrupt
6927          * at this time, but the irq handler may still be called due to irq
6928          * sharing or irqpoll.
6929          */
6930         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6931         for (i = 0; i < tp->irq_cnt; i++) {
6932                 struct tg3_napi *tnapi = &tp->napi[i];
6933                 if (tnapi->hw_status) {
6934                         tnapi->hw_status->status = 0;
6935                         tnapi->hw_status->status_tag = 0;
6936                 }
6937                 tnapi->last_tag = 0;
6938                 tnapi->last_irq_tag = 0;
6939         }
6940         smp_mb();
6941
6942         for (i = 0; i < tp->irq_cnt; i++)
6943                 synchronize_irq(tp->napi[i].irq_vec);
6944
6945         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6946                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6947                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6948         }
6949
6950         /* do the reset */
6951         val = GRC_MISC_CFG_CORECLK_RESET;
6952
6953         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6954                 /* Force PCIe 1.0a mode */
6955                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
6956                     !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
6957                     tr32(TG3_PCIE_PHY_TSTCTL) ==
6958                     (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
6959                         tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
6960
6961                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6962                         tw32(GRC_MISC_CFG, (1 << 29));
6963                         val |= (1 << 29);
6964                 }
6965         }
6966
6967         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6968                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6969                 tw32(GRC_VCPU_EXT_CTRL,
6970                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6971         }
6972
6973         /* Manage gphy power for all CPMU absent PCIe devices. */
6974         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6975             !(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
6976                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6977
6978         tw32(GRC_MISC_CFG, val);
6979
6980         /* restore 5701 hardware bug workaround write method */
6981         tp->write32 = write_op;
6982
6983         /* Unfortunately, we have to delay before the PCI read back.
6984          * Some 575X chips even will not respond to a PCI cfg access
6985          * when the reset command is given to the chip.
6986          *
6987          * How do these hardware designers expect things to work
6988          * properly if the PCI write is posted for a long period
6989          * of time?  It is always necessary to have some method by
6990          * which a register read back can occur to push the write
6991          * out which does the reset.
6992          *
6993          * For most tg3 variants the trick below was working.
6994          * Ho hum...
6995          */
6996         udelay(120);
6997
6998         /* Flush PCI posted writes.  The normal MMIO registers
6999          * are inaccessible at this time so this is the only
7000          * way to make this reliably (actually, this is no longer
7001          * the case, see above).  I tried to use indirect
7002          * register read/write but this upset some 5701 variants.
7003          */
7004         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
7005
7006         udelay(120);
7007
7008         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
7009                 u16 val16;
7010
7011                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
7012                         int i;
7013                         u32 cfg_val;
7014
7015                         /* Wait for link training to complete.  */
7016                         for (i = 0; i < 5000; i++)
7017                                 udelay(100);
7018
7019                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
7020                         pci_write_config_dword(tp->pdev, 0xc4,
7021                                                cfg_val | (1 << 15));
7022                 }
7023
7024                 /* Clear the "no snoop" and "relaxed ordering" bits. */
7025                 pci_read_config_word(tp->pdev,
7026                                      tp->pcie_cap + PCI_EXP_DEVCTL,
7027                                      &val16);
7028                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
7029                            PCI_EXP_DEVCTL_NOSNOOP_EN);
7030                 /*
7031                  * Older PCIe devices only support the 128 byte
7032                  * MPS setting.  Enforce the restriction.
7033                  */
7034                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7035                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
7036                 pci_write_config_word(tp->pdev,
7037                                       tp->pcie_cap + PCI_EXP_DEVCTL,
7038                                       val16);
7039
7040                 pcie_set_readrq(tp->pdev, 4096);
7041
7042                 /* Clear error status */
7043                 pci_write_config_word(tp->pdev,
7044                                       tp->pcie_cap + PCI_EXP_DEVSTA,
7045                                       PCI_EXP_DEVSTA_CED |
7046                                       PCI_EXP_DEVSTA_NFED |
7047                                       PCI_EXP_DEVSTA_FED |
7048                                       PCI_EXP_DEVSTA_URD);
7049         }
7050
7051         tg3_restore_pci_state(tp);
7052
7053         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
7054
7055         val = 0;
7056         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
7057                 val = tr32(MEMARB_MODE);
7058         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7059
7060         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7061                 tg3_stop_fw(tp);
7062                 tw32(0x5000, 0x400);
7063         }
7064
7065         tw32(GRC_MODE, tp->grc_mode);
7066
7067         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
7068                 val = tr32(0xc4);
7069
7070                 tw32(0xc4, val | (1 << 15));
7071         }
7072
7073         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7074             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7075                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7076                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7077                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7078                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7079         }
7080
7081         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
7082                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
7083                 tw32_f(MAC_MODE, tp->mac_mode);
7084         } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
7085                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
7086                 tw32_f(MAC_MODE, tp->mac_mode);
7087         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7088                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
7089                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
7090                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
7091                 tw32_f(MAC_MODE, tp->mac_mode);
7092         } else
7093                 tw32_f(MAC_MODE, 0);
7094         udelay(40);
7095
7096         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7097
7098         err = tg3_poll_fw(tp);
7099         if (err)
7100                 return err;
7101
7102         tg3_mdio_start(tp);
7103
7104         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
7105             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7106             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7107             !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
7108                 val = tr32(0x7c00);
7109
7110                 tw32(0x7c00, val | (1 << 25));
7111         }
7112
7113         /* Reprobe ASF enable state.  */
7114         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7115         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7116         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7117         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7118                 u32 nic_cfg;
7119
7120                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7121                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7122                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7123                         tp->last_event_jiffies = jiffies;
7124                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7125                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7126                 }
7127         }
7128
7129         return 0;
7130 }
7131
7132 /* tp->lock is held. */
7133 static void tg3_stop_fw(struct tg3 *tp)
7134 {
7135         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7136            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7137                 /* Wait for RX cpu to ACK the previous event. */
7138                 tg3_wait_for_event_ack(tp);
7139
7140                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7141
7142                 tg3_generate_fw_event(tp);
7143
7144                 /* Wait for RX cpu to ACK this event. */
7145                 tg3_wait_for_event_ack(tp);
7146         }
7147 }
7148
7149 /* tp->lock is held. */
7150 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7151 {
7152         int err;
7153
7154         tg3_stop_fw(tp);
7155
7156         tg3_write_sig_pre_reset(tp, kind);
7157
7158         tg3_abort_hw(tp, silent);
7159         err = tg3_chip_reset(tp);
7160
7161         __tg3_set_mac_addr(tp, 0);
7162
7163         tg3_write_sig_legacy(tp, kind);
7164         tg3_write_sig_post_reset(tp, kind);
7165
7166         if (err)
7167                 return err;
7168
7169         return 0;
7170 }
7171
7172 #define RX_CPU_SCRATCH_BASE     0x30000
7173 #define RX_CPU_SCRATCH_SIZE     0x04000
7174 #define TX_CPU_SCRATCH_BASE     0x34000
7175 #define TX_CPU_SCRATCH_SIZE     0x04000
7176
7177 /* tp->lock is held. */
7178 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7179 {
7180         int i;
7181
7182         BUG_ON(offset == TX_CPU_BASE &&
7183             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7184
7185         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7186                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7187
7188                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7189                 return 0;
7190         }
7191         if (offset == RX_CPU_BASE) {
7192                 for (i = 0; i < 10000; i++) {
7193                         tw32(offset + CPU_STATE, 0xffffffff);
7194                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7195                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7196                                 break;
7197                 }
7198
7199                 tw32(offset + CPU_STATE, 0xffffffff);
7200                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
7201                 udelay(10);
7202         } else {
7203                 for (i = 0; i < 10000; i++) {
7204                         tw32(offset + CPU_STATE, 0xffffffff);
7205                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7206                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7207                                 break;
7208                 }
7209         }
7210
7211         if (i >= 10000) {
7212                 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7213                            __func__, offset == RX_CPU_BASE ? "RX" : "TX");
7214                 return -ENODEV;
7215         }
7216
7217         /* Clear firmware's nvram arbitration. */
7218         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7219                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7220         return 0;
7221 }
7222
7223 struct fw_info {
7224         unsigned int fw_base;
7225         unsigned int fw_len;
7226         const __be32 *fw_data;
7227 };
7228
7229 /* tp->lock is held. */
7230 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7231                                  int cpu_scratch_size, struct fw_info *info)
7232 {
7233         int err, lock_err, i;
7234         void (*write_op)(struct tg3 *, u32, u32);
7235
7236         if (cpu_base == TX_CPU_BASE &&
7237             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7238                 netdev_err(tp->dev,
7239                            "%s: Trying to load TX cpu firmware which is 5705\n",
7240                            __func__);
7241                 return -EINVAL;
7242         }
7243
7244         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7245                 write_op = tg3_write_mem;
7246         else
7247                 write_op = tg3_write_indirect_reg32;
7248
7249         /* It is possible that bootcode is still loading at this point.
7250          * Get the nvram lock first before halting the cpu.
7251          */
7252         lock_err = tg3_nvram_lock(tp);
7253         err = tg3_halt_cpu(tp, cpu_base);
7254         if (!lock_err)
7255                 tg3_nvram_unlock(tp);
7256         if (err)
7257                 goto out;
7258
7259         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7260                 write_op(tp, cpu_scratch_base + i, 0);
7261         tw32(cpu_base + CPU_STATE, 0xffffffff);
7262         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7263         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7264                 write_op(tp, (cpu_scratch_base +
7265                               (info->fw_base & 0xffff) +
7266                               (i * sizeof(u32))),
7267                               be32_to_cpu(info->fw_data[i]));
7268
7269         err = 0;
7270
7271 out:
7272         return err;
7273 }
7274
7275 /* tp->lock is held. */
7276 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7277 {
7278         struct fw_info info;
7279         const __be32 *fw_data;
7280         int err, i;
7281
7282         fw_data = (void *)tp->fw->data;
7283
7284         /* Firmware blob starts with version numbers, followed by
7285            start address and length. We are setting complete length.
7286            length = end_address_of_bss - start_address_of_text.
7287            Remainder is the blob to be loaded contiguously
7288            from start address. */
7289
7290         info.fw_base = be32_to_cpu(fw_data[1]);
7291         info.fw_len = tp->fw->size - 12;
7292         info.fw_data = &fw_data[3];
7293
7294         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7295                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7296                                     &info);
7297         if (err)
7298                 return err;
7299
7300         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7301                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7302                                     &info);
7303         if (err)
7304                 return err;
7305
7306         /* Now startup only the RX cpu. */
7307         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7308         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7309
7310         for (i = 0; i < 5; i++) {
7311                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7312                         break;
7313                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7314                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
7315                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7316                 udelay(1000);
7317         }
7318         if (i >= 5) {
7319                 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7320                            "should be %08x\n", __func__,
7321                            tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
7322                 return -ENODEV;
7323         }
7324         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7325         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
7326
7327         return 0;
7328 }
7329
7330 /* 5705 needs a special version of the TSO firmware.  */
7331
7332 /* tp->lock is held. */
7333 static int tg3_load_tso_firmware(struct tg3 *tp)
7334 {
7335         struct fw_info info;
7336         const __be32 *fw_data;
7337         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7338         int err, i;
7339
7340         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7341                 return 0;
7342
7343         fw_data = (void *)tp->fw->data;
7344
7345         /* Firmware blob starts with version numbers, followed by
7346            start address and length. We are setting complete length.
7347            length = end_address_of_bss - start_address_of_text.
7348            Remainder is the blob to be loaded contiguously
7349            from start address. */
7350
7351         info.fw_base = be32_to_cpu(fw_data[1]);
7352         cpu_scratch_size = tp->fw_len;
7353         info.fw_len = tp->fw->size - 12;
7354         info.fw_data = &fw_data[3];
7355
7356         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7357                 cpu_base = RX_CPU_BASE;
7358                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7359         } else {
7360                 cpu_base = TX_CPU_BASE;
7361                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7362                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7363         }
7364
7365         err = tg3_load_firmware_cpu(tp, cpu_base,
7366                                     cpu_scratch_base, cpu_scratch_size,
7367                                     &info);
7368         if (err)
7369                 return err;
7370
7371         /* Now startup the cpu. */
7372         tw32(cpu_base + CPU_STATE, 0xffffffff);
7373         tw32_f(cpu_base + CPU_PC, info.fw_base);
7374
7375         for (i = 0; i < 5; i++) {
7376                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7377                         break;
7378                 tw32(cpu_base + CPU_STATE, 0xffffffff);
7379                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
7380                 tw32_f(cpu_base + CPU_PC, info.fw_base);
7381                 udelay(1000);
7382         }
7383         if (i >= 5) {
7384                 netdev_err(tp->dev,
7385                            "%s fails to set CPU PC, is %08x should be %08x\n",
7386                            __func__, tr32(cpu_base + CPU_PC), info.fw_base);
7387                 return -ENODEV;
7388         }
7389         tw32(cpu_base + CPU_STATE, 0xffffffff);
7390         tw32_f(cpu_base + CPU_MODE,  0x00000000);
7391         return 0;
7392 }
7393
7394
7395 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7396 {
7397         struct tg3 *tp = netdev_priv(dev);
7398         struct sockaddr *addr = p;
7399         int err = 0, skip_mac_1 = 0;
7400
7401         if (!is_valid_ether_addr(addr->sa_data))
7402                 return -EINVAL;
7403
7404         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7405
7406         if (!netif_running(dev))
7407                 return 0;
7408
7409         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7410                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7411
7412                 addr0_high = tr32(MAC_ADDR_0_HIGH);
7413                 addr0_low = tr32(MAC_ADDR_0_LOW);
7414                 addr1_high = tr32(MAC_ADDR_1_HIGH);
7415                 addr1_low = tr32(MAC_ADDR_1_LOW);
7416
7417                 /* Skip MAC addr 1 if ASF is using it. */
7418                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7419                     !(addr1_high == 0 && addr1_low == 0))
7420                         skip_mac_1 = 1;
7421         }
7422         spin_lock_bh(&tp->lock);
7423         __tg3_set_mac_addr(tp, skip_mac_1);
7424         spin_unlock_bh(&tp->lock);
7425
7426         return err;
7427 }
7428
7429 /* tp->lock is held. */
7430 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7431                            dma_addr_t mapping, u32 maxlen_flags,
7432                            u32 nic_addr)
7433 {
7434         tg3_write_mem(tp,
7435                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7436                       ((u64) mapping >> 32));
7437         tg3_write_mem(tp,
7438                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7439                       ((u64) mapping & 0xffffffff));
7440         tg3_write_mem(tp,
7441                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7442                        maxlen_flags);
7443
7444         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7445                 tg3_write_mem(tp,
7446                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7447                               nic_addr);
7448 }
7449
7450 static void __tg3_set_rx_mode(struct net_device *);
7451 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7452 {
7453         int i;
7454
7455         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7456                 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7457                 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7458                 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7459         } else {
7460                 tw32(HOSTCC_TXCOL_TICKS, 0);
7461                 tw32(HOSTCC_TXMAX_FRAMES, 0);
7462                 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7463         }
7464
7465         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
7466                 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7467                 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7468                 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7469         } else {
7470                 tw32(HOSTCC_RXCOL_TICKS, 0);
7471                 tw32(HOSTCC_RXMAX_FRAMES, 0);
7472                 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7473         }
7474
7475         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7476                 u32 val = ec->stats_block_coalesce_usecs;
7477
7478                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7479                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7480
7481                 if (!netif_carrier_ok(tp->dev))
7482                         val = 0;
7483
7484                 tw32(HOSTCC_STAT_COAL_TICKS, val);
7485         }
7486
7487         for (i = 0; i < tp->irq_cnt - 1; i++) {
7488                 u32 reg;
7489
7490                 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7491                 tw32(reg, ec->rx_coalesce_usecs);
7492                 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7493                 tw32(reg, ec->rx_max_coalesced_frames);
7494                 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7495                 tw32(reg, ec->rx_max_coalesced_frames_irq);
7496
7497                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7498                         reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7499                         tw32(reg, ec->tx_coalesce_usecs);
7500                         reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7501                         tw32(reg, ec->tx_max_coalesced_frames);
7502                         reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7503                         tw32(reg, ec->tx_max_coalesced_frames_irq);
7504                 }
7505         }
7506
7507         for (; i < tp->irq_max - 1; i++) {
7508                 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7509                 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7510                 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7511
7512                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7513                         tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7514                         tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7515                         tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7516                 }
7517         }
7518 }
7519
7520 /* tp->lock is held. */
7521 static void tg3_rings_reset(struct tg3 *tp)
7522 {
7523         int i;
7524         u32 stblk, txrcb, rxrcb, limit;
7525         struct tg3_napi *tnapi = &tp->napi[0];
7526
7527         /* Disable all transmit rings but the first. */
7528         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7529                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7530         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7531                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7532         else
7533                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7534
7535         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7536              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7537                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7538                               BDINFO_FLAGS_DISABLED);
7539
7540
7541         /* Disable all receive return rings but the first. */
7542         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7543             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7544                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7545         else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7546                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7547         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7548                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7549                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7550         else
7551                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7552
7553         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7554              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7555                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7556                               BDINFO_FLAGS_DISABLED);
7557
7558         /* Disable interrupts */
7559         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7560
7561         /* Zero mailbox registers. */
7562         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7563                 for (i = 1; i < tp->irq_max; i++) {
7564                         tp->napi[i].tx_prod = 0;
7565                         tp->napi[i].tx_cons = 0;
7566                         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7567                                 tw32_mailbox(tp->napi[i].prodmbox, 0);
7568                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
7569                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7570                 }
7571                 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7572                         tw32_mailbox(tp->napi[0].prodmbox, 0);
7573         } else {
7574                 tp->napi[0].tx_prod = 0;
7575                 tp->napi[0].tx_cons = 0;
7576                 tw32_mailbox(tp->napi[0].prodmbox, 0);
7577                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7578         }
7579
7580         /* Make sure the NIC-based send BD rings are disabled. */
7581         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7582                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7583                 for (i = 0; i < 16; i++)
7584                         tw32_tx_mbox(mbox + i * 8, 0);
7585         }
7586
7587         txrcb = NIC_SRAM_SEND_RCB;
7588         rxrcb = NIC_SRAM_RCV_RET_RCB;
7589
7590         /* Clear status block in ram. */
7591         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7592
7593         /* Set status block DMA address */
7594         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7595              ((u64) tnapi->status_mapping >> 32));
7596         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7597              ((u64) tnapi->status_mapping & 0xffffffff));
7598
7599         if (tnapi->tx_ring) {
7600                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7601                                (TG3_TX_RING_SIZE <<
7602                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7603                                NIC_SRAM_TX_BUFFER_DESC);
7604                 txrcb += TG3_BDINFO_SIZE;
7605         }
7606
7607         if (tnapi->rx_rcb) {
7608                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7609                                (TG3_RX_RCB_RING_SIZE(tp) <<
7610                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7611                 rxrcb += TG3_BDINFO_SIZE;
7612         }
7613
7614         stblk = HOSTCC_STATBLCK_RING1;
7615
7616         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7617                 u64 mapping = (u64)tnapi->status_mapping;
7618                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7619                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7620
7621                 /* Clear status block in ram. */
7622                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7623
7624                 if (tnapi->tx_ring) {
7625                         tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7626                                        (TG3_TX_RING_SIZE <<
7627                                         BDINFO_FLAGS_MAXLEN_SHIFT),
7628                                        NIC_SRAM_TX_BUFFER_DESC);
7629                         txrcb += TG3_BDINFO_SIZE;
7630                 }
7631
7632                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7633                                (TG3_RX_RCB_RING_SIZE(tp) <<
7634                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7635
7636                 stblk += 8;
7637                 rxrcb += TG3_BDINFO_SIZE;
7638         }
7639 }
7640
7641 /* tp->lock is held. */
7642 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7643 {
7644         u32 val, rdmac_mode;
7645         int i, err, limit;
7646         struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
7647
7648         tg3_disable_ints(tp);
7649
7650         tg3_stop_fw(tp);
7651
7652         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7653
7654         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
7655                 tg3_abort_hw(tp, 1);
7656
7657         if (reset_phy)
7658                 tg3_phy_reset(tp);
7659
7660         err = tg3_chip_reset(tp);
7661         if (err)
7662                 return err;
7663
7664         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7665
7666         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7667                 val = tr32(TG3_CPMU_CTRL);
7668                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7669                 tw32(TG3_CPMU_CTRL, val);
7670
7671                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7672                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7673                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7674                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7675
7676                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7677                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7678                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7679                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7680
7681                 val = tr32(TG3_CPMU_HST_ACC);
7682                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7683                 val |= CPMU_HST_ACC_MACCLK_6_25;
7684                 tw32(TG3_CPMU_HST_ACC, val);
7685         }
7686
7687         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7688                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7689                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7690                        PCIE_PWR_MGMT_L1_THRESH_4MS;
7691                 tw32(PCIE_PWR_MGMT_THRESH, val);
7692
7693                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7694                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7695
7696                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7697
7698                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7699                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7700         }
7701
7702         if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7703                 u32 grc_mode = tr32(GRC_MODE);
7704
7705                 /* Access the lower 1K of PL PCIE block registers. */
7706                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7707                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7708
7709                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7710                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7711                      val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7712
7713                 tw32(GRC_MODE, grc_mode);
7714         }
7715
7716         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
7717                 u32 grc_mode = tr32(GRC_MODE);
7718
7719                 /* Access the lower 1K of PL PCIE block registers. */
7720                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7721                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7722
7723                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5);
7724                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
7725                      val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
7726
7727                 tw32(GRC_MODE, grc_mode);
7728
7729                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7730                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7731                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7732                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7733         }
7734
7735         /* This works around an issue with Athlon chipsets on
7736          * B3 tigon3 silicon.  This bit has no effect on any
7737          * other revision.  But do not set this on PCI Express
7738          * chips and don't even touch the clocks if the CPMU is present.
7739          */
7740         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7741                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7742                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7743                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7744         }
7745
7746         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7747             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7748                 val = tr32(TG3PCI_PCISTATE);
7749                 val |= PCISTATE_RETRY_SAME_DMA;
7750                 tw32(TG3PCI_PCISTATE, val);
7751         }
7752
7753         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7754                 /* Allow reads and writes to the
7755                  * APE register and memory space.
7756                  */
7757                 val = tr32(TG3PCI_PCISTATE);
7758                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7759                        PCISTATE_ALLOW_APE_SHMEM_WR |
7760                        PCISTATE_ALLOW_APE_PSPACE_WR;
7761                 tw32(TG3PCI_PCISTATE, val);
7762         }
7763
7764         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7765                 /* Enable some hw fixes.  */
7766                 val = tr32(TG3PCI_MSI_DATA);
7767                 val |= (1 << 26) | (1 << 28) | (1 << 29);
7768                 tw32(TG3PCI_MSI_DATA, val);
7769         }
7770
7771         /* Descriptor ring init may make accesses to the
7772          * NIC SRAM area to setup the TX descriptors, so we
7773          * can only do this after the hardware has been
7774          * successfully reset.
7775          */
7776         err = tg3_init_rings(tp);
7777         if (err)
7778                 return err;
7779
7780         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
7781                 val = tr32(TG3PCI_DMA_RW_CTRL) &
7782                       ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7783                 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
7784                         val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
7785                 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7786         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7787                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7788                 /* This value is determined during the probe time DMA
7789                  * engine test, tg3_test_dma.
7790                  */
7791                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7792         }
7793
7794         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7795                           GRC_MODE_4X_NIC_SEND_RINGS |
7796                           GRC_MODE_NO_TX_PHDR_CSUM |
7797                           GRC_MODE_NO_RX_PHDR_CSUM);
7798         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7799
7800         /* Pseudo-header checksum is done by hardware logic and not
7801          * the offload processers, so make the chip do the pseudo-
7802          * header checksums on receive.  For transmit it is more
7803          * convenient to do the pseudo-header checksum in software
7804          * as Linux does that on transmit for us in all cases.
7805          */
7806         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7807
7808         tw32(GRC_MODE,
7809              tp->grc_mode |
7810              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7811
7812         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7813         val = tr32(GRC_MISC_CFG);
7814         val &= ~0xff;
7815         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7816         tw32(GRC_MISC_CFG, val);
7817
7818         /* Initialize MBUF/DESC pool. */
7819         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7820                 /* Do nothing.  */
7821         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7822                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7823                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7824                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7825                 else
7826                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7827                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7828                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7829         } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7830                 int fw_len;
7831
7832                 fw_len = tp->fw_len;
7833                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7834                 tw32(BUFMGR_MB_POOL_ADDR,
7835                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7836                 tw32(BUFMGR_MB_POOL_SIZE,
7837                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7838         }
7839
7840         if (tp->dev->mtu <= ETH_DATA_LEN) {
7841                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7842                      tp->bufmgr_config.mbuf_read_dma_low_water);
7843                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7844                      tp->bufmgr_config.mbuf_mac_rx_low_water);
7845                 tw32(BUFMGR_MB_HIGH_WATER,
7846                      tp->bufmgr_config.mbuf_high_water);
7847         } else {
7848                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7849                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7850                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7851                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7852                 tw32(BUFMGR_MB_HIGH_WATER,
7853                      tp->bufmgr_config.mbuf_high_water_jumbo);
7854         }
7855         tw32(BUFMGR_DMA_LOW_WATER,
7856              tp->bufmgr_config.dma_low_water);
7857         tw32(BUFMGR_DMA_HIGH_WATER,
7858              tp->bufmgr_config.dma_high_water);
7859
7860         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7861         for (i = 0; i < 2000; i++) {
7862                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7863                         break;
7864                 udelay(10);
7865         }
7866         if (i >= 2000) {
7867                 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
7868                 return -ENODEV;
7869         }
7870
7871         /* Setup replenish threshold. */
7872         val = tp->rx_pending / 8;
7873         if (val == 0)
7874                 val = 1;
7875         else if (val > tp->rx_std_max_post)
7876                 val = tp->rx_std_max_post;
7877         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7878                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7879                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7880
7881                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7882                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7883         }
7884
7885         tw32(RCVBDI_STD_THRESH, val);
7886
7887         /* Initialize TG3_BDINFO's at:
7888          *  RCVDBDI_STD_BD:     standard eth size rx ring
7889          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
7890          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
7891          *
7892          * like so:
7893          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
7894          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
7895          *                              ring attribute flags
7896          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
7897          *
7898          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7899          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7900          *
7901          * The size of each ring is fixed in the firmware, but the location is
7902          * configurable.
7903          */
7904         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7905              ((u64) tpr->rx_std_mapping >> 32));
7906         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7907              ((u64) tpr->rx_std_mapping & 0xffffffff));
7908         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
7909             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
7910                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7911                      NIC_SRAM_RX_BUFFER_DESC);
7912
7913         /* Disable the mini ring */
7914         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7915                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7916                      BDINFO_FLAGS_DISABLED);
7917
7918         /* Program the jumbo buffer descriptor ring control
7919          * blocks on those devices that have them.
7920          */
7921         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7922             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7923                 /* Setup replenish threshold. */
7924                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7925
7926                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7927                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7928                              ((u64) tpr->rx_jmb_mapping >> 32));
7929                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7930                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7931                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7932                              (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7933                              BDINFO_FLAGS_USE_EXT_RECV);
7934                         if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) ||
7935                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7936                                 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7937                                      NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7938                 } else {
7939                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7940                              BDINFO_FLAGS_DISABLED);
7941                 }
7942
7943                 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
7944                         val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7945                               (TG3_RX_STD_DMA_SZ << 2);
7946                 else
7947                         val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
7948         } else
7949                 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7950
7951         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7952
7953         tpr->rx_std_prod_idx = tp->rx_pending;
7954         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
7955
7956         tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7957                           tp->rx_jumbo_pending : 0;
7958         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
7959
7960         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
7961                 tw32(STD_REPLENISH_LWM, 32);
7962                 tw32(JMB_REPLENISH_LWM, 16);
7963         }
7964
7965         tg3_rings_reset(tp);
7966
7967         /* Initialize MAC address and backoff seed. */
7968         __tg3_set_mac_addr(tp, 0);
7969
7970         /* MTU + ethernet header + FCS + optional VLAN tag */
7971         tw32(MAC_RX_MTU_SIZE,
7972              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7973
7974         /* The slot time is changed by tg3_setup_phy if we
7975          * run at gigabit with half duplex.
7976          */
7977         tw32(MAC_TX_LENGTHS,
7978              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7979              (6 << TX_LENGTHS_IPG_SHIFT) |
7980              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7981
7982         /* Receive rules. */
7983         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7984         tw32(RCVLPC_CONFIG, 0x0181);
7985
7986         /* Calculate RDMAC_MODE setting early, we need it to determine
7987          * the RCVLPC_STATE_ENABLE mask.
7988          */
7989         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7990                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7991                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7992                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7993                       RDMAC_MODE_LNGREAD_ENAB);
7994
7995         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7996             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7997                 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
7998
7999         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8000             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8001             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8002                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
8003                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
8004                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
8005
8006         /* If statement applies to 5705 and 5750 PCI devices only */
8007         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8008              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8009             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
8010                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
8011                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
8012                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
8013                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8014                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
8015                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8016                 }
8017         }
8018
8019         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
8020                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8021
8022         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8023                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8024
8025         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
8026             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8027             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8028                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
8029
8030         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8031             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8032             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8033             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
8034             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
8035                 val = tr32(TG3_RDMA_RSRVCTRL_REG);
8036                 tw32(TG3_RDMA_RSRVCTRL_REG,
8037                      val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
8038         }
8039
8040         /* Receive/send statistics. */
8041         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
8042                 val = tr32(RCVLPC_STATS_ENABLE);
8043                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8044                 tw32(RCVLPC_STATS_ENABLE, val);
8045         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8046                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8047                 val = tr32(RCVLPC_STATS_ENABLE);
8048                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8049                 tw32(RCVLPC_STATS_ENABLE, val);
8050         } else {
8051                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8052         }
8053         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8054         tw32(SNDDATAI_STATSENAB, 0xffffff);
8055         tw32(SNDDATAI_STATSCTRL,
8056              (SNDDATAI_SCTRL_ENABLE |
8057               SNDDATAI_SCTRL_FASTUPD));
8058
8059         /* Setup host coalescing engine. */
8060         tw32(HOSTCC_MODE, 0);
8061         for (i = 0; i < 2000; i++) {
8062                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8063                         break;
8064                 udelay(10);
8065         }
8066
8067         __tg3_set_coalesce(tp, &tp->coal);
8068
8069         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8070                 /* Status/statistics block address.  See tg3_timer,
8071                  * the tg3_periodic_fetch_stats call there, and
8072                  * tg3_get_stats to see how this works for 5705/5750 chips.
8073                  */
8074                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8075                      ((u64) tp->stats_mapping >> 32));
8076                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8077                      ((u64) tp->stats_mapping & 0xffffffff));
8078                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8079
8080                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
8081
8082                 /* Clear statistics and status block memory areas */
8083                 for (i = NIC_SRAM_STATS_BLK;
8084                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8085                      i += sizeof(u32)) {
8086                         tg3_write_mem(tp, i, 0);
8087                         udelay(40);
8088                 }
8089         }
8090
8091         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8092
8093         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8094         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8095         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8096                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8097
8098         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
8099                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
8100                 /* reset to prevent losing 1st rx packet intermittently */
8101                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8102                 udelay(10);
8103         }
8104
8105         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8106                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8107         else
8108                 tp->mac_mode = 0;
8109         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8110                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
8111         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8112             !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8113             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8114                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8115         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8116         udelay(40);
8117
8118         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8119          * If TG3_FLG2_IS_NIC is zero, we should read the
8120          * register to preserve the GPIO settings for LOMs. The GPIOs,
8121          * whether used as inputs or outputs, are set by boot code after
8122          * reset.
8123          */
8124         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
8125                 u32 gpio_mask;
8126
8127                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8128                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8129                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8130
8131                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8132                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8133                                      GRC_LCLCTRL_GPIO_OUTPUT3;
8134
8135                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8136                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8137
8138                 tp->grc_local_ctrl &= ~gpio_mask;
8139                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8140
8141                 /* GPIO1 must be driven high for eeprom write protect */
8142                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8143                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8144                                                GRC_LCLCTRL_GPIO_OUTPUT1);
8145         }
8146         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8147         udelay(100);
8148
8149         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
8150                 val = tr32(MSGINT_MODE);
8151                 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8152                 tw32(MSGINT_MODE, val);
8153         }
8154
8155         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8156                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8157                 udelay(40);
8158         }
8159
8160         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8161                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8162                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8163                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8164                WDMAC_MODE_LNGREAD_ENAB);
8165
8166         /* If statement applies to 5705 and 5750 PCI devices only */
8167         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8168              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8169             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
8170                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8171                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8172                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8173                         /* nothing */
8174                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8175                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8176                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8177                         val |= WDMAC_MODE_RX_ACCEL;
8178                 }
8179         }
8180
8181         /* Enable host coalescing bug fix */
8182         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8183                 val |= WDMAC_MODE_STATUS_TAG_FIX;
8184
8185         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8186                 val |= WDMAC_MODE_BURST_ALL_DATA;
8187
8188         tw32_f(WDMAC_MODE, val);
8189         udelay(40);
8190
8191         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8192                 u16 pcix_cmd;
8193
8194                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8195                                      &pcix_cmd);
8196                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8197                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8198                         pcix_cmd |= PCI_X_CMD_READ_2K;
8199                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8200                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8201                         pcix_cmd |= PCI_X_CMD_READ_2K;
8202                 }
8203                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8204                                       pcix_cmd);
8205         }
8206
8207         tw32_f(RDMAC_MODE, rdmac_mode);
8208         udelay(40);
8209
8210         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8211         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8212                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8213
8214         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8215                 tw32(SNDDATAC_MODE,
8216                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8217         else
8218                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8219
8220         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8221         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8222         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8223         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8224         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8225                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8226         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8227         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8228                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8229         tw32(SNDBDI_MODE, val);
8230         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8231
8232         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8233                 err = tg3_load_5701_a0_firmware_fix(tp);
8234                 if (err)
8235                         return err;
8236         }
8237
8238         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8239                 err = tg3_load_tso_firmware(tp);
8240                 if (err)
8241                         return err;
8242         }
8243
8244         tp->tx_mode = TX_MODE_ENABLE;
8245         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
8246             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8247                 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
8248         tw32_f(MAC_TX_MODE, tp->tx_mode);
8249         udelay(100);
8250
8251         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8252                 u32 reg = MAC_RSS_INDIR_TBL_0;
8253                 u8 *ent = (u8 *)&val;
8254
8255                 /* Setup the indirection table */
8256                 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8257                         int idx = i % sizeof(val);
8258
8259                         ent[idx] = i % (tp->irq_cnt - 1);
8260                         if (idx == sizeof(val) - 1) {
8261                                 tw32(reg, val);
8262                                 reg += 4;
8263                         }
8264                 }
8265
8266                 /* Setup the "secret" hash key. */
8267                 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8268                 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8269                 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8270                 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8271                 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8272                 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8273                 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8274                 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8275                 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8276                 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8277         }
8278
8279         tp->rx_mode = RX_MODE_ENABLE;
8280         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8281                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8282
8283         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8284                 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8285                                RX_MODE_RSS_ITBL_HASH_BITS_7 |
8286                                RX_MODE_RSS_IPV6_HASH_EN |
8287                                RX_MODE_RSS_TCP_IPV6_HASH_EN |
8288                                RX_MODE_RSS_IPV4_HASH_EN |
8289                                RX_MODE_RSS_TCP_IPV4_HASH_EN;
8290
8291         tw32_f(MAC_RX_MODE, tp->rx_mode);
8292         udelay(10);
8293
8294         tw32(MAC_LED_CTRL, tp->led_ctrl);
8295
8296         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8297         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8298                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8299                 udelay(10);
8300         }
8301         tw32_f(MAC_RX_MODE, tp->rx_mode);
8302         udelay(10);
8303
8304         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8305                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8306                         !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
8307                         /* Set drive transmission level to 1.2V  */
8308                         /* only if the signal pre-emphasis bit is not set  */
8309                         val = tr32(MAC_SERDES_CFG);
8310                         val &= 0xfffff000;
8311                         val |= 0x880;
8312                         tw32(MAC_SERDES_CFG, val);
8313                 }
8314                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8315                         tw32(MAC_SERDES_CFG, 0x616000);
8316         }
8317
8318         /* Prevent chip from dropping frames when flow control
8319          * is enabled.
8320          */
8321         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8322                 val = 1;
8323         else
8324                 val = 2;
8325         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8326
8327         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8328             (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
8329                 /* Use hardware link auto-negotiation */
8330                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8331         }
8332
8333         if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8334             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8335                 u32 tmp;
8336
8337                 tmp = tr32(SERDES_RX_CTRL);
8338                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8339                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8340                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8341                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8342         }
8343
8344         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8345                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
8346                         tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
8347                         tp->link_config.speed = tp->link_config.orig_speed;
8348                         tp->link_config.duplex = tp->link_config.orig_duplex;
8349                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
8350                 }
8351
8352                 err = tg3_setup_phy(tp, 0);
8353                 if (err)
8354                         return err;
8355
8356                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8357                     !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8358                         u32 tmp;
8359
8360                         /* Clear CRC stats. */
8361                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8362                                 tg3_writephy(tp, MII_TG3_TEST1,
8363                                              tmp | MII_TG3_TEST1_CRC_EN);
8364                                 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
8365                         }
8366                 }
8367         }
8368
8369         __tg3_set_rx_mode(tp->dev);
8370
8371         /* Initialize receive rules. */
8372         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
8373         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8374         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
8375         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8376
8377         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8378             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8379                 limit = 8;
8380         else
8381                 limit = 16;
8382         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8383                 limit -= 4;
8384         switch (limit) {
8385         case 16:
8386                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
8387         case 15:
8388                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
8389         case 14:
8390                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
8391         case 13:
8392                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
8393         case 12:
8394                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
8395         case 11:
8396                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
8397         case 10:
8398                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
8399         case 9:
8400                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
8401         case 8:
8402                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
8403         case 7:
8404                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
8405         case 6:
8406                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
8407         case 5:
8408                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
8409         case 4:
8410                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
8411         case 3:
8412                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
8413         case 2:
8414         case 1:
8415
8416         default:
8417                 break;
8418         }
8419
8420         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8421                 /* Write our heartbeat update interval to APE. */
8422                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8423                                 APE_HOST_HEARTBEAT_INT_DISABLE);
8424
8425         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8426
8427         return 0;
8428 }
8429
8430 /* Called at device open time to get the chip ready for
8431  * packet processing.  Invoked with tp->lock held.
8432  */
8433 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8434 {
8435         tg3_switch_clocks(tp);
8436
8437         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8438
8439         return tg3_reset_hw(tp, reset_phy);
8440 }
8441
8442 #define TG3_STAT_ADD32(PSTAT, REG) \
8443 do {    u32 __val = tr32(REG); \
8444         (PSTAT)->low += __val; \
8445         if ((PSTAT)->low < __val) \
8446                 (PSTAT)->high += 1; \
8447 } while (0)
8448
8449 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8450 {
8451         struct tg3_hw_stats *sp = tp->hw_stats;
8452
8453         if (!netif_carrier_ok(tp->dev))
8454                 return;
8455
8456         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8457         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8458         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8459         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8460         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8461         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8462         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8463         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8464         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8465         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8466         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8467         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8468         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8469
8470         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8471         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8472         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8473         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8474         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8475         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8476         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8477         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8478         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8479         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8480         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8481         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8482         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8483         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8484
8485         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8486         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8487         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8488 }
8489
8490 static void tg3_timer(unsigned long __opaque)
8491 {
8492         struct tg3 *tp = (struct tg3 *) __opaque;
8493
8494         if (tp->irq_sync)
8495                 goto restart_timer;
8496
8497         spin_lock(&tp->lock);
8498
8499         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8500                 /* All of this garbage is because when using non-tagged
8501                  * IRQ status the mailbox/status_block protocol the chip
8502                  * uses with the cpu is race prone.
8503                  */
8504                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8505                         tw32(GRC_LOCAL_CTRL,
8506                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8507                 } else {
8508                         tw32(HOSTCC_MODE, tp->coalesce_mode |
8509                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8510                 }
8511
8512                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8513                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8514                         spin_unlock(&tp->lock);
8515                         schedule_work(&tp->reset_task);
8516                         return;
8517                 }
8518         }
8519
8520         /* This part only runs once per second. */
8521         if (!--tp->timer_counter) {
8522                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8523                         tg3_periodic_fetch_stats(tp);
8524
8525                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8526                         u32 mac_stat;
8527                         int phy_event;
8528
8529                         mac_stat = tr32(MAC_STATUS);
8530
8531                         phy_event = 0;
8532                         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
8533                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8534                                         phy_event = 1;
8535                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8536                                 phy_event = 1;
8537
8538                         if (phy_event)
8539                                 tg3_setup_phy(tp, 0);
8540                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8541                         u32 mac_stat = tr32(MAC_STATUS);
8542                         int need_setup = 0;
8543
8544                         if (netif_carrier_ok(tp->dev) &&
8545                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8546                                 need_setup = 1;
8547                         }
8548                         if (!netif_carrier_ok(tp->dev) &&
8549                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
8550                                          MAC_STATUS_SIGNAL_DET))) {
8551                                 need_setup = 1;
8552                         }
8553                         if (need_setup) {
8554                                 if (!tp->serdes_counter) {
8555                                         tw32_f(MAC_MODE,
8556                                              (tp->mac_mode &
8557                                               ~MAC_MODE_PORT_MODE_MASK));
8558                                         udelay(40);
8559                                         tw32_f(MAC_MODE, tp->mac_mode);
8560                                         udelay(40);
8561                                 }
8562                                 tg3_setup_phy(tp, 0);
8563                         }
8564                 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8565                            (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8566                         tg3_serdes_parallel_detect(tp);
8567                 }
8568
8569                 tp->timer_counter = tp->timer_multiplier;
8570         }
8571
8572         /* Heartbeat is only sent once every 2 seconds.
8573          *
8574          * The heartbeat is to tell the ASF firmware that the host
8575          * driver is still alive.  In the event that the OS crashes,
8576          * ASF needs to reset the hardware to free up the FIFO space
8577          * that may be filled with rx packets destined for the host.
8578          * If the FIFO is full, ASF will no longer function properly.
8579          *
8580          * Unintended resets have been reported on real time kernels
8581          * where the timer doesn't run on time.  Netpoll will also have
8582          * same problem.
8583          *
8584          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8585          * to check the ring condition when the heartbeat is expiring
8586          * before doing the reset.  This will prevent most unintended
8587          * resets.
8588          */
8589         if (!--tp->asf_counter) {
8590                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8591                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8592                         tg3_wait_for_event_ack(tp);
8593
8594                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8595                                       FWCMD_NICDRV_ALIVE3);
8596                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8597                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
8598                                       TG3_FW_UPDATE_TIMEOUT_SEC);
8599
8600                         tg3_generate_fw_event(tp);
8601                 }
8602                 tp->asf_counter = tp->asf_multiplier;
8603         }
8604
8605         spin_unlock(&tp->lock);
8606
8607 restart_timer:
8608         tp->timer.expires = jiffies + tp->timer_offset;
8609         add_timer(&tp->timer);
8610 }
8611
8612 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8613 {
8614         irq_handler_t fn;
8615         unsigned long flags;
8616         char *name;
8617         struct tg3_napi *tnapi = &tp->napi[irq_num];
8618
8619         if (tp->irq_cnt == 1)
8620                 name = tp->dev->name;
8621         else {
8622                 name = &tnapi->irq_lbl[0];
8623                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8624                 name[IFNAMSIZ-1] = 0;
8625         }
8626
8627         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8628                 fn = tg3_msi;
8629                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8630                         fn = tg3_msi_1shot;
8631                 flags = IRQF_SAMPLE_RANDOM;
8632         } else {
8633                 fn = tg3_interrupt;
8634                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8635                         fn = tg3_interrupt_tagged;
8636                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8637         }
8638
8639         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8640 }
8641
8642 static int tg3_test_interrupt(struct tg3 *tp)
8643 {
8644         struct tg3_napi *tnapi = &tp->napi[0];
8645         struct net_device *dev = tp->dev;
8646         int err, i, intr_ok = 0;
8647         u32 val;
8648
8649         if (!netif_running(dev))
8650                 return -ENODEV;
8651
8652         tg3_disable_ints(tp);
8653
8654         free_irq(tnapi->irq_vec, tnapi);
8655
8656         /*
8657          * Turn off MSI one shot mode.  Otherwise this test has no
8658          * observable way to know whether the interrupt was delivered.
8659          */
8660         if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8661             (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8662                 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8663                 tw32(MSGINT_MODE, val);
8664         }
8665
8666         err = request_irq(tnapi->irq_vec, tg3_test_isr,
8667                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8668         if (err)
8669                 return err;
8670
8671         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8672         tg3_enable_ints(tp);
8673
8674         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8675                tnapi->coal_now);
8676
8677         for (i = 0; i < 5; i++) {
8678                 u32 int_mbox, misc_host_ctrl;
8679
8680                 int_mbox = tr32_mailbox(tnapi->int_mbox);
8681                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8682
8683                 if ((int_mbox != 0) ||
8684                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8685                         intr_ok = 1;
8686                         break;
8687                 }
8688
8689                 msleep(10);
8690         }
8691
8692         tg3_disable_ints(tp);
8693
8694         free_irq(tnapi->irq_vec, tnapi);
8695
8696         err = tg3_request_irq(tp, 0);
8697
8698         if (err)
8699                 return err;
8700
8701         if (intr_ok) {
8702                 /* Reenable MSI one shot mode. */
8703                 if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8704                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8705                         val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8706                         tw32(MSGINT_MODE, val);
8707                 }
8708                 return 0;
8709         }
8710
8711         return -EIO;
8712 }
8713
8714 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8715  * successfully restored
8716  */
8717 static int tg3_test_msi(struct tg3 *tp)
8718 {
8719         int err;
8720         u16 pci_cmd;
8721
8722         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8723                 return 0;
8724
8725         /* Turn off SERR reporting in case MSI terminates with Master
8726          * Abort.
8727          */
8728         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8729         pci_write_config_word(tp->pdev, PCI_COMMAND,
8730                               pci_cmd & ~PCI_COMMAND_SERR);
8731
8732         err = tg3_test_interrupt(tp);
8733
8734         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8735
8736         if (!err)
8737                 return 0;
8738
8739         /* other failures */
8740         if (err != -EIO)
8741                 return err;
8742
8743         /* MSI test failed, go back to INTx mode */
8744         netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
8745                     "to INTx mode. Please report this failure to the PCI "
8746                     "maintainer and include system chipset information\n");
8747
8748         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8749
8750         pci_disable_msi(tp->pdev);
8751
8752         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8753         tp->napi[0].irq_vec = tp->pdev->irq;
8754
8755         err = tg3_request_irq(tp, 0);
8756         if (err)
8757                 return err;
8758
8759         /* Need to reset the chip because the MSI cycle may have terminated
8760          * with Master Abort.
8761          */
8762         tg3_full_lock(tp, 1);
8763
8764         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8765         err = tg3_init_hw(tp, 1);
8766
8767         tg3_full_unlock(tp);
8768
8769         if (err)
8770                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8771
8772         return err;
8773 }
8774
8775 static int tg3_request_firmware(struct tg3 *tp)
8776 {
8777         const __be32 *fw_data;
8778
8779         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8780                 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
8781                            tp->fw_needed);
8782                 return -ENOENT;
8783         }
8784
8785         fw_data = (void *)tp->fw->data;
8786
8787         /* Firmware blob starts with version numbers, followed by
8788          * start address and _full_ length including BSS sections
8789          * (which must be longer than the actual data, of course
8790          */
8791
8792         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
8793         if (tp->fw_len < (tp->fw->size - 12)) {
8794                 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
8795                            tp->fw_len, tp->fw_needed);
8796                 release_firmware(tp->fw);
8797                 tp->fw = NULL;
8798                 return -EINVAL;
8799         }
8800
8801         /* We no longer need firmware; we have it. */
8802         tp->fw_needed = NULL;
8803         return 0;
8804 }
8805
8806 static bool tg3_enable_msix(struct tg3 *tp)
8807 {
8808         int i, rc, cpus = num_online_cpus();
8809         struct msix_entry msix_ent[tp->irq_max];
8810
8811         if (cpus == 1)
8812                 /* Just fallback to the simpler MSI mode. */
8813                 return false;
8814
8815         /*
8816          * We want as many rx rings enabled as there are cpus.
8817          * The first MSIX vector only deals with link interrupts, etc,
8818          * so we add one to the number of vectors we are requesting.
8819          */
8820         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8821
8822         for (i = 0; i < tp->irq_max; i++) {
8823                 msix_ent[i].entry  = i;
8824                 msix_ent[i].vector = 0;
8825         }
8826
8827         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8828         if (rc < 0) {
8829                 return false;
8830         } else if (rc != 0) {
8831                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8832                         return false;
8833                 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
8834                               tp->irq_cnt, rc);
8835                 tp->irq_cnt = rc;
8836         }
8837
8838         for (i = 0; i < tp->irq_max; i++)
8839                 tp->napi[i].irq_vec = msix_ent[i].vector;
8840
8841         netif_set_real_num_tx_queues(tp->dev, 1);
8842         rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1;
8843         if (netif_set_real_num_rx_queues(tp->dev, rc)) {
8844                 pci_disable_msix(tp->pdev);
8845                 return false;
8846         }
8847         if (tp->irq_cnt > 1)
8848                 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8849
8850         return true;
8851 }
8852
8853 static void tg3_ints_init(struct tg3 *tp)
8854 {
8855         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8856             !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8857                 /* All MSI supporting chips should support tagged
8858                  * status.  Assert that this is the case.
8859                  */
8860                 netdev_warn(tp->dev,
8861                             "MSI without TAGGED_STATUS? Not using MSI\n");
8862                 goto defcfg;
8863         }
8864
8865         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8866                 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8867         else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8868                  pci_enable_msi(tp->pdev) == 0)
8869                 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8870
8871         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8872                 u32 msi_mode = tr32(MSGINT_MODE);
8873                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8874                         msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8875                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8876         }
8877 defcfg:
8878         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8879                 tp->irq_cnt = 1;
8880                 tp->napi[0].irq_vec = tp->pdev->irq;
8881                 netif_set_real_num_tx_queues(tp->dev, 1);
8882         }
8883 }
8884
8885 static void tg3_ints_fini(struct tg3 *tp)
8886 {
8887         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8888                 pci_disable_msix(tp->pdev);
8889         else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8890                 pci_disable_msi(tp->pdev);
8891         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8892         tp->tg3_flags3 &= ~(TG3_FLG3_ENABLE_RSS | TG3_FLG3_ENABLE_TSS);
8893 }
8894
8895 static int tg3_open(struct net_device *dev)
8896 {
8897         struct tg3 *tp = netdev_priv(dev);
8898         int i, err;
8899
8900         if (tp->fw_needed) {
8901                 err = tg3_request_firmware(tp);
8902                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8903                         if (err)
8904                                 return err;
8905                 } else if (err) {
8906                         netdev_warn(tp->dev, "TSO capability disabled\n");
8907                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8908                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8909                         netdev_notice(tp->dev, "TSO capability restored\n");
8910                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8911                 }
8912         }
8913
8914         netif_carrier_off(tp->dev);
8915
8916         err = tg3_set_power_state(tp, PCI_D0);
8917         if (err)
8918                 return err;
8919
8920         tg3_full_lock(tp, 0);
8921
8922         tg3_disable_ints(tp);
8923         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8924
8925         tg3_full_unlock(tp);
8926
8927         /*
8928          * Setup interrupts first so we know how
8929          * many NAPI resources to allocate
8930          */
8931         tg3_ints_init(tp);
8932
8933         /* The placement of this call is tied
8934          * to the setup and use of Host TX descriptors.
8935          */
8936         err = tg3_alloc_consistent(tp);
8937         if (err)
8938                 goto err_out1;
8939
8940         tg3_napi_init(tp);
8941
8942         tg3_napi_enable(tp);
8943
8944         for (i = 0; i < tp->irq_cnt; i++) {
8945                 struct tg3_napi *tnapi = &tp->napi[i];
8946                 err = tg3_request_irq(tp, i);
8947                 if (err) {
8948                         for (i--; i >= 0; i--)
8949                                 free_irq(tnapi->irq_vec, tnapi);
8950                         break;
8951                 }
8952         }
8953
8954         if (err)
8955                 goto err_out2;
8956
8957         tg3_full_lock(tp, 0);
8958
8959         err = tg3_init_hw(tp, 1);
8960         if (err) {
8961                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8962                 tg3_free_rings(tp);
8963         } else {
8964                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8965                         tp->timer_offset = HZ;
8966                 else
8967                         tp->timer_offset = HZ / 10;
8968
8969                 BUG_ON(tp->timer_offset > HZ);
8970                 tp->timer_counter = tp->timer_multiplier =
8971                         (HZ / tp->timer_offset);
8972                 tp->asf_counter = tp->asf_multiplier =
8973                         ((HZ / tp->timer_offset) * 2);
8974
8975                 init_timer(&tp->timer);
8976                 tp->timer.expires = jiffies + tp->timer_offset;
8977                 tp->timer.data = (unsigned long) tp;
8978                 tp->timer.function = tg3_timer;
8979         }
8980
8981         tg3_full_unlock(tp);
8982
8983         if (err)
8984                 goto err_out3;
8985
8986         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8987                 err = tg3_test_msi(tp);
8988
8989                 if (err) {
8990                         tg3_full_lock(tp, 0);
8991                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8992                         tg3_free_rings(tp);
8993                         tg3_full_unlock(tp);
8994
8995                         goto err_out2;
8996                 }
8997
8998                 if (!(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8999                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
9000                         u32 val = tr32(PCIE_TRANSACTION_CFG);
9001
9002                         tw32(PCIE_TRANSACTION_CFG,
9003                              val | PCIE_TRANS_CFG_1SHOT_MSI);
9004                 }
9005         }
9006
9007         tg3_phy_start(tp);
9008
9009         tg3_full_lock(tp, 0);
9010
9011         add_timer(&tp->timer);
9012         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9013         tg3_enable_ints(tp);
9014
9015         tg3_full_unlock(tp);
9016
9017         netif_tx_start_all_queues(dev);
9018
9019         return 0;
9020
9021 err_out3:
9022         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9023                 struct tg3_napi *tnapi = &tp->napi[i];
9024                 free_irq(tnapi->irq_vec, tnapi);
9025         }
9026
9027 err_out2:
9028         tg3_napi_disable(tp);
9029         tg3_napi_fini(tp);
9030         tg3_free_consistent(tp);
9031
9032 err_out1:
9033         tg3_ints_fini(tp);
9034         return err;
9035 }
9036
9037 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
9038                                                  struct rtnl_link_stats64 *);
9039 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9040
9041 static int tg3_close(struct net_device *dev)
9042 {
9043         int i;
9044         struct tg3 *tp = netdev_priv(dev);
9045
9046         tg3_napi_disable(tp);
9047         cancel_work_sync(&tp->reset_task);
9048
9049         netif_tx_stop_all_queues(dev);
9050
9051         del_timer_sync(&tp->timer);
9052
9053         tg3_phy_stop(tp);
9054
9055         tg3_full_lock(tp, 1);
9056
9057         tg3_disable_ints(tp);
9058
9059         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9060         tg3_free_rings(tp);
9061         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9062
9063         tg3_full_unlock(tp);
9064
9065         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9066                 struct tg3_napi *tnapi = &tp->napi[i];
9067                 free_irq(tnapi->irq_vec, tnapi);
9068         }
9069
9070         tg3_ints_fini(tp);
9071
9072         tg3_get_stats64(tp->dev, &tp->net_stats_prev);
9073
9074         memcpy(&tp->estats_prev, tg3_get_estats(tp),
9075                sizeof(tp->estats_prev));
9076
9077         tg3_napi_fini(tp);
9078
9079         tg3_free_consistent(tp);
9080
9081         tg3_set_power_state(tp, PCI_D3hot);
9082
9083         netif_carrier_off(tp->dev);
9084
9085         return 0;
9086 }
9087
9088 static inline u64 get_stat64(tg3_stat64_t *val)
9089 {
9090        return ((u64)val->high << 32) | ((u64)val->low);
9091 }
9092
9093 static u64 calc_crc_errors(struct tg3 *tp)
9094 {
9095         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9096
9097         if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9098             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9099              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9100                 u32 val;
9101
9102                 spin_lock_bh(&tp->lock);
9103                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9104                         tg3_writephy(tp, MII_TG3_TEST1,
9105                                      val | MII_TG3_TEST1_CRC_EN);
9106                         tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
9107                 } else
9108                         val = 0;
9109                 spin_unlock_bh(&tp->lock);
9110
9111                 tp->phy_crc_errors += val;
9112
9113                 return tp->phy_crc_errors;
9114         }
9115
9116         return get_stat64(&hw_stats->rx_fcs_errors);
9117 }
9118
9119 #define ESTAT_ADD(member) \
9120         estats->member =        old_estats->member + \
9121                                 get_stat64(&hw_stats->member)
9122
9123 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9124 {
9125         struct tg3_ethtool_stats *estats = &tp->estats;
9126         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9127         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9128
9129         if (!hw_stats)
9130                 return old_estats;
9131
9132         ESTAT_ADD(rx_octets);
9133         ESTAT_ADD(rx_fragments);
9134         ESTAT_ADD(rx_ucast_packets);
9135         ESTAT_ADD(rx_mcast_packets);
9136         ESTAT_ADD(rx_bcast_packets);
9137         ESTAT_ADD(rx_fcs_errors);
9138         ESTAT_ADD(rx_align_errors);
9139         ESTAT_ADD(rx_xon_pause_rcvd);
9140         ESTAT_ADD(rx_xoff_pause_rcvd);
9141         ESTAT_ADD(rx_mac_ctrl_rcvd);
9142         ESTAT_ADD(rx_xoff_entered);
9143         ESTAT_ADD(rx_frame_too_long_errors);
9144         ESTAT_ADD(rx_jabbers);
9145         ESTAT_ADD(rx_undersize_packets);
9146         ESTAT_ADD(rx_in_length_errors);
9147         ESTAT_ADD(rx_out_length_errors);
9148         ESTAT_ADD(rx_64_or_less_octet_packets);
9149         ESTAT_ADD(rx_65_to_127_octet_packets);
9150         ESTAT_ADD(rx_128_to_255_octet_packets);
9151         ESTAT_ADD(rx_256_to_511_octet_packets);
9152         ESTAT_ADD(rx_512_to_1023_octet_packets);
9153         ESTAT_ADD(rx_1024_to_1522_octet_packets);
9154         ESTAT_ADD(rx_1523_to_2047_octet_packets);
9155         ESTAT_ADD(rx_2048_to_4095_octet_packets);
9156         ESTAT_ADD(rx_4096_to_8191_octet_packets);
9157         ESTAT_ADD(rx_8192_to_9022_octet_packets);
9158
9159         ESTAT_ADD(tx_octets);
9160         ESTAT_ADD(tx_collisions);
9161         ESTAT_ADD(tx_xon_sent);
9162         ESTAT_ADD(tx_xoff_sent);
9163         ESTAT_ADD(tx_flow_control);
9164         ESTAT_ADD(tx_mac_errors);
9165         ESTAT_ADD(tx_single_collisions);
9166         ESTAT_ADD(tx_mult_collisions);
9167         ESTAT_ADD(tx_deferred);
9168         ESTAT_ADD(tx_excessive_collisions);
9169         ESTAT_ADD(tx_late_collisions);
9170         ESTAT_ADD(tx_collide_2times);
9171         ESTAT_ADD(tx_collide_3times);
9172         ESTAT_ADD(tx_collide_4times);
9173         ESTAT_ADD(tx_collide_5times);
9174         ESTAT_ADD(tx_collide_6times);
9175         ESTAT_ADD(tx_collide_7times);
9176         ESTAT_ADD(tx_collide_8times);
9177         ESTAT_ADD(tx_collide_9times);
9178         ESTAT_ADD(tx_collide_10times);
9179         ESTAT_ADD(tx_collide_11times);
9180         ESTAT_ADD(tx_collide_12times);
9181         ESTAT_ADD(tx_collide_13times);
9182         ESTAT_ADD(tx_collide_14times);
9183         ESTAT_ADD(tx_collide_15times);
9184         ESTAT_ADD(tx_ucast_packets);
9185         ESTAT_ADD(tx_mcast_packets);
9186         ESTAT_ADD(tx_bcast_packets);
9187         ESTAT_ADD(tx_carrier_sense_errors);
9188         ESTAT_ADD(tx_discards);
9189         ESTAT_ADD(tx_errors);
9190
9191         ESTAT_ADD(dma_writeq_full);
9192         ESTAT_ADD(dma_write_prioq_full);
9193         ESTAT_ADD(rxbds_empty);
9194         ESTAT_ADD(rx_discards);
9195         ESTAT_ADD(rx_errors);
9196         ESTAT_ADD(rx_threshold_hit);
9197
9198         ESTAT_ADD(dma_readq_full);
9199         ESTAT_ADD(dma_read_prioq_full);
9200         ESTAT_ADD(tx_comp_queue_full);
9201
9202         ESTAT_ADD(ring_set_send_prod_index);
9203         ESTAT_ADD(ring_status_update);
9204         ESTAT_ADD(nic_irqs);
9205         ESTAT_ADD(nic_avoided_irqs);
9206         ESTAT_ADD(nic_tx_threshold_hit);
9207
9208         return estats;
9209 }
9210
9211 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
9212                                                  struct rtnl_link_stats64 *stats)
9213 {
9214         struct tg3 *tp = netdev_priv(dev);
9215         struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
9216         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9217
9218         if (!hw_stats)
9219                 return old_stats;
9220
9221         stats->rx_packets = old_stats->rx_packets +
9222                 get_stat64(&hw_stats->rx_ucast_packets) +
9223                 get_stat64(&hw_stats->rx_mcast_packets) +
9224                 get_stat64(&hw_stats->rx_bcast_packets);
9225
9226         stats->tx_packets = old_stats->tx_packets +
9227                 get_stat64(&hw_stats->tx_ucast_packets) +
9228                 get_stat64(&hw_stats->tx_mcast_packets) +
9229                 get_stat64(&hw_stats->tx_bcast_packets);
9230
9231         stats->rx_bytes = old_stats->rx_bytes +
9232                 get_stat64(&hw_stats->rx_octets);
9233         stats->tx_bytes = old_stats->tx_bytes +
9234                 get_stat64(&hw_stats->tx_octets);
9235
9236         stats->rx_errors = old_stats->rx_errors +
9237                 get_stat64(&hw_stats->rx_errors);
9238         stats->tx_errors = old_stats->tx_errors +
9239                 get_stat64(&hw_stats->tx_errors) +
9240                 get_stat64(&hw_stats->tx_mac_errors) +
9241                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9242                 get_stat64(&hw_stats->tx_discards);
9243
9244         stats->multicast = old_stats->multicast +
9245                 get_stat64(&hw_stats->rx_mcast_packets);
9246         stats->collisions = old_stats->collisions +
9247                 get_stat64(&hw_stats->tx_collisions);
9248
9249         stats->rx_length_errors = old_stats->rx_length_errors +
9250                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9251                 get_stat64(&hw_stats->rx_undersize_packets);
9252
9253         stats->rx_over_errors = old_stats->rx_over_errors +
9254                 get_stat64(&hw_stats->rxbds_empty);
9255         stats->rx_frame_errors = old_stats->rx_frame_errors +
9256                 get_stat64(&hw_stats->rx_align_errors);
9257         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9258                 get_stat64(&hw_stats->tx_discards);
9259         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9260                 get_stat64(&hw_stats->tx_carrier_sense_errors);
9261
9262         stats->rx_crc_errors = old_stats->rx_crc_errors +
9263                 calc_crc_errors(tp);
9264
9265         stats->rx_missed_errors = old_stats->rx_missed_errors +
9266                 get_stat64(&hw_stats->rx_discards);
9267
9268         return stats;
9269 }
9270
9271 static inline u32 calc_crc(unsigned char *buf, int len)
9272 {
9273         u32 reg;
9274         u32 tmp;
9275         int j, k;
9276
9277         reg = 0xffffffff;
9278
9279         for (j = 0; j < len; j++) {
9280                 reg ^= buf[j];
9281
9282                 for (k = 0; k < 8; k++) {
9283                         tmp = reg & 0x01;
9284
9285                         reg >>= 1;
9286
9287                         if (tmp)
9288                                 reg ^= 0xedb88320;
9289                 }
9290         }
9291
9292         return ~reg;
9293 }
9294
9295 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9296 {
9297         /* accept or reject all multicast frames */
9298         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9299         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9300         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9301         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9302 }
9303
9304 static void __tg3_set_rx_mode(struct net_device *dev)
9305 {
9306         struct tg3 *tp = netdev_priv(dev);
9307         u32 rx_mode;
9308
9309         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9310                                   RX_MODE_KEEP_VLAN_TAG);
9311
9312         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9313          * flag clear.
9314          */
9315 #if TG3_VLAN_TAG_USED
9316         if (!tp->vlgrp &&
9317             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9318                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9319 #else
9320         /* By definition, VLAN is disabled always in this
9321          * case.
9322          */
9323         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9324                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9325 #endif
9326
9327         if (dev->flags & IFF_PROMISC) {
9328                 /* Promiscuous mode. */
9329                 rx_mode |= RX_MODE_PROMISC;
9330         } else if (dev->flags & IFF_ALLMULTI) {
9331                 /* Accept all multicast. */
9332                 tg3_set_multi(tp, 1);
9333         } else if (netdev_mc_empty(dev)) {
9334                 /* Reject all multicast. */
9335                 tg3_set_multi(tp, 0);
9336         } else {
9337                 /* Accept one or more multicast(s). */
9338                 struct netdev_hw_addr *ha;
9339                 u32 mc_filter[4] = { 0, };
9340                 u32 regidx;
9341                 u32 bit;
9342                 u32 crc;
9343
9344                 netdev_for_each_mc_addr(ha, dev) {
9345                         crc = calc_crc(ha->addr, ETH_ALEN);
9346                         bit = ~crc & 0x7f;
9347                         regidx = (bit & 0x60) >> 5;
9348                         bit &= 0x1f;
9349                         mc_filter[regidx] |= (1 << bit);
9350                 }
9351
9352                 tw32(MAC_HASH_REG_0, mc_filter[0]);
9353                 tw32(MAC_HASH_REG_1, mc_filter[1]);
9354                 tw32(MAC_HASH_REG_2, mc_filter[2]);
9355                 tw32(MAC_HASH_REG_3, mc_filter[3]);
9356         }
9357
9358         if (rx_mode != tp->rx_mode) {
9359                 tp->rx_mode = rx_mode;
9360                 tw32_f(MAC_RX_MODE, rx_mode);
9361                 udelay(10);
9362         }
9363 }
9364
9365 static void tg3_set_rx_mode(struct net_device *dev)
9366 {
9367         struct tg3 *tp = netdev_priv(dev);
9368
9369         if (!netif_running(dev))
9370                 return;
9371
9372         tg3_full_lock(tp, 0);
9373         __tg3_set_rx_mode(dev);
9374         tg3_full_unlock(tp);
9375 }
9376
9377 #define TG3_REGDUMP_LEN         (32 * 1024)
9378
9379 static int tg3_get_regs_len(struct net_device *dev)
9380 {
9381         return TG3_REGDUMP_LEN;
9382 }
9383
9384 static void tg3_get_regs(struct net_device *dev,
9385                 struct ethtool_regs *regs, void *_p)
9386 {
9387         u32 *p = _p;
9388         struct tg3 *tp = netdev_priv(dev);
9389         u8 *orig_p = _p;
9390         int i;
9391
9392         regs->version = 0;
9393
9394         memset(p, 0, TG3_REGDUMP_LEN);
9395
9396         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9397                 return;
9398
9399         tg3_full_lock(tp, 0);
9400
9401 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
9402 #define GET_REG32_LOOP(base, len)               \
9403 do {    p = (u32 *)(orig_p + (base));           \
9404         for (i = 0; i < len; i += 4)            \
9405                 __GET_REG32((base) + i);        \
9406 } while (0)
9407 #define GET_REG32_1(reg)                        \
9408 do {    p = (u32 *)(orig_p + (reg));            \
9409         __GET_REG32((reg));                     \
9410 } while (0)
9411
9412         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9413         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9414         GET_REG32_LOOP(MAC_MODE, 0x4f0);
9415         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9416         GET_REG32_1(SNDDATAC_MODE);
9417         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9418         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9419         GET_REG32_1(SNDBDC_MODE);
9420         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9421         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9422         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9423         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9424         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9425         GET_REG32_1(RCVDCC_MODE);
9426         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9427         GET_REG32_LOOP(RCVCC_MODE, 0x14);
9428         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9429         GET_REG32_1(MBFREE_MODE);
9430         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9431         GET_REG32_LOOP(MEMARB_MODE, 0x10);
9432         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9433         GET_REG32_LOOP(RDMAC_MODE, 0x08);
9434         GET_REG32_LOOP(WDMAC_MODE, 0x08);
9435         GET_REG32_1(RX_CPU_MODE);
9436         GET_REG32_1(RX_CPU_STATE);
9437         GET_REG32_1(RX_CPU_PGMCTR);
9438         GET_REG32_1(RX_CPU_HWBKPT);
9439         GET_REG32_1(TX_CPU_MODE);
9440         GET_REG32_1(TX_CPU_STATE);
9441         GET_REG32_1(TX_CPU_PGMCTR);
9442         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9443         GET_REG32_LOOP(FTQ_RESET, 0x120);
9444         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9445         GET_REG32_1(DMAC_MODE);
9446         GET_REG32_LOOP(GRC_MODE, 0x4c);
9447         if (tp->tg3_flags & TG3_FLAG_NVRAM)
9448                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9449
9450 #undef __GET_REG32
9451 #undef GET_REG32_LOOP
9452 #undef GET_REG32_1
9453
9454         tg3_full_unlock(tp);
9455 }
9456
9457 static int tg3_get_eeprom_len(struct net_device *dev)
9458 {
9459         struct tg3 *tp = netdev_priv(dev);
9460
9461         return tp->nvram_size;
9462 }
9463
9464 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9465 {
9466         struct tg3 *tp = netdev_priv(dev);
9467         int ret;
9468         u8  *pd;
9469         u32 i, offset, len, b_offset, b_count;
9470         __be32 val;
9471
9472         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9473                 return -EINVAL;
9474
9475         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9476                 return -EAGAIN;
9477
9478         offset = eeprom->offset;
9479         len = eeprom->len;
9480         eeprom->len = 0;
9481
9482         eeprom->magic = TG3_EEPROM_MAGIC;
9483
9484         if (offset & 3) {
9485                 /* adjustments to start on required 4 byte boundary */
9486                 b_offset = offset & 3;
9487                 b_count = 4 - b_offset;
9488                 if (b_count > len) {
9489                         /* i.e. offset=1 len=2 */
9490                         b_count = len;
9491                 }
9492                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9493                 if (ret)
9494                         return ret;
9495                 memcpy(data, ((char *)&val) + b_offset, b_count);
9496                 len -= b_count;
9497                 offset += b_count;
9498                 eeprom->len += b_count;
9499         }
9500
9501         /* read bytes upto the last 4 byte boundary */
9502         pd = &data[eeprom->len];
9503         for (i = 0; i < (len - (len & 3)); i += 4) {
9504                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9505                 if (ret) {
9506                         eeprom->len += i;
9507                         return ret;
9508                 }
9509                 memcpy(pd + i, &val, 4);
9510         }
9511         eeprom->len += i;
9512
9513         if (len & 3) {
9514                 /* read last bytes not ending on 4 byte boundary */
9515                 pd = &data[eeprom->len];
9516                 b_count = len & 3;
9517                 b_offset = offset + len - b_count;
9518                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9519                 if (ret)
9520                         return ret;
9521                 memcpy(pd, &val, b_count);
9522                 eeprom->len += b_count;
9523         }
9524         return 0;
9525 }
9526
9527 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9528
9529 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9530 {
9531         struct tg3 *tp = netdev_priv(dev);
9532         int ret;
9533         u32 offset, len, b_offset, odd_len;
9534         u8 *buf;
9535         __be32 start, end;
9536
9537         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9538                 return -EAGAIN;
9539
9540         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9541             eeprom->magic != TG3_EEPROM_MAGIC)
9542                 return -EINVAL;
9543
9544         offset = eeprom->offset;
9545         len = eeprom->len;
9546
9547         if ((b_offset = (offset & 3))) {
9548                 /* adjustments to start on required 4 byte boundary */
9549                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9550                 if (ret)
9551                         return ret;
9552                 len += b_offset;
9553                 offset &= ~3;
9554                 if (len < 4)
9555                         len = 4;
9556         }
9557
9558         odd_len = 0;
9559         if (len & 3) {
9560                 /* adjustments to end on required 4 byte boundary */
9561                 odd_len = 1;
9562                 len = (len + 3) & ~3;
9563                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9564                 if (ret)
9565                         return ret;
9566         }
9567
9568         buf = data;
9569         if (b_offset || odd_len) {
9570                 buf = kmalloc(len, GFP_KERNEL);
9571                 if (!buf)
9572                         return -ENOMEM;
9573                 if (b_offset)
9574                         memcpy(buf, &start, 4);
9575                 if (odd_len)
9576                         memcpy(buf+len-4, &end, 4);
9577                 memcpy(buf + b_offset, data, eeprom->len);
9578         }
9579
9580         ret = tg3_nvram_write_block(tp, offset, len, buf);
9581
9582         if (buf != data)
9583                 kfree(buf);
9584
9585         return ret;
9586 }
9587
9588 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9589 {
9590         struct tg3 *tp = netdev_priv(dev);
9591
9592         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9593                 struct phy_device *phydev;
9594                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9595                         return -EAGAIN;
9596                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9597                 return phy_ethtool_gset(phydev, cmd);
9598         }
9599
9600         cmd->supported = (SUPPORTED_Autoneg);
9601
9602         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9603                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9604                                    SUPPORTED_1000baseT_Full);
9605
9606         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
9607                 cmd->supported |= (SUPPORTED_100baseT_Half |
9608                                   SUPPORTED_100baseT_Full |
9609                                   SUPPORTED_10baseT_Half |
9610                                   SUPPORTED_10baseT_Full |
9611                                   SUPPORTED_TP);
9612                 cmd->port = PORT_TP;
9613         } else {
9614                 cmd->supported |= SUPPORTED_FIBRE;
9615                 cmd->port = PORT_FIBRE;
9616         }
9617
9618         cmd->advertising = tp->link_config.advertising;
9619         if (netif_running(dev)) {
9620                 cmd->speed = tp->link_config.active_speed;
9621                 cmd->duplex = tp->link_config.active_duplex;
9622         }
9623         cmd->phy_address = tp->phy_addr;
9624         cmd->transceiver = XCVR_INTERNAL;
9625         cmd->autoneg = tp->link_config.autoneg;
9626         cmd->maxtxpkt = 0;
9627         cmd->maxrxpkt = 0;
9628         return 0;
9629 }
9630
9631 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9632 {
9633         struct tg3 *tp = netdev_priv(dev);
9634
9635         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9636                 struct phy_device *phydev;
9637                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9638                         return -EAGAIN;
9639                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9640                 return phy_ethtool_sset(phydev, cmd);
9641         }
9642
9643         if (cmd->autoneg != AUTONEG_ENABLE &&
9644             cmd->autoneg != AUTONEG_DISABLE)
9645                 return -EINVAL;
9646
9647         if (cmd->autoneg == AUTONEG_DISABLE &&
9648             cmd->duplex != DUPLEX_FULL &&
9649             cmd->duplex != DUPLEX_HALF)
9650                 return -EINVAL;
9651
9652         if (cmd->autoneg == AUTONEG_ENABLE) {
9653                 u32 mask = ADVERTISED_Autoneg |
9654                            ADVERTISED_Pause |
9655                            ADVERTISED_Asym_Pause;
9656
9657                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9658                         mask |= ADVERTISED_1000baseT_Half |
9659                                 ADVERTISED_1000baseT_Full;
9660
9661                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
9662                         mask |= ADVERTISED_100baseT_Half |
9663                                 ADVERTISED_100baseT_Full |
9664                                 ADVERTISED_10baseT_Half |
9665                                 ADVERTISED_10baseT_Full |
9666                                 ADVERTISED_TP;
9667                 else
9668                         mask |= ADVERTISED_FIBRE;
9669
9670                 if (cmd->advertising & ~mask)
9671                         return -EINVAL;
9672
9673                 mask &= (ADVERTISED_1000baseT_Half |
9674                          ADVERTISED_1000baseT_Full |
9675                          ADVERTISED_100baseT_Half |
9676                          ADVERTISED_100baseT_Full |
9677                          ADVERTISED_10baseT_Half |
9678                          ADVERTISED_10baseT_Full);
9679
9680                 cmd->advertising &= mask;
9681         } else {
9682                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
9683                         if (cmd->speed != SPEED_1000)
9684                                 return -EINVAL;
9685
9686                         if (cmd->duplex != DUPLEX_FULL)
9687                                 return -EINVAL;
9688                 } else {
9689                         if (cmd->speed != SPEED_100 &&
9690                             cmd->speed != SPEED_10)
9691                                 return -EINVAL;
9692                 }
9693         }
9694
9695         tg3_full_lock(tp, 0);
9696
9697         tp->link_config.autoneg = cmd->autoneg;
9698         if (cmd->autoneg == AUTONEG_ENABLE) {
9699                 tp->link_config.advertising = (cmd->advertising |
9700                                               ADVERTISED_Autoneg);
9701                 tp->link_config.speed = SPEED_INVALID;
9702                 tp->link_config.duplex = DUPLEX_INVALID;
9703         } else {
9704                 tp->link_config.advertising = 0;
9705                 tp->link_config.speed = cmd->speed;
9706                 tp->link_config.duplex = cmd->duplex;
9707         }
9708
9709         tp->link_config.orig_speed = tp->link_config.speed;
9710         tp->link_config.orig_duplex = tp->link_config.duplex;
9711         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9712
9713         if (netif_running(dev))
9714                 tg3_setup_phy(tp, 1);
9715
9716         tg3_full_unlock(tp);
9717
9718         return 0;
9719 }
9720
9721 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9722 {
9723         struct tg3 *tp = netdev_priv(dev);
9724
9725         strcpy(info->driver, DRV_MODULE_NAME);
9726         strcpy(info->version, DRV_MODULE_VERSION);
9727         strcpy(info->fw_version, tp->fw_ver);
9728         strcpy(info->bus_info, pci_name(tp->pdev));
9729 }
9730
9731 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9732 {
9733         struct tg3 *tp = netdev_priv(dev);
9734
9735         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9736             device_can_wakeup(&tp->pdev->dev))
9737                 wol->supported = WAKE_MAGIC;
9738         else
9739                 wol->supported = 0;
9740         wol->wolopts = 0;
9741         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9742             device_can_wakeup(&tp->pdev->dev))
9743                 wol->wolopts = WAKE_MAGIC;
9744         memset(&wol->sopass, 0, sizeof(wol->sopass));
9745 }
9746
9747 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9748 {
9749         struct tg3 *tp = netdev_priv(dev);
9750         struct device *dp = &tp->pdev->dev;
9751
9752         if (wol->wolopts & ~WAKE_MAGIC)
9753                 return -EINVAL;
9754         if ((wol->wolopts & WAKE_MAGIC) &&
9755             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9756                 return -EINVAL;
9757
9758         spin_lock_bh(&tp->lock);
9759         if (wol->wolopts & WAKE_MAGIC) {
9760                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9761                 device_set_wakeup_enable(dp, true);
9762         } else {
9763                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9764                 device_set_wakeup_enable(dp, false);
9765         }
9766         spin_unlock_bh(&tp->lock);
9767
9768         return 0;
9769 }
9770
9771 static u32 tg3_get_msglevel(struct net_device *dev)
9772 {
9773         struct tg3 *tp = netdev_priv(dev);
9774         return tp->msg_enable;
9775 }
9776
9777 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9778 {
9779         struct tg3 *tp = netdev_priv(dev);
9780         tp->msg_enable = value;
9781 }
9782
9783 static int tg3_set_tso(struct net_device *dev, u32 value)
9784 {
9785         struct tg3 *tp = netdev_priv(dev);
9786
9787         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9788                 if (value)
9789                         return -EINVAL;
9790                 return 0;
9791         }
9792         if ((dev->features & NETIF_F_IPV6_CSUM) &&
9793             ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9794              (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9795                 if (value) {
9796                         dev->features |= NETIF_F_TSO6;
9797                         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9798                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9799                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9800                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9801                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9802                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9803                                 dev->features |= NETIF_F_TSO_ECN;
9804                 } else
9805                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9806         }
9807         return ethtool_op_set_tso(dev, value);
9808 }
9809
9810 static int tg3_nway_reset(struct net_device *dev)
9811 {
9812         struct tg3 *tp = netdev_priv(dev);
9813         int r;
9814
9815         if (!netif_running(dev))
9816                 return -EAGAIN;
9817
9818         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
9819                 return -EINVAL;
9820
9821         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9822                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9823                         return -EAGAIN;
9824                 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9825         } else {
9826                 u32 bmcr;
9827
9828                 spin_lock_bh(&tp->lock);
9829                 r = -EINVAL;
9830                 tg3_readphy(tp, MII_BMCR, &bmcr);
9831                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9832                     ((bmcr & BMCR_ANENABLE) ||
9833                      (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
9834                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9835                                                    BMCR_ANENABLE);
9836                         r = 0;
9837                 }
9838                 spin_unlock_bh(&tp->lock);
9839         }
9840
9841         return r;
9842 }
9843
9844 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9845 {
9846         struct tg3 *tp = netdev_priv(dev);
9847
9848         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9849         ering->rx_mini_max_pending = 0;
9850         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9851                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9852         else
9853                 ering->rx_jumbo_max_pending = 0;
9854
9855         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9856
9857         ering->rx_pending = tp->rx_pending;
9858         ering->rx_mini_pending = 0;
9859         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9860                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9861         else
9862                 ering->rx_jumbo_pending = 0;
9863
9864         ering->tx_pending = tp->napi[0].tx_pending;
9865 }
9866
9867 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9868 {
9869         struct tg3 *tp = netdev_priv(dev);
9870         int i, irq_sync = 0, err = 0;
9871
9872         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9873             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9874             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9875             (ering->tx_pending <= MAX_SKB_FRAGS) ||
9876             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9877              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9878                 return -EINVAL;
9879
9880         if (netif_running(dev)) {
9881                 tg3_phy_stop(tp);
9882                 tg3_netif_stop(tp);
9883                 irq_sync = 1;
9884         }
9885
9886         tg3_full_lock(tp, irq_sync);
9887
9888         tp->rx_pending = ering->rx_pending;
9889
9890         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9891             tp->rx_pending > 63)
9892                 tp->rx_pending = 63;
9893         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9894
9895         for (i = 0; i < tp->irq_max; i++)
9896                 tp->napi[i].tx_pending = ering->tx_pending;
9897
9898         if (netif_running(dev)) {
9899                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9900                 err = tg3_restart_hw(tp, 1);
9901                 if (!err)
9902                         tg3_netif_start(tp);
9903         }
9904
9905         tg3_full_unlock(tp);
9906
9907         if (irq_sync && !err)
9908                 tg3_phy_start(tp);
9909
9910         return err;
9911 }
9912
9913 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9914 {
9915         struct tg3 *tp = netdev_priv(dev);
9916
9917         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9918
9919         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9920                 epause->rx_pause = 1;
9921         else
9922                 epause->rx_pause = 0;
9923
9924         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9925                 epause->tx_pause = 1;
9926         else
9927                 epause->tx_pause = 0;
9928 }
9929
9930 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9931 {
9932         struct tg3 *tp = netdev_priv(dev);
9933         int err = 0;
9934
9935         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9936                 u32 newadv;
9937                 struct phy_device *phydev;
9938
9939                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9940
9941                 if (!(phydev->supported & SUPPORTED_Pause) ||
9942                     (!(phydev->supported & SUPPORTED_Asym_Pause) &&
9943                      ((epause->rx_pause && !epause->tx_pause) ||
9944                       (!epause->rx_pause && epause->tx_pause))))
9945                         return -EINVAL;
9946
9947                 tp->link_config.flowctrl = 0;
9948                 if (epause->rx_pause) {
9949                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
9950
9951                         if (epause->tx_pause) {
9952                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9953                                 newadv = ADVERTISED_Pause;
9954                         } else
9955                                 newadv = ADVERTISED_Pause |
9956                                          ADVERTISED_Asym_Pause;
9957                 } else if (epause->tx_pause) {
9958                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
9959                         newadv = ADVERTISED_Asym_Pause;
9960                 } else
9961                         newadv = 0;
9962
9963                 if (epause->autoneg)
9964                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9965                 else
9966                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9967
9968                 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
9969                         u32 oldadv = phydev->advertising &
9970                                      (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
9971                         if (oldadv != newadv) {
9972                                 phydev->advertising &=
9973                                         ~(ADVERTISED_Pause |
9974                                           ADVERTISED_Asym_Pause);
9975                                 phydev->advertising |= newadv;
9976                                 if (phydev->autoneg) {
9977                                         /*
9978                                          * Always renegotiate the link to
9979                                          * inform our link partner of our
9980                                          * flow control settings, even if the
9981                                          * flow control is forced.  Let
9982                                          * tg3_adjust_link() do the final
9983                                          * flow control setup.
9984                                          */
9985                                         return phy_start_aneg(phydev);
9986                                 }
9987                         }
9988
9989                         if (!epause->autoneg)
9990                                 tg3_setup_flow_control(tp, 0, 0);
9991                 } else {
9992                         tp->link_config.orig_advertising &=
9993                                         ~(ADVERTISED_Pause |
9994                                           ADVERTISED_Asym_Pause);
9995                         tp->link_config.orig_advertising |= newadv;
9996                 }
9997         } else {
9998                 int irq_sync = 0;
9999
10000                 if (netif_running(dev)) {
10001                         tg3_netif_stop(tp);
10002                         irq_sync = 1;
10003                 }
10004
10005                 tg3_full_lock(tp, irq_sync);
10006
10007                 if (epause->autoneg)
10008                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10009                 else
10010                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10011                 if (epause->rx_pause)
10012                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
10013                 else
10014                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10015                 if (epause->tx_pause)
10016                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
10017                 else
10018                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10019
10020                 if (netif_running(dev)) {
10021                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10022                         err = tg3_restart_hw(tp, 1);
10023                         if (!err)
10024                                 tg3_netif_start(tp);
10025                 }
10026
10027                 tg3_full_unlock(tp);
10028         }
10029
10030         return err;
10031 }
10032
10033 static u32 tg3_get_rx_csum(struct net_device *dev)
10034 {
10035         struct tg3 *tp = netdev_priv(dev);
10036         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10037 }
10038
10039 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10040 {
10041         struct tg3 *tp = netdev_priv(dev);
10042
10043         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10044                 if (data != 0)
10045                         return -EINVAL;
10046                 return 0;
10047         }
10048
10049         spin_lock_bh(&tp->lock);
10050         if (data)
10051                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10052         else
10053                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10054         spin_unlock_bh(&tp->lock);
10055
10056         return 0;
10057 }
10058
10059 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10060 {
10061         struct tg3 *tp = netdev_priv(dev);
10062
10063         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10064                 if (data != 0)
10065                         return -EINVAL;
10066                 return 0;
10067         }
10068
10069         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10070                 ethtool_op_set_tx_ipv6_csum(dev, data);
10071         else
10072                 ethtool_op_set_tx_csum(dev, data);
10073
10074         return 0;
10075 }
10076
10077 static int tg3_get_sset_count(struct net_device *dev, int sset)
10078 {
10079         switch (sset) {
10080         case ETH_SS_TEST:
10081                 return TG3_NUM_TEST;
10082         case ETH_SS_STATS:
10083                 return TG3_NUM_STATS;
10084         default:
10085                 return -EOPNOTSUPP;
10086         }
10087 }
10088
10089 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
10090 {
10091         switch (stringset) {
10092         case ETH_SS_STATS:
10093                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10094                 break;
10095         case ETH_SS_TEST:
10096                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10097                 break;
10098         default:
10099                 WARN_ON(1);     /* we need a WARN() */
10100                 break;
10101         }
10102 }
10103
10104 static int tg3_phys_id(struct net_device *dev, u32 data)
10105 {
10106         struct tg3 *tp = netdev_priv(dev);
10107         int i;
10108
10109         if (!netif_running(tp->dev))
10110                 return -EAGAIN;
10111
10112         if (data == 0)
10113                 data = UINT_MAX / 2;
10114
10115         for (i = 0; i < (data * 2); i++) {
10116                 if ((i % 2) == 0)
10117                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10118                                            LED_CTRL_1000MBPS_ON |
10119                                            LED_CTRL_100MBPS_ON |
10120                                            LED_CTRL_10MBPS_ON |
10121                                            LED_CTRL_TRAFFIC_OVERRIDE |
10122                                            LED_CTRL_TRAFFIC_BLINK |
10123                                            LED_CTRL_TRAFFIC_LED);
10124
10125                 else
10126                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10127                                            LED_CTRL_TRAFFIC_OVERRIDE);
10128
10129                 if (msleep_interruptible(500))
10130                         break;
10131         }
10132         tw32(MAC_LED_CTRL, tp->led_ctrl);
10133         return 0;
10134 }
10135
10136 static void tg3_get_ethtool_stats(struct net_device *dev,
10137                                    struct ethtool_stats *estats, u64 *tmp_stats)
10138 {
10139         struct tg3 *tp = netdev_priv(dev);
10140         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10141 }
10142
10143 #define NVRAM_TEST_SIZE 0x100
10144 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
10145 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
10146 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
10147 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10148 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10149
10150 static int tg3_test_nvram(struct tg3 *tp)
10151 {
10152         u32 csum, magic;
10153         __be32 *buf;
10154         int i, j, k, err = 0, size;
10155
10156         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10157                 return 0;
10158
10159         if (tg3_nvram_read(tp, 0, &magic) != 0)
10160                 return -EIO;
10161
10162         if (magic == TG3_EEPROM_MAGIC)
10163                 size = NVRAM_TEST_SIZE;
10164         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10165                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10166                     TG3_EEPROM_SB_FORMAT_1) {
10167                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10168                         case TG3_EEPROM_SB_REVISION_0:
10169                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10170                                 break;
10171                         case TG3_EEPROM_SB_REVISION_2:
10172                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10173                                 break;
10174                         case TG3_EEPROM_SB_REVISION_3:
10175                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10176                                 break;
10177                         default:
10178                                 return 0;
10179                         }
10180                 } else
10181                         return 0;
10182         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10183                 size = NVRAM_SELFBOOT_HW_SIZE;
10184         else
10185                 return -EIO;
10186
10187         buf = kmalloc(size, GFP_KERNEL);
10188         if (buf == NULL)
10189                 return -ENOMEM;
10190
10191         err = -EIO;
10192         for (i = 0, j = 0; i < size; i += 4, j++) {
10193                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10194                 if (err)
10195                         break;
10196         }
10197         if (i < size)
10198                 goto out;
10199
10200         /* Selfboot format */
10201         magic = be32_to_cpu(buf[0]);
10202         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10203             TG3_EEPROM_MAGIC_FW) {
10204                 u8 *buf8 = (u8 *) buf, csum8 = 0;
10205
10206                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10207                     TG3_EEPROM_SB_REVISION_2) {
10208                         /* For rev 2, the csum doesn't include the MBA. */
10209                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10210                                 csum8 += buf8[i];
10211                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10212                                 csum8 += buf8[i];
10213                 } else {
10214                         for (i = 0; i < size; i++)
10215                                 csum8 += buf8[i];
10216                 }
10217
10218                 if (csum8 == 0) {
10219                         err = 0;
10220                         goto out;
10221                 }
10222
10223                 err = -EIO;
10224                 goto out;
10225         }
10226
10227         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10228             TG3_EEPROM_MAGIC_HW) {
10229                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10230                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10231                 u8 *buf8 = (u8 *) buf;
10232
10233                 /* Separate the parity bits and the data bytes.  */
10234                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10235                         if ((i == 0) || (i == 8)) {
10236                                 int l;
10237                                 u8 msk;
10238
10239                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10240                                         parity[k++] = buf8[i] & msk;
10241                                 i++;
10242                         } else if (i == 16) {
10243                                 int l;
10244                                 u8 msk;
10245
10246                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10247                                         parity[k++] = buf8[i] & msk;
10248                                 i++;
10249
10250                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10251                                         parity[k++] = buf8[i] & msk;
10252                                 i++;
10253                         }
10254                         data[j++] = buf8[i];
10255                 }
10256
10257                 err = -EIO;
10258                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10259                         u8 hw8 = hweight8(data[i]);
10260
10261                         if ((hw8 & 0x1) && parity[i])
10262                                 goto out;
10263                         else if (!(hw8 & 0x1) && !parity[i])
10264                                 goto out;
10265                 }
10266                 err = 0;
10267                 goto out;
10268         }
10269
10270         /* Bootstrap checksum at offset 0x10 */
10271         csum = calc_crc((unsigned char *) buf, 0x10);
10272         if (csum != be32_to_cpu(buf[0x10/4]))
10273                 goto out;
10274
10275         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10276         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10277         if (csum != be32_to_cpu(buf[0xfc/4]))
10278                 goto out;
10279
10280         err = 0;
10281
10282 out:
10283         kfree(buf);
10284         return err;
10285 }
10286
10287 #define TG3_SERDES_TIMEOUT_SEC  2
10288 #define TG3_COPPER_TIMEOUT_SEC  6
10289
10290 static int tg3_test_link(struct tg3 *tp)
10291 {
10292         int i, max;
10293
10294         if (!netif_running(tp->dev))
10295                 return -ENODEV;
10296
10297         if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
10298                 max = TG3_SERDES_TIMEOUT_SEC;
10299         else
10300                 max = TG3_COPPER_TIMEOUT_SEC;
10301
10302         for (i = 0; i < max; i++) {
10303                 if (netif_carrier_ok(tp->dev))
10304                         return 0;
10305
10306                 if (msleep_interruptible(1000))
10307                         break;
10308         }
10309
10310         return -EIO;
10311 }
10312
10313 /* Only test the commonly used registers */
10314 static int tg3_test_registers(struct tg3 *tp)
10315 {
10316         int i, is_5705, is_5750;
10317         u32 offset, read_mask, write_mask, val, save_val, read_val;
10318         static struct {
10319                 u16 offset;
10320                 u16 flags;
10321 #define TG3_FL_5705     0x1
10322 #define TG3_FL_NOT_5705 0x2
10323 #define TG3_FL_NOT_5788 0x4
10324 #define TG3_FL_NOT_5750 0x8
10325                 u32 read_mask;
10326                 u32 write_mask;
10327         } reg_tbl[] = {
10328                 /* MAC Control Registers */
10329                 { MAC_MODE, TG3_FL_NOT_5705,
10330                         0x00000000, 0x00ef6f8c },
10331                 { MAC_MODE, TG3_FL_5705,
10332                         0x00000000, 0x01ef6b8c },
10333                 { MAC_STATUS, TG3_FL_NOT_5705,
10334                         0x03800107, 0x00000000 },
10335                 { MAC_STATUS, TG3_FL_5705,
10336                         0x03800100, 0x00000000 },
10337                 { MAC_ADDR_0_HIGH, 0x0000,
10338                         0x00000000, 0x0000ffff },
10339                 { MAC_ADDR_0_LOW, 0x0000,
10340                         0x00000000, 0xffffffff },
10341                 { MAC_RX_MTU_SIZE, 0x0000,
10342                         0x00000000, 0x0000ffff },
10343                 { MAC_TX_MODE, 0x0000,
10344                         0x00000000, 0x00000070 },
10345                 { MAC_TX_LENGTHS, 0x0000,
10346                         0x00000000, 0x00003fff },
10347                 { MAC_RX_MODE, TG3_FL_NOT_5705,
10348                         0x00000000, 0x000007fc },
10349                 { MAC_RX_MODE, TG3_FL_5705,
10350                         0x00000000, 0x000007dc },
10351                 { MAC_HASH_REG_0, 0x0000,
10352                         0x00000000, 0xffffffff },
10353                 { MAC_HASH_REG_1, 0x0000,
10354                         0x00000000, 0xffffffff },
10355                 { MAC_HASH_REG_2, 0x0000,
10356                         0x00000000, 0xffffffff },
10357                 { MAC_HASH_REG_3, 0x0000,
10358                         0x00000000, 0xffffffff },
10359
10360                 /* Receive Data and Receive BD Initiator Control Registers. */
10361                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10362                         0x00000000, 0xffffffff },
10363                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10364                         0x00000000, 0xffffffff },
10365                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10366                         0x00000000, 0x00000003 },
10367                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10368                         0x00000000, 0xffffffff },
10369                 { RCVDBDI_STD_BD+0, 0x0000,
10370                         0x00000000, 0xffffffff },
10371                 { RCVDBDI_STD_BD+4, 0x0000,
10372                         0x00000000, 0xffffffff },
10373                 { RCVDBDI_STD_BD+8, 0x0000,
10374                         0x00000000, 0xffff0002 },
10375                 { RCVDBDI_STD_BD+0xc, 0x0000,
10376                         0x00000000, 0xffffffff },
10377
10378                 /* Receive BD Initiator Control Registers. */
10379                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10380                         0x00000000, 0xffffffff },
10381                 { RCVBDI_STD_THRESH, TG3_FL_5705,
10382                         0x00000000, 0x000003ff },
10383                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10384                         0x00000000, 0xffffffff },
10385
10386                 /* Host Coalescing Control Registers. */
10387                 { HOSTCC_MODE, TG3_FL_NOT_5705,
10388                         0x00000000, 0x00000004 },
10389                 { HOSTCC_MODE, TG3_FL_5705,
10390                         0x00000000, 0x000000f6 },
10391                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10392                         0x00000000, 0xffffffff },
10393                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10394                         0x00000000, 0x000003ff },
10395                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10396                         0x00000000, 0xffffffff },
10397                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10398                         0x00000000, 0x000003ff },
10399                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10400                         0x00000000, 0xffffffff },
10401                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10402                         0x00000000, 0x000000ff },
10403                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10404                         0x00000000, 0xffffffff },
10405                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10406                         0x00000000, 0x000000ff },
10407                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10408                         0x00000000, 0xffffffff },
10409                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10410                         0x00000000, 0xffffffff },
10411                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10412                         0x00000000, 0xffffffff },
10413                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10414                         0x00000000, 0x000000ff },
10415                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10416                         0x00000000, 0xffffffff },
10417                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10418                         0x00000000, 0x000000ff },
10419                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10420                         0x00000000, 0xffffffff },
10421                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10422                         0x00000000, 0xffffffff },
10423                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10424                         0x00000000, 0xffffffff },
10425                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10426                         0x00000000, 0xffffffff },
10427                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10428                         0x00000000, 0xffffffff },
10429                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10430                         0xffffffff, 0x00000000 },
10431                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10432                         0xffffffff, 0x00000000 },
10433
10434                 /* Buffer Manager Control Registers. */
10435                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10436                         0x00000000, 0x007fff80 },
10437                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10438                         0x00000000, 0x007fffff },
10439                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10440                         0x00000000, 0x0000003f },
10441                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10442                         0x00000000, 0x000001ff },
10443                 { BUFMGR_MB_HIGH_WATER, 0x0000,
10444                         0x00000000, 0x000001ff },
10445                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10446                         0xffffffff, 0x00000000 },
10447                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10448                         0xffffffff, 0x00000000 },
10449
10450                 /* Mailbox Registers */
10451                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10452                         0x00000000, 0x000001ff },
10453                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10454                         0x00000000, 0x000001ff },
10455                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10456                         0x00000000, 0x000007ff },
10457                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10458                         0x00000000, 0x000001ff },
10459
10460                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10461         };
10462
10463         is_5705 = is_5750 = 0;
10464         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10465                 is_5705 = 1;
10466                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10467                         is_5750 = 1;
10468         }
10469
10470         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10471                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10472                         continue;
10473
10474                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10475                         continue;
10476
10477                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10478                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
10479                         continue;
10480
10481                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10482                         continue;
10483
10484                 offset = (u32) reg_tbl[i].offset;
10485                 read_mask = reg_tbl[i].read_mask;
10486                 write_mask = reg_tbl[i].write_mask;
10487
10488                 /* Save the original register content */
10489                 save_val = tr32(offset);
10490
10491                 /* Determine the read-only value. */
10492                 read_val = save_val & read_mask;
10493
10494                 /* Write zero to the register, then make sure the read-only bits
10495                  * are not changed and the read/write bits are all zeros.
10496                  */
10497                 tw32(offset, 0);
10498
10499                 val = tr32(offset);
10500
10501                 /* Test the read-only and read/write bits. */
10502                 if (((val & read_mask) != read_val) || (val & write_mask))
10503                         goto out;
10504
10505                 /* Write ones to all the bits defined by RdMask and WrMask, then
10506                  * make sure the read-only bits are not changed and the
10507                  * read/write bits are all ones.
10508                  */
10509                 tw32(offset, read_mask | write_mask);
10510
10511                 val = tr32(offset);
10512
10513                 /* Test the read-only bits. */
10514                 if ((val & read_mask) != read_val)
10515                         goto out;
10516
10517                 /* Test the read/write bits. */
10518                 if ((val & write_mask) != write_mask)
10519                         goto out;
10520
10521                 tw32(offset, save_val);
10522         }
10523
10524         return 0;
10525
10526 out:
10527         if (netif_msg_hw(tp))
10528                 netdev_err(tp->dev,
10529                            "Register test failed at offset %x\n", offset);
10530         tw32(offset, save_val);
10531         return -EIO;
10532 }
10533
10534 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10535 {
10536         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10537         int i;
10538         u32 j;
10539
10540         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10541                 for (j = 0; j < len; j += 4) {
10542                         u32 val;
10543
10544                         tg3_write_mem(tp, offset + j, test_pattern[i]);
10545                         tg3_read_mem(tp, offset + j, &val);
10546                         if (val != test_pattern[i])
10547                                 return -EIO;
10548                 }
10549         }
10550         return 0;
10551 }
10552
10553 static int tg3_test_memory(struct tg3 *tp)
10554 {
10555         static struct mem_entry {
10556                 u32 offset;
10557                 u32 len;
10558         } mem_tbl_570x[] = {
10559                 { 0x00000000, 0x00b50},
10560                 { 0x00002000, 0x1c000},
10561                 { 0xffffffff, 0x00000}
10562         }, mem_tbl_5705[] = {
10563                 { 0x00000100, 0x0000c},
10564                 { 0x00000200, 0x00008},
10565                 { 0x00004000, 0x00800},
10566                 { 0x00006000, 0x01000},
10567                 { 0x00008000, 0x02000},
10568                 { 0x00010000, 0x0e000},
10569                 { 0xffffffff, 0x00000}
10570         }, mem_tbl_5755[] = {
10571                 { 0x00000200, 0x00008},
10572                 { 0x00004000, 0x00800},
10573                 { 0x00006000, 0x00800},
10574                 { 0x00008000, 0x02000},
10575                 { 0x00010000, 0x0c000},
10576                 { 0xffffffff, 0x00000}
10577         }, mem_tbl_5906[] = {
10578                 { 0x00000200, 0x00008},
10579                 { 0x00004000, 0x00400},
10580                 { 0x00006000, 0x00400},
10581                 { 0x00008000, 0x01000},
10582                 { 0x00010000, 0x01000},
10583                 { 0xffffffff, 0x00000}
10584         }, mem_tbl_5717[] = {
10585                 { 0x00000200, 0x00008},
10586                 { 0x00010000, 0x0a000},
10587                 { 0x00020000, 0x13c00},
10588                 { 0xffffffff, 0x00000}
10589         }, mem_tbl_57765[] = {
10590                 { 0x00000200, 0x00008},
10591                 { 0x00004000, 0x00800},
10592                 { 0x00006000, 0x09800},
10593                 { 0x00010000, 0x0a000},
10594                 { 0xffffffff, 0x00000}
10595         };
10596         struct mem_entry *mem_tbl;
10597         int err = 0;
10598         int i;
10599
10600         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
10601             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
10602                 mem_tbl = mem_tbl_5717;
10603         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10604                 mem_tbl = mem_tbl_57765;
10605         else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10606                 mem_tbl = mem_tbl_5755;
10607         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10608                 mem_tbl = mem_tbl_5906;
10609         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10610                 mem_tbl = mem_tbl_5705;
10611         else
10612                 mem_tbl = mem_tbl_570x;
10613
10614         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10615                 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
10616                 if (err)
10617                         break;
10618         }
10619
10620         return err;
10621 }
10622
10623 #define TG3_MAC_LOOPBACK        0
10624 #define TG3_PHY_LOOPBACK        1
10625
10626 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10627 {
10628         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10629         u32 desc_idx, coal_now;
10630         struct sk_buff *skb, *rx_skb;
10631         u8 *tx_data;
10632         dma_addr_t map;
10633         int num_pkts, tx_len, rx_len, i, err;
10634         struct tg3_rx_buffer_desc *desc;
10635         struct tg3_napi *tnapi, *rnapi;
10636         struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
10637
10638         tnapi = &tp->napi[0];
10639         rnapi = &tp->napi[0];
10640         if (tp->irq_cnt > 1) {
10641                 rnapi = &tp->napi[1];
10642                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
10643                         tnapi = &tp->napi[1];
10644         }
10645         coal_now = tnapi->coal_now | rnapi->coal_now;
10646
10647         if (loopback_mode == TG3_MAC_LOOPBACK) {
10648                 /* HW errata - mac loopback fails in some cases on 5780.
10649                  * Normal traffic and PHY loopback are not affected by
10650                  * errata.
10651                  */
10652                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10653                         return 0;
10654
10655                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10656                            MAC_MODE_PORT_INT_LPBACK;
10657                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10658                         mac_mode |= MAC_MODE_LINK_POLARITY;
10659                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
10660                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10661                 else
10662                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10663                 tw32(MAC_MODE, mac_mode);
10664         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10665                 u32 val;
10666
10667                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10668                         tg3_phy_fet_toggle_apd(tp, false);
10669                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10670                 } else
10671                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10672
10673                 tg3_phy_toggle_automdix(tp, 0);
10674
10675                 tg3_writephy(tp, MII_BMCR, val);
10676                 udelay(40);
10677
10678                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10679                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10680                         tg3_writephy(tp, MII_TG3_FET_PTEST,
10681                                      MII_TG3_FET_PTEST_FRC_TX_LINK |
10682                                      MII_TG3_FET_PTEST_FRC_TX_LOCK);
10683                         /* The write needs to be flushed for the AC131 */
10684                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10685                                 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
10686                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10687                 } else
10688                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10689
10690                 /* reset to prevent losing 1st rx packet intermittently */
10691                 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10692                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10693                         udelay(10);
10694                         tw32_f(MAC_RX_MODE, tp->rx_mode);
10695                 }
10696                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10697                         u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
10698                         if (masked_phy_id == TG3_PHY_ID_BCM5401)
10699                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10700                         else if (masked_phy_id == TG3_PHY_ID_BCM5411)
10701                                 mac_mode |= MAC_MODE_LINK_POLARITY;
10702                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
10703                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10704                 }
10705                 tw32(MAC_MODE, mac_mode);
10706         } else {
10707                 return -EINVAL;
10708         }
10709
10710         err = -EIO;
10711
10712         tx_len = 1514;
10713         skb = netdev_alloc_skb(tp->dev, tx_len);
10714         if (!skb)
10715                 return -ENOMEM;
10716
10717         tx_data = skb_put(skb, tx_len);
10718         memcpy(tx_data, tp->dev->dev_addr, 6);
10719         memset(tx_data + 6, 0x0, 8);
10720
10721         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10722
10723         for (i = 14; i < tx_len; i++)
10724                 tx_data[i] = (u8) (i & 0xff);
10725
10726         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10727         if (pci_dma_mapping_error(tp->pdev, map)) {
10728                 dev_kfree_skb(skb);
10729                 return -EIO;
10730         }
10731
10732         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10733                rnapi->coal_now);
10734
10735         udelay(10);
10736
10737         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10738
10739         num_pkts = 0;
10740
10741         tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10742
10743         tnapi->tx_prod++;
10744         num_pkts++;
10745
10746         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10747         tr32_mailbox(tnapi->prodmbox);
10748
10749         udelay(10);
10750
10751         /* 350 usec to allow enough time on some 10/100 Mbps devices.  */
10752         for (i = 0; i < 35; i++) {
10753                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10754                        coal_now);
10755
10756                 udelay(10);
10757
10758                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10759                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10760                 if ((tx_idx == tnapi->tx_prod) &&
10761                     (rx_idx == (rx_start_idx + num_pkts)))
10762                         break;
10763         }
10764
10765         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10766         dev_kfree_skb(skb);
10767
10768         if (tx_idx != tnapi->tx_prod)
10769                 goto out;
10770
10771         if (rx_idx != rx_start_idx + num_pkts)
10772                 goto out;
10773
10774         desc = &rnapi->rx_rcb[rx_start_idx];
10775         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10776         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10777         if (opaque_key != RXD_OPAQUE_RING_STD)
10778                 goto out;
10779
10780         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10781             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10782                 goto out;
10783
10784         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10785         if (rx_len != tx_len)
10786                 goto out;
10787
10788         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10789
10790         map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10791         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10792
10793         for (i = 14; i < tx_len; i++) {
10794                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10795                         goto out;
10796         }
10797         err = 0;
10798
10799         /* tg3_free_rings will unmap and free the rx_skb */
10800 out:
10801         return err;
10802 }
10803
10804 #define TG3_MAC_LOOPBACK_FAILED         1
10805 #define TG3_PHY_LOOPBACK_FAILED         2
10806 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
10807                                          TG3_PHY_LOOPBACK_FAILED)
10808
10809 static int tg3_test_loopback(struct tg3 *tp)
10810 {
10811         int err = 0;
10812         u32 cpmuctrl = 0;
10813
10814         if (!netif_running(tp->dev))
10815                 return TG3_LOOPBACK_FAILED;
10816
10817         err = tg3_reset_hw(tp, 1);
10818         if (err)
10819                 return TG3_LOOPBACK_FAILED;
10820
10821         /* Turn off gphy autopowerdown. */
10822         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
10823                 tg3_phy_toggle_apd(tp, false);
10824
10825         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10826                 int i;
10827                 u32 status;
10828
10829                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10830
10831                 /* Wait for up to 40 microseconds to acquire lock. */
10832                 for (i = 0; i < 4; i++) {
10833                         status = tr32(TG3_CPMU_MUTEX_GNT);
10834                         if (status == CPMU_MUTEX_GNT_DRIVER)
10835                                 break;
10836                         udelay(10);
10837                 }
10838
10839                 if (status != CPMU_MUTEX_GNT_DRIVER)
10840                         return TG3_LOOPBACK_FAILED;
10841
10842                 /* Turn off link-based power management. */
10843                 cpmuctrl = tr32(TG3_CPMU_CTRL);
10844                 tw32(TG3_CPMU_CTRL,
10845                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10846                                   CPMU_CTRL_LINK_AWARE_MODE));
10847         }
10848
10849         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10850                 err |= TG3_MAC_LOOPBACK_FAILED;
10851
10852         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10853                 tw32(TG3_CPMU_CTRL, cpmuctrl);
10854
10855                 /* Release the mutex */
10856                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10857         }
10858
10859         if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10860             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10861                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10862                         err |= TG3_PHY_LOOPBACK_FAILED;
10863         }
10864
10865         /* Re-enable gphy autopowerdown. */
10866         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
10867                 tg3_phy_toggle_apd(tp, true);
10868
10869         return err;
10870 }
10871
10872 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10873                           u64 *data)
10874 {
10875         struct tg3 *tp = netdev_priv(dev);
10876
10877         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10878                 tg3_set_power_state(tp, PCI_D0);
10879
10880         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10881
10882         if (tg3_test_nvram(tp) != 0) {
10883                 etest->flags |= ETH_TEST_FL_FAILED;
10884                 data[0] = 1;
10885         }
10886         if (tg3_test_link(tp) != 0) {
10887                 etest->flags |= ETH_TEST_FL_FAILED;
10888                 data[1] = 1;
10889         }
10890         if (etest->flags & ETH_TEST_FL_OFFLINE) {
10891                 int err, err2 = 0, irq_sync = 0;
10892
10893                 if (netif_running(dev)) {
10894                         tg3_phy_stop(tp);
10895                         tg3_netif_stop(tp);
10896                         irq_sync = 1;
10897                 }
10898
10899                 tg3_full_lock(tp, irq_sync);
10900
10901                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10902                 err = tg3_nvram_lock(tp);
10903                 tg3_halt_cpu(tp, RX_CPU_BASE);
10904                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10905                         tg3_halt_cpu(tp, TX_CPU_BASE);
10906                 if (!err)
10907                         tg3_nvram_unlock(tp);
10908
10909                 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
10910                         tg3_phy_reset(tp);
10911
10912                 if (tg3_test_registers(tp) != 0) {
10913                         etest->flags |= ETH_TEST_FL_FAILED;
10914                         data[2] = 1;
10915                 }
10916                 if (tg3_test_memory(tp) != 0) {
10917                         etest->flags |= ETH_TEST_FL_FAILED;
10918                         data[3] = 1;
10919                 }
10920                 if ((data[4] = tg3_test_loopback(tp)) != 0)
10921                         etest->flags |= ETH_TEST_FL_FAILED;
10922
10923                 tg3_full_unlock(tp);
10924
10925                 if (tg3_test_interrupt(tp) != 0) {
10926                         etest->flags |= ETH_TEST_FL_FAILED;
10927                         data[5] = 1;
10928                 }
10929
10930                 tg3_full_lock(tp, 0);
10931
10932                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10933                 if (netif_running(dev)) {
10934                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10935                         err2 = tg3_restart_hw(tp, 1);
10936                         if (!err2)
10937                                 tg3_netif_start(tp);
10938                 }
10939
10940                 tg3_full_unlock(tp);
10941
10942                 if (irq_sync && !err2)
10943                         tg3_phy_start(tp);
10944         }
10945         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10946                 tg3_set_power_state(tp, PCI_D3hot);
10947
10948 }
10949
10950 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10951 {
10952         struct mii_ioctl_data *data = if_mii(ifr);
10953         struct tg3 *tp = netdev_priv(dev);
10954         int err;
10955
10956         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10957                 struct phy_device *phydev;
10958                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10959                         return -EAGAIN;
10960                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10961                 return phy_mii_ioctl(phydev, ifr, cmd);
10962         }
10963
10964         switch (cmd) {
10965         case SIOCGMIIPHY:
10966                 data->phy_id = tp->phy_addr;
10967
10968                 /* fallthru */
10969         case SIOCGMIIREG: {
10970                 u32 mii_regval;
10971
10972                 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
10973                         break;                  /* We have no PHY */
10974
10975                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10976                         return -EAGAIN;
10977
10978                 spin_lock_bh(&tp->lock);
10979                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10980                 spin_unlock_bh(&tp->lock);
10981
10982                 data->val_out = mii_regval;
10983
10984                 return err;
10985         }
10986
10987         case SIOCSMIIREG:
10988                 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
10989                         break;                  /* We have no PHY */
10990
10991                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10992                         return -EAGAIN;
10993
10994                 spin_lock_bh(&tp->lock);
10995                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10996                 spin_unlock_bh(&tp->lock);
10997
10998                 return err;
10999
11000         default:
11001                 /* do nothing */
11002                 break;
11003         }
11004         return -EOPNOTSUPP;
11005 }
11006
11007 #if TG3_VLAN_TAG_USED
11008 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
11009 {
11010         struct tg3 *tp = netdev_priv(dev);
11011
11012         if (!netif_running(dev)) {
11013                 tp->vlgrp = grp;
11014                 return;
11015         }
11016
11017         tg3_netif_stop(tp);
11018
11019         tg3_full_lock(tp, 0);
11020
11021         tp->vlgrp = grp;
11022
11023         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11024         __tg3_set_rx_mode(dev);
11025
11026         tg3_netif_start(tp);
11027
11028         tg3_full_unlock(tp);
11029 }
11030 #endif
11031
11032 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11033 {
11034         struct tg3 *tp = netdev_priv(dev);
11035
11036         memcpy(ec, &tp->coal, sizeof(*ec));
11037         return 0;
11038 }
11039
11040 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11041 {
11042         struct tg3 *tp = netdev_priv(dev);
11043         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11044         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11045
11046         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11047                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11048                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11049                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11050                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11051         }
11052
11053         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11054             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11055             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11056             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11057             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11058             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11059             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11060             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11061             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11062             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11063                 return -EINVAL;
11064
11065         /* No rx interrupts will be generated if both are zero */
11066         if ((ec->rx_coalesce_usecs == 0) &&
11067             (ec->rx_max_coalesced_frames == 0))
11068                 return -EINVAL;
11069
11070         /* No tx interrupts will be generated if both are zero */
11071         if ((ec->tx_coalesce_usecs == 0) &&
11072             (ec->tx_max_coalesced_frames == 0))
11073                 return -EINVAL;
11074
11075         /* Only copy relevant parameters, ignore all others. */
11076         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11077         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11078         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11079         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11080         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11081         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11082         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11083         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11084         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11085
11086         if (netif_running(dev)) {
11087                 tg3_full_lock(tp, 0);
11088                 __tg3_set_coalesce(tp, &tp->coal);
11089                 tg3_full_unlock(tp);
11090         }
11091         return 0;
11092 }
11093
11094 static const struct ethtool_ops tg3_ethtool_ops = {
11095         .get_settings           = tg3_get_settings,
11096         .set_settings           = tg3_set_settings,
11097         .get_drvinfo            = tg3_get_drvinfo,
11098         .get_regs_len           = tg3_get_regs_len,
11099         .get_regs               = tg3_get_regs,
11100         .get_wol                = tg3_get_wol,
11101         .set_wol                = tg3_set_wol,
11102         .get_msglevel           = tg3_get_msglevel,
11103         .set_msglevel           = tg3_set_msglevel,
11104         .nway_reset             = tg3_nway_reset,
11105         .get_link               = ethtool_op_get_link,
11106         .get_eeprom_len         = tg3_get_eeprom_len,
11107         .get_eeprom             = tg3_get_eeprom,
11108         .set_eeprom             = tg3_set_eeprom,
11109         .get_ringparam          = tg3_get_ringparam,
11110         .set_ringparam          = tg3_set_ringparam,
11111         .get_pauseparam         = tg3_get_pauseparam,
11112         .set_pauseparam         = tg3_set_pauseparam,
11113         .get_rx_csum            = tg3_get_rx_csum,
11114         .set_rx_csum            = tg3_set_rx_csum,
11115         .set_tx_csum            = tg3_set_tx_csum,
11116         .set_sg                 = ethtool_op_set_sg,
11117         .set_tso                = tg3_set_tso,
11118         .self_test              = tg3_self_test,
11119         .get_strings            = tg3_get_strings,
11120         .phys_id                = tg3_phys_id,
11121         .get_ethtool_stats      = tg3_get_ethtool_stats,
11122         .get_coalesce           = tg3_get_coalesce,
11123         .set_coalesce           = tg3_set_coalesce,
11124         .get_sset_count         = tg3_get_sset_count,
11125 };
11126
11127 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11128 {
11129         u32 cursize, val, magic;
11130
11131         tp->nvram_size = EEPROM_CHIP_SIZE;
11132
11133         if (tg3_nvram_read(tp, 0, &magic) != 0)
11134                 return;
11135
11136         if ((magic != TG3_EEPROM_MAGIC) &&
11137             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11138             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11139                 return;
11140
11141         /*
11142          * Size the chip by reading offsets at increasing powers of two.
11143          * When we encounter our validation signature, we know the addressing
11144          * has wrapped around, and thus have our chip size.
11145          */
11146         cursize = 0x10;
11147
11148         while (cursize < tp->nvram_size) {
11149                 if (tg3_nvram_read(tp, cursize, &val) != 0)
11150                         return;
11151
11152                 if (val == magic)
11153                         break;
11154
11155                 cursize <<= 1;
11156         }
11157
11158         tp->nvram_size = cursize;
11159 }
11160
11161 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11162 {
11163         u32 val;
11164
11165         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11166             tg3_nvram_read(tp, 0, &val) != 0)
11167                 return;
11168
11169         /* Selfboot format */
11170         if (val != TG3_EEPROM_MAGIC) {
11171                 tg3_get_eeprom_size(tp);
11172                 return;
11173         }
11174
11175         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11176                 if (val != 0) {
11177                         /* This is confusing.  We want to operate on the
11178                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
11179                          * call will read from NVRAM and byteswap the data
11180                          * according to the byteswapping settings for all
11181                          * other register accesses.  This ensures the data we
11182                          * want will always reside in the lower 16-bits.
11183                          * However, the data in NVRAM is in LE format, which
11184                          * means the data from the NVRAM read will always be
11185                          * opposite the endianness of the CPU.  The 16-bit
11186                          * byteswap then brings the data to CPU endianness.
11187                          */
11188                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11189                         return;
11190                 }
11191         }
11192         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11193 }
11194
11195 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11196 {
11197         u32 nvcfg1;
11198
11199         nvcfg1 = tr32(NVRAM_CFG1);
11200         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11201                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11202         } else {
11203                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11204                 tw32(NVRAM_CFG1, nvcfg1);
11205         }
11206
11207         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11208             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11209                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11210                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11211                         tp->nvram_jedecnum = JEDEC_ATMEL;
11212                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11213                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11214                         break;
11215                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11216                         tp->nvram_jedecnum = JEDEC_ATMEL;
11217                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11218                         break;
11219                 case FLASH_VENDOR_ATMEL_EEPROM:
11220                         tp->nvram_jedecnum = JEDEC_ATMEL;
11221                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11222                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11223                         break;
11224                 case FLASH_VENDOR_ST:
11225                         tp->nvram_jedecnum = JEDEC_ST;
11226                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11227                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11228                         break;
11229                 case FLASH_VENDOR_SAIFUN:
11230                         tp->nvram_jedecnum = JEDEC_SAIFUN;
11231                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11232                         break;
11233                 case FLASH_VENDOR_SST_SMALL:
11234                 case FLASH_VENDOR_SST_LARGE:
11235                         tp->nvram_jedecnum = JEDEC_SST;
11236                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11237                         break;
11238                 }
11239         } else {
11240                 tp->nvram_jedecnum = JEDEC_ATMEL;
11241                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11242                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11243         }
11244 }
11245
11246 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11247 {
11248         switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11249         case FLASH_5752PAGE_SIZE_256:
11250                 tp->nvram_pagesize = 256;
11251                 break;
11252         case FLASH_5752PAGE_SIZE_512:
11253                 tp->nvram_pagesize = 512;
11254                 break;
11255         case FLASH_5752PAGE_SIZE_1K:
11256                 tp->nvram_pagesize = 1024;
11257                 break;
11258         case FLASH_5752PAGE_SIZE_2K:
11259                 tp->nvram_pagesize = 2048;
11260                 break;
11261         case FLASH_5752PAGE_SIZE_4K:
11262                 tp->nvram_pagesize = 4096;
11263                 break;
11264         case FLASH_5752PAGE_SIZE_264:
11265                 tp->nvram_pagesize = 264;
11266                 break;
11267         case FLASH_5752PAGE_SIZE_528:
11268                 tp->nvram_pagesize = 528;
11269                 break;
11270         }
11271 }
11272
11273 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11274 {
11275         u32 nvcfg1;
11276
11277         nvcfg1 = tr32(NVRAM_CFG1);
11278
11279         /* NVRAM protection for TPM */
11280         if (nvcfg1 & (1 << 27))
11281                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11282
11283         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11284         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11285         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11286                 tp->nvram_jedecnum = JEDEC_ATMEL;
11287                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11288                 break;
11289         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11290                 tp->nvram_jedecnum = JEDEC_ATMEL;
11291                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11292                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11293                 break;
11294         case FLASH_5752VENDOR_ST_M45PE10:
11295         case FLASH_5752VENDOR_ST_M45PE20:
11296         case FLASH_5752VENDOR_ST_M45PE40:
11297                 tp->nvram_jedecnum = JEDEC_ST;
11298                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11299                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11300                 break;
11301         }
11302
11303         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11304                 tg3_nvram_get_pagesize(tp, nvcfg1);
11305         } else {
11306                 /* For eeprom, set pagesize to maximum eeprom size */
11307                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11308
11309                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11310                 tw32(NVRAM_CFG1, nvcfg1);
11311         }
11312 }
11313
11314 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11315 {
11316         u32 nvcfg1, protect = 0;
11317
11318         nvcfg1 = tr32(NVRAM_CFG1);
11319
11320         /* NVRAM protection for TPM */
11321         if (nvcfg1 & (1 << 27)) {
11322                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11323                 protect = 1;
11324         }
11325
11326         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11327         switch (nvcfg1) {
11328         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11329         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11330         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11331         case FLASH_5755VENDOR_ATMEL_FLASH_5:
11332                 tp->nvram_jedecnum = JEDEC_ATMEL;
11333                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11334                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11335                 tp->nvram_pagesize = 264;
11336                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11337                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11338                         tp->nvram_size = (protect ? 0x3e200 :
11339                                           TG3_NVRAM_SIZE_512KB);
11340                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11341                         tp->nvram_size = (protect ? 0x1f200 :
11342                                           TG3_NVRAM_SIZE_256KB);
11343                 else
11344                         tp->nvram_size = (protect ? 0x1f200 :
11345                                           TG3_NVRAM_SIZE_128KB);
11346                 break;
11347         case FLASH_5752VENDOR_ST_M45PE10:
11348         case FLASH_5752VENDOR_ST_M45PE20:
11349         case FLASH_5752VENDOR_ST_M45PE40:
11350                 tp->nvram_jedecnum = JEDEC_ST;
11351                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11352                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11353                 tp->nvram_pagesize = 256;
11354                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11355                         tp->nvram_size = (protect ?
11356                                           TG3_NVRAM_SIZE_64KB :
11357                                           TG3_NVRAM_SIZE_128KB);
11358                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11359                         tp->nvram_size = (protect ?
11360                                           TG3_NVRAM_SIZE_64KB :
11361                                           TG3_NVRAM_SIZE_256KB);
11362                 else
11363                         tp->nvram_size = (protect ?
11364                                           TG3_NVRAM_SIZE_128KB :
11365                                           TG3_NVRAM_SIZE_512KB);
11366                 break;
11367         }
11368 }
11369
11370 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11371 {
11372         u32 nvcfg1;
11373
11374         nvcfg1 = tr32(NVRAM_CFG1);
11375
11376         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11377         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11378         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11379         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11380         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11381                 tp->nvram_jedecnum = JEDEC_ATMEL;
11382                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11383                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11384
11385                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11386                 tw32(NVRAM_CFG1, nvcfg1);
11387                 break;
11388         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11389         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11390         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11391         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11392                 tp->nvram_jedecnum = JEDEC_ATMEL;
11393                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11394                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11395                 tp->nvram_pagesize = 264;
11396                 break;
11397         case FLASH_5752VENDOR_ST_M45PE10:
11398         case FLASH_5752VENDOR_ST_M45PE20:
11399         case FLASH_5752VENDOR_ST_M45PE40:
11400                 tp->nvram_jedecnum = JEDEC_ST;
11401                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11402                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11403                 tp->nvram_pagesize = 256;
11404                 break;
11405         }
11406 }
11407
11408 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11409 {
11410         u32 nvcfg1, protect = 0;
11411
11412         nvcfg1 = tr32(NVRAM_CFG1);
11413
11414         /* NVRAM protection for TPM */
11415         if (nvcfg1 & (1 << 27)) {
11416                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11417                 protect = 1;
11418         }
11419
11420         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11421         switch (nvcfg1) {
11422         case FLASH_5761VENDOR_ATMEL_ADB021D:
11423         case FLASH_5761VENDOR_ATMEL_ADB041D:
11424         case FLASH_5761VENDOR_ATMEL_ADB081D:
11425         case FLASH_5761VENDOR_ATMEL_ADB161D:
11426         case FLASH_5761VENDOR_ATMEL_MDB021D:
11427         case FLASH_5761VENDOR_ATMEL_MDB041D:
11428         case FLASH_5761VENDOR_ATMEL_MDB081D:
11429         case FLASH_5761VENDOR_ATMEL_MDB161D:
11430                 tp->nvram_jedecnum = JEDEC_ATMEL;
11431                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11432                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11433                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11434                 tp->nvram_pagesize = 256;
11435                 break;
11436         case FLASH_5761VENDOR_ST_A_M45PE20:
11437         case FLASH_5761VENDOR_ST_A_M45PE40:
11438         case FLASH_5761VENDOR_ST_A_M45PE80:
11439         case FLASH_5761VENDOR_ST_A_M45PE16:
11440         case FLASH_5761VENDOR_ST_M_M45PE20:
11441         case FLASH_5761VENDOR_ST_M_M45PE40:
11442         case FLASH_5761VENDOR_ST_M_M45PE80:
11443         case FLASH_5761VENDOR_ST_M_M45PE16:
11444                 tp->nvram_jedecnum = JEDEC_ST;
11445                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11446                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11447                 tp->nvram_pagesize = 256;
11448                 break;
11449         }
11450
11451         if (protect) {
11452                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11453         } else {
11454                 switch (nvcfg1) {
11455                 case FLASH_5761VENDOR_ATMEL_ADB161D:
11456                 case FLASH_5761VENDOR_ATMEL_MDB161D:
11457                 case FLASH_5761VENDOR_ST_A_M45PE16:
11458                 case FLASH_5761VENDOR_ST_M_M45PE16:
11459                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11460                         break;
11461                 case FLASH_5761VENDOR_ATMEL_ADB081D:
11462                 case FLASH_5761VENDOR_ATMEL_MDB081D:
11463                 case FLASH_5761VENDOR_ST_A_M45PE80:
11464                 case FLASH_5761VENDOR_ST_M_M45PE80:
11465                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11466                         break;
11467                 case FLASH_5761VENDOR_ATMEL_ADB041D:
11468                 case FLASH_5761VENDOR_ATMEL_MDB041D:
11469                 case FLASH_5761VENDOR_ST_A_M45PE40:
11470                 case FLASH_5761VENDOR_ST_M_M45PE40:
11471                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11472                         break;
11473                 case FLASH_5761VENDOR_ATMEL_ADB021D:
11474                 case FLASH_5761VENDOR_ATMEL_MDB021D:
11475                 case FLASH_5761VENDOR_ST_A_M45PE20:
11476                 case FLASH_5761VENDOR_ST_M_M45PE20:
11477                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11478                         break;
11479                 }
11480         }
11481 }
11482
11483 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11484 {
11485         tp->nvram_jedecnum = JEDEC_ATMEL;
11486         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11487         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11488 }
11489
11490 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11491 {
11492         u32 nvcfg1;
11493
11494         nvcfg1 = tr32(NVRAM_CFG1);
11495
11496         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11497         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11498         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11499                 tp->nvram_jedecnum = JEDEC_ATMEL;
11500                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11501                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11502
11503                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11504                 tw32(NVRAM_CFG1, nvcfg1);
11505                 return;
11506         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11507         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11508         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11509         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11510         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11511         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11512         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11513                 tp->nvram_jedecnum = JEDEC_ATMEL;
11514                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11515                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11516
11517                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11518                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11519                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11520                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11521                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11522                         break;
11523                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11524                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11525                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11526                         break;
11527                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11528                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11529                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11530                         break;
11531                 }
11532                 break;
11533         case FLASH_5752VENDOR_ST_M45PE10:
11534         case FLASH_5752VENDOR_ST_M45PE20:
11535         case FLASH_5752VENDOR_ST_M45PE40:
11536                 tp->nvram_jedecnum = JEDEC_ST;
11537                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11538                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11539
11540                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11541                 case FLASH_5752VENDOR_ST_M45PE10:
11542                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11543                         break;
11544                 case FLASH_5752VENDOR_ST_M45PE20:
11545                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11546                         break;
11547                 case FLASH_5752VENDOR_ST_M45PE40:
11548                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11549                         break;
11550                 }
11551                 break;
11552         default:
11553                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11554                 return;
11555         }
11556
11557         tg3_nvram_get_pagesize(tp, nvcfg1);
11558         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11559                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11560 }
11561
11562
11563 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11564 {
11565         u32 nvcfg1;
11566
11567         nvcfg1 = tr32(NVRAM_CFG1);
11568
11569         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11570         case FLASH_5717VENDOR_ATMEL_EEPROM:
11571         case FLASH_5717VENDOR_MICRO_EEPROM:
11572                 tp->nvram_jedecnum = JEDEC_ATMEL;
11573                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11574                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11575
11576                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11577                 tw32(NVRAM_CFG1, nvcfg1);
11578                 return;
11579         case FLASH_5717VENDOR_ATMEL_MDB011D:
11580         case FLASH_5717VENDOR_ATMEL_ADB011B:
11581         case FLASH_5717VENDOR_ATMEL_ADB011D:
11582         case FLASH_5717VENDOR_ATMEL_MDB021D:
11583         case FLASH_5717VENDOR_ATMEL_ADB021B:
11584         case FLASH_5717VENDOR_ATMEL_ADB021D:
11585         case FLASH_5717VENDOR_ATMEL_45USPT:
11586                 tp->nvram_jedecnum = JEDEC_ATMEL;
11587                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11588                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11589
11590                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11591                 case FLASH_5717VENDOR_ATMEL_MDB021D:
11592                 case FLASH_5717VENDOR_ATMEL_ADB021B:
11593                 case FLASH_5717VENDOR_ATMEL_ADB021D:
11594                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11595                         break;
11596                 default:
11597                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11598                         break;
11599                 }
11600                 break;
11601         case FLASH_5717VENDOR_ST_M_M25PE10:
11602         case FLASH_5717VENDOR_ST_A_M25PE10:
11603         case FLASH_5717VENDOR_ST_M_M45PE10:
11604         case FLASH_5717VENDOR_ST_A_M45PE10:
11605         case FLASH_5717VENDOR_ST_M_M25PE20:
11606         case FLASH_5717VENDOR_ST_A_M25PE20:
11607         case FLASH_5717VENDOR_ST_M_M45PE20:
11608         case FLASH_5717VENDOR_ST_A_M45PE20:
11609         case FLASH_5717VENDOR_ST_25USPT:
11610         case FLASH_5717VENDOR_ST_45USPT:
11611                 tp->nvram_jedecnum = JEDEC_ST;
11612                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11613                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11614
11615                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11616                 case FLASH_5717VENDOR_ST_M_M25PE20:
11617                 case FLASH_5717VENDOR_ST_A_M25PE20:
11618                 case FLASH_5717VENDOR_ST_M_M45PE20:
11619                 case FLASH_5717VENDOR_ST_A_M45PE20:
11620                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11621                         break;
11622                 default:
11623                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11624                         break;
11625                 }
11626                 break;
11627         default:
11628                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11629                 return;
11630         }
11631
11632         tg3_nvram_get_pagesize(tp, nvcfg1);
11633         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11634                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11635 }
11636
11637 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11638 static void __devinit tg3_nvram_init(struct tg3 *tp)
11639 {
11640         tw32_f(GRC_EEPROM_ADDR,
11641              (EEPROM_ADDR_FSM_RESET |
11642               (EEPROM_DEFAULT_CLOCK_PERIOD <<
11643                EEPROM_ADDR_CLKPERD_SHIFT)));
11644
11645         msleep(1);
11646
11647         /* Enable seeprom accesses. */
11648         tw32_f(GRC_LOCAL_CTRL,
11649              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11650         udelay(100);
11651
11652         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11653             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11654                 tp->tg3_flags |= TG3_FLAG_NVRAM;
11655
11656                 if (tg3_nvram_lock(tp)) {
11657                         netdev_warn(tp->dev,
11658                                     "Cannot get nvram lock, %s failed\n",
11659                                     __func__);
11660                         return;
11661                 }
11662                 tg3_enable_nvram_access(tp);
11663
11664                 tp->nvram_size = 0;
11665
11666                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11667                         tg3_get_5752_nvram_info(tp);
11668                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11669                         tg3_get_5755_nvram_info(tp);
11670                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11671                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11672                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11673                         tg3_get_5787_nvram_info(tp);
11674                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11675                         tg3_get_5761_nvram_info(tp);
11676                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11677                         tg3_get_5906_nvram_info(tp);
11678                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11679                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11680                         tg3_get_57780_nvram_info(tp);
11681                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
11682                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
11683                         tg3_get_5717_nvram_info(tp);
11684                 else
11685                         tg3_get_nvram_info(tp);
11686
11687                 if (tp->nvram_size == 0)
11688                         tg3_get_nvram_size(tp);
11689
11690                 tg3_disable_nvram_access(tp);
11691                 tg3_nvram_unlock(tp);
11692
11693         } else {
11694                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11695
11696                 tg3_get_eeprom_size(tp);
11697         }
11698 }
11699
11700 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11701                                     u32 offset, u32 len, u8 *buf)
11702 {
11703         int i, j, rc = 0;
11704         u32 val;
11705
11706         for (i = 0; i < len; i += 4) {
11707                 u32 addr;
11708                 __be32 data;
11709
11710                 addr = offset + i;
11711
11712                 memcpy(&data, buf + i, 4);
11713
11714                 /*
11715                  * The SEEPROM interface expects the data to always be opposite
11716                  * the native endian format.  We accomplish this by reversing
11717                  * all the operations that would have been performed on the
11718                  * data from a call to tg3_nvram_read_be32().
11719                  */
11720                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11721
11722                 val = tr32(GRC_EEPROM_ADDR);
11723                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11724
11725                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11726                         EEPROM_ADDR_READ);
11727                 tw32(GRC_EEPROM_ADDR, val |
11728                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
11729                         (addr & EEPROM_ADDR_ADDR_MASK) |
11730                         EEPROM_ADDR_START |
11731                         EEPROM_ADDR_WRITE);
11732
11733                 for (j = 0; j < 1000; j++) {
11734                         val = tr32(GRC_EEPROM_ADDR);
11735
11736                         if (val & EEPROM_ADDR_COMPLETE)
11737                                 break;
11738                         msleep(1);
11739                 }
11740                 if (!(val & EEPROM_ADDR_COMPLETE)) {
11741                         rc = -EBUSY;
11742                         break;
11743                 }
11744         }
11745
11746         return rc;
11747 }
11748
11749 /* offset and length are dword aligned */
11750 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11751                 u8 *buf)
11752 {
11753         int ret = 0;
11754         u32 pagesize = tp->nvram_pagesize;
11755         u32 pagemask = pagesize - 1;
11756         u32 nvram_cmd;
11757         u8 *tmp;
11758
11759         tmp = kmalloc(pagesize, GFP_KERNEL);
11760         if (tmp == NULL)
11761                 return -ENOMEM;
11762
11763         while (len) {
11764                 int j;
11765                 u32 phy_addr, page_off, size;
11766
11767                 phy_addr = offset & ~pagemask;
11768
11769                 for (j = 0; j < pagesize; j += 4) {
11770                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
11771                                                   (__be32 *) (tmp + j));
11772                         if (ret)
11773                                 break;
11774                 }
11775                 if (ret)
11776                         break;
11777
11778                 page_off = offset & pagemask;
11779                 size = pagesize;
11780                 if (len < size)
11781                         size = len;
11782
11783                 len -= size;
11784
11785                 memcpy(tmp + page_off, buf, size);
11786
11787                 offset = offset + (pagesize - page_off);
11788
11789                 tg3_enable_nvram_access(tp);
11790
11791                 /*
11792                  * Before we can erase the flash page, we need
11793                  * to issue a special "write enable" command.
11794                  */
11795                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11796
11797                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11798                         break;
11799
11800                 /* Erase the target page */
11801                 tw32(NVRAM_ADDR, phy_addr);
11802
11803                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11804                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11805
11806                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11807                         break;
11808
11809                 /* Issue another write enable to start the write. */
11810                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11811
11812                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11813                         break;
11814
11815                 for (j = 0; j < pagesize; j += 4) {
11816                         __be32 data;
11817
11818                         data = *((__be32 *) (tmp + j));
11819
11820                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
11821
11822                         tw32(NVRAM_ADDR, phy_addr + j);
11823
11824                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11825                                 NVRAM_CMD_WR;
11826
11827                         if (j == 0)
11828                                 nvram_cmd |= NVRAM_CMD_FIRST;
11829                         else if (j == (pagesize - 4))
11830                                 nvram_cmd |= NVRAM_CMD_LAST;
11831
11832                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11833                                 break;
11834                 }
11835                 if (ret)
11836                         break;
11837         }
11838
11839         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11840         tg3_nvram_exec_cmd(tp, nvram_cmd);
11841
11842         kfree(tmp);
11843
11844         return ret;
11845 }
11846
11847 /* offset and length are dword aligned */
11848 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11849                 u8 *buf)
11850 {
11851         int i, ret = 0;
11852
11853         for (i = 0; i < len; i += 4, offset += 4) {
11854                 u32 page_off, phy_addr, nvram_cmd;
11855                 __be32 data;
11856
11857                 memcpy(&data, buf + i, 4);
11858                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11859
11860                 page_off = offset % tp->nvram_pagesize;
11861
11862                 phy_addr = tg3_nvram_phys_addr(tp, offset);
11863
11864                 tw32(NVRAM_ADDR, phy_addr);
11865
11866                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11867
11868                 if (page_off == 0 || i == 0)
11869                         nvram_cmd |= NVRAM_CMD_FIRST;
11870                 if (page_off == (tp->nvram_pagesize - 4))
11871                         nvram_cmd |= NVRAM_CMD_LAST;
11872
11873                 if (i == (len - 4))
11874                         nvram_cmd |= NVRAM_CMD_LAST;
11875
11876                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11877                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11878                     (tp->nvram_jedecnum == JEDEC_ST) &&
11879                     (nvram_cmd & NVRAM_CMD_FIRST)) {
11880
11881                         if ((ret = tg3_nvram_exec_cmd(tp,
11882                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11883                                 NVRAM_CMD_DONE)))
11884
11885                                 break;
11886                 }
11887                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11888                         /* We always do complete word writes to eeprom. */
11889                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11890                 }
11891
11892                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11893                         break;
11894         }
11895         return ret;
11896 }
11897
11898 /* offset and length are dword aligned */
11899 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11900 {
11901         int ret;
11902
11903         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11904                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11905                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
11906                 udelay(40);
11907         }
11908
11909         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11910                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11911         } else {
11912                 u32 grc_mode;
11913
11914                 ret = tg3_nvram_lock(tp);
11915                 if (ret)
11916                         return ret;
11917
11918                 tg3_enable_nvram_access(tp);
11919                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11920                     !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
11921                         tw32(NVRAM_WRITE1, 0x406);
11922
11923                 grc_mode = tr32(GRC_MODE);
11924                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11925
11926                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11927                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11928
11929                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
11930                                 buf);
11931                 } else {
11932                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11933                                 buf);
11934                 }
11935
11936                 grc_mode = tr32(GRC_MODE);
11937                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11938
11939                 tg3_disable_nvram_access(tp);
11940                 tg3_nvram_unlock(tp);
11941         }
11942
11943         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11944                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11945                 udelay(40);
11946         }
11947
11948         return ret;
11949 }
11950
11951 struct subsys_tbl_ent {
11952         u16 subsys_vendor, subsys_devid;
11953         u32 phy_id;
11954 };
11955
11956 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
11957         /* Broadcom boards. */
11958         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11959           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
11960         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11961           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
11962         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11963           TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
11964         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11965           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
11966         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11967           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
11968         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11969           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
11970         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11971           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
11972         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11973           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
11974         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11975           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
11976         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11977           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
11978         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11979           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
11980
11981         /* 3com boards. */
11982         { TG3PCI_SUBVENDOR_ID_3COM,
11983           TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
11984         { TG3PCI_SUBVENDOR_ID_3COM,
11985           TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
11986         { TG3PCI_SUBVENDOR_ID_3COM,
11987           TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
11988         { TG3PCI_SUBVENDOR_ID_3COM,
11989           TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
11990         { TG3PCI_SUBVENDOR_ID_3COM,
11991           TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
11992
11993         /* DELL boards. */
11994         { TG3PCI_SUBVENDOR_ID_DELL,
11995           TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
11996         { TG3PCI_SUBVENDOR_ID_DELL,
11997           TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
11998         { TG3PCI_SUBVENDOR_ID_DELL,
11999           TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
12000         { TG3PCI_SUBVENDOR_ID_DELL,
12001           TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
12002
12003         /* Compaq boards. */
12004         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12005           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
12006         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12007           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
12008         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12009           TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
12010         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12011           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
12012         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12013           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
12014
12015         /* IBM boards. */
12016         { TG3PCI_SUBVENDOR_ID_IBM,
12017           TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
12018 };
12019
12020 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
12021 {
12022         int i;
12023
12024         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12025                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12026                      tp->pdev->subsystem_vendor) &&
12027                     (subsys_id_to_phy_id[i].subsys_devid ==
12028                      tp->pdev->subsystem_device))
12029                         return &subsys_id_to_phy_id[i];
12030         }
12031         return NULL;
12032 }
12033
12034 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12035 {
12036         u32 val;
12037         u16 pmcsr;
12038
12039         /* On some early chips the SRAM cannot be accessed in D3hot state,
12040          * so need make sure we're in D0.
12041          */
12042         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12043         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12044         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12045         msleep(1);
12046
12047         /* Make sure register accesses (indirect or otherwise)
12048          * will function correctly.
12049          */
12050         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12051                                tp->misc_host_ctrl);
12052
12053         /* The memory arbiter has to be enabled in order for SRAM accesses
12054          * to succeed.  Normally on powerup the tg3 chip firmware will make
12055          * sure it is enabled, but other entities such as system netboot
12056          * code might disable it.
12057          */
12058         val = tr32(MEMARB_MODE);
12059         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12060
12061         tp->phy_id = TG3_PHY_ID_INVALID;
12062         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12063
12064         /* Assume an onboard device and WOL capable by default.  */
12065         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12066
12067         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12068                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12069                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12070                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12071                 }
12072                 val = tr32(VCPU_CFGSHDW);
12073                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12074                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12075                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12076                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
12077                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12078                 goto done;
12079         }
12080
12081         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12082         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12083                 u32 nic_cfg, led_cfg;
12084                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12085                 int eeprom_phy_serdes = 0;
12086
12087                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12088                 tp->nic_sram_data_cfg = nic_cfg;
12089
12090                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12091                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12092                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12093                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12094                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12095                     (ver > 0) && (ver < 0x100))
12096                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12097
12098                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12099                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12100
12101                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12102                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12103                         eeprom_phy_serdes = 1;
12104
12105                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12106                 if (nic_phy_id != 0) {
12107                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12108                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12109
12110                         eeprom_phy_id  = (id1 >> 16) << 10;
12111                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
12112                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
12113                 } else
12114                         eeprom_phy_id = 0;
12115
12116                 tp->phy_id = eeprom_phy_id;
12117                 if (eeprom_phy_serdes) {
12118                         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12119                                 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12120                         else
12121                                 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
12122                 }
12123
12124                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12125                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12126                                     SHASTA_EXT_LED_MODE_MASK);
12127                 else
12128                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12129
12130                 switch (led_cfg) {
12131                 default:
12132                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12133                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12134                         break;
12135
12136                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12137                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12138                         break;
12139
12140                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12141                         tp->led_ctrl = LED_CTRL_MODE_MAC;
12142
12143                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12144                          * read on some older 5700/5701 bootcode.
12145                          */
12146                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12147                             ASIC_REV_5700 ||
12148                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
12149                             ASIC_REV_5701)
12150                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12151
12152                         break;
12153
12154                 case SHASTA_EXT_LED_SHARED:
12155                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
12156                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12157                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12158                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12159                                                  LED_CTRL_MODE_PHY_2);
12160                         break;
12161
12162                 case SHASTA_EXT_LED_MAC:
12163                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12164                         break;
12165
12166                 case SHASTA_EXT_LED_COMBO:
12167                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
12168                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12169                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12170                                                  LED_CTRL_MODE_PHY_2);
12171                         break;
12172
12173                 }
12174
12175                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12176                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12177                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12178                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12179
12180                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12181                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12182
12183                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12184                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12185                         if ((tp->pdev->subsystem_vendor ==
12186                              PCI_VENDOR_ID_ARIMA) &&
12187                             (tp->pdev->subsystem_device == 0x205a ||
12188                              tp->pdev->subsystem_device == 0x2063))
12189                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12190                 } else {
12191                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12192                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12193                 }
12194
12195                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12196                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12197                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12198                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12199                 }
12200
12201                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12202                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12203                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12204
12205                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
12206                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12207                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12208
12209                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12210                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12211                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12212
12213                 if (cfg2 & (1 << 17))
12214                         tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
12215
12216                 /* serdes signal pre-emphasis in register 0x590 set by */
12217                 /* bootcode if bit 18 is set */
12218                 if (cfg2 & (1 << 18))
12219                         tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
12220
12221                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12222                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
12223                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12224                         tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
12225
12226                 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12227                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12228                     !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
12229                         u32 cfg3;
12230
12231                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12232                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12233                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12234                 }
12235
12236                 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12237                         tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
12238                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12239                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12240                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12241                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12242         }
12243 done:
12244         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12245         device_set_wakeup_enable(&tp->pdev->dev,
12246                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12247 }
12248
12249 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12250 {
12251         int i;
12252         u32 val;
12253
12254         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12255         tw32(OTP_CTRL, cmd);
12256
12257         /* Wait for up to 1 ms for command to execute. */
12258         for (i = 0; i < 100; i++) {
12259                 val = tr32(OTP_STATUS);
12260                 if (val & OTP_STATUS_CMD_DONE)
12261                         break;
12262                 udelay(10);
12263         }
12264
12265         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12266 }
12267
12268 /* Read the gphy configuration from the OTP region of the chip.  The gphy
12269  * configuration is a 32-bit value that straddles the alignment boundary.
12270  * We do two 32-bit reads and then shift and merge the results.
12271  */
12272 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12273 {
12274         u32 bhalf_otp, thalf_otp;
12275
12276         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12277
12278         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12279                 return 0;
12280
12281         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12282
12283         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12284                 return 0;
12285
12286         thalf_otp = tr32(OTP_READ_DATA);
12287
12288         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12289
12290         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12291                 return 0;
12292
12293         bhalf_otp = tr32(OTP_READ_DATA);
12294
12295         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12296 }
12297
12298 static int __devinit tg3_phy_probe(struct tg3 *tp)
12299 {
12300         u32 hw_phy_id_1, hw_phy_id_2;
12301         u32 hw_phy_id, hw_phy_id_masked;
12302         int err;
12303
12304         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12305                 return tg3_phy_init(tp);
12306
12307         /* Reading the PHY ID register can conflict with ASF
12308          * firmware access to the PHY hardware.
12309          */
12310         err = 0;
12311         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12312             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12313                 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
12314         } else {
12315                 /* Now read the physical PHY_ID from the chip and verify
12316                  * that it is sane.  If it doesn't look good, we fall back
12317                  * to either the hard-coded table based PHY_ID and failing
12318                  * that the value found in the eeprom area.
12319                  */
12320                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12321                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12322
12323                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
12324                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12325                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
12326
12327                 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
12328         }
12329
12330         if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
12331                 tp->phy_id = hw_phy_id;
12332                 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
12333                         tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12334                 else
12335                         tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
12336         } else {
12337                 if (tp->phy_id != TG3_PHY_ID_INVALID) {
12338                         /* Do nothing, phy ID already set up in
12339                          * tg3_get_eeprom_hw_cfg().
12340                          */
12341                 } else {
12342                         struct subsys_tbl_ent *p;
12343
12344                         /* No eeprom signature?  Try the hardcoded
12345                          * subsys device table.
12346                          */
12347                         p = tg3_lookup_by_subsys(tp);
12348                         if (!p)
12349                                 return -ENODEV;
12350
12351                         tp->phy_id = p->phy_id;
12352                         if (!tp->phy_id ||
12353                             tp->phy_id == TG3_PHY_ID_BCM8002)
12354                                 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12355                 }
12356         }
12357
12358         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
12359             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12360             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12361                 u32 bmsr, adv_reg, tg3_ctrl, mask;
12362
12363                 tg3_readphy(tp, MII_BMSR, &bmsr);
12364                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12365                     (bmsr & BMSR_LSTATUS))
12366                         goto skip_phy_reset;
12367
12368                 err = tg3_phy_reset(tp);
12369                 if (err)
12370                         return err;
12371
12372                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12373                            ADVERTISE_100HALF | ADVERTISE_100FULL |
12374                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12375                 tg3_ctrl = 0;
12376                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
12377                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12378                                     MII_TG3_CTRL_ADV_1000_FULL);
12379                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12380                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12381                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12382                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
12383                 }
12384
12385                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12386                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12387                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12388                 if (!tg3_copper_is_advertising_all(tp, mask)) {
12389                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12390
12391                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12392                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12393
12394                         tg3_writephy(tp, MII_BMCR,
12395                                      BMCR_ANENABLE | BMCR_ANRESTART);
12396                 }
12397                 tg3_phy_set_wirespeed(tp);
12398
12399                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12400                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12401                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12402         }
12403
12404 skip_phy_reset:
12405         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
12406                 err = tg3_init_5401phy_dsp(tp);
12407                 if (err)
12408                         return err;
12409
12410                 err = tg3_init_5401phy_dsp(tp);
12411         }
12412
12413         if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
12414                 tp->link_config.advertising =
12415                         (ADVERTISED_1000baseT_Half |
12416                          ADVERTISED_1000baseT_Full |
12417                          ADVERTISED_Autoneg |
12418                          ADVERTISED_FIBRE);
12419         if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
12420                 tp->link_config.advertising &=
12421                         ~(ADVERTISED_1000baseT_Half |
12422                           ADVERTISED_1000baseT_Full);
12423
12424         return err;
12425 }
12426
12427 static void __devinit tg3_read_vpd(struct tg3 *tp)
12428 {
12429         u8 *vpd_data;
12430         unsigned int block_end, rosize, len;
12431         int j, i = 0;
12432         u32 magic;
12433
12434         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12435             tg3_nvram_read(tp, 0x0, &magic))
12436                 goto out_no_vpd;
12437
12438         vpd_data = kmalloc(TG3_NVM_VPD_LEN, GFP_KERNEL);
12439         if (!vpd_data)
12440                 goto out_no_vpd;
12441
12442         if (magic == TG3_EEPROM_MAGIC) {
12443                 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12444                         u32 tmp;
12445
12446                         /* The data is in little-endian format in NVRAM.
12447                          * Use the big-endian read routines to preserve
12448                          * the byte order as it exists in NVRAM.
12449                          */
12450                         if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12451                                 goto out_not_found;
12452
12453                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12454                 }
12455         } else {
12456                 ssize_t cnt;
12457                 unsigned int pos = 0;
12458
12459                 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12460                         cnt = pci_read_vpd(tp->pdev, pos,
12461                                            TG3_NVM_VPD_LEN - pos,
12462                                            &vpd_data[pos]);
12463                         if (cnt == -ETIMEDOUT || -EINTR)
12464                                 cnt = 0;
12465                         else if (cnt < 0)
12466                                 goto out_not_found;
12467                 }
12468                 if (pos != TG3_NVM_VPD_LEN)
12469                         goto out_not_found;
12470         }
12471
12472         i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
12473                              PCI_VPD_LRDT_RO_DATA);
12474         if (i < 0)
12475                 goto out_not_found;
12476
12477         rosize = pci_vpd_lrdt_size(&vpd_data[i]);
12478         block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
12479         i += PCI_VPD_LRDT_TAG_SIZE;
12480
12481         if (block_end > TG3_NVM_VPD_LEN)
12482                 goto out_not_found;
12483
12484         j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12485                                       PCI_VPD_RO_KEYWORD_MFR_ID);
12486         if (j > 0) {
12487                 len = pci_vpd_info_field_size(&vpd_data[j]);
12488
12489                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12490                 if (j + len > block_end || len != 4 ||
12491                     memcmp(&vpd_data[j], "1028", 4))
12492                         goto partno;
12493
12494                 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12495                                               PCI_VPD_RO_KEYWORD_VENDOR0);
12496                 if (j < 0)
12497                         goto partno;
12498
12499                 len = pci_vpd_info_field_size(&vpd_data[j]);
12500
12501                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12502                 if (j + len > block_end)
12503                         goto partno;
12504
12505                 memcpy(tp->fw_ver, &vpd_data[j], len);
12506                 strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
12507         }
12508
12509 partno:
12510         i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12511                                       PCI_VPD_RO_KEYWORD_PARTNO);
12512         if (i < 0)
12513                 goto out_not_found;
12514
12515         len = pci_vpd_info_field_size(&vpd_data[i]);
12516
12517         i += PCI_VPD_INFO_FLD_HDR_SIZE;
12518         if (len > TG3_BPN_SIZE ||
12519             (len + i) > TG3_NVM_VPD_LEN)
12520                 goto out_not_found;
12521
12522         memcpy(tp->board_part_number, &vpd_data[i], len);
12523
12524 out_not_found:
12525         kfree(vpd_data);
12526         if (!tp->board_part_number[0])
12527                 return;
12528
12529 out_no_vpd:
12530         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12531                 strcpy(tp->board_part_number, "BCM95906");
12532         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12533                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12534                 strcpy(tp->board_part_number, "BCM57780");
12535         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12536                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12537                 strcpy(tp->board_part_number, "BCM57760");
12538         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12539                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12540                 strcpy(tp->board_part_number, "BCM57790");
12541         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12542                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12543                 strcpy(tp->board_part_number, "BCM57788");
12544         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12545                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
12546                 strcpy(tp->board_part_number, "BCM57761");
12547         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12548                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
12549                 strcpy(tp->board_part_number, "BCM57765");
12550         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12551                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
12552                 strcpy(tp->board_part_number, "BCM57781");
12553         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12554                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
12555                 strcpy(tp->board_part_number, "BCM57785");
12556         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12557                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
12558                 strcpy(tp->board_part_number, "BCM57791");
12559         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12560                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12561                 strcpy(tp->board_part_number, "BCM57795");
12562         else
12563                 strcpy(tp->board_part_number, "none");
12564 }
12565
12566 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12567 {
12568         u32 val;
12569
12570         if (tg3_nvram_read(tp, offset, &val) ||
12571             (val & 0xfc000000) != 0x0c000000 ||
12572             tg3_nvram_read(tp, offset + 4, &val) ||
12573             val != 0)
12574                 return 0;
12575
12576         return 1;
12577 }
12578
12579 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12580 {
12581         u32 val, offset, start, ver_offset;
12582         int i, dst_off;
12583         bool newver = false;
12584
12585         if (tg3_nvram_read(tp, 0xc, &offset) ||
12586             tg3_nvram_read(tp, 0x4, &start))
12587                 return;
12588
12589         offset = tg3_nvram_logical_addr(tp, offset);
12590
12591         if (tg3_nvram_read(tp, offset, &val))
12592                 return;
12593
12594         if ((val & 0xfc000000) == 0x0c000000) {
12595                 if (tg3_nvram_read(tp, offset + 4, &val))
12596                         return;
12597
12598                 if (val == 0)
12599                         newver = true;
12600         }
12601
12602         dst_off = strlen(tp->fw_ver);
12603
12604         if (newver) {
12605                 if (TG3_VER_SIZE - dst_off < 16 ||
12606                     tg3_nvram_read(tp, offset + 8, &ver_offset))
12607                         return;
12608
12609                 offset = offset + ver_offset - start;
12610                 for (i = 0; i < 16; i += 4) {
12611                         __be32 v;
12612                         if (tg3_nvram_read_be32(tp, offset + i, &v))
12613                                 return;
12614
12615                         memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
12616                 }
12617         } else {
12618                 u32 major, minor;
12619
12620                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12621                         return;
12622
12623                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12624                         TG3_NVM_BCVER_MAJSFT;
12625                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12626                 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
12627                          "v%d.%02d", major, minor);
12628         }
12629 }
12630
12631 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12632 {
12633         u32 val, major, minor;
12634
12635         /* Use native endian representation */
12636         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12637                 return;
12638
12639         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12640                 TG3_NVM_HWSB_CFG1_MAJSFT;
12641         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12642                 TG3_NVM_HWSB_CFG1_MINSFT;
12643
12644         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12645 }
12646
12647 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12648 {
12649         u32 offset, major, minor, build;
12650
12651         strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
12652
12653         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12654                 return;
12655
12656         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12657         case TG3_EEPROM_SB_REVISION_0:
12658                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12659                 break;
12660         case TG3_EEPROM_SB_REVISION_2:
12661                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12662                 break;
12663         case TG3_EEPROM_SB_REVISION_3:
12664                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12665                 break;
12666         case TG3_EEPROM_SB_REVISION_4:
12667                 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
12668                 break;
12669         case TG3_EEPROM_SB_REVISION_5:
12670                 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
12671                 break;
12672         default:
12673                 return;
12674         }
12675
12676         if (tg3_nvram_read(tp, offset, &val))
12677                 return;
12678
12679         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12680                 TG3_EEPROM_SB_EDH_BLD_SHFT;
12681         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12682                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12683         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
12684
12685         if (minor > 99 || build > 26)
12686                 return;
12687
12688         offset = strlen(tp->fw_ver);
12689         snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
12690                  " v%d.%02d", major, minor);
12691
12692         if (build > 0) {
12693                 offset = strlen(tp->fw_ver);
12694                 if (offset < TG3_VER_SIZE - 1)
12695                         tp->fw_ver[offset] = 'a' + build - 1;
12696         }
12697 }
12698
12699 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12700 {
12701         u32 val, offset, start;
12702         int i, vlen;
12703
12704         for (offset = TG3_NVM_DIR_START;
12705              offset < TG3_NVM_DIR_END;
12706              offset += TG3_NVM_DIRENT_SIZE) {
12707                 if (tg3_nvram_read(tp, offset, &val))
12708                         return;
12709
12710                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12711                         break;
12712         }
12713
12714         if (offset == TG3_NVM_DIR_END)
12715                 return;
12716
12717         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12718                 start = 0x08000000;
12719         else if (tg3_nvram_read(tp, offset - 4, &start))
12720                 return;
12721
12722         if (tg3_nvram_read(tp, offset + 4, &offset) ||
12723             !tg3_fw_img_is_valid(tp, offset) ||
12724             tg3_nvram_read(tp, offset + 8, &val))
12725                 return;
12726
12727         offset += val - start;
12728
12729         vlen = strlen(tp->fw_ver);
12730
12731         tp->fw_ver[vlen++] = ',';
12732         tp->fw_ver[vlen++] = ' ';
12733
12734         for (i = 0; i < 4; i++) {
12735                 __be32 v;
12736                 if (tg3_nvram_read_be32(tp, offset, &v))
12737                         return;
12738
12739                 offset += sizeof(v);
12740
12741                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12742                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12743                         break;
12744                 }
12745
12746                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12747                 vlen += sizeof(v);
12748         }
12749 }
12750
12751 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12752 {
12753         int vlen;
12754         u32 apedata;
12755         char *fwtype;
12756
12757         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12758             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
12759                 return;
12760
12761         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12762         if (apedata != APE_SEG_SIG_MAGIC)
12763                 return;
12764
12765         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12766         if (!(apedata & APE_FW_STATUS_READY))
12767                 return;
12768
12769         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12770
12771         if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) {
12772                 tp->tg3_flags3 |= TG3_FLG3_APE_HAS_NCSI;
12773                 fwtype = "NCSI";
12774         } else {
12775                 fwtype = "DASH";
12776         }
12777
12778         vlen = strlen(tp->fw_ver);
12779
12780         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
12781                  fwtype,
12782                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12783                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12784                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12785                  (apedata & APE_FW_VERSION_BLDMSK));
12786 }
12787
12788 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12789 {
12790         u32 val;
12791         bool vpd_vers = false;
12792
12793         if (tp->fw_ver[0] != 0)
12794                 vpd_vers = true;
12795
12796         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12797                 strcat(tp->fw_ver, "sb");
12798                 return;
12799         }
12800
12801         if (tg3_nvram_read(tp, 0, &val))
12802                 return;
12803
12804         if (val == TG3_EEPROM_MAGIC)
12805                 tg3_read_bc_ver(tp);
12806         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12807                 tg3_read_sb_ver(tp, val);
12808         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12809                 tg3_read_hwsb_ver(tp);
12810         else
12811                 return;
12812
12813         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12814              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
12815                 goto done;
12816
12817         tg3_read_mgmtfw_ver(tp);
12818
12819 done:
12820         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12821 }
12822
12823 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12824
12825 static void inline vlan_features_add(struct net_device *dev, unsigned long flags)
12826 {
12827 #if TG3_VLAN_TAG_USED
12828         dev->vlan_features |= flags;
12829 #endif
12830 }
12831
12832 static int __devinit tg3_get_invariants(struct tg3 *tp)
12833 {
12834         static struct pci_device_id write_reorder_chipsets[] = {
12835                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12836                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12837                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12838                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12839                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12840                              PCI_DEVICE_ID_VIA_8385_0) },
12841                 { },
12842         };
12843         u32 misc_ctrl_reg;
12844         u32 pci_state_reg, grc_misc_cfg;
12845         u32 val;
12846         u16 pci_cmd;
12847         int err;
12848
12849         /* Force memory write invalidate off.  If we leave it on,
12850          * then on 5700_BX chips we have to enable a workaround.
12851          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12852          * to match the cacheline size.  The Broadcom driver have this
12853          * workaround but turns MWI off all the times so never uses
12854          * it.  This seems to suggest that the workaround is insufficient.
12855          */
12856         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12857         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12858         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12859
12860         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12861          * has the register indirect write enable bit set before
12862          * we try to access any of the MMIO registers.  It is also
12863          * critical that the PCI-X hw workaround situation is decided
12864          * before that as well.
12865          */
12866         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12867                               &misc_ctrl_reg);
12868
12869         tp->pci_chip_rev_id = (misc_ctrl_reg >>
12870                                MISC_HOST_CTRL_CHIPREV_SHIFT);
12871         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12872                 u32 prod_id_asic_rev;
12873
12874                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12875                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12876                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724 ||
12877                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719)
12878                         pci_read_config_dword(tp->pdev,
12879                                               TG3PCI_GEN2_PRODID_ASICREV,
12880                                               &prod_id_asic_rev);
12881                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
12882                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
12883                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
12884                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
12885                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
12886                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12887                         pci_read_config_dword(tp->pdev,
12888                                               TG3PCI_GEN15_PRODID_ASICREV,
12889                                               &prod_id_asic_rev);
12890                 else
12891                         pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12892                                               &prod_id_asic_rev);
12893
12894                 tp->pci_chip_rev_id = prod_id_asic_rev;
12895         }
12896
12897         /* Wrong chip ID in 5752 A0. This code can be removed later
12898          * as A0 is not in production.
12899          */
12900         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12901                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12902
12903         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12904          * we need to disable memory and use config. cycles
12905          * only to access all registers. The 5702/03 chips
12906          * can mistakenly decode the special cycles from the
12907          * ICH chipsets as memory write cycles, causing corruption
12908          * of register and memory space. Only certain ICH bridges
12909          * will drive special cycles with non-zero data during the
12910          * address phase which can fall within the 5703's address
12911          * range. This is not an ICH bug as the PCI spec allows
12912          * non-zero address during special cycles. However, only
12913          * these ICH bridges are known to drive non-zero addresses
12914          * during special cycles.
12915          *
12916          * Since special cycles do not cross PCI bridges, we only
12917          * enable this workaround if the 5703 is on the secondary
12918          * bus of these ICH bridges.
12919          */
12920         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12921             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12922                 static struct tg3_dev_id {
12923                         u32     vendor;
12924                         u32     device;
12925                         u32     rev;
12926                 } ich_chipsets[] = {
12927                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12928                           PCI_ANY_ID },
12929                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12930                           PCI_ANY_ID },
12931                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12932                           0xa },
12933                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12934                           PCI_ANY_ID },
12935                         { },
12936                 };
12937                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12938                 struct pci_dev *bridge = NULL;
12939
12940                 while (pci_id->vendor != 0) {
12941                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
12942                                                 bridge);
12943                         if (!bridge) {
12944                                 pci_id++;
12945                                 continue;
12946                         }
12947                         if (pci_id->rev != PCI_ANY_ID) {
12948                                 if (bridge->revision > pci_id->rev)
12949                                         continue;
12950                         }
12951                         if (bridge->subordinate &&
12952                             (bridge->subordinate->number ==
12953                              tp->pdev->bus->number)) {
12954
12955                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12956                                 pci_dev_put(bridge);
12957                                 break;
12958                         }
12959                 }
12960         }
12961
12962         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12963                 static struct tg3_dev_id {
12964                         u32     vendor;
12965                         u32     device;
12966                 } bridge_chipsets[] = {
12967                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12968                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12969                         { },
12970                 };
12971                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12972                 struct pci_dev *bridge = NULL;
12973
12974                 while (pci_id->vendor != 0) {
12975                         bridge = pci_get_device(pci_id->vendor,
12976                                                 pci_id->device,
12977                                                 bridge);
12978                         if (!bridge) {
12979                                 pci_id++;
12980                                 continue;
12981                         }
12982                         if (bridge->subordinate &&
12983                             (bridge->subordinate->number <=
12984                              tp->pdev->bus->number) &&
12985                             (bridge->subordinate->subordinate >=
12986                              tp->pdev->bus->number)) {
12987                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12988                                 pci_dev_put(bridge);
12989                                 break;
12990                         }
12991                 }
12992         }
12993
12994         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12995          * DMA addresses > 40-bit. This bridge may have other additional
12996          * 57xx devices behind it in some 4-port NIC designs for example.
12997          * Any tg3 device found behind the bridge will also need the 40-bit
12998          * DMA workaround.
12999          */
13000         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
13001             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13002                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
13003                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13004                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
13005         } else {
13006                 struct pci_dev *bridge = NULL;
13007
13008                 do {
13009                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
13010                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
13011                                                 bridge);
13012                         if (bridge && bridge->subordinate &&
13013                             (bridge->subordinate->number <=
13014                              tp->pdev->bus->number) &&
13015                             (bridge->subordinate->subordinate >=
13016                              tp->pdev->bus->number)) {
13017                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13018                                 pci_dev_put(bridge);
13019                                 break;
13020                         }
13021                 } while (bridge);
13022         }
13023
13024         /* Initialize misc host control in PCI block. */
13025         tp->misc_host_ctrl |= (misc_ctrl_reg &
13026                                MISC_HOST_CTRL_CHIPREV);
13027         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13028                                tp->misc_host_ctrl);
13029
13030         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13031             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13032             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13033                 tp->pdev_peer = tg3_find_peer(tp);
13034
13035         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13036             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13037             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13038                 tp->tg3_flags3 |= TG3_FLG3_5717_PLUS;
13039
13040         /* Intentionally exclude ASIC_REV_5906 */
13041         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13042             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13043             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13044             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13045             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13046             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13047             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13048                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13049
13050         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13051             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13052             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13053             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13054             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13055                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13056
13057         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13058             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13059                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13060
13061         /* 5700 B0 chips do not support checksumming correctly due
13062          * to hardware bugs.
13063          */
13064         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13065                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13066         else {
13067                 unsigned long features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_GRO;
13068
13069                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13070                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13071                         features |= NETIF_F_IPV6_CSUM;
13072                 tp->dev->features |= features;
13073                 vlan_features_add(tp->dev, features);
13074         }
13075
13076         /* Determine TSO capabilities */
13077         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13078                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13079         else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13080                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13081                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13082         else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13083                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13084                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13085                     tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13086                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13087         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13088                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13089                    tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13090                 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13091                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13092                         tp->fw_needed = FIRMWARE_TG3TSO5;
13093                 else
13094                         tp->fw_needed = FIRMWARE_TG3TSO;
13095         }
13096
13097         tp->irq_max = 1;
13098
13099         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13100                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13101                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13102                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13103                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13104                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13105                      tp->pdev_peer == tp->pdev))
13106                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13107
13108                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13109                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13110                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13111                 }
13112
13113                 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
13114                         tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13115                         tp->irq_max = TG3_IRQ_MAX_VECS;
13116                 }
13117         }
13118
13119         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13120             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13121             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13122                 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13123         else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13124                 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13125                 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13126         }
13127
13128         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13129                 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13130
13131         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13132             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13133             (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13134                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13135
13136         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13137                               &pci_state_reg);
13138
13139         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13140         if (tp->pcie_cap != 0) {
13141                 u16 lnkctl;
13142
13143                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13144
13145                 pcie_set_readrq(tp->pdev, 4096);
13146
13147                 pci_read_config_word(tp->pdev,
13148                                      tp->pcie_cap + PCI_EXP_LNKCTL,
13149                                      &lnkctl);
13150                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13151                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13152                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13153                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13154                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13155                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13156                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13157                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13158                 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13159                         tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13160                 }
13161         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13162                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13163         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13164                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13165                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13166                 if (!tp->pcix_cap) {
13167                         dev_err(&tp->pdev->dev,
13168                                 "Cannot find PCI-X capability, aborting\n");
13169                         return -EIO;
13170                 }
13171
13172                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13173                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13174         }
13175
13176         /* If we have an AMD 762 or VIA K8T800 chipset, write
13177          * reordering to the mailbox registers done by the host
13178          * controller can cause major troubles.  We read back from
13179          * every mailbox register write to force the writes to be
13180          * posted to the chip in order.
13181          */
13182         if (pci_dev_present(write_reorder_chipsets) &&
13183             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13184                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13185
13186         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13187                              &tp->pci_cacheline_sz);
13188         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13189                              &tp->pci_lat_timer);
13190         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13191             tp->pci_lat_timer < 64) {
13192                 tp->pci_lat_timer = 64;
13193                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13194                                       tp->pci_lat_timer);
13195         }
13196
13197         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13198                 /* 5700 BX chips need to have their TX producer index
13199                  * mailboxes written twice to workaround a bug.
13200                  */
13201                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13202
13203                 /* If we are in PCI-X mode, enable register write workaround.
13204                  *
13205                  * The workaround is to use indirect register accesses
13206                  * for all chip writes not to mailbox registers.
13207                  */
13208                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13209                         u32 pm_reg;
13210
13211                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13212
13213                         /* The chip can have it's power management PCI config
13214                          * space registers clobbered due to this bug.
13215                          * So explicitly force the chip into D0 here.
13216                          */
13217                         pci_read_config_dword(tp->pdev,
13218                                               tp->pm_cap + PCI_PM_CTRL,
13219                                               &pm_reg);
13220                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13221                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13222                         pci_write_config_dword(tp->pdev,
13223                                                tp->pm_cap + PCI_PM_CTRL,
13224                                                pm_reg);
13225
13226                         /* Also, force SERR#/PERR# in PCI command. */
13227                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13228                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13229                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13230                 }
13231         }
13232
13233         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13234                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13235         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13236                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13237
13238         /* Chip-specific fixup from Broadcom driver */
13239         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13240             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13241                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13242                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13243         }
13244
13245         /* Default fast path register access methods */
13246         tp->read32 = tg3_read32;
13247         tp->write32 = tg3_write32;
13248         tp->read32_mbox = tg3_read32;
13249         tp->write32_mbox = tg3_write32;
13250         tp->write32_tx_mbox = tg3_write32;
13251         tp->write32_rx_mbox = tg3_write32;
13252
13253         /* Various workaround register access methods */
13254         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13255                 tp->write32 = tg3_write_indirect_reg32;
13256         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13257                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13258                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13259                 /*
13260                  * Back to back register writes can cause problems on these
13261                  * chips, the workaround is to read back all reg writes
13262                  * except those to mailbox regs.
13263                  *
13264                  * See tg3_write_indirect_reg32().
13265                  */
13266                 tp->write32 = tg3_write_flush_reg32;
13267         }
13268
13269         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13270             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13271                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13272                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13273                         tp->write32_rx_mbox = tg3_write_flush_reg32;
13274         }
13275
13276         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13277                 tp->read32 = tg3_read_indirect_reg32;
13278                 tp->write32 = tg3_write_indirect_reg32;
13279                 tp->read32_mbox = tg3_read_indirect_mbox;
13280                 tp->write32_mbox = tg3_write_indirect_mbox;
13281                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13282                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13283
13284                 iounmap(tp->regs);
13285                 tp->regs = NULL;
13286
13287                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13288                 pci_cmd &= ~PCI_COMMAND_MEMORY;
13289                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13290         }
13291         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13292                 tp->read32_mbox = tg3_read32_mbox_5906;
13293                 tp->write32_mbox = tg3_write32_mbox_5906;
13294                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13295                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13296         }
13297
13298         if (tp->write32 == tg3_write_indirect_reg32 ||
13299             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13300              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13301               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13302                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13303
13304         /* Get eeprom hw config before calling tg3_set_power_state().
13305          * In particular, the TG3_FLG2_IS_NIC flag must be
13306          * determined before calling tg3_set_power_state() so that
13307          * we know whether or not to switch out of Vaux power.
13308          * When the flag is set, it means that GPIO1 is used for eeprom
13309          * write protect and also implies that it is a LOM where GPIOs
13310          * are not used to switch power.
13311          */
13312         tg3_get_eeprom_hw_cfg(tp);
13313
13314         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13315                 /* Allow reads and writes to the
13316                  * APE register and memory space.
13317                  */
13318                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13319                                  PCISTATE_ALLOW_APE_SHMEM_WR |
13320                                  PCISTATE_ALLOW_APE_PSPACE_WR;
13321                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13322                                        pci_state_reg);
13323         }
13324
13325         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13326             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13327             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13328             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13329             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13330                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13331
13332         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13333          * GPIO1 driven high will bring 5700's external PHY out of reset.
13334          * It is also used as eeprom write protect on LOMs.
13335          */
13336         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13337         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13338             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13339                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13340                                        GRC_LCLCTRL_GPIO_OUTPUT1);
13341         /* Unused GPIO3 must be driven as output on 5752 because there
13342          * are no pull-up resistors on unused GPIO pins.
13343          */
13344         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13345                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13346
13347         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13348             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13349             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13350                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13351
13352         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13353             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13354                 /* Turn off the debug UART. */
13355                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13356                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13357                         /* Keep VMain power. */
13358                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13359                                               GRC_LCLCTRL_GPIO_OUTPUT0;
13360         }
13361
13362         /* Force the chip into D0. */
13363         err = tg3_set_power_state(tp, PCI_D0);
13364         if (err) {
13365                 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
13366                 return err;
13367         }
13368
13369         /* Derive initial jumbo mode from MTU assigned in
13370          * ether_setup() via the alloc_etherdev() call
13371          */
13372         if (tp->dev->mtu > ETH_DATA_LEN &&
13373             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13374                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13375
13376         /* Determine WakeOnLan speed to use. */
13377         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13378             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13379             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13380             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13381                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13382         } else {
13383                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13384         }
13385
13386         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13387                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
13388
13389         /* A few boards don't want Ethernet@WireSpeed phy feature */
13390         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13391             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13392              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13393              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13394             (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
13395             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
13396                 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
13397
13398         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13399             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13400                 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
13401         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13402                 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
13403
13404         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13405             !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
13406             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13407             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13408             !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
13409                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13410                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13411                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13412                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13413                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13414                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13415                                 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
13416                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13417                                 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
13418                 } else
13419                         tp->phy_flags |= TG3_PHYFLG_BER_BUG;
13420         }
13421
13422         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13423             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13424                 tp->phy_otp = tg3_read_otp_phycfg(tp);
13425                 if (tp->phy_otp == 0)
13426                         tp->phy_otp = TG3_OTP_DEFAULT;
13427         }
13428
13429         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13430                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13431         else
13432                 tp->mi_mode = MAC_MI_MODE_BASE;
13433
13434         tp->coalesce_mode = 0;
13435         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13436             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13437                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13438
13439         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13440             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13441                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13442
13443         err = tg3_mdio_init(tp);
13444         if (err)
13445                 return err;
13446
13447         /* Initialize data/descriptor byte/word swapping. */
13448         val = tr32(GRC_MODE);
13449         val &= GRC_MODE_HOST_STACKUP;
13450         tw32(GRC_MODE, val | tp->grc_mode);
13451
13452         tg3_switch_clocks(tp);
13453
13454         /* Clear this out for sanity. */
13455         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13456
13457         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13458                               &pci_state_reg);
13459         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13460             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13461                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13462
13463                 if (chiprevid == CHIPREV_ID_5701_A0 ||
13464                     chiprevid == CHIPREV_ID_5701_B0 ||
13465                     chiprevid == CHIPREV_ID_5701_B2 ||
13466                     chiprevid == CHIPREV_ID_5701_B5) {
13467                         void __iomem *sram_base;
13468
13469                         /* Write some dummy words into the SRAM status block
13470                          * area, see if it reads back correctly.  If the return
13471                          * value is bad, force enable the PCIX workaround.
13472                          */
13473                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13474
13475                         writel(0x00000000, sram_base);
13476                         writel(0x00000000, sram_base + 4);
13477                         writel(0xffffffff, sram_base + 4);
13478                         if (readl(sram_base) != 0x00000000)
13479                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13480                 }
13481         }
13482
13483         udelay(50);
13484         tg3_nvram_init(tp);
13485
13486         grc_misc_cfg = tr32(GRC_MISC_CFG);
13487         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13488
13489         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13490             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13491              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13492                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13493
13494         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13495             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13496                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13497         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13498                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13499                                       HOSTCC_MODE_CLRTICK_TXBD);
13500
13501                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13502                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13503                                        tp->misc_host_ctrl);
13504         }
13505
13506         /* Preserve the APE MAC_MODE bits */
13507         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13508                 tp->mac_mode = tr32(MAC_MODE) |
13509                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13510         else
13511                 tp->mac_mode = TG3_DEF_MAC_MODE;
13512
13513         /* these are limited to 10/100 only */
13514         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13515              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13516             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13517              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13518              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13519               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13520               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13521             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13522              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13523               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13524               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13525             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13526             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13527             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
13528             (tp->phy_flags & TG3_PHYFLG_IS_FET))
13529                 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
13530
13531         err = tg3_phy_probe(tp);
13532         if (err) {
13533                 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
13534                 /* ... but do not return immediately ... */
13535                 tg3_mdio_fini(tp);
13536         }
13537
13538         tg3_read_vpd(tp);
13539         tg3_read_fw_ver(tp);
13540
13541         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
13542                 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
13543         } else {
13544                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13545                         tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
13546                 else
13547                         tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
13548         }
13549
13550         /* 5700 {AX,BX} chips have a broken status block link
13551          * change bit implementation, so we must use the
13552          * status register in those cases.
13553          */
13554         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13555                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13556         else
13557                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13558
13559         /* The led_ctrl is set during tg3_phy_probe, here we might
13560          * have to force the link status polling mechanism based
13561          * upon subsystem IDs.
13562          */
13563         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13564             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13565             !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
13566                 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
13567                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13568         }
13569
13570         /* For all SERDES we poll the MAC status register. */
13571         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
13572                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13573         else
13574                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13575
13576         tp->rx_offset = NET_IP_ALIGN + TG3_RX_HEADROOM;
13577         tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
13578         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13579             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
13580                 tp->rx_offset -= NET_IP_ALIGN;
13581 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
13582                 tp->rx_copy_thresh = ~(u16)0;
13583 #endif
13584         }
13585
13586         tp->rx_std_max_post = TG3_RX_RING_SIZE;
13587
13588         /* Increment the rx prod index on the rx std ring by at most
13589          * 8 for these chips to workaround hw errata.
13590          */
13591         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13592             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13593             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13594                 tp->rx_std_max_post = 8;
13595
13596         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13597                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13598                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
13599
13600         return err;
13601 }
13602
13603 #ifdef CONFIG_SPARC
13604 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13605 {
13606         struct net_device *dev = tp->dev;
13607         struct pci_dev *pdev = tp->pdev;
13608         struct device_node *dp = pci_device_to_OF_node(pdev);
13609         const unsigned char *addr;
13610         int len;
13611
13612         addr = of_get_property(dp, "local-mac-address", &len);
13613         if (addr && len == 6) {
13614                 memcpy(dev->dev_addr, addr, 6);
13615                 memcpy(dev->perm_addr, dev->dev_addr, 6);
13616                 return 0;
13617         }
13618         return -ENODEV;
13619 }
13620
13621 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13622 {
13623         struct net_device *dev = tp->dev;
13624
13625         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13626         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13627         return 0;
13628 }
13629 #endif
13630
13631 static int __devinit tg3_get_device_address(struct tg3 *tp)
13632 {
13633         struct net_device *dev = tp->dev;
13634         u32 hi, lo, mac_offset;
13635         int addr_ok = 0;
13636
13637 #ifdef CONFIG_SPARC
13638         if (!tg3_get_macaddr_sparc(tp))
13639                 return 0;
13640 #endif
13641
13642         mac_offset = 0x7c;
13643         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13644             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13645                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13646                         mac_offset = 0xcc;
13647                 if (tg3_nvram_lock(tp))
13648                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13649                 else
13650                         tg3_nvram_unlock(tp);
13651         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13652                    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
13653                 if (PCI_FUNC(tp->pdev->devfn) & 1)
13654                         mac_offset = 0xcc;
13655                 if (PCI_FUNC(tp->pdev->devfn) > 1)
13656                         mac_offset += 0x18c;
13657         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13658                 mac_offset = 0x10;
13659
13660         /* First try to get it from MAC address mailbox. */
13661         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13662         if ((hi >> 16) == 0x484b) {
13663                 dev->dev_addr[0] = (hi >>  8) & 0xff;
13664                 dev->dev_addr[1] = (hi >>  0) & 0xff;
13665
13666                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13667                 dev->dev_addr[2] = (lo >> 24) & 0xff;
13668                 dev->dev_addr[3] = (lo >> 16) & 0xff;
13669                 dev->dev_addr[4] = (lo >>  8) & 0xff;
13670                 dev->dev_addr[5] = (lo >>  0) & 0xff;
13671
13672                 /* Some old bootcode may report a 0 MAC address in SRAM */
13673                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13674         }
13675         if (!addr_ok) {
13676                 /* Next, try NVRAM. */
13677                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13678                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13679                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13680                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13681                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13682                 }
13683                 /* Finally just fetch it out of the MAC control regs. */
13684                 else {
13685                         hi = tr32(MAC_ADDR_0_HIGH);
13686                         lo = tr32(MAC_ADDR_0_LOW);
13687
13688                         dev->dev_addr[5] = lo & 0xff;
13689                         dev->dev_addr[4] = (lo >> 8) & 0xff;
13690                         dev->dev_addr[3] = (lo >> 16) & 0xff;
13691                         dev->dev_addr[2] = (lo >> 24) & 0xff;
13692                         dev->dev_addr[1] = hi & 0xff;
13693                         dev->dev_addr[0] = (hi >> 8) & 0xff;
13694                 }
13695         }
13696
13697         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13698 #ifdef CONFIG_SPARC
13699                 if (!tg3_get_default_macaddr_sparc(tp))
13700                         return 0;
13701 #endif
13702                 return -EINVAL;
13703         }
13704         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13705         return 0;
13706 }
13707
13708 #define BOUNDARY_SINGLE_CACHELINE       1
13709 #define BOUNDARY_MULTI_CACHELINE        2
13710
13711 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13712 {
13713         int cacheline_size;
13714         u8 byte;
13715         int goal;
13716
13717         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13718         if (byte == 0)
13719                 cacheline_size = 1024;
13720         else
13721                 cacheline_size = (int) byte * 4;
13722
13723         /* On 5703 and later chips, the boundary bits have no
13724          * effect.
13725          */
13726         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13727             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13728             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13729                 goto out;
13730
13731 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13732         goal = BOUNDARY_MULTI_CACHELINE;
13733 #else
13734 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13735         goal = BOUNDARY_SINGLE_CACHELINE;
13736 #else
13737         goal = 0;
13738 #endif
13739 #endif
13740
13741         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
13742                 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13743                 goto out;
13744         }
13745
13746         if (!goal)
13747                 goto out;
13748
13749         /* PCI controllers on most RISC systems tend to disconnect
13750          * when a device tries to burst across a cache-line boundary.
13751          * Therefore, letting tg3 do so just wastes PCI bandwidth.
13752          *
13753          * Unfortunately, for PCI-E there are only limited
13754          * write-side controls for this, and thus for reads
13755          * we will still get the disconnects.  We'll also waste
13756          * these PCI cycles for both read and write for chips
13757          * other than 5700 and 5701 which do not implement the
13758          * boundary bits.
13759          */
13760         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13761             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13762                 switch (cacheline_size) {
13763                 case 16:
13764                 case 32:
13765                 case 64:
13766                 case 128:
13767                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13768                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13769                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13770                         } else {
13771                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13772                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13773                         }
13774                         break;
13775
13776                 case 256:
13777                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13778                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13779                         break;
13780
13781                 default:
13782                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13783                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13784                         break;
13785                 }
13786         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13787                 switch (cacheline_size) {
13788                 case 16:
13789                 case 32:
13790                 case 64:
13791                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13792                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13793                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13794                                 break;
13795                         }
13796                         /* fallthrough */
13797                 case 128:
13798                 default:
13799                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13800                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13801                         break;
13802                 }
13803         } else {
13804                 switch (cacheline_size) {
13805                 case 16:
13806                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13807                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13808                                         DMA_RWCTRL_WRITE_BNDRY_16);
13809                                 break;
13810                         }
13811                         /* fallthrough */
13812                 case 32:
13813                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13814                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13815                                         DMA_RWCTRL_WRITE_BNDRY_32);
13816                                 break;
13817                         }
13818                         /* fallthrough */
13819                 case 64:
13820                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13821                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13822                                         DMA_RWCTRL_WRITE_BNDRY_64);
13823                                 break;
13824                         }
13825                         /* fallthrough */
13826                 case 128:
13827                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13828                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13829                                         DMA_RWCTRL_WRITE_BNDRY_128);
13830                                 break;
13831                         }
13832                         /* fallthrough */
13833                 case 256:
13834                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
13835                                 DMA_RWCTRL_WRITE_BNDRY_256);
13836                         break;
13837                 case 512:
13838                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
13839                                 DMA_RWCTRL_WRITE_BNDRY_512);
13840                         break;
13841                 case 1024:
13842                 default:
13843                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13844                                 DMA_RWCTRL_WRITE_BNDRY_1024);
13845                         break;
13846                 }
13847         }
13848
13849 out:
13850         return val;
13851 }
13852
13853 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13854 {
13855         struct tg3_internal_buffer_desc test_desc;
13856         u32 sram_dma_descs;
13857         int i, ret;
13858
13859         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13860
13861         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13862         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13863         tw32(RDMAC_STATUS, 0);
13864         tw32(WDMAC_STATUS, 0);
13865
13866         tw32(BUFMGR_MODE, 0);
13867         tw32(FTQ_RESET, 0);
13868
13869         test_desc.addr_hi = ((u64) buf_dma) >> 32;
13870         test_desc.addr_lo = buf_dma & 0xffffffff;
13871         test_desc.nic_mbuf = 0x00002100;
13872         test_desc.len = size;
13873
13874         /*
13875          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13876          * the *second* time the tg3 driver was getting loaded after an
13877          * initial scan.
13878          *
13879          * Broadcom tells me:
13880          *   ...the DMA engine is connected to the GRC block and a DMA
13881          *   reset may affect the GRC block in some unpredictable way...
13882          *   The behavior of resets to individual blocks has not been tested.
13883          *
13884          * Broadcom noted the GRC reset will also reset all sub-components.
13885          */
13886         if (to_device) {
13887                 test_desc.cqid_sqid = (13 << 8) | 2;
13888
13889                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13890                 udelay(40);
13891         } else {
13892                 test_desc.cqid_sqid = (16 << 8) | 7;
13893
13894                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13895                 udelay(40);
13896         }
13897         test_desc.flags = 0x00000005;
13898
13899         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13900                 u32 val;
13901
13902                 val = *(((u32 *)&test_desc) + i);
13903                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13904                                        sram_dma_descs + (i * sizeof(u32)));
13905                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13906         }
13907         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13908
13909         if (to_device)
13910                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13911         else
13912                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13913
13914         ret = -ENODEV;
13915         for (i = 0; i < 40; i++) {
13916                 u32 val;
13917
13918                 if (to_device)
13919                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13920                 else
13921                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13922                 if ((val & 0xffff) == sram_dma_descs) {
13923                         ret = 0;
13924                         break;
13925                 }
13926
13927                 udelay(100);
13928         }
13929
13930         return ret;
13931 }
13932
13933 #define TEST_BUFFER_SIZE        0x2000
13934
13935 static int __devinit tg3_test_dma(struct tg3 *tp)
13936 {
13937         dma_addr_t buf_dma;
13938         u32 *buf, saved_dma_rwctrl;
13939         int ret = 0;
13940
13941         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13942         if (!buf) {
13943                 ret = -ENOMEM;
13944                 goto out_nofree;
13945         }
13946
13947         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13948                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13949
13950         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13951
13952         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13953                 goto out;
13954
13955         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13956                 /* DMA read watermark not used on PCIE */
13957                 tp->dma_rwctrl |= 0x00180000;
13958         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
13959                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13960                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
13961                         tp->dma_rwctrl |= 0x003f0000;
13962                 else
13963                         tp->dma_rwctrl |= 0x003f000f;
13964         } else {
13965                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13966                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13967                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
13968                         u32 read_water = 0x7;
13969
13970                         /* If the 5704 is behind the EPB bridge, we can
13971                          * do the less restrictive ONE_DMA workaround for
13972                          * better performance.
13973                          */
13974                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13975                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13976                                 tp->dma_rwctrl |= 0x8000;
13977                         else if (ccval == 0x6 || ccval == 0x7)
13978                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13979
13980                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13981                                 read_water = 4;
13982                         /* Set bit 23 to enable PCIX hw bug fix */
13983                         tp->dma_rwctrl |=
13984                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13985                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13986                                 (1 << 23);
13987                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13988                         /* 5780 always in PCIX mode */
13989                         tp->dma_rwctrl |= 0x00144000;
13990                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13991                         /* 5714 always in PCIX mode */
13992                         tp->dma_rwctrl |= 0x00148000;
13993                 } else {
13994                         tp->dma_rwctrl |= 0x001b000f;
13995                 }
13996         }
13997
13998         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13999             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14000                 tp->dma_rwctrl &= 0xfffffff0;
14001
14002         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14003             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
14004                 /* Remove this if it causes problems for some boards. */
14005                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
14006
14007                 /* On 5700/5701 chips, we need to set this bit.
14008                  * Otherwise the chip will issue cacheline transactions
14009                  * to streamable DMA memory with not all the byte
14010                  * enables turned on.  This is an error on several
14011                  * RISC PCI controllers, in particular sparc64.
14012                  *
14013                  * On 5703/5704 chips, this bit has been reassigned
14014                  * a different meaning.  In particular, it is used
14015                  * on those chips to enable a PCI-X workaround.
14016                  */
14017                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
14018         }
14019
14020         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14021
14022 #if 0
14023         /* Unneeded, already done by tg3_get_invariants.  */
14024         tg3_switch_clocks(tp);
14025 #endif
14026
14027         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14028             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14029                 goto out;
14030
14031         /* It is best to perform DMA test with maximum write burst size
14032          * to expose the 5700/5701 write DMA bug.
14033          */
14034         saved_dma_rwctrl = tp->dma_rwctrl;
14035         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14036         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14037
14038         while (1) {
14039                 u32 *p = buf, i;
14040
14041                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14042                         p[i] = i;
14043
14044                 /* Send the buffer to the chip. */
14045                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14046                 if (ret) {
14047                         dev_err(&tp->pdev->dev,
14048                                 "%s: Buffer write failed. err = %d\n",
14049                                 __func__, ret);
14050                         break;
14051                 }
14052
14053 #if 0
14054                 /* validate data reached card RAM correctly. */
14055                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14056                         u32 val;
14057                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
14058                         if (le32_to_cpu(val) != p[i]) {
14059                                 dev_err(&tp->pdev->dev,
14060                                         "%s: Buffer corrupted on device! "
14061                                         "(%d != %d)\n", __func__, val, i);
14062                                 /* ret = -ENODEV here? */
14063                         }
14064                         p[i] = 0;
14065                 }
14066 #endif
14067                 /* Now read it back. */
14068                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14069                 if (ret) {
14070                         dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
14071                                 "err = %d\n", __func__, ret);
14072                         break;
14073                 }
14074
14075                 /* Verify it. */
14076                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14077                         if (p[i] == i)
14078                                 continue;
14079
14080                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14081                             DMA_RWCTRL_WRITE_BNDRY_16) {
14082                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14083                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14084                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14085                                 break;
14086                         } else {
14087                                 dev_err(&tp->pdev->dev,
14088                                         "%s: Buffer corrupted on read back! "
14089                                         "(%d != %d)\n", __func__, p[i], i);
14090                                 ret = -ENODEV;
14091                                 goto out;
14092                         }
14093                 }
14094
14095                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14096                         /* Success. */
14097                         ret = 0;
14098                         break;
14099                 }
14100         }
14101         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14102             DMA_RWCTRL_WRITE_BNDRY_16) {
14103                 static struct pci_device_id dma_wait_state_chipsets[] = {
14104                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14105                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14106                         { },
14107                 };
14108
14109                 /* DMA test passed without adjusting DMA boundary,
14110                  * now look for chipsets that are known to expose the
14111                  * DMA bug without failing the test.
14112                  */
14113                 if (pci_dev_present(dma_wait_state_chipsets)) {
14114                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14115                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14116                 } else {
14117                         /* Safe to use the calculated DMA boundary. */
14118                         tp->dma_rwctrl = saved_dma_rwctrl;
14119                 }
14120
14121                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14122         }
14123
14124 out:
14125         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14126 out_nofree:
14127         return ret;
14128 }
14129
14130 static void __devinit tg3_init_link_config(struct tg3 *tp)
14131 {
14132         tp->link_config.advertising =
14133                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14134                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14135                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14136                  ADVERTISED_Autoneg | ADVERTISED_MII);
14137         tp->link_config.speed = SPEED_INVALID;
14138         tp->link_config.duplex = DUPLEX_INVALID;
14139         tp->link_config.autoneg = AUTONEG_ENABLE;
14140         tp->link_config.active_speed = SPEED_INVALID;
14141         tp->link_config.active_duplex = DUPLEX_INVALID;
14142         tp->link_config.orig_speed = SPEED_INVALID;
14143         tp->link_config.orig_duplex = DUPLEX_INVALID;
14144         tp->link_config.orig_autoneg = AUTONEG_INVALID;
14145 }
14146
14147 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14148 {
14149         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
14150                 tp->bufmgr_config.mbuf_read_dma_low_water =
14151                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14152                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14153                         DEFAULT_MB_MACRX_LOW_WATER_57765;
14154                 tp->bufmgr_config.mbuf_high_water =
14155                         DEFAULT_MB_HIGH_WATER_57765;
14156
14157                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14158                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14159                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14160                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14161                 tp->bufmgr_config.mbuf_high_water_jumbo =
14162                         DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14163         } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14164                 tp->bufmgr_config.mbuf_read_dma_low_water =
14165                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14166                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14167                         DEFAULT_MB_MACRX_LOW_WATER_5705;
14168                 tp->bufmgr_config.mbuf_high_water =
14169                         DEFAULT_MB_HIGH_WATER_5705;
14170                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14171                         tp->bufmgr_config.mbuf_mac_rx_low_water =
14172                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
14173                         tp->bufmgr_config.mbuf_high_water =
14174                                 DEFAULT_MB_HIGH_WATER_5906;
14175                 }
14176
14177                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14178                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14179                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14180                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14181                 tp->bufmgr_config.mbuf_high_water_jumbo =
14182                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14183         } else {
14184                 tp->bufmgr_config.mbuf_read_dma_low_water =
14185                         DEFAULT_MB_RDMA_LOW_WATER;
14186                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14187                         DEFAULT_MB_MACRX_LOW_WATER;
14188                 tp->bufmgr_config.mbuf_high_water =
14189                         DEFAULT_MB_HIGH_WATER;
14190
14191                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14192                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14193                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14194                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14195                 tp->bufmgr_config.mbuf_high_water_jumbo =
14196                         DEFAULT_MB_HIGH_WATER_JUMBO;
14197         }
14198
14199         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14200         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14201 }
14202
14203 static char * __devinit tg3_phy_string(struct tg3 *tp)
14204 {
14205         switch (tp->phy_id & TG3_PHY_ID_MASK) {
14206         case TG3_PHY_ID_BCM5400:        return "5400";
14207         case TG3_PHY_ID_BCM5401:        return "5401";
14208         case TG3_PHY_ID_BCM5411:        return "5411";
14209         case TG3_PHY_ID_BCM5701:        return "5701";
14210         case TG3_PHY_ID_BCM5703:        return "5703";
14211         case TG3_PHY_ID_BCM5704:        return "5704";
14212         case TG3_PHY_ID_BCM5705:        return "5705";
14213         case TG3_PHY_ID_BCM5750:        return "5750";
14214         case TG3_PHY_ID_BCM5752:        return "5752";
14215         case TG3_PHY_ID_BCM5714:        return "5714";
14216         case TG3_PHY_ID_BCM5780:        return "5780";
14217         case TG3_PHY_ID_BCM5755:        return "5755";
14218         case TG3_PHY_ID_BCM5787:        return "5787";
14219         case TG3_PHY_ID_BCM5784:        return "5784";
14220         case TG3_PHY_ID_BCM5756:        return "5722/5756";
14221         case TG3_PHY_ID_BCM5906:        return "5906";
14222         case TG3_PHY_ID_BCM5761:        return "5761";
14223         case TG3_PHY_ID_BCM5718C:       return "5718C";
14224         case TG3_PHY_ID_BCM5718S:       return "5718S";
14225         case TG3_PHY_ID_BCM57765:       return "57765";
14226         case TG3_PHY_ID_BCM5719C:       return "5719C";
14227         case TG3_PHY_ID_BCM8002:        return "8002/serdes";
14228         case 0:                 return "serdes";
14229         default:                return "unknown";
14230         }
14231 }
14232
14233 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14234 {
14235         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14236                 strcpy(str, "PCI Express");
14237                 return str;
14238         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14239                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14240
14241                 strcpy(str, "PCIX:");
14242
14243                 if ((clock_ctrl == 7) ||
14244                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14245                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14246                         strcat(str, "133MHz");
14247                 else if (clock_ctrl == 0)
14248                         strcat(str, "33MHz");
14249                 else if (clock_ctrl == 2)
14250                         strcat(str, "50MHz");
14251                 else if (clock_ctrl == 4)
14252                         strcat(str, "66MHz");
14253                 else if (clock_ctrl == 6)
14254                         strcat(str, "100MHz");
14255         } else {
14256                 strcpy(str, "PCI:");
14257                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14258                         strcat(str, "66MHz");
14259                 else
14260                         strcat(str, "33MHz");
14261         }
14262         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14263                 strcat(str, ":32-bit");
14264         else
14265                 strcat(str, ":64-bit");
14266         return str;
14267 }
14268
14269 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14270 {
14271         struct pci_dev *peer;
14272         unsigned int func, devnr = tp->pdev->devfn & ~7;
14273
14274         for (func = 0; func < 8; func++) {
14275                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14276                 if (peer && peer != tp->pdev)
14277                         break;
14278                 pci_dev_put(peer);
14279         }
14280         /* 5704 can be configured in single-port mode, set peer to
14281          * tp->pdev in that case.
14282          */
14283         if (!peer) {
14284                 peer = tp->pdev;
14285                 return peer;
14286         }
14287
14288         /*
14289          * We don't need to keep the refcount elevated; there's no way
14290          * to remove one half of this device without removing the other
14291          */
14292         pci_dev_put(peer);
14293
14294         return peer;
14295 }
14296
14297 static void __devinit tg3_init_coal(struct tg3 *tp)
14298 {
14299         struct ethtool_coalesce *ec = &tp->coal;
14300
14301         memset(ec, 0, sizeof(*ec));
14302         ec->cmd = ETHTOOL_GCOALESCE;
14303         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14304         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14305         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14306         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14307         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14308         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14309         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14310         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14311         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14312
14313         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14314                                  HOSTCC_MODE_CLRTICK_TXBD)) {
14315                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14316                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14317                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14318                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14319         }
14320
14321         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14322                 ec->rx_coalesce_usecs_irq = 0;
14323                 ec->tx_coalesce_usecs_irq = 0;
14324                 ec->stats_block_coalesce_usecs = 0;
14325         }
14326 }
14327
14328 static const struct net_device_ops tg3_netdev_ops = {
14329         .ndo_open               = tg3_open,
14330         .ndo_stop               = tg3_close,
14331         .ndo_start_xmit         = tg3_start_xmit,
14332         .ndo_get_stats64        = tg3_get_stats64,
14333         .ndo_validate_addr      = eth_validate_addr,
14334         .ndo_set_multicast_list = tg3_set_rx_mode,
14335         .ndo_set_mac_address    = tg3_set_mac_addr,
14336         .ndo_do_ioctl           = tg3_ioctl,
14337         .ndo_tx_timeout         = tg3_tx_timeout,
14338         .ndo_change_mtu         = tg3_change_mtu,
14339 #if TG3_VLAN_TAG_USED
14340         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14341 #endif
14342 #ifdef CONFIG_NET_POLL_CONTROLLER
14343         .ndo_poll_controller    = tg3_poll_controller,
14344 #endif
14345 };
14346
14347 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14348         .ndo_open               = tg3_open,
14349         .ndo_stop               = tg3_close,
14350         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
14351         .ndo_get_stats64        = tg3_get_stats64,
14352         .ndo_validate_addr      = eth_validate_addr,
14353         .ndo_set_multicast_list = tg3_set_rx_mode,
14354         .ndo_set_mac_address    = tg3_set_mac_addr,
14355         .ndo_do_ioctl           = tg3_ioctl,
14356         .ndo_tx_timeout         = tg3_tx_timeout,
14357         .ndo_change_mtu         = tg3_change_mtu,
14358 #if TG3_VLAN_TAG_USED
14359         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14360 #endif
14361 #ifdef CONFIG_NET_POLL_CONTROLLER
14362         .ndo_poll_controller    = tg3_poll_controller,
14363 #endif
14364 };
14365
14366 static int __devinit tg3_init_one(struct pci_dev *pdev,
14367                                   const struct pci_device_id *ent)
14368 {
14369         struct net_device *dev;
14370         struct tg3 *tp;
14371         int i, err, pm_cap;
14372         u32 sndmbx, rcvmbx, intmbx;
14373         char str[40];
14374         u64 dma_mask, persist_dma_mask;
14375
14376         printk_once(KERN_INFO "%s\n", version);
14377
14378         err = pci_enable_device(pdev);
14379         if (err) {
14380                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
14381                 return err;
14382         }
14383
14384         err = pci_request_regions(pdev, DRV_MODULE_NAME);
14385         if (err) {
14386                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
14387                 goto err_out_disable_pdev;
14388         }
14389
14390         pci_set_master(pdev);
14391
14392         /* Find power-management capability. */
14393         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14394         if (pm_cap == 0) {
14395                 dev_err(&pdev->dev,
14396                         "Cannot find Power Management capability, aborting\n");
14397                 err = -EIO;
14398                 goto err_out_free_res;
14399         }
14400
14401         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14402         if (!dev) {
14403                 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
14404                 err = -ENOMEM;
14405                 goto err_out_free_res;
14406         }
14407
14408         SET_NETDEV_DEV(dev, &pdev->dev);
14409
14410 #if TG3_VLAN_TAG_USED
14411         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14412 #endif
14413
14414         tp = netdev_priv(dev);
14415         tp->pdev = pdev;
14416         tp->dev = dev;
14417         tp->pm_cap = pm_cap;
14418         tp->rx_mode = TG3_DEF_RX_MODE;
14419         tp->tx_mode = TG3_DEF_TX_MODE;
14420
14421         if (tg3_debug > 0)
14422                 tp->msg_enable = tg3_debug;
14423         else
14424                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14425
14426         /* The word/byte swap controls here control register access byte
14427          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
14428          * setting below.
14429          */
14430         tp->misc_host_ctrl =
14431                 MISC_HOST_CTRL_MASK_PCI_INT |
14432                 MISC_HOST_CTRL_WORD_SWAP |
14433                 MISC_HOST_CTRL_INDIR_ACCESS |
14434                 MISC_HOST_CTRL_PCISTATE_RW;
14435
14436         /* The NONFRM (non-frame) byte/word swap controls take effect
14437          * on descriptor entries, anything which isn't packet data.
14438          *
14439          * The StrongARM chips on the board (one for tx, one for rx)
14440          * are running in big-endian mode.
14441          */
14442         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14443                         GRC_MODE_WSWAP_NONFRM_DATA);
14444 #ifdef __BIG_ENDIAN
14445         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14446 #endif
14447         spin_lock_init(&tp->lock);
14448         spin_lock_init(&tp->indirect_lock);
14449         INIT_WORK(&tp->reset_task, tg3_reset_task);
14450
14451         tp->regs = pci_ioremap_bar(pdev, BAR_0);
14452         if (!tp->regs) {
14453                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
14454                 err = -ENOMEM;
14455                 goto err_out_free_dev;
14456         }
14457
14458         tg3_init_link_config(tp);
14459
14460         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14461         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14462
14463         dev->ethtool_ops = &tg3_ethtool_ops;
14464         dev->watchdog_timeo = TG3_TX_TIMEOUT;
14465         dev->irq = pdev->irq;
14466
14467         err = tg3_get_invariants(tp);
14468         if (err) {
14469                 dev_err(&pdev->dev,
14470                         "Problem fetching invariants of chip, aborting\n");
14471                 goto err_out_iounmap;
14472         }
14473
14474         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14475             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
14476             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
14477                 dev->netdev_ops = &tg3_netdev_ops;
14478         else
14479                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14480
14481
14482         /* The EPB bridge inside 5714, 5715, and 5780 and any
14483          * device behind the EPB cannot support DMA addresses > 40-bit.
14484          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14485          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14486          * do DMA address check in tg3_start_xmit().
14487          */
14488         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14489                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14490         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14491                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14492 #ifdef CONFIG_HIGHMEM
14493                 dma_mask = DMA_BIT_MASK(64);
14494 #endif
14495         } else
14496                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14497
14498         /* Configure DMA attributes. */
14499         if (dma_mask > DMA_BIT_MASK(32)) {
14500                 err = pci_set_dma_mask(pdev, dma_mask);
14501                 if (!err) {
14502                         dev->features |= NETIF_F_HIGHDMA;
14503                         err = pci_set_consistent_dma_mask(pdev,
14504                                                           persist_dma_mask);
14505                         if (err < 0) {
14506                                 dev_err(&pdev->dev, "Unable to obtain 64 bit "
14507                                         "DMA for consistent allocations\n");
14508                                 goto err_out_iounmap;
14509                         }
14510                 }
14511         }
14512         if (err || dma_mask == DMA_BIT_MASK(32)) {
14513                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14514                 if (err) {
14515                         dev_err(&pdev->dev,
14516                                 "No usable DMA configuration, aborting\n");
14517                         goto err_out_iounmap;
14518                 }
14519         }
14520
14521         tg3_init_bufmgr_config(tp);
14522
14523         /* Selectively allow TSO based on operating conditions */
14524         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14525             (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14526                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14527         else {
14528                 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14529                 tp->fw_needed = NULL;
14530         }
14531
14532         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14533                 tp->fw_needed = FIRMWARE_TG3;
14534
14535         /* TSO is on by default on chips that support hardware TSO.
14536          * Firmware TSO on older chips gives lower performance, so it
14537          * is off by default, but can be enabled using ethtool.
14538          */
14539         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14540             (dev->features & NETIF_F_IP_CSUM)) {
14541                 dev->features |= NETIF_F_TSO;
14542                 vlan_features_add(dev, NETIF_F_TSO);
14543         }
14544         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14545             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14546                 if (dev->features & NETIF_F_IPV6_CSUM) {
14547                         dev->features |= NETIF_F_TSO6;
14548                         vlan_features_add(dev, NETIF_F_TSO6);
14549                 }
14550                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14551                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14552                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14553                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14554                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14555                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
14556                         dev->features |= NETIF_F_TSO_ECN;
14557                         vlan_features_add(dev, NETIF_F_TSO_ECN);
14558                 }
14559         }
14560
14561         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14562             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14563             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14564                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14565                 tp->rx_pending = 63;
14566         }
14567
14568         err = tg3_get_device_address(tp);
14569         if (err) {
14570                 dev_err(&pdev->dev,
14571                         "Could not obtain valid ethernet address, aborting\n");
14572                 goto err_out_iounmap;
14573         }
14574
14575         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14576                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14577                 if (!tp->aperegs) {
14578                         dev_err(&pdev->dev,
14579                                 "Cannot map APE registers, aborting\n");
14580                         err = -ENOMEM;
14581                         goto err_out_iounmap;
14582                 }
14583
14584                 tg3_ape_lock_init(tp);
14585
14586                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14587                         tg3_read_dash_ver(tp);
14588         }
14589
14590         /*
14591          * Reset chip in case UNDI or EFI driver did not shutdown
14592          * DMA self test will enable WDMAC and we'll see (spurious)
14593          * pending DMA on the PCI bus at that point.
14594          */
14595         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14596             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14597                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14598                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14599         }
14600
14601         err = tg3_test_dma(tp);
14602         if (err) {
14603                 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
14604                 goto err_out_apeunmap;
14605         }
14606
14607         /* flow control autonegotiation is default behavior */
14608         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14609         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14610
14611         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14612         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14613         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14614         for (i = 0; i < tp->irq_max; i++) {
14615                 struct tg3_napi *tnapi = &tp->napi[i];
14616
14617                 tnapi->tp = tp;
14618                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14619
14620                 tnapi->int_mbox = intmbx;
14621                 if (i < 4)
14622                         intmbx += 0x8;
14623                 else
14624                         intmbx += 0x4;
14625
14626                 tnapi->consmbox = rcvmbx;
14627                 tnapi->prodmbox = sndmbx;
14628
14629                 if (i)
14630                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14631                 else
14632                         tnapi->coal_now = HOSTCC_MODE_NOW;
14633
14634                 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14635                         break;
14636
14637                 /*
14638                  * If we support MSIX, we'll be using RSS.  If we're using
14639                  * RSS, the first vector only handles link interrupts and the
14640                  * remaining vectors handle rx and tx interrupts.  Reuse the
14641                  * mailbox values for the next iteration.  The values we setup
14642                  * above are still useful for the single vectored mode.
14643                  */
14644                 if (!i)
14645                         continue;
14646
14647                 rcvmbx += 0x8;
14648
14649                 if (sndmbx & 0x4)
14650                         sndmbx -= 0x4;
14651                 else
14652                         sndmbx += 0xc;
14653         }
14654
14655         tg3_init_coal(tp);
14656
14657         pci_set_drvdata(pdev, dev);
14658
14659         err = register_netdev(dev);
14660         if (err) {
14661                 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
14662                 goto err_out_apeunmap;
14663         }
14664
14665         netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14666                     tp->board_part_number,
14667                     tp->pci_chip_rev_id,
14668                     tg3_bus_string(tp, str),
14669                     dev->dev_addr);
14670
14671         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
14672                 struct phy_device *phydev;
14673                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14674                 netdev_info(dev,
14675                             "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14676                             phydev->drv->name, dev_name(&phydev->dev));
14677         } else {
14678                 char *ethtype;
14679
14680                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
14681                         ethtype = "10/100Base-TX";
14682                 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
14683                         ethtype = "1000Base-SX";
14684                 else
14685                         ethtype = "10/100/1000Base-T";
14686
14687                 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
14688                             "(WireSpeed[%d])\n", tg3_phy_string(tp), ethtype,
14689                           (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0);
14690         }
14691
14692         netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14693                     (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14694                     (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14695                     (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
14696                     (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14697                     (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14698         netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14699                     tp->dma_rwctrl,
14700                     pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
14701                     ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
14702
14703         return 0;
14704
14705 err_out_apeunmap:
14706         if (tp->aperegs) {
14707                 iounmap(tp->aperegs);
14708                 tp->aperegs = NULL;
14709         }
14710
14711 err_out_iounmap:
14712         if (tp->regs) {
14713                 iounmap(tp->regs);
14714                 tp->regs = NULL;
14715         }
14716
14717 err_out_free_dev:
14718         free_netdev(dev);
14719
14720 err_out_free_res:
14721         pci_release_regions(pdev);
14722
14723 err_out_disable_pdev:
14724         pci_disable_device(pdev);
14725         pci_set_drvdata(pdev, NULL);
14726         return err;
14727 }
14728
14729 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14730 {
14731         struct net_device *dev = pci_get_drvdata(pdev);
14732
14733         if (dev) {
14734                 struct tg3 *tp = netdev_priv(dev);
14735
14736                 if (tp->fw)
14737                         release_firmware(tp->fw);
14738
14739                 flush_scheduled_work();
14740
14741                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14742                         tg3_phy_fini(tp);
14743                         tg3_mdio_fini(tp);
14744                 }
14745
14746                 unregister_netdev(dev);
14747                 if (tp->aperegs) {
14748                         iounmap(tp->aperegs);
14749                         tp->aperegs = NULL;
14750                 }
14751                 if (tp->regs) {
14752                         iounmap(tp->regs);
14753                         tp->regs = NULL;
14754                 }
14755                 free_netdev(dev);
14756                 pci_release_regions(pdev);
14757                 pci_disable_device(pdev);
14758                 pci_set_drvdata(pdev, NULL);
14759         }
14760 }
14761
14762 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14763 {
14764         struct net_device *dev = pci_get_drvdata(pdev);
14765         struct tg3 *tp = netdev_priv(dev);
14766         pci_power_t target_state;
14767         int err;
14768
14769         /* PCI register 4 needs to be saved whether netif_running() or not.
14770          * MSI address and data need to be saved if using MSI and
14771          * netif_running().
14772          */
14773         pci_save_state(pdev);
14774
14775         if (!netif_running(dev))
14776                 return 0;
14777
14778         flush_scheduled_work();
14779         tg3_phy_stop(tp);
14780         tg3_netif_stop(tp);
14781
14782         del_timer_sync(&tp->timer);
14783
14784         tg3_full_lock(tp, 1);
14785         tg3_disable_ints(tp);
14786         tg3_full_unlock(tp);
14787
14788         netif_device_detach(dev);
14789
14790         tg3_full_lock(tp, 0);
14791         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14792         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14793         tg3_full_unlock(tp);
14794
14795         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14796
14797         err = tg3_set_power_state(tp, target_state);
14798         if (err) {
14799                 int err2;
14800
14801                 tg3_full_lock(tp, 0);
14802
14803                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14804                 err2 = tg3_restart_hw(tp, 1);
14805                 if (err2)
14806                         goto out;
14807
14808                 tp->timer.expires = jiffies + tp->timer_offset;
14809                 add_timer(&tp->timer);
14810
14811                 netif_device_attach(dev);
14812                 tg3_netif_start(tp);
14813
14814 out:
14815                 tg3_full_unlock(tp);
14816
14817                 if (!err2)
14818                         tg3_phy_start(tp);
14819         }
14820
14821         return err;
14822 }
14823
14824 static int tg3_resume(struct pci_dev *pdev)
14825 {
14826         struct net_device *dev = pci_get_drvdata(pdev);
14827         struct tg3 *tp = netdev_priv(dev);
14828         int err;
14829
14830         pci_restore_state(tp->pdev);
14831
14832         if (!netif_running(dev))
14833                 return 0;
14834
14835         err = tg3_set_power_state(tp, PCI_D0);
14836         if (err)
14837                 return err;
14838
14839         netif_device_attach(dev);
14840
14841         tg3_full_lock(tp, 0);
14842
14843         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14844         err = tg3_restart_hw(tp, 1);
14845         if (err)
14846                 goto out;
14847
14848         tp->timer.expires = jiffies + tp->timer_offset;
14849         add_timer(&tp->timer);
14850
14851         tg3_netif_start(tp);
14852
14853 out:
14854         tg3_full_unlock(tp);
14855
14856         if (!err)
14857                 tg3_phy_start(tp);
14858
14859         return err;
14860 }
14861
14862 static struct pci_driver tg3_driver = {
14863         .name           = DRV_MODULE_NAME,
14864         .id_table       = tg3_pci_tbl,
14865         .probe          = tg3_init_one,
14866         .remove         = __devexit_p(tg3_remove_one),
14867         .suspend        = tg3_suspend,
14868         .resume         = tg3_resume
14869 };
14870
14871 static int __init tg3_init(void)
14872 {
14873         return pci_register_driver(&tg3_driver);
14874 }
14875
14876 static void __exit tg3_cleanup(void)
14877 {
14878         pci_unregister_driver(&tg3_driver);
14879 }
14880
14881 module_init(tg3_init);
14882 module_exit(tg3_cleanup);