drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2010 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/phy.h>
  36 #include <linux/brcmphy.h>
  37 #include <linux/if_vlan.h>
  38 #include <linux/ip.h>
  39 #include <linux/tcp.h>
  40 #include <linux/workqueue.h>
  41 #include <linux/prefetch.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/firmware.h>
  44
  45 #include <net/checksum.h>
  46 #include <net/ip.h>
  47
  48 #include <asm/system.h>
  49 #include <asm/io.h>
  50 #include <asm/byteorder.h>
  51 #include <asm/uaccess.h>
  52
  53 #ifdef CONFIG_SPARC
  54 #include <asm/idprom.h>
  55 #include <asm/prom.h>
  56 #endif
  57
  58 #define BAR_0   0
  59 #define BAR_2   2
  60
  61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  62 #define TG3_VLAN_TAG_USED 1
  63 #else
  64 #define TG3_VLAN_TAG_USED 0
  65 #endif
  66
  67 #include "tg3.h"
  68
  69 #define DRV_MODULE_NAME         "tg3"
  70 #define DRV_MODULE_VERSION      "3.111"
  71 #define DRV_MODULE_RELDATE      "June 5, 2010"
  72
  73 #define TG3_DEF_MAC_MODE        0
  74 #define TG3_DEF_RX_MODE         0
  75 #define TG3_DEF_TX_MODE         0
  76 #define TG3_DEF_MSG_ENABLE        \
  77         (NETIF_MSG_DRV          | \
  78          NETIF_MSG_PROBE        | \
  79          NETIF_MSG_LINK         | \
  80          NETIF_MSG_TIMER        | \
  81          NETIF_MSG_IFDOWN       | \
  82          NETIF_MSG_IFUP         | \
  83          NETIF_MSG_RX_ERR       | \
  84          NETIF_MSG_TX_ERR)
  85
  86 /* length of time before we decide the hardware is borked,
  87  * and dev->tx_timeout() should be called to fix the problem
  88  */
  89 #define TG3_TX_TIMEOUT                  (5 * HZ)
  90
  91 /* hardware minimum and maximum for a single frame's data payload */
  92 #define TG3_MIN_MTU                     60
  93 #define TG3_MAX_MTU(tp) \
  94         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  95
  96 /* These numbers seem to be hard coded in the NIC firmware somehow.
  97  * You can't change the ring sizes, but you can change where you place
  98  * them in the NIC onboard memory.
  99  */
 100 #define TG3_RX_RING_SIZE                512
 101 #define TG3_DEF_RX_RING_PENDING         200
 102 #define TG3_RX_JUMBO_RING_SIZE          256
 103 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 104 #define TG3_RSS_INDIR_TBL_SIZE          128
 105
 106 /* Do not place this n-ring entries value into the tp struct itself,
 107  * we really want to expose these constants to GCC so that modulo et
 108  * al.  operations are done with shifts and masks instead of with
 109  * hw multiply/modulo instructions.  Another solution would be to
 110  * replace things like '% foo' with '& (foo - 1)'.
 111  */
 112 #define TG3_RX_RCB_RING_SIZE(tp)        \
 113         (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
 114           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
 115
 116 #define TG3_TX_RING_SIZE                512
 117 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 118
 119 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 120                                  TG3_RX_RING_SIZE)
 121 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
 122                                  TG3_RX_JUMBO_RING_SIZE)
 123 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 124                                  TG3_RX_RCB_RING_SIZE(tp))
 125 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 126                                  TG3_TX_RING_SIZE)
 127 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 128
 129 #define TG3_RX_DMA_ALIGN                16
 130 #define TG3_RX_HEADROOM                 ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
 131
 132 #define TG3_DMA_BYTE_ENAB               64
 133
 134 #define TG3_RX_STD_DMA_SZ               1536
 135 #define TG3_RX_JMB_DMA_SZ               9046
 136
 137 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 138
 139 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 140 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 141
 142 #define TG3_RX_STD_BUFF_RING_SIZE \
 143         (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
 144
 145 #define TG3_RX_JMB_BUFF_RING_SIZE \
 146         (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
 147
 148 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
 149  * that are at least dword aligned when used in PCIX mode.  The driver
 150  * works around this bug by double copying the packet.  This workaround
 151  * is built into the normal double copy length check for efficiency.
 152  *
 153  * However, the double copy is only necessary on those architectures
 154  * where unaligned memory accesses are inefficient.  For those architectures
 155  * where unaligned memory accesses incur little penalty, we can reintegrate
 156  * the 5701 in the normal rx path.  Doing so saves a device structure
 157  * dereference by hardcoding the double copy threshold in place.
 158  */
 159 #define TG3_RX_COPY_THRESHOLD           256
 160 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
 161         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
 162 #else
 163         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
 164 #endif
 165
 166 /* minimum number of free TX descriptors required to wake up TX process */
 167 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 168
 169 #define TG3_RAW_IP_ALIGN 2
 170
 171 /* number of ETHTOOL_GSTATS u64's */
 172 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 173
 174 #define TG3_NUM_TEST            6
 175
 176 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
 177
 178 #define FIRMWARE_TG3            "tigon/tg3.bin"
 179 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 180 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 181
 182 static char version[] __devinitdata =
 183         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
 184
 185 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 186 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 187 MODULE_LICENSE("GPL");
 188 MODULE_VERSION(DRV_MODULE_VERSION);
 189 MODULE_FIRMWARE(FIRMWARE_TG3);
 190 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 191 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 192
 193 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 194 module_param(tg3_debug, int, 0);
 195 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 196
 197 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 255         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 256         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 257         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 258         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 259         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 260         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 261         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 262         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 263         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 264         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
 265         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
 266         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
 267         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
 268         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
 269         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
 270         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
 271         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
 272         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
 273         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
 274         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 275         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 276         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 277         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 278         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 279         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 280         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 281         {}
 282 };
 283
 284 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 285
 286 static const struct {
 287         const char string[ETH_GSTRING_LEN];
 288 } ethtool_stats_keys[TG3_NUM_STATS] = {
 289         { "rx_octets" },
 290         { "rx_fragments" },
 291         { "rx_ucast_packets" },
 292         { "rx_mcast_packets" },
 293         { "rx_bcast_packets" },
 294         { "rx_fcs_errors" },
 295         { "rx_align_errors" },
 296         { "rx_xon_pause_rcvd" },
 297         { "rx_xoff_pause_rcvd" },
 298         { "rx_mac_ctrl_rcvd" },
 299         { "rx_xoff_entered" },
 300         { "rx_frame_too_long_errors" },
 301         { "rx_jabbers" },
 302         { "rx_undersize_packets" },
 303         { "rx_in_length_errors" },
 304         { "rx_out_length_errors" },
 305         { "rx_64_or_less_octet_packets" },
 306         { "rx_65_to_127_octet_packets" },
 307         { "rx_128_to_255_octet_packets" },
 308         { "rx_256_to_511_octet_packets" },
 309         { "rx_512_to_1023_octet_packets" },
 310         { "rx_1024_to_1522_octet_packets" },
 311         { "rx_1523_to_2047_octet_packets" },
 312         { "rx_2048_to_4095_octet_packets" },
 313         { "rx_4096_to_8191_octet_packets" },
 314         { "rx_8192_to_9022_octet_packets" },
 315
 316         { "tx_octets" },
 317         { "tx_collisions" },
 318
 319         { "tx_xon_sent" },
 320         { "tx_xoff_sent" },
 321         { "tx_flow_control" },
 322         { "tx_mac_errors" },
 323         { "tx_single_collisions" },
 324         { "tx_mult_collisions" },
 325         { "tx_deferred" },
 326         { "tx_excessive_collisions" },
 327         { "tx_late_collisions" },
 328         { "tx_collide_2times" },
 329         { "tx_collide_3times" },
 330         { "tx_collide_4times" },
 331         { "tx_collide_5times" },
 332         { "tx_collide_6times" },
 333         { "tx_collide_7times" },
 334         { "tx_collide_8times" },
 335         { "tx_collide_9times" },
 336         { "tx_collide_10times" },
 337         { "tx_collide_11times" },
 338         { "tx_collide_12times" },
 339         { "tx_collide_13times" },
 340         { "tx_collide_14times" },
 341         { "tx_collide_15times" },
 342         { "tx_ucast_packets" },
 343         { "tx_mcast_packets" },
 344         { "tx_bcast_packets" },
 345         { "tx_carrier_sense_errors" },
 346         { "tx_discards" },
 347         { "tx_errors" },
 348
 349         { "dma_writeq_full" },
 350         { "dma_write_prioq_full" },
 351         { "rxbds_empty" },
 352         { "rx_discards" },
 353         { "rx_errors" },
 354         { "rx_threshold_hit" },
 355
 356         { "dma_readq_full" },
 357         { "dma_read_prioq_full" },
 358         { "tx_comp_queue_full" },
 359
 360         { "ring_set_send_prod_index" },
 361         { "ring_status_update" },
 362         { "nic_irqs" },
 363         { "nic_avoided_irqs" },
 364         { "nic_tx_threshold_hit" }
 365 };
 366
 367 static const struct {
 368         const char string[ETH_GSTRING_LEN];
 369 } ethtool_test_keys[TG3_NUM_TEST] = {
 370         { "nvram test     (online) " },
 371         { "link test      (online) " },
 372         { "register test  (offline)" },
 373         { "memory test    (offline)" },
 374         { "loopback test  (offline)" },
 375         { "interrupt test (offline)" },
 376 };
 377
 378 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 379 {
 380         writel(val, tp->regs + off);
 381 }
 382
 383 static u32 tg3_read32(struct tg3 *tp, u32 off)
 384 {
 385         return readl(tp->regs + off);
 386 }
 387
 388 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 389 {
 390         writel(val, tp->aperegs + off);
 391 }
 392
 393 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 394 {
 395         return readl(tp->aperegs + off);
 396 }
 397
 398 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 399 {
 400         unsigned long flags;
 401
 402         spin_lock_irqsave(&tp->indirect_lock, flags);
 403         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 404         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 405         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 406 }
 407
 408 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 409 {
 410         writel(val, tp->regs + off);
 411         readl(tp->regs + off);
 412 }
 413
 414 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 415 {
 416         unsigned long flags;
 417         u32 val;
 418
 419         spin_lock_irqsave(&tp->indirect_lock, flags);
 420         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 421         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 422         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 423         return val;
 424 }
 425
 426 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 427 {
 428         unsigned long flags;
 429
 430         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 431                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 432                                        TG3_64BIT_REG_LOW, val);
 433                 return;
 434         }
 435         if (off == TG3_RX_STD_PROD_IDX_REG) {
 436                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 437                                        TG3_64BIT_REG_LOW, val);
 438                 return;
 439         }
 440
 441         spin_lock_irqsave(&tp->indirect_lock, flags);
 442         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 443         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 444         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 445
 446         /* In indirect mode when disabling interrupts, we also need
 447          * to clear the interrupt bit in the GRC local ctrl register.
 448          */
 449         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 450             (val == 0x1)) {
 451                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 452                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 453         }
 454 }
 455
 456 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 457 {
 458         unsigned long flags;
 459         u32 val;
 460
 461         spin_lock_irqsave(&tp->indirect_lock, flags);
 462         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 463         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 464         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 465         return val;
 466 }
 467
 468 /* usec_wait specifies the wait time in usec when writing to certain registers
 469  * where it is unsafe to read back the register without some delay.
 470  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 471  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 472  */
 473 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 474 {
 475         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 476             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 477                 /* Non-posted methods */
 478                 tp->write32(tp, off, val);
 479         else {
 480                 /* Posted method */
 481                 tg3_write32(tp, off, val);
 482                 if (usec_wait)
 483                         udelay(usec_wait);
 484                 tp->read32(tp, off);
 485         }
 486         /* Wait again after the read for the posted method to guarantee that
 487          * the wait time is met.
 488          */
 489         if (usec_wait)
 490                 udelay(usec_wait);
 491 }
 492
 493 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 494 {
 495         tp->write32_mbox(tp, off, val);
 496         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 497             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 498                 tp->read32_mbox(tp, off);
 499 }
 500
 501 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 502 {
 503         void __iomem *mbox = tp->regs + off;
 504         writel(val, mbox);
 505         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 506                 writel(val, mbox);
 507         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 508                 readl(mbox);
 509 }
 510
 511 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 512 {
 513         return readl(tp->regs + off + GRCMBOX_BASE);
 514 }
 515
 516 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 517 {
 518         writel(val, tp->regs + off + GRCMBOX_BASE);
 519 }
 520
 521 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
 522 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 523 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
 524 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
 525 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
 526
 527 #define tw32(reg, val)                  tp->write32(tp, reg, val)
 528 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
 529 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
 530 #define tr32(reg)                       tp->read32(tp, reg)
 531
 532 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 533 {
 534         unsigned long flags;
 535
 536         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 537             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 538                 return;
 539
 540         spin_lock_irqsave(&tp->indirect_lock, flags);
 541         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 542                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 543                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 544
 545                 /* Always leave this as zero. */
 546                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 547         } else {
 548                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 549                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 550
 551                 /* Always leave this as zero. */
 552                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 553         }
 554         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 555 }
 556
 557 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 558 {
 559         unsigned long flags;
 560
 561         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 562             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 563                 *val = 0;
 564                 return;
 565         }
 566
 567         spin_lock_irqsave(&tp->indirect_lock, flags);
 568         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 569                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 570                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 571
 572                 /* Always leave this as zero. */
 573                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 574         } else {
 575                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 576                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 577
 578                 /* Always leave this as zero. */
 579                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 580         }
 581         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 582 }
 583
 584 static void tg3_ape_lock_init(struct tg3 *tp)
 585 {
 586         int i;
 587         u32 regbase;
 588
 589         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 590                 regbase = TG3_APE_LOCK_GRANT;
 591         else
 592                 regbase = TG3_APE_PER_LOCK_GRANT;
 593
 594         /* Make sure the driver hasn't any stale locks. */
 595         for (i = 0; i < 8; i++)
 596                 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
 597 }
 598
 599 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 600 {
 601         int i, off;
 602         int ret = 0;
 603         u32 status, req, gnt;
 604
 605         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 606                 return 0;
 607
 608         switch (locknum) {
 609         case TG3_APE_LOCK_GRC:
 610         case TG3_APE_LOCK_MEM:
 611                 break;
 612         default:
 613                 return -EINVAL;
 614         }
 615
 616         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
 617                 req = TG3_APE_LOCK_REQ;
 618                 gnt = TG3_APE_LOCK_GRANT;
 619         } else {
 620                 req = TG3_APE_PER_LOCK_REQ;
 621                 gnt = TG3_APE_PER_LOCK_GRANT;
 622         }
 623
 624         off = 4 * locknum;
 625
 626         tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
 627
 628         /* Wait for up to 1 millisecond to acquire lock. */
 629         for (i = 0; i < 100; i++) {
 630                 status = tg3_ape_read32(tp, gnt + off);
 631                 if (status == APE_LOCK_GRANT_DRIVER)
 632                         break;
 633                 udelay(10);
 634         }
 635
 636         if (status != APE_LOCK_GRANT_DRIVER) {
 637                 /* Revoke the lock request. */
 638                 tg3_ape_write32(tp, gnt + off,
 639                                 APE_LOCK_GRANT_DRIVER);
 640
 641                 ret = -EBUSY;
 642         }
 643
 644         return ret;
 645 }
 646
 647 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 648 {
 649         u32 gnt;
 650
 651         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 652                 return;
 653
 654         switch (locknum) {
 655         case TG3_APE_LOCK_GRC:
 656         case TG3_APE_LOCK_MEM:
 657                 break;
 658         default:
 659                 return;
 660         }
 661
 662         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 663                 gnt = TG3_APE_LOCK_GRANT;
 664         else
 665                 gnt = TG3_APE_PER_LOCK_GRANT;
 666
 667         tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
 668 }
 669
 670 static void tg3_disable_ints(struct tg3 *tp)
 671 {
 672         int i;
 673
 674         tw32(TG3PCI_MISC_HOST_CTRL,
 675              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 676         for (i = 0; i < tp->irq_max; i++)
 677                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 678 }
 679
 680 static void tg3_enable_ints(struct tg3 *tp)
 681 {
 682         int i;
 683
 684         tp->irq_sync = 0;
 685         wmb();
 686
 687         tw32(TG3PCI_MISC_HOST_CTRL,
 688              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 689
 690         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
 691         for (i = 0; i < tp->irq_cnt; i++) {
 692                 struct tg3_napi *tnapi = &tp->napi[i];
 693
 694                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 695                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 696                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 697
 698                 tp->coal_now |= tnapi->coal_now;
 699         }
 700
 701         /* Force an initial interrupt */
 702         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 703             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 704                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 705         else
 706                 tw32(HOSTCC_MODE, tp->coal_now);
 707
 708         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
 709 }
 710
 711 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 712 {
 713         struct tg3 *tp = tnapi->tp;
 714         struct tg3_hw_status *sblk = tnapi->hw_status;
 715         unsigned int work_exists = 0;
 716
 717         /* check for phy events */
 718         if (!(tp->tg3_flags &
 719               (TG3_FLAG_USE_LINKCHG_REG |
 720                TG3_FLAG_POLL_SERDES))) {
 721                 if (sblk->status & SD_STATUS_LINK_CHG)
 722                         work_exists = 1;
 723         }
 724         /* check for RX/TX work to do */
 725         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 726             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
 727                 work_exists = 1;
 728
 729         return work_exists;
 730 }
 731
 732 /* tg3_int_reenable
 733  *  similar to tg3_enable_ints, but it accurately determines whether there
 734  *  is new work pending and can return without flushing the PIO write
 735  *  which reenables interrupts
 736  */
 737 static void tg3_int_reenable(struct tg3_napi *tnapi)
 738 {
 739         struct tg3 *tp = tnapi->tp;
 740
 741         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 742         mmiowb();
 743
 744         /* When doing tagged status, this work check is unnecessary.
 745          * The last_tag we write above tells the chip which piece of
 746          * work we've completed.
 747          */
 748         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 749             tg3_has_work(tnapi))
 750                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 751                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 752 }
 753
 754 static void tg3_napi_disable(struct tg3 *tp)
 755 {
 756         int i;
 757
 758         for (i = tp->irq_cnt - 1; i >= 0; i--)
 759                 napi_disable(&tp->napi[i].napi);
 760 }
 761
 762 static void tg3_napi_enable(struct tg3 *tp)
 763 {
 764         int i;
 765
 766         for (i = 0; i < tp->irq_cnt; i++)
 767                 napi_enable(&tp->napi[i].napi);
 768 }
 769
 770 static inline void tg3_netif_stop(struct tg3 *tp)
 771 {
 772         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 773         tg3_napi_disable(tp);
 774         netif_tx_disable(tp->dev);
 775 }
 776
 777 static inline void tg3_netif_start(struct tg3 *tp)
 778 {
 779         /* NOTE: unconditional netif_tx_wake_all_queues is only
 780          * appropriate so long as all callers are assured to
 781          * have free tx slots (such as after tg3_init_hw)
 782          */
 783         netif_tx_wake_all_queues(tp->dev);
 784
 785         tg3_napi_enable(tp);
 786         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
 787         tg3_enable_ints(tp);
 788 }
 789
 790 static void tg3_switch_clocks(struct tg3 *tp)
 791 {
 792         u32 clock_ctrl;
 793         u32 orig_clock_ctrl;
 794
 795         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 796             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 797                 return;
 798
 799         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 800
 801         orig_clock_ctrl = clock_ctrl;
 802         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 803                        CLOCK_CTRL_CLKRUN_OENABLE |
 804                        0x1f);
 805         tp->pci_clock_ctrl = clock_ctrl;
 806
 807         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 808                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 809                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 810                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 811                 }
 812         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 813                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 814                             clock_ctrl |
 815                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 816                             40);
 817                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 818                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 819                             40);
 820         }
 821         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 822 }
 823
 824 #define PHY_BUSY_LOOPS  5000
 825
 826 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 827 {
 828         u32 frame_val;
 829         unsigned int loops;
 830         int ret;
 831
 832         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 833                 tw32_f(MAC_MI_MODE,
 834                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 835                 udelay(80);
 836         }
 837
 838         *val = 0x0;
 839
 840         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 841                       MI_COM_PHY_ADDR_MASK);
 842         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 843                       MI_COM_REG_ADDR_MASK);
 844         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 845
 846         tw32_f(MAC_MI_COM, frame_val);
 847
 848         loops = PHY_BUSY_LOOPS;
 849         while (loops != 0) {
 850                 udelay(10);
 851                 frame_val = tr32(MAC_MI_COM);
 852
 853                 if ((frame_val & MI_COM_BUSY) == 0) {
 854                         udelay(5);
 855                         frame_val = tr32(MAC_MI_COM);
 856                         break;
 857                 }
 858                 loops -= 1;
 859         }
 860
 861         ret = -EBUSY;
 862         if (loops != 0) {
 863                 *val = frame_val & MI_COM_DATA_MASK;
 864                 ret = 0;
 865         }
 866
 867         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 868                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 869                 udelay(80);
 870         }
 871
 872         return ret;
 873 }
 874
 875 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 876 {
 877         u32 frame_val;
 878         unsigned int loops;
 879         int ret;
 880
 881         if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
 882             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 883                 return 0;
 884
 885         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 886                 tw32_f(MAC_MI_MODE,
 887                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 888                 udelay(80);
 889         }
 890
 891         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 892                       MI_COM_PHY_ADDR_MASK);
 893         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 894                       MI_COM_REG_ADDR_MASK);
 895         frame_val |= (val & MI_COM_DATA_MASK);
 896         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 897
 898         tw32_f(MAC_MI_COM, frame_val);
 899
 900         loops = PHY_BUSY_LOOPS;
 901         while (loops != 0) {
 902                 udelay(10);
 903                 frame_val = tr32(MAC_MI_COM);
 904                 if ((frame_val & MI_COM_BUSY) == 0) {
 905                         udelay(5);
 906                         frame_val = tr32(MAC_MI_COM);
 907                         break;
 908                 }
 909                 loops -= 1;
 910         }
 911
 912         ret = -EBUSY;
 913         if (loops != 0)
 914                 ret = 0;
 915
 916         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 917                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 918                 udelay(80);
 919         }
 920
 921         return ret;
 922 }
 923
 924 static int tg3_bmcr_reset(struct tg3 *tp)
 925 {
 926         u32 phy_control;
 927         int limit, err;
 928
 929         /* OK, reset it, and poll the BMCR_RESET bit until it
 930          * clears or we time out.
 931          */
 932         phy_control = BMCR_RESET;
 933         err = tg3_writephy(tp, MII_BMCR, phy_control);
 934         if (err != 0)
 935                 return -EBUSY;
 936
 937         limit = 5000;
 938         while (limit--) {
 939                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 940                 if (err != 0)
 941                         return -EBUSY;
 942
 943                 if ((phy_control & BMCR_RESET) == 0) {
 944                         udelay(40);
 945                         break;
 946                 }
 947                 udelay(10);
 948         }
 949         if (limit < 0)
 950                 return -EBUSY;
 951
 952         return 0;
 953 }
 954
 955 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 956 {
 957         struct tg3 *tp = bp->priv;
 958         u32 val;
 959
 960         spin_lock_bh(&tp->lock);
 961
 962         if (tg3_readphy(tp, reg, &val))
 963                 val = -EIO;
 964
 965         spin_unlock_bh(&tp->lock);
 966
 967         return val;
 968 }
 969
 970 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 971 {
 972         struct tg3 *tp = bp->priv;
 973         u32 ret = 0;
 974
 975         spin_lock_bh(&tp->lock);
 976
 977         if (tg3_writephy(tp, reg, val))
 978                 ret = -EIO;
 979
 980         spin_unlock_bh(&tp->lock);
 981
 982         return ret;
 983 }
 984
 985 static int tg3_mdio_reset(struct mii_bus *bp)
 986 {
 987         return 0;
 988 }
 989
 990 static void tg3_mdio_config_5785(struct tg3 *tp)
 991 {
 992         u32 val;
 993         struct phy_device *phydev;
 994
 995         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
 996         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 997         case PHY_ID_BCM50610:
 998         case PHY_ID_BCM50610M:
 999                 val = MAC_PHYCFG2_50610_LED_MODES;
1000                 break;
1001         case PHY_ID_BCMAC131:
1002                 val = MAC_PHYCFG2_AC131_LED_MODES;
1003                 break;
1004         case PHY_ID_RTL8211C:
1005                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1006                 break;
1007         case PHY_ID_RTL8201E:
1008                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1009                 break;
1010         default:
1011                 return;
1012         }
1013
1014         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1015                 tw32(MAC_PHYCFG2, val);
1016
1017                 val = tr32(MAC_PHYCFG1);
1018                 val &= ~(MAC_PHYCFG1_RGMII_INT |
1019                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1020                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1021                 tw32(MAC_PHYCFG1, val);
1022
1023                 return;
1024         }
1025
1026         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
1027                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1028                        MAC_PHYCFG2_FMODE_MASK_MASK |
1029                        MAC_PHYCFG2_GMODE_MASK_MASK |
1030                        MAC_PHYCFG2_ACT_MASK_MASK   |
1031                        MAC_PHYCFG2_QUAL_MASK_MASK |
1032                        MAC_PHYCFG2_INBAND_ENABLE;
1033
1034         tw32(MAC_PHYCFG2, val);
1035
1036         val = tr32(MAC_PHYCFG1);
1037         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1038                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1039         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1040                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1041                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1042                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1043                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1044         }
1045         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1046                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1047         tw32(MAC_PHYCFG1, val);
1048
1049         val = tr32(MAC_EXT_RGMII_MODE);
1050         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1051                  MAC_RGMII_MODE_RX_QUALITY |
1052                  MAC_RGMII_MODE_RX_ACTIVITY |
1053                  MAC_RGMII_MODE_RX_ENG_DET |
1054                  MAC_RGMII_MODE_TX_ENABLE |
1055                  MAC_RGMII_MODE_TX_LOWPWR |
1056                  MAC_RGMII_MODE_TX_RESET);
1057         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1058                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1059                         val |= MAC_RGMII_MODE_RX_INT_B |
1060                                MAC_RGMII_MODE_RX_QUALITY |
1061                                MAC_RGMII_MODE_RX_ACTIVITY |
1062                                MAC_RGMII_MODE_RX_ENG_DET;
1063                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1064                         val |= MAC_RGMII_MODE_TX_ENABLE |
1065                                MAC_RGMII_MODE_TX_LOWPWR |
1066                                MAC_RGMII_MODE_TX_RESET;
1067         }
1068         tw32(MAC_EXT_RGMII_MODE, val);
1069 }
1070
1071 static void tg3_mdio_start(struct tg3 *tp)
1072 {
1073         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1074         tw32_f(MAC_MI_MODE, tp->mi_mode);
1075         udelay(80);
1076
1077         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1078             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1079                 tg3_mdio_config_5785(tp);
1080 }
1081
1082 static int tg3_mdio_init(struct tg3 *tp)
1083 {
1084         int i;
1085         u32 reg;
1086         struct phy_device *phydev;
1087
1088         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1089             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
1090                 u32 is_serdes;
1091
1092                 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1093
1094                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1095                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1096                 else
1097                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1098                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1099                 if (is_serdes)
1100                         tp->phy_addr += 7;
1101         } else
1102                 tp->phy_addr = TG3_PHY_MII_ADDR;
1103
1104         tg3_mdio_start(tp);
1105
1106         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1107             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1108                 return 0;
1109
1110         tp->mdio_bus = mdiobus_alloc();
1111         if (tp->mdio_bus == NULL)
1112                 return -ENOMEM;
1113
1114         tp->mdio_bus->name     = "tg3 mdio bus";
1115         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1116                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1117         tp->mdio_bus->priv     = tp;
1118         tp->mdio_bus->parent   = &tp->pdev->dev;
1119         tp->mdio_bus->read     = &tg3_mdio_read;
1120         tp->mdio_bus->write    = &tg3_mdio_write;
1121         tp->mdio_bus->reset    = &tg3_mdio_reset;
1122         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1123         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1124
1125         for (i = 0; i < PHY_MAX_ADDR; i++)
1126                 tp->mdio_bus->irq[i] = PHY_POLL;
1127
1128         /* The bus registration will look for all the PHYs on the mdio bus.
1129          * Unfortunately, it does not ensure the PHY is powered up before
1130          * accessing the PHY ID registers.  A chip reset is the
1131          * quickest way to bring the device back to an operational state..
1132          */
1133         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1134                 tg3_bmcr_reset(tp);
1135
1136         i = mdiobus_register(tp->mdio_bus);
1137         if (i) {
1138                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1139                 mdiobus_free(tp->mdio_bus);
1140                 return i;
1141         }
1142
1143         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1144
1145         if (!phydev || !phydev->drv) {
1146                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1147                 mdiobus_unregister(tp->mdio_bus);
1148                 mdiobus_free(tp->mdio_bus);
1149                 return -ENODEV;
1150         }
1151
1152         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1153         case PHY_ID_BCM57780:
1154                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1155                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1156                 break;
1157         case PHY_ID_BCM50610:
1158         case PHY_ID_BCM50610M:
1159                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1160                                      PHY_BRCM_RX_REFCLK_UNUSED |
1161                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1162                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1163                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1164                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1165                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1166                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1167                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1168                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1169                 /* fallthru */
1170         case PHY_ID_RTL8211C:
1171                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1172                 break;
1173         case PHY_ID_RTL8201E:
1174         case PHY_ID_BCMAC131:
1175                 phydev->interface = PHY_INTERFACE_MODE_MII;
1176                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1177                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1178                 break;
1179         }
1180
1181         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1182
1183         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1184                 tg3_mdio_config_5785(tp);
1185
1186         return 0;
1187 }
1188
1189 static void tg3_mdio_fini(struct tg3 *tp)
1190 {
1191         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1192                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1193                 mdiobus_unregister(tp->mdio_bus);
1194                 mdiobus_free(tp->mdio_bus);
1195         }
1196 }
1197
1198 /* tp->lock is held. */
1199 static inline void tg3_generate_fw_event(struct tg3 *tp)
1200 {
1201         u32 val;
1202
1203         val = tr32(GRC_RX_CPU_EVENT);
1204         val |= GRC_RX_CPU_DRIVER_EVENT;
1205         tw32_f(GRC_RX_CPU_EVENT, val);
1206
1207         tp->last_event_jiffies = jiffies;
1208 }
1209
1210 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1211
1212 /* tp->lock is held. */
1213 static void tg3_wait_for_event_ack(struct tg3 *tp)
1214 {
1215         int i;
1216         unsigned int delay_cnt;
1217         long time_remain;
1218
1219         /* If enough time has passed, no wait is necessary. */
1220         time_remain = (long)(tp->last_event_jiffies + 1 +
1221                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1222                       (long)jiffies;
1223         if (time_remain < 0)
1224                 return;
1225
1226         /* Check if we can shorten the wait time. */
1227         delay_cnt = jiffies_to_usecs(time_remain);
1228         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1229                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1230         delay_cnt = (delay_cnt >> 3) + 1;
1231
1232         for (i = 0; i < delay_cnt; i++) {
1233                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1234                         break;
1235                 udelay(8);
1236         }
1237 }
1238
1239 /* tp->lock is held. */
1240 static void tg3_ump_link_report(struct tg3 *tp)
1241 {
1242         u32 reg;
1243         u32 val;
1244
1245         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1246             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1247                 return;
1248
1249         tg3_wait_for_event_ack(tp);
1250
1251         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1252
1253         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1254
1255         val = 0;
1256         if (!tg3_readphy(tp, MII_BMCR, &reg))
1257                 val = reg << 16;
1258         if (!tg3_readphy(tp, MII_BMSR, &reg))
1259                 val |= (reg & 0xffff);
1260         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1261
1262         val = 0;
1263         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1264                 val = reg << 16;
1265         if (!tg3_readphy(tp, MII_LPA, &reg))
1266                 val |= (reg & 0xffff);
1267         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1268
1269         val = 0;
1270         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1271                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1272                         val = reg << 16;
1273                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1274                         val |= (reg & 0xffff);
1275         }
1276         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1277
1278         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1279                 val = reg << 16;
1280         else
1281                 val = 0;
1282         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1283
1284         tg3_generate_fw_event(tp);
1285 }
1286
1287 static void tg3_link_report(struct tg3 *tp)
1288 {
1289         if (!netif_carrier_ok(tp->dev)) {
1290                 netif_info(tp, link, tp->dev, "Link is down\n");
1291                 tg3_ump_link_report(tp);
1292         } else if (netif_msg_link(tp)) {
1293                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1294                             (tp->link_config.active_speed == SPEED_1000 ?
1295                              1000 :
1296                              (tp->link_config.active_speed == SPEED_100 ?
1297                               100 : 10)),
1298                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1299                              "full" : "half"));
1300
1301                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1302                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1303                             "on" : "off",
1304                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1305                             "on" : "off");
1306                 tg3_ump_link_report(tp);
1307         }
1308 }
1309
1310 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1311 {
1312         u16 miireg;
1313
1314         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1315                 miireg = ADVERTISE_PAUSE_CAP;
1316         else if (flow_ctrl & FLOW_CTRL_TX)
1317                 miireg = ADVERTISE_PAUSE_ASYM;
1318         else if (flow_ctrl & FLOW_CTRL_RX)
1319                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1320         else
1321                 miireg = 0;
1322
1323         return miireg;
1324 }
1325
1326 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1327 {
1328         u16 miireg;
1329
1330         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1331                 miireg = ADVERTISE_1000XPAUSE;
1332         else if (flow_ctrl & FLOW_CTRL_TX)
1333                 miireg = ADVERTISE_1000XPSE_ASYM;
1334         else if (flow_ctrl & FLOW_CTRL_RX)
1335                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1336         else
1337                 miireg = 0;
1338
1339         return miireg;
1340 }
1341
1342 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1343 {
1344         u8 cap = 0;
1345
1346         if (lcladv & ADVERTISE_1000XPAUSE) {
1347                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1348                         if (rmtadv & LPA_1000XPAUSE)
1349                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1350                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1351                                 cap = FLOW_CTRL_RX;
1352                 } else {
1353                         if (rmtadv & LPA_1000XPAUSE)
1354                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1355                 }
1356         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1357                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1358                         cap = FLOW_CTRL_TX;
1359         }
1360
1361         return cap;
1362 }
1363
1364 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1365 {
1366         u8 autoneg;
1367         u8 flowctrl = 0;
1368         u32 old_rx_mode = tp->rx_mode;
1369         u32 old_tx_mode = tp->tx_mode;
1370
1371         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1372                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1373         else
1374                 autoneg = tp->link_config.autoneg;
1375
1376         if (autoneg == AUTONEG_ENABLE &&
1377             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1378                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1379                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1380                 else
1381                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1382         } else
1383                 flowctrl = tp->link_config.flowctrl;
1384
1385         tp->link_config.active_flowctrl = flowctrl;
1386
1387         if (flowctrl & FLOW_CTRL_RX)
1388                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1389         else
1390                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1391
1392         if (old_rx_mode != tp->rx_mode)
1393                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1394
1395         if (flowctrl & FLOW_CTRL_TX)
1396                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1397         else
1398                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1399
1400         if (old_tx_mode != tp->tx_mode)
1401                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1402 }
1403
1404 static void tg3_adjust_link(struct net_device *dev)
1405 {
1406         u8 oldflowctrl, linkmesg = 0;
1407         u32 mac_mode, lcl_adv, rmt_adv;
1408         struct tg3 *tp = netdev_priv(dev);
1409         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1410
1411         spin_lock_bh(&tp->lock);
1412
1413         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1414                                     MAC_MODE_HALF_DUPLEX);
1415
1416         oldflowctrl = tp->link_config.active_flowctrl;
1417
1418         if (phydev->link) {
1419                 lcl_adv = 0;
1420                 rmt_adv = 0;
1421
1422                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1423                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1424                 else if (phydev->speed == SPEED_1000 ||
1425                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1426                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1427                 else
1428                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1429
1430                 if (phydev->duplex == DUPLEX_HALF)
1431                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1432                 else {
1433                         lcl_adv = tg3_advert_flowctrl_1000T(
1434                                   tp->link_config.flowctrl);
1435
1436                         if (phydev->pause)
1437                                 rmt_adv = LPA_PAUSE_CAP;
1438                         if (phydev->asym_pause)
1439                                 rmt_adv |= LPA_PAUSE_ASYM;
1440                 }
1441
1442                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1443         } else
1444                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1445
1446         if (mac_mode != tp->mac_mode) {
1447                 tp->mac_mode = mac_mode;
1448                 tw32_f(MAC_MODE, tp->mac_mode);
1449                 udelay(40);
1450         }
1451
1452         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1453                 if (phydev->speed == SPEED_10)
1454                         tw32(MAC_MI_STAT,
1455                              MAC_MI_STAT_10MBPS_MODE |
1456                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1457                 else
1458                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1459         }
1460
1461         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1462                 tw32(MAC_TX_LENGTHS,
1463                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1464                       (6 << TX_LENGTHS_IPG_SHIFT) |
1465                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1466         else
1467                 tw32(MAC_TX_LENGTHS,
1468                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1469                       (6 << TX_LENGTHS_IPG_SHIFT) |
1470                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1471
1472         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1473             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1474             phydev->speed != tp->link_config.active_speed ||
1475             phydev->duplex != tp->link_config.active_duplex ||
1476             oldflowctrl != tp->link_config.active_flowctrl)
1477                 linkmesg = 1;
1478
1479         tp->link_config.active_speed = phydev->speed;
1480         tp->link_config.active_duplex = phydev->duplex;
1481
1482         spin_unlock_bh(&tp->lock);
1483
1484         if (linkmesg)
1485                 tg3_link_report(tp);
1486 }
1487
1488 static int tg3_phy_init(struct tg3 *tp)
1489 {
1490         struct phy_device *phydev;
1491
1492         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1493                 return 0;
1494
1495         /* Bring the PHY back to a known state. */
1496         tg3_bmcr_reset(tp);
1497
1498         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1499
1500         /* Attach the MAC to the PHY. */
1501         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1502                              phydev->dev_flags, phydev->interface);
1503         if (IS_ERR(phydev)) {
1504                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1505                 return PTR_ERR(phydev);
1506         }
1507
1508         /* Mask with MAC supported features. */
1509         switch (phydev->interface) {
1510         case PHY_INTERFACE_MODE_GMII:
1511         case PHY_INTERFACE_MODE_RGMII:
1512                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1513                         phydev->supported &= (PHY_GBIT_FEATURES |
1514                                               SUPPORTED_Pause |
1515                                               SUPPORTED_Asym_Pause);
1516                         break;
1517                 }
1518                 /* fallthru */
1519         case PHY_INTERFACE_MODE_MII:
1520                 phydev->supported &= (PHY_BASIC_FEATURES |
1521                                       SUPPORTED_Pause |
1522                                       SUPPORTED_Asym_Pause);
1523                 break;
1524         default:
1525                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1526                 return -EINVAL;
1527         }
1528
1529         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1530
1531         phydev->advertising = phydev->supported;
1532
1533         return 0;
1534 }
1535
1536 static void tg3_phy_start(struct tg3 *tp)
1537 {
1538         struct phy_device *phydev;
1539
1540         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1541                 return;
1542
1543         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1544
1545         if (tp->link_config.phy_is_low_power) {
1546                 tp->link_config.phy_is_low_power = 0;
1547                 phydev->speed = tp->link_config.orig_speed;
1548                 phydev->duplex = tp->link_config.orig_duplex;
1549                 phydev->autoneg = tp->link_config.orig_autoneg;
1550                 phydev->advertising = tp->link_config.orig_advertising;
1551         }
1552
1553         phy_start(phydev);
1554
1555         phy_start_aneg(phydev);
1556 }
1557
1558 static void tg3_phy_stop(struct tg3 *tp)
1559 {
1560         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1561                 return;
1562
1563         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1564 }
1565
1566 static void tg3_phy_fini(struct tg3 *tp)
1567 {
1568         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1569                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1570                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1571         }
1572 }
1573
1574 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1575 {
1576         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1577         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1578 }
1579
1580 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1581 {
1582         u32 phytest;
1583
1584         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1585                 u32 phy;
1586
1587                 tg3_writephy(tp, MII_TG3_FET_TEST,
1588                              phytest | MII_TG3_FET_SHADOW_EN);
1589                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1590                         if (enable)
1591                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1592                         else
1593                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1594                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1595                 }
1596                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1597         }
1598 }
1599
1600 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1601 {
1602         u32 reg;
1603
1604         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1605             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1606               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1607              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1608                 return;
1609
1610         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1611                 tg3_phy_fet_toggle_apd(tp, enable);
1612                 return;
1613         }
1614
1615         reg = MII_TG3_MISC_SHDW_WREN |
1616               MII_TG3_MISC_SHDW_SCR5_SEL |
1617               MII_TG3_MISC_SHDW_SCR5_LPED |
1618               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1619               MII_TG3_MISC_SHDW_SCR5_SDTL |
1620               MII_TG3_MISC_SHDW_SCR5_C125OE;
1621         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1622                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1623
1624         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1625
1626
1627         reg = MII_TG3_MISC_SHDW_WREN |
1628               MII_TG3_MISC_SHDW_APD_SEL |
1629               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1630         if (enable)
1631                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1632
1633         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1634 }
1635
1636 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1637 {
1638         u32 phy;
1639
1640         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1641             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1642                 return;
1643
1644         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1645                 u32 ephy;
1646
1647                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1648                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1649
1650                         tg3_writephy(tp, MII_TG3_FET_TEST,
1651                                      ephy | MII_TG3_FET_SHADOW_EN);
1652                         if (!tg3_readphy(tp, reg, &phy)) {
1653                                 if (enable)
1654                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1655                                 else
1656                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1657                                 tg3_writephy(tp, reg, phy);
1658                         }
1659                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1660                 }
1661         } else {
1662                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1663                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1664                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1665                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1666                         if (enable)
1667                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1668                         else
1669                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1670                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1671                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1672                 }
1673         }
1674 }
1675
1676 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1677 {
1678         u32 val;
1679
1680         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1681                 return;
1682
1683         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1684             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1685                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1686                              (val | (1 << 15) | (1 << 4)));
1687 }
1688
1689 static void tg3_phy_apply_otp(struct tg3 *tp)
1690 {
1691         u32 otp, phy;
1692
1693         if (!tp->phy_otp)
1694                 return;
1695
1696         otp = tp->phy_otp;
1697
1698         /* Enable SM_DSP clock and tx 6dB coding. */
1699         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1700               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1701               MII_TG3_AUXCTL_ACTL_TX_6DB;
1702         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1703
1704         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1705         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1706         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1707
1708         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1709               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1710         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1711
1712         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1713         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1714         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1715
1716         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1717         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1718
1719         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1720         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1721
1722         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1723               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1724         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1725
1726         /* Turn off SM_DSP clock. */
1727         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1728               MII_TG3_AUXCTL_ACTL_TX_6DB;
1729         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1730 }
1731
1732 static int tg3_wait_macro_done(struct tg3 *tp)
1733 {
1734         int limit = 100;
1735
1736         while (limit--) {
1737                 u32 tmp32;
1738
1739                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1740                         if ((tmp32 & 0x1000) == 0)
1741                                 break;
1742                 }
1743         }
1744         if (limit < 0)
1745                 return -EBUSY;
1746
1747         return 0;
1748 }
1749
1750 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1751 {
1752         static const u32 test_pat[4][6] = {
1753         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1754         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1755         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1756         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1757         };
1758         int chan;
1759
1760         for (chan = 0; chan < 4; chan++) {
1761                 int i;
1762
1763                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1764                              (chan * 0x2000) | 0x0200);
1765                 tg3_writephy(tp, 0x16, 0x0002);
1766
1767                 for (i = 0; i < 6; i++)
1768                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1769                                      test_pat[chan][i]);
1770
1771                 tg3_writephy(tp, 0x16, 0x0202);
1772                 if (tg3_wait_macro_done(tp)) {
1773                         *resetp = 1;
1774                         return -EBUSY;
1775                 }
1776
1777                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1778                              (chan * 0x2000) | 0x0200);
1779                 tg3_writephy(tp, 0x16, 0x0082);
1780                 if (tg3_wait_macro_done(tp)) {
1781                         *resetp = 1;
1782                         return -EBUSY;
1783                 }
1784
1785                 tg3_writephy(tp, 0x16, 0x0802);
1786                 if (tg3_wait_macro_done(tp)) {
1787                         *resetp = 1;
1788                         return -EBUSY;
1789                 }
1790
1791                 for (i = 0; i < 6; i += 2) {
1792                         u32 low, high;
1793
1794                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1795                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1796                             tg3_wait_macro_done(tp)) {
1797                                 *resetp = 1;
1798                                 return -EBUSY;
1799                         }
1800                         low &= 0x7fff;
1801                         high &= 0x000f;
1802                         if (low != test_pat[chan][i] ||
1803                             high != test_pat[chan][i+1]) {
1804                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1805                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1806                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1807
1808                                 return -EBUSY;
1809                         }
1810                 }
1811         }
1812
1813         return 0;
1814 }
1815
1816 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1817 {
1818         int chan;
1819
1820         for (chan = 0; chan < 4; chan++) {
1821                 int i;
1822
1823                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1824                              (chan * 0x2000) | 0x0200);
1825                 tg3_writephy(tp, 0x16, 0x0002);
1826                 for (i = 0; i < 6; i++)
1827                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1828                 tg3_writephy(tp, 0x16, 0x0202);
1829                 if (tg3_wait_macro_done(tp))
1830                         return -EBUSY;
1831         }
1832
1833         return 0;
1834 }
1835
1836 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1837 {
1838         u32 reg32, phy9_orig;
1839         int retries, do_phy_reset, err;
1840
1841         retries = 10;
1842         do_phy_reset = 1;
1843         do {
1844                 if (do_phy_reset) {
1845                         err = tg3_bmcr_reset(tp);
1846                         if (err)
1847                                 return err;
1848                         do_phy_reset = 0;
1849                 }
1850
1851                 /* Disable transmitter and interrupt.  */
1852                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1853                         continue;
1854
1855                 reg32 |= 0x3000;
1856                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1857
1858                 /* Set full-duplex, 1000 mbps.  */
1859                 tg3_writephy(tp, MII_BMCR,
1860                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1861
1862                 /* Set to master mode.  */
1863                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1864                         continue;
1865
1866                 tg3_writephy(tp, MII_TG3_CTRL,
1867                              (MII_TG3_CTRL_AS_MASTER |
1868                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1869
1870                 /* Enable SM_DSP_CLOCK and 6dB.  */
1871                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1872
1873                 /* Block the PHY control access.  */
1874                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1875                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1876
1877                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1878                 if (!err)
1879                         break;
1880         } while (--retries);
1881
1882         err = tg3_phy_reset_chanpat(tp);
1883         if (err)
1884                 return err;
1885
1886         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1887         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1888
1889         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1890         tg3_writephy(tp, 0x16, 0x0000);
1891
1892         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1893             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1894                 /* Set Extended packet length bit for jumbo frames */
1895                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1896         } else {
1897                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1898         }
1899
1900         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1901
1902         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1903                 reg32 &= ~0x3000;
1904                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1905         } else if (!err)
1906                 err = -EBUSY;
1907
1908         return err;
1909 }
1910
1911 /* This will reset the tigon3 PHY if there is no valid
1912  * link unless the FORCE argument is non-zero.
1913  */
1914 static int tg3_phy_reset(struct tg3 *tp)
1915 {
1916         u32 cpmuctrl;
1917         u32 phy_status;
1918         int err;
1919
1920         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1921                 u32 val;
1922
1923                 val = tr32(GRC_MISC_CFG);
1924                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1925                 udelay(40);
1926         }
1927         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1928         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1929         if (err != 0)
1930                 return -EBUSY;
1931
1932         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1933                 netif_carrier_off(tp->dev);
1934                 tg3_link_report(tp);
1935         }
1936
1937         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1938             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1939             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1940                 err = tg3_phy_reset_5703_4_5(tp);
1941                 if (err)
1942                         return err;
1943                 goto out;
1944         }
1945
1946         cpmuctrl = 0;
1947         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1948             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1949                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1950                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1951                         tw32(TG3_CPMU_CTRL,
1952                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1953         }
1954
1955         err = tg3_bmcr_reset(tp);
1956         if (err)
1957                 return err;
1958
1959         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1960                 u32 phy;
1961
1962                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1963                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1964
1965                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1966         }
1967
1968         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1969             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1970                 u32 val;
1971
1972                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1973                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1974                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1975                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1976                         udelay(40);
1977                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1978                 }
1979         }
1980
1981         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1982              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1983             (tp->tg3_flags2 & TG3_FLG2_MII_SERDES))
1984                 return 0;
1985
1986         tg3_phy_apply_otp(tp);
1987
1988         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1989                 tg3_phy_toggle_apd(tp, true);
1990         else
1991                 tg3_phy_toggle_apd(tp, false);
1992
1993 out:
1994         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1995                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1996                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1997                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1998                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1999                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
2000                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2001         }
2002         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
2003                 tg3_writephy(tp, 0x1c, 0x8d68);
2004                 tg3_writephy(tp, 0x1c, 0x8d68);
2005         }
2006         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
2007                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2008                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2009                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
2010                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2011                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
2012                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
2013                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
2014                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2015         } else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
2016                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2017                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2018                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
2019                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2020                         tg3_writephy(tp, MII_TG3_TEST1,
2021                                      MII_TG3_TEST1_TRIM_EN | 0x4);
2022                 } else
2023                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2024                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2025         }
2026         /* Set Extended packet length bit (bit 14) on all chips that */
2027         /* support jumbo frames */
2028         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2029                 /* Cannot do read-modify-write on 5401 */
2030                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2031         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2032                 u32 phy_reg;
2033
2034                 /* Set bit 14 with read-modify-write to preserve other bits */
2035                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2036                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
2037                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
2038         }
2039
2040         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2041          * jumbo frames transmission.
2042          */
2043         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2044                 u32 phy_reg;
2045
2046                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
2047                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2048                                      phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2049         }
2050
2051         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2052                 /* adjust output voltage */
2053                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2054         }
2055
2056         tg3_phy_toggle_automdix(tp, 1);
2057         tg3_phy_set_wirespeed(tp);
2058         return 0;
2059 }
2060
2061 static void tg3_frob_aux_power(struct tg3 *tp)
2062 {
2063         struct tg3 *tp_peer = tp;
2064
2065         /* The GPIOs do something completely different on 57765. */
2066         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2067             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2068             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2069                 return;
2070
2071         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2072             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2073             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2074                 struct net_device *dev_peer;
2075
2076                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2077                 /* remove_one() may have been run on the peer. */
2078                 if (!dev_peer)
2079                         tp_peer = tp;
2080                 else
2081                         tp_peer = netdev_priv(dev_peer);
2082         }
2083
2084         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2085             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2086             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2087             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2088                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2089                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2090                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2091                                     (GRC_LCLCTRL_GPIO_OE0 |
2092                                      GRC_LCLCTRL_GPIO_OE1 |
2093                                      GRC_LCLCTRL_GPIO_OE2 |
2094                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2095                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2096                                     100);
2097                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2098                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2099                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2100                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2101                                              GRC_LCLCTRL_GPIO_OE1 |
2102                                              GRC_LCLCTRL_GPIO_OE2 |
2103                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2104                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2105                                              tp->grc_local_ctrl;
2106                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2107
2108                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2109                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2110
2111                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2112                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2113                 } else {
2114                         u32 no_gpio2;
2115                         u32 grc_local_ctrl = 0;
2116
2117                         if (tp_peer != tp &&
2118                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2119                                 return;
2120
2121                         /* Workaround to prevent overdrawing Amps. */
2122                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2123                             ASIC_REV_5714) {
2124                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2125                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2126                                             grc_local_ctrl, 100);
2127                         }
2128
2129                         /* On 5753 and variants, GPIO2 cannot be used. */
2130                         no_gpio2 = tp->nic_sram_data_cfg &
2131                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2132
2133                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2134                                          GRC_LCLCTRL_GPIO_OE1 |
2135                                          GRC_LCLCTRL_GPIO_OE2 |
2136                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2137                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2138                         if (no_gpio2) {
2139                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2140                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2141                         }
2142                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2143                                                     grc_local_ctrl, 100);
2144
2145                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2146
2147                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2148                                                     grc_local_ctrl, 100);
2149
2150                         if (!no_gpio2) {
2151                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2152                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2153                                             grc_local_ctrl, 100);
2154                         }
2155                 }
2156         } else {
2157                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2158                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2159                         if (tp_peer != tp &&
2160                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2161                                 return;
2162
2163                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2164                                     (GRC_LCLCTRL_GPIO_OE1 |
2165                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2166
2167                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2168                                     GRC_LCLCTRL_GPIO_OE1, 100);
2169
2170                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2171                                     (GRC_LCLCTRL_GPIO_OE1 |
2172                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2173                 }
2174         }
2175 }
2176
2177 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2178 {
2179         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2180                 return 1;
2181         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2182                 if (speed != SPEED_10)
2183                         return 1;
2184         } else if (speed == SPEED_10)
2185                 return 1;
2186
2187         return 0;
2188 }
2189
2190 static int tg3_setup_phy(struct tg3 *, int);
2191
2192 #define RESET_KIND_SHUTDOWN     0
2193 #define RESET_KIND_INIT         1
2194 #define RESET_KIND_SUSPEND      2
2195
2196 static void tg3_write_sig_post_reset(struct tg3 *, int);
2197 static int tg3_halt_cpu(struct tg3 *, u32);
2198
2199 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2200 {
2201         u32 val;
2202
2203         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2204                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2205                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2206                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2207
2208                         sg_dig_ctrl |=
2209                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2210                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2211                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2212                 }
2213                 return;
2214         }
2215
2216         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2217                 tg3_bmcr_reset(tp);
2218                 val = tr32(GRC_MISC_CFG);
2219                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2220                 udelay(40);
2221                 return;
2222         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2223                 u32 phytest;
2224                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2225                         u32 phy;
2226
2227                         tg3_writephy(tp, MII_ADVERTISE, 0);
2228                         tg3_writephy(tp, MII_BMCR,
2229                                      BMCR_ANENABLE | BMCR_ANRESTART);
2230
2231                         tg3_writephy(tp, MII_TG3_FET_TEST,
2232                                      phytest | MII_TG3_FET_SHADOW_EN);
2233                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2234                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2235                                 tg3_writephy(tp,
2236                                              MII_TG3_FET_SHDW_AUXMODE4,
2237                                              phy);
2238                         }
2239                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2240                 }
2241                 return;
2242         } else if (do_low_power) {
2243                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2244                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2245
2246                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2247                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2248                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2249                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2250                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2251         }
2252
2253         /* The PHY should not be powered down on some chips because
2254          * of bugs.
2255          */
2256         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2257             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2258             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2259              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2260                 return;
2261
2262         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2263             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2264                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2265                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2266                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2267                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2268         }
2269
2270         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2271 }
2272
2273 /* tp->lock is held. */
2274 static int tg3_nvram_lock(struct tg3 *tp)
2275 {
2276         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2277                 int i;
2278
2279                 if (tp->nvram_lock_cnt == 0) {
2280                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2281                         for (i = 0; i < 8000; i++) {
2282                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2283                                         break;
2284                                 udelay(20);
2285                         }
2286                         if (i == 8000) {
2287                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2288                                 return -ENODEV;
2289                         }
2290                 }
2291                 tp->nvram_lock_cnt++;
2292         }
2293         return 0;
2294 }
2295
2296 /* tp->lock is held. */
2297 static void tg3_nvram_unlock(struct tg3 *tp)
2298 {
2299         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2300                 if (tp->nvram_lock_cnt > 0)
2301                         tp->nvram_lock_cnt--;
2302                 if (tp->nvram_lock_cnt == 0)
2303                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2304         }
2305 }
2306
2307 /* tp->lock is held. */
2308 static void tg3_enable_nvram_access(struct tg3 *tp)
2309 {
2310         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2311             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2312                 u32 nvaccess = tr32(NVRAM_ACCESS);
2313
2314                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2315         }
2316 }
2317
2318 /* tp->lock is held. */
2319 static void tg3_disable_nvram_access(struct tg3 *tp)
2320 {
2321         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2322             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2323                 u32 nvaccess = tr32(NVRAM_ACCESS);
2324
2325                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2326         }
2327 }
2328
2329 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2330                                         u32 offset, u32 *val)
2331 {
2332         u32 tmp;
2333         int i;
2334
2335         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2336                 return -EINVAL;
2337
2338         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2339                                         EEPROM_ADDR_DEVID_MASK |
2340                                         EEPROM_ADDR_READ);
2341         tw32(GRC_EEPROM_ADDR,
2342              tmp |
2343              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2344              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2345               EEPROM_ADDR_ADDR_MASK) |
2346              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2347
2348         for (i = 0; i < 1000; i++) {
2349                 tmp = tr32(GRC_EEPROM_ADDR);
2350
2351                 if (tmp & EEPROM_ADDR_COMPLETE)
2352                         break;
2353                 msleep(1);
2354         }
2355         if (!(tmp & EEPROM_ADDR_COMPLETE))
2356                 return -EBUSY;
2357
2358         tmp = tr32(GRC_EEPROM_DATA);
2359
2360         /*
2361          * The data will always be opposite the native endian
2362          * format.  Perform a blind byteswap to compensate.
2363          */
2364         *val = swab32(tmp);
2365
2366         return 0;
2367 }
2368
2369 #define NVRAM_CMD_TIMEOUT 10000
2370
2371 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2372 {
2373         int i;
2374
2375         tw32(NVRAM_CMD, nvram_cmd);
2376         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2377                 udelay(10);
2378                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2379                         udelay(10);
2380                         break;
2381                 }
2382         }
2383
2384         if (i == NVRAM_CMD_TIMEOUT)
2385                 return -EBUSY;
2386
2387         return 0;
2388 }
2389
2390 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2391 {
2392         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2393             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2394             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2395            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2396             (tp->nvram_jedecnum == JEDEC_ATMEL))
2397
2398                 addr = ((addr / tp->nvram_pagesize) <<
2399                         ATMEL_AT45DB0X1B_PAGE_POS) +
2400                        (addr % tp->nvram_pagesize);
2401
2402         return addr;
2403 }
2404
2405 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2406 {
2407         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2408             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2409             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2410            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2411             (tp->nvram_jedecnum == JEDEC_ATMEL))
2412
2413                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2414                         tp->nvram_pagesize) +
2415                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2416
2417         return addr;
2418 }
2419
2420 /* NOTE: Data read in from NVRAM is byteswapped according to
2421  * the byteswapping settings for all other register accesses.
2422  * tg3 devices are BE devices, so on a BE machine, the data
2423  * returned will be exactly as it is seen in NVRAM.  On a LE
2424  * machine, the 32-bit value will be byteswapped.
2425  */
2426 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2427 {
2428         int ret;
2429
2430         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2431                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2432
2433         offset = tg3_nvram_phys_addr(tp, offset);
2434
2435         if (offset > NVRAM_ADDR_MSK)
2436                 return -EINVAL;
2437
2438         ret = tg3_nvram_lock(tp);
2439         if (ret)
2440                 return ret;
2441
2442         tg3_enable_nvram_access(tp);
2443
2444         tw32(NVRAM_ADDR, offset);
2445         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2446                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2447
2448         if (ret == 0)
2449                 *val = tr32(NVRAM_RDDATA);
2450
2451         tg3_disable_nvram_access(tp);
2452
2453         tg3_nvram_unlock(tp);
2454
2455         return ret;
2456 }
2457
2458 /* Ensures NVRAM data is in bytestream format. */
2459 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2460 {
2461         u32 v;
2462         int res = tg3_nvram_read(tp, offset, &v);
2463         if (!res)
2464                 *val = cpu_to_be32(v);
2465         return res;
2466 }
2467
2468 /* tp->lock is held. */
2469 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2470 {
2471         u32 addr_high, addr_low;
2472         int i;
2473
2474         addr_high = ((tp->dev->dev_addr[0] << 8) |
2475                      tp->dev->dev_addr[1]);
2476         addr_low = ((tp->dev->dev_addr[2] << 24) |
2477                     (tp->dev->dev_addr[3] << 16) |
2478                     (tp->dev->dev_addr[4] <<  8) |
2479                     (tp->dev->dev_addr[5] <<  0));
2480         for (i = 0; i < 4; i++) {
2481                 if (i == 1 && skip_mac_1)
2482                         continue;
2483                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2484                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2485         }
2486
2487         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2488             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2489                 for (i = 0; i < 12; i++) {
2490                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2491                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2492                 }
2493         }
2494
2495         addr_high = (tp->dev->dev_addr[0] +
2496                      tp->dev->dev_addr[1] +
2497                      tp->dev->dev_addr[2] +
2498                      tp->dev->dev_addr[3] +
2499                      tp->dev->dev_addr[4] +
2500                      tp->dev->dev_addr[5]) &
2501                 TX_BACKOFF_SEED_MASK;
2502         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2503 }
2504
2505 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2506 {
2507         u32 misc_host_ctrl;
2508         bool device_should_wake, do_low_power;
2509
2510         /* Make sure register accesses (indirect or otherwise)
2511          * will function correctly.
2512          */
2513         pci_write_config_dword(tp->pdev,
2514                                TG3PCI_MISC_HOST_CTRL,
2515                                tp->misc_host_ctrl);
2516
2517         switch (state) {
2518         case PCI_D0:
2519                 pci_enable_wake(tp->pdev, state, false);
2520                 pci_set_power_state(tp->pdev, PCI_D0);
2521
2522                 /* Switch out of Vaux if it is a NIC */
2523                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2524                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2525
2526                 return 0;
2527
2528         case PCI_D1:
2529         case PCI_D2:
2530         case PCI_D3hot:
2531                 break;
2532
2533         default:
2534                 netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
2535                            state);
2536                 return -EINVAL;
2537         }
2538
2539         /* Restore the CLKREQ setting. */
2540         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2541                 u16 lnkctl;
2542
2543                 pci_read_config_word(tp->pdev,
2544                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2545                                      &lnkctl);
2546                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2547                 pci_write_config_word(tp->pdev,
2548                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2549                                       lnkctl);
2550         }
2551
2552         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2553         tw32(TG3PCI_MISC_HOST_CTRL,
2554              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2555
2556         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2557                              device_may_wakeup(&tp->pdev->dev) &&
2558                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2559
2560         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2561                 do_low_power = false;
2562                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2563                     !tp->link_config.phy_is_low_power) {
2564                         struct phy_device *phydev;
2565                         u32 phyid, advertising;
2566
2567                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2568
2569                         tp->link_config.phy_is_low_power = 1;
2570
2571                         tp->link_config.orig_speed = phydev->speed;
2572                         tp->link_config.orig_duplex = phydev->duplex;
2573                         tp->link_config.orig_autoneg = phydev->autoneg;
2574                         tp->link_config.orig_advertising = phydev->advertising;
2575
2576                         advertising = ADVERTISED_TP |
2577                                       ADVERTISED_Pause |
2578                                       ADVERTISED_Autoneg |
2579                                       ADVERTISED_10baseT_Half;
2580
2581                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2582                             device_should_wake) {
2583                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2584                                         advertising |=
2585                                                 ADVERTISED_100baseT_Half |
2586                                                 ADVERTISED_100baseT_Full |
2587                                                 ADVERTISED_10baseT_Full;
2588                                 else
2589                                         advertising |= ADVERTISED_10baseT_Full;
2590                         }
2591
2592                         phydev->advertising = advertising;
2593
2594                         phy_start_aneg(phydev);
2595
2596                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2597                         if (phyid != PHY_ID_BCMAC131) {
2598                                 phyid &= PHY_BCM_OUI_MASK;
2599                                 if (phyid == PHY_BCM_OUI_1 ||
2600                                     phyid == PHY_BCM_OUI_2 ||
2601                                     phyid == PHY_BCM_OUI_3)
2602                                         do_low_power = true;
2603                         }
2604                 }
2605         } else {
2606                 do_low_power = true;
2607
2608                 if (tp->link_config.phy_is_low_power == 0) {
2609                         tp->link_config.phy_is_low_power = 1;
2610                         tp->link_config.orig_speed = tp->link_config.speed;
2611                         tp->link_config.orig_duplex = tp->link_config.duplex;
2612                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2613                 }
2614
2615                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2616                         tp->link_config.speed = SPEED_10;
2617                         tp->link_config.duplex = DUPLEX_HALF;
2618                         tp->link_config.autoneg = AUTONEG_ENABLE;
2619                         tg3_setup_phy(tp, 0);
2620                 }
2621         }
2622
2623         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2624                 u32 val;
2625
2626                 val = tr32(GRC_VCPU_EXT_CTRL);
2627                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2628         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2629                 int i;
2630                 u32 val;
2631
2632                 for (i = 0; i < 200; i++) {
2633                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2634                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2635                                 break;
2636                         msleep(1);
2637                 }
2638         }
2639         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2640                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2641                                                      WOL_DRV_STATE_SHUTDOWN |
2642                                                      WOL_DRV_WOL |
2643                                                      WOL_SET_MAGIC_PKT);
2644
2645         if (device_should_wake) {
2646                 u32 mac_mode;
2647
2648                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2649                         if (do_low_power) {
2650                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2651                                 udelay(40);
2652                         }
2653
2654                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2655                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2656                         else
2657                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2658
2659                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2660                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2661                             ASIC_REV_5700) {
2662                                 u32 speed = (tp->tg3_flags &
2663                                              TG3_FLAG_WOL_SPEED_100MB) ?
2664                                              SPEED_100 : SPEED_10;
2665                                 if (tg3_5700_link_polarity(tp, speed))
2666                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2667                                 else
2668                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2669                         }
2670                 } else {
2671                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2672                 }
2673
2674                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2675                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2676
2677                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2678                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2679                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2680                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2681                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2682                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2683
2684                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2685                         mac_mode |= tp->mac_mode &
2686                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2687                         if (mac_mode & MAC_MODE_APE_TX_EN)
2688                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2689                 }
2690
2691                 tw32_f(MAC_MODE, mac_mode);
2692                 udelay(100);
2693
2694                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2695                 udelay(10);
2696         }
2697
2698         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2699             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2700              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2701                 u32 base_val;
2702
2703                 base_val = tp->pci_clock_ctrl;
2704                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2705                              CLOCK_CTRL_TXCLK_DISABLE);
2706
2707                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2708                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2709         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2710                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2711                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2712                 /* do nothing */
2713         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2714                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2715                 u32 newbits1, newbits2;
2716
2717                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2718                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2719                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2720                                     CLOCK_CTRL_TXCLK_DISABLE |
2721                                     CLOCK_CTRL_ALTCLK);
2722                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2723                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2724                         newbits1 = CLOCK_CTRL_625_CORE;
2725                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2726                 } else {
2727                         newbits1 = CLOCK_CTRL_ALTCLK;
2728                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2729                 }
2730
2731                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2732                             40);
2733
2734                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2735                             40);
2736
2737                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2738                         u32 newbits3;
2739
2740                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2741                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2742                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2743                                             CLOCK_CTRL_TXCLK_DISABLE |
2744                                             CLOCK_CTRL_44MHZ_CORE);
2745                         } else {
2746                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2747                         }
2748
2749                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2750                                     tp->pci_clock_ctrl | newbits3, 40);
2751                 }
2752         }
2753
2754         if (!(device_should_wake) &&
2755             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2756                 tg3_power_down_phy(tp, do_low_power);
2757
2758         tg3_frob_aux_power(tp);
2759
2760         /* Workaround for unstable PLL clock */
2761         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2762             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2763                 u32 val = tr32(0x7d00);
2764
2765                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2766                 tw32(0x7d00, val);
2767                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2768                         int err;
2769
2770                         err = tg3_nvram_lock(tp);
2771                         tg3_halt_cpu(tp, RX_CPU_BASE);
2772                         if (!err)
2773                                 tg3_nvram_unlock(tp);
2774                 }
2775         }
2776
2777         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2778
2779         if (device_should_wake)
2780                 pci_enable_wake(tp->pdev, state, true);
2781
2782         /* Finally, set the new power state. */
2783         pci_set_power_state(tp->pdev, state);
2784
2785         return 0;
2786 }
2787
2788 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2789 {
2790         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2791         case MII_TG3_AUX_STAT_10HALF:
2792                 *speed = SPEED_10;
2793                 *duplex = DUPLEX_HALF;
2794                 break;
2795
2796         case MII_TG3_AUX_STAT_10FULL:
2797                 *speed = SPEED_10;
2798                 *duplex = DUPLEX_FULL;
2799                 break;
2800
2801         case MII_TG3_AUX_STAT_100HALF:
2802                 *speed = SPEED_100;
2803                 *duplex = DUPLEX_HALF;
2804                 break;
2805
2806         case MII_TG3_AUX_STAT_100FULL:
2807                 *speed = SPEED_100;
2808                 *duplex = DUPLEX_FULL;
2809                 break;
2810
2811         case MII_TG3_AUX_STAT_1000HALF:
2812                 *speed = SPEED_1000;
2813                 *duplex = DUPLEX_HALF;
2814                 break;
2815
2816         case MII_TG3_AUX_STAT_1000FULL:
2817                 *speed = SPEED_1000;
2818                 *duplex = DUPLEX_FULL;
2819                 break;
2820
2821         default:
2822                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2823                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2824                                  SPEED_10;
2825                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2826                                   DUPLEX_HALF;
2827                         break;
2828                 }
2829                 *speed = SPEED_INVALID;
2830                 *duplex = DUPLEX_INVALID;
2831                 break;
2832         }
2833 }
2834
2835 static void tg3_phy_copper_begin(struct tg3 *tp)
2836 {
2837         u32 new_adv;
2838         int i;
2839
2840         if (tp->link_config.phy_is_low_power) {
2841                 /* Entering low power mode.  Disable gigabit and
2842                  * 100baseT advertisements.
2843                  */
2844                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2845
2846                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2847                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2848                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2849                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2850
2851                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2852         } else if (tp->link_config.speed == SPEED_INVALID) {
2853                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2854                         tp->link_config.advertising &=
2855                                 ~(ADVERTISED_1000baseT_Half |
2856                                   ADVERTISED_1000baseT_Full);
2857
2858                 new_adv = ADVERTISE_CSMA;
2859                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2860                         new_adv |= ADVERTISE_10HALF;
2861                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2862                         new_adv |= ADVERTISE_10FULL;
2863                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2864                         new_adv |= ADVERTISE_100HALF;
2865                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2866                         new_adv |= ADVERTISE_100FULL;
2867
2868                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2869
2870                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2871
2872                 if (tp->link_config.advertising &
2873                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2874                         new_adv = 0;
2875                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2876                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2877                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2878                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2879                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2880                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2881                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2882                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2883                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2884                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2885                 } else {
2886                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2887                 }
2888         } else {
2889                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2890                 new_adv |= ADVERTISE_CSMA;
2891
2892                 /* Asking for a specific link mode. */
2893                 if (tp->link_config.speed == SPEED_1000) {
2894                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2895
2896                         if (tp->link_config.duplex == DUPLEX_FULL)
2897                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2898                         else
2899                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2900                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2901                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2902                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2903                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2904                 } else {
2905                         if (tp->link_config.speed == SPEED_100) {
2906                                 if (tp->link_config.duplex == DUPLEX_FULL)
2907                                         new_adv |= ADVERTISE_100FULL;
2908                                 else
2909                                         new_adv |= ADVERTISE_100HALF;
2910                         } else {
2911                                 if (tp->link_config.duplex == DUPLEX_FULL)
2912                                         new_adv |= ADVERTISE_10FULL;
2913                                 else
2914                                         new_adv |= ADVERTISE_10HALF;
2915                         }
2916                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2917
2918                         new_adv = 0;
2919                 }
2920
2921                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2922         }
2923
2924         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2925             tp->link_config.speed != SPEED_INVALID) {
2926                 u32 bmcr, orig_bmcr;
2927
2928                 tp->link_config.active_speed = tp->link_config.speed;
2929                 tp->link_config.active_duplex = tp->link_config.duplex;
2930
2931                 bmcr = 0;
2932                 switch (tp->link_config.speed) {
2933                 default:
2934                 case SPEED_10:
2935                         break;
2936
2937                 case SPEED_100:
2938                         bmcr |= BMCR_SPEED100;
2939                         break;
2940
2941                 case SPEED_1000:
2942                         bmcr |= TG3_BMCR_SPEED1000;
2943                         break;
2944                 }
2945
2946                 if (tp->link_config.duplex == DUPLEX_FULL)
2947                         bmcr |= BMCR_FULLDPLX;
2948
2949                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2950                     (bmcr != orig_bmcr)) {
2951                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2952                         for (i = 0; i < 1500; i++) {
2953                                 u32 tmp;
2954
2955                                 udelay(10);
2956                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2957                                     tg3_readphy(tp, MII_BMSR, &tmp))
2958                                         continue;
2959                                 if (!(tmp & BMSR_LSTATUS)) {
2960                                         udelay(40);
2961                                         break;
2962                                 }
2963                         }
2964                         tg3_writephy(tp, MII_BMCR, bmcr);
2965                         udelay(40);
2966                 }
2967         } else {
2968                 tg3_writephy(tp, MII_BMCR,
2969                              BMCR_ANENABLE | BMCR_ANRESTART);
2970         }
2971 }
2972
2973 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2974 {
2975         int err;
2976
2977         /* Turn off tap power management. */
2978         /* Set Extended packet length bit */
2979         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2980
2981         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2982         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2983
2984         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2985         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2986
2987         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2988         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2989
2990         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2991         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2992
2993         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2994         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2995
2996         udelay(40);
2997
2998         return err;
2999 }
3000
3001 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
3002 {
3003         u32 adv_reg, all_mask = 0;
3004
3005         if (mask & ADVERTISED_10baseT_Half)
3006                 all_mask |= ADVERTISE_10HALF;
3007         if (mask & ADVERTISED_10baseT_Full)
3008                 all_mask |= ADVERTISE_10FULL;
3009         if (mask & ADVERTISED_100baseT_Half)
3010                 all_mask |= ADVERTISE_100HALF;
3011         if (mask & ADVERTISED_100baseT_Full)
3012                 all_mask |= ADVERTISE_100FULL;
3013
3014         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3015                 return 0;
3016
3017         if ((adv_reg & all_mask) != all_mask)
3018                 return 0;
3019         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
3020                 u32 tg3_ctrl;
3021
3022                 all_mask = 0;
3023                 if (mask & ADVERTISED_1000baseT_Half)
3024                         all_mask |= ADVERTISE_1000HALF;
3025                 if (mask & ADVERTISED_1000baseT_Full)
3026                         all_mask |= ADVERTISE_1000FULL;
3027
3028                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3029                         return 0;
3030
3031                 if ((tg3_ctrl & all_mask) != all_mask)
3032                         return 0;
3033         }
3034         return 1;
3035 }
3036
3037 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3038 {
3039         u32 curadv, reqadv;
3040
3041         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3042                 return 1;
3043
3044         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3045         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3046
3047         if (tp->link_config.active_duplex == DUPLEX_FULL) {
3048                 if (curadv != reqadv)
3049                         return 0;
3050
3051                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3052                         tg3_readphy(tp, MII_LPA, rmtadv);
3053         } else {
3054                 /* Reprogram the advertisement register, even if it
3055                  * does not affect the current link.  If the link
3056                  * gets renegotiated in the future, we can save an
3057                  * additional renegotiation cycle by advertising
3058                  * it correctly in the first place.
3059                  */
3060                 if (curadv != reqadv) {
3061                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3062                                      ADVERTISE_PAUSE_ASYM);
3063                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3064                 }
3065         }
3066
3067         return 1;
3068 }
3069
3070 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3071 {
3072         int current_link_up;
3073         u32 bmsr, dummy;
3074         u32 lcl_adv, rmt_adv;
3075         u16 current_speed;
3076         u8 current_duplex;
3077         int i, err;
3078
3079         tw32(MAC_EVENT, 0);
3080
3081         tw32_f(MAC_STATUS,
3082              (MAC_STATUS_SYNC_CHANGED |
3083               MAC_STATUS_CFG_CHANGED |
3084               MAC_STATUS_MI_COMPLETION |
3085               MAC_STATUS_LNKSTATE_CHANGED));
3086         udelay(40);
3087
3088         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3089                 tw32_f(MAC_MI_MODE,
3090                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3091                 udelay(80);
3092         }
3093
3094         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3095
3096         /* Some third-party PHYs need to be reset on link going
3097          * down.
3098          */
3099         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3100              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3101              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3102             netif_carrier_ok(tp->dev)) {
3103                 tg3_readphy(tp, MII_BMSR, &bmsr);
3104                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3105                     !(bmsr & BMSR_LSTATUS))
3106                         force_reset = 1;
3107         }
3108         if (force_reset)
3109                 tg3_phy_reset(tp);
3110
3111         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3112                 tg3_readphy(tp, MII_BMSR, &bmsr);
3113                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3114                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3115                         bmsr = 0;
3116
3117                 if (!(bmsr & BMSR_LSTATUS)) {
3118                         err = tg3_init_5401phy_dsp(tp);
3119                         if (err)
3120                                 return err;
3121
3122                         tg3_readphy(tp, MII_BMSR, &bmsr);
3123                         for (i = 0; i < 1000; i++) {
3124                                 udelay(10);
3125                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3126                                     (bmsr & BMSR_LSTATUS)) {
3127                                         udelay(40);
3128                                         break;
3129                                 }
3130                         }
3131
3132                         if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3133                             TG3_PHY_REV_BCM5401_B0 &&
3134                             !(bmsr & BMSR_LSTATUS) &&
3135                             tp->link_config.active_speed == SPEED_1000) {
3136                                 err = tg3_phy_reset(tp);
3137                                 if (!err)
3138                                         err = tg3_init_5401phy_dsp(tp);
3139                                 if (err)
3140                                         return err;
3141                         }
3142                 }
3143         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3144                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3145                 /* 5701 {A0,B0} CRC bug workaround */
3146                 tg3_writephy(tp, 0x15, 0x0a75);
3147                 tg3_writephy(tp, 0x1c, 0x8c68);
3148                 tg3_writephy(tp, 0x1c, 0x8d68);
3149                 tg3_writephy(tp, 0x1c, 0x8c68);
3150         }
3151
3152         /* Clear pending interrupts... */
3153         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3154         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3155
3156         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3157                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3158         else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3159                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3160
3161         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3162             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3163                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3164                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3165                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3166                 else
3167                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3168         }
3169
3170         current_link_up = 0;
3171         current_speed = SPEED_INVALID;
3172         current_duplex = DUPLEX_INVALID;
3173
3174         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3175                 u32 val;
3176
3177                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3178                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3179                 if (!(val & (1 << 10))) {
3180                         val |= (1 << 10);
3181                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3182                         goto relink;
3183                 }
3184         }
3185
3186         bmsr = 0;
3187         for (i = 0; i < 100; i++) {
3188                 tg3_readphy(tp, MII_BMSR, &bmsr);
3189                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3190                     (bmsr & BMSR_LSTATUS))
3191                         break;
3192                 udelay(40);
3193         }
3194
3195         if (bmsr & BMSR_LSTATUS) {
3196                 u32 aux_stat, bmcr;
3197
3198                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3199                 for (i = 0; i < 2000; i++) {
3200                         udelay(10);
3201                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3202                             aux_stat)
3203                                 break;
3204                 }
3205
3206                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3207                                              &current_speed,
3208                                              &current_duplex);
3209
3210                 bmcr = 0;
3211                 for (i = 0; i < 200; i++) {
3212                         tg3_readphy(tp, MII_BMCR, &bmcr);
3213                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3214                                 continue;
3215                         if (bmcr && bmcr != 0x7fff)
3216                                 break;
3217                         udelay(10);
3218                 }
3219
3220                 lcl_adv = 0;
3221                 rmt_adv = 0;
3222
3223                 tp->link_config.active_speed = current_speed;
3224                 tp->link_config.active_duplex = current_duplex;
3225
3226                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3227                         if ((bmcr & BMCR_ANENABLE) &&
3228                             tg3_copper_is_advertising_all(tp,
3229                                                 tp->link_config.advertising)) {
3230                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3231                                                                   &rmt_adv))
3232                                         current_link_up = 1;
3233                         }
3234                 } else {
3235                         if (!(bmcr & BMCR_ANENABLE) &&
3236                             tp->link_config.speed == current_speed &&
3237                             tp->link_config.duplex == current_duplex &&
3238                             tp->link_config.flowctrl ==
3239                             tp->link_config.active_flowctrl) {
3240                                 current_link_up = 1;
3241                         }
3242                 }
3243
3244                 if (current_link_up == 1 &&
3245                     tp->link_config.active_duplex == DUPLEX_FULL)
3246                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3247         }
3248
3249 relink:
3250         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3251                 u32 tmp;
3252
3253                 tg3_phy_copper_begin(tp);
3254
3255                 tg3_readphy(tp, MII_BMSR, &tmp);
3256                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3257                     (tmp & BMSR_LSTATUS))
3258                         current_link_up = 1;
3259         }
3260
3261         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3262         if (current_link_up == 1) {
3263                 if (tp->link_config.active_speed == SPEED_100 ||
3264                     tp->link_config.active_speed == SPEED_10)
3265                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3266                 else
3267                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3268         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3269                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3270         else
3271                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3272
3273         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3274         if (tp->link_config.active_duplex == DUPLEX_HALF)
3275                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3276
3277         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3278                 if (current_link_up == 1 &&
3279                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3280                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3281                 else
3282                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3283         }
3284
3285         /* ??? Without this setting Netgear GA302T PHY does not
3286          * ??? send/receive packets...
3287          */
3288         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3289             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3290                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3291                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3292                 udelay(80);
3293         }
3294
3295         tw32_f(MAC_MODE, tp->mac_mode);
3296         udelay(40);
3297
3298         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3299                 /* Polled via timer. */
3300                 tw32_f(MAC_EVENT, 0);
3301         } else {
3302                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3303         }
3304         udelay(40);
3305
3306         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3307             current_link_up == 1 &&
3308             tp->link_config.active_speed == SPEED_1000 &&
3309             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3310              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3311                 udelay(120);
3312                 tw32_f(MAC_STATUS,
3313                      (MAC_STATUS_SYNC_CHANGED |
3314                       MAC_STATUS_CFG_CHANGED));
3315                 udelay(40);
3316                 tg3_write_mem(tp,
3317                               NIC_SRAM_FIRMWARE_MBOX,
3318                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3319         }
3320
3321         /* Prevent send BD corruption. */
3322         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3323                 u16 oldlnkctl, newlnkctl;
3324
3325                 pci_read_config_word(tp->pdev,
3326                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3327                                      &oldlnkctl);
3328                 if (tp->link_config.active_speed == SPEED_100 ||
3329                     tp->link_config.active_speed == SPEED_10)
3330                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3331                 else
3332                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3333                 if (newlnkctl != oldlnkctl)
3334                         pci_write_config_word(tp->pdev,
3335                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3336                                               newlnkctl);
3337         }
3338
3339         if (current_link_up != netif_carrier_ok(tp->dev)) {
3340                 if (current_link_up)
3341                         netif_carrier_on(tp->dev);
3342                 else
3343                         netif_carrier_off(tp->dev);
3344                 tg3_link_report(tp);
3345         }
3346
3347         return 0;
3348 }
3349
3350 struct tg3_fiber_aneginfo {
3351         int state;
3352 #define ANEG_STATE_UNKNOWN              0
3353 #define ANEG_STATE_AN_ENABLE            1
3354 #define ANEG_STATE_RESTART_INIT         2
3355 #define ANEG_STATE_RESTART              3
3356 #define ANEG_STATE_DISABLE_LINK_OK      4
3357 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3358 #define ANEG_STATE_ABILITY_DETECT       6
3359 #define ANEG_STATE_ACK_DETECT_INIT      7
3360 #define ANEG_STATE_ACK_DETECT           8
3361 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3362 #define ANEG_STATE_COMPLETE_ACK         10
3363 #define ANEG_STATE_IDLE_DETECT_INIT     11
3364 #define ANEG_STATE_IDLE_DETECT          12
3365 #define ANEG_STATE_LINK_OK              13
3366 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3367 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3368
3369         u32 flags;
3370 #define MR_AN_ENABLE            0x00000001
3371 #define MR_RESTART_AN           0x00000002
3372 #define MR_AN_COMPLETE          0x00000004
3373 #define MR_PAGE_RX              0x00000008
3374 #define MR_NP_LOADED            0x00000010
3375 #define MR_TOGGLE_TX            0x00000020
3376 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3377 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3378 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3379 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3380 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3381 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3382 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3383 #define MR_TOGGLE_RX            0x00002000
3384 #define MR_NP_RX                0x00004000
3385
3386 #define MR_LINK_OK              0x80000000
3387
3388         unsigned long link_time, cur_time;
3389
3390         u32 ability_match_cfg;
3391         int ability_match_count;
3392
3393         char ability_match, idle_match, ack_match;
3394
3395         u32 txconfig, rxconfig;
3396 #define ANEG_CFG_NP             0x00000080
3397 #define ANEG_CFG_ACK            0x00000040
3398 #define ANEG_CFG_RF2            0x00000020
3399 #define ANEG_CFG_RF1            0x00000010
3400 #define ANEG_CFG_PS2            0x00000001
3401 #define ANEG_CFG_PS1            0x00008000
3402 #define ANEG_CFG_HD             0x00004000
3403 #define ANEG_CFG_FD             0x00002000
3404 #define ANEG_CFG_INVAL          0x00001f06
3405
3406 };
3407 #define ANEG_OK         0
3408 #define ANEG_DONE       1
3409 #define ANEG_TIMER_ENAB 2
3410 #define ANEG_FAILED     -1
3411
3412 #define ANEG_STATE_SETTLE_TIME  10000
3413
3414 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3415                                    struct tg3_fiber_aneginfo *ap)
3416 {
3417         u16 flowctrl;
3418         unsigned long delta;
3419         u32 rx_cfg_reg;
3420         int ret;
3421
3422         if (ap->state == ANEG_STATE_UNKNOWN) {
3423                 ap->rxconfig = 0;
3424                 ap->link_time = 0;
3425                 ap->cur_time = 0;
3426                 ap->ability_match_cfg = 0;
3427                 ap->ability_match_count = 0;
3428                 ap->ability_match = 0;
3429                 ap->idle_match = 0;
3430                 ap->ack_match = 0;
3431         }
3432         ap->cur_time++;
3433
3434         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3435                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3436
3437                 if (rx_cfg_reg != ap->ability_match_cfg) {
3438                         ap->ability_match_cfg = rx_cfg_reg;
3439                         ap->ability_match = 0;
3440                         ap->ability_match_count = 0;
3441                 } else {
3442                         if (++ap->ability_match_count > 1) {
3443                                 ap->ability_match = 1;
3444                                 ap->ability_match_cfg = rx_cfg_reg;
3445                         }
3446                 }
3447                 if (rx_cfg_reg & ANEG_CFG_ACK)
3448                         ap->ack_match = 1;
3449                 else
3450                         ap->ack_match = 0;
3451
3452                 ap->idle_match = 0;
3453         } else {
3454                 ap->idle_match = 1;
3455                 ap->ability_match_cfg = 0;
3456                 ap->ability_match_count = 0;
3457                 ap->ability_match = 0;
3458                 ap->ack_match = 0;
3459
3460                 rx_cfg_reg = 0;
3461         }
3462
3463         ap->rxconfig = rx_cfg_reg;
3464         ret = ANEG_OK;
3465
3466         switch (ap->state) {
3467         case ANEG_STATE_UNKNOWN:
3468                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3469                         ap->state = ANEG_STATE_AN_ENABLE;
3470
3471                 /* fallthru */
3472         case ANEG_STATE_AN_ENABLE:
3473                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3474                 if (ap->flags & MR_AN_ENABLE) {
3475                         ap->link_time = 0;
3476                         ap->cur_time = 0;
3477                         ap->ability_match_cfg = 0;
3478                         ap->ability_match_count = 0;
3479                         ap->ability_match = 0;
3480                         ap->idle_match = 0;
3481                         ap->ack_match = 0;
3482
3483                         ap->state = ANEG_STATE_RESTART_INIT;
3484                 } else {
3485                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3486                 }
3487                 break;
3488
3489         case ANEG_STATE_RESTART_INIT:
3490                 ap->link_time = ap->cur_time;
3491                 ap->flags &= ~(MR_NP_LOADED);
3492                 ap->txconfig = 0;
3493                 tw32(MAC_TX_AUTO_NEG, 0);
3494                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3495                 tw32_f(MAC_MODE, tp->mac_mode);
3496                 udelay(40);
3497
3498                 ret = ANEG_TIMER_ENAB;
3499                 ap->state = ANEG_STATE_RESTART;
3500
3501                 /* fallthru */
3502         case ANEG_STATE_RESTART:
3503                 delta = ap->cur_time - ap->link_time;
3504                 if (delta > ANEG_STATE_SETTLE_TIME)
3505                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3506                 else
3507                         ret = ANEG_TIMER_ENAB;
3508                 break;
3509
3510         case ANEG_STATE_DISABLE_LINK_OK:
3511                 ret = ANEG_DONE;
3512                 break;
3513
3514         case ANEG_STATE_ABILITY_DETECT_INIT:
3515                 ap->flags &= ~(MR_TOGGLE_TX);
3516                 ap->txconfig = ANEG_CFG_FD;
3517                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3518                 if (flowctrl & ADVERTISE_1000XPAUSE)
3519                         ap->txconfig |= ANEG_CFG_PS1;
3520                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3521                         ap->txconfig |= ANEG_CFG_PS2;
3522                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3523                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3524                 tw32_f(MAC_MODE, tp->mac_mode);
3525                 udelay(40);
3526
3527                 ap->state = ANEG_STATE_ABILITY_DETECT;
3528                 break;
3529
3530         case ANEG_STATE_ABILITY_DETECT:
3531                 if (ap->ability_match != 0 && ap->rxconfig != 0)
3532                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3533                 break;
3534
3535         case ANEG_STATE_ACK_DETECT_INIT:
3536                 ap->txconfig |= ANEG_CFG_ACK;
3537                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3538                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3539                 tw32_f(MAC_MODE, tp->mac_mode);
3540                 udelay(40);
3541
3542                 ap->state = ANEG_STATE_ACK_DETECT;
3543
3544                 /* fallthru */
3545         case ANEG_STATE_ACK_DETECT:
3546                 if (ap->ack_match != 0) {
3547                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3548                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3549                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3550                         } else {
3551                                 ap->state = ANEG_STATE_AN_ENABLE;
3552                         }
3553                 } else if (ap->ability_match != 0 &&
3554                            ap->rxconfig == 0) {
3555                         ap->state = ANEG_STATE_AN_ENABLE;
3556                 }
3557                 break;
3558
3559         case ANEG_STATE_COMPLETE_ACK_INIT:
3560                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3561                         ret = ANEG_FAILED;
3562                         break;
3563                 }
3564                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3565                                MR_LP_ADV_HALF_DUPLEX |
3566                                MR_LP_ADV_SYM_PAUSE |
3567                                MR_LP_ADV_ASYM_PAUSE |
3568                                MR_LP_ADV_REMOTE_FAULT1 |
3569                                MR_LP_ADV_REMOTE_FAULT2 |
3570                                MR_LP_ADV_NEXT_PAGE |
3571                                MR_TOGGLE_RX |
3572                                MR_NP_RX);
3573                 if (ap->rxconfig & ANEG_CFG_FD)
3574                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3575                 if (ap->rxconfig & ANEG_CFG_HD)
3576                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3577                 if (ap->rxconfig & ANEG_CFG_PS1)
3578                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3579                 if (ap->rxconfig & ANEG_CFG_PS2)
3580                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3581                 if (ap->rxconfig & ANEG_CFG_RF1)
3582                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3583                 if (ap->rxconfig & ANEG_CFG_RF2)
3584                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3585                 if (ap->rxconfig & ANEG_CFG_NP)
3586                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3587
3588                 ap->link_time = ap->cur_time;
3589
3590                 ap->flags ^= (MR_TOGGLE_TX);
3591                 if (ap->rxconfig & 0x0008)
3592                         ap->flags |= MR_TOGGLE_RX;
3593                 if (ap->rxconfig & ANEG_CFG_NP)
3594                         ap->flags |= MR_NP_RX;
3595                 ap->flags |= MR_PAGE_RX;
3596
3597                 ap->state = ANEG_STATE_COMPLETE_ACK;
3598                 ret = ANEG_TIMER_ENAB;
3599                 break;
3600
3601         case ANEG_STATE_COMPLETE_ACK:
3602                 if (ap->ability_match != 0 &&
3603                     ap->rxconfig == 0) {
3604                         ap->state = ANEG_STATE_AN_ENABLE;
3605                         break;
3606                 }
3607                 delta = ap->cur_time - ap->link_time;
3608                 if (delta > ANEG_STATE_SETTLE_TIME) {
3609                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3610                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3611                         } else {
3612                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3613                                     !(ap->flags & MR_NP_RX)) {
3614                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3615                                 } else {
3616                                         ret = ANEG_FAILED;
3617                                 }
3618                         }
3619                 }
3620                 break;
3621
3622         case ANEG_STATE_IDLE_DETECT_INIT:
3623                 ap->link_time = ap->cur_time;
3624                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3625                 tw32_f(MAC_MODE, tp->mac_mode);
3626                 udelay(40);
3627
3628                 ap->state = ANEG_STATE_IDLE_DETECT;
3629                 ret = ANEG_TIMER_ENAB;
3630                 break;
3631
3632         case ANEG_STATE_IDLE_DETECT:
3633                 if (ap->ability_match != 0 &&
3634                     ap->rxconfig == 0) {
3635                         ap->state = ANEG_STATE_AN_ENABLE;
3636                         break;
3637                 }
3638                 delta = ap->cur_time - ap->link_time;
3639                 if (delta > ANEG_STATE_SETTLE_TIME) {
3640                         /* XXX another gem from the Broadcom driver :( */
3641                         ap->state = ANEG_STATE_LINK_OK;
3642                 }
3643                 break;
3644
3645         case ANEG_STATE_LINK_OK:
3646                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3647                 ret = ANEG_DONE;
3648                 break;
3649
3650         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3651                 /* ??? unimplemented */
3652                 break;
3653
3654         case ANEG_STATE_NEXT_PAGE_WAIT:
3655                 /* ??? unimplemented */
3656                 break;
3657
3658         default:
3659                 ret = ANEG_FAILED;
3660                 break;
3661         }
3662
3663         return ret;
3664 }
3665
3666 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3667 {
3668         int res = 0;
3669         struct tg3_fiber_aneginfo aninfo;
3670         int status = ANEG_FAILED;
3671         unsigned int tick;
3672         u32 tmp;
3673
3674         tw32_f(MAC_TX_AUTO_NEG, 0);
3675
3676         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3677         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3678         udelay(40);
3679
3680         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3681         udelay(40);
3682
3683         memset(&aninfo, 0, sizeof(aninfo));
3684         aninfo.flags |= MR_AN_ENABLE;
3685         aninfo.state = ANEG_STATE_UNKNOWN;
3686         aninfo.cur_time = 0;
3687         tick = 0;
3688         while (++tick < 195000) {
3689                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3690                 if (status == ANEG_DONE || status == ANEG_FAILED)
3691                         break;
3692
3693                 udelay(1);
3694         }
3695
3696         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3697         tw32_f(MAC_MODE, tp->mac_mode);
3698         udelay(40);
3699
3700         *txflags = aninfo.txconfig;
3701         *rxflags = aninfo.flags;
3702
3703         if (status == ANEG_DONE &&
3704             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3705                              MR_LP_ADV_FULL_DUPLEX)))
3706                 res = 1;
3707
3708         return res;
3709 }
3710
3711 static void tg3_init_bcm8002(struct tg3 *tp)
3712 {
3713         u32 mac_status = tr32(MAC_STATUS);
3714         int i;
3715
3716         /* Reset when initting first time or we have a link. */
3717         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3718             !(mac_status & MAC_STATUS_PCS_SYNCED))
3719                 return;
3720
3721         /* Set PLL lock range. */
3722         tg3_writephy(tp, 0x16, 0x8007);
3723
3724         /* SW reset */
3725         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3726
3727         /* Wait for reset to complete. */
3728         /* XXX schedule_timeout() ... */
3729         for (i = 0; i < 500; i++)
3730                 udelay(10);
3731
3732         /* Config mode; select PMA/Ch 1 regs. */
3733         tg3_writephy(tp, 0x10, 0x8411);
3734
3735         /* Enable auto-lock and comdet, select txclk for tx. */
3736         tg3_writephy(tp, 0x11, 0x0a10);
3737
3738         tg3_writephy(tp, 0x18, 0x00a0);
3739         tg3_writephy(tp, 0x16, 0x41ff);
3740
3741         /* Assert and deassert POR. */
3742         tg3_writephy(tp, 0x13, 0x0400);
3743         udelay(40);
3744         tg3_writephy(tp, 0x13, 0x0000);
3745
3746         tg3_writephy(tp, 0x11, 0x0a50);
3747         udelay(40);
3748         tg3_writephy(tp, 0x11, 0x0a10);
3749
3750         /* Wait for signal to stabilize */
3751         /* XXX schedule_timeout() ... */
3752         for (i = 0; i < 15000; i++)
3753                 udelay(10);
3754
3755         /* Deselect the channel register so we can read the PHYID
3756          * later.
3757          */
3758         tg3_writephy(tp, 0x10, 0x8011);
3759 }
3760
3761 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3762 {
3763         u16 flowctrl;
3764         u32 sg_dig_ctrl, sg_dig_status;
3765         u32 serdes_cfg, expected_sg_dig_ctrl;
3766         int workaround, port_a;
3767         int current_link_up;
3768
3769         serdes_cfg = 0;
3770         expected_sg_dig_ctrl = 0;
3771         workaround = 0;
3772         port_a = 1;
3773         current_link_up = 0;
3774
3775         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3776             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3777                 workaround = 1;
3778                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3779                         port_a = 0;
3780
3781                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3782                 /* preserve bits 20-23 for voltage regulator */
3783                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3784         }
3785
3786         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3787
3788         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3789                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3790                         if (workaround) {
3791                                 u32 val = serdes_cfg;
3792
3793                                 if (port_a)
3794                                         val |= 0xc010000;
3795                                 else
3796                                         val |= 0x4010000;
3797                                 tw32_f(MAC_SERDES_CFG, val);
3798                         }
3799
3800                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3801                 }
3802                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3803                         tg3_setup_flow_control(tp, 0, 0);
3804                         current_link_up = 1;
3805                 }
3806                 goto out;
3807         }
3808
3809         /* Want auto-negotiation.  */
3810         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3811
3812         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3813         if (flowctrl & ADVERTISE_1000XPAUSE)
3814                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3815         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3816                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3817
3818         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3819                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3820                     tp->serdes_counter &&
3821                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3822                                     MAC_STATUS_RCVD_CFG)) ==
3823                      MAC_STATUS_PCS_SYNCED)) {
3824                         tp->serdes_counter--;
3825                         current_link_up = 1;
3826                         goto out;
3827                 }
3828 restart_autoneg:
3829                 if (workaround)
3830                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3831                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3832                 udelay(5);
3833                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3834
3835                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3836                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3837         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3838                                  MAC_STATUS_SIGNAL_DET)) {
3839                 sg_dig_status = tr32(SG_DIG_STATUS);
3840                 mac_status = tr32(MAC_STATUS);
3841
3842                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3843                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3844                         u32 local_adv = 0, remote_adv = 0;
3845
3846                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3847                                 local_adv |= ADVERTISE_1000XPAUSE;
3848                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3849                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3850
3851                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3852                                 remote_adv |= LPA_1000XPAUSE;
3853                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3854                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3855
3856                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3857                         current_link_up = 1;
3858                         tp->serdes_counter = 0;
3859                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3860                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3861                         if (tp->serdes_counter)
3862                                 tp->serdes_counter--;
3863                         else {
3864                                 if (workaround) {
3865                                         u32 val = serdes_cfg;
3866
3867                                         if (port_a)
3868                                                 val |= 0xc010000;
3869                                         else
3870                                                 val |= 0x4010000;
3871
3872                                         tw32_f(MAC_SERDES_CFG, val);
3873                                 }
3874
3875                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3876                                 udelay(40);
3877
3878                                 /* Link parallel detection - link is up */
3879                                 /* only if we have PCS_SYNC and not */
3880                                 /* receiving config code words */
3881                                 mac_status = tr32(MAC_STATUS);
3882                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3883                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3884                                         tg3_setup_flow_control(tp, 0, 0);
3885                                         current_link_up = 1;
3886                                         tp->tg3_flags2 |=
3887                                                 TG3_FLG2_PARALLEL_DETECT;
3888                                         tp->serdes_counter =
3889                                                 SERDES_PARALLEL_DET_TIMEOUT;
3890                                 } else
3891                                         goto restart_autoneg;
3892                         }
3893                 }
3894         } else {
3895                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3896                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3897         }
3898
3899 out:
3900         return current_link_up;
3901 }
3902
3903 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3904 {
3905         int current_link_up = 0;
3906
3907         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3908                 goto out;
3909
3910         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3911                 u32 txflags, rxflags;
3912                 int i;
3913
3914                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3915                         u32 local_adv = 0, remote_adv = 0;
3916
3917                         if (txflags & ANEG_CFG_PS1)
3918                                 local_adv |= ADVERTISE_1000XPAUSE;
3919                         if (txflags & ANEG_CFG_PS2)
3920                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3921
3922                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3923                                 remote_adv |= LPA_1000XPAUSE;
3924                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3925                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3926
3927                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3928
3929                         current_link_up = 1;
3930                 }
3931                 for (i = 0; i < 30; i++) {
3932                         udelay(20);
3933                         tw32_f(MAC_STATUS,
3934                                (MAC_STATUS_SYNC_CHANGED |
3935                                 MAC_STATUS_CFG_CHANGED));
3936                         udelay(40);
3937                         if ((tr32(MAC_STATUS) &
3938                              (MAC_STATUS_SYNC_CHANGED |
3939                               MAC_STATUS_CFG_CHANGED)) == 0)
3940                                 break;
3941                 }
3942
3943                 mac_status = tr32(MAC_STATUS);
3944                 if (current_link_up == 0 &&
3945                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3946                     !(mac_status & MAC_STATUS_RCVD_CFG))
3947                         current_link_up = 1;
3948         } else {
3949                 tg3_setup_flow_control(tp, 0, 0);
3950
3951                 /* Forcing 1000FD link up. */
3952                 current_link_up = 1;
3953
3954                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3955                 udelay(40);
3956
3957                 tw32_f(MAC_MODE, tp->mac_mode);
3958                 udelay(40);
3959         }
3960
3961 out:
3962         return current_link_up;
3963 }
3964
3965 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3966 {
3967         u32 orig_pause_cfg;
3968         u16 orig_active_speed;
3969         u8 orig_active_duplex;
3970         u32 mac_status;
3971         int current_link_up;
3972         int i;
3973
3974         orig_pause_cfg = tp->link_config.active_flowctrl;
3975         orig_active_speed = tp->link_config.active_speed;
3976         orig_active_duplex = tp->link_config.active_duplex;
3977
3978         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3979             netif_carrier_ok(tp->dev) &&
3980             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3981                 mac_status = tr32(MAC_STATUS);
3982                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3983                                MAC_STATUS_SIGNAL_DET |
3984                                MAC_STATUS_CFG_CHANGED |
3985                                MAC_STATUS_RCVD_CFG);
3986                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3987                                    MAC_STATUS_SIGNAL_DET)) {
3988                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3989                                             MAC_STATUS_CFG_CHANGED));
3990                         return 0;
3991                 }
3992         }
3993
3994         tw32_f(MAC_TX_AUTO_NEG, 0);
3995
3996         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3997         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3998         tw32_f(MAC_MODE, tp->mac_mode);
3999         udelay(40);
4000
4001         if (tp->phy_id == TG3_PHY_ID_BCM8002)
4002                 tg3_init_bcm8002(tp);
4003
4004         /* Enable link change event even when serdes polling.  */
4005         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4006         udelay(40);
4007
4008         current_link_up = 0;
4009         mac_status = tr32(MAC_STATUS);
4010
4011         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
4012                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4013         else
4014                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4015
4016         tp->napi[0].hw_status->status =
4017                 (SD_STATUS_UPDATED |
4018                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4019
4020         for (i = 0; i < 100; i++) {
4021                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4022                                     MAC_STATUS_CFG_CHANGED));
4023                 udelay(5);
4024                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4025                                          MAC_STATUS_CFG_CHANGED |
4026                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4027                         break;
4028         }
4029
4030         mac_status = tr32(MAC_STATUS);
4031         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4032                 current_link_up = 0;
4033                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4034                     tp->serdes_counter == 0) {
4035                         tw32_f(MAC_MODE, (tp->mac_mode |
4036                                           MAC_MODE_SEND_CONFIGS));
4037                         udelay(1);
4038                         tw32_f(MAC_MODE, tp->mac_mode);
4039                 }
4040         }
4041
4042         if (current_link_up == 1) {
4043                 tp->link_config.active_speed = SPEED_1000;
4044                 tp->link_config.active_duplex = DUPLEX_FULL;
4045                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4046                                     LED_CTRL_LNKLED_OVERRIDE |
4047                                     LED_CTRL_1000MBPS_ON));
4048         } else {
4049                 tp->link_config.active_speed = SPEED_INVALID;
4050                 tp->link_config.active_duplex = DUPLEX_INVALID;
4051                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4052                                     LED_CTRL_LNKLED_OVERRIDE |
4053                                     LED_CTRL_TRAFFIC_OVERRIDE));
4054         }
4055
4056         if (current_link_up != netif_carrier_ok(tp->dev)) {
4057                 if (current_link_up)
4058                         netif_carrier_on(tp->dev);
4059                 else
4060                         netif_carrier_off(tp->dev);
4061                 tg3_link_report(tp);
4062         } else {
4063                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4064                 if (orig_pause_cfg != now_pause_cfg ||
4065                     orig_active_speed != tp->link_config.active_speed ||
4066                     orig_active_duplex != tp->link_config.active_duplex)
4067                         tg3_link_report(tp);
4068         }
4069
4070         return 0;
4071 }
4072
4073 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4074 {
4075         int current_link_up, err = 0;
4076         u32 bmsr, bmcr;
4077         u16 current_speed;
4078         u8 current_duplex;
4079         u32 local_adv, remote_adv;
4080
4081         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4082         tw32_f(MAC_MODE, tp->mac_mode);
4083         udelay(40);
4084
4085         tw32(MAC_EVENT, 0);
4086
4087         tw32_f(MAC_STATUS,
4088              (MAC_STATUS_SYNC_CHANGED |
4089               MAC_STATUS_CFG_CHANGED |
4090               MAC_STATUS_MI_COMPLETION |
4091               MAC_STATUS_LNKSTATE_CHANGED));
4092         udelay(40);
4093
4094         if (force_reset)
4095                 tg3_phy_reset(tp);
4096
4097         current_link_up = 0;
4098         current_speed = SPEED_INVALID;
4099         current_duplex = DUPLEX_INVALID;
4100
4101         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4102         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4103         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4104                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4105                         bmsr |= BMSR_LSTATUS;
4106                 else
4107                         bmsr &= ~BMSR_LSTATUS;
4108         }
4109
4110         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4111
4112         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4113             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4114                 /* do nothing, just check for link up at the end */
4115         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4116                 u32 adv, new_adv;
4117
4118                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4119                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4120                                   ADVERTISE_1000XPAUSE |
4121                                   ADVERTISE_1000XPSE_ASYM |
4122                                   ADVERTISE_SLCT);
4123
4124                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4125
4126                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4127                         new_adv |= ADVERTISE_1000XHALF;
4128                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4129                         new_adv |= ADVERTISE_1000XFULL;
4130
4131                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4132                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4133                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4134                         tg3_writephy(tp, MII_BMCR, bmcr);
4135
4136                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4137                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4138                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4139
4140                         return err;
4141                 }
4142         } else {
4143                 u32 new_bmcr;
4144
4145                 bmcr &= ~BMCR_SPEED1000;
4146                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4147
4148                 if (tp->link_config.duplex == DUPLEX_FULL)
4149                         new_bmcr |= BMCR_FULLDPLX;
4150
4151                 if (new_bmcr != bmcr) {
4152                         /* BMCR_SPEED1000 is a reserved bit that needs
4153                          * to be set on write.
4154                          */
4155                         new_bmcr |= BMCR_SPEED1000;
4156
4157                         /* Force a linkdown */
4158                         if (netif_carrier_ok(tp->dev)) {
4159                                 u32 adv;
4160
4161                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4162                                 adv &= ~(ADVERTISE_1000XFULL |
4163                                          ADVERTISE_1000XHALF |
4164                                          ADVERTISE_SLCT);
4165                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4166                                 tg3_writephy(tp, MII_BMCR, bmcr |
4167                                                            BMCR_ANRESTART |
4168                                                            BMCR_ANENABLE);
4169                                 udelay(10);
4170                                 netif_carrier_off(tp->dev);
4171                         }
4172                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4173                         bmcr = new_bmcr;
4174                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4175                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4176                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4177                             ASIC_REV_5714) {
4178                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4179                                         bmsr |= BMSR_LSTATUS;
4180                                 else
4181                                         bmsr &= ~BMSR_LSTATUS;
4182                         }
4183                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4184                 }
4185         }
4186
4187         if (bmsr & BMSR_LSTATUS) {
4188                 current_speed = SPEED_1000;
4189                 current_link_up = 1;
4190                 if (bmcr & BMCR_FULLDPLX)
4191                         current_duplex = DUPLEX_FULL;
4192                 else
4193                         current_duplex = DUPLEX_HALF;
4194
4195                 local_adv = 0;
4196                 remote_adv = 0;
4197
4198                 if (bmcr & BMCR_ANENABLE) {
4199                         u32 common;
4200
4201                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4202                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4203                         common = local_adv & remote_adv;
4204                         if (common & (ADVERTISE_1000XHALF |
4205                                       ADVERTISE_1000XFULL)) {
4206                                 if (common & ADVERTISE_1000XFULL)
4207                                         current_duplex = DUPLEX_FULL;
4208                                 else
4209                                         current_duplex = DUPLEX_HALF;
4210                         } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4211                                 /* Link is up via parallel detect */
4212                         } else {
4213                                 current_link_up = 0;
4214                         }
4215                 }
4216         }
4217
4218         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4219                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4220
4221         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4222         if (tp->link_config.active_duplex == DUPLEX_HALF)
4223                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4224
4225         tw32_f(MAC_MODE, tp->mac_mode);
4226         udelay(40);
4227
4228         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4229
4230         tp->link_config.active_speed = current_speed;
4231         tp->link_config.active_duplex = current_duplex;
4232
4233         if (current_link_up != netif_carrier_ok(tp->dev)) {
4234                 if (current_link_up)
4235                         netif_carrier_on(tp->dev);
4236                 else {
4237                         netif_carrier_off(tp->dev);
4238                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4239                 }
4240                 tg3_link_report(tp);
4241         }
4242         return err;
4243 }
4244
4245 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4246 {
4247         if (tp->serdes_counter) {
4248                 /* Give autoneg time to complete. */
4249                 tp->serdes_counter--;
4250                 return;
4251         }
4252
4253         if (!netif_carrier_ok(tp->dev) &&
4254             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4255                 u32 bmcr;
4256
4257                 tg3_readphy(tp, MII_BMCR, &bmcr);
4258                 if (bmcr & BMCR_ANENABLE) {
4259                         u32 phy1, phy2;
4260
4261                         /* Select shadow register 0x1f */
4262                         tg3_writephy(tp, 0x1c, 0x7c00);
4263                         tg3_readphy(tp, 0x1c, &phy1);
4264
4265                         /* Select expansion interrupt status register */
4266                         tg3_writephy(tp, 0x17, 0x0f01);
4267                         tg3_readphy(tp, 0x15, &phy2);
4268                         tg3_readphy(tp, 0x15, &phy2);
4269
4270                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4271                                 /* We have signal detect and not receiving
4272                                  * config code words, link is up by parallel
4273                                  * detection.
4274                                  */
4275
4276                                 bmcr &= ~BMCR_ANENABLE;
4277                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4278                                 tg3_writephy(tp, MII_BMCR, bmcr);
4279                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4280                         }
4281                 }
4282         } else if (netif_carrier_ok(tp->dev) &&
4283                    (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4284                    (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4285                 u32 phy2;
4286
4287                 /* Select expansion interrupt status register */
4288                 tg3_writephy(tp, 0x17, 0x0f01);
4289                 tg3_readphy(tp, 0x15, &phy2);
4290                 if (phy2 & 0x20) {
4291                         u32 bmcr;
4292
4293                         /* Config code words received, turn on autoneg. */
4294                         tg3_readphy(tp, MII_BMCR, &bmcr);
4295                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4296
4297                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4298
4299                 }
4300         }
4301 }
4302
4303 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4304 {
4305         int err;
4306
4307         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
4308                 err = tg3_setup_fiber_phy(tp, force_reset);
4309         else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
4310                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4311         else
4312                 err = tg3_setup_copper_phy(tp, force_reset);
4313
4314         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4315                 u32 val, scale;
4316
4317                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4318                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4319                         scale = 65;
4320                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4321                         scale = 6;
4322                 else
4323                         scale = 12;
4324
4325                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4326                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4327                 tw32(GRC_MISC_CFG, val);
4328         }
4329
4330         if (tp->link_config.active_speed == SPEED_1000 &&
4331             tp->link_config.active_duplex == DUPLEX_HALF)
4332                 tw32(MAC_TX_LENGTHS,
4333                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4334                       (6 << TX_LENGTHS_IPG_SHIFT) |
4335                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4336         else
4337                 tw32(MAC_TX_LENGTHS,
4338                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4339                       (6 << TX_LENGTHS_IPG_SHIFT) |
4340                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4341
4342         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4343                 if (netif_carrier_ok(tp->dev)) {
4344                         tw32(HOSTCC_STAT_COAL_TICKS,
4345                              tp->coal.stats_block_coalesce_usecs);
4346                 } else {
4347                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4348                 }
4349         }
4350
4351         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4352                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4353                 if (!netif_carrier_ok(tp->dev))
4354                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4355                               tp->pwrmgmt_thresh;
4356                 else
4357                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4358                 tw32(PCIE_PWR_MGMT_THRESH, val);
4359         }
4360
4361         return err;
4362 }
4363
4364 /* This is called whenever we suspect that the system chipset is re-
4365  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4366  * is bogus tx completions. We try to recover by setting the
4367  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4368  * in the workqueue.
4369  */
4370 static void tg3_tx_recover(struct tg3 *tp)
4371 {
4372         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4373                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4374
4375         netdev_warn(tp->dev,
4376                     "The system may be re-ordering memory-mapped I/O "
4377                     "cycles to the network device, attempting to recover. "
4378                     "Please report the problem to the driver maintainer "
4379                     "and include system chipset information.\n");
4380
4381         spin_lock(&tp->lock);
4382         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4383         spin_unlock(&tp->lock);
4384 }
4385
4386 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4387 {
4388         smp_mb();
4389         return tnapi->tx_pending -
4390                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4391 }
4392
4393 /* Tigon3 never reports partial packet sends.  So we do not
4394  * need special logic to handle SKBs that have not had all
4395  * of their frags sent yet, like SunGEM does.
4396  */
4397 static void tg3_tx(struct tg3_napi *tnapi)
4398 {
4399         struct tg3 *tp = tnapi->tp;
4400         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4401         u32 sw_idx = tnapi->tx_cons;
4402         struct netdev_queue *txq;
4403         int index = tnapi - tp->napi;
4404
4405         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4406                 index--;
4407
4408         txq = netdev_get_tx_queue(tp->dev, index);
4409
4410         while (sw_idx != hw_idx) {
4411                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4412                 struct sk_buff *skb = ri->skb;
4413                 int i, tx_bug = 0;
4414
4415                 if (unlikely(skb == NULL)) {
4416                         tg3_tx_recover(tp);
4417                         return;
4418                 }
4419
4420                 pci_unmap_single(tp->pdev,
4421                                  dma_unmap_addr(ri, mapping),
4422                                  skb_headlen(skb),
4423                                  PCI_DMA_TODEVICE);
4424
4425                 ri->skb = NULL;
4426
4427                 sw_idx = NEXT_TX(sw_idx);
4428
4429                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4430                         ri = &tnapi->tx_buffers[sw_idx];
4431                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4432                                 tx_bug = 1;
4433
4434                         pci_unmap_page(tp->pdev,
4435                                        dma_unmap_addr(ri, mapping),
4436                                        skb_shinfo(skb)->frags[i].size,
4437                                        PCI_DMA_TODEVICE);
4438                         sw_idx = NEXT_TX(sw_idx);
4439                 }
4440
4441                 dev_kfree_skb(skb);
4442
4443                 if (unlikely(tx_bug)) {
4444                         tg3_tx_recover(tp);
4445                         return;
4446                 }
4447         }
4448
4449         tnapi->tx_cons = sw_idx;
4450
4451         /* Need to make the tx_cons update visible to tg3_start_xmit()
4452          * before checking for netif_queue_stopped().  Without the
4453          * memory barrier, there is a small possibility that tg3_start_xmit()
4454          * will miss it and cause the queue to be stopped forever.
4455          */
4456         smp_mb();
4457
4458         if (unlikely(netif_tx_queue_stopped(txq) &&
4459                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4460                 __netif_tx_lock(txq, smp_processor_id());
4461                 if (netif_tx_queue_stopped(txq) &&
4462                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4463                         netif_tx_wake_queue(txq);
4464                 __netif_tx_unlock(txq);
4465         }
4466 }
4467
4468 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4469 {
4470         if (!ri->skb)
4471                 return;
4472
4473         pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4474                          map_sz, PCI_DMA_FROMDEVICE);
4475         dev_kfree_skb_any(ri->skb);
4476         ri->skb = NULL;
4477 }
4478
4479 /* Returns size of skb allocated or < 0 on error.
4480  *
4481  * We only need to fill in the address because the other members
4482  * of the RX descriptor are invariant, see tg3_init_rings.
4483  *
4484  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4485  * posting buffers we only dirty the first cache line of the RX
4486  * descriptor (containing the address).  Whereas for the RX status
4487  * buffers the cpu only reads the last cacheline of the RX descriptor
4488  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4489  */
4490 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4491                             u32 opaque_key, u32 dest_idx_unmasked)
4492 {
4493         struct tg3_rx_buffer_desc *desc;
4494         struct ring_info *map, *src_map;
4495         struct sk_buff *skb;
4496         dma_addr_t mapping;
4497         int skb_size, dest_idx;
4498
4499         src_map = NULL;
4500         switch (opaque_key) {
4501         case RXD_OPAQUE_RING_STD:
4502                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4503                 desc = &tpr->rx_std[dest_idx];
4504                 map = &tpr->rx_std_buffers[dest_idx];
4505                 skb_size = tp->rx_pkt_map_sz;
4506                 break;
4507
4508         case RXD_OPAQUE_RING_JUMBO:
4509                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4510                 desc = &tpr->rx_jmb[dest_idx].std;
4511                 map = &tpr->rx_jmb_buffers[dest_idx];
4512                 skb_size = TG3_RX_JMB_MAP_SZ;
4513                 break;
4514
4515         default:
4516                 return -EINVAL;
4517         }
4518
4519         /* Do not overwrite any of the map or rp information
4520          * until we are sure we can commit to a new buffer.
4521          *
4522          * Callers depend upon this behavior and assume that
4523          * we leave everything unchanged if we fail.
4524          */
4525         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4526         if (skb == NULL)
4527                 return -ENOMEM;
4528
4529         skb_reserve(skb, tp->rx_offset);
4530
4531         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4532                                  PCI_DMA_FROMDEVICE);
4533         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4534                 dev_kfree_skb(skb);
4535                 return -EIO;
4536         }
4537
4538         map->skb = skb;
4539         dma_unmap_addr_set(map, mapping, mapping);
4540
4541         desc->addr_hi = ((u64)mapping >> 32);
4542         desc->addr_lo = ((u64)mapping & 0xffffffff);
4543
4544         return skb_size;
4545 }
4546
4547 /* We only need to move over in the address because the other
4548  * members of the RX descriptor are invariant.  See notes above
4549  * tg3_alloc_rx_skb for full details.
4550  */
4551 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4552                            struct tg3_rx_prodring_set *dpr,
4553                            u32 opaque_key, int src_idx,
4554                            u32 dest_idx_unmasked)
4555 {
4556         struct tg3 *tp = tnapi->tp;
4557         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4558         struct ring_info *src_map, *dest_map;
4559         struct tg3_rx_prodring_set *spr = &tp->prodring[0];
4560         int dest_idx;
4561
4562         switch (opaque_key) {
4563         case RXD_OPAQUE_RING_STD:
4564                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4565                 dest_desc = &dpr->rx_std[dest_idx];
4566                 dest_map = &dpr->rx_std_buffers[dest_idx];
4567                 src_desc = &spr->rx_std[src_idx];
4568                 src_map = &spr->rx_std_buffers[src_idx];
4569                 break;
4570
4571         case RXD_OPAQUE_RING_JUMBO:
4572                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4573                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4574                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4575                 src_desc = &spr->rx_jmb[src_idx].std;
4576                 src_map = &spr->rx_jmb_buffers[src_idx];
4577                 break;
4578
4579         default:
4580                 return;
4581         }
4582
4583         dest_map->skb = src_map->skb;
4584         dma_unmap_addr_set(dest_map, mapping,
4585                            dma_unmap_addr(src_map, mapping));
4586         dest_desc->addr_hi = src_desc->addr_hi;
4587         dest_desc->addr_lo = src_desc->addr_lo;
4588
4589         /* Ensure that the update to the skb happens after the physical
4590          * addresses have been transferred to the new BD location.
4591          */
4592         smp_wmb();
4593
4594         src_map->skb = NULL;
4595 }
4596
4597 /* The RX ring scheme is composed of multiple rings which post fresh
4598  * buffers to the chip, and one special ring the chip uses to report
4599  * status back to the host.
4600  *
4601  * The special ring reports the status of received packets to the
4602  * host.  The chip does not write into the original descriptor the
4603  * RX buffer was obtained from.  The chip simply takes the original
4604  * descriptor as provided by the host, updates the status and length
4605  * field, then writes this into the next status ring entry.
4606  *
4607  * Each ring the host uses to post buffers to the chip is described
4608  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4609  * it is first placed into the on-chip ram.  When the packet's length
4610  * is known, it walks down the TG3_BDINFO entries to select the ring.
4611  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4612  * which is within the range of the new packet's length is chosen.
4613  *
4614  * The "separate ring for rx status" scheme may sound queer, but it makes
4615  * sense from a cache coherency perspective.  If only the host writes
4616  * to the buffer post rings, and only the chip writes to the rx status
4617  * rings, then cache lines never move beyond shared-modified state.
4618  * If both the host and chip were to write into the same ring, cache line
4619  * eviction could occur since both entities want it in an exclusive state.
4620  */
4621 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4622 {
4623         struct tg3 *tp = tnapi->tp;
4624         u32 work_mask, rx_std_posted = 0;
4625         u32 std_prod_idx, jmb_prod_idx;
4626         u32 sw_idx = tnapi->rx_rcb_ptr;
4627         u16 hw_idx;
4628         int received;
4629         struct tg3_rx_prodring_set *tpr = tnapi->prodring;
4630
4631         hw_idx = *(tnapi->rx_rcb_prod_idx);
4632         /*
4633          * We need to order the read of hw_idx and the read of
4634          * the opaque cookie.
4635          */
4636         rmb();
4637         work_mask = 0;
4638         received = 0;
4639         std_prod_idx = tpr->rx_std_prod_idx;
4640         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4641         while (sw_idx != hw_idx && budget > 0) {
4642                 struct ring_info *ri;
4643                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4644                 unsigned int len;
4645                 struct sk_buff *skb;
4646                 dma_addr_t dma_addr;
4647                 u32 opaque_key, desc_idx, *post_ptr;
4648                 bool hw_vlan __maybe_unused = false;
4649                 u16 vtag __maybe_unused = 0;
4650
4651                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4652                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4653                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4654                         ri = &tp->prodring[0].rx_std_buffers[desc_idx];
4655                         dma_addr = dma_unmap_addr(ri, mapping);
4656                         skb = ri->skb;
4657                         post_ptr = &std_prod_idx;
4658                         rx_std_posted++;
4659                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4660                         ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
4661                         dma_addr = dma_unmap_addr(ri, mapping);
4662                         skb = ri->skb;
4663                         post_ptr = &jmb_prod_idx;
4664                 } else
4665                         goto next_pkt_nopost;
4666
4667                 work_mask |= opaque_key;
4668
4669                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4670                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4671                 drop_it:
4672                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4673                                        desc_idx, *post_ptr);
4674                 drop_it_no_recycle:
4675                         /* Other statistics kept track of by card. */
4676                         tp->net_stats.rx_dropped++;
4677                         goto next_pkt;
4678                 }
4679
4680                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4681                       ETH_FCS_LEN;
4682
4683                 if (len > TG3_RX_COPY_THRESH(tp)) {
4684                         int skb_size;
4685
4686                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4687                                                     *post_ptr);
4688                         if (skb_size < 0)
4689                                 goto drop_it;
4690
4691                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4692                                          PCI_DMA_FROMDEVICE);
4693
4694                         /* Ensure that the update to the skb happens
4695                          * after the usage of the old DMA mapping.
4696                          */
4697                         smp_wmb();
4698
4699                         ri->skb = NULL;
4700
4701                         skb_put(skb, len);
4702                 } else {
4703                         struct sk_buff *copy_skb;
4704
4705                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4706                                        desc_idx, *post_ptr);
4707
4708                         copy_skb = netdev_alloc_skb(tp->dev, len + VLAN_HLEN +
4709                                                     TG3_RAW_IP_ALIGN);
4710                         if (copy_skb == NULL)
4711                                 goto drop_it_no_recycle;
4712
4713                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN + VLAN_HLEN);
4714                         skb_put(copy_skb, len);
4715                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4716                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4717                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4718
4719                         /* We'll reuse the original ring buffer. */
4720                         skb = copy_skb;
4721                 }
4722
4723                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4724                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4725                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4726                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4727                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4728                 else
4729                         skb->ip_summed = CHECKSUM_NONE;
4730
4731                 skb->protocol = eth_type_trans(skb, tp->dev);
4732
4733                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4734                     skb->protocol != htons(ETH_P_8021Q)) {
4735                         dev_kfree_skb(skb);
4736                         goto next_pkt;
4737                 }
4738
4739                 if (desc->type_flags & RXD_FLAG_VLAN &&
4740                     !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) {
4741                         vtag = desc->err_vlan & RXD_VLAN_MASK;
4742 #if TG3_VLAN_TAG_USED
4743                         if (tp->vlgrp)
4744                                 hw_vlan = true;
4745                         else
4746 #endif
4747                         {
4748                                 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
4749                                                     __skb_push(skb, VLAN_HLEN);
4750
4751                                 memmove(ve, skb->data + VLAN_HLEN,
4752                                         ETH_ALEN * 2);
4753                                 ve->h_vlan_proto = htons(ETH_P_8021Q);
4754                                 ve->h_vlan_TCI = htons(vtag);
4755                         }
4756                 }
4757
4758 #if TG3_VLAN_TAG_USED
4759                 if (hw_vlan)
4760                         vlan_gro_receive(&tnapi->napi, tp->vlgrp, vtag, skb);
4761                 else
4762 #endif
4763                         napi_gro_receive(&tnapi->napi, skb);
4764
4765                 received++;
4766                 budget--;
4767
4768 next_pkt:
4769                 (*post_ptr)++;
4770
4771                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4772                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4773                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4774                                      tpr->rx_std_prod_idx);
4775                         work_mask &= ~RXD_OPAQUE_RING_STD;
4776                         rx_std_posted = 0;
4777                 }
4778 next_pkt_nopost:
4779                 sw_idx++;
4780                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4781
4782                 /* Refresh hw_idx to see if there is new work */
4783                 if (sw_idx == hw_idx) {
4784                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4785                         rmb();
4786                 }
4787         }
4788
4789         /* ACK the status ring. */
4790         tnapi->rx_rcb_ptr = sw_idx;
4791         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4792
4793         /* Refill RX ring(s). */
4794         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4795                 if (work_mask & RXD_OPAQUE_RING_STD) {
4796                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4797                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4798                                      tpr->rx_std_prod_idx);
4799                 }
4800                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4801                         tpr->rx_jmb_prod_idx = jmb_prod_idx %
4802                                                TG3_RX_JUMBO_RING_SIZE;
4803                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4804                                      tpr->rx_jmb_prod_idx);
4805                 }
4806                 mmiowb();
4807         } else if (work_mask) {
4808                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4809                  * updated before the producer indices can be updated.
4810                  */
4811                 smp_wmb();
4812
4813                 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4814                 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
4815
4816                 if (tnapi != &tp->napi[1])
4817                         napi_schedule(&tp->napi[1].napi);
4818         }
4819
4820         return received;
4821 }
4822
4823 static void tg3_poll_link(struct tg3 *tp)
4824 {
4825         /* handle link change and other phy events */
4826         if (!(tp->tg3_flags &
4827               (TG3_FLAG_USE_LINKCHG_REG |
4828                TG3_FLAG_POLL_SERDES))) {
4829                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4830
4831                 if (sblk->status & SD_STATUS_LINK_CHG) {
4832                         sblk->status = SD_STATUS_UPDATED |
4833                                        (sblk->status & ~SD_STATUS_LINK_CHG);
4834                         spin_lock(&tp->lock);
4835                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4836                                 tw32_f(MAC_STATUS,
4837                                      (MAC_STATUS_SYNC_CHANGED |
4838                                       MAC_STATUS_CFG_CHANGED |
4839                                       MAC_STATUS_MI_COMPLETION |
4840                                       MAC_STATUS_LNKSTATE_CHANGED));
4841                                 udelay(40);
4842                         } else
4843                                 tg3_setup_phy(tp, 0);
4844                         spin_unlock(&tp->lock);
4845                 }
4846         }
4847 }
4848
4849 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4850                                 struct tg3_rx_prodring_set *dpr,
4851                                 struct tg3_rx_prodring_set *spr)
4852 {
4853         u32 si, di, cpycnt, src_prod_idx;
4854         int i, err = 0;
4855
4856         while (1) {
4857                 src_prod_idx = spr->rx_std_prod_idx;
4858
4859                 /* Make sure updates to the rx_std_buffers[] entries and the
4860                  * standard producer index are seen in the correct order.
4861                  */
4862                 smp_rmb();
4863
4864                 if (spr->rx_std_cons_idx == src_prod_idx)
4865                         break;
4866
4867                 if (spr->rx_std_cons_idx < src_prod_idx)
4868                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4869                 else
4870                         cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4871
4872                 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4873
4874                 si = spr->rx_std_cons_idx;
4875                 di = dpr->rx_std_prod_idx;
4876
4877                 for (i = di; i < di + cpycnt; i++) {
4878                         if (dpr->rx_std_buffers[i].skb) {
4879                                 cpycnt = i - di;
4880                                 err = -ENOSPC;
4881                                 break;
4882                         }
4883                 }
4884
4885                 if (!cpycnt)
4886                         break;
4887
4888                 /* Ensure that updates to the rx_std_buffers ring and the
4889                  * shadowed hardware producer ring from tg3_recycle_skb() are
4890                  * ordered correctly WRT the skb check above.
4891                  */
4892                 smp_rmb();
4893
4894                 memcpy(&dpr->rx_std_buffers[di],
4895                        &spr->rx_std_buffers[si],
4896                        cpycnt * sizeof(struct ring_info));
4897
4898                 for (i = 0; i < cpycnt; i++, di++, si++) {
4899                         struct tg3_rx_buffer_desc *sbd, *dbd;
4900                         sbd = &spr->rx_std[si];
4901                         dbd = &dpr->rx_std[di];
4902                         dbd->addr_hi = sbd->addr_hi;
4903                         dbd->addr_lo = sbd->addr_lo;
4904                 }
4905
4906                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4907                                        TG3_RX_RING_SIZE;
4908                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4909                                        TG3_RX_RING_SIZE;
4910         }
4911
4912         while (1) {
4913                 src_prod_idx = spr->rx_jmb_prod_idx;
4914
4915                 /* Make sure updates to the rx_jmb_buffers[] entries and
4916                  * the jumbo producer index are seen in the correct order.
4917                  */
4918                 smp_rmb();
4919
4920                 if (spr->rx_jmb_cons_idx == src_prod_idx)
4921                         break;
4922
4923                 if (spr->rx_jmb_cons_idx < src_prod_idx)
4924                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4925                 else
4926                         cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4927
4928                 cpycnt = min(cpycnt,
4929                              TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4930
4931                 si = spr->rx_jmb_cons_idx;
4932                 di = dpr->rx_jmb_prod_idx;
4933
4934                 for (i = di; i < di + cpycnt; i++) {
4935                         if (dpr->rx_jmb_buffers[i].skb) {
4936                                 cpycnt = i - di;
4937                                 err = -ENOSPC;
4938                                 break;
4939                         }
4940                 }
4941
4942                 if (!cpycnt)
4943                         break;
4944
4945                 /* Ensure that updates to the rx_jmb_buffers ring and the
4946                  * shadowed hardware producer ring from tg3_recycle_skb() are
4947                  * ordered correctly WRT the skb check above.
4948                  */
4949                 smp_rmb();
4950
4951                 memcpy(&dpr->rx_jmb_buffers[di],
4952                        &spr->rx_jmb_buffers[si],
4953                        cpycnt * sizeof(struct ring_info));
4954
4955                 for (i = 0; i < cpycnt; i++, di++, si++) {
4956                         struct tg3_rx_buffer_desc *sbd, *dbd;
4957                         sbd = &spr->rx_jmb[si].std;
4958                         dbd = &dpr->rx_jmb[di].std;
4959                         dbd->addr_hi = sbd->addr_hi;
4960                         dbd->addr_lo = sbd->addr_lo;
4961                 }
4962
4963                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4964                                        TG3_RX_JUMBO_RING_SIZE;
4965                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4966                                        TG3_RX_JUMBO_RING_SIZE;
4967         }
4968
4969         return err;
4970 }
4971
4972 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4973 {
4974         struct tg3 *tp = tnapi->tp;
4975
4976         /* run TX completion thread */
4977         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4978                 tg3_tx(tnapi);
4979                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4980                         return work_done;
4981         }
4982
4983         /* run RX thread, within the bounds set by NAPI.
4984          * All RX "locking" is done by ensuring outside
4985          * code synchronizes with tg3->napi.poll()
4986          */
4987         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4988                 work_done += tg3_rx(tnapi, budget - work_done);
4989
4990         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4991                 struct tg3_rx_prodring_set *dpr = &tp->prodring[0];
4992                 int i, err = 0;
4993                 u32 std_prod_idx = dpr->rx_std_prod_idx;
4994                 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
4995
4996                 for (i = 1; i < tp->irq_cnt; i++)
4997                         err |= tg3_rx_prodring_xfer(tp, dpr,
4998                                                     tp->napi[i].prodring);
4999
5000                 wmb();
5001
5002                 if (std_prod_idx != dpr->rx_std_prod_idx)
5003                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5004                                      dpr->rx_std_prod_idx);
5005
5006                 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5007                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5008                                      dpr->rx_jmb_prod_idx);
5009
5010                 mmiowb();
5011
5012                 if (err)
5013                         tw32_f(HOSTCC_MODE, tp->coal_now);
5014         }
5015
5016         return work_done;
5017 }
5018
5019 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5020 {
5021         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5022         struct tg3 *tp = tnapi->tp;
5023         int work_done = 0;
5024         struct tg3_hw_status *sblk = tnapi->hw_status;
5025
5026         while (1) {
5027                 work_done = tg3_poll_work(tnapi, work_done, budget);
5028
5029                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5030                         goto tx_recovery;
5031
5032                 if (unlikely(work_done >= budget))
5033                         break;
5034
5035                 /* tp->last_tag is used in tg3_int_reenable() below
5036                  * to tell the hw how much work has been processed,
5037                  * so we must read it before checking for more work.
5038                  */
5039                 tnapi->last_tag = sblk->status_tag;
5040                 tnapi->last_irq_tag = tnapi->last_tag;
5041                 rmb();
5042
5043                 /* check for RX/TX work to do */
5044                 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5045                            *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5046                         napi_complete(napi);
5047                         /* Reenable interrupts. */
5048                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5049                         mmiowb();
5050                         break;
5051                 }
5052         }
5053
5054         return work_done;
5055
5056 tx_recovery:
5057         /* work_done is guaranteed to be less than budget. */
5058         napi_complete(napi);
5059         schedule_work(&tp->reset_task);
5060         return work_done;
5061 }
5062
5063 static int tg3_poll(struct napi_struct *napi, int budget)
5064 {
5065         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5066         struct tg3 *tp = tnapi->tp;
5067         int work_done = 0;
5068         struct tg3_hw_status *sblk = tnapi->hw_status;
5069
5070         while (1) {
5071                 tg3_poll_link(tp);
5072
5073                 work_done = tg3_poll_work(tnapi, work_done, budget);
5074
5075                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5076                         goto tx_recovery;
5077
5078                 if (unlikely(work_done >= budget))
5079                         break;
5080
5081                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5082                         /* tp->last_tag is used in tg3_int_reenable() below
5083                          * to tell the hw how much work has been processed,
5084                          * so we must read it before checking for more work.
5085                          */
5086                         tnapi->last_tag = sblk->status_tag;
5087                         tnapi->last_irq_tag = tnapi->last_tag;
5088                         rmb();
5089                 } else
5090                         sblk->status &= ~SD_STATUS_UPDATED;
5091
5092                 if (likely(!tg3_has_work(tnapi))) {
5093                         napi_complete(napi);
5094                         tg3_int_reenable(tnapi);
5095                         break;
5096                 }
5097         }
5098
5099         return work_done;
5100
5101 tx_recovery:
5102         /* work_done is guaranteed to be less than budget. */
5103         napi_complete(napi);
5104         schedule_work(&tp->reset_task);
5105         return work_done;
5106 }
5107
5108 static void tg3_irq_quiesce(struct tg3 *tp)
5109 {
5110         int i;
5111
5112         BUG_ON(tp->irq_sync);
5113
5114         tp->irq_sync = 1;
5115         smp_mb();
5116
5117         for (i = 0; i < tp->irq_cnt; i++)
5118                 synchronize_irq(tp->napi[i].irq_vec);
5119 }
5120
5121 static inline int tg3_irq_sync(struct tg3 *tp)
5122 {
5123         return tp->irq_sync;
5124 }
5125
5126 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5127  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5128  * with as well.  Most of the time, this is not necessary except when
5129  * shutting down the device.
5130  */
5131 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5132 {
5133         spin_lock_bh(&tp->lock);
5134         if (irq_sync)
5135                 tg3_irq_quiesce(tp);
5136 }
5137
5138 static inline void tg3_full_unlock(struct tg3 *tp)
5139 {
5140         spin_unlock_bh(&tp->lock);
5141 }
5142
5143 /* One-shot MSI handler - Chip automatically disables interrupt
5144  * after sending MSI so driver doesn't have to do it.
5145  */
5146 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5147 {
5148         struct tg3_napi *tnapi = dev_id;
5149         struct tg3 *tp = tnapi->tp;
5150
5151         prefetch(tnapi->hw_status);
5152         if (tnapi->rx_rcb)
5153                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5154
5155         if (likely(!tg3_irq_sync(tp)))
5156                 napi_schedule(&tnapi->napi);
5157
5158         return IRQ_HANDLED;
5159 }
5160
5161 /* MSI ISR - No need to check for interrupt sharing and no need to
5162  * flush status block and interrupt mailbox. PCI ordering rules
5163  * guarantee that MSI will arrive after the status block.
5164  */
5165 static irqreturn_t tg3_msi(int irq, void *dev_id)
5166 {
5167         struct tg3_napi *tnapi = dev_id;
5168         struct tg3 *tp = tnapi->tp;
5169
5170         prefetch(tnapi->hw_status);
5171         if (tnapi->rx_rcb)
5172                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5173         /*
5174          * Writing any value to intr-mbox-0 clears PCI INTA# and
5175          * chip-internal interrupt pending events.
5176          * Writing non-zero to intr-mbox-0 additional tells the
5177          * NIC to stop sending us irqs, engaging "in-intr-handler"
5178          * event coalescing.
5179          */
5180         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5181         if (likely(!tg3_irq_sync(tp)))
5182                 napi_schedule(&tnapi->napi);
5183
5184         return IRQ_RETVAL(1);
5185 }
5186
5187 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5188 {
5189         struct tg3_napi *tnapi = dev_id;
5190         struct tg3 *tp = tnapi->tp;
5191         struct tg3_hw_status *sblk = tnapi->hw_status;
5192         unsigned int handled = 1;
5193
5194         /* In INTx mode, it is possible for the interrupt to arrive at
5195          * the CPU before the status block posted prior to the interrupt.
5196          * Reading the PCI State register will confirm whether the
5197          * interrupt is ours and will flush the status block.
5198          */
5199         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5200                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5201                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5202                         handled = 0;
5203                         goto out;
5204                 }
5205         }
5206
5207         /*
5208          * Writing any value to intr-mbox-0 clears PCI INTA# and
5209          * chip-internal interrupt pending events.
5210          * Writing non-zero to intr-mbox-0 additional tells the
5211          * NIC to stop sending us irqs, engaging "in-intr-handler"
5212          * event coalescing.
5213          *
5214          * Flush the mailbox to de-assert the IRQ immediately to prevent
5215          * spurious interrupts.  The flush impacts performance but
5216          * excessive spurious interrupts can be worse in some cases.
5217          */
5218         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5219         if (tg3_irq_sync(tp))
5220                 goto out;
5221         sblk->status &= ~SD_STATUS_UPDATED;
5222         if (likely(tg3_has_work(tnapi))) {
5223                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5224                 napi_schedule(&tnapi->napi);
5225         } else {
5226                 /* No work, shared interrupt perhaps?  re-enable
5227                  * interrupts, and flush that PCI write
5228                  */
5229                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5230                                0x00000000);
5231         }
5232 out:
5233         return IRQ_RETVAL(handled);
5234 }
5235
5236 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5237 {
5238         struct tg3_napi *tnapi = dev_id;
5239         struct tg3 *tp = tnapi->tp;
5240         struct tg3_hw_status *sblk = tnapi->hw_status;
5241         unsigned int handled = 1;
5242
5243         /* In INTx mode, it is possible for the interrupt to arrive at
5244          * the CPU before the status block posted prior to the interrupt.
5245          * Reading the PCI State register will confirm whether the
5246          * interrupt is ours and will flush the status block.
5247          */
5248         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5249                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5250                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5251                         handled = 0;
5252                         goto out;
5253                 }
5254         }
5255
5256         /*
5257          * writing any value to intr-mbox-0 clears PCI INTA# and
5258          * chip-internal interrupt pending events.
5259          * writing non-zero to intr-mbox-0 additional tells the
5260          * NIC to stop sending us irqs, engaging "in-intr-handler"
5261          * event coalescing.
5262          *
5263          * Flush the mailbox to de-assert the IRQ immediately to prevent
5264          * spurious interrupts.  The flush impacts performance but
5265          * excessive spurious interrupts can be worse in some cases.
5266          */
5267         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5268
5269         /*
5270          * In a shared interrupt configuration, sometimes other devices'
5271          * interrupts will scream.  We record the current status tag here
5272          * so that the above check can report that the screaming interrupts
5273          * are unhandled.  Eventually they will be silenced.
5274          */
5275         tnapi->last_irq_tag = sblk->status_tag;
5276
5277         if (tg3_irq_sync(tp))
5278                 goto out;
5279
5280         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5281
5282         napi_schedule(&tnapi->napi);
5283
5284 out:
5285         return IRQ_RETVAL(handled);
5286 }
5287
5288 /* ISR for interrupt test */
5289 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5290 {
5291         struct tg3_napi *tnapi = dev_id;
5292         struct tg3 *tp = tnapi->tp;
5293         struct tg3_hw_status *sblk = tnapi->hw_status;
5294
5295         if ((sblk->status & SD_STATUS_UPDATED) ||
5296             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5297                 tg3_disable_ints(tp);
5298                 return IRQ_RETVAL(1);
5299         }
5300         return IRQ_RETVAL(0);
5301 }
5302
5303 static int tg3_init_hw(struct tg3 *, int);
5304 static int tg3_halt(struct tg3 *, int, int);
5305
5306 /* Restart hardware after configuration changes, self-test, etc.
5307  * Invoked with tp->lock held.
5308  */
5309 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5310         __releases(tp->lock)
5311         __acquires(tp->lock)
5312 {
5313         int err;
5314
5315         err = tg3_init_hw(tp, reset_phy);
5316         if (err) {
5317                 netdev_err(tp->dev,
5318                            "Failed to re-initialize device, aborting\n");
5319                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5320                 tg3_full_unlock(tp);
5321                 del_timer_sync(&tp->timer);
5322                 tp->irq_sync = 0;
5323                 tg3_napi_enable(tp);
5324                 dev_close(tp->dev);
5325                 tg3_full_lock(tp, 0);
5326         }
5327         return err;
5328 }
5329
5330 #ifdef CONFIG_NET_POLL_CONTROLLER
5331 static void tg3_poll_controller(struct net_device *dev)
5332 {
5333         int i;
5334         struct tg3 *tp = netdev_priv(dev);
5335
5336         for (i = 0; i < tp->irq_cnt; i++)
5337                 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5338 }
5339 #endif
5340
5341 static void tg3_reset_task(struct work_struct *work)
5342 {
5343         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5344         int err;
5345         unsigned int restart_timer;
5346
5347         tg3_full_lock(tp, 0);
5348
5349         if (!netif_running(tp->dev)) {
5350                 tg3_full_unlock(tp);
5351                 return;
5352         }
5353
5354         tg3_full_unlock(tp);
5355
5356         tg3_phy_stop(tp);
5357
5358         tg3_netif_stop(tp);
5359
5360         tg3_full_lock(tp, 1);
5361
5362         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5363         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5364
5365         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5366                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5367                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5368                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5369                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5370         }
5371
5372         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5373         err = tg3_init_hw(tp, 1);
5374         if (err)
5375                 goto out;
5376
5377         tg3_netif_start(tp);
5378
5379         if (restart_timer)
5380                 mod_timer(&tp->timer, jiffies + 1);
5381
5382 out:
5383         tg3_full_unlock(tp);
5384
5385         if (!err)
5386                 tg3_phy_start(tp);
5387 }
5388
5389 static void tg3_dump_short_state(struct tg3 *tp)
5390 {
5391         netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5392                    tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5393         netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5394                    tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5395 }
5396
5397 static void tg3_tx_timeout(struct net_device *dev)
5398 {
5399         struct tg3 *tp = netdev_priv(dev);
5400
5401         if (netif_msg_tx_err(tp)) {
5402                 netdev_err(dev, "transmit timed out, resetting\n");
5403                 tg3_dump_short_state(tp);
5404         }
5405
5406         schedule_work(&tp->reset_task);
5407 }
5408
5409 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5410 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5411 {
5412         u32 base = (u32) mapping & 0xffffffff;
5413
5414         return ((base > 0xffffdcc0) &&
5415                 (base + len + 8 < base));
5416 }
5417
5418 /* Test for DMA addresses > 40-bit */
5419 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5420                                           int len)
5421 {
5422 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5423         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5424                 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5425         return 0;
5426 #else
5427         return 0;
5428 #endif
5429 }
5430
5431 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5432
5433 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5434 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5435                                        struct sk_buff *skb, u32 last_plus_one,
5436                                        u32 *start, u32 base_flags, u32 mss)
5437 {
5438         struct tg3 *tp = tnapi->tp;
5439         struct sk_buff *new_skb;
5440         dma_addr_t new_addr = 0;
5441         u32 entry = *start;
5442         int i, ret = 0;
5443
5444         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5445                 new_skb = skb_copy(skb, GFP_ATOMIC);
5446         else {
5447                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5448
5449                 new_skb = skb_copy_expand(skb,
5450                                           skb_headroom(skb) + more_headroom,
5451                                           skb_tailroom(skb), GFP_ATOMIC);
5452         }
5453
5454         if (!new_skb) {
5455                 ret = -1;
5456         } else {
5457                 /* New SKB is guaranteed to be linear. */
5458                 entry = *start;
5459                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5460                                           PCI_DMA_TODEVICE);
5461                 /* Make sure the mapping succeeded */
5462                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5463                         ret = -1;
5464                         dev_kfree_skb(new_skb);
5465                         new_skb = NULL;
5466
5467                 /* Make sure new skb does not cross any 4G boundaries.
5468                  * Drop the packet if it does.
5469                  */
5470                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5471                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5472                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5473                                          PCI_DMA_TODEVICE);
5474                         ret = -1;
5475                         dev_kfree_skb(new_skb);
5476                         new_skb = NULL;
5477                 } else {
5478                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5479                                     base_flags, 1 | (mss << 1));
5480                         *start = NEXT_TX(entry);
5481                 }
5482         }
5483
5484         /* Now clean up the sw ring entries. */
5485         i = 0;
5486         while (entry != last_plus_one) {
5487                 int len;
5488
5489                 if (i == 0)
5490                         len = skb_headlen(skb);
5491                 else
5492                         len = skb_shinfo(skb)->frags[i-1].size;
5493
5494                 pci_unmap_single(tp->pdev,
5495                                  dma_unmap_addr(&tnapi->tx_buffers[entry],
5496                                                 mapping),
5497                                  len, PCI_DMA_TODEVICE);
5498                 if (i == 0) {
5499                         tnapi->tx_buffers[entry].skb = new_skb;
5500                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5501                                            new_addr);
5502                 } else {
5503                         tnapi->tx_buffers[entry].skb = NULL;
5504                 }
5505                 entry = NEXT_TX(entry);
5506                 i++;
5507         }
5508
5509         dev_kfree_skb(skb);
5510
5511         return ret;
5512 }
5513
5514 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5515                         dma_addr_t mapping, int len, u32 flags,
5516                         u32 mss_and_is_end)
5517 {
5518         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5519         int is_end = (mss_and_is_end & 0x1);
5520         u32 mss = (mss_and_is_end >> 1);
5521         u32 vlan_tag = 0;
5522
5523         if (is_end)
5524                 flags |= TXD_FLAG_END;
5525         if (flags & TXD_FLAG_VLAN) {
5526                 vlan_tag = flags >> 16;
5527                 flags &= 0xffff;
5528         }
5529         vlan_tag |= (mss << TXD_MSS_SHIFT);
5530
5531         txd->addr_hi = ((u64) mapping >> 32);
5532         txd->addr_lo = ((u64) mapping & 0xffffffff);
5533         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5534         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5535 }
5536
5537 /* hard_start_xmit for devices that don't have any bugs and
5538  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5539  */
5540 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5541                                   struct net_device *dev)
5542 {
5543         struct tg3 *tp = netdev_priv(dev);
5544         u32 len, entry, base_flags, mss;
5545         dma_addr_t mapping;
5546         struct tg3_napi *tnapi;
5547         struct netdev_queue *txq;
5548         unsigned int i, last;
5549
5550         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5551         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5552         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5553                 tnapi++;
5554
5555         /* We are running in BH disabled context with netif_tx_lock
5556          * and TX reclaim runs via tp->napi.poll inside of a software
5557          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5558          * no IRQ context deadlocks to worry about either.  Rejoice!
5559          */
5560         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5561                 if (!netif_tx_queue_stopped(txq)) {
5562                         netif_tx_stop_queue(txq);
5563
5564                         /* This is a hard error, log it. */
5565                         netdev_err(dev,
5566                                    "BUG! Tx Ring full when queue awake!\n");
5567                 }
5568                 return NETDEV_TX_BUSY;
5569         }
5570
5571         entry = tnapi->tx_prod;
5572         base_flags = 0;
5573         mss = 0;
5574         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5575                 int tcp_opt_len, ip_tcp_len;
5576                 u32 hdrlen;
5577
5578                 if (skb_header_cloned(skb) &&
5579                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5580                         dev_kfree_skb(skb);
5581                         goto out_unlock;
5582                 }
5583
5584                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5585                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5586                 else {
5587                         struct iphdr *iph = ip_hdr(skb);
5588
5589                         tcp_opt_len = tcp_optlen(skb);
5590                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5591
5592                         iph->check = 0;
5593                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5594                         hdrlen = ip_tcp_len + tcp_opt_len;
5595                 }
5596
5597                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5598                         mss |= (hdrlen & 0xc) << 12;
5599                         if (hdrlen & 0x10)
5600                                 base_flags |= 0x00000010;
5601                         base_flags |= (hdrlen & 0x3e0) << 5;
5602                 } else
5603                         mss |= hdrlen << 9;
5604
5605                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5606                                TXD_FLAG_CPU_POST_DMA);
5607
5608                 tcp_hdr(skb)->check = 0;
5609
5610         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5611                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5612         }
5613
5614 #if TG3_VLAN_TAG_USED
5615         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5616                 base_flags |= (TXD_FLAG_VLAN |
5617                                (vlan_tx_tag_get(skb) << 16));
5618 #endif
5619
5620         len = skb_headlen(skb);
5621
5622         /* Queue skb data, a.k.a. the main skb fragment. */
5623         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5624         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5625                 dev_kfree_skb(skb);
5626                 goto out_unlock;
5627         }
5628
5629         tnapi->tx_buffers[entry].skb = skb;
5630         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5631
5632         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5633             !mss && skb->len > ETH_DATA_LEN)
5634                 base_flags |= TXD_FLAG_JMB_PKT;
5635
5636         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5637                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5638
5639         entry = NEXT_TX(entry);
5640
5641         /* Now loop through additional data fragments, and queue them. */
5642         if (skb_shinfo(skb)->nr_frags > 0) {
5643                 last = skb_shinfo(skb)->nr_frags - 1;
5644                 for (i = 0; i <= last; i++) {
5645                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5646
5647                         len = frag->size;
5648                         mapping = pci_map_page(tp->pdev,
5649                                                frag->page,
5650                                                frag->page_offset,
5651                                                len, PCI_DMA_TODEVICE);
5652                         if (pci_dma_mapping_error(tp->pdev, mapping))
5653                                 goto dma_error;
5654
5655                         tnapi->tx_buffers[entry].skb = NULL;
5656                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5657                                            mapping);
5658
5659                         tg3_set_txd(tnapi, entry, mapping, len,
5660                                     base_flags, (i == last) | (mss << 1));
5661
5662                         entry = NEXT_TX(entry);
5663                 }
5664         }
5665
5666         /* Packets are ready, update Tx producer idx local and on card. */
5667         tw32_tx_mbox(tnapi->prodmbox, entry);
5668
5669         tnapi->tx_prod = entry;
5670         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5671                 netif_tx_stop_queue(txq);
5672                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5673                         netif_tx_wake_queue(txq);
5674         }
5675
5676 out_unlock:
5677         mmiowb();
5678
5679         return NETDEV_TX_OK;
5680
5681 dma_error:
5682         last = i;
5683         entry = tnapi->tx_prod;
5684         tnapi->tx_buffers[entry].skb = NULL;
5685         pci_unmap_single(tp->pdev,
5686                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5687                          skb_headlen(skb),
5688                          PCI_DMA_TODEVICE);
5689         for (i = 0; i <= last; i++) {
5690                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5691                 entry = NEXT_TX(entry);
5692
5693                 pci_unmap_page(tp->pdev,
5694                                dma_unmap_addr(&tnapi->tx_buffers[entry],
5695                                               mapping),
5696                                frag->size, PCI_DMA_TODEVICE);
5697         }
5698
5699         dev_kfree_skb(skb);
5700         return NETDEV_TX_OK;
5701 }
5702
5703 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5704                                           struct net_device *);
5705
5706 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5707  * TSO header is greater than 80 bytes.
5708  */
5709 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5710 {
5711         struct sk_buff *segs, *nskb;
5712         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5713
5714         /* Estimate the number of fragments in the worst case */
5715         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5716                 netif_stop_queue(tp->dev);
5717                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5718                         return NETDEV_TX_BUSY;
5719
5720                 netif_wake_queue(tp->dev);
5721         }
5722
5723         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5724         if (IS_ERR(segs))
5725                 goto tg3_tso_bug_end;
5726
5727         do {
5728                 nskb = segs;
5729                 segs = segs->next;
5730                 nskb->next = NULL;
5731                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5732         } while (segs);
5733
5734 tg3_tso_bug_end:
5735         dev_kfree_skb(skb);
5736
5737         return NETDEV_TX_OK;
5738 }
5739
5740 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5741  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5742  */
5743 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5744                                           struct net_device *dev)
5745 {
5746         struct tg3 *tp = netdev_priv(dev);
5747         u32 len, entry, base_flags, mss;
5748         int would_hit_hwbug;
5749         dma_addr_t mapping;
5750         struct tg3_napi *tnapi;
5751         struct netdev_queue *txq;
5752         unsigned int i, last;
5753
5754         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5755         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5756         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5757                 tnapi++;
5758
5759         /* We are running in BH disabled context with netif_tx_lock
5760          * and TX reclaim runs via tp->napi.poll inside of a software
5761          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5762          * no IRQ context deadlocks to worry about either.  Rejoice!
5763          */
5764         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5765                 if (!netif_tx_queue_stopped(txq)) {
5766                         netif_tx_stop_queue(txq);
5767
5768                         /* This is a hard error, log it. */
5769                         netdev_err(dev,
5770                                    "BUG! Tx Ring full when queue awake!\n");
5771                 }
5772                 return NETDEV_TX_BUSY;
5773         }
5774
5775         entry = tnapi->tx_prod;
5776         base_flags = 0;
5777         if (skb->ip_summed == CHECKSUM_PARTIAL)
5778                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5779
5780         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5781                 struct iphdr *iph;
5782                 u32 tcp_opt_len, ip_tcp_len, hdr_len;
5783
5784                 if (skb_header_cloned(skb) &&
5785                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5786                         dev_kfree_skb(skb);
5787                         goto out_unlock;
5788                 }
5789
5790                 tcp_opt_len = tcp_optlen(skb);
5791                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5792
5793                 hdr_len = ip_tcp_len + tcp_opt_len;
5794                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5795                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5796                         return tg3_tso_bug(tp, skb);
5797
5798                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5799                                TXD_FLAG_CPU_POST_DMA);
5800
5801                 iph = ip_hdr(skb);
5802                 iph->check = 0;
5803                 iph->tot_len = htons(mss + hdr_len);
5804                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5805                         tcp_hdr(skb)->check = 0;
5806                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5807                 } else
5808                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5809                                                                  iph->daddr, 0,
5810                                                                  IPPROTO_TCP,
5811                                                                  0);
5812
5813                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5814                         mss |= (hdr_len & 0xc) << 12;
5815                         if (hdr_len & 0x10)
5816                                 base_flags |= 0x00000010;
5817                         base_flags |= (hdr_len & 0x3e0) << 5;
5818                 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5819                         mss |= hdr_len << 9;
5820                 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5821                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5822                         if (tcp_opt_len || iph->ihl > 5) {
5823                                 int tsflags;
5824
5825                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5826                                 mss |= (tsflags << 11);
5827                         }
5828                 } else {
5829                         if (tcp_opt_len || iph->ihl > 5) {
5830                                 int tsflags;
5831
5832                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5833                                 base_flags |= tsflags << 12;
5834                         }
5835                 }
5836         }
5837 #if TG3_VLAN_TAG_USED
5838         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5839                 base_flags |= (TXD_FLAG_VLAN |
5840                                (vlan_tx_tag_get(skb) << 16));
5841 #endif
5842
5843         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5844             !mss && skb->len > ETH_DATA_LEN)
5845                 base_flags |= TXD_FLAG_JMB_PKT;
5846
5847         len = skb_headlen(skb);
5848
5849         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5850         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5851                 dev_kfree_skb(skb);
5852                 goto out_unlock;
5853         }
5854
5855         tnapi->tx_buffers[entry].skb = skb;
5856         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5857
5858         would_hit_hwbug = 0;
5859
5860         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5861                 would_hit_hwbug = 1;
5862
5863         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5864             tg3_4g_overflow_test(mapping, len))
5865                 would_hit_hwbug = 1;
5866
5867         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5868             tg3_40bit_overflow_test(tp, mapping, len))
5869                 would_hit_hwbug = 1;
5870
5871         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5872                 would_hit_hwbug = 1;
5873
5874         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5875                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5876
5877         entry = NEXT_TX(entry);
5878
5879         /* Now loop through additional data fragments, and queue them. */
5880         if (skb_shinfo(skb)->nr_frags > 0) {
5881                 last = skb_shinfo(skb)->nr_frags - 1;
5882                 for (i = 0; i <= last; i++) {
5883                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5884
5885                         len = frag->size;
5886                         mapping = pci_map_page(tp->pdev,
5887                                                frag->page,
5888                                                frag->page_offset,
5889                                                len, PCI_DMA_TODEVICE);
5890
5891                         tnapi->tx_buffers[entry].skb = NULL;
5892                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5893                                            mapping);
5894                         if (pci_dma_mapping_error(tp->pdev, mapping))
5895                                 goto dma_error;
5896
5897                         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5898                             len <= 8)
5899                                 would_hit_hwbug = 1;
5900
5901                         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5902                             tg3_4g_overflow_test(mapping, len))
5903                                 would_hit_hwbug = 1;
5904
5905                         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5906                             tg3_40bit_overflow_test(tp, mapping, len))
5907                                 would_hit_hwbug = 1;
5908
5909                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5910                                 tg3_set_txd(tnapi, entry, mapping, len,
5911                                             base_flags, (i == last)|(mss << 1));
5912                         else
5913                                 tg3_set_txd(tnapi, entry, mapping, len,
5914                                             base_flags, (i == last));
5915
5916                         entry = NEXT_TX(entry);
5917                 }
5918         }
5919
5920         if (would_hit_hwbug) {
5921                 u32 last_plus_one = entry;
5922                 u32 start;
5923
5924                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5925                 start &= (TG3_TX_RING_SIZE - 1);
5926
5927                 /* If the workaround fails due to memory/mapping
5928                  * failure, silently drop this packet.
5929                  */
5930                 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
5931                                                 &start, base_flags, mss))
5932                         goto out_unlock;
5933
5934                 entry = start;
5935         }
5936
5937         /* Packets are ready, update Tx producer idx local and on card. */
5938         tw32_tx_mbox(tnapi->prodmbox, entry);
5939
5940         tnapi->tx_prod = entry;
5941         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5942                 netif_tx_stop_queue(txq);
5943                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5944                         netif_tx_wake_queue(txq);
5945         }
5946
5947 out_unlock:
5948         mmiowb();
5949
5950         return NETDEV_TX_OK;
5951
5952 dma_error:
5953         last = i;
5954         entry = tnapi->tx_prod;
5955         tnapi->tx_buffers[entry].skb = NULL;
5956         pci_unmap_single(tp->pdev,
5957                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5958                          skb_headlen(skb),
5959                          PCI_DMA_TODEVICE);
5960         for (i = 0; i <= last; i++) {
5961                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5962                 entry = NEXT_TX(entry);
5963
5964                 pci_unmap_page(tp->pdev,
5965                                dma_unmap_addr(&tnapi->tx_buffers[entry],
5966                                               mapping),
5967                                frag->size, PCI_DMA_TODEVICE);
5968         }
5969
5970         dev_kfree_skb(skb);
5971         return NETDEV_TX_OK;
5972 }
5973
5974 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5975                                int new_mtu)
5976 {
5977         dev->mtu = new_mtu;
5978
5979         if (new_mtu > ETH_DATA_LEN) {
5980                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5981                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5982                         ethtool_op_set_tso(dev, 0);
5983                 } else {
5984                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5985                 }
5986         } else {
5987                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5988                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5989                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5990         }
5991 }
5992
5993 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5994 {
5995         struct tg3 *tp = netdev_priv(dev);
5996         int err;
5997
5998         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5999                 return -EINVAL;
6000
6001         if (!netif_running(dev)) {
6002                 /* We'll just catch it later when the
6003                  * device is up'd.
6004                  */
6005                 tg3_set_mtu(dev, tp, new_mtu);
6006                 return 0;
6007         }
6008
6009         tg3_phy_stop(tp);
6010
6011         tg3_netif_stop(tp);
6012
6013         tg3_full_lock(tp, 1);
6014
6015         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6016
6017         tg3_set_mtu(dev, tp, new_mtu);
6018
6019         err = tg3_restart_hw(tp, 0);
6020
6021         if (!err)
6022                 tg3_netif_start(tp);
6023
6024         tg3_full_unlock(tp);
6025
6026         if (!err)
6027                 tg3_phy_start(tp);
6028
6029         return err;
6030 }
6031
6032 static void tg3_rx_prodring_free(struct tg3 *tp,
6033                                  struct tg3_rx_prodring_set *tpr)
6034 {
6035         int i;
6036
6037         if (tpr != &tp->prodring[0]) {
6038                 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
6039                      i = (i + 1) % TG3_RX_RING_SIZE)
6040                         tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6041                                         tp->rx_pkt_map_sz);
6042
6043                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6044                         for (i = tpr->rx_jmb_cons_idx;
6045                              i != tpr->rx_jmb_prod_idx;
6046                              i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
6047                                 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6048                                                 TG3_RX_JMB_MAP_SZ);
6049                         }
6050                 }
6051
6052                 return;
6053         }
6054
6055         for (i = 0; i < TG3_RX_RING_SIZE; i++)
6056                 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6057                                 tp->rx_pkt_map_sz);
6058
6059         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6060                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
6061                         tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6062                                         TG3_RX_JMB_MAP_SZ);
6063         }
6064 }
6065
6066 /* Initialize rx rings for packet processing.
6067  *
6068  * The chip has been shut down and the driver detached from
6069  * the networking, so no interrupts or new tx packets will
6070  * end up in the driver.  tp->{tx,}lock are held and thus
6071  * we may not sleep.
6072  */
6073 static int tg3_rx_prodring_alloc(struct tg3 *tp,
6074                                  struct tg3_rx_prodring_set *tpr)
6075 {
6076         u32 i, rx_pkt_dma_sz;
6077
6078         tpr->rx_std_cons_idx = 0;
6079         tpr->rx_std_prod_idx = 0;
6080         tpr->rx_jmb_cons_idx = 0;
6081         tpr->rx_jmb_prod_idx = 0;
6082
6083         if (tpr != &tp->prodring[0]) {
6084                 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
6085                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
6086                         memset(&tpr->rx_jmb_buffers[0], 0,
6087                                TG3_RX_JMB_BUFF_RING_SIZE);
6088                 goto done;
6089         }
6090
6091         /* Zero out all descriptors. */
6092         memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
6093
6094         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6095         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
6096             tp->dev->mtu > ETH_DATA_LEN)
6097                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6098         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6099
6100         /* Initialize invariants of the rings, we only set this
6101          * stuff once.  This works because the card does not
6102          * write into the rx buffer posting rings.
6103          */
6104         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
6105                 struct tg3_rx_buffer_desc *rxd;
6106
6107                 rxd = &tpr->rx_std[i];
6108                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6109                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6110                 rxd->opaque = (RXD_OPAQUE_RING_STD |
6111                                (i << RXD_OPAQUE_INDEX_SHIFT));
6112         }
6113
6114         /* Now allocate fresh SKBs for each rx ring. */
6115         for (i = 0; i < tp->rx_pending; i++) {
6116                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6117                         netdev_warn(tp->dev,
6118                                     "Using a smaller RX standard ring. Only "
6119                                     "%d out of %d buffers were allocated "
6120                                     "successfully\n", i, tp->rx_pending);
6121                         if (i == 0)
6122                                 goto initfail;
6123                         tp->rx_pending = i;
6124                         break;
6125                 }
6126         }
6127
6128         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6129                 goto done;
6130
6131         memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
6132
6133         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
6134                 goto done;
6135
6136         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
6137                 struct tg3_rx_buffer_desc *rxd;
6138
6139                 rxd = &tpr->rx_jmb[i].std;
6140                 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6141                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6142                                   RXD_FLAG_JUMBO;
6143                 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6144                        (i << RXD_OPAQUE_INDEX_SHIFT));
6145         }
6146
6147         for (i = 0; i < tp->rx_jumbo_pending; i++) {
6148                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
6149                         netdev_warn(tp->dev,
6150                                     "Using a smaller RX jumbo ring. Only %d "
6151                                     "out of %d buffers were allocated "
6152                                     "successfully\n", i, tp->rx_jumbo_pending);
6153                         if (i == 0)
6154                                 goto initfail;
6155                         tp->rx_jumbo_pending = i;
6156                         break;
6157                 }
6158         }
6159
6160 done:
6161         return 0;
6162
6163 initfail:
6164         tg3_rx_prodring_free(tp, tpr);
6165         return -ENOMEM;
6166 }
6167
6168 static void tg3_rx_prodring_fini(struct tg3 *tp,
6169                                  struct tg3_rx_prodring_set *tpr)
6170 {
6171         kfree(tpr->rx_std_buffers);
6172         tpr->rx_std_buffers = NULL;
6173         kfree(tpr->rx_jmb_buffers);
6174         tpr->rx_jmb_buffers = NULL;
6175         if (tpr->rx_std) {
6176                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
6177                                     tpr->rx_std, tpr->rx_std_mapping);
6178                 tpr->rx_std = NULL;
6179         }
6180         if (tpr->rx_jmb) {
6181                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
6182                                     tpr->rx_jmb, tpr->rx_jmb_mapping);
6183                 tpr->rx_jmb = NULL;
6184         }
6185 }
6186
6187 static int tg3_rx_prodring_init(struct tg3 *tp,
6188                                 struct tg3_rx_prodring_set *tpr)
6189 {
6190         tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
6191         if (!tpr->rx_std_buffers)
6192                 return -ENOMEM;
6193
6194         tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6195                                            &tpr->rx_std_mapping);
6196         if (!tpr->rx_std)
6197                 goto err_out;
6198
6199         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6200                 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
6201                                               GFP_KERNEL);
6202                 if (!tpr->rx_jmb_buffers)
6203                         goto err_out;
6204
6205                 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6206                                                    TG3_RX_JUMBO_RING_BYTES,
6207                                                    &tpr->rx_jmb_mapping);
6208                 if (!tpr->rx_jmb)
6209                         goto err_out;
6210         }
6211
6212         return 0;
6213
6214 err_out:
6215         tg3_rx_prodring_fini(tp, tpr);
6216         return -ENOMEM;
6217 }
6218
6219 /* Free up pending packets in all rx/tx rings.
6220  *
6221  * The chip has been shut down and the driver detached from
6222  * the networking, so no interrupts or new tx packets will
6223  * end up in the driver.  tp->{tx,}lock is not held and we are not
6224  * in an interrupt context and thus may sleep.
6225  */
6226 static void tg3_free_rings(struct tg3 *tp)
6227 {
6228         int i, j;
6229
6230         for (j = 0; j < tp->irq_cnt; j++) {
6231                 struct tg3_napi *tnapi = &tp->napi[j];
6232
6233                 tg3_rx_prodring_free(tp, &tp->prodring[j]);
6234
6235                 if (!tnapi->tx_buffers)
6236                         continue;
6237
6238                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6239                         struct ring_info *txp;
6240                         struct sk_buff *skb;
6241                         unsigned int k;
6242
6243                         txp = &tnapi->tx_buffers[i];
6244                         skb = txp->skb;
6245
6246                         if (skb == NULL) {
6247                                 i++;
6248                                 continue;
6249                         }
6250
6251                         pci_unmap_single(tp->pdev,
6252                                          dma_unmap_addr(txp, mapping),
6253                                          skb_headlen(skb),
6254                                          PCI_DMA_TODEVICE);
6255                         txp->skb = NULL;
6256
6257                         i++;
6258
6259                         for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6260                                 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6261                                 pci_unmap_page(tp->pdev,
6262                                                dma_unmap_addr(txp, mapping),
6263                                                skb_shinfo(skb)->frags[k].size,
6264                                                PCI_DMA_TODEVICE);
6265                                 i++;
6266                         }
6267
6268                         dev_kfree_skb_any(skb);
6269                 }
6270         }
6271 }
6272
6273 /* Initialize tx/rx rings for packet processing.
6274  *
6275  * The chip has been shut down and the driver detached from
6276  * the networking, so no interrupts or new tx packets will
6277  * end up in the driver.  tp->{tx,}lock are held and thus
6278  * we may not sleep.
6279  */
6280 static int tg3_init_rings(struct tg3 *tp)
6281 {
6282         int i;
6283
6284         /* Free up all the SKBs. */
6285         tg3_free_rings(tp);
6286
6287         for (i = 0; i < tp->irq_cnt; i++) {
6288                 struct tg3_napi *tnapi = &tp->napi[i];
6289
6290                 tnapi->last_tag = 0;
6291                 tnapi->last_irq_tag = 0;
6292                 tnapi->hw_status->status = 0;
6293                 tnapi->hw_status->status_tag = 0;
6294                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6295
6296                 tnapi->tx_prod = 0;
6297                 tnapi->tx_cons = 0;
6298                 if (tnapi->tx_ring)
6299                         memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6300
6301                 tnapi->rx_rcb_ptr = 0;
6302                 if (tnapi->rx_rcb)
6303                         memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6304
6305                 if (tg3_rx_prodring_alloc(tp, &tp->prodring[i])) {
6306                         tg3_free_rings(tp);
6307                         return -ENOMEM;
6308                 }
6309         }
6310
6311         return 0;
6312 }
6313
6314 /*
6315  * Must not be invoked with interrupt sources disabled and
6316  * the hardware shutdown down.
6317  */
6318 static void tg3_free_consistent(struct tg3 *tp)
6319 {
6320         int i;
6321
6322         for (i = 0; i < tp->irq_cnt; i++) {
6323                 struct tg3_napi *tnapi = &tp->napi[i];
6324
6325                 if (tnapi->tx_ring) {
6326                         pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6327                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
6328                         tnapi->tx_ring = NULL;
6329                 }
6330
6331                 kfree(tnapi->tx_buffers);
6332                 tnapi->tx_buffers = NULL;
6333
6334                 if (tnapi->rx_rcb) {
6335                         pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6336                                             tnapi->rx_rcb,
6337                                             tnapi->rx_rcb_mapping);
6338                         tnapi->rx_rcb = NULL;
6339                 }
6340
6341                 if (tnapi->hw_status) {
6342                         pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6343                                             tnapi->hw_status,
6344                                             tnapi->status_mapping);
6345                         tnapi->hw_status = NULL;
6346                 }
6347         }
6348
6349         if (tp->hw_stats) {
6350                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6351                                     tp->hw_stats, tp->stats_mapping);
6352                 tp->hw_stats = NULL;
6353         }
6354
6355         for (i = 0; i < tp->irq_cnt; i++)
6356                 tg3_rx_prodring_fini(tp, &tp->prodring[i]);
6357 }
6358
6359 /*
6360  * Must not be invoked with interrupt sources disabled and
6361  * the hardware shutdown down.  Can sleep.
6362  */
6363 static int tg3_alloc_consistent(struct tg3 *tp)
6364 {
6365         int i;
6366
6367         for (i = 0; i < tp->irq_cnt; i++) {
6368                 if (tg3_rx_prodring_init(tp, &tp->prodring[i]))
6369                         goto err_out;
6370         }
6371
6372         tp->hw_stats = pci_alloc_consistent(tp->pdev,
6373                                             sizeof(struct tg3_hw_stats),
6374                                             &tp->stats_mapping);
6375         if (!tp->hw_stats)
6376                 goto err_out;
6377
6378         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6379
6380         for (i = 0; i < tp->irq_cnt; i++) {
6381                 struct tg3_napi *tnapi = &tp->napi[i];
6382                 struct tg3_hw_status *sblk;
6383
6384                 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6385                                                         TG3_HW_STATUS_SIZE,
6386                                                         &tnapi->status_mapping);
6387                 if (!tnapi->hw_status)
6388                         goto err_out;
6389
6390                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6391                 sblk = tnapi->hw_status;
6392
6393                 /* If multivector TSS is enabled, vector 0 does not handle
6394                  * tx interrupts.  Don't allocate any resources for it.
6395                  */
6396                 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6397                     (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6398                         tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6399                                                     TG3_TX_RING_SIZE,
6400                                                     GFP_KERNEL);
6401                         if (!tnapi->tx_buffers)
6402                                 goto err_out;
6403
6404                         tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6405                                                               TG3_TX_RING_BYTES,
6406                                                        &tnapi->tx_desc_mapping);
6407                         if (!tnapi->tx_ring)
6408                                 goto err_out;
6409                 }
6410
6411                 /*
6412                  * When RSS is enabled, the status block format changes
6413                  * slightly.  The "rx_jumbo_consumer", "reserved",
6414                  * and "rx_mini_consumer" members get mapped to the
6415                  * other three rx return ring producer indexes.
6416                  */
6417                 switch (i) {
6418                 default:
6419                         tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6420                         break;
6421                 case 2:
6422                         tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6423                         break;
6424                 case 3:
6425                         tnapi->rx_rcb_prod_idx = &sblk->reserved;
6426                         break;
6427                 case 4:
6428                         tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6429                         break;
6430                 }
6431
6432                 tnapi->prodring = &tp->prodring[i];
6433
6434                 /*
6435                  * If multivector RSS is enabled, vector 0 does not handle
6436                  * rx or tx interrupts.  Don't allocate any resources for it.
6437                  */
6438                 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6439                         continue;
6440
6441                 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6442                                                      TG3_RX_RCB_RING_BYTES(tp),
6443                                                      &tnapi->rx_rcb_mapping);
6444                 if (!tnapi->rx_rcb)
6445                         goto err_out;
6446
6447                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6448         }
6449
6450         return 0;
6451
6452 err_out:
6453         tg3_free_consistent(tp);
6454         return -ENOMEM;
6455 }
6456
6457 #define MAX_WAIT_CNT 1000
6458
6459 /* To stop a block, clear the enable bit and poll till it
6460  * clears.  tp->lock is held.
6461  */
6462 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6463 {
6464         unsigned int i;
6465         u32 val;
6466
6467         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6468                 switch (ofs) {
6469                 case RCVLSC_MODE:
6470                 case DMAC_MODE:
6471                 case MBFREE_MODE:
6472                 case BUFMGR_MODE:
6473                 case MEMARB_MODE:
6474                         /* We can't enable/disable these bits of the
6475                          * 5705/5750, just say success.
6476                          */
6477                         return 0;
6478
6479                 default:
6480                         break;
6481                 }
6482         }
6483
6484         val = tr32(ofs);
6485         val &= ~enable_bit;
6486         tw32_f(ofs, val);
6487
6488         for (i = 0; i < MAX_WAIT_CNT; i++) {
6489                 udelay(100);
6490                 val = tr32(ofs);
6491                 if ((val & enable_bit) == 0)
6492                         break;
6493         }
6494
6495         if (i == MAX_WAIT_CNT && !silent) {
6496                 dev_err(&tp->pdev->dev,
6497                         "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6498                         ofs, enable_bit);
6499                 return -ENODEV;
6500         }
6501
6502         return 0;
6503 }
6504
6505 /* tp->lock is held. */
6506 static int tg3_abort_hw(struct tg3 *tp, int silent)
6507 {
6508         int i, err;
6509
6510         tg3_disable_ints(tp);
6511
6512         tp->rx_mode &= ~RX_MODE_ENABLE;
6513         tw32_f(MAC_RX_MODE, tp->rx_mode);
6514         udelay(10);
6515
6516         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6517         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6518         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6519         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6520         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6521         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6522
6523         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6524         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6525         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6526         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6527         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6528         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6529         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6530
6531         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6532         tw32_f(MAC_MODE, tp->mac_mode);
6533         udelay(40);
6534
6535         tp->tx_mode &= ~TX_MODE_ENABLE;
6536         tw32_f(MAC_TX_MODE, tp->tx_mode);
6537
6538         for (i = 0; i < MAX_WAIT_CNT; i++) {
6539                 udelay(100);
6540                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6541                         break;
6542         }
6543         if (i >= MAX_WAIT_CNT) {
6544                 dev_err(&tp->pdev->dev,
6545                         "%s timed out, TX_MODE_ENABLE will not clear "
6546                         "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
6547                 err |= -ENODEV;
6548         }
6549
6550         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6551         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6552         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6553
6554         tw32(FTQ_RESET, 0xffffffff);
6555         tw32(FTQ_RESET, 0x00000000);
6556
6557         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6558         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6559
6560         for (i = 0; i < tp->irq_cnt; i++) {
6561                 struct tg3_napi *tnapi = &tp->napi[i];
6562                 if (tnapi->hw_status)
6563                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6564         }
6565         if (tp->hw_stats)
6566                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6567
6568         return err;
6569 }
6570
6571 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6572 {
6573         int i;
6574         u32 apedata;
6575
6576         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6577         if (apedata != APE_SEG_SIG_MAGIC)
6578                 return;
6579
6580         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6581         if (!(apedata & APE_FW_STATUS_READY))
6582                 return;
6583
6584         /* Wait for up to 1 millisecond for APE to service previous event. */
6585         for (i = 0; i < 10; i++) {
6586                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6587                         return;
6588
6589                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6590
6591                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6592                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6593                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6594
6595                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6596
6597                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6598                         break;
6599
6600                 udelay(100);
6601         }
6602
6603         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6604                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6605 }
6606
6607 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6608 {
6609         u32 event;
6610         u32 apedata;
6611
6612         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6613                 return;
6614
6615         switch (kind) {
6616         case RESET_KIND_INIT:
6617                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6618                                 APE_HOST_SEG_SIG_MAGIC);
6619                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6620                                 APE_HOST_SEG_LEN_MAGIC);
6621                 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6622                 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6623                 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6624                                 APE_HOST_DRIVER_ID_MAGIC);
6625                 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6626                                 APE_HOST_BEHAV_NO_PHYLOCK);
6627
6628                 event = APE_EVENT_STATUS_STATE_START;
6629                 break;
6630         case RESET_KIND_SHUTDOWN:
6631                 /* With the interface we are currently using,
6632                  * APE does not track driver state.  Wiping
6633                  * out the HOST SEGMENT SIGNATURE forces
6634                  * the APE to assume OS absent status.
6635                  */
6636                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6637
6638                 event = APE_EVENT_STATUS_STATE_UNLOAD;
6639                 break;
6640         case RESET_KIND_SUSPEND:
6641                 event = APE_EVENT_STATUS_STATE_SUSPEND;
6642                 break;
6643         default:
6644                 return;
6645         }
6646
6647         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6648
6649         tg3_ape_send_event(tp, event);
6650 }
6651
6652 /* tp->lock is held. */
6653 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6654 {
6655         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6656                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6657
6658         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6659                 switch (kind) {
6660                 case RESET_KIND_INIT:
6661                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6662                                       DRV_STATE_START);
6663                         break;
6664
6665                 case RESET_KIND_SHUTDOWN:
6666                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6667                                       DRV_STATE_UNLOAD);
6668                         break;
6669
6670                 case RESET_KIND_SUSPEND:
6671                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6672                                       DRV_STATE_SUSPEND);
6673                         break;
6674
6675                 default:
6676                         break;
6677                 }
6678         }
6679
6680         if (kind == RESET_KIND_INIT ||
6681             kind == RESET_KIND_SUSPEND)
6682                 tg3_ape_driver_state_change(tp, kind);
6683 }
6684
6685 /* tp->lock is held. */
6686 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6687 {
6688         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6689                 switch (kind) {
6690                 case RESET_KIND_INIT:
6691                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6692                                       DRV_STATE_START_DONE);
6693                         break;
6694
6695                 case RESET_KIND_SHUTDOWN:
6696                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6697                                       DRV_STATE_UNLOAD_DONE);
6698                         break;
6699
6700                 default:
6701                         break;
6702                 }
6703         }
6704
6705         if (kind == RESET_KIND_SHUTDOWN)
6706                 tg3_ape_driver_state_change(tp, kind);
6707 }
6708
6709 /* tp->lock is held. */
6710 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6711 {
6712         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6713                 switch (kind) {
6714                 case RESET_KIND_INIT:
6715                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6716                                       DRV_STATE_START);
6717                         break;
6718
6719                 case RESET_KIND_SHUTDOWN:
6720                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6721                                       DRV_STATE_UNLOAD);
6722                         break;
6723
6724                 case RESET_KIND_SUSPEND:
6725                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6726                                       DRV_STATE_SUSPEND);
6727                         break;
6728
6729                 default:
6730                         break;
6731                 }
6732         }
6733 }
6734
6735 static int tg3_poll_fw(struct tg3 *tp)
6736 {
6737         int i;
6738         u32 val;
6739
6740         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6741                 /* Wait up to 20ms for init done. */
6742                 for (i = 0; i < 200; i++) {
6743                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6744                                 return 0;
6745                         udelay(100);
6746                 }
6747                 return -ENODEV;
6748         }
6749
6750         /* Wait for firmware initialization to complete. */
6751         for (i = 0; i < 100000; i++) {
6752                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6753                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6754                         break;
6755                 udelay(10);
6756         }
6757
6758         /* Chip might not be fitted with firmware.  Some Sun onboard
6759          * parts are configured like that.  So don't signal the timeout
6760          * of the above loop as an error, but do report the lack of
6761          * running firmware once.
6762          */
6763         if (i >= 100000 &&
6764             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6765                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6766
6767                 netdev_info(tp->dev, "No firmware running\n");
6768         }
6769
6770         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6771                 /* The 57765 A0 needs a little more
6772                  * time to do some important work.
6773                  */
6774                 mdelay(10);
6775         }
6776
6777         return 0;
6778 }
6779
6780 /* Save PCI command register before chip reset */
6781 static void tg3_save_pci_state(struct tg3 *tp)
6782 {
6783         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6784 }
6785
6786 /* Restore PCI state after chip reset */
6787 static void tg3_restore_pci_state(struct tg3 *tp)
6788 {
6789         u32 val;
6790
6791         /* Re-enable indirect register accesses. */
6792         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6793                                tp->misc_host_ctrl);
6794
6795         /* Set MAX PCI retry to zero. */
6796         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6797         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6798             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6799                 val |= PCISTATE_RETRY_SAME_DMA;
6800         /* Allow reads and writes to the APE register and memory space. */
6801         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6802                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6803                        PCISTATE_ALLOW_APE_SHMEM_WR |
6804                        PCISTATE_ALLOW_APE_PSPACE_WR;
6805         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6806
6807         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6808
6809         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6810                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6811                         pcie_set_readrq(tp->pdev, 4096);
6812                 else {
6813                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6814                                               tp->pci_cacheline_sz);
6815                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6816                                               tp->pci_lat_timer);
6817                 }
6818         }
6819
6820         /* Make sure PCI-X relaxed ordering bit is clear. */
6821         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6822                 u16 pcix_cmd;
6823
6824                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6825                                      &pcix_cmd);
6826                 pcix_cmd &= ~PCI_X_CMD_ERO;
6827                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6828                                       pcix_cmd);
6829         }
6830
6831         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6832
6833                 /* Chip reset on 5780 will reset MSI enable bit,
6834                  * so need to restore it.
6835                  */
6836                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6837                         u16 ctrl;
6838
6839                         pci_read_config_word(tp->pdev,
6840                                              tp->msi_cap + PCI_MSI_FLAGS,
6841                                              &ctrl);
6842                         pci_write_config_word(tp->pdev,
6843                                               tp->msi_cap + PCI_MSI_FLAGS,
6844                                               ctrl | PCI_MSI_FLAGS_ENABLE);
6845                         val = tr32(MSGINT_MODE);
6846                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6847                 }
6848         }
6849 }
6850
6851 static void tg3_stop_fw(struct tg3 *);
6852
6853 /* tp->lock is held. */
6854 static int tg3_chip_reset(struct tg3 *tp)
6855 {
6856         u32 val;
6857         void (*write_op)(struct tg3 *, u32, u32);
6858         int i, err;
6859
6860         tg3_nvram_lock(tp);
6861
6862         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6863
6864         /* No matching tg3_nvram_unlock() after this because
6865          * chip reset below will undo the nvram lock.
6866          */
6867         tp->nvram_lock_cnt = 0;
6868
6869         /* GRC_MISC_CFG core clock reset will clear the memory
6870          * enable bit in PCI register 4 and the MSI enable bit
6871          * on some chips, so we save relevant registers here.
6872          */
6873         tg3_save_pci_state(tp);
6874
6875         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6876             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6877                 tw32(GRC_FASTBOOT_PC, 0);
6878
6879         /*
6880          * We must avoid the readl() that normally takes place.
6881          * It locks machines, causes machine checks, and other
6882          * fun things.  So, temporarily disable the 5701
6883          * hardware workaround, while we do the reset.
6884          */
6885         write_op = tp->write32;
6886         if (write_op == tg3_write_flush_reg32)
6887                 tp->write32 = tg3_write32;
6888
6889         /* Prevent the irq handler from reading or writing PCI registers
6890          * during chip reset when the memory enable bit in the PCI command
6891          * register may be cleared.  The chip does not generate interrupt
6892          * at this time, but the irq handler may still be called due to irq
6893          * sharing or irqpoll.
6894          */
6895         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6896         for (i = 0; i < tp->irq_cnt; i++) {
6897                 struct tg3_napi *tnapi = &tp->napi[i];
6898                 if (tnapi->hw_status) {
6899                         tnapi->hw_status->status = 0;
6900                         tnapi->hw_status->status_tag = 0;
6901                 }
6902                 tnapi->last_tag = 0;
6903                 tnapi->last_irq_tag = 0;
6904         }
6905         smp_mb();
6906
6907         for (i = 0; i < tp->irq_cnt; i++)
6908                 synchronize_irq(tp->napi[i].irq_vec);
6909
6910         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6911                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6912                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6913         }
6914
6915         /* do the reset */
6916         val = GRC_MISC_CFG_CORECLK_RESET;
6917
6918         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6919                 if (tr32(0x7e2c) == 0x60) {
6920                         tw32(0x7e2c, 0x20);
6921                 }
6922                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6923                         tw32(GRC_MISC_CFG, (1 << 29));
6924                         val |= (1 << 29);
6925                 }
6926         }
6927
6928         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6929                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6930                 tw32(GRC_VCPU_EXT_CTRL,
6931                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6932         }
6933
6934         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6935                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6936         tw32(GRC_MISC_CFG, val);
6937
6938         /* restore 5701 hardware bug workaround write method */
6939         tp->write32 = write_op;
6940
6941         /* Unfortunately, we have to delay before the PCI read back.
6942          * Some 575X chips even will not respond to a PCI cfg access
6943          * when the reset command is given to the chip.
6944          *
6945          * How do these hardware designers expect things to work
6946          * properly if the PCI write is posted for a long period
6947          * of time?  It is always necessary to have some method by
6948          * which a register read back can occur to push the write
6949          * out which does the reset.
6950          *
6951          * For most tg3 variants the trick below was working.
6952          * Ho hum...
6953          */
6954         udelay(120);
6955
6956         /* Flush PCI posted writes.  The normal MMIO registers
6957          * are inaccessible at this time so this is the only
6958          * way to make this reliably (actually, this is no longer
6959          * the case, see above).  I tried to use indirect
6960          * register read/write but this upset some 5701 variants.
6961          */
6962         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6963
6964         udelay(120);
6965
6966         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6967                 u16 val16;
6968
6969                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6970                         int i;
6971                         u32 cfg_val;
6972
6973                         /* Wait for link training to complete.  */
6974                         for (i = 0; i < 5000; i++)
6975                                 udelay(100);
6976
6977                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6978                         pci_write_config_dword(tp->pdev, 0xc4,
6979                                                cfg_val | (1 << 15));
6980                 }
6981
6982                 /* Clear the "no snoop" and "relaxed ordering" bits. */
6983                 pci_read_config_word(tp->pdev,
6984                                      tp->pcie_cap + PCI_EXP_DEVCTL,
6985                                      &val16);
6986                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6987                            PCI_EXP_DEVCTL_NOSNOOP_EN);
6988                 /*
6989                  * Older PCIe devices only support the 128 byte
6990                  * MPS setting.  Enforce the restriction.
6991                  */
6992                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6993                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6994                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
6995                 pci_write_config_word(tp->pdev,
6996                                       tp->pcie_cap + PCI_EXP_DEVCTL,
6997                                       val16);
6998
6999                 pcie_set_readrq(tp->pdev, 4096);
7000
7001                 /* Clear error status */
7002                 pci_write_config_word(tp->pdev,
7003                                       tp->pcie_cap + PCI_EXP_DEVSTA,
7004                                       PCI_EXP_DEVSTA_CED |
7005                                       PCI_EXP_DEVSTA_NFED |
7006                                       PCI_EXP_DEVSTA_FED |
7007                                       PCI_EXP_DEVSTA_URD);
7008         }
7009
7010         tg3_restore_pci_state(tp);
7011
7012         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
7013
7014         val = 0;
7015         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
7016                 val = tr32(MEMARB_MODE);
7017         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7018
7019         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7020                 tg3_stop_fw(tp);
7021                 tw32(0x5000, 0x400);
7022         }
7023
7024         tw32(GRC_MODE, tp->grc_mode);
7025
7026         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
7027                 val = tr32(0xc4);
7028
7029                 tw32(0xc4, val | (1 << 15));
7030         }
7031
7032         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7033             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7034                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7035                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7036                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7037                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7038         }
7039
7040         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7041                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
7042                 tw32_f(MAC_MODE, tp->mac_mode);
7043         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7044                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
7045                 tw32_f(MAC_MODE, tp->mac_mode);
7046         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7047                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
7048                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
7049                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
7050                 tw32_f(MAC_MODE, tp->mac_mode);
7051         } else
7052                 tw32_f(MAC_MODE, 0);
7053         udelay(40);
7054
7055         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7056
7057         err = tg3_poll_fw(tp);
7058         if (err)
7059                 return err;
7060
7061         tg3_mdio_start(tp);
7062
7063         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7064                 u8 phy_addr;
7065
7066                 phy_addr = tp->phy_addr;
7067                 tp->phy_addr = TG3_PHY_PCIE_ADDR;
7068
7069                 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
7070                              TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
7071                 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
7072                       TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
7073                       TG3_PCIEPHY_TX0CTRL1_NB_EN;
7074                 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
7075                 udelay(10);
7076
7077                 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
7078                              TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
7079                 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
7080                       TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
7081                 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
7082                 udelay(10);
7083
7084                 tp->phy_addr = phy_addr;
7085         }
7086
7087         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
7088             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7089             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7090             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
7091             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719 &&
7092             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
7093                 val = tr32(0x7c00);
7094
7095                 tw32(0x7c00, val | (1 << 25));
7096         }
7097
7098         /* Reprobe ASF enable state.  */
7099         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7100         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7101         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7102         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7103                 u32 nic_cfg;
7104
7105                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7106                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7107                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7108                         tp->last_event_jiffies = jiffies;
7109                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7110                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7111                 }
7112         }
7113
7114         return 0;
7115 }
7116
7117 /* tp->lock is held. */
7118 static void tg3_stop_fw(struct tg3 *tp)
7119 {
7120         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7121            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7122                 /* Wait for RX cpu to ACK the previous event. */
7123                 tg3_wait_for_event_ack(tp);
7124
7125                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7126
7127                 tg3_generate_fw_event(tp);
7128
7129                 /* Wait for RX cpu to ACK this event. */
7130                 tg3_wait_for_event_ack(tp);
7131         }
7132 }
7133
7134 /* tp->lock is held. */
7135 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7136 {
7137         int err;
7138
7139         tg3_stop_fw(tp);
7140
7141         tg3_write_sig_pre_reset(tp, kind);
7142
7143         tg3_abort_hw(tp, silent);
7144         err = tg3_chip_reset(tp);
7145
7146         __tg3_set_mac_addr(tp, 0);
7147
7148         tg3_write_sig_legacy(tp, kind);
7149         tg3_write_sig_post_reset(tp, kind);
7150
7151         if (err)
7152                 return err;
7153
7154         return 0;
7155 }
7156
7157 #define RX_CPU_SCRATCH_BASE     0x30000
7158 #define RX_CPU_SCRATCH_SIZE     0x04000
7159 #define TX_CPU_SCRATCH_BASE     0x34000
7160 #define TX_CPU_SCRATCH_SIZE     0x04000
7161
7162 /* tp->lock is held. */
7163 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7164 {
7165         int i;
7166
7167         BUG_ON(offset == TX_CPU_BASE &&
7168             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7169
7170         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7171                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7172
7173                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7174                 return 0;
7175         }
7176         if (offset == RX_CPU_BASE) {
7177                 for (i = 0; i < 10000; i++) {
7178                         tw32(offset + CPU_STATE, 0xffffffff);
7179                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7180                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7181                                 break;
7182                 }
7183
7184                 tw32(offset + CPU_STATE, 0xffffffff);
7185                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
7186                 udelay(10);
7187         } else {
7188                 for (i = 0; i < 10000; i++) {
7189                         tw32(offset + CPU_STATE, 0xffffffff);
7190                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7191                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7192                                 break;
7193                 }
7194         }
7195
7196         if (i >= 10000) {
7197                 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7198                            __func__, offset == RX_CPU_BASE ? "RX" : "TX");
7199                 return -ENODEV;
7200         }
7201
7202         /* Clear firmware's nvram arbitration. */
7203         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7204                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7205         return 0;
7206 }
7207
7208 struct fw_info {
7209         unsigned int fw_base;
7210         unsigned int fw_len;
7211         const __be32 *fw_data;
7212 };
7213
7214 /* tp->lock is held. */
7215 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7216                                  int cpu_scratch_size, struct fw_info *info)
7217 {
7218         int err, lock_err, i;
7219         void (*write_op)(struct tg3 *, u32, u32);
7220
7221         if (cpu_base == TX_CPU_BASE &&
7222             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7223                 netdev_err(tp->dev,
7224                            "%s: Trying to load TX cpu firmware which is 5705\n",
7225                            __func__);
7226                 return -EINVAL;
7227         }
7228
7229         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7230                 write_op = tg3_write_mem;
7231         else
7232                 write_op = tg3_write_indirect_reg32;
7233
7234         /* It is possible that bootcode is still loading at this point.
7235          * Get the nvram lock first before halting the cpu.
7236          */
7237         lock_err = tg3_nvram_lock(tp);
7238         err = tg3_halt_cpu(tp, cpu_base);
7239         if (!lock_err)
7240                 tg3_nvram_unlock(tp);
7241         if (err)
7242                 goto out;
7243
7244         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7245                 write_op(tp, cpu_scratch_base + i, 0);
7246         tw32(cpu_base + CPU_STATE, 0xffffffff);
7247         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7248         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7249                 write_op(tp, (cpu_scratch_base +
7250                               (info->fw_base & 0xffff) +
7251                               (i * sizeof(u32))),
7252                               be32_to_cpu(info->fw_data[i]));
7253
7254         err = 0;
7255
7256 out:
7257         return err;
7258 }
7259
7260 /* tp->lock is held. */
7261 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7262 {
7263         struct fw_info info;
7264         const __be32 *fw_data;
7265         int err, i;
7266
7267         fw_data = (void *)tp->fw->data;
7268
7269         /* Firmware blob starts with version numbers, followed by
7270            start address and length. We are setting complete length.
7271            length = end_address_of_bss - start_address_of_text.
7272            Remainder is the blob to be loaded contiguously
7273            from start address. */
7274
7275         info.fw_base = be32_to_cpu(fw_data[1]);
7276         info.fw_len = tp->fw->size - 12;
7277         info.fw_data = &fw_data[3];
7278
7279         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7280                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7281                                     &info);
7282         if (err)
7283                 return err;
7284
7285         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7286                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7287                                     &info);
7288         if (err)
7289                 return err;
7290
7291         /* Now startup only the RX cpu. */
7292         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7293         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7294
7295         for (i = 0; i < 5; i++) {
7296                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7297                         break;
7298                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7299                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
7300                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7301                 udelay(1000);
7302         }
7303         if (i >= 5) {
7304                 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7305                            "should be %08x\n", __func__,
7306                            tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
7307                 return -ENODEV;
7308         }
7309         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7310         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
7311
7312         return 0;
7313 }
7314
7315 /* 5705 needs a special version of the TSO firmware.  */
7316
7317 /* tp->lock is held. */
7318 static int tg3_load_tso_firmware(struct tg3 *tp)
7319 {
7320         struct fw_info info;
7321         const __be32 *fw_data;
7322         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7323         int err, i;
7324
7325         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7326                 return 0;
7327
7328         fw_data = (void *)tp->fw->data;
7329
7330         /* Firmware blob starts with version numbers, followed by
7331            start address and length. We are setting complete length.
7332            length = end_address_of_bss - start_address_of_text.
7333            Remainder is the blob to be loaded contiguously
7334            from start address. */
7335
7336         info.fw_base = be32_to_cpu(fw_data[1]);
7337         cpu_scratch_size = tp->fw_len;
7338         info.fw_len = tp->fw->size - 12;
7339         info.fw_data = &fw_data[3];
7340
7341         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7342                 cpu_base = RX_CPU_BASE;
7343                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7344         } else {
7345                 cpu_base = TX_CPU_BASE;
7346                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7347                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7348         }
7349
7350         err = tg3_load_firmware_cpu(tp, cpu_base,
7351                                     cpu_scratch_base, cpu_scratch_size,
7352                                     &info);
7353         if (err)
7354                 return err;
7355
7356         /* Now startup the cpu. */
7357         tw32(cpu_base + CPU_STATE, 0xffffffff);
7358         tw32_f(cpu_base + CPU_PC, info.fw_base);
7359
7360         for (i = 0; i < 5; i++) {
7361                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7362                         break;
7363                 tw32(cpu_base + CPU_STATE, 0xffffffff);
7364                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
7365                 tw32_f(cpu_base + CPU_PC, info.fw_base);
7366                 udelay(1000);
7367         }
7368         if (i >= 5) {
7369                 netdev_err(tp->dev,
7370                            "%s fails to set CPU PC, is %08x should be %08x\n",
7371                            __func__, tr32(cpu_base + CPU_PC), info.fw_base);
7372                 return -ENODEV;
7373         }
7374         tw32(cpu_base + CPU_STATE, 0xffffffff);
7375         tw32_f(cpu_base + CPU_MODE,  0x00000000);
7376         return 0;
7377 }
7378
7379
7380 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7381 {
7382         struct tg3 *tp = netdev_priv(dev);
7383         struct sockaddr *addr = p;
7384         int err = 0, skip_mac_1 = 0;
7385
7386         if (!is_valid_ether_addr(addr->sa_data))
7387                 return -EINVAL;
7388
7389         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7390
7391         if (!netif_running(dev))
7392                 return 0;
7393
7394         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7395                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7396
7397                 addr0_high = tr32(MAC_ADDR_0_HIGH);
7398                 addr0_low = tr32(MAC_ADDR_0_LOW);
7399                 addr1_high = tr32(MAC_ADDR_1_HIGH);
7400                 addr1_low = tr32(MAC_ADDR_1_LOW);
7401
7402                 /* Skip MAC addr 1 if ASF is using it. */
7403                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7404                     !(addr1_high == 0 && addr1_low == 0))
7405                         skip_mac_1 = 1;
7406         }
7407         spin_lock_bh(&tp->lock);
7408         __tg3_set_mac_addr(tp, skip_mac_1);
7409         spin_unlock_bh(&tp->lock);
7410
7411         return err;
7412 }
7413
7414 /* tp->lock is held. */
7415 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7416                            dma_addr_t mapping, u32 maxlen_flags,
7417                            u32 nic_addr)
7418 {
7419         tg3_write_mem(tp,
7420                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7421                       ((u64) mapping >> 32));
7422         tg3_write_mem(tp,
7423                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7424                       ((u64) mapping & 0xffffffff));
7425         tg3_write_mem(tp,
7426                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7427                        maxlen_flags);
7428
7429         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7430                 tg3_write_mem(tp,
7431                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7432                               nic_addr);
7433 }
7434
7435 static void __tg3_set_rx_mode(struct net_device *);
7436 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7437 {
7438         int i;
7439
7440         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7441                 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7442                 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7443                 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7444         } else {
7445                 tw32(HOSTCC_TXCOL_TICKS, 0);
7446                 tw32(HOSTCC_TXMAX_FRAMES, 0);
7447                 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7448         }
7449
7450         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7451                 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7452                 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7453                 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7454         } else {
7455                 tw32(HOSTCC_RXCOL_TICKS, 0);
7456                 tw32(HOSTCC_RXMAX_FRAMES, 0);
7457                 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7458         }
7459
7460         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7461                 u32 val = ec->stats_block_coalesce_usecs;
7462
7463                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7464                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7465
7466                 if (!netif_carrier_ok(tp->dev))
7467                         val = 0;
7468
7469                 tw32(HOSTCC_STAT_COAL_TICKS, val);
7470         }
7471
7472         for (i = 0; i < tp->irq_cnt - 1; i++) {
7473                 u32 reg;
7474
7475                 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7476                 tw32(reg, ec->rx_coalesce_usecs);
7477                 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7478                 tw32(reg, ec->rx_max_coalesced_frames);
7479                 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7480                 tw32(reg, ec->rx_max_coalesced_frames_irq);
7481
7482                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7483                         reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7484                         tw32(reg, ec->tx_coalesce_usecs);
7485                         reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7486                         tw32(reg, ec->tx_max_coalesced_frames);
7487                         reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7488                         tw32(reg, ec->tx_max_coalesced_frames_irq);
7489                 }
7490         }
7491
7492         for (; i < tp->irq_max - 1; i++) {
7493                 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7494                 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7495                 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7496
7497                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7498                         tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7499                         tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7500                         tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7501                 }
7502         }
7503 }
7504
7505 /* tp->lock is held. */
7506 static void tg3_rings_reset(struct tg3 *tp)
7507 {
7508         int i;
7509         u32 stblk, txrcb, rxrcb, limit;
7510         struct tg3_napi *tnapi = &tp->napi[0];
7511
7512         /* Disable all transmit rings but the first. */
7513         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7514                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7515         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7516                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7517         else
7518                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7519
7520         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7521              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7522                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7523                               BDINFO_FLAGS_DISABLED);
7524
7525
7526         /* Disable all receive return rings but the first. */
7527         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7528             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7529                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7530         else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7531                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7532         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7533                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7534                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7535         else
7536                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7537
7538         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7539              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7540                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7541                               BDINFO_FLAGS_DISABLED);
7542
7543         /* Disable interrupts */
7544         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7545
7546         /* Zero mailbox registers. */
7547         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7548                 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7549                         tp->napi[i].tx_prod = 0;
7550                         tp->napi[i].tx_cons = 0;
7551                         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7552                                 tw32_mailbox(tp->napi[i].prodmbox, 0);
7553                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
7554                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7555                 }
7556                 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7557                         tw32_mailbox(tp->napi[0].prodmbox, 0);
7558         } else {
7559                 tp->napi[0].tx_prod = 0;
7560                 tp->napi[0].tx_cons = 0;
7561                 tw32_mailbox(tp->napi[0].prodmbox, 0);
7562                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7563         }
7564
7565         /* Make sure the NIC-based send BD rings are disabled. */
7566         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7567                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7568                 for (i = 0; i < 16; i++)
7569                         tw32_tx_mbox(mbox + i * 8, 0);
7570         }
7571
7572         txrcb = NIC_SRAM_SEND_RCB;
7573         rxrcb = NIC_SRAM_RCV_RET_RCB;
7574
7575         /* Clear status block in ram. */
7576         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7577
7578         /* Set status block DMA address */
7579         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7580              ((u64) tnapi->status_mapping >> 32));
7581         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7582              ((u64) tnapi->status_mapping & 0xffffffff));
7583
7584         if (tnapi->tx_ring) {
7585                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7586                                (TG3_TX_RING_SIZE <<
7587                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7588                                NIC_SRAM_TX_BUFFER_DESC);
7589                 txrcb += TG3_BDINFO_SIZE;
7590         }
7591
7592         if (tnapi->rx_rcb) {
7593                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7594                                (TG3_RX_RCB_RING_SIZE(tp) <<
7595                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7596                 rxrcb += TG3_BDINFO_SIZE;
7597         }
7598
7599         stblk = HOSTCC_STATBLCK_RING1;
7600
7601         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7602                 u64 mapping = (u64)tnapi->status_mapping;
7603                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7604                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7605
7606                 /* Clear status block in ram. */
7607                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7608
7609                 if (tnapi->tx_ring) {
7610                         tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7611                                        (TG3_TX_RING_SIZE <<
7612                                         BDINFO_FLAGS_MAXLEN_SHIFT),
7613                                        NIC_SRAM_TX_BUFFER_DESC);
7614                         txrcb += TG3_BDINFO_SIZE;
7615                 }
7616
7617                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7618                                (TG3_RX_RCB_RING_SIZE(tp) <<
7619                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7620
7621                 stblk += 8;
7622                 rxrcb += TG3_BDINFO_SIZE;
7623         }
7624 }
7625
7626 /* tp->lock is held. */
7627 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7628 {
7629         u32 val, rdmac_mode;
7630         int i, err, limit;
7631         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
7632
7633         tg3_disable_ints(tp);
7634
7635         tg3_stop_fw(tp);
7636
7637         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7638
7639         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
7640                 tg3_abort_hw(tp, 1);
7641
7642         if (reset_phy)
7643                 tg3_phy_reset(tp);
7644
7645         err = tg3_chip_reset(tp);
7646         if (err)
7647                 return err;
7648
7649         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7650
7651         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7652                 val = tr32(TG3_CPMU_CTRL);
7653                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7654                 tw32(TG3_CPMU_CTRL, val);
7655
7656                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7657                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7658                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7659                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7660
7661                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7662                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7663                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7664                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7665
7666                 val = tr32(TG3_CPMU_HST_ACC);
7667                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7668                 val |= CPMU_HST_ACC_MACCLK_6_25;
7669                 tw32(TG3_CPMU_HST_ACC, val);
7670         }
7671
7672         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7673                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7674                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7675                        PCIE_PWR_MGMT_L1_THRESH_4MS;
7676                 tw32(PCIE_PWR_MGMT_THRESH, val);
7677
7678                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7679                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7680
7681                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7682
7683                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7684                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7685         }
7686
7687         if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7688                 u32 grc_mode = tr32(GRC_MODE);
7689
7690                 /* Access the lower 1K of PL PCIE block registers. */
7691                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7692                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7693
7694                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7695                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7696                      val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7697
7698                 tw32(GRC_MODE, grc_mode);
7699         }
7700
7701         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
7702                 u32 grc_mode = tr32(GRC_MODE);
7703
7704                 /* Access the lower 1K of PL PCIE block registers. */
7705                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7706                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7707
7708                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5);
7709                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
7710                      val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
7711
7712                 tw32(GRC_MODE, grc_mode);
7713
7714                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7715                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7716                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7717                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7718         }
7719
7720         /* This works around an issue with Athlon chipsets on
7721          * B3 tigon3 silicon.  This bit has no effect on any
7722          * other revision.  But do not set this on PCI Express
7723          * chips and don't even touch the clocks if the CPMU is present.
7724          */
7725         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7726                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7727                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7728                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7729         }
7730
7731         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7732             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7733                 val = tr32(TG3PCI_PCISTATE);
7734                 val |= PCISTATE_RETRY_SAME_DMA;
7735                 tw32(TG3PCI_PCISTATE, val);
7736         }
7737
7738         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7739                 /* Allow reads and writes to the
7740                  * APE register and memory space.
7741                  */
7742                 val = tr32(TG3PCI_PCISTATE);
7743                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7744                        PCISTATE_ALLOW_APE_SHMEM_WR |
7745                        PCISTATE_ALLOW_APE_PSPACE_WR;
7746                 tw32(TG3PCI_PCISTATE, val);
7747         }
7748
7749         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7750                 /* Enable some hw fixes.  */
7751                 val = tr32(TG3PCI_MSI_DATA);
7752                 val |= (1 << 26) | (1 << 28) | (1 << 29);
7753                 tw32(TG3PCI_MSI_DATA, val);
7754         }
7755
7756         /* Descriptor ring init may make accesses to the
7757          * NIC SRAM area to setup the TX descriptors, so we
7758          * can only do this after the hardware has been
7759          * successfully reset.
7760          */
7761         err = tg3_init_rings(tp);
7762         if (err)
7763                 return err;
7764
7765         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7766             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
7767             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7768                 val = tr32(TG3PCI_DMA_RW_CTRL) &
7769                       ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7770                 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
7771                         val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
7772                 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7773         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7774                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7775                 /* This value is determined during the probe time DMA
7776                  * engine test, tg3_test_dma.
7777                  */
7778                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7779         }
7780
7781         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7782                           GRC_MODE_4X_NIC_SEND_RINGS |
7783                           GRC_MODE_NO_TX_PHDR_CSUM |
7784                           GRC_MODE_NO_RX_PHDR_CSUM);
7785         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7786
7787         /* Pseudo-header checksum is done by hardware logic and not
7788          * the offload processers, so make the chip do the pseudo-
7789          * header checksums on receive.  For transmit it is more
7790          * convenient to do the pseudo-header checksum in software
7791          * as Linux does that on transmit for us in all cases.
7792          */
7793         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7794
7795         tw32(GRC_MODE,
7796              tp->grc_mode |
7797              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7798
7799         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7800         val = tr32(GRC_MISC_CFG);
7801         val &= ~0xff;
7802         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7803         tw32(GRC_MISC_CFG, val);
7804
7805         /* Initialize MBUF/DESC pool. */
7806         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7807                 /* Do nothing.  */
7808         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7809                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7810                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7811                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7812                 else
7813                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7814                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7815                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7816         } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7817                 int fw_len;
7818
7819                 fw_len = tp->fw_len;
7820                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7821                 tw32(BUFMGR_MB_POOL_ADDR,
7822                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7823                 tw32(BUFMGR_MB_POOL_SIZE,
7824                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7825         }
7826
7827         if (tp->dev->mtu <= ETH_DATA_LEN) {
7828                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7829                      tp->bufmgr_config.mbuf_read_dma_low_water);
7830                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7831                      tp->bufmgr_config.mbuf_mac_rx_low_water);
7832                 tw32(BUFMGR_MB_HIGH_WATER,
7833                      tp->bufmgr_config.mbuf_high_water);
7834         } else {
7835                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7836                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7837                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7838                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7839                 tw32(BUFMGR_MB_HIGH_WATER,
7840                      tp->bufmgr_config.mbuf_high_water_jumbo);
7841         }
7842         tw32(BUFMGR_DMA_LOW_WATER,
7843              tp->bufmgr_config.dma_low_water);
7844         tw32(BUFMGR_DMA_HIGH_WATER,
7845              tp->bufmgr_config.dma_high_water);
7846
7847         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7848         for (i = 0; i < 2000; i++) {
7849                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7850                         break;
7851                 udelay(10);
7852         }
7853         if (i >= 2000) {
7854                 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
7855                 return -ENODEV;
7856         }
7857
7858         /* Setup replenish threshold. */
7859         val = tp->rx_pending / 8;
7860         if (val == 0)
7861                 val = 1;
7862         else if (val > tp->rx_std_max_post)
7863                 val = tp->rx_std_max_post;
7864         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7865                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7866                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7867
7868                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7869                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7870         }
7871
7872         tw32(RCVBDI_STD_THRESH, val);
7873
7874         /* Initialize TG3_BDINFO's at:
7875          *  RCVDBDI_STD_BD:     standard eth size rx ring
7876          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
7877          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
7878          *
7879          * like so:
7880          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
7881          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
7882          *                              ring attribute flags
7883          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
7884          *
7885          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7886          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7887          *
7888          * The size of each ring is fixed in the firmware, but the location is
7889          * configurable.
7890          */
7891         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7892              ((u64) tpr->rx_std_mapping >> 32));
7893         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7894              ((u64) tpr->rx_std_mapping & 0xffffffff));
7895         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
7896             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
7897                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7898                      NIC_SRAM_RX_BUFFER_DESC);
7899
7900         /* Disable the mini ring */
7901         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7902                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7903                      BDINFO_FLAGS_DISABLED);
7904
7905         /* Program the jumbo buffer descriptor ring control
7906          * blocks on those devices that have them.
7907          */
7908         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7909             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7910                 /* Setup replenish threshold. */
7911                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7912
7913                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7914                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7915                              ((u64) tpr->rx_jmb_mapping >> 32));
7916                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7917                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7918                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7919                              (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7920                              BDINFO_FLAGS_USE_EXT_RECV);
7921                         if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) ||
7922                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7923                                 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7924                                      NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7925                 } else {
7926                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7927                              BDINFO_FLAGS_DISABLED);
7928                 }
7929
7930                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7931                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
7932                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7933                         val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7934                               (TG3_RX_STD_DMA_SZ << 2);
7935                 else
7936                         val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
7937         } else
7938                 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7939
7940         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7941
7942         tpr->rx_std_prod_idx = tp->rx_pending;
7943         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
7944
7945         tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7946                           tp->rx_jumbo_pending : 0;
7947         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
7948
7949         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7950             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
7951             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7952                 tw32(STD_REPLENISH_LWM, 32);
7953                 tw32(JMB_REPLENISH_LWM, 16);
7954         }
7955
7956         tg3_rings_reset(tp);
7957
7958         /* Initialize MAC address and backoff seed. */
7959         __tg3_set_mac_addr(tp, 0);
7960
7961         /* MTU + ethernet header + FCS + optional VLAN tag */
7962         tw32(MAC_RX_MTU_SIZE,
7963              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7964
7965         /* The slot time is changed by tg3_setup_phy if we
7966          * run at gigabit with half duplex.
7967          */
7968         tw32(MAC_TX_LENGTHS,
7969              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7970              (6 << TX_LENGTHS_IPG_SHIFT) |
7971              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7972
7973         /* Receive rules. */
7974         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7975         tw32(RCVLPC_CONFIG, 0x0181);
7976
7977         /* Calculate RDMAC_MODE setting early, we need it to determine
7978          * the RCVLPC_STATE_ENABLE mask.
7979          */
7980         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7981                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7982                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7983                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7984                       RDMAC_MODE_LNGREAD_ENAB);
7985
7986         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7987             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7988                 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
7989
7990         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7991             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7992             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7993                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7994                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7995                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7996
7997         /* If statement applies to 5705 and 5750 PCI devices only */
7998         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7999              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8000             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
8001                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
8002                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
8003                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
8004                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8005                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
8006                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8007                 }
8008         }
8009
8010         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
8011                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8012
8013         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8014                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8015
8016         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
8017             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8018             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8019                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
8020
8021         /* Receive/send statistics. */
8022         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
8023                 val = tr32(RCVLPC_STATS_ENABLE);
8024                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8025                 tw32(RCVLPC_STATS_ENABLE, val);
8026         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8027                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8028                 val = tr32(RCVLPC_STATS_ENABLE);
8029                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8030                 tw32(RCVLPC_STATS_ENABLE, val);
8031         } else {
8032                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8033         }
8034         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8035         tw32(SNDDATAI_STATSENAB, 0xffffff);
8036         tw32(SNDDATAI_STATSCTRL,
8037              (SNDDATAI_SCTRL_ENABLE |
8038               SNDDATAI_SCTRL_FASTUPD));
8039
8040         /* Setup host coalescing engine. */
8041         tw32(HOSTCC_MODE, 0);
8042         for (i = 0; i < 2000; i++) {
8043                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8044                         break;
8045                 udelay(10);
8046         }
8047
8048         __tg3_set_coalesce(tp, &tp->coal);
8049
8050         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8051                 /* Status/statistics block address.  See tg3_timer,
8052                  * the tg3_periodic_fetch_stats call there, and
8053                  * tg3_get_stats to see how this works for 5705/5750 chips.
8054                  */
8055                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8056                      ((u64) tp->stats_mapping >> 32));
8057                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8058                      ((u64) tp->stats_mapping & 0xffffffff));
8059                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8060
8061                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
8062
8063                 /* Clear statistics and status block memory areas */
8064                 for (i = NIC_SRAM_STATS_BLK;
8065                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8066                      i += sizeof(u32)) {
8067                         tg3_write_mem(tp, i, 0);
8068                         udelay(40);
8069                 }
8070         }
8071
8072         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8073
8074         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8075         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8076         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8077                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8078
8079         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8080                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
8081                 /* reset to prevent losing 1st rx packet intermittently */
8082                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8083                 udelay(10);
8084         }
8085
8086         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8087                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8088         else
8089                 tp->mac_mode = 0;
8090         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8091                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
8092         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8093             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8094             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8095                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8096         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8097         udelay(40);
8098
8099         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8100          * If TG3_FLG2_IS_NIC is zero, we should read the
8101          * register to preserve the GPIO settings for LOMs. The GPIOs,
8102          * whether used as inputs or outputs, are set by boot code after
8103          * reset.
8104          */
8105         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
8106                 u32 gpio_mask;
8107
8108                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8109                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8110                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8111
8112                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8113                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8114                                      GRC_LCLCTRL_GPIO_OUTPUT3;
8115
8116                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8117                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8118
8119                 tp->grc_local_ctrl &= ~gpio_mask;
8120                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8121
8122                 /* GPIO1 must be driven high for eeprom write protect */
8123                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8124                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8125                                                GRC_LCLCTRL_GPIO_OUTPUT1);
8126         }
8127         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8128         udelay(100);
8129
8130         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
8131                 val = tr32(MSGINT_MODE);
8132                 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8133                 tw32(MSGINT_MODE, val);
8134         }
8135
8136         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8137                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8138                 udelay(40);
8139         }
8140
8141         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8142                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8143                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8144                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8145                WDMAC_MODE_LNGREAD_ENAB);
8146
8147         /* If statement applies to 5705 and 5750 PCI devices only */
8148         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8149              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8150             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
8151                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8152                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8153                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8154                         /* nothing */
8155                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8156                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8157                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8158                         val |= WDMAC_MODE_RX_ACCEL;
8159                 }
8160         }
8161
8162         /* Enable host coalescing bug fix */
8163         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8164                 val |= WDMAC_MODE_STATUS_TAG_FIX;
8165
8166         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8167                 val |= WDMAC_MODE_BURST_ALL_DATA;
8168
8169         tw32_f(WDMAC_MODE, val);
8170         udelay(40);
8171
8172         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8173                 u16 pcix_cmd;
8174
8175                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8176                                      &pcix_cmd);
8177                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8178                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8179                         pcix_cmd |= PCI_X_CMD_READ_2K;
8180                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8181                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8182                         pcix_cmd |= PCI_X_CMD_READ_2K;
8183                 }
8184                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8185                                       pcix_cmd);
8186         }
8187
8188         tw32_f(RDMAC_MODE, rdmac_mode);
8189         udelay(40);
8190
8191         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8192         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8193                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8194
8195         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8196                 tw32(SNDDATAC_MODE,
8197                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8198         else
8199                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8200
8201         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8202         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8203         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8204         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8205         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8206                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8207         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8208         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8209                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8210         tw32(SNDBDI_MODE, val);
8211         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8212
8213         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8214                 err = tg3_load_5701_a0_firmware_fix(tp);
8215                 if (err)
8216                         return err;
8217         }
8218
8219         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8220                 err = tg3_load_tso_firmware(tp);
8221                 if (err)
8222                         return err;
8223         }
8224
8225         tp->tx_mode = TX_MODE_ENABLE;
8226         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
8227             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8228                 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
8229         tw32_f(MAC_TX_MODE, tp->tx_mode);
8230         udelay(100);
8231
8232         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8233                 u32 reg = MAC_RSS_INDIR_TBL_0;
8234                 u8 *ent = (u8 *)&val;
8235
8236                 /* Setup the indirection table */
8237                 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8238                         int idx = i % sizeof(val);
8239
8240                         ent[idx] = i % (tp->irq_cnt - 1);
8241                         if (idx == sizeof(val) - 1) {
8242                                 tw32(reg, val);
8243                                 reg += 4;
8244                         }
8245                 }
8246
8247                 /* Setup the "secret" hash key. */
8248                 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8249                 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8250                 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8251                 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8252                 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8253                 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8254                 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8255                 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8256                 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8257                 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8258         }
8259
8260         tp->rx_mode = RX_MODE_ENABLE;
8261         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8262                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8263
8264         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8265                 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8266                                RX_MODE_RSS_ITBL_HASH_BITS_7 |
8267                                RX_MODE_RSS_IPV6_HASH_EN |
8268                                RX_MODE_RSS_TCP_IPV6_HASH_EN |
8269                                RX_MODE_RSS_IPV4_HASH_EN |
8270                                RX_MODE_RSS_TCP_IPV4_HASH_EN;
8271
8272         tw32_f(MAC_RX_MODE, tp->rx_mode);
8273         udelay(10);
8274
8275         tw32(MAC_LED_CTRL, tp->led_ctrl);
8276
8277         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8278         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8279                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8280                 udelay(10);
8281         }
8282         tw32_f(MAC_RX_MODE, tp->rx_mode);
8283         udelay(10);
8284
8285         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8286                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8287                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
8288                         /* Set drive transmission level to 1.2V  */
8289                         /* only if the signal pre-emphasis bit is not set  */
8290                         val = tr32(MAC_SERDES_CFG);
8291                         val &= 0xfffff000;
8292                         val |= 0x880;
8293                         tw32(MAC_SERDES_CFG, val);
8294                 }
8295                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8296                         tw32(MAC_SERDES_CFG, 0x616000);
8297         }
8298
8299         /* Prevent chip from dropping frames when flow control
8300          * is enabled.
8301          */
8302         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8303                 val = 1;
8304         else
8305                 val = 2;
8306         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8307
8308         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8309             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8310                 /* Use hardware link auto-negotiation */
8311                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8312         }
8313
8314         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8315             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8316                 u32 tmp;
8317
8318                 tmp = tr32(SERDES_RX_CTRL);
8319                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8320                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8321                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8322                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8323         }
8324
8325         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8326                 if (tp->link_config.phy_is_low_power) {
8327                         tp->link_config.phy_is_low_power = 0;
8328                         tp->link_config.speed = tp->link_config.orig_speed;
8329                         tp->link_config.duplex = tp->link_config.orig_duplex;
8330                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
8331                 }
8332
8333                 err = tg3_setup_phy(tp, 0);
8334                 if (err)
8335                         return err;
8336
8337                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8338                     !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
8339                         u32 tmp;
8340
8341                         /* Clear CRC stats. */
8342                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8343                                 tg3_writephy(tp, MII_TG3_TEST1,
8344                                              tmp | MII_TG3_TEST1_CRC_EN);
8345                                 tg3_readphy(tp, 0x14, &tmp);
8346                         }
8347                 }
8348         }
8349
8350         __tg3_set_rx_mode(tp->dev);
8351
8352         /* Initialize receive rules. */
8353         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
8354         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8355         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
8356         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8357
8358         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8359             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8360                 limit = 8;
8361         else
8362                 limit = 16;
8363         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8364                 limit -= 4;
8365         switch (limit) {
8366         case 16:
8367                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
8368         case 15:
8369                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
8370         case 14:
8371                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
8372         case 13:
8373                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
8374         case 12:
8375                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
8376         case 11:
8377                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
8378         case 10:
8379                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
8380         case 9:
8381                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
8382         case 8:
8383                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
8384         case 7:
8385                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
8386         case 6:
8387                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
8388         case 5:
8389                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
8390         case 4:
8391                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
8392         case 3:
8393                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
8394         case 2:
8395         case 1:
8396
8397         default:
8398                 break;
8399         }
8400
8401         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8402                 /* Write our heartbeat update interval to APE. */
8403                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8404                                 APE_HOST_HEARTBEAT_INT_DISABLE);
8405
8406         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8407
8408         return 0;
8409 }
8410
8411 /* Called at device open time to get the chip ready for
8412  * packet processing.  Invoked with tp->lock held.
8413  */
8414 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8415 {
8416         tg3_switch_clocks(tp);
8417
8418         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8419
8420         return tg3_reset_hw(tp, reset_phy);
8421 }
8422
8423 #define TG3_STAT_ADD32(PSTAT, REG) \
8424 do {    u32 __val = tr32(REG); \
8425         (PSTAT)->low += __val; \
8426         if ((PSTAT)->low < __val) \
8427                 (PSTAT)->high += 1; \
8428 } while (0)
8429
8430 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8431 {
8432         struct tg3_hw_stats *sp = tp->hw_stats;
8433
8434         if (!netif_carrier_ok(tp->dev))
8435                 return;
8436
8437         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8438         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8439         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8440         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8441         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8442         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8443         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8444         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8445         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8446         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8447         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8448         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8449         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8450
8451         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8452         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8453         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8454         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8455         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8456         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8457         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8458         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8459         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8460         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8461         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8462         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8463         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8464         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8465
8466         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8467         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8468         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8469 }
8470
8471 static void tg3_timer(unsigned long __opaque)
8472 {
8473         struct tg3 *tp = (struct tg3 *) __opaque;
8474
8475         if (tp->irq_sync)
8476                 goto restart_timer;
8477
8478         spin_lock(&tp->lock);
8479
8480         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8481                 /* All of this garbage is because when using non-tagged
8482                  * IRQ status the mailbox/status_block protocol the chip
8483                  * uses with the cpu is race prone.
8484                  */
8485                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8486                         tw32(GRC_LOCAL_CTRL,
8487                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8488                 } else {
8489                         tw32(HOSTCC_MODE, tp->coalesce_mode |
8490                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8491                 }
8492
8493                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8494                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8495                         spin_unlock(&tp->lock);
8496                         schedule_work(&tp->reset_task);
8497                         return;
8498                 }
8499         }
8500
8501         /* This part only runs once per second. */
8502         if (!--tp->timer_counter) {
8503                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8504                         tg3_periodic_fetch_stats(tp);
8505
8506                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8507                         u32 mac_stat;
8508                         int phy_event;
8509
8510                         mac_stat = tr32(MAC_STATUS);
8511
8512                         phy_event = 0;
8513                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8514                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8515                                         phy_event = 1;
8516                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8517                                 phy_event = 1;
8518
8519                         if (phy_event)
8520                                 tg3_setup_phy(tp, 0);
8521                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8522                         u32 mac_stat = tr32(MAC_STATUS);
8523                         int need_setup = 0;
8524
8525                         if (netif_carrier_ok(tp->dev) &&
8526                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8527                                 need_setup = 1;
8528                         }
8529                         if (! netif_carrier_ok(tp->dev) &&
8530                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
8531                                          MAC_STATUS_SIGNAL_DET))) {
8532                                 need_setup = 1;
8533                         }
8534                         if (need_setup) {
8535                                 if (!tp->serdes_counter) {
8536                                         tw32_f(MAC_MODE,
8537                                              (tp->mac_mode &
8538                                               ~MAC_MODE_PORT_MODE_MASK));
8539                                         udelay(40);
8540                                         tw32_f(MAC_MODE, tp->mac_mode);
8541                                         udelay(40);
8542                                 }
8543                                 tg3_setup_phy(tp, 0);
8544                         }
8545                 } else if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8546                            !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8547                         tg3_serdes_parallel_detect(tp);
8548                 }
8549
8550                 tp->timer_counter = tp->timer_multiplier;
8551         }
8552
8553         /* Heartbeat is only sent once every 2 seconds.
8554          *
8555          * The heartbeat is to tell the ASF firmware that the host
8556          * driver is still alive.  In the event that the OS crashes,
8557          * ASF needs to reset the hardware to free up the FIFO space
8558          * that may be filled with rx packets destined for the host.
8559          * If the FIFO is full, ASF will no longer function properly.
8560          *
8561          * Unintended resets have been reported on real time kernels
8562          * where the timer doesn't run on time.  Netpoll will also have
8563          * same problem.
8564          *
8565          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8566          * to check the ring condition when the heartbeat is expiring
8567          * before doing the reset.  This will prevent most unintended
8568          * resets.
8569          */
8570         if (!--tp->asf_counter) {
8571                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8572                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8573                         tg3_wait_for_event_ack(tp);
8574
8575                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8576                                       FWCMD_NICDRV_ALIVE3);
8577                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8578                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
8579                                       TG3_FW_UPDATE_TIMEOUT_SEC);
8580
8581                         tg3_generate_fw_event(tp);
8582                 }
8583                 tp->asf_counter = tp->asf_multiplier;
8584         }
8585
8586         spin_unlock(&tp->lock);
8587
8588 restart_timer:
8589         tp->timer.expires = jiffies + tp->timer_offset;
8590         add_timer(&tp->timer);
8591 }
8592
8593 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8594 {
8595         irq_handler_t fn;
8596         unsigned long flags;
8597         char *name;
8598         struct tg3_napi *tnapi = &tp->napi[irq_num];
8599
8600         if (tp->irq_cnt == 1)
8601                 name = tp->dev->name;
8602         else {
8603                 name = &tnapi->irq_lbl[0];
8604                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8605                 name[IFNAMSIZ-1] = 0;
8606         }
8607
8608         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8609                 fn = tg3_msi;
8610                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8611                         fn = tg3_msi_1shot;
8612                 flags = IRQF_SAMPLE_RANDOM;
8613         } else {
8614                 fn = tg3_interrupt;
8615                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8616                         fn = tg3_interrupt_tagged;
8617                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8618         }
8619
8620         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8621 }
8622
8623 static int tg3_test_interrupt(struct tg3 *tp)
8624 {
8625         struct tg3_napi *tnapi = &tp->napi[0];
8626         struct net_device *dev = tp->dev;
8627         int err, i, intr_ok = 0;
8628         u32 val;
8629
8630         if (!netif_running(dev))
8631                 return -ENODEV;
8632
8633         tg3_disable_ints(tp);
8634
8635         free_irq(tnapi->irq_vec, tnapi);
8636
8637         /*
8638          * Turn off MSI one shot mode.  Otherwise this test has no
8639          * observable way to know whether the interrupt was delivered.
8640          */
8641         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8642              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8643              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
8644             (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8645                 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8646                 tw32(MSGINT_MODE, val);
8647         }
8648
8649         err = request_irq(tnapi->irq_vec, tg3_test_isr,
8650                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8651         if (err)
8652                 return err;
8653
8654         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8655         tg3_enable_ints(tp);
8656
8657         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8658                tnapi->coal_now);
8659
8660         for (i = 0; i < 5; i++) {
8661                 u32 int_mbox, misc_host_ctrl;
8662
8663                 int_mbox = tr32_mailbox(tnapi->int_mbox);
8664                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8665
8666                 if ((int_mbox != 0) ||
8667                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8668                         intr_ok = 1;
8669                         break;
8670                 }
8671
8672                 msleep(10);
8673         }
8674
8675         tg3_disable_ints(tp);
8676
8677         free_irq(tnapi->irq_vec, tnapi);
8678
8679         err = tg3_request_irq(tp, 0);
8680
8681         if (err)
8682                 return err;
8683
8684         if (intr_ok) {
8685                 /* Reenable MSI one shot mode. */
8686                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8687                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8688                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
8689                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8690                         val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8691                         tw32(MSGINT_MODE, val);
8692                 }
8693                 return 0;
8694         }
8695
8696         return -EIO;
8697 }
8698
8699 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8700  * successfully restored
8701  */
8702 static int tg3_test_msi(struct tg3 *tp)
8703 {
8704         int err;
8705         u16 pci_cmd;
8706
8707         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8708                 return 0;
8709
8710         /* Turn off SERR reporting in case MSI terminates with Master
8711          * Abort.
8712          */
8713         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8714         pci_write_config_word(tp->pdev, PCI_COMMAND,
8715                               pci_cmd & ~PCI_COMMAND_SERR);
8716
8717         err = tg3_test_interrupt(tp);
8718
8719         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8720
8721         if (!err)
8722                 return 0;
8723
8724         /* other failures */
8725         if (err != -EIO)
8726                 return err;
8727
8728         /* MSI test failed, go back to INTx mode */
8729         netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
8730                     "to INTx mode. Please report this failure to the PCI "
8731                     "maintainer and include system chipset information\n");
8732
8733         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8734
8735         pci_disable_msi(tp->pdev);
8736
8737         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8738         tp->napi[0].irq_vec = tp->pdev->irq;
8739
8740         err = tg3_request_irq(tp, 0);
8741         if (err)
8742                 return err;
8743
8744         /* Need to reset the chip because the MSI cycle may have terminated
8745          * with Master Abort.
8746          */
8747         tg3_full_lock(tp, 1);
8748
8749         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8750         err = tg3_init_hw(tp, 1);
8751
8752         tg3_full_unlock(tp);
8753
8754         if (err)
8755                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8756
8757         return err;
8758 }
8759
8760 static int tg3_request_firmware(struct tg3 *tp)
8761 {
8762         const __be32 *fw_data;
8763
8764         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8765                 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
8766                            tp->fw_needed);
8767                 return -ENOENT;
8768         }
8769
8770         fw_data = (void *)tp->fw->data;
8771
8772         /* Firmware blob starts with version numbers, followed by
8773          * start address and _full_ length including BSS sections
8774          * (which must be longer than the actual data, of course
8775          */
8776
8777         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
8778         if (tp->fw_len < (tp->fw->size - 12)) {
8779                 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
8780                            tp->fw_len, tp->fw_needed);
8781                 release_firmware(tp->fw);
8782                 tp->fw = NULL;
8783                 return -EINVAL;
8784         }
8785
8786         /* We no longer need firmware; we have it. */
8787         tp->fw_needed = NULL;
8788         return 0;
8789 }
8790
8791 static bool tg3_enable_msix(struct tg3 *tp)
8792 {
8793         int i, rc, cpus = num_online_cpus();
8794         struct msix_entry msix_ent[tp->irq_max];
8795
8796         if (cpus == 1)
8797                 /* Just fallback to the simpler MSI mode. */
8798                 return false;
8799
8800         /*
8801          * We want as many rx rings enabled as there are cpus.
8802          * The first MSIX vector only deals with link interrupts, etc,
8803          * so we add one to the number of vectors we are requesting.
8804          */
8805         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8806
8807         for (i = 0; i < tp->irq_max; i++) {
8808                 msix_ent[i].entry  = i;
8809                 msix_ent[i].vector = 0;
8810         }
8811
8812         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8813         if (rc < 0) {
8814                 return false;
8815         } else if (rc != 0) {
8816                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8817                         return false;
8818                 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
8819                               tp->irq_cnt, rc);
8820                 tp->irq_cnt = rc;
8821         }
8822
8823         for (i = 0; i < tp->irq_max; i++)
8824                 tp->napi[i].irq_vec = msix_ent[i].vector;
8825
8826         tp->dev->real_num_tx_queues = 1;
8827         if (tp->irq_cnt > 1) {
8828                 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8829
8830                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8831                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
8832                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
8833                         tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8834                 }
8835         }
8836
8837         return true;
8838 }
8839
8840 static void tg3_ints_init(struct tg3 *tp)
8841 {
8842         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8843             !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8844                 /* All MSI supporting chips should support tagged
8845                  * status.  Assert that this is the case.
8846                  */
8847                 netdev_warn(tp->dev,
8848                             "MSI without TAGGED_STATUS? Not using MSI\n");
8849                 goto defcfg;
8850         }
8851
8852         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8853                 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8854         else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8855                  pci_enable_msi(tp->pdev) == 0)
8856                 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8857
8858         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8859                 u32 msi_mode = tr32(MSGINT_MODE);
8860                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8861                         msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8862                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8863         }
8864 defcfg:
8865         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8866                 tp->irq_cnt = 1;
8867                 tp->napi[0].irq_vec = tp->pdev->irq;
8868                 tp->dev->real_num_tx_queues = 1;
8869         }
8870 }
8871
8872 static void tg3_ints_fini(struct tg3 *tp)
8873 {
8874         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8875                 pci_disable_msix(tp->pdev);
8876         else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8877                 pci_disable_msi(tp->pdev);
8878         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8879         tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
8880 }
8881
8882 static int tg3_open(struct net_device *dev)
8883 {
8884         struct tg3 *tp = netdev_priv(dev);
8885         int i, err;
8886
8887         if (tp->fw_needed) {
8888                 err = tg3_request_firmware(tp);
8889                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8890                         if (err)
8891                                 return err;
8892                 } else if (err) {
8893                         netdev_warn(tp->dev, "TSO capability disabled\n");
8894                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8895                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8896                         netdev_notice(tp->dev, "TSO capability restored\n");
8897                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8898                 }
8899         }
8900
8901         netif_carrier_off(tp->dev);
8902
8903         err = tg3_set_power_state(tp, PCI_D0);
8904         if (err)
8905                 return err;
8906
8907         tg3_full_lock(tp, 0);
8908
8909         tg3_disable_ints(tp);
8910         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8911
8912         tg3_full_unlock(tp);
8913
8914         /*
8915          * Setup interrupts first so we know how
8916          * many NAPI resources to allocate
8917          */
8918         tg3_ints_init(tp);
8919
8920         /* The placement of this call is tied
8921          * to the setup and use of Host TX descriptors.
8922          */
8923         err = tg3_alloc_consistent(tp);
8924         if (err)
8925                 goto err_out1;
8926
8927         tg3_napi_enable(tp);
8928
8929         for (i = 0; i < tp->irq_cnt; i++) {
8930                 struct tg3_napi *tnapi = &tp->napi[i];
8931                 err = tg3_request_irq(tp, i);
8932                 if (err) {
8933                         for (i--; i >= 0; i--)
8934                                 free_irq(tnapi->irq_vec, tnapi);
8935                         break;
8936                 }
8937         }
8938
8939         if (err)
8940                 goto err_out2;
8941
8942         tg3_full_lock(tp, 0);
8943
8944         err = tg3_init_hw(tp, 1);
8945         if (err) {
8946                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8947                 tg3_free_rings(tp);
8948         } else {
8949                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8950                         tp->timer_offset = HZ;
8951                 else
8952                         tp->timer_offset = HZ / 10;
8953
8954                 BUG_ON(tp->timer_offset > HZ);
8955                 tp->timer_counter = tp->timer_multiplier =
8956                         (HZ / tp->timer_offset);
8957                 tp->asf_counter = tp->asf_multiplier =
8958                         ((HZ / tp->timer_offset) * 2);
8959
8960                 init_timer(&tp->timer);
8961                 tp->timer.expires = jiffies + tp->timer_offset;
8962                 tp->timer.data = (unsigned long) tp;
8963                 tp->timer.function = tg3_timer;
8964         }
8965
8966         tg3_full_unlock(tp);
8967
8968         if (err)
8969                 goto err_out3;
8970
8971         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8972                 err = tg3_test_msi(tp);
8973
8974                 if (err) {
8975                         tg3_full_lock(tp, 0);
8976                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8977                         tg3_free_rings(tp);
8978                         tg3_full_unlock(tp);
8979
8980                         goto err_out2;
8981                 }
8982
8983                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8984                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719 &&
8985                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 &&
8986                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8987                     (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8988                         u32 val = tr32(PCIE_TRANSACTION_CFG);
8989
8990                         tw32(PCIE_TRANSACTION_CFG,
8991                              val | PCIE_TRANS_CFG_1SHOT_MSI);
8992                 }
8993         }
8994
8995         tg3_phy_start(tp);
8996
8997         tg3_full_lock(tp, 0);
8998
8999         add_timer(&tp->timer);
9000         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9001         tg3_enable_ints(tp);
9002
9003         tg3_full_unlock(tp);
9004
9005         netif_tx_start_all_queues(dev);
9006
9007         return 0;
9008
9009 err_out3:
9010         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9011                 struct tg3_napi *tnapi = &tp->napi[i];
9012                 free_irq(tnapi->irq_vec, tnapi);
9013         }
9014
9015 err_out2:
9016         tg3_napi_disable(tp);
9017         tg3_free_consistent(tp);
9018
9019 err_out1:
9020         tg3_ints_fini(tp);
9021         return err;
9022 }
9023
9024 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
9025                                                  struct rtnl_link_stats64 *);
9026 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9027
9028 static int tg3_close(struct net_device *dev)
9029 {
9030         int i;
9031         struct tg3 *tp = netdev_priv(dev);
9032
9033         tg3_napi_disable(tp);
9034         cancel_work_sync(&tp->reset_task);
9035
9036         netif_tx_stop_all_queues(dev);
9037
9038         del_timer_sync(&tp->timer);
9039
9040         tg3_phy_stop(tp);
9041
9042         tg3_full_lock(tp, 1);
9043
9044         tg3_disable_ints(tp);
9045
9046         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9047         tg3_free_rings(tp);
9048         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9049
9050         tg3_full_unlock(tp);
9051
9052         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9053                 struct tg3_napi *tnapi = &tp->napi[i];
9054                 free_irq(tnapi->irq_vec, tnapi);
9055         }
9056
9057         tg3_ints_fini(tp);
9058
9059         tg3_get_stats64(tp->dev, &tp->net_stats_prev);
9060
9061         memcpy(&tp->estats_prev, tg3_get_estats(tp),
9062                sizeof(tp->estats_prev));
9063
9064         tg3_free_consistent(tp);
9065
9066         tg3_set_power_state(tp, PCI_D3hot);
9067
9068         netif_carrier_off(tp->dev);
9069
9070         return 0;
9071 }
9072
9073 static inline u64 get_stat64(tg3_stat64_t *val)
9074 {
9075        return ((u64)val->high << 32) | ((u64)val->low);
9076 }
9077
9078 static u64 calc_crc_errors(struct tg3 *tp)
9079 {
9080         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9081
9082         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9083             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9084              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9085                 u32 val;
9086
9087                 spin_lock_bh(&tp->lock);
9088                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9089                         tg3_writephy(tp, MII_TG3_TEST1,
9090                                      val | MII_TG3_TEST1_CRC_EN);
9091                         tg3_readphy(tp, 0x14, &val);
9092                 } else
9093                         val = 0;
9094                 spin_unlock_bh(&tp->lock);
9095
9096                 tp->phy_crc_errors += val;
9097
9098                 return tp->phy_crc_errors;
9099         }
9100
9101         return get_stat64(&hw_stats->rx_fcs_errors);
9102 }
9103
9104 #define ESTAT_ADD(member) \
9105         estats->member =        old_estats->member + \
9106                                 get_stat64(&hw_stats->member)
9107
9108 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9109 {
9110         struct tg3_ethtool_stats *estats = &tp->estats;
9111         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9112         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9113
9114         if (!hw_stats)
9115                 return old_estats;
9116
9117         ESTAT_ADD(rx_octets);
9118         ESTAT_ADD(rx_fragments);
9119         ESTAT_ADD(rx_ucast_packets);
9120         ESTAT_ADD(rx_mcast_packets);
9121         ESTAT_ADD(rx_bcast_packets);
9122         ESTAT_ADD(rx_fcs_errors);
9123         ESTAT_ADD(rx_align_errors);
9124         ESTAT_ADD(rx_xon_pause_rcvd);
9125         ESTAT_ADD(rx_xoff_pause_rcvd);
9126         ESTAT_ADD(rx_mac_ctrl_rcvd);
9127         ESTAT_ADD(rx_xoff_entered);
9128         ESTAT_ADD(rx_frame_too_long_errors);
9129         ESTAT_ADD(rx_jabbers);
9130         ESTAT_ADD(rx_undersize_packets);
9131         ESTAT_ADD(rx_in_length_errors);
9132         ESTAT_ADD(rx_out_length_errors);
9133         ESTAT_ADD(rx_64_or_less_octet_packets);
9134         ESTAT_ADD(rx_65_to_127_octet_packets);
9135         ESTAT_ADD(rx_128_to_255_octet_packets);
9136         ESTAT_ADD(rx_256_to_511_octet_packets);
9137         ESTAT_ADD(rx_512_to_1023_octet_packets);
9138         ESTAT_ADD(rx_1024_to_1522_octet_packets);
9139         ESTAT_ADD(rx_1523_to_2047_octet_packets);
9140         ESTAT_ADD(rx_2048_to_4095_octet_packets);
9141         ESTAT_ADD(rx_4096_to_8191_octet_packets);
9142         ESTAT_ADD(rx_8192_to_9022_octet_packets);
9143
9144         ESTAT_ADD(tx_octets);
9145         ESTAT_ADD(tx_collisions);
9146         ESTAT_ADD(tx_xon_sent);
9147         ESTAT_ADD(tx_xoff_sent);
9148         ESTAT_ADD(tx_flow_control);
9149         ESTAT_ADD(tx_mac_errors);
9150         ESTAT_ADD(tx_single_collisions);
9151         ESTAT_ADD(tx_mult_collisions);
9152         ESTAT_ADD(tx_deferred);
9153         ESTAT_ADD(tx_excessive_collisions);
9154         ESTAT_ADD(tx_late_collisions);
9155         ESTAT_ADD(tx_collide_2times);
9156         ESTAT_ADD(tx_collide_3times);
9157         ESTAT_ADD(tx_collide_4times);
9158         ESTAT_ADD(tx_collide_5times);
9159         ESTAT_ADD(tx_collide_6times);
9160         ESTAT_ADD(tx_collide_7times);
9161         ESTAT_ADD(tx_collide_8times);
9162         ESTAT_ADD(tx_collide_9times);
9163         ESTAT_ADD(tx_collide_10times);
9164         ESTAT_ADD(tx_collide_11times);
9165         ESTAT_ADD(tx_collide_12times);
9166         ESTAT_ADD(tx_collide_13times);
9167         ESTAT_ADD(tx_collide_14times);
9168         ESTAT_ADD(tx_collide_15times);
9169         ESTAT_ADD(tx_ucast_packets);
9170         ESTAT_ADD(tx_mcast_packets);
9171         ESTAT_ADD(tx_bcast_packets);
9172         ESTAT_ADD(tx_carrier_sense_errors);
9173         ESTAT_ADD(tx_discards);
9174         ESTAT_ADD(tx_errors);
9175
9176         ESTAT_ADD(dma_writeq_full);
9177         ESTAT_ADD(dma_write_prioq_full);
9178         ESTAT_ADD(rxbds_empty);
9179         ESTAT_ADD(rx_discards);
9180         ESTAT_ADD(rx_errors);
9181         ESTAT_ADD(rx_threshold_hit);
9182
9183         ESTAT_ADD(dma_readq_full);
9184         ESTAT_ADD(dma_read_prioq_full);
9185         ESTAT_ADD(tx_comp_queue_full);
9186
9187         ESTAT_ADD(ring_set_send_prod_index);
9188         ESTAT_ADD(ring_status_update);
9189         ESTAT_ADD(nic_irqs);
9190         ESTAT_ADD(nic_avoided_irqs);
9191         ESTAT_ADD(nic_tx_threshold_hit);
9192
9193         return estats;
9194 }
9195
9196 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
9197                                                  struct rtnl_link_stats64 *stats)
9198 {
9199         struct tg3 *tp = netdev_priv(dev);
9200         struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
9201         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9202
9203         if (!hw_stats)
9204                 return old_stats;
9205
9206         stats->rx_packets = old_stats->rx_packets +
9207                 get_stat64(&hw_stats->rx_ucast_packets) +
9208                 get_stat64(&hw_stats->rx_mcast_packets) +
9209                 get_stat64(&hw_stats->rx_bcast_packets);
9210
9211         stats->tx_packets = old_stats->tx_packets +
9212                 get_stat64(&hw_stats->tx_ucast_packets) +
9213                 get_stat64(&hw_stats->tx_mcast_packets) +
9214                 get_stat64(&hw_stats->tx_bcast_packets);
9215
9216         stats->rx_bytes = old_stats->rx_bytes +
9217                 get_stat64(&hw_stats->rx_octets);
9218         stats->tx_bytes = old_stats->tx_bytes +
9219                 get_stat64(&hw_stats->tx_octets);
9220
9221         stats->rx_errors = old_stats->rx_errors +
9222                 get_stat64(&hw_stats->rx_errors);
9223         stats->tx_errors = old_stats->tx_errors +
9224                 get_stat64(&hw_stats->tx_errors) +
9225                 get_stat64(&hw_stats->tx_mac_errors) +
9226                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9227                 get_stat64(&hw_stats->tx_discards);
9228
9229         stats->multicast = old_stats->multicast +
9230                 get_stat64(&hw_stats->rx_mcast_packets);
9231         stats->collisions = old_stats->collisions +
9232                 get_stat64(&hw_stats->tx_collisions);
9233
9234         stats->rx_length_errors = old_stats->rx_length_errors +
9235                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9236                 get_stat64(&hw_stats->rx_undersize_packets);
9237
9238         stats->rx_over_errors = old_stats->rx_over_errors +
9239                 get_stat64(&hw_stats->rxbds_empty);
9240         stats->rx_frame_errors = old_stats->rx_frame_errors +
9241                 get_stat64(&hw_stats->rx_align_errors);
9242         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9243                 get_stat64(&hw_stats->tx_discards);
9244         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9245                 get_stat64(&hw_stats->tx_carrier_sense_errors);
9246
9247         stats->rx_crc_errors = old_stats->rx_crc_errors +
9248                 calc_crc_errors(tp);
9249
9250         stats->rx_missed_errors = old_stats->rx_missed_errors +
9251                 get_stat64(&hw_stats->rx_discards);
9252
9253         return stats;
9254 }
9255
9256 static inline u32 calc_crc(unsigned char *buf, int len)
9257 {
9258         u32 reg;
9259         u32 tmp;
9260         int j, k;
9261
9262         reg = 0xffffffff;
9263
9264         for (j = 0; j < len; j++) {
9265                 reg ^= buf[j];
9266
9267                 for (k = 0; k < 8; k++) {
9268                         tmp = reg & 0x01;
9269
9270                         reg >>= 1;
9271
9272                         if (tmp)
9273                                 reg ^= 0xedb88320;
9274                 }
9275         }
9276
9277         return ~reg;
9278 }
9279
9280 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9281 {
9282         /* accept or reject all multicast frames */
9283         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9284         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9285         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9286         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9287 }
9288
9289 static void __tg3_set_rx_mode(struct net_device *dev)
9290 {
9291         struct tg3 *tp = netdev_priv(dev);
9292         u32 rx_mode;
9293
9294         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9295                                   RX_MODE_KEEP_VLAN_TAG);
9296
9297         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9298          * flag clear.
9299          */
9300 #if TG3_VLAN_TAG_USED
9301         if (!tp->vlgrp &&
9302             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9303                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9304 #else
9305         /* By definition, VLAN is disabled always in this
9306          * case.
9307          */
9308         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9309                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9310 #endif
9311
9312         if (dev->flags & IFF_PROMISC) {
9313                 /* Promiscuous mode. */
9314                 rx_mode |= RX_MODE_PROMISC;
9315         } else if (dev->flags & IFF_ALLMULTI) {
9316                 /* Accept all multicast. */
9317                 tg3_set_multi(tp, 1);
9318         } else if (netdev_mc_empty(dev)) {
9319                 /* Reject all multicast. */
9320                 tg3_set_multi(tp, 0);
9321         } else {
9322                 /* Accept one or more multicast(s). */
9323                 struct netdev_hw_addr *ha;
9324                 u32 mc_filter[4] = { 0, };
9325                 u32 regidx;
9326                 u32 bit;
9327                 u32 crc;
9328
9329                 netdev_for_each_mc_addr(ha, dev) {
9330                         crc = calc_crc(ha->addr, ETH_ALEN);
9331                         bit = ~crc & 0x7f;
9332                         regidx = (bit & 0x60) >> 5;
9333                         bit &= 0x1f;
9334                         mc_filter[regidx] |= (1 << bit);
9335                 }
9336
9337                 tw32(MAC_HASH_REG_0, mc_filter[0]);
9338                 tw32(MAC_HASH_REG_1, mc_filter[1]);
9339                 tw32(MAC_HASH_REG_2, mc_filter[2]);
9340                 tw32(MAC_HASH_REG_3, mc_filter[3]);
9341         }
9342
9343         if (rx_mode != tp->rx_mode) {
9344                 tp->rx_mode = rx_mode;
9345                 tw32_f(MAC_RX_MODE, rx_mode);
9346                 udelay(10);
9347         }
9348 }
9349
9350 static void tg3_set_rx_mode(struct net_device *dev)
9351 {
9352         struct tg3 *tp = netdev_priv(dev);
9353
9354         if (!netif_running(dev))
9355                 return;
9356
9357         tg3_full_lock(tp, 0);
9358         __tg3_set_rx_mode(dev);
9359         tg3_full_unlock(tp);
9360 }
9361
9362 #define TG3_REGDUMP_LEN         (32 * 1024)
9363
9364 static int tg3_get_regs_len(struct net_device *dev)
9365 {
9366         return TG3_REGDUMP_LEN;
9367 }
9368
9369 static void tg3_get_regs(struct net_device *dev,
9370                 struct ethtool_regs *regs, void *_p)
9371 {
9372         u32 *p = _p;
9373         struct tg3 *tp = netdev_priv(dev);
9374         u8 *orig_p = _p;
9375         int i;
9376
9377         regs->version = 0;
9378
9379         memset(p, 0, TG3_REGDUMP_LEN);
9380
9381         if (tp->link_config.phy_is_low_power)
9382                 return;
9383
9384         tg3_full_lock(tp, 0);
9385
9386 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
9387 #define GET_REG32_LOOP(base,len)                \
9388 do {    p = (u32 *)(orig_p + (base));           \
9389         for (i = 0; i < len; i += 4)            \
9390                 __GET_REG32((base) + i);        \
9391 } while (0)
9392 #define GET_REG32_1(reg)                        \
9393 do {    p = (u32 *)(orig_p + (reg));            \
9394         __GET_REG32((reg));                     \
9395 } while (0)
9396
9397         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9398         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9399         GET_REG32_LOOP(MAC_MODE, 0x4f0);
9400         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9401         GET_REG32_1(SNDDATAC_MODE);
9402         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9403         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9404         GET_REG32_1(SNDBDC_MODE);
9405         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9406         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9407         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9408         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9409         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9410         GET_REG32_1(RCVDCC_MODE);
9411         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9412         GET_REG32_LOOP(RCVCC_MODE, 0x14);
9413         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9414         GET_REG32_1(MBFREE_MODE);
9415         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9416         GET_REG32_LOOP(MEMARB_MODE, 0x10);
9417         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9418         GET_REG32_LOOP(RDMAC_MODE, 0x08);
9419         GET_REG32_LOOP(WDMAC_MODE, 0x08);
9420         GET_REG32_1(RX_CPU_MODE);
9421         GET_REG32_1(RX_CPU_STATE);
9422         GET_REG32_1(RX_CPU_PGMCTR);
9423         GET_REG32_1(RX_CPU_HWBKPT);
9424         GET_REG32_1(TX_CPU_MODE);
9425         GET_REG32_1(TX_CPU_STATE);
9426         GET_REG32_1(TX_CPU_PGMCTR);
9427         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9428         GET_REG32_LOOP(FTQ_RESET, 0x120);
9429         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9430         GET_REG32_1(DMAC_MODE);
9431         GET_REG32_LOOP(GRC_MODE, 0x4c);
9432         if (tp->tg3_flags & TG3_FLAG_NVRAM)
9433                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9434
9435 #undef __GET_REG32
9436 #undef GET_REG32_LOOP
9437 #undef GET_REG32_1
9438
9439         tg3_full_unlock(tp);
9440 }
9441
9442 static int tg3_get_eeprom_len(struct net_device *dev)
9443 {
9444         struct tg3 *tp = netdev_priv(dev);
9445
9446         return tp->nvram_size;
9447 }
9448
9449 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9450 {
9451         struct tg3 *tp = netdev_priv(dev);
9452         int ret;
9453         u8  *pd;
9454         u32 i, offset, len, b_offset, b_count;
9455         __be32 val;
9456
9457         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9458                 return -EINVAL;
9459
9460         if (tp->link_config.phy_is_low_power)
9461                 return -EAGAIN;
9462
9463         offset = eeprom->offset;
9464         len = eeprom->len;
9465         eeprom->len = 0;
9466
9467         eeprom->magic = TG3_EEPROM_MAGIC;
9468
9469         if (offset & 3) {
9470                 /* adjustments to start on required 4 byte boundary */
9471                 b_offset = offset & 3;
9472                 b_count = 4 - b_offset;
9473                 if (b_count > len) {
9474                         /* i.e. offset=1 len=2 */
9475                         b_count = len;
9476                 }
9477                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9478                 if (ret)
9479                         return ret;
9480                 memcpy(data, ((char*)&val) + b_offset, b_count);
9481                 len -= b_count;
9482                 offset += b_count;
9483                 eeprom->len += b_count;
9484         }
9485
9486         /* read bytes upto the last 4 byte boundary */
9487         pd = &data[eeprom->len];
9488         for (i = 0; i < (len - (len & 3)); i += 4) {
9489                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9490                 if (ret) {
9491                         eeprom->len += i;
9492                         return ret;
9493                 }
9494                 memcpy(pd + i, &val, 4);
9495         }
9496         eeprom->len += i;
9497
9498         if (len & 3) {
9499                 /* read last bytes not ending on 4 byte boundary */
9500                 pd = &data[eeprom->len];
9501                 b_count = len & 3;
9502                 b_offset = offset + len - b_count;
9503                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9504                 if (ret)
9505                         return ret;
9506                 memcpy(pd, &val, b_count);
9507                 eeprom->len += b_count;
9508         }
9509         return 0;
9510 }
9511
9512 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9513
9514 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9515 {
9516         struct tg3 *tp = netdev_priv(dev);
9517         int ret;
9518         u32 offset, len, b_offset, odd_len;
9519         u8 *buf;
9520         __be32 start, end;
9521
9522         if (tp->link_config.phy_is_low_power)
9523                 return -EAGAIN;
9524
9525         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9526             eeprom->magic != TG3_EEPROM_MAGIC)
9527                 return -EINVAL;
9528
9529         offset = eeprom->offset;
9530         len = eeprom->len;
9531
9532         if ((b_offset = (offset & 3))) {
9533                 /* adjustments to start on required 4 byte boundary */
9534                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9535                 if (ret)
9536                         return ret;
9537                 len += b_offset;
9538                 offset &= ~3;
9539                 if (len < 4)
9540                         len = 4;
9541         }
9542
9543         odd_len = 0;
9544         if (len & 3) {
9545                 /* adjustments to end on required 4 byte boundary */
9546                 odd_len = 1;
9547                 len = (len + 3) & ~3;
9548                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9549                 if (ret)
9550                         return ret;
9551         }
9552
9553         buf = data;
9554         if (b_offset || odd_len) {
9555                 buf = kmalloc(len, GFP_KERNEL);
9556                 if (!buf)
9557                         return -ENOMEM;
9558                 if (b_offset)
9559                         memcpy(buf, &start, 4);
9560                 if (odd_len)
9561                         memcpy(buf+len-4, &end, 4);
9562                 memcpy(buf + b_offset, data, eeprom->len);
9563         }
9564
9565         ret = tg3_nvram_write_block(tp, offset, len, buf);
9566
9567         if (buf != data)
9568                 kfree(buf);
9569
9570         return ret;
9571 }
9572
9573 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9574 {
9575         struct tg3 *tp = netdev_priv(dev);
9576
9577         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9578                 struct phy_device *phydev;
9579                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9580                         return -EAGAIN;
9581                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9582                 return phy_ethtool_gset(phydev, cmd);
9583         }
9584
9585         cmd->supported = (SUPPORTED_Autoneg);
9586
9587         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9588                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9589                                    SUPPORTED_1000baseT_Full);
9590
9591         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
9592                 cmd->supported |= (SUPPORTED_100baseT_Half |
9593                                   SUPPORTED_100baseT_Full |
9594                                   SUPPORTED_10baseT_Half |
9595                                   SUPPORTED_10baseT_Full |
9596                                   SUPPORTED_TP);
9597                 cmd->port = PORT_TP;
9598         } else {
9599                 cmd->supported |= SUPPORTED_FIBRE;
9600                 cmd->port = PORT_FIBRE;
9601         }
9602
9603         cmd->advertising = tp->link_config.advertising;
9604         if (netif_running(dev)) {
9605                 cmd->speed = tp->link_config.active_speed;
9606                 cmd->duplex = tp->link_config.active_duplex;
9607         }
9608         cmd->phy_address = tp->phy_addr;
9609         cmd->transceiver = XCVR_INTERNAL;
9610         cmd->autoneg = tp->link_config.autoneg;
9611         cmd->maxtxpkt = 0;
9612         cmd->maxrxpkt = 0;
9613         return 0;
9614 }
9615
9616 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9617 {
9618         struct tg3 *tp = netdev_priv(dev);
9619
9620         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9621                 struct phy_device *phydev;
9622                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9623                         return -EAGAIN;
9624                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9625                 return phy_ethtool_sset(phydev, cmd);
9626         }
9627
9628         if (cmd->autoneg != AUTONEG_ENABLE &&
9629             cmd->autoneg != AUTONEG_DISABLE)
9630                 return -EINVAL;
9631
9632         if (cmd->autoneg == AUTONEG_DISABLE &&
9633             cmd->duplex != DUPLEX_FULL &&
9634             cmd->duplex != DUPLEX_HALF)
9635                 return -EINVAL;
9636
9637         if (cmd->autoneg == AUTONEG_ENABLE) {
9638                 u32 mask = ADVERTISED_Autoneg |
9639                            ADVERTISED_Pause |
9640                            ADVERTISED_Asym_Pause;
9641
9642                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9643                         mask |= ADVERTISED_1000baseT_Half |
9644                                 ADVERTISED_1000baseT_Full;
9645
9646                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9647                         mask |= ADVERTISED_100baseT_Half |
9648                                 ADVERTISED_100baseT_Full |
9649                                 ADVERTISED_10baseT_Half |
9650                                 ADVERTISED_10baseT_Full |
9651                                 ADVERTISED_TP;
9652                 else
9653                         mask |= ADVERTISED_FIBRE;
9654
9655                 if (cmd->advertising & ~mask)
9656                         return -EINVAL;
9657
9658                 mask &= (ADVERTISED_1000baseT_Half |
9659                          ADVERTISED_1000baseT_Full |
9660                          ADVERTISED_100baseT_Half |
9661                          ADVERTISED_100baseT_Full |
9662                          ADVERTISED_10baseT_Half |
9663                          ADVERTISED_10baseT_Full);
9664
9665                 cmd->advertising &= mask;
9666         } else {
9667                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9668                         if (cmd->speed != SPEED_1000)
9669                                 return -EINVAL;
9670
9671                         if (cmd->duplex != DUPLEX_FULL)
9672                                 return -EINVAL;
9673                 } else {
9674                         if (cmd->speed != SPEED_100 &&
9675                             cmd->speed != SPEED_10)
9676                                 return -EINVAL;
9677                 }
9678         }
9679
9680         tg3_full_lock(tp, 0);
9681
9682         tp->link_config.autoneg = cmd->autoneg;
9683         if (cmd->autoneg == AUTONEG_ENABLE) {
9684                 tp->link_config.advertising = (cmd->advertising |
9685                                               ADVERTISED_Autoneg);
9686                 tp->link_config.speed = SPEED_INVALID;
9687                 tp->link_config.duplex = DUPLEX_INVALID;
9688         } else {
9689                 tp->link_config.advertising = 0;
9690                 tp->link_config.speed = cmd->speed;
9691                 tp->link_config.duplex = cmd->duplex;
9692         }
9693
9694         tp->link_config.orig_speed = tp->link_config.speed;
9695         tp->link_config.orig_duplex = tp->link_config.duplex;
9696         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9697
9698         if (netif_running(dev))
9699                 tg3_setup_phy(tp, 1);
9700
9701         tg3_full_unlock(tp);
9702
9703         return 0;
9704 }
9705
9706 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9707 {
9708         struct tg3 *tp = netdev_priv(dev);
9709
9710         strcpy(info->driver, DRV_MODULE_NAME);
9711         strcpy(info->version, DRV_MODULE_VERSION);
9712         strcpy(info->fw_version, tp->fw_ver);
9713         strcpy(info->bus_info, pci_name(tp->pdev));
9714 }
9715
9716 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9717 {
9718         struct tg3 *tp = netdev_priv(dev);
9719
9720         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9721             device_can_wakeup(&tp->pdev->dev))
9722                 wol->supported = WAKE_MAGIC;
9723         else
9724                 wol->supported = 0;
9725         wol->wolopts = 0;
9726         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9727             device_can_wakeup(&tp->pdev->dev))
9728                 wol->wolopts = WAKE_MAGIC;
9729         memset(&wol->sopass, 0, sizeof(wol->sopass));
9730 }
9731
9732 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9733 {
9734         struct tg3 *tp = netdev_priv(dev);
9735         struct device *dp = &tp->pdev->dev;
9736
9737         if (wol->wolopts & ~WAKE_MAGIC)
9738                 return -EINVAL;
9739         if ((wol->wolopts & WAKE_MAGIC) &&
9740             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9741                 return -EINVAL;
9742
9743         spin_lock_bh(&tp->lock);
9744         if (wol->wolopts & WAKE_MAGIC) {
9745                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9746                 device_set_wakeup_enable(dp, true);
9747         } else {
9748                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9749                 device_set_wakeup_enable(dp, false);
9750         }
9751         spin_unlock_bh(&tp->lock);
9752
9753         return 0;
9754 }
9755
9756 static u32 tg3_get_msglevel(struct net_device *dev)
9757 {
9758         struct tg3 *tp = netdev_priv(dev);
9759         return tp->msg_enable;
9760 }
9761
9762 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9763 {
9764         struct tg3 *tp = netdev_priv(dev);
9765         tp->msg_enable = value;
9766 }
9767
9768 static int tg3_set_tso(struct net_device *dev, u32 value)
9769 {
9770         struct tg3 *tp = netdev_priv(dev);
9771
9772         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9773                 if (value)
9774                         return -EINVAL;
9775                 return 0;
9776         }
9777         if ((dev->features & NETIF_F_IPV6_CSUM) &&
9778             ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9779              (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9780                 if (value) {
9781                         dev->features |= NETIF_F_TSO6;
9782                         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9783                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9784                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9785                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9786                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9787                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9788                                 dev->features |= NETIF_F_TSO_ECN;
9789                 } else
9790                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9791         }
9792         return ethtool_op_set_tso(dev, value);
9793 }
9794
9795 static int tg3_nway_reset(struct net_device *dev)
9796 {
9797         struct tg3 *tp = netdev_priv(dev);
9798         int r;
9799
9800         if (!netif_running(dev))
9801                 return -EAGAIN;
9802
9803         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9804                 return -EINVAL;
9805
9806         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9807                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9808                         return -EAGAIN;
9809                 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9810         } else {
9811                 u32 bmcr;
9812
9813                 spin_lock_bh(&tp->lock);
9814                 r = -EINVAL;
9815                 tg3_readphy(tp, MII_BMCR, &bmcr);
9816                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9817                     ((bmcr & BMCR_ANENABLE) ||
9818                      (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9819                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9820                                                    BMCR_ANENABLE);
9821                         r = 0;
9822                 }
9823                 spin_unlock_bh(&tp->lock);
9824         }
9825
9826         return r;
9827 }
9828
9829 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9830 {
9831         struct tg3 *tp = netdev_priv(dev);
9832
9833         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9834         ering->rx_mini_max_pending = 0;
9835         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9836                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9837         else
9838                 ering->rx_jumbo_max_pending = 0;
9839
9840         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9841
9842         ering->rx_pending = tp->rx_pending;
9843         ering->rx_mini_pending = 0;
9844         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9845                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9846         else
9847                 ering->rx_jumbo_pending = 0;
9848
9849         ering->tx_pending = tp->napi[0].tx_pending;
9850 }
9851
9852 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9853 {
9854         struct tg3 *tp = netdev_priv(dev);
9855         int i, irq_sync = 0, err = 0;
9856
9857         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9858             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9859             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9860             (ering->tx_pending <= MAX_SKB_FRAGS) ||
9861             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9862              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9863                 return -EINVAL;
9864
9865         if (netif_running(dev)) {
9866                 tg3_phy_stop(tp);
9867                 tg3_netif_stop(tp);
9868                 irq_sync = 1;
9869         }
9870
9871         tg3_full_lock(tp, irq_sync);
9872
9873         tp->rx_pending = ering->rx_pending;
9874
9875         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9876             tp->rx_pending > 63)
9877                 tp->rx_pending = 63;
9878         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9879
9880         for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9881                 tp->napi[i].tx_pending = ering->tx_pending;
9882
9883         if (netif_running(dev)) {
9884                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9885                 err = tg3_restart_hw(tp, 1);
9886                 if (!err)
9887                         tg3_netif_start(tp);
9888         }
9889
9890         tg3_full_unlock(tp);
9891
9892         if (irq_sync && !err)
9893                 tg3_phy_start(tp);
9894
9895         return err;
9896 }
9897
9898 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9899 {
9900         struct tg3 *tp = netdev_priv(dev);
9901
9902         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9903
9904         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9905                 epause->rx_pause = 1;
9906         else
9907                 epause->rx_pause = 0;
9908
9909         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9910                 epause->tx_pause = 1;
9911         else
9912                 epause->tx_pause = 0;
9913 }
9914
9915 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9916 {
9917         struct tg3 *tp = netdev_priv(dev);
9918         int err = 0;
9919
9920         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9921                 u32 newadv;
9922                 struct phy_device *phydev;
9923
9924                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9925
9926                 if (!(phydev->supported & SUPPORTED_Pause) ||
9927                     (!(phydev->supported & SUPPORTED_Asym_Pause) &&
9928                      ((epause->rx_pause && !epause->tx_pause) ||
9929                       (!epause->rx_pause && epause->tx_pause))))
9930                         return -EINVAL;
9931
9932                 tp->link_config.flowctrl = 0;
9933                 if (epause->rx_pause) {
9934                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
9935
9936                         if (epause->tx_pause) {
9937                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9938                                 newadv = ADVERTISED_Pause;
9939                         } else
9940                                 newadv = ADVERTISED_Pause |
9941                                          ADVERTISED_Asym_Pause;
9942                 } else if (epause->tx_pause) {
9943                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
9944                         newadv = ADVERTISED_Asym_Pause;
9945                 } else
9946                         newadv = 0;
9947
9948                 if (epause->autoneg)
9949                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9950                 else
9951                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9952
9953                 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9954                         u32 oldadv = phydev->advertising &
9955                                      (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
9956                         if (oldadv != newadv) {
9957                                 phydev->advertising &=
9958                                         ~(ADVERTISED_Pause |
9959                                           ADVERTISED_Asym_Pause);
9960                                 phydev->advertising |= newadv;
9961                                 if (phydev->autoneg) {
9962                                         /*
9963                                          * Always renegotiate the link to
9964                                          * inform our link partner of our
9965                                          * flow control settings, even if the
9966                                          * flow control is forced.  Let
9967                                          * tg3_adjust_link() do the final
9968                                          * flow control setup.
9969                                          */
9970                                         return phy_start_aneg(phydev);
9971                                 }
9972                         }
9973
9974                         if (!epause->autoneg)
9975                                 tg3_setup_flow_control(tp, 0, 0);
9976                 } else {
9977                         tp->link_config.orig_advertising &=
9978                                         ~(ADVERTISED_Pause |
9979                                           ADVERTISED_Asym_Pause);
9980                         tp->link_config.orig_advertising |= newadv;
9981                 }
9982         } else {
9983                 int irq_sync = 0;
9984
9985                 if (netif_running(dev)) {
9986                         tg3_netif_stop(tp);
9987                         irq_sync = 1;
9988                 }
9989
9990                 tg3_full_lock(tp, irq_sync);
9991
9992                 if (epause->autoneg)
9993                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9994                 else
9995                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9996                 if (epause->rx_pause)
9997                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
9998                 else
9999                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10000                 if (epause->tx_pause)
10001                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
10002                 else
10003                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10004
10005                 if (netif_running(dev)) {
10006                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10007                         err = tg3_restart_hw(tp, 1);
10008                         if (!err)
10009                                 tg3_netif_start(tp);
10010                 }
10011
10012                 tg3_full_unlock(tp);
10013         }
10014
10015         return err;
10016 }
10017
10018 static u32 tg3_get_rx_csum(struct net_device *dev)
10019 {
10020         struct tg3 *tp = netdev_priv(dev);
10021         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10022 }
10023
10024 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10025 {
10026         struct tg3 *tp = netdev_priv(dev);
10027
10028         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10029                 if (data != 0)
10030                         return -EINVAL;
10031                 return 0;
10032         }
10033
10034         spin_lock_bh(&tp->lock);
10035         if (data)
10036                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10037         else
10038                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10039         spin_unlock_bh(&tp->lock);
10040
10041         return 0;
10042 }
10043
10044 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10045 {
10046         struct tg3 *tp = netdev_priv(dev);
10047
10048         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10049                 if (data != 0)
10050                         return -EINVAL;
10051                 return 0;
10052         }
10053
10054         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10055                 ethtool_op_set_tx_ipv6_csum(dev, data);
10056         else
10057                 ethtool_op_set_tx_csum(dev, data);
10058
10059         return 0;
10060 }
10061
10062 static int tg3_get_sset_count(struct net_device *dev, int sset)
10063 {
10064         switch (sset) {
10065         case ETH_SS_TEST:
10066                 return TG3_NUM_TEST;
10067         case ETH_SS_STATS:
10068                 return TG3_NUM_STATS;
10069         default:
10070                 return -EOPNOTSUPP;
10071         }
10072 }
10073
10074 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
10075 {
10076         switch (stringset) {
10077         case ETH_SS_STATS:
10078                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10079                 break;
10080         case ETH_SS_TEST:
10081                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10082                 break;
10083         default:
10084                 WARN_ON(1);     /* we need a WARN() */
10085                 break;
10086         }
10087 }
10088
10089 static int tg3_phys_id(struct net_device *dev, u32 data)
10090 {
10091         struct tg3 *tp = netdev_priv(dev);
10092         int i;
10093
10094         if (!netif_running(tp->dev))
10095                 return -EAGAIN;
10096
10097         if (data == 0)
10098                 data = UINT_MAX / 2;
10099
10100         for (i = 0; i < (data * 2); i++) {
10101                 if ((i % 2) == 0)
10102                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10103                                            LED_CTRL_1000MBPS_ON |
10104                                            LED_CTRL_100MBPS_ON |
10105                                            LED_CTRL_10MBPS_ON |
10106                                            LED_CTRL_TRAFFIC_OVERRIDE |
10107                                            LED_CTRL_TRAFFIC_BLINK |
10108                                            LED_CTRL_TRAFFIC_LED);
10109
10110                 else
10111                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10112                                            LED_CTRL_TRAFFIC_OVERRIDE);
10113
10114                 if (msleep_interruptible(500))
10115                         break;
10116         }
10117         tw32(MAC_LED_CTRL, tp->led_ctrl);
10118         return 0;
10119 }
10120
10121 static void tg3_get_ethtool_stats(struct net_device *dev,
10122                                    struct ethtool_stats *estats, u64 *tmp_stats)
10123 {
10124         struct tg3 *tp = netdev_priv(dev);
10125         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10126 }
10127
10128 #define NVRAM_TEST_SIZE 0x100
10129 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
10130 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
10131 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
10132 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10133 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10134
10135 static int tg3_test_nvram(struct tg3 *tp)
10136 {
10137         u32 csum, magic;
10138         __be32 *buf;
10139         int i, j, k, err = 0, size;
10140
10141         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10142                 return 0;
10143
10144         if (tg3_nvram_read(tp, 0, &magic) != 0)
10145                 return -EIO;
10146
10147         if (magic == TG3_EEPROM_MAGIC)
10148                 size = NVRAM_TEST_SIZE;
10149         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10150                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10151                     TG3_EEPROM_SB_FORMAT_1) {
10152                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10153                         case TG3_EEPROM_SB_REVISION_0:
10154                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10155                                 break;
10156                         case TG3_EEPROM_SB_REVISION_2:
10157                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10158                                 break;
10159                         case TG3_EEPROM_SB_REVISION_3:
10160                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10161                                 break;
10162                         default:
10163                                 return 0;
10164                         }
10165                 } else
10166                         return 0;
10167         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10168                 size = NVRAM_SELFBOOT_HW_SIZE;
10169         else
10170                 return -EIO;
10171
10172         buf = kmalloc(size, GFP_KERNEL);
10173         if (buf == NULL)
10174                 return -ENOMEM;
10175
10176         err = -EIO;
10177         for (i = 0, j = 0; i < size; i += 4, j++) {
10178                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10179                 if (err)
10180                         break;
10181         }
10182         if (i < size)
10183                 goto out;
10184
10185         /* Selfboot format */
10186         magic = be32_to_cpu(buf[0]);
10187         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10188             TG3_EEPROM_MAGIC_FW) {
10189                 u8 *buf8 = (u8 *) buf, csum8 = 0;
10190
10191                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10192                     TG3_EEPROM_SB_REVISION_2) {
10193                         /* For rev 2, the csum doesn't include the MBA. */
10194                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10195                                 csum8 += buf8[i];
10196                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10197                                 csum8 += buf8[i];
10198                 } else {
10199                         for (i = 0; i < size; i++)
10200                                 csum8 += buf8[i];
10201                 }
10202
10203                 if (csum8 == 0) {
10204                         err = 0;
10205                         goto out;
10206                 }
10207
10208                 err = -EIO;
10209                 goto out;
10210         }
10211
10212         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10213             TG3_EEPROM_MAGIC_HW) {
10214                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10215                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10216                 u8 *buf8 = (u8 *) buf;
10217
10218                 /* Separate the parity bits and the data bytes.  */
10219                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10220                         if ((i == 0) || (i == 8)) {
10221                                 int l;
10222                                 u8 msk;
10223
10224                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10225                                         parity[k++] = buf8[i] & msk;
10226                                 i++;
10227                         } else if (i == 16) {
10228                                 int l;
10229                                 u8 msk;
10230
10231                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10232                                         parity[k++] = buf8[i] & msk;
10233                                 i++;
10234
10235                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10236                                         parity[k++] = buf8[i] & msk;
10237                                 i++;
10238                         }
10239                         data[j++] = buf8[i];
10240                 }
10241
10242                 err = -EIO;
10243                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10244                         u8 hw8 = hweight8(data[i]);
10245
10246                         if ((hw8 & 0x1) && parity[i])
10247                                 goto out;
10248                         else if (!(hw8 & 0x1) && !parity[i])
10249                                 goto out;
10250                 }
10251                 err = 0;
10252                 goto out;
10253         }
10254
10255         /* Bootstrap checksum at offset 0x10 */
10256         csum = calc_crc((unsigned char *) buf, 0x10);
10257         if (csum != be32_to_cpu(buf[0x10/4]))
10258                 goto out;
10259
10260         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10261         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10262         if (csum != be32_to_cpu(buf[0xfc/4]))
10263                 goto out;
10264
10265         err = 0;
10266
10267 out:
10268         kfree(buf);
10269         return err;
10270 }
10271
10272 #define TG3_SERDES_TIMEOUT_SEC  2
10273 #define TG3_COPPER_TIMEOUT_SEC  6
10274
10275 static int tg3_test_link(struct tg3 *tp)
10276 {
10277         int i, max;
10278
10279         if (!netif_running(tp->dev))
10280                 return -ENODEV;
10281
10282         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10283                 max = TG3_SERDES_TIMEOUT_SEC;
10284         else
10285                 max = TG3_COPPER_TIMEOUT_SEC;
10286
10287         for (i = 0; i < max; i++) {
10288                 if (netif_carrier_ok(tp->dev))
10289                         return 0;
10290
10291                 if (msleep_interruptible(1000))
10292                         break;
10293         }
10294
10295         return -EIO;
10296 }
10297
10298 /* Only test the commonly used registers */
10299 static int tg3_test_registers(struct tg3 *tp)
10300 {
10301         int i, is_5705, is_5750;
10302         u32 offset, read_mask, write_mask, val, save_val, read_val;
10303         static struct {
10304                 u16 offset;
10305                 u16 flags;
10306 #define TG3_FL_5705     0x1
10307 #define TG3_FL_NOT_5705 0x2
10308 #define TG3_FL_NOT_5788 0x4
10309 #define TG3_FL_NOT_5750 0x8
10310                 u32 read_mask;
10311                 u32 write_mask;
10312         } reg_tbl[] = {
10313                 /* MAC Control Registers */
10314                 { MAC_MODE, TG3_FL_NOT_5705,
10315                         0x00000000, 0x00ef6f8c },
10316                 { MAC_MODE, TG3_FL_5705,
10317                         0x00000000, 0x01ef6b8c },
10318                 { MAC_STATUS, TG3_FL_NOT_5705,
10319                         0x03800107, 0x00000000 },
10320                 { MAC_STATUS, TG3_FL_5705,
10321                         0x03800100, 0x00000000 },
10322                 { MAC_ADDR_0_HIGH, 0x0000,
10323                         0x00000000, 0x0000ffff },
10324                 { MAC_ADDR_0_LOW, 0x0000,
10325                         0x00000000, 0xffffffff },
10326                 { MAC_RX_MTU_SIZE, 0x0000,
10327                         0x00000000, 0x0000ffff },
10328                 { MAC_TX_MODE, 0x0000,
10329                         0x00000000, 0x00000070 },
10330                 { MAC_TX_LENGTHS, 0x0000,
10331                         0x00000000, 0x00003fff },
10332                 { MAC_RX_MODE, TG3_FL_NOT_5705,
10333                         0x00000000, 0x000007fc },
10334                 { MAC_RX_MODE, TG3_FL_5705,
10335                         0x00000000, 0x000007dc },
10336                 { MAC_HASH_REG_0, 0x0000,
10337                         0x00000000, 0xffffffff },
10338                 { MAC_HASH_REG_1, 0x0000,
10339                         0x00000000, 0xffffffff },
10340                 { MAC_HASH_REG_2, 0x0000,
10341                         0x00000000, 0xffffffff },
10342                 { MAC_HASH_REG_3, 0x0000,
10343                         0x00000000, 0xffffffff },
10344
10345                 /* Receive Data and Receive BD Initiator Control Registers. */
10346                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10347                         0x00000000, 0xffffffff },
10348                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10349                         0x00000000, 0xffffffff },
10350                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10351                         0x00000000, 0x00000003 },
10352                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10353                         0x00000000, 0xffffffff },
10354                 { RCVDBDI_STD_BD+0, 0x0000,
10355                         0x00000000, 0xffffffff },
10356                 { RCVDBDI_STD_BD+4, 0x0000,
10357                         0x00000000, 0xffffffff },
10358                 { RCVDBDI_STD_BD+8, 0x0000,
10359                         0x00000000, 0xffff0002 },
10360                 { RCVDBDI_STD_BD+0xc, 0x0000,
10361                         0x00000000, 0xffffffff },
10362
10363                 /* Receive BD Initiator Control Registers. */
10364                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10365                         0x00000000, 0xffffffff },
10366                 { RCVBDI_STD_THRESH, TG3_FL_5705,
10367                         0x00000000, 0x000003ff },
10368                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10369                         0x00000000, 0xffffffff },
10370
10371                 /* Host Coalescing Control Registers. */
10372                 { HOSTCC_MODE, TG3_FL_NOT_5705,
10373                         0x00000000, 0x00000004 },
10374                 { HOSTCC_MODE, TG3_FL_5705,
10375                         0x00000000, 0x000000f6 },
10376                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10377                         0x00000000, 0xffffffff },
10378                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10379                         0x00000000, 0x000003ff },
10380                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10381                         0x00000000, 0xffffffff },
10382                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10383                         0x00000000, 0x000003ff },
10384                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10385                         0x00000000, 0xffffffff },
10386                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10387                         0x00000000, 0x000000ff },
10388                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10389                         0x00000000, 0xffffffff },
10390                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10391                         0x00000000, 0x000000ff },
10392                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10393                         0x00000000, 0xffffffff },
10394                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10395                         0x00000000, 0xffffffff },
10396                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10397                         0x00000000, 0xffffffff },
10398                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10399                         0x00000000, 0x000000ff },
10400                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10401                         0x00000000, 0xffffffff },
10402                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10403                         0x00000000, 0x000000ff },
10404                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10405                         0x00000000, 0xffffffff },
10406                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10407                         0x00000000, 0xffffffff },
10408                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10409                         0x00000000, 0xffffffff },
10410                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10411                         0x00000000, 0xffffffff },
10412                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10413                         0x00000000, 0xffffffff },
10414                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10415                         0xffffffff, 0x00000000 },
10416                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10417                         0xffffffff, 0x00000000 },
10418
10419                 /* Buffer Manager Control Registers. */
10420                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10421                         0x00000000, 0x007fff80 },
10422                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10423                         0x00000000, 0x007fffff },
10424                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10425                         0x00000000, 0x0000003f },
10426                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10427                         0x00000000, 0x000001ff },
10428                 { BUFMGR_MB_HIGH_WATER, 0x0000,
10429                         0x00000000, 0x000001ff },
10430                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10431                         0xffffffff, 0x00000000 },
10432                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10433                         0xffffffff, 0x00000000 },
10434
10435                 /* Mailbox Registers */
10436                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10437                         0x00000000, 0x000001ff },
10438                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10439                         0x00000000, 0x000001ff },
10440                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10441                         0x00000000, 0x000007ff },
10442                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10443                         0x00000000, 0x000001ff },
10444
10445                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10446         };
10447
10448         is_5705 = is_5750 = 0;
10449         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10450                 is_5705 = 1;
10451                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10452                         is_5750 = 1;
10453         }
10454
10455         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10456                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10457                         continue;
10458
10459                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10460                         continue;
10461
10462                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10463                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
10464                         continue;
10465
10466                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10467                         continue;
10468
10469                 offset = (u32) reg_tbl[i].offset;
10470                 read_mask = reg_tbl[i].read_mask;
10471                 write_mask = reg_tbl[i].write_mask;
10472
10473                 /* Save the original register content */
10474                 save_val = tr32(offset);
10475
10476                 /* Determine the read-only value. */
10477                 read_val = save_val & read_mask;
10478
10479                 /* Write zero to the register, then make sure the read-only bits
10480                  * are not changed and the read/write bits are all zeros.
10481                  */
10482                 tw32(offset, 0);
10483
10484                 val = tr32(offset);
10485
10486                 /* Test the read-only and read/write bits. */
10487                 if (((val & read_mask) != read_val) || (val & write_mask))
10488                         goto out;
10489
10490                 /* Write ones to all the bits defined by RdMask and WrMask, then
10491                  * make sure the read-only bits are not changed and the
10492                  * read/write bits are all ones.
10493                  */
10494                 tw32(offset, read_mask | write_mask);
10495
10496                 val = tr32(offset);
10497
10498                 /* Test the read-only bits. */
10499                 if ((val & read_mask) != read_val)
10500                         goto out;
10501
10502                 /* Test the read/write bits. */
10503                 if ((val & write_mask) != write_mask)
10504                         goto out;
10505
10506                 tw32(offset, save_val);
10507         }
10508
10509         return 0;
10510
10511 out:
10512         if (netif_msg_hw(tp))
10513                 netdev_err(tp->dev,
10514                            "Register test failed at offset %x\n", offset);
10515         tw32(offset, save_val);
10516         return -EIO;
10517 }
10518
10519 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10520 {
10521         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10522         int i;
10523         u32 j;
10524
10525         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10526                 for (j = 0; j < len; j += 4) {
10527                         u32 val;
10528
10529                         tg3_write_mem(tp, offset + j, test_pattern[i]);
10530                         tg3_read_mem(tp, offset + j, &val);
10531                         if (val != test_pattern[i])
10532                                 return -EIO;
10533                 }
10534         }
10535         return 0;
10536 }
10537
10538 static int tg3_test_memory(struct tg3 *tp)
10539 {
10540         static struct mem_entry {
10541                 u32 offset;
10542                 u32 len;
10543         } mem_tbl_570x[] = {
10544                 { 0x00000000, 0x00b50},
10545                 { 0x00002000, 0x1c000},
10546                 { 0xffffffff, 0x00000}
10547         }, mem_tbl_5705[] = {
10548                 { 0x00000100, 0x0000c},
10549                 { 0x00000200, 0x00008},
10550                 { 0x00004000, 0x00800},
10551                 { 0x00006000, 0x01000},
10552                 { 0x00008000, 0x02000},
10553                 { 0x00010000, 0x0e000},
10554                 { 0xffffffff, 0x00000}
10555         }, mem_tbl_5755[] = {
10556                 { 0x00000200, 0x00008},
10557                 { 0x00004000, 0x00800},
10558                 { 0x00006000, 0x00800},
10559                 { 0x00008000, 0x02000},
10560                 { 0x00010000, 0x0c000},
10561                 { 0xffffffff, 0x00000}
10562         }, mem_tbl_5906[] = {
10563                 { 0x00000200, 0x00008},
10564                 { 0x00004000, 0x00400},
10565                 { 0x00006000, 0x00400},
10566                 { 0x00008000, 0x01000},
10567                 { 0x00010000, 0x01000},
10568                 { 0xffffffff, 0x00000}
10569         }, mem_tbl_5717[] = {
10570                 { 0x00000200, 0x00008},
10571                 { 0x00010000, 0x0a000},
10572                 { 0x00020000, 0x13c00},
10573                 { 0xffffffff, 0x00000}
10574         }, mem_tbl_57765[] = {
10575                 { 0x00000200, 0x00008},
10576                 { 0x00004000, 0x00800},
10577                 { 0x00006000, 0x09800},
10578                 { 0x00010000, 0x0a000},
10579                 { 0xffffffff, 0x00000}
10580         };
10581         struct mem_entry *mem_tbl;
10582         int err = 0;
10583         int i;
10584
10585         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
10586             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
10587                 mem_tbl = mem_tbl_5717;
10588         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10589                 mem_tbl = mem_tbl_57765;
10590         else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10591                 mem_tbl = mem_tbl_5755;
10592         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10593                 mem_tbl = mem_tbl_5906;
10594         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10595                 mem_tbl = mem_tbl_5705;
10596         else
10597                 mem_tbl = mem_tbl_570x;
10598
10599         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10600                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10601                     mem_tbl[i].len)) != 0)
10602                         break;
10603         }
10604
10605         return err;
10606 }
10607
10608 #define TG3_MAC_LOOPBACK        0
10609 #define TG3_PHY_LOOPBACK        1
10610
10611 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10612 {
10613         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10614         u32 desc_idx, coal_now;
10615         struct sk_buff *skb, *rx_skb;
10616         u8 *tx_data;
10617         dma_addr_t map;
10618         int num_pkts, tx_len, rx_len, i, err;
10619         struct tg3_rx_buffer_desc *desc;
10620         struct tg3_napi *tnapi, *rnapi;
10621         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
10622
10623         tnapi = &tp->napi[0];
10624         rnapi = &tp->napi[0];
10625         if (tp->irq_cnt > 1) {
10626                 rnapi = &tp->napi[1];
10627                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
10628                         tnapi = &tp->napi[1];
10629         }
10630         coal_now = tnapi->coal_now | rnapi->coal_now;
10631
10632         if (loopback_mode == TG3_MAC_LOOPBACK) {
10633                 /* HW errata - mac loopback fails in some cases on 5780.
10634                  * Normal traffic and PHY loopback are not affected by
10635                  * errata.
10636                  */
10637                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10638                         return 0;
10639
10640                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10641                            MAC_MODE_PORT_INT_LPBACK;
10642                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10643                         mac_mode |= MAC_MODE_LINK_POLARITY;
10644                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10645                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10646                 else
10647                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10648                 tw32(MAC_MODE, mac_mode);
10649         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10650                 u32 val;
10651
10652                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10653                         tg3_phy_fet_toggle_apd(tp, false);
10654                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10655                 } else
10656                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10657
10658                 tg3_phy_toggle_automdix(tp, 0);
10659
10660                 tg3_writephy(tp, MII_BMCR, val);
10661                 udelay(40);
10662
10663                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10664                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10665                         tg3_writephy(tp, MII_TG3_FET_PTEST,
10666                                      MII_TG3_FET_PTEST_FRC_TX_LINK |
10667                                      MII_TG3_FET_PTEST_FRC_TX_LOCK);
10668                         /* The write needs to be flushed for the AC131 */
10669                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10670                                 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
10671                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10672                 } else
10673                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10674
10675                 /* reset to prevent losing 1st rx packet intermittently */
10676                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10677                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10678                         udelay(10);
10679                         tw32_f(MAC_RX_MODE, tp->rx_mode);
10680                 }
10681                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10682                         u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
10683                         if (masked_phy_id == TG3_PHY_ID_BCM5401)
10684                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10685                         else if (masked_phy_id == TG3_PHY_ID_BCM5411)
10686                                 mac_mode |= MAC_MODE_LINK_POLARITY;
10687                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
10688                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10689                 }
10690                 tw32(MAC_MODE, mac_mode);
10691         } else {
10692                 return -EINVAL;
10693         }
10694
10695         err = -EIO;
10696
10697         tx_len = 1514;
10698         skb = netdev_alloc_skb(tp->dev, tx_len);
10699         if (!skb)
10700                 return -ENOMEM;
10701
10702         tx_data = skb_put(skb, tx_len);
10703         memcpy(tx_data, tp->dev->dev_addr, 6);
10704         memset(tx_data + 6, 0x0, 8);
10705
10706         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10707
10708         for (i = 14; i < tx_len; i++)
10709                 tx_data[i] = (u8) (i & 0xff);
10710
10711         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10712         if (pci_dma_mapping_error(tp->pdev, map)) {
10713                 dev_kfree_skb(skb);
10714                 return -EIO;
10715         }
10716
10717         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10718                rnapi->coal_now);
10719
10720         udelay(10);
10721
10722         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10723
10724         num_pkts = 0;
10725
10726         tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10727
10728         tnapi->tx_prod++;
10729         num_pkts++;
10730
10731         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10732         tr32_mailbox(tnapi->prodmbox);
10733
10734         udelay(10);
10735
10736         /* 350 usec to allow enough time on some 10/100 Mbps devices.  */
10737         for (i = 0; i < 35; i++) {
10738                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10739                        coal_now);
10740
10741                 udelay(10);
10742
10743                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10744                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10745                 if ((tx_idx == tnapi->tx_prod) &&
10746                     (rx_idx == (rx_start_idx + num_pkts)))
10747                         break;
10748         }
10749
10750         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10751         dev_kfree_skb(skb);
10752
10753         if (tx_idx != tnapi->tx_prod)
10754                 goto out;
10755
10756         if (rx_idx != rx_start_idx + num_pkts)
10757                 goto out;
10758
10759         desc = &rnapi->rx_rcb[rx_start_idx];
10760         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10761         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10762         if (opaque_key != RXD_OPAQUE_RING_STD)
10763                 goto out;
10764
10765         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10766             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10767                 goto out;
10768
10769         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10770         if (rx_len != tx_len)
10771                 goto out;
10772
10773         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10774
10775         map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10776         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10777
10778         for (i = 14; i < tx_len; i++) {
10779                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10780                         goto out;
10781         }
10782         err = 0;
10783
10784         /* tg3_free_rings will unmap and free the rx_skb */
10785 out:
10786         return err;
10787 }
10788
10789 #define TG3_MAC_LOOPBACK_FAILED         1
10790 #define TG3_PHY_LOOPBACK_FAILED         2
10791 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
10792                                          TG3_PHY_LOOPBACK_FAILED)
10793
10794 static int tg3_test_loopback(struct tg3 *tp)
10795 {
10796         int err = 0;
10797         u32 cpmuctrl = 0;
10798
10799         if (!netif_running(tp->dev))
10800                 return TG3_LOOPBACK_FAILED;
10801
10802         err = tg3_reset_hw(tp, 1);
10803         if (err)
10804                 return TG3_LOOPBACK_FAILED;
10805
10806         /* Turn off gphy autopowerdown. */
10807         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10808                 tg3_phy_toggle_apd(tp, false);
10809
10810         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10811                 int i;
10812                 u32 status;
10813
10814                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10815
10816                 /* Wait for up to 40 microseconds to acquire lock. */
10817                 for (i = 0; i < 4; i++) {
10818                         status = tr32(TG3_CPMU_MUTEX_GNT);
10819                         if (status == CPMU_MUTEX_GNT_DRIVER)
10820                                 break;
10821                         udelay(10);
10822                 }
10823
10824                 if (status != CPMU_MUTEX_GNT_DRIVER)
10825                         return TG3_LOOPBACK_FAILED;
10826
10827                 /* Turn off link-based power management. */
10828                 cpmuctrl = tr32(TG3_CPMU_CTRL);
10829                 tw32(TG3_CPMU_CTRL,
10830                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10831                                   CPMU_CTRL_LINK_AWARE_MODE));
10832         }
10833
10834         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10835                 err |= TG3_MAC_LOOPBACK_FAILED;
10836
10837         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10838                 tw32(TG3_CPMU_CTRL, cpmuctrl);
10839
10840                 /* Release the mutex */
10841                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10842         }
10843
10844         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10845             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10846                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10847                         err |= TG3_PHY_LOOPBACK_FAILED;
10848         }
10849
10850         /* Re-enable gphy autopowerdown. */
10851         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10852                 tg3_phy_toggle_apd(tp, true);
10853
10854         return err;
10855 }
10856
10857 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10858                           u64 *data)
10859 {
10860         struct tg3 *tp = netdev_priv(dev);
10861
10862         if (tp->link_config.phy_is_low_power)
10863                 tg3_set_power_state(tp, PCI_D0);
10864
10865         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10866
10867         if (tg3_test_nvram(tp) != 0) {
10868                 etest->flags |= ETH_TEST_FL_FAILED;
10869                 data[0] = 1;
10870         }
10871         if (tg3_test_link(tp) != 0) {
10872                 etest->flags |= ETH_TEST_FL_FAILED;
10873                 data[1] = 1;
10874         }
10875         if (etest->flags & ETH_TEST_FL_OFFLINE) {
10876                 int err, err2 = 0, irq_sync = 0;
10877
10878                 if (netif_running(dev)) {
10879                         tg3_phy_stop(tp);
10880                         tg3_netif_stop(tp);
10881                         irq_sync = 1;
10882                 }
10883
10884                 tg3_full_lock(tp, irq_sync);
10885
10886                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10887                 err = tg3_nvram_lock(tp);
10888                 tg3_halt_cpu(tp, RX_CPU_BASE);
10889                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10890                         tg3_halt_cpu(tp, TX_CPU_BASE);
10891                 if (!err)
10892                         tg3_nvram_unlock(tp);
10893
10894                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10895                         tg3_phy_reset(tp);
10896
10897                 if (tg3_test_registers(tp) != 0) {
10898                         etest->flags |= ETH_TEST_FL_FAILED;
10899                         data[2] = 1;
10900                 }
10901                 if (tg3_test_memory(tp) != 0) {
10902                         etest->flags |= ETH_TEST_FL_FAILED;
10903                         data[3] = 1;
10904                 }
10905                 if ((data[4] = tg3_test_loopback(tp)) != 0)
10906                         etest->flags |= ETH_TEST_FL_FAILED;
10907
10908                 tg3_full_unlock(tp);
10909
10910                 if (tg3_test_interrupt(tp) != 0) {
10911                         etest->flags |= ETH_TEST_FL_FAILED;
10912                         data[5] = 1;
10913                 }
10914
10915                 tg3_full_lock(tp, 0);
10916
10917                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10918                 if (netif_running(dev)) {
10919                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10920                         err2 = tg3_restart_hw(tp, 1);
10921                         if (!err2)
10922                                 tg3_netif_start(tp);
10923                 }
10924
10925                 tg3_full_unlock(tp);
10926
10927                 if (irq_sync && !err2)
10928                         tg3_phy_start(tp);
10929         }
10930         if (tp->link_config.phy_is_low_power)
10931                 tg3_set_power_state(tp, PCI_D3hot);
10932
10933 }
10934
10935 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10936 {
10937         struct mii_ioctl_data *data = if_mii(ifr);
10938         struct tg3 *tp = netdev_priv(dev);
10939         int err;
10940
10941         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10942                 struct phy_device *phydev;
10943                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10944                         return -EAGAIN;
10945                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10946                 return phy_mii_ioctl(phydev, data, cmd);
10947         }
10948
10949         switch (cmd) {
10950         case SIOCGMIIPHY:
10951                 data->phy_id = tp->phy_addr;
10952
10953                 /* fallthru */
10954         case SIOCGMIIREG: {
10955                 u32 mii_regval;
10956
10957                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10958                         break;                  /* We have no PHY */
10959
10960                 if (tp->link_config.phy_is_low_power)
10961                         return -EAGAIN;
10962
10963                 spin_lock_bh(&tp->lock);
10964                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10965                 spin_unlock_bh(&tp->lock);
10966
10967                 data->val_out = mii_regval;
10968
10969                 return err;
10970         }
10971
10972         case SIOCSMIIREG:
10973                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10974                         break;                  /* We have no PHY */
10975
10976                 if (tp->link_config.phy_is_low_power)
10977                         return -EAGAIN;
10978
10979                 spin_lock_bh(&tp->lock);
10980                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10981                 spin_unlock_bh(&tp->lock);
10982
10983                 return err;
10984
10985         default:
10986                 /* do nothing */
10987                 break;
10988         }
10989         return -EOPNOTSUPP;
10990 }
10991
10992 #if TG3_VLAN_TAG_USED
10993 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10994 {
10995         struct tg3 *tp = netdev_priv(dev);
10996
10997         if (!netif_running(dev)) {
10998                 tp->vlgrp = grp;
10999                 return;
11000         }
11001
11002         tg3_netif_stop(tp);
11003
11004         tg3_full_lock(tp, 0);
11005
11006         tp->vlgrp = grp;
11007
11008         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11009         __tg3_set_rx_mode(dev);
11010
11011         tg3_netif_start(tp);
11012
11013         tg3_full_unlock(tp);
11014 }
11015 #endif
11016
11017 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11018 {
11019         struct tg3 *tp = netdev_priv(dev);
11020
11021         memcpy(ec, &tp->coal, sizeof(*ec));
11022         return 0;
11023 }
11024
11025 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11026 {
11027         struct tg3 *tp = netdev_priv(dev);
11028         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11029         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11030
11031         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11032                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11033                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11034                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11035                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11036         }
11037
11038         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11039             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11040             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11041             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11042             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11043             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11044             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11045             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11046             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11047             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11048                 return -EINVAL;
11049
11050         /* No rx interrupts will be generated if both are zero */
11051         if ((ec->rx_coalesce_usecs == 0) &&
11052             (ec->rx_max_coalesced_frames == 0))
11053                 return -EINVAL;
11054
11055         /* No tx interrupts will be generated if both are zero */
11056         if ((ec->tx_coalesce_usecs == 0) &&
11057             (ec->tx_max_coalesced_frames == 0))
11058                 return -EINVAL;
11059
11060         /* Only copy relevant parameters, ignore all others. */
11061         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11062         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11063         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11064         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11065         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11066         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11067         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11068         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11069         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11070
11071         if (netif_running(dev)) {
11072                 tg3_full_lock(tp, 0);
11073                 __tg3_set_coalesce(tp, &tp->coal);
11074                 tg3_full_unlock(tp);
11075         }
11076         return 0;
11077 }
11078
11079 static const struct ethtool_ops tg3_ethtool_ops = {
11080         .get_settings           = tg3_get_settings,
11081         .set_settings           = tg3_set_settings,
11082         .get_drvinfo            = tg3_get_drvinfo,
11083         .get_regs_len           = tg3_get_regs_len,
11084         .get_regs               = tg3_get_regs,
11085         .get_wol                = tg3_get_wol,
11086         .set_wol                = tg3_set_wol,
11087         .get_msglevel           = tg3_get_msglevel,
11088         .set_msglevel           = tg3_set_msglevel,
11089         .nway_reset             = tg3_nway_reset,
11090         .get_link               = ethtool_op_get_link,
11091         .get_eeprom_len         = tg3_get_eeprom_len,
11092         .get_eeprom             = tg3_get_eeprom,
11093         .set_eeprom             = tg3_set_eeprom,
11094         .get_ringparam          = tg3_get_ringparam,
11095         .set_ringparam          = tg3_set_ringparam,
11096         .get_pauseparam         = tg3_get_pauseparam,
11097         .set_pauseparam         = tg3_set_pauseparam,
11098         .get_rx_csum            = tg3_get_rx_csum,
11099         .set_rx_csum            = tg3_set_rx_csum,
11100         .set_tx_csum            = tg3_set_tx_csum,
11101         .set_sg                 = ethtool_op_set_sg,
11102         .set_tso                = tg3_set_tso,
11103         .self_test              = tg3_self_test,
11104         .get_strings            = tg3_get_strings,
11105         .phys_id                = tg3_phys_id,
11106         .get_ethtool_stats      = tg3_get_ethtool_stats,
11107         .get_coalesce           = tg3_get_coalesce,
11108         .set_coalesce           = tg3_set_coalesce,
11109         .get_sset_count         = tg3_get_sset_count,
11110 };
11111
11112 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11113 {
11114         u32 cursize, val, magic;
11115
11116         tp->nvram_size = EEPROM_CHIP_SIZE;
11117
11118         if (tg3_nvram_read(tp, 0, &magic) != 0)
11119                 return;
11120
11121         if ((magic != TG3_EEPROM_MAGIC) &&
11122             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11123             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11124                 return;
11125
11126         /*
11127          * Size the chip by reading offsets at increasing powers of two.
11128          * When we encounter our validation signature, we know the addressing
11129          * has wrapped around, and thus have our chip size.
11130          */
11131         cursize = 0x10;
11132
11133         while (cursize < tp->nvram_size) {
11134                 if (tg3_nvram_read(tp, cursize, &val) != 0)
11135                         return;
11136
11137                 if (val == magic)
11138                         break;
11139
11140                 cursize <<= 1;
11141         }
11142
11143         tp->nvram_size = cursize;
11144 }
11145
11146 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11147 {
11148         u32 val;
11149
11150         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11151             tg3_nvram_read(tp, 0, &val) != 0)
11152                 return;
11153
11154         /* Selfboot format */
11155         if (val != TG3_EEPROM_MAGIC) {
11156                 tg3_get_eeprom_size(tp);
11157                 return;
11158         }
11159
11160         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11161                 if (val != 0) {
11162                         /* This is confusing.  We want to operate on the
11163                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
11164                          * call will read from NVRAM and byteswap the data
11165                          * according to the byteswapping settings for all
11166                          * other register accesses.  This ensures the data we
11167                          * want will always reside in the lower 16-bits.
11168                          * However, the data in NVRAM is in LE format, which
11169                          * means the data from the NVRAM read will always be
11170                          * opposite the endianness of the CPU.  The 16-bit
11171                          * byteswap then brings the data to CPU endianness.
11172                          */
11173                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11174                         return;
11175                 }
11176         }
11177         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11178 }
11179
11180 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11181 {
11182         u32 nvcfg1;
11183
11184         nvcfg1 = tr32(NVRAM_CFG1);
11185         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11186                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11187         } else {
11188                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11189                 tw32(NVRAM_CFG1, nvcfg1);
11190         }
11191
11192         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11193             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11194                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11195                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11196                         tp->nvram_jedecnum = JEDEC_ATMEL;
11197                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11198                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11199                         break;
11200                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11201                         tp->nvram_jedecnum = JEDEC_ATMEL;
11202                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11203                         break;
11204                 case FLASH_VENDOR_ATMEL_EEPROM:
11205                         tp->nvram_jedecnum = JEDEC_ATMEL;
11206                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11207                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11208                         break;
11209                 case FLASH_VENDOR_ST:
11210                         tp->nvram_jedecnum = JEDEC_ST;
11211                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11212                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11213                         break;
11214                 case FLASH_VENDOR_SAIFUN:
11215                         tp->nvram_jedecnum = JEDEC_SAIFUN;
11216                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11217                         break;
11218                 case FLASH_VENDOR_SST_SMALL:
11219                 case FLASH_VENDOR_SST_LARGE:
11220                         tp->nvram_jedecnum = JEDEC_SST;
11221                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11222                         break;
11223                 }
11224         } else {
11225                 tp->nvram_jedecnum = JEDEC_ATMEL;
11226                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11227                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11228         }
11229 }
11230
11231 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11232 {
11233         switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11234         case FLASH_5752PAGE_SIZE_256:
11235                 tp->nvram_pagesize = 256;
11236                 break;
11237         case FLASH_5752PAGE_SIZE_512:
11238                 tp->nvram_pagesize = 512;
11239                 break;
11240         case FLASH_5752PAGE_SIZE_1K:
11241                 tp->nvram_pagesize = 1024;
11242                 break;
11243         case FLASH_5752PAGE_SIZE_2K:
11244                 tp->nvram_pagesize = 2048;
11245                 break;
11246         case FLASH_5752PAGE_SIZE_4K:
11247                 tp->nvram_pagesize = 4096;
11248                 break;
11249         case FLASH_5752PAGE_SIZE_264:
11250                 tp->nvram_pagesize = 264;
11251                 break;
11252         case FLASH_5752PAGE_SIZE_528:
11253                 tp->nvram_pagesize = 528;
11254                 break;
11255         }
11256 }
11257
11258 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11259 {
11260         u32 nvcfg1;
11261
11262         nvcfg1 = tr32(NVRAM_CFG1);
11263
11264         /* NVRAM protection for TPM */
11265         if (nvcfg1 & (1 << 27))
11266                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11267
11268         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11269         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11270         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11271                 tp->nvram_jedecnum = JEDEC_ATMEL;
11272                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11273                 break;
11274         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11275                 tp->nvram_jedecnum = JEDEC_ATMEL;
11276                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11277                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11278                 break;
11279         case FLASH_5752VENDOR_ST_M45PE10:
11280         case FLASH_5752VENDOR_ST_M45PE20:
11281         case FLASH_5752VENDOR_ST_M45PE40:
11282                 tp->nvram_jedecnum = JEDEC_ST;
11283                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11284                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11285                 break;
11286         }
11287
11288         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11289                 tg3_nvram_get_pagesize(tp, nvcfg1);
11290         } else {
11291                 /* For eeprom, set pagesize to maximum eeprom size */
11292                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11293
11294                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11295                 tw32(NVRAM_CFG1, nvcfg1);
11296         }
11297 }
11298
11299 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11300 {
11301         u32 nvcfg1, protect = 0;
11302
11303         nvcfg1 = tr32(NVRAM_CFG1);
11304
11305         /* NVRAM protection for TPM */
11306         if (nvcfg1 & (1 << 27)) {
11307                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11308                 protect = 1;
11309         }
11310
11311         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11312         switch (nvcfg1) {
11313         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11314         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11315         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11316         case FLASH_5755VENDOR_ATMEL_FLASH_5:
11317                 tp->nvram_jedecnum = JEDEC_ATMEL;
11318                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11319                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11320                 tp->nvram_pagesize = 264;
11321                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11322                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11323                         tp->nvram_size = (protect ? 0x3e200 :
11324                                           TG3_NVRAM_SIZE_512KB);
11325                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11326                         tp->nvram_size = (protect ? 0x1f200 :
11327                                           TG3_NVRAM_SIZE_256KB);
11328                 else
11329                         tp->nvram_size = (protect ? 0x1f200 :
11330                                           TG3_NVRAM_SIZE_128KB);
11331                 break;
11332         case FLASH_5752VENDOR_ST_M45PE10:
11333         case FLASH_5752VENDOR_ST_M45PE20:
11334         case FLASH_5752VENDOR_ST_M45PE40:
11335                 tp->nvram_jedecnum = JEDEC_ST;
11336                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11337                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11338                 tp->nvram_pagesize = 256;
11339                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11340                         tp->nvram_size = (protect ?
11341                                           TG3_NVRAM_SIZE_64KB :
11342                                           TG3_NVRAM_SIZE_128KB);
11343                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11344                         tp->nvram_size = (protect ?
11345                                           TG3_NVRAM_SIZE_64KB :
11346                                           TG3_NVRAM_SIZE_256KB);
11347                 else
11348                         tp->nvram_size = (protect ?
11349                                           TG3_NVRAM_SIZE_128KB :
11350                                           TG3_NVRAM_SIZE_512KB);
11351                 break;
11352         }
11353 }
11354
11355 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11356 {
11357         u32 nvcfg1;
11358
11359         nvcfg1 = tr32(NVRAM_CFG1);
11360
11361         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11362         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11363         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11364         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11365         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11366                 tp->nvram_jedecnum = JEDEC_ATMEL;
11367                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11368                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11369
11370                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11371                 tw32(NVRAM_CFG1, nvcfg1);
11372                 break;
11373         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11374         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11375         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11376         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11377                 tp->nvram_jedecnum = JEDEC_ATMEL;
11378                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11379                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11380                 tp->nvram_pagesize = 264;
11381                 break;
11382         case FLASH_5752VENDOR_ST_M45PE10:
11383         case FLASH_5752VENDOR_ST_M45PE20:
11384         case FLASH_5752VENDOR_ST_M45PE40:
11385                 tp->nvram_jedecnum = JEDEC_ST;
11386                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11387                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11388                 tp->nvram_pagesize = 256;
11389                 break;
11390         }
11391 }
11392
11393 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11394 {
11395         u32 nvcfg1, protect = 0;
11396
11397         nvcfg1 = tr32(NVRAM_CFG1);
11398
11399         /* NVRAM protection for TPM */
11400         if (nvcfg1 & (1 << 27)) {
11401                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11402                 protect = 1;
11403         }
11404
11405         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11406         switch (nvcfg1) {
11407         case FLASH_5761VENDOR_ATMEL_ADB021D:
11408         case FLASH_5761VENDOR_ATMEL_ADB041D:
11409         case FLASH_5761VENDOR_ATMEL_ADB081D:
11410         case FLASH_5761VENDOR_ATMEL_ADB161D:
11411         case FLASH_5761VENDOR_ATMEL_MDB021D:
11412         case FLASH_5761VENDOR_ATMEL_MDB041D:
11413         case FLASH_5761VENDOR_ATMEL_MDB081D:
11414         case FLASH_5761VENDOR_ATMEL_MDB161D:
11415                 tp->nvram_jedecnum = JEDEC_ATMEL;
11416                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11417                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11418                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11419                 tp->nvram_pagesize = 256;
11420                 break;
11421         case FLASH_5761VENDOR_ST_A_M45PE20:
11422         case FLASH_5761VENDOR_ST_A_M45PE40:
11423         case FLASH_5761VENDOR_ST_A_M45PE80:
11424         case FLASH_5761VENDOR_ST_A_M45PE16:
11425         case FLASH_5761VENDOR_ST_M_M45PE20:
11426         case FLASH_5761VENDOR_ST_M_M45PE40:
11427         case FLASH_5761VENDOR_ST_M_M45PE80:
11428         case FLASH_5761VENDOR_ST_M_M45PE16:
11429                 tp->nvram_jedecnum = JEDEC_ST;
11430                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11431                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11432                 tp->nvram_pagesize = 256;
11433                 break;
11434         }
11435
11436         if (protect) {
11437                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11438         } else {
11439                 switch (nvcfg1) {
11440                 case FLASH_5761VENDOR_ATMEL_ADB161D:
11441                 case FLASH_5761VENDOR_ATMEL_MDB161D:
11442                 case FLASH_5761VENDOR_ST_A_M45PE16:
11443                 case FLASH_5761VENDOR_ST_M_M45PE16:
11444                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11445                         break;
11446                 case FLASH_5761VENDOR_ATMEL_ADB081D:
11447                 case FLASH_5761VENDOR_ATMEL_MDB081D:
11448                 case FLASH_5761VENDOR_ST_A_M45PE80:
11449                 case FLASH_5761VENDOR_ST_M_M45PE80:
11450                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11451                         break;
11452                 case FLASH_5761VENDOR_ATMEL_ADB041D:
11453                 case FLASH_5761VENDOR_ATMEL_MDB041D:
11454                 case FLASH_5761VENDOR_ST_A_M45PE40:
11455                 case FLASH_5761VENDOR_ST_M_M45PE40:
11456                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11457                         break;
11458                 case FLASH_5761VENDOR_ATMEL_ADB021D:
11459                 case FLASH_5761VENDOR_ATMEL_MDB021D:
11460                 case FLASH_5761VENDOR_ST_A_M45PE20:
11461                 case FLASH_5761VENDOR_ST_M_M45PE20:
11462                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11463                         break;
11464                 }
11465         }
11466 }
11467
11468 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11469 {
11470         tp->nvram_jedecnum = JEDEC_ATMEL;
11471         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11472         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11473 }
11474
11475 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11476 {
11477         u32 nvcfg1;
11478
11479         nvcfg1 = tr32(NVRAM_CFG1);
11480
11481         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11482         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11483         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11484                 tp->nvram_jedecnum = JEDEC_ATMEL;
11485                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11486                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11487
11488                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11489                 tw32(NVRAM_CFG1, nvcfg1);
11490                 return;
11491         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11492         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11493         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11494         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11495         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11496         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11497         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11498                 tp->nvram_jedecnum = JEDEC_ATMEL;
11499                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11500                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11501
11502                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11503                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11504                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11505                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11506                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11507                         break;
11508                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11509                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11510                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11511                         break;
11512                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11513                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11514                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11515                         break;
11516                 }
11517                 break;
11518         case FLASH_5752VENDOR_ST_M45PE10:
11519         case FLASH_5752VENDOR_ST_M45PE20:
11520         case FLASH_5752VENDOR_ST_M45PE40:
11521                 tp->nvram_jedecnum = JEDEC_ST;
11522                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11523                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11524
11525                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11526                 case FLASH_5752VENDOR_ST_M45PE10:
11527                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11528                         break;
11529                 case FLASH_5752VENDOR_ST_M45PE20:
11530                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11531                         break;
11532                 case FLASH_5752VENDOR_ST_M45PE40:
11533                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11534                         break;
11535                 }
11536                 break;
11537         default:
11538                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11539                 return;
11540         }
11541
11542         tg3_nvram_get_pagesize(tp, nvcfg1);
11543         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11544                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11545 }
11546
11547
11548 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11549 {
11550         u32 nvcfg1;
11551
11552         nvcfg1 = tr32(NVRAM_CFG1);
11553
11554         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11555         case FLASH_5717VENDOR_ATMEL_EEPROM:
11556         case FLASH_5717VENDOR_MICRO_EEPROM:
11557                 tp->nvram_jedecnum = JEDEC_ATMEL;
11558                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11559                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11560
11561                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11562                 tw32(NVRAM_CFG1, nvcfg1);
11563                 return;
11564         case FLASH_5717VENDOR_ATMEL_MDB011D:
11565         case FLASH_5717VENDOR_ATMEL_ADB011B:
11566         case FLASH_5717VENDOR_ATMEL_ADB011D:
11567         case FLASH_5717VENDOR_ATMEL_MDB021D:
11568         case FLASH_5717VENDOR_ATMEL_ADB021B:
11569         case FLASH_5717VENDOR_ATMEL_ADB021D:
11570         case FLASH_5717VENDOR_ATMEL_45USPT:
11571                 tp->nvram_jedecnum = JEDEC_ATMEL;
11572                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11573                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11574
11575                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11576                 case FLASH_5717VENDOR_ATMEL_MDB021D:
11577                 case FLASH_5717VENDOR_ATMEL_ADB021B:
11578                 case FLASH_5717VENDOR_ATMEL_ADB021D:
11579                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11580                         break;
11581                 default:
11582                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11583                         break;
11584                 }
11585                 break;
11586         case FLASH_5717VENDOR_ST_M_M25PE10:
11587         case FLASH_5717VENDOR_ST_A_M25PE10:
11588         case FLASH_5717VENDOR_ST_M_M45PE10:
11589         case FLASH_5717VENDOR_ST_A_M45PE10:
11590         case FLASH_5717VENDOR_ST_M_M25PE20:
11591         case FLASH_5717VENDOR_ST_A_M25PE20:
11592         case FLASH_5717VENDOR_ST_M_M45PE20:
11593         case FLASH_5717VENDOR_ST_A_M45PE20:
11594         case FLASH_5717VENDOR_ST_25USPT:
11595         case FLASH_5717VENDOR_ST_45USPT:
11596                 tp->nvram_jedecnum = JEDEC_ST;
11597                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11598                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11599
11600                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11601                 case FLASH_5717VENDOR_ST_M_M25PE20:
11602                 case FLASH_5717VENDOR_ST_A_M25PE20:
11603                 case FLASH_5717VENDOR_ST_M_M45PE20:
11604                 case FLASH_5717VENDOR_ST_A_M45PE20:
11605                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11606                         break;
11607                 default:
11608                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11609                         break;
11610                 }
11611                 break;
11612         default:
11613                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11614                 return;
11615         }
11616
11617         tg3_nvram_get_pagesize(tp, nvcfg1);
11618         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11619                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11620 }
11621
11622 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11623 static void __devinit tg3_nvram_init(struct tg3 *tp)
11624 {
11625         tw32_f(GRC_EEPROM_ADDR,
11626              (EEPROM_ADDR_FSM_RESET |
11627               (EEPROM_DEFAULT_CLOCK_PERIOD <<
11628                EEPROM_ADDR_CLKPERD_SHIFT)));
11629
11630         msleep(1);
11631
11632         /* Enable seeprom accesses. */
11633         tw32_f(GRC_LOCAL_CTRL,
11634              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11635         udelay(100);
11636
11637         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11638             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11639                 tp->tg3_flags |= TG3_FLAG_NVRAM;
11640
11641                 if (tg3_nvram_lock(tp)) {
11642                         netdev_warn(tp->dev,
11643                                     "Cannot get nvram lock, %s failed\n",
11644                                     __func__);
11645                         return;
11646                 }
11647                 tg3_enable_nvram_access(tp);
11648
11649                 tp->nvram_size = 0;
11650
11651                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11652                         tg3_get_5752_nvram_info(tp);
11653                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11654                         tg3_get_5755_nvram_info(tp);
11655                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11656                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11657                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11658                         tg3_get_5787_nvram_info(tp);
11659                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11660                         tg3_get_5761_nvram_info(tp);
11661                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11662                         tg3_get_5906_nvram_info(tp);
11663                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11664                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11665                         tg3_get_57780_nvram_info(tp);
11666                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
11667                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
11668                         tg3_get_5717_nvram_info(tp);
11669                 else
11670                         tg3_get_nvram_info(tp);
11671
11672                 if (tp->nvram_size == 0)
11673                         tg3_get_nvram_size(tp);
11674
11675                 tg3_disable_nvram_access(tp);
11676                 tg3_nvram_unlock(tp);
11677
11678         } else {
11679                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11680
11681                 tg3_get_eeprom_size(tp);
11682         }
11683 }
11684
11685 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11686                                     u32 offset, u32 len, u8 *buf)
11687 {
11688         int i, j, rc = 0;
11689         u32 val;
11690
11691         for (i = 0; i < len; i += 4) {
11692                 u32 addr;
11693                 __be32 data;
11694
11695                 addr = offset + i;
11696
11697                 memcpy(&data, buf + i, 4);
11698
11699                 /*
11700                  * The SEEPROM interface expects the data to always be opposite
11701                  * the native endian format.  We accomplish this by reversing
11702                  * all the operations that would have been performed on the
11703                  * data from a call to tg3_nvram_read_be32().
11704                  */
11705                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11706
11707                 val = tr32(GRC_EEPROM_ADDR);
11708                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11709
11710                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11711                         EEPROM_ADDR_READ);
11712                 tw32(GRC_EEPROM_ADDR, val |
11713                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
11714                         (addr & EEPROM_ADDR_ADDR_MASK) |
11715                         EEPROM_ADDR_START |
11716                         EEPROM_ADDR_WRITE);
11717
11718                 for (j = 0; j < 1000; j++) {
11719                         val = tr32(GRC_EEPROM_ADDR);
11720
11721                         if (val & EEPROM_ADDR_COMPLETE)
11722                                 break;
11723                         msleep(1);
11724                 }
11725                 if (!(val & EEPROM_ADDR_COMPLETE)) {
11726                         rc = -EBUSY;
11727                         break;
11728                 }
11729         }
11730
11731         return rc;
11732 }
11733
11734 /* offset and length are dword aligned */
11735 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11736                 u8 *buf)
11737 {
11738         int ret = 0;
11739         u32 pagesize = tp->nvram_pagesize;
11740         u32 pagemask = pagesize - 1;
11741         u32 nvram_cmd;
11742         u8 *tmp;
11743
11744         tmp = kmalloc(pagesize, GFP_KERNEL);
11745         if (tmp == NULL)
11746                 return -ENOMEM;
11747
11748         while (len) {
11749                 int j;
11750                 u32 phy_addr, page_off, size;
11751
11752                 phy_addr = offset & ~pagemask;
11753
11754                 for (j = 0; j < pagesize; j += 4) {
11755                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
11756                                                   (__be32 *) (tmp + j));
11757                         if (ret)
11758                                 break;
11759                 }
11760                 if (ret)
11761                         break;
11762
11763                 page_off = offset & pagemask;
11764                 size = pagesize;
11765                 if (len < size)
11766                         size = len;
11767
11768                 len -= size;
11769
11770                 memcpy(tmp + page_off, buf, size);
11771
11772                 offset = offset + (pagesize - page_off);
11773
11774                 tg3_enable_nvram_access(tp);
11775
11776                 /*
11777                  * Before we can erase the flash page, we need
11778                  * to issue a special "write enable" command.
11779                  */
11780                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11781
11782                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11783                         break;
11784
11785                 /* Erase the target page */
11786                 tw32(NVRAM_ADDR, phy_addr);
11787
11788                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11789                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11790
11791                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11792                         break;
11793
11794                 /* Issue another write enable to start the write. */
11795                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11796
11797                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11798                         break;
11799
11800                 for (j = 0; j < pagesize; j += 4) {
11801                         __be32 data;
11802
11803                         data = *((__be32 *) (tmp + j));
11804
11805                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
11806
11807                         tw32(NVRAM_ADDR, phy_addr + j);
11808
11809                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11810                                 NVRAM_CMD_WR;
11811
11812                         if (j == 0)
11813                                 nvram_cmd |= NVRAM_CMD_FIRST;
11814                         else if (j == (pagesize - 4))
11815                                 nvram_cmd |= NVRAM_CMD_LAST;
11816
11817                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11818                                 break;
11819                 }
11820                 if (ret)
11821                         break;
11822         }
11823
11824         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11825         tg3_nvram_exec_cmd(tp, nvram_cmd);
11826
11827         kfree(tmp);
11828
11829         return ret;
11830 }
11831
11832 /* offset and length are dword aligned */
11833 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11834                 u8 *buf)
11835 {
11836         int i, ret = 0;
11837
11838         for (i = 0; i < len; i += 4, offset += 4) {
11839                 u32 page_off, phy_addr, nvram_cmd;
11840                 __be32 data;
11841
11842                 memcpy(&data, buf + i, 4);
11843                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11844
11845                 page_off = offset % tp->nvram_pagesize;
11846
11847                 phy_addr = tg3_nvram_phys_addr(tp, offset);
11848
11849                 tw32(NVRAM_ADDR, phy_addr);
11850
11851                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11852
11853                 if (page_off == 0 || i == 0)
11854                         nvram_cmd |= NVRAM_CMD_FIRST;
11855                 if (page_off == (tp->nvram_pagesize - 4))
11856                         nvram_cmd |= NVRAM_CMD_LAST;
11857
11858                 if (i == (len - 4))
11859                         nvram_cmd |= NVRAM_CMD_LAST;
11860
11861                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11862                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11863                     (tp->nvram_jedecnum == JEDEC_ST) &&
11864                     (nvram_cmd & NVRAM_CMD_FIRST)) {
11865
11866                         if ((ret = tg3_nvram_exec_cmd(tp,
11867                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11868                                 NVRAM_CMD_DONE)))
11869
11870                                 break;
11871                 }
11872                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11873                         /* We always do complete word writes to eeprom. */
11874                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11875                 }
11876
11877                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11878                         break;
11879         }
11880         return ret;
11881 }
11882
11883 /* offset and length are dword aligned */
11884 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11885 {
11886         int ret;
11887
11888         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11889                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11890                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
11891                 udelay(40);
11892         }
11893
11894         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11895                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11896         } else {
11897                 u32 grc_mode;
11898
11899                 ret = tg3_nvram_lock(tp);
11900                 if (ret)
11901                         return ret;
11902
11903                 tg3_enable_nvram_access(tp);
11904                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11905                     !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
11906                         tw32(NVRAM_WRITE1, 0x406);
11907
11908                 grc_mode = tr32(GRC_MODE);
11909                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11910
11911                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11912                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11913
11914                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
11915                                 buf);
11916                 } else {
11917                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11918                                 buf);
11919                 }
11920
11921                 grc_mode = tr32(GRC_MODE);
11922                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11923
11924                 tg3_disable_nvram_access(tp);
11925                 tg3_nvram_unlock(tp);
11926         }
11927
11928         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11929                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11930                 udelay(40);
11931         }
11932
11933         return ret;
11934 }
11935
11936 struct subsys_tbl_ent {
11937         u16 subsys_vendor, subsys_devid;
11938         u32 phy_id;
11939 };
11940
11941 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
11942         /* Broadcom boards. */
11943         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11944           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
11945         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11946           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
11947         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11948           TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
11949         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11950           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
11951         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11952           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
11953         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11954           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
11955         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11956           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
11957         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11958           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
11959         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11960           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
11961         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11962           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
11963         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11964           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
11965
11966         /* 3com boards. */
11967         { TG3PCI_SUBVENDOR_ID_3COM,
11968           TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
11969         { TG3PCI_SUBVENDOR_ID_3COM,
11970           TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
11971         { TG3PCI_SUBVENDOR_ID_3COM,
11972           TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
11973         { TG3PCI_SUBVENDOR_ID_3COM,
11974           TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
11975         { TG3PCI_SUBVENDOR_ID_3COM,
11976           TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
11977
11978         /* DELL boards. */
11979         { TG3PCI_SUBVENDOR_ID_DELL,
11980           TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
11981         { TG3PCI_SUBVENDOR_ID_DELL,
11982           TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
11983         { TG3PCI_SUBVENDOR_ID_DELL,
11984           TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
11985         { TG3PCI_SUBVENDOR_ID_DELL,
11986           TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
11987
11988         /* Compaq boards. */
11989         { TG3PCI_SUBVENDOR_ID_COMPAQ,
11990           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
11991         { TG3PCI_SUBVENDOR_ID_COMPAQ,
11992           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
11993         { TG3PCI_SUBVENDOR_ID_COMPAQ,
11994           TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
11995         { TG3PCI_SUBVENDOR_ID_COMPAQ,
11996           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
11997         { TG3PCI_SUBVENDOR_ID_COMPAQ,
11998           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
11999
12000         /* IBM boards. */
12001         { TG3PCI_SUBVENDOR_ID_IBM,
12002           TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
12003 };
12004
12005 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
12006 {
12007         int i;
12008
12009         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12010                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12011                      tp->pdev->subsystem_vendor) &&
12012                     (subsys_id_to_phy_id[i].subsys_devid ==
12013                      tp->pdev->subsystem_device))
12014                         return &subsys_id_to_phy_id[i];
12015         }
12016         return NULL;
12017 }
12018
12019 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12020 {
12021         u32 val;
12022         u16 pmcsr;
12023
12024         /* On some early chips the SRAM cannot be accessed in D3hot state,
12025          * so need make sure we're in D0.
12026          */
12027         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12028         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12029         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12030         msleep(1);
12031
12032         /* Make sure register accesses (indirect or otherwise)
12033          * will function correctly.
12034          */
12035         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12036                                tp->misc_host_ctrl);
12037
12038         /* The memory arbiter has to be enabled in order for SRAM accesses
12039          * to succeed.  Normally on powerup the tg3 chip firmware will make
12040          * sure it is enabled, but other entities such as system netboot
12041          * code might disable it.
12042          */
12043         val = tr32(MEMARB_MODE);
12044         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12045
12046         tp->phy_id = TG3_PHY_ID_INVALID;
12047         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12048
12049         /* Assume an onboard device and WOL capable by default.  */
12050         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12051
12052         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12053                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12054                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12055                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12056                 }
12057                 val = tr32(VCPU_CFGSHDW);
12058                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12059                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12060                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12061                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
12062                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12063                 goto done;
12064         }
12065
12066         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12067         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12068                 u32 nic_cfg, led_cfg;
12069                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12070                 int eeprom_phy_serdes = 0;
12071
12072                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12073                 tp->nic_sram_data_cfg = nic_cfg;
12074
12075                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12076                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12077                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12078                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12079                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12080                     (ver > 0) && (ver < 0x100))
12081                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12082
12083                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12084                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12085
12086                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12087                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12088                         eeprom_phy_serdes = 1;
12089
12090                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12091                 if (nic_phy_id != 0) {
12092                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12093                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12094
12095                         eeprom_phy_id  = (id1 >> 16) << 10;
12096                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
12097                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
12098                 } else
12099                         eeprom_phy_id = 0;
12100
12101                 tp->phy_id = eeprom_phy_id;
12102                 if (eeprom_phy_serdes) {
12103                         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12104                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12105                         else
12106                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
12107                 }
12108
12109                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12110                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12111                                     SHASTA_EXT_LED_MODE_MASK);
12112                 else
12113                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12114
12115                 switch (led_cfg) {
12116                 default:
12117                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12118                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12119                         break;
12120
12121                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12122                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12123                         break;
12124
12125                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12126                         tp->led_ctrl = LED_CTRL_MODE_MAC;
12127
12128                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12129                          * read on some older 5700/5701 bootcode.
12130                          */
12131                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12132                             ASIC_REV_5700 ||
12133                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
12134                             ASIC_REV_5701)
12135                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12136
12137                         break;
12138
12139                 case SHASTA_EXT_LED_SHARED:
12140                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
12141                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12142                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12143                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12144                                                  LED_CTRL_MODE_PHY_2);
12145                         break;
12146
12147                 case SHASTA_EXT_LED_MAC:
12148                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12149                         break;
12150
12151                 case SHASTA_EXT_LED_COMBO:
12152                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
12153                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12154                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12155                                                  LED_CTRL_MODE_PHY_2);
12156                         break;
12157
12158                 }
12159
12160                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12161                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12162                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12163                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12164
12165                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12166                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12167
12168                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12169                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12170                         if ((tp->pdev->subsystem_vendor ==
12171                              PCI_VENDOR_ID_ARIMA) &&
12172                             (tp->pdev->subsystem_device == 0x205a ||
12173                              tp->pdev->subsystem_device == 0x2063))
12174                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12175                 } else {
12176                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12177                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12178                 }
12179
12180                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12181                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12182                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12183                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12184                 }
12185
12186                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12187                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12188                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12189
12190                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
12191                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12192                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12193
12194                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12195                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12196                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12197
12198                 if (cfg2 & (1 << 17))
12199                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
12200
12201                 /* serdes signal pre-emphasis in register 0x590 set by */
12202                 /* bootcode if bit 18 is set */
12203                 if (cfg2 & (1 << 18))
12204                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
12205
12206                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12207                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
12208                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12209                         tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
12210
12211                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12212                         u32 cfg3;
12213
12214                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12215                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12216                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12217                 }
12218
12219                 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12220                         tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
12221                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12222                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12223                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12224                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12225         }
12226 done:
12227         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12228         device_set_wakeup_enable(&tp->pdev->dev,
12229                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12230 }
12231
12232 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12233 {
12234         int i;
12235         u32 val;
12236
12237         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12238         tw32(OTP_CTRL, cmd);
12239
12240         /* Wait for up to 1 ms for command to execute. */
12241         for (i = 0; i < 100; i++) {
12242                 val = tr32(OTP_STATUS);
12243                 if (val & OTP_STATUS_CMD_DONE)
12244                         break;
12245                 udelay(10);
12246         }
12247
12248         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12249 }
12250
12251 /* Read the gphy configuration from the OTP region of the chip.  The gphy
12252  * configuration is a 32-bit value that straddles the alignment boundary.
12253  * We do two 32-bit reads and then shift and merge the results.
12254  */
12255 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12256 {
12257         u32 bhalf_otp, thalf_otp;
12258
12259         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12260
12261         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12262                 return 0;
12263
12264         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12265
12266         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12267                 return 0;
12268
12269         thalf_otp = tr32(OTP_READ_DATA);
12270
12271         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12272
12273         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12274                 return 0;
12275
12276         bhalf_otp = tr32(OTP_READ_DATA);
12277
12278         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12279 }
12280
12281 static int __devinit tg3_phy_probe(struct tg3 *tp)
12282 {
12283         u32 hw_phy_id_1, hw_phy_id_2;
12284         u32 hw_phy_id, hw_phy_id_masked;
12285         int err;
12286
12287         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12288                 return tg3_phy_init(tp);
12289
12290         /* Reading the PHY ID register can conflict with ASF
12291          * firmware access to the PHY hardware.
12292          */
12293         err = 0;
12294         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12295             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12296                 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
12297         } else {
12298                 /* Now read the physical PHY_ID from the chip and verify
12299                  * that it is sane.  If it doesn't look good, we fall back
12300                  * to either the hard-coded table based PHY_ID and failing
12301                  * that the value found in the eeprom area.
12302                  */
12303                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12304                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12305
12306                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
12307                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12308                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
12309
12310                 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
12311         }
12312
12313         if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
12314                 tp->phy_id = hw_phy_id;
12315                 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
12316                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12317                 else
12318                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
12319         } else {
12320                 if (tp->phy_id != TG3_PHY_ID_INVALID) {
12321                         /* Do nothing, phy ID already set up in
12322                          * tg3_get_eeprom_hw_cfg().
12323                          */
12324                 } else {
12325                         struct subsys_tbl_ent *p;
12326
12327                         /* No eeprom signature?  Try the hardcoded
12328                          * subsys device table.
12329                          */
12330                         p = tg3_lookup_by_subsys(tp);
12331                         if (!p)
12332                                 return -ENODEV;
12333
12334                         tp->phy_id = p->phy_id;
12335                         if (!tp->phy_id ||
12336                             tp->phy_id == TG3_PHY_ID_BCM8002)
12337                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12338                 }
12339         }
12340
12341         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
12342             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12343             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12344                 u32 bmsr, adv_reg, tg3_ctrl, mask;
12345
12346                 tg3_readphy(tp, MII_BMSR, &bmsr);
12347                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12348                     (bmsr & BMSR_LSTATUS))
12349                         goto skip_phy_reset;
12350
12351                 err = tg3_phy_reset(tp);
12352                 if (err)
12353                         return err;
12354
12355                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12356                            ADVERTISE_100HALF | ADVERTISE_100FULL |
12357                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12358                 tg3_ctrl = 0;
12359                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12360                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12361                                     MII_TG3_CTRL_ADV_1000_FULL);
12362                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12363                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12364                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12365                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
12366                 }
12367
12368                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12369                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12370                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12371                 if (!tg3_copper_is_advertising_all(tp, mask)) {
12372                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12373
12374                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12375                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12376
12377                         tg3_writephy(tp, MII_BMCR,
12378                                      BMCR_ANENABLE | BMCR_ANRESTART);
12379                 }
12380                 tg3_phy_set_wirespeed(tp);
12381
12382                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12383                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12384                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12385         }
12386
12387 skip_phy_reset:
12388         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
12389                 err = tg3_init_5401phy_dsp(tp);
12390                 if (err)
12391                         return err;
12392
12393                 err = tg3_init_5401phy_dsp(tp);
12394         }
12395
12396         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
12397                 tp->link_config.advertising =
12398                         (ADVERTISED_1000baseT_Half |
12399                          ADVERTISED_1000baseT_Full |
12400                          ADVERTISED_Autoneg |
12401                          ADVERTISED_FIBRE);
12402         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12403                 tp->link_config.advertising &=
12404                         ~(ADVERTISED_1000baseT_Half |
12405                           ADVERTISED_1000baseT_Full);
12406
12407         return err;
12408 }
12409
12410 static void __devinit tg3_read_vpd(struct tg3 *tp)
12411 {
12412         u8 vpd_data[TG3_NVM_VPD_LEN];
12413         unsigned int block_end, rosize, len;
12414         int j, i = 0;
12415         u32 magic;
12416
12417         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12418             tg3_nvram_read(tp, 0x0, &magic))
12419                 goto out_not_found;
12420
12421         if (magic == TG3_EEPROM_MAGIC) {
12422                 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12423                         u32 tmp;
12424
12425                         /* The data is in little-endian format in NVRAM.
12426                          * Use the big-endian read routines to preserve
12427                          * the byte order as it exists in NVRAM.
12428                          */
12429                         if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12430                                 goto out_not_found;
12431
12432                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12433                 }
12434         } else {
12435                 ssize_t cnt;
12436                 unsigned int pos = 0;
12437
12438                 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12439                         cnt = pci_read_vpd(tp->pdev, pos,
12440                                            TG3_NVM_VPD_LEN - pos,
12441                                            &vpd_data[pos]);
12442                         if (cnt == -ETIMEDOUT || -EINTR)
12443                                 cnt = 0;
12444                         else if (cnt < 0)
12445                                 goto out_not_found;
12446                 }
12447                 if (pos != TG3_NVM_VPD_LEN)
12448                         goto out_not_found;
12449         }
12450
12451         i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
12452                              PCI_VPD_LRDT_RO_DATA);
12453         if (i < 0)
12454                 goto out_not_found;
12455
12456         rosize = pci_vpd_lrdt_size(&vpd_data[i]);
12457         block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
12458         i += PCI_VPD_LRDT_TAG_SIZE;
12459
12460         if (block_end > TG3_NVM_VPD_LEN)
12461                 goto out_not_found;
12462
12463         j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12464                                       PCI_VPD_RO_KEYWORD_MFR_ID);
12465         if (j > 0) {
12466                 len = pci_vpd_info_field_size(&vpd_data[j]);
12467
12468                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12469                 if (j + len > block_end || len != 4 ||
12470                     memcmp(&vpd_data[j], "1028", 4))
12471                         goto partno;
12472
12473                 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12474                                               PCI_VPD_RO_KEYWORD_VENDOR0);
12475                 if (j < 0)
12476                         goto partno;
12477
12478                 len = pci_vpd_info_field_size(&vpd_data[j]);
12479
12480                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12481                 if (j + len > block_end)
12482                         goto partno;
12483
12484                 memcpy(tp->fw_ver, &vpd_data[j], len);
12485                 strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
12486         }
12487
12488 partno:
12489         i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12490                                       PCI_VPD_RO_KEYWORD_PARTNO);
12491         if (i < 0)
12492                 goto out_not_found;
12493
12494         len = pci_vpd_info_field_size(&vpd_data[i]);
12495
12496         i += PCI_VPD_INFO_FLD_HDR_SIZE;
12497         if (len > TG3_BPN_SIZE ||
12498             (len + i) > TG3_NVM_VPD_LEN)
12499                 goto out_not_found;
12500
12501         memcpy(tp->board_part_number, &vpd_data[i], len);
12502
12503         return;
12504
12505 out_not_found:
12506         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12507                 strcpy(tp->board_part_number, "BCM95906");
12508         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12509                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12510                 strcpy(tp->board_part_number, "BCM57780");
12511         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12512                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12513                 strcpy(tp->board_part_number, "BCM57760");
12514         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12515                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12516                 strcpy(tp->board_part_number, "BCM57790");
12517         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12518                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12519                 strcpy(tp->board_part_number, "BCM57788");
12520         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12521                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
12522                 strcpy(tp->board_part_number, "BCM57761");
12523         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12524                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
12525                 strcpy(tp->board_part_number, "BCM57765");
12526         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12527                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
12528                 strcpy(tp->board_part_number, "BCM57781");
12529         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12530                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
12531                 strcpy(tp->board_part_number, "BCM57785");
12532         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12533                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
12534                 strcpy(tp->board_part_number, "BCM57791");
12535         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12536                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12537                 strcpy(tp->board_part_number, "BCM57795");
12538         else
12539                 strcpy(tp->board_part_number, "none");
12540 }
12541
12542 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12543 {
12544         u32 val;
12545
12546         if (tg3_nvram_read(tp, offset, &val) ||
12547             (val & 0xfc000000) != 0x0c000000 ||
12548             tg3_nvram_read(tp, offset + 4, &val) ||
12549             val != 0)
12550                 return 0;
12551
12552         return 1;
12553 }
12554
12555 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12556 {
12557         u32 val, offset, start, ver_offset;
12558         int i, dst_off;
12559         bool newver = false;
12560
12561         if (tg3_nvram_read(tp, 0xc, &offset) ||
12562             tg3_nvram_read(tp, 0x4, &start))
12563                 return;
12564
12565         offset = tg3_nvram_logical_addr(tp, offset);
12566
12567         if (tg3_nvram_read(tp, offset, &val))
12568                 return;
12569
12570         if ((val & 0xfc000000) == 0x0c000000) {
12571                 if (tg3_nvram_read(tp, offset + 4, &val))
12572                         return;
12573
12574                 if (val == 0)
12575                         newver = true;
12576         }
12577
12578         dst_off = strlen(tp->fw_ver);
12579
12580         if (newver) {
12581                 if (TG3_VER_SIZE - dst_off < 16 ||
12582                     tg3_nvram_read(tp, offset + 8, &ver_offset))
12583                         return;
12584
12585                 offset = offset + ver_offset - start;
12586                 for (i = 0; i < 16; i += 4) {
12587                         __be32 v;
12588                         if (tg3_nvram_read_be32(tp, offset + i, &v))
12589                                 return;
12590
12591                         memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
12592                 }
12593         } else {
12594                 u32 major, minor;
12595
12596                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12597                         return;
12598
12599                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12600                         TG3_NVM_BCVER_MAJSFT;
12601                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12602                 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
12603                          "v%d.%02d", major, minor);
12604         }
12605 }
12606
12607 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12608 {
12609         u32 val, major, minor;
12610
12611         /* Use native endian representation */
12612         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12613                 return;
12614
12615         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12616                 TG3_NVM_HWSB_CFG1_MAJSFT;
12617         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12618                 TG3_NVM_HWSB_CFG1_MINSFT;
12619
12620         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12621 }
12622
12623 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12624 {
12625         u32 offset, major, minor, build;
12626
12627         strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
12628
12629         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12630                 return;
12631
12632         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12633         case TG3_EEPROM_SB_REVISION_0:
12634                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12635                 break;
12636         case TG3_EEPROM_SB_REVISION_2:
12637                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12638                 break;
12639         case TG3_EEPROM_SB_REVISION_3:
12640                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12641                 break;
12642         case TG3_EEPROM_SB_REVISION_4:
12643                 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
12644                 break;
12645         case TG3_EEPROM_SB_REVISION_5:
12646                 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
12647                 break;
12648         default:
12649                 return;
12650         }
12651
12652         if (tg3_nvram_read(tp, offset, &val))
12653                 return;
12654
12655         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12656                 TG3_EEPROM_SB_EDH_BLD_SHFT;
12657         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12658                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12659         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
12660
12661         if (minor > 99 || build > 26)
12662                 return;
12663
12664         offset = strlen(tp->fw_ver);
12665         snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
12666                  " v%d.%02d", major, minor);
12667
12668         if (build > 0) {
12669                 offset = strlen(tp->fw_ver);
12670                 if (offset < TG3_VER_SIZE - 1)
12671                         tp->fw_ver[offset] = 'a' + build - 1;
12672         }
12673 }
12674
12675 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12676 {
12677         u32 val, offset, start;
12678         int i, vlen;
12679
12680         for (offset = TG3_NVM_DIR_START;
12681              offset < TG3_NVM_DIR_END;
12682              offset += TG3_NVM_DIRENT_SIZE) {
12683                 if (tg3_nvram_read(tp, offset, &val))
12684                         return;
12685
12686                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12687                         break;
12688         }
12689
12690         if (offset == TG3_NVM_DIR_END)
12691                 return;
12692
12693         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12694                 start = 0x08000000;
12695         else if (tg3_nvram_read(tp, offset - 4, &start))
12696                 return;
12697
12698         if (tg3_nvram_read(tp, offset + 4, &offset) ||
12699             !tg3_fw_img_is_valid(tp, offset) ||
12700             tg3_nvram_read(tp, offset + 8, &val))
12701                 return;
12702
12703         offset += val - start;
12704
12705         vlen = strlen(tp->fw_ver);
12706
12707         tp->fw_ver[vlen++] = ',';
12708         tp->fw_ver[vlen++] = ' ';
12709
12710         for (i = 0; i < 4; i++) {
12711                 __be32 v;
12712                 if (tg3_nvram_read_be32(tp, offset, &v))
12713                         return;
12714
12715                 offset += sizeof(v);
12716
12717                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12718                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12719                         break;
12720                 }
12721
12722                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12723                 vlen += sizeof(v);
12724         }
12725 }
12726
12727 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12728 {
12729         int vlen;
12730         u32 apedata;
12731
12732         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12733             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
12734                 return;
12735
12736         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12737         if (apedata != APE_SEG_SIG_MAGIC)
12738                 return;
12739
12740         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12741         if (!(apedata & APE_FW_STATUS_READY))
12742                 return;
12743
12744         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12745
12746         vlen = strlen(tp->fw_ver);
12747
12748         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12749                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12750                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12751                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12752                  (apedata & APE_FW_VERSION_BLDMSK));
12753 }
12754
12755 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12756 {
12757         u32 val;
12758         bool vpd_vers = false;
12759
12760         if (tp->fw_ver[0] != 0)
12761                 vpd_vers = true;
12762
12763         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12764                 strcat(tp->fw_ver, "sb");
12765                 return;
12766         }
12767
12768         if (tg3_nvram_read(tp, 0, &val))
12769                 return;
12770
12771         if (val == TG3_EEPROM_MAGIC)
12772                 tg3_read_bc_ver(tp);
12773         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12774                 tg3_read_sb_ver(tp, val);
12775         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12776                 tg3_read_hwsb_ver(tp);
12777         else
12778                 return;
12779
12780         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12781              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
12782                 goto done;
12783
12784         tg3_read_mgmtfw_ver(tp);
12785
12786 done:
12787         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12788 }
12789
12790 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12791
12792 static void inline vlan_features_add(struct net_device *dev, unsigned long flags)
12793 {
12794 #if TG3_VLAN_TAG_USED
12795         dev->vlan_features |= flags;
12796 #endif
12797 }
12798
12799 static int __devinit tg3_get_invariants(struct tg3 *tp)
12800 {
12801         static struct pci_device_id write_reorder_chipsets[] = {
12802                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12803                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12804                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12805                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12806                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12807                              PCI_DEVICE_ID_VIA_8385_0) },
12808                 { },
12809         };
12810         u32 misc_ctrl_reg;
12811         u32 pci_state_reg, grc_misc_cfg;
12812         u32 val;
12813         u16 pci_cmd;
12814         int err;
12815
12816         /* Force memory write invalidate off.  If we leave it on,
12817          * then on 5700_BX chips we have to enable a workaround.
12818          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12819          * to match the cacheline size.  The Broadcom driver have this
12820          * workaround but turns MWI off all the times so never uses
12821          * it.  This seems to suggest that the workaround is insufficient.
12822          */
12823         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12824         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12825         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12826
12827         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12828          * has the register indirect write enable bit set before
12829          * we try to access any of the MMIO registers.  It is also
12830          * critical that the PCI-X hw workaround situation is decided
12831          * before that as well.
12832          */
12833         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12834                               &misc_ctrl_reg);
12835
12836         tp->pci_chip_rev_id = (misc_ctrl_reg >>
12837                                MISC_HOST_CTRL_CHIPREV_SHIFT);
12838         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12839                 u32 prod_id_asic_rev;
12840
12841                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12842                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12843                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724 ||
12844                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719)
12845                         pci_read_config_dword(tp->pdev,
12846                                               TG3PCI_GEN2_PRODID_ASICREV,
12847                                               &prod_id_asic_rev);
12848                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
12849                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
12850                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
12851                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
12852                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
12853                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12854                         pci_read_config_dword(tp->pdev,
12855                                               TG3PCI_GEN15_PRODID_ASICREV,
12856                                               &prod_id_asic_rev);
12857                 else
12858                         pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12859                                               &prod_id_asic_rev);
12860
12861                 tp->pci_chip_rev_id = prod_id_asic_rev;
12862         }
12863
12864         /* Wrong chip ID in 5752 A0. This code can be removed later
12865          * as A0 is not in production.
12866          */
12867         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12868                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12869
12870         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12871          * we need to disable memory and use config. cycles
12872          * only to access all registers. The 5702/03 chips
12873          * can mistakenly decode the special cycles from the
12874          * ICH chipsets as memory write cycles, causing corruption
12875          * of register and memory space. Only certain ICH bridges
12876          * will drive special cycles with non-zero data during the
12877          * address phase which can fall within the 5703's address
12878          * range. This is not an ICH bug as the PCI spec allows
12879          * non-zero address during special cycles. However, only
12880          * these ICH bridges are known to drive non-zero addresses
12881          * during special cycles.
12882          *
12883          * Since special cycles do not cross PCI bridges, we only
12884          * enable this workaround if the 5703 is on the secondary
12885          * bus of these ICH bridges.
12886          */
12887         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12888             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12889                 static struct tg3_dev_id {
12890                         u32     vendor;
12891                         u32     device;
12892                         u32     rev;
12893                 } ich_chipsets[] = {
12894                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12895                           PCI_ANY_ID },
12896                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12897                           PCI_ANY_ID },
12898                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12899                           0xa },
12900                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12901                           PCI_ANY_ID },
12902                         { },
12903                 };
12904                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12905                 struct pci_dev *bridge = NULL;
12906
12907                 while (pci_id->vendor != 0) {
12908                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
12909                                                 bridge);
12910                         if (!bridge) {
12911                                 pci_id++;
12912                                 continue;
12913                         }
12914                         if (pci_id->rev != PCI_ANY_ID) {
12915                                 if (bridge->revision > pci_id->rev)
12916                                         continue;
12917                         }
12918                         if (bridge->subordinate &&
12919                             (bridge->subordinate->number ==
12920                              tp->pdev->bus->number)) {
12921
12922                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12923                                 pci_dev_put(bridge);
12924                                 break;
12925                         }
12926                 }
12927         }
12928
12929         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12930                 static struct tg3_dev_id {
12931                         u32     vendor;
12932                         u32     device;
12933                 } bridge_chipsets[] = {
12934                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12935                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12936                         { },
12937                 };
12938                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12939                 struct pci_dev *bridge = NULL;
12940
12941                 while (pci_id->vendor != 0) {
12942                         bridge = pci_get_device(pci_id->vendor,
12943                                                 pci_id->device,
12944                                                 bridge);
12945                         if (!bridge) {
12946                                 pci_id++;
12947                                 continue;
12948                         }
12949                         if (bridge->subordinate &&
12950                             (bridge->subordinate->number <=
12951                              tp->pdev->bus->number) &&
12952                             (bridge->subordinate->subordinate >=
12953                              tp->pdev->bus->number)) {
12954                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12955                                 pci_dev_put(bridge);
12956                                 break;
12957                         }
12958                 }
12959         }
12960
12961         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12962          * DMA addresses > 40-bit. This bridge may have other additional
12963          * 57xx devices behind it in some 4-port NIC designs for example.
12964          * Any tg3 device found behind the bridge will also need the 40-bit
12965          * DMA workaround.
12966          */
12967         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12968             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12969                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
12970                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12971                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
12972         } else {
12973                 struct pci_dev *bridge = NULL;
12974
12975                 do {
12976                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12977                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
12978                                                 bridge);
12979                         if (bridge && bridge->subordinate &&
12980                             (bridge->subordinate->number <=
12981                              tp->pdev->bus->number) &&
12982                             (bridge->subordinate->subordinate >=
12983                              tp->pdev->bus->number)) {
12984                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12985                                 pci_dev_put(bridge);
12986                                 break;
12987                         }
12988                 } while (bridge);
12989         }
12990
12991         /* Initialize misc host control in PCI block. */
12992         tp->misc_host_ctrl |= (misc_ctrl_reg &
12993                                MISC_HOST_CTRL_CHIPREV);
12994         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12995                                tp->misc_host_ctrl);
12996
12997         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
12998             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
12999             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13000                 tp->pdev_peer = tg3_find_peer(tp);
13001
13002         /* Intentionally exclude ASIC_REV_5906 */
13003         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13004             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13005             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13006             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13007             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13008             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13009             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13010             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13011             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13012                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13013
13014         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13015             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13016             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13017             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13018             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13019                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13020
13021         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13022             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13023                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13024
13025         /* 5700 B0 chips do not support checksumming correctly due
13026          * to hardware bugs.
13027          */
13028         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13029                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13030         else {
13031                 unsigned long features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_GRO;
13032
13033                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13034                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13035                         features |= NETIF_F_IPV6_CSUM;
13036                 tp->dev->features |= features;
13037                 vlan_features_add(tp->dev, features);
13038         }
13039
13040         /* Determine TSO capabilities */
13041         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13042             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13043             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13044                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13045         else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13046                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13047                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13048         else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13049                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13050                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13051                     tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13052                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13053         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13054                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13055                    tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13056                 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13057                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13058                         tp->fw_needed = FIRMWARE_TG3TSO5;
13059                 else
13060                         tp->fw_needed = FIRMWARE_TG3TSO;
13061         }
13062
13063         tp->irq_max = 1;
13064
13065         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13066                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13067                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13068                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13069                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13070                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13071                      tp->pdev_peer == tp->pdev))
13072                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13073
13074                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13075                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13076                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13077                 }
13078
13079                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13080                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13081                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13082                         tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13083                         tp->irq_max = TG3_IRQ_MAX_VECS;
13084                 }
13085         }
13086
13087         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13088             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13089             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13090                 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13091         else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13092                 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13093                 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13094         }
13095
13096         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13097             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13098             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13099                 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13100
13101         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13102             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13103             (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13104                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13105
13106         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13107                               &pci_state_reg);
13108
13109         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13110         if (tp->pcie_cap != 0) {
13111                 u16 lnkctl;
13112
13113                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13114
13115                 pcie_set_readrq(tp->pdev, 4096);
13116
13117                 pci_read_config_word(tp->pdev,
13118                                      tp->pcie_cap + PCI_EXP_LNKCTL,
13119                                      &lnkctl);
13120                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13121                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13122                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13123                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13124                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13125                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13126                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13127                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13128                 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13129                         tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13130                 }
13131         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13132                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13133         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13134                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13135                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13136                 if (!tp->pcix_cap) {
13137                         dev_err(&tp->pdev->dev,
13138                                 "Cannot find PCI-X capability, aborting\n");
13139                         return -EIO;
13140                 }
13141
13142                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13143                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13144         }
13145
13146         /* If we have an AMD 762 or VIA K8T800 chipset, write
13147          * reordering to the mailbox registers done by the host
13148          * controller can cause major troubles.  We read back from
13149          * every mailbox register write to force the writes to be
13150          * posted to the chip in order.
13151          */
13152         if (pci_dev_present(write_reorder_chipsets) &&
13153             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13154                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13155
13156         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13157                              &tp->pci_cacheline_sz);
13158         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13159                              &tp->pci_lat_timer);
13160         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13161             tp->pci_lat_timer < 64) {
13162                 tp->pci_lat_timer = 64;
13163                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13164                                       tp->pci_lat_timer);
13165         }
13166
13167         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13168                 /* 5700 BX chips need to have their TX producer index
13169                  * mailboxes written twice to workaround a bug.
13170                  */
13171                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13172
13173                 /* If we are in PCI-X mode, enable register write workaround.
13174                  *
13175                  * The workaround is to use indirect register accesses
13176                  * for all chip writes not to mailbox registers.
13177                  */
13178                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13179                         u32 pm_reg;
13180
13181                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13182
13183                         /* The chip can have it's power management PCI config
13184                          * space registers clobbered due to this bug.
13185                          * So explicitly force the chip into D0 here.
13186                          */
13187                         pci_read_config_dword(tp->pdev,
13188                                               tp->pm_cap + PCI_PM_CTRL,
13189                                               &pm_reg);
13190                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13191                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13192                         pci_write_config_dword(tp->pdev,
13193                                                tp->pm_cap + PCI_PM_CTRL,
13194                                                pm_reg);
13195
13196                         /* Also, force SERR#/PERR# in PCI command. */
13197                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13198                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13199                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13200                 }
13201         }
13202
13203         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13204                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13205         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13206                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13207
13208         /* Chip-specific fixup from Broadcom driver */
13209         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13210             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13211                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13212                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13213         }
13214
13215         /* Default fast path register access methods */
13216         tp->read32 = tg3_read32;
13217         tp->write32 = tg3_write32;
13218         tp->read32_mbox = tg3_read32;
13219         tp->write32_mbox = tg3_write32;
13220         tp->write32_tx_mbox = tg3_write32;
13221         tp->write32_rx_mbox = tg3_write32;
13222
13223         /* Various workaround register access methods */
13224         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13225                 tp->write32 = tg3_write_indirect_reg32;
13226         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13227                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13228                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13229                 /*
13230                  * Back to back register writes can cause problems on these
13231                  * chips, the workaround is to read back all reg writes
13232                  * except those to mailbox regs.
13233                  *
13234                  * See tg3_write_indirect_reg32().
13235                  */
13236                 tp->write32 = tg3_write_flush_reg32;
13237         }
13238
13239         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13240             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13241                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13242                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13243                         tp->write32_rx_mbox = tg3_write_flush_reg32;
13244         }
13245
13246         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13247                 tp->read32 = tg3_read_indirect_reg32;
13248                 tp->write32 = tg3_write_indirect_reg32;
13249                 tp->read32_mbox = tg3_read_indirect_mbox;
13250                 tp->write32_mbox = tg3_write_indirect_mbox;
13251                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13252                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13253
13254                 iounmap(tp->regs);
13255                 tp->regs = NULL;
13256
13257                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13258                 pci_cmd &= ~PCI_COMMAND_MEMORY;
13259                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13260         }
13261         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13262                 tp->read32_mbox = tg3_read32_mbox_5906;
13263                 tp->write32_mbox = tg3_write32_mbox_5906;
13264                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13265                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13266         }
13267
13268         if (tp->write32 == tg3_write_indirect_reg32 ||
13269             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13270              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13271               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13272                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13273
13274         /* Get eeprom hw config before calling tg3_set_power_state().
13275          * In particular, the TG3_FLG2_IS_NIC flag must be
13276          * determined before calling tg3_set_power_state() so that
13277          * we know whether or not to switch out of Vaux power.
13278          * When the flag is set, it means that GPIO1 is used for eeprom
13279          * write protect and also implies that it is a LOM where GPIOs
13280          * are not used to switch power.
13281          */
13282         tg3_get_eeprom_hw_cfg(tp);
13283
13284         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13285                 /* Allow reads and writes to the
13286                  * APE register and memory space.
13287                  */
13288                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13289                                  PCISTATE_ALLOW_APE_SHMEM_WR |
13290                                  PCISTATE_ALLOW_APE_PSPACE_WR;
13291                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13292                                        pci_state_reg);
13293         }
13294
13295         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13296             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13297             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13298             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13299             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13300             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13301             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13302                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13303
13304         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13305          * GPIO1 driven high will bring 5700's external PHY out of reset.
13306          * It is also used as eeprom write protect on LOMs.
13307          */
13308         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13309         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13310             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13311                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13312                                        GRC_LCLCTRL_GPIO_OUTPUT1);
13313         /* Unused GPIO3 must be driven as output on 5752 because there
13314          * are no pull-up resistors on unused GPIO pins.
13315          */
13316         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13317                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13318
13319         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13320             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13321             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13322                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13323
13324         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13325             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13326                 /* Turn off the debug UART. */
13327                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13328                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13329                         /* Keep VMain power. */
13330                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13331                                               GRC_LCLCTRL_GPIO_OUTPUT0;
13332         }
13333
13334         /* Force the chip into D0. */
13335         err = tg3_set_power_state(tp, PCI_D0);
13336         if (err) {
13337                 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
13338                 return err;
13339         }
13340
13341         /* Derive initial jumbo mode from MTU assigned in
13342          * ether_setup() via the alloc_etherdev() call
13343          */
13344         if (tp->dev->mtu > ETH_DATA_LEN &&
13345             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13346                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13347
13348         /* Determine WakeOnLan speed to use. */
13349         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13350             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13351             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13352             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13353                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13354         } else {
13355                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13356         }
13357
13358         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13359                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
13360
13361         /* A few boards don't want Ethernet@WireSpeed phy feature */
13362         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13363             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13364              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13365              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13366             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
13367             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
13368                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
13369
13370         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13371             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13372                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
13373         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13374                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
13375
13376         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13377             !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
13378             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13379             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13380             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
13381             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719 &&
13382             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
13383                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13384                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13385                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13386                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13387                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13388                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13389                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
13390                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13391                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
13392                 } else
13393                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
13394         }
13395
13396         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13397             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13398                 tp->phy_otp = tg3_read_otp_phycfg(tp);
13399                 if (tp->phy_otp == 0)
13400                         tp->phy_otp = TG3_OTP_DEFAULT;
13401         }
13402
13403         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13404                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13405         else
13406                 tp->mi_mode = MAC_MI_MODE_BASE;
13407
13408         tp->coalesce_mode = 0;
13409         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13410             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13411                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13412
13413         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13414             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13415                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13416
13417         err = tg3_mdio_init(tp);
13418         if (err)
13419                 return err;
13420
13421         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
13422             (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0 ||
13423                  (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
13424                 return -ENOTSUPP;
13425
13426         /* Initialize data/descriptor byte/word swapping. */
13427         val = tr32(GRC_MODE);
13428         val &= GRC_MODE_HOST_STACKUP;
13429         tw32(GRC_MODE, val | tp->grc_mode);
13430
13431         tg3_switch_clocks(tp);
13432
13433         /* Clear this out for sanity. */
13434         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13435
13436         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13437                               &pci_state_reg);
13438         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13439             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13440                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13441
13442                 if (chiprevid == CHIPREV_ID_5701_A0 ||
13443                     chiprevid == CHIPREV_ID_5701_B0 ||
13444                     chiprevid == CHIPREV_ID_5701_B2 ||
13445                     chiprevid == CHIPREV_ID_5701_B5) {
13446                         void __iomem *sram_base;
13447
13448                         /* Write some dummy words into the SRAM status block
13449                          * area, see if it reads back correctly.  If the return
13450                          * value is bad, force enable the PCIX workaround.
13451                          */
13452                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13453
13454                         writel(0x00000000, sram_base);
13455                         writel(0x00000000, sram_base + 4);
13456                         writel(0xffffffff, sram_base + 4);
13457                         if (readl(sram_base) != 0x00000000)
13458                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13459                 }
13460         }
13461
13462         udelay(50);
13463         tg3_nvram_init(tp);
13464
13465         grc_misc_cfg = tr32(GRC_MISC_CFG);
13466         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13467
13468         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13469             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13470              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13471                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13472
13473         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13474             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13475                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13476         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13477                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13478                                       HOSTCC_MODE_CLRTICK_TXBD);
13479
13480                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13481                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13482                                        tp->misc_host_ctrl);
13483         }
13484
13485         /* Preserve the APE MAC_MODE bits */
13486         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13487                 tp->mac_mode = tr32(MAC_MODE) |
13488                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13489         else
13490                 tp->mac_mode = TG3_DEF_MAC_MODE;
13491
13492         /* these are limited to 10/100 only */
13493         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13494              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13495             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13496              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13497              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13498               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13499               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13500             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13501              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13502               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13503               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13504             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13505             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13506             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
13507             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
13508                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13509
13510         err = tg3_phy_probe(tp);
13511         if (err) {
13512                 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
13513                 /* ... but do not return immediately ... */
13514                 tg3_mdio_fini(tp);
13515         }
13516
13517         tg3_read_vpd(tp);
13518         tg3_read_fw_ver(tp);
13519
13520         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13521                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13522         } else {
13523                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13524                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13525                 else
13526                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13527         }
13528
13529         /* 5700 {AX,BX} chips have a broken status block link
13530          * change bit implementation, so we must use the
13531          * status register in those cases.
13532          */
13533         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13534                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13535         else
13536                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13537
13538         /* The led_ctrl is set during tg3_phy_probe, here we might
13539          * have to force the link status polling mechanism based
13540          * upon subsystem IDs.
13541          */
13542         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13543             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13544             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13545                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13546                                   TG3_FLAG_USE_LINKCHG_REG);
13547         }
13548
13549         /* For all SERDES we poll the MAC status register. */
13550         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13551                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13552         else
13553                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13554
13555         tp->rx_offset = NET_IP_ALIGN + TG3_RX_HEADROOM;
13556         tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
13557         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13558             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
13559                 tp->rx_offset -= NET_IP_ALIGN;
13560 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
13561                 tp->rx_copy_thresh = ~(u16)0;
13562 #endif
13563         }
13564
13565         tp->rx_std_max_post = TG3_RX_RING_SIZE;
13566
13567         /* Increment the rx prod index on the rx std ring by at most
13568          * 8 for these chips to workaround hw errata.
13569          */
13570         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13571             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13572             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13573                 tp->rx_std_max_post = 8;
13574
13575         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13576                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13577                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
13578
13579         return err;
13580 }
13581
13582 #ifdef CONFIG_SPARC
13583 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13584 {
13585         struct net_device *dev = tp->dev;
13586         struct pci_dev *pdev = tp->pdev;
13587         struct device_node *dp = pci_device_to_OF_node(pdev);
13588         const unsigned char *addr;
13589         int len;
13590
13591         addr = of_get_property(dp, "local-mac-address", &len);
13592         if (addr && len == 6) {
13593                 memcpy(dev->dev_addr, addr, 6);
13594                 memcpy(dev->perm_addr, dev->dev_addr, 6);
13595                 return 0;
13596         }
13597         return -ENODEV;
13598 }
13599
13600 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13601 {
13602         struct net_device *dev = tp->dev;
13603
13604         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13605         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13606         return 0;
13607 }
13608 #endif
13609
13610 static int __devinit tg3_get_device_address(struct tg3 *tp)
13611 {
13612         struct net_device *dev = tp->dev;
13613         u32 hi, lo, mac_offset;
13614         int addr_ok = 0;
13615
13616 #ifdef CONFIG_SPARC
13617         if (!tg3_get_macaddr_sparc(tp))
13618                 return 0;
13619 #endif
13620
13621         mac_offset = 0x7c;
13622         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13623             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13624                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13625                         mac_offset = 0xcc;
13626                 if (tg3_nvram_lock(tp))
13627                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13628                 else
13629                         tg3_nvram_unlock(tp);
13630         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13631                    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
13632                 if (PCI_FUNC(tp->pdev->devfn) & 1)
13633                         mac_offset = 0xcc;
13634                 if (PCI_FUNC(tp->pdev->devfn) > 1)
13635                         mac_offset += 0x18c;
13636         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13637                 mac_offset = 0x10;
13638
13639         /* First try to get it from MAC address mailbox. */
13640         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13641         if ((hi >> 16) == 0x484b) {
13642                 dev->dev_addr[0] = (hi >>  8) & 0xff;
13643                 dev->dev_addr[1] = (hi >>  0) & 0xff;
13644
13645                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13646                 dev->dev_addr[2] = (lo >> 24) & 0xff;
13647                 dev->dev_addr[3] = (lo >> 16) & 0xff;
13648                 dev->dev_addr[4] = (lo >>  8) & 0xff;
13649                 dev->dev_addr[5] = (lo >>  0) & 0xff;
13650
13651                 /* Some old bootcode may report a 0 MAC address in SRAM */
13652                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13653         }
13654         if (!addr_ok) {
13655                 /* Next, try NVRAM. */
13656                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13657                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13658                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13659                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13660                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13661                 }
13662                 /* Finally just fetch it out of the MAC control regs. */
13663                 else {
13664                         hi = tr32(MAC_ADDR_0_HIGH);
13665                         lo = tr32(MAC_ADDR_0_LOW);
13666
13667                         dev->dev_addr[5] = lo & 0xff;
13668                         dev->dev_addr[4] = (lo >> 8) & 0xff;
13669                         dev->dev_addr[3] = (lo >> 16) & 0xff;
13670                         dev->dev_addr[2] = (lo >> 24) & 0xff;
13671                         dev->dev_addr[1] = hi & 0xff;
13672                         dev->dev_addr[0] = (hi >> 8) & 0xff;
13673                 }
13674         }
13675
13676         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13677 #ifdef CONFIG_SPARC
13678                 if (!tg3_get_default_macaddr_sparc(tp))
13679                         return 0;
13680 #endif
13681                 return -EINVAL;
13682         }
13683         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13684         return 0;
13685 }
13686
13687 #define BOUNDARY_SINGLE_CACHELINE       1
13688 #define BOUNDARY_MULTI_CACHELINE        2
13689
13690 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13691 {
13692         int cacheline_size;
13693         u8 byte;
13694         int goal;
13695
13696         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13697         if (byte == 0)
13698                 cacheline_size = 1024;
13699         else
13700                 cacheline_size = (int) byte * 4;
13701
13702         /* On 5703 and later chips, the boundary bits have no
13703          * effect.
13704          */
13705         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13706             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13707             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13708                 goto out;
13709
13710 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13711         goal = BOUNDARY_MULTI_CACHELINE;
13712 #else
13713 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13714         goal = BOUNDARY_SINGLE_CACHELINE;
13715 #else
13716         goal = 0;
13717 #endif
13718 #endif
13719
13720         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13721             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13722             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13723                 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13724                 goto out;
13725         }
13726
13727         if (!goal)
13728                 goto out;
13729
13730         /* PCI controllers on most RISC systems tend to disconnect
13731          * when a device tries to burst across a cache-line boundary.
13732          * Therefore, letting tg3 do so just wastes PCI bandwidth.
13733          *
13734          * Unfortunately, for PCI-E there are only limited
13735          * write-side controls for this, and thus for reads
13736          * we will still get the disconnects.  We'll also waste
13737          * these PCI cycles for both read and write for chips
13738          * other than 5700 and 5701 which do not implement the
13739          * boundary bits.
13740          */
13741         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13742             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13743                 switch (cacheline_size) {
13744                 case 16:
13745                 case 32:
13746                 case 64:
13747                 case 128:
13748                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13749                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13750                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13751                         } else {
13752                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13753                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13754                         }
13755                         break;
13756
13757                 case 256:
13758                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13759                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13760                         break;
13761
13762                 default:
13763                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13764                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13765                         break;
13766                 }
13767         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13768                 switch (cacheline_size) {
13769                 case 16:
13770                 case 32:
13771                 case 64:
13772                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13773                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13774                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13775                                 break;
13776                         }
13777                         /* fallthrough */
13778                 case 128:
13779                 default:
13780                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13781                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13782                         break;
13783                 }
13784         } else {
13785                 switch (cacheline_size) {
13786                 case 16:
13787                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13788                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13789                                         DMA_RWCTRL_WRITE_BNDRY_16);
13790                                 break;
13791                         }
13792                         /* fallthrough */
13793                 case 32:
13794                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13795                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13796                                         DMA_RWCTRL_WRITE_BNDRY_32);
13797                                 break;
13798                         }
13799                         /* fallthrough */
13800                 case 64:
13801                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13802                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13803                                         DMA_RWCTRL_WRITE_BNDRY_64);
13804                                 break;
13805                         }
13806                         /* fallthrough */
13807                 case 128:
13808                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13809                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13810                                         DMA_RWCTRL_WRITE_BNDRY_128);
13811                                 break;
13812                         }
13813                         /* fallthrough */
13814                 case 256:
13815                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
13816                                 DMA_RWCTRL_WRITE_BNDRY_256);
13817                         break;
13818                 case 512:
13819                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
13820                                 DMA_RWCTRL_WRITE_BNDRY_512);
13821                         break;
13822                 case 1024:
13823                 default:
13824                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13825                                 DMA_RWCTRL_WRITE_BNDRY_1024);
13826                         break;
13827                 }
13828         }
13829
13830 out:
13831         return val;
13832 }
13833
13834 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13835 {
13836         struct tg3_internal_buffer_desc test_desc;
13837         u32 sram_dma_descs;
13838         int i, ret;
13839
13840         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13841
13842         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13843         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13844         tw32(RDMAC_STATUS, 0);
13845         tw32(WDMAC_STATUS, 0);
13846
13847         tw32(BUFMGR_MODE, 0);
13848         tw32(FTQ_RESET, 0);
13849
13850         test_desc.addr_hi = ((u64) buf_dma) >> 32;
13851         test_desc.addr_lo = buf_dma & 0xffffffff;
13852         test_desc.nic_mbuf = 0x00002100;
13853         test_desc.len = size;
13854
13855         /*
13856          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13857          * the *second* time the tg3 driver was getting loaded after an
13858          * initial scan.
13859          *
13860          * Broadcom tells me:
13861          *   ...the DMA engine is connected to the GRC block and a DMA
13862          *   reset may affect the GRC block in some unpredictable way...
13863          *   The behavior of resets to individual blocks has not been tested.
13864          *
13865          * Broadcom noted the GRC reset will also reset all sub-components.
13866          */
13867         if (to_device) {
13868                 test_desc.cqid_sqid = (13 << 8) | 2;
13869
13870                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13871                 udelay(40);
13872         } else {
13873                 test_desc.cqid_sqid = (16 << 8) | 7;
13874
13875                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13876                 udelay(40);
13877         }
13878         test_desc.flags = 0x00000005;
13879
13880         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13881                 u32 val;
13882
13883                 val = *(((u32 *)&test_desc) + i);
13884                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13885                                        sram_dma_descs + (i * sizeof(u32)));
13886                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13887         }
13888         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13889
13890         if (to_device)
13891                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13892         else
13893                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13894
13895         ret = -ENODEV;
13896         for (i = 0; i < 40; i++) {
13897                 u32 val;
13898
13899                 if (to_device)
13900                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13901                 else
13902                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13903                 if ((val & 0xffff) == sram_dma_descs) {
13904                         ret = 0;
13905                         break;
13906                 }
13907
13908                 udelay(100);
13909         }
13910
13911         return ret;
13912 }
13913
13914 #define TEST_BUFFER_SIZE        0x2000
13915
13916 static int __devinit tg3_test_dma(struct tg3 *tp)
13917 {
13918         dma_addr_t buf_dma;
13919         u32 *buf, saved_dma_rwctrl;
13920         int ret = 0;
13921
13922         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13923         if (!buf) {
13924                 ret = -ENOMEM;
13925                 goto out_nofree;
13926         }
13927
13928         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13929                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13930
13931         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13932
13933         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13934             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13935             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13936                 goto out;
13937
13938         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13939                 /* DMA read watermark not used on PCIE */
13940                 tp->dma_rwctrl |= 0x00180000;
13941         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
13942                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13943                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
13944                         tp->dma_rwctrl |= 0x003f0000;
13945                 else
13946                         tp->dma_rwctrl |= 0x003f000f;
13947         } else {
13948                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13949                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13950                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
13951                         u32 read_water = 0x7;
13952
13953                         /* If the 5704 is behind the EPB bridge, we can
13954                          * do the less restrictive ONE_DMA workaround for
13955                          * better performance.
13956                          */
13957                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13958                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13959                                 tp->dma_rwctrl |= 0x8000;
13960                         else if (ccval == 0x6 || ccval == 0x7)
13961                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13962
13963                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13964                                 read_water = 4;
13965                         /* Set bit 23 to enable PCIX hw bug fix */
13966                         tp->dma_rwctrl |=
13967                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13968                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13969                                 (1 << 23);
13970                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13971                         /* 5780 always in PCIX mode */
13972                         tp->dma_rwctrl |= 0x00144000;
13973                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13974                         /* 5714 always in PCIX mode */
13975                         tp->dma_rwctrl |= 0x00148000;
13976                 } else {
13977                         tp->dma_rwctrl |= 0x001b000f;
13978                 }
13979         }
13980
13981         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13982             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13983                 tp->dma_rwctrl &= 0xfffffff0;
13984
13985         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13986             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13987                 /* Remove this if it causes problems for some boards. */
13988                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13989
13990                 /* On 5700/5701 chips, we need to set this bit.
13991                  * Otherwise the chip will issue cacheline transactions
13992                  * to streamable DMA memory with not all the byte
13993                  * enables turned on.  This is an error on several
13994                  * RISC PCI controllers, in particular sparc64.
13995                  *
13996                  * On 5703/5704 chips, this bit has been reassigned
13997                  * a different meaning.  In particular, it is used
13998                  * on those chips to enable a PCI-X workaround.
13999                  */
14000                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
14001         }
14002
14003         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14004
14005 #if 0
14006         /* Unneeded, already done by tg3_get_invariants.  */
14007         tg3_switch_clocks(tp);
14008 #endif
14009
14010         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14011             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14012                 goto out;
14013
14014         /* It is best to perform DMA test with maximum write burst size
14015          * to expose the 5700/5701 write DMA bug.
14016          */
14017         saved_dma_rwctrl = tp->dma_rwctrl;
14018         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14019         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14020
14021         while (1) {
14022                 u32 *p = buf, i;
14023
14024                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14025                         p[i] = i;
14026
14027                 /* Send the buffer to the chip. */
14028                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14029                 if (ret) {
14030                         dev_err(&tp->pdev->dev,
14031                                 "%s: Buffer write failed. err = %d\n",
14032                                 __func__, ret);
14033                         break;
14034                 }
14035
14036 #if 0
14037                 /* validate data reached card RAM correctly. */
14038                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14039                         u32 val;
14040                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
14041                         if (le32_to_cpu(val) != p[i]) {
14042                                 dev_err(&tp->pdev->dev,
14043                                         "%s: Buffer corrupted on device! "
14044                                         "(%d != %d)\n", __func__, val, i);
14045                                 /* ret = -ENODEV here? */
14046                         }
14047                         p[i] = 0;
14048                 }
14049 #endif
14050                 /* Now read it back. */
14051                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14052                 if (ret) {
14053                         dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
14054                                 "err = %d\n", __func__, ret);
14055                         break;
14056                 }
14057
14058                 /* Verify it. */
14059                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14060                         if (p[i] == i)
14061                                 continue;
14062
14063                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14064                             DMA_RWCTRL_WRITE_BNDRY_16) {
14065                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14066                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14067                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14068                                 break;
14069                         } else {
14070                                 dev_err(&tp->pdev->dev,
14071                                         "%s: Buffer corrupted on read back! "
14072                                         "(%d != %d)\n", __func__, p[i], i);
14073                                 ret = -ENODEV;
14074                                 goto out;
14075                         }
14076                 }
14077
14078                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14079                         /* Success. */
14080                         ret = 0;
14081                         break;
14082                 }
14083         }
14084         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14085             DMA_RWCTRL_WRITE_BNDRY_16) {
14086                 static struct pci_device_id dma_wait_state_chipsets[] = {
14087                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14088                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14089                         { },
14090                 };
14091
14092                 /* DMA test passed without adjusting DMA boundary,
14093                  * now look for chipsets that are known to expose the
14094                  * DMA bug without failing the test.
14095                  */
14096                 if (pci_dev_present(dma_wait_state_chipsets)) {
14097                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14098                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14099                 } else {
14100                         /* Safe to use the calculated DMA boundary. */
14101                         tp->dma_rwctrl = saved_dma_rwctrl;
14102                 }
14103
14104                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14105         }
14106
14107 out:
14108         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14109 out_nofree:
14110         return ret;
14111 }
14112
14113 static void __devinit tg3_init_link_config(struct tg3 *tp)
14114 {
14115         tp->link_config.advertising =
14116                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14117                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14118                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14119                  ADVERTISED_Autoneg | ADVERTISED_MII);
14120         tp->link_config.speed = SPEED_INVALID;
14121         tp->link_config.duplex = DUPLEX_INVALID;
14122         tp->link_config.autoneg = AUTONEG_ENABLE;
14123         tp->link_config.active_speed = SPEED_INVALID;
14124         tp->link_config.active_duplex = DUPLEX_INVALID;
14125         tp->link_config.phy_is_low_power = 0;
14126         tp->link_config.orig_speed = SPEED_INVALID;
14127         tp->link_config.orig_duplex = DUPLEX_INVALID;
14128         tp->link_config.orig_autoneg = AUTONEG_INVALID;
14129 }
14130
14131 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14132 {
14133         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14134             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
14135             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
14136                 tp->bufmgr_config.mbuf_read_dma_low_water =
14137                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14138                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14139                         DEFAULT_MB_MACRX_LOW_WATER_57765;
14140                 tp->bufmgr_config.mbuf_high_water =
14141                         DEFAULT_MB_HIGH_WATER_57765;
14142
14143                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14144                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14145                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14146                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14147                 tp->bufmgr_config.mbuf_high_water_jumbo =
14148                         DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14149         } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14150                 tp->bufmgr_config.mbuf_read_dma_low_water =
14151                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14152                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14153                         DEFAULT_MB_MACRX_LOW_WATER_5705;
14154                 tp->bufmgr_config.mbuf_high_water =
14155                         DEFAULT_MB_HIGH_WATER_5705;
14156                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14157                         tp->bufmgr_config.mbuf_mac_rx_low_water =
14158                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
14159                         tp->bufmgr_config.mbuf_high_water =
14160                                 DEFAULT_MB_HIGH_WATER_5906;
14161                 }
14162
14163                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14164                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14165                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14166                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14167                 tp->bufmgr_config.mbuf_high_water_jumbo =
14168                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14169         } else {
14170                 tp->bufmgr_config.mbuf_read_dma_low_water =
14171                         DEFAULT_MB_RDMA_LOW_WATER;
14172                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14173                         DEFAULT_MB_MACRX_LOW_WATER;
14174                 tp->bufmgr_config.mbuf_high_water =
14175                         DEFAULT_MB_HIGH_WATER;
14176
14177                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14178                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14179                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14180                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14181                 tp->bufmgr_config.mbuf_high_water_jumbo =
14182                         DEFAULT_MB_HIGH_WATER_JUMBO;
14183         }
14184
14185         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14186         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14187 }
14188
14189 static char * __devinit tg3_phy_string(struct tg3 *tp)
14190 {
14191         switch (tp->phy_id & TG3_PHY_ID_MASK) {
14192         case TG3_PHY_ID_BCM5400:        return "5400";
14193         case TG3_PHY_ID_BCM5401:        return "5401";
14194         case TG3_PHY_ID_BCM5411:        return "5411";
14195         case TG3_PHY_ID_BCM5701:        return "5701";
14196         case TG3_PHY_ID_BCM5703:        return "5703";
14197         case TG3_PHY_ID_BCM5704:        return "5704";
14198         case TG3_PHY_ID_BCM5705:        return "5705";
14199         case TG3_PHY_ID_BCM5750:        return "5750";
14200         case TG3_PHY_ID_BCM5752:        return "5752";
14201         case TG3_PHY_ID_BCM5714:        return "5714";
14202         case TG3_PHY_ID_BCM5780:        return "5780";
14203         case TG3_PHY_ID_BCM5755:        return "5755";
14204         case TG3_PHY_ID_BCM5787:        return "5787";
14205         case TG3_PHY_ID_BCM5784:        return "5784";
14206         case TG3_PHY_ID_BCM5756:        return "5722/5756";
14207         case TG3_PHY_ID_BCM5906:        return "5906";
14208         case TG3_PHY_ID_BCM5761:        return "5761";
14209         case TG3_PHY_ID_BCM5718C:       return "5718C";
14210         case TG3_PHY_ID_BCM5718S:       return "5718S";
14211         case TG3_PHY_ID_BCM57765:       return "57765";
14212         case TG3_PHY_ID_BCM5719C:       return "5719C";
14213         case TG3_PHY_ID_BCM8002:        return "8002/serdes";
14214         case 0:                 return "serdes";
14215         default:                return "unknown";
14216         }
14217 }
14218
14219 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14220 {
14221         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14222                 strcpy(str, "PCI Express");
14223                 return str;
14224         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14225                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14226
14227                 strcpy(str, "PCIX:");
14228
14229                 if ((clock_ctrl == 7) ||
14230                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14231                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14232                         strcat(str, "133MHz");
14233                 else if (clock_ctrl == 0)
14234                         strcat(str, "33MHz");
14235                 else if (clock_ctrl == 2)
14236                         strcat(str, "50MHz");
14237                 else if (clock_ctrl == 4)
14238                         strcat(str, "66MHz");
14239                 else if (clock_ctrl == 6)
14240                         strcat(str, "100MHz");
14241         } else {
14242                 strcpy(str, "PCI:");
14243                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14244                         strcat(str, "66MHz");
14245                 else
14246                         strcat(str, "33MHz");
14247         }
14248         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14249                 strcat(str, ":32-bit");
14250         else
14251                 strcat(str, ":64-bit");
14252         return str;
14253 }
14254
14255 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14256 {
14257         struct pci_dev *peer;
14258         unsigned int func, devnr = tp->pdev->devfn & ~7;
14259
14260         for (func = 0; func < 8; func++) {
14261                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14262                 if (peer && peer != tp->pdev)
14263                         break;
14264                 pci_dev_put(peer);
14265         }
14266         /* 5704 can be configured in single-port mode, set peer to
14267          * tp->pdev in that case.
14268          */
14269         if (!peer) {
14270                 peer = tp->pdev;
14271                 return peer;
14272         }
14273
14274         /*
14275          * We don't need to keep the refcount elevated; there's no way
14276          * to remove one half of this device without removing the other
14277          */
14278         pci_dev_put(peer);
14279
14280         return peer;
14281 }
14282
14283 static void __devinit tg3_init_coal(struct tg3 *tp)
14284 {
14285         struct ethtool_coalesce *ec = &tp->coal;
14286
14287         memset(ec, 0, sizeof(*ec));
14288         ec->cmd = ETHTOOL_GCOALESCE;
14289         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14290         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14291         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14292         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14293         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14294         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14295         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14296         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14297         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14298
14299         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14300                                  HOSTCC_MODE_CLRTICK_TXBD)) {
14301                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14302                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14303                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14304                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14305         }
14306
14307         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14308                 ec->rx_coalesce_usecs_irq = 0;
14309                 ec->tx_coalesce_usecs_irq = 0;
14310                 ec->stats_block_coalesce_usecs = 0;
14311         }
14312 }
14313
14314 static const struct net_device_ops tg3_netdev_ops = {
14315         .ndo_open               = tg3_open,
14316         .ndo_stop               = tg3_close,
14317         .ndo_start_xmit         = tg3_start_xmit,
14318         .ndo_get_stats64        = tg3_get_stats64,
14319         .ndo_validate_addr      = eth_validate_addr,
14320         .ndo_set_multicast_list = tg3_set_rx_mode,
14321         .ndo_set_mac_address    = tg3_set_mac_addr,
14322         .ndo_do_ioctl           = tg3_ioctl,
14323         .ndo_tx_timeout         = tg3_tx_timeout,
14324         .ndo_change_mtu         = tg3_change_mtu,
14325 #if TG3_VLAN_TAG_USED
14326         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14327 #endif
14328 #ifdef CONFIG_NET_POLL_CONTROLLER
14329         .ndo_poll_controller    = tg3_poll_controller,
14330 #endif
14331 };
14332
14333 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14334         .ndo_open               = tg3_open,
14335         .ndo_stop               = tg3_close,
14336         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
14337         .ndo_get_stats64        = tg3_get_stats64,
14338         .ndo_validate_addr      = eth_validate_addr,
14339         .ndo_set_multicast_list = tg3_set_rx_mode,
14340         .ndo_set_mac_address    = tg3_set_mac_addr,
14341         .ndo_do_ioctl           = tg3_ioctl,
14342         .ndo_tx_timeout         = tg3_tx_timeout,
14343         .ndo_change_mtu         = tg3_change_mtu,
14344 #if TG3_VLAN_TAG_USED
14345         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14346 #endif
14347 #ifdef CONFIG_NET_POLL_CONTROLLER
14348         .ndo_poll_controller    = tg3_poll_controller,
14349 #endif
14350 };
14351
14352 static int __devinit tg3_init_one(struct pci_dev *pdev,
14353                                   const struct pci_device_id *ent)
14354 {
14355         struct net_device *dev;
14356         struct tg3 *tp;
14357         int i, err, pm_cap;
14358         u32 sndmbx, rcvmbx, intmbx;
14359         char str[40];
14360         u64 dma_mask, persist_dma_mask;
14361
14362         printk_once(KERN_INFO "%s\n", version);
14363
14364         err = pci_enable_device(pdev);
14365         if (err) {
14366                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
14367                 return err;
14368         }
14369
14370         err = pci_request_regions(pdev, DRV_MODULE_NAME);
14371         if (err) {
14372                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
14373                 goto err_out_disable_pdev;
14374         }
14375
14376         pci_set_master(pdev);
14377
14378         /* Find power-management capability. */
14379         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14380         if (pm_cap == 0) {
14381                 dev_err(&pdev->dev,
14382                         "Cannot find Power Management capability, aborting\n");
14383                 err = -EIO;
14384                 goto err_out_free_res;
14385         }
14386
14387         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14388         if (!dev) {
14389                 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
14390                 err = -ENOMEM;
14391                 goto err_out_free_res;
14392         }
14393
14394         SET_NETDEV_DEV(dev, &pdev->dev);
14395
14396 #if TG3_VLAN_TAG_USED
14397         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14398 #endif
14399
14400         tp = netdev_priv(dev);
14401         tp->pdev = pdev;
14402         tp->dev = dev;
14403         tp->pm_cap = pm_cap;
14404         tp->rx_mode = TG3_DEF_RX_MODE;
14405         tp->tx_mode = TG3_DEF_TX_MODE;
14406
14407         if (tg3_debug > 0)
14408                 tp->msg_enable = tg3_debug;
14409         else
14410                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14411
14412         /* The word/byte swap controls here control register access byte
14413          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
14414          * setting below.
14415          */
14416         tp->misc_host_ctrl =
14417                 MISC_HOST_CTRL_MASK_PCI_INT |
14418                 MISC_HOST_CTRL_WORD_SWAP |
14419                 MISC_HOST_CTRL_INDIR_ACCESS |
14420                 MISC_HOST_CTRL_PCISTATE_RW;
14421
14422         /* The NONFRM (non-frame) byte/word swap controls take effect
14423          * on descriptor entries, anything which isn't packet data.
14424          *
14425          * The StrongARM chips on the board (one for tx, one for rx)
14426          * are running in big-endian mode.
14427          */
14428         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14429                         GRC_MODE_WSWAP_NONFRM_DATA);
14430 #ifdef __BIG_ENDIAN
14431         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14432 #endif
14433         spin_lock_init(&tp->lock);
14434         spin_lock_init(&tp->indirect_lock);
14435         INIT_WORK(&tp->reset_task, tg3_reset_task);
14436
14437         tp->regs = pci_ioremap_bar(pdev, BAR_0);
14438         if (!tp->regs) {
14439                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
14440                 err = -ENOMEM;
14441                 goto err_out_free_dev;
14442         }
14443
14444         tg3_init_link_config(tp);
14445
14446         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14447         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14448
14449         dev->ethtool_ops = &tg3_ethtool_ops;
14450         dev->watchdog_timeo = TG3_TX_TIMEOUT;
14451         dev->irq = pdev->irq;
14452
14453         err = tg3_get_invariants(tp);
14454         if (err) {
14455                 dev_err(&pdev->dev,
14456                         "Problem fetching invariants of chip, aborting\n");
14457                 goto err_out_iounmap;
14458         }
14459
14460         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14461             tp->pci_chip_rev_id != CHIPREV_ID_5717_A0 &&
14462             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
14463                 dev->netdev_ops = &tg3_netdev_ops;
14464         else
14465                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14466
14467
14468         /* The EPB bridge inside 5714, 5715, and 5780 and any
14469          * device behind the EPB cannot support DMA addresses > 40-bit.
14470          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14471          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14472          * do DMA address check in tg3_start_xmit().
14473          */
14474         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14475                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14476         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14477                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14478 #ifdef CONFIG_HIGHMEM
14479                 dma_mask = DMA_BIT_MASK(64);
14480 #endif
14481         } else
14482                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14483
14484         /* Configure DMA attributes. */
14485         if (dma_mask > DMA_BIT_MASK(32)) {
14486                 err = pci_set_dma_mask(pdev, dma_mask);
14487                 if (!err) {
14488                         dev->features |= NETIF_F_HIGHDMA;
14489                         err = pci_set_consistent_dma_mask(pdev,
14490                                                           persist_dma_mask);
14491                         if (err < 0) {
14492                                 dev_err(&pdev->dev, "Unable to obtain 64 bit "
14493                                         "DMA for consistent allocations\n");
14494                                 goto err_out_iounmap;
14495                         }
14496                 }
14497         }
14498         if (err || dma_mask == DMA_BIT_MASK(32)) {
14499                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14500                 if (err) {
14501                         dev_err(&pdev->dev,
14502                                 "No usable DMA configuration, aborting\n");
14503                         goto err_out_iounmap;
14504                 }
14505         }
14506
14507         tg3_init_bufmgr_config(tp);
14508
14509         /* Selectively allow TSO based on operating conditions */
14510         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14511             (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14512                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14513         else {
14514                 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14515                 tp->fw_needed = NULL;
14516         }
14517
14518         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14519                 tp->fw_needed = FIRMWARE_TG3;
14520
14521         /* TSO is on by default on chips that support hardware TSO.
14522          * Firmware TSO on older chips gives lower performance, so it
14523          * is off by default, but can be enabled using ethtool.
14524          */
14525         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14526             (dev->features & NETIF_F_IP_CSUM)) {
14527                 dev->features |= NETIF_F_TSO;
14528                 vlan_features_add(dev, NETIF_F_TSO);
14529         }
14530         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14531             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14532                 if (dev->features & NETIF_F_IPV6_CSUM) {
14533                         dev->features |= NETIF_F_TSO6;
14534                         vlan_features_add(dev, NETIF_F_TSO6);
14535                 }
14536                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14537                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14538                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14539                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14540                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14541                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
14542                         dev->features |= NETIF_F_TSO_ECN;
14543                         vlan_features_add(dev, NETIF_F_TSO_ECN);
14544                 }
14545         }
14546
14547         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14548             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14549             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14550                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14551                 tp->rx_pending = 63;
14552         }
14553
14554         err = tg3_get_device_address(tp);
14555         if (err) {
14556                 dev_err(&pdev->dev,
14557                         "Could not obtain valid ethernet address, aborting\n");
14558                 goto err_out_iounmap;
14559         }
14560
14561         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14562                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14563                 if (!tp->aperegs) {
14564                         dev_err(&pdev->dev,
14565                                 "Cannot map APE registers, aborting\n");
14566                         err = -ENOMEM;
14567                         goto err_out_iounmap;
14568                 }
14569
14570                 tg3_ape_lock_init(tp);
14571
14572                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14573                         tg3_read_dash_ver(tp);
14574         }
14575
14576         /*
14577          * Reset chip in case UNDI or EFI driver did not shutdown
14578          * DMA self test will enable WDMAC and we'll see (spurious)
14579          * pending DMA on the PCI bus at that point.
14580          */
14581         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14582             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14583                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14584                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14585         }
14586
14587         err = tg3_test_dma(tp);
14588         if (err) {
14589                 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
14590                 goto err_out_apeunmap;
14591         }
14592
14593         /* flow control autonegotiation is default behavior */
14594         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14595         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14596
14597         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14598         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14599         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14600         for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14601                 struct tg3_napi *tnapi = &tp->napi[i];
14602
14603                 tnapi->tp = tp;
14604                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14605
14606                 tnapi->int_mbox = intmbx;
14607                 if (i < 4)
14608                         intmbx += 0x8;
14609                 else
14610                         intmbx += 0x4;
14611
14612                 tnapi->consmbox = rcvmbx;
14613                 tnapi->prodmbox = sndmbx;
14614
14615                 if (i) {
14616                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14617                         netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14618                 } else {
14619                         tnapi->coal_now = HOSTCC_MODE_NOW;
14620                         netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14621                 }
14622
14623                 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14624                         break;
14625
14626                 /*
14627                  * If we support MSIX, we'll be using RSS.  If we're using
14628                  * RSS, the first vector only handles link interrupts and the
14629                  * remaining vectors handle rx and tx interrupts.  Reuse the
14630                  * mailbox values for the next iteration.  The values we setup
14631                  * above are still useful for the single vectored mode.
14632                  */
14633                 if (!i)
14634                         continue;
14635
14636                 rcvmbx += 0x8;
14637
14638                 if (sndmbx & 0x4)
14639                         sndmbx -= 0x4;
14640                 else
14641                         sndmbx += 0xc;
14642         }
14643
14644         tg3_init_coal(tp);
14645
14646         pci_set_drvdata(pdev, dev);
14647
14648         err = register_netdev(dev);
14649         if (err) {
14650                 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
14651                 goto err_out_apeunmap;
14652         }
14653
14654         netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14655                     tp->board_part_number,
14656                     tp->pci_chip_rev_id,
14657                     tg3_bus_string(tp, str),
14658                     dev->dev_addr);
14659
14660         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14661                 struct phy_device *phydev;
14662                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14663                 netdev_info(dev,
14664                             "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14665                             phydev->drv->name, dev_name(&phydev->dev));
14666         } else
14667                 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
14668                             "(WireSpeed[%d])\n", tg3_phy_string(tp),
14669                             ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14670                              ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14671                               "10/100/1000Base-T")),
14672                             (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14673
14674         netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14675                     (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14676                     (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14677                     (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14678                     (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14679                     (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14680         netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14681                     tp->dma_rwctrl,
14682                     pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
14683                     ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
14684
14685         return 0;
14686
14687 err_out_apeunmap:
14688         if (tp->aperegs) {
14689                 iounmap(tp->aperegs);
14690                 tp->aperegs = NULL;
14691         }
14692
14693 err_out_iounmap:
14694         if (tp->regs) {
14695                 iounmap(tp->regs);
14696                 tp->regs = NULL;
14697         }
14698
14699 err_out_free_dev:
14700         free_netdev(dev);
14701
14702 err_out_free_res:
14703         pci_release_regions(pdev);
14704
14705 err_out_disable_pdev:
14706         pci_disable_device(pdev);
14707         pci_set_drvdata(pdev, NULL);
14708         return err;
14709 }
14710
14711 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14712 {
14713         struct net_device *dev = pci_get_drvdata(pdev);
14714
14715         if (dev) {
14716                 struct tg3 *tp = netdev_priv(dev);
14717
14718                 if (tp->fw)
14719                         release_firmware(tp->fw);
14720
14721                 flush_scheduled_work();
14722
14723                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14724                         tg3_phy_fini(tp);
14725                         tg3_mdio_fini(tp);
14726                 }
14727
14728                 unregister_netdev(dev);
14729                 if (tp->aperegs) {
14730                         iounmap(tp->aperegs);
14731                         tp->aperegs = NULL;
14732                 }
14733                 if (tp->regs) {
14734                         iounmap(tp->regs);
14735                         tp->regs = NULL;
14736                 }
14737                 free_netdev(dev);
14738                 pci_release_regions(pdev);
14739                 pci_disable_device(pdev);
14740                 pci_set_drvdata(pdev, NULL);
14741         }
14742 }
14743
14744 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14745 {
14746         struct net_device *dev = pci_get_drvdata(pdev);
14747         struct tg3 *tp = netdev_priv(dev);
14748         pci_power_t target_state;
14749         int err;
14750
14751         /* PCI register 4 needs to be saved whether netif_running() or not.
14752          * MSI address and data need to be saved if using MSI and
14753          * netif_running().
14754          */
14755         pci_save_state(pdev);
14756
14757         if (!netif_running(dev))
14758                 return 0;
14759
14760         flush_scheduled_work();
14761         tg3_phy_stop(tp);
14762         tg3_netif_stop(tp);
14763
14764         del_timer_sync(&tp->timer);
14765
14766         tg3_full_lock(tp, 1);
14767         tg3_disable_ints(tp);
14768         tg3_full_unlock(tp);
14769
14770         netif_device_detach(dev);
14771
14772         tg3_full_lock(tp, 0);
14773         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14774         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14775         tg3_full_unlock(tp);
14776
14777         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14778
14779         err = tg3_set_power_state(tp, target_state);
14780         if (err) {
14781                 int err2;
14782
14783                 tg3_full_lock(tp, 0);
14784
14785                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14786                 err2 = tg3_restart_hw(tp, 1);
14787                 if (err2)
14788                         goto out;
14789
14790                 tp->timer.expires = jiffies + tp->timer_offset;
14791                 add_timer(&tp->timer);
14792
14793                 netif_device_attach(dev);
14794                 tg3_netif_start(tp);
14795
14796 out:
14797                 tg3_full_unlock(tp);
14798
14799                 if (!err2)
14800                         tg3_phy_start(tp);
14801         }
14802
14803         return err;
14804 }
14805
14806 static int tg3_resume(struct pci_dev *pdev)
14807 {
14808         struct net_device *dev = pci_get_drvdata(pdev);
14809         struct tg3 *tp = netdev_priv(dev);
14810         int err;
14811
14812         pci_restore_state(tp->pdev);
14813
14814         if (!netif_running(dev))
14815                 return 0;
14816
14817         err = tg3_set_power_state(tp, PCI_D0);
14818         if (err)
14819                 return err;
14820
14821         netif_device_attach(dev);
14822
14823         tg3_full_lock(tp, 0);
14824
14825         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14826         err = tg3_restart_hw(tp, 1);
14827         if (err)
14828                 goto out;
14829
14830         tp->timer.expires = jiffies + tp->timer_offset;
14831         add_timer(&tp->timer);
14832
14833         tg3_netif_start(tp);
14834
14835 out:
14836         tg3_full_unlock(tp);
14837
14838         if (!err)
14839                 tg3_phy_start(tp);
14840
14841         return err;
14842 }
14843
14844 static struct pci_driver tg3_driver = {
14845         .name           = DRV_MODULE_NAME,
14846         .id_table       = tg3_pci_tbl,
14847         .probe          = tg3_init_one,
14848         .remove         = __devexit_p(tg3_remove_one),
14849         .suspend        = tg3_suspend,
14850         .resume         = tg3_resume
14851 };
14852
14853 static int __init tg3_init(void)
14854 {
14855         return pci_register_driver(&tg3_driver);
14856 }
14857
14858 static void __exit tg3_cleanup(void)
14859 {
14860         pci_unregister_driver(&tg3_driver);
14861 }
14862
14863 module_init(tg3_init);
14864 module_exit(tg3_cleanup);