drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2010 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/stringify.h>
  22 #include <linux/kernel.h>
  23 #include <linux/types.h>
  24 #include <linux/compiler.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/in.h>
  28 #include <linux/init.h>
  29 #include <linux/ioport.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/ethtool.h>
  35 #include <linux/mii.h>
  36 #include <linux/phy.h>
  37 #include <linux/brcmphy.h>
  38 #include <linux/if_vlan.h>
  39 #include <linux/ip.h>
  40 #include <linux/tcp.h>
  41 #include <linux/workqueue.h>
  42 #include <linux/prefetch.h>
  43 #include <linux/dma-mapping.h>
  44 #include <linux/firmware.h>
  45
  46 #include <net/checksum.h>
  47 #include <net/ip.h>
  48
  49 #include <asm/system.h>
  50 #include <asm/io.h>
  51 #include <asm/byteorder.h>
  52 #include <asm/uaccess.h>
  53
  54 #ifdef CONFIG_SPARC
  55 #include <asm/idprom.h>
  56 #include <asm/prom.h>
  57 #endif
  58
  59 #define BAR_0   0
  60 #define BAR_2   2
  61
  62 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  63 #define TG3_VLAN_TAG_USED 1
  64 #else
  65 #define TG3_VLAN_TAG_USED 0
  66 #endif
  67
  68 #include "tg3.h"
  69
  70 #define DRV_MODULE_NAME         "tg3"
  71 #define TG3_MAJ_NUM                     3
  72 #define TG3_MIN_NUM                     114
  73 #define DRV_MODULE_VERSION      \
  74         __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
  75 #define DRV_MODULE_RELDATE      "September 30, 2010"
  76
  77 #define TG3_DEF_MAC_MODE        0
  78 #define TG3_DEF_RX_MODE         0
  79 #define TG3_DEF_TX_MODE         0
  80 #define TG3_DEF_MSG_ENABLE        \
  81         (NETIF_MSG_DRV          | \
  82          NETIF_MSG_PROBE        | \
  83          NETIF_MSG_LINK         | \
  84          NETIF_MSG_TIMER        | \
  85          NETIF_MSG_IFDOWN       | \
  86          NETIF_MSG_IFUP         | \
  87          NETIF_MSG_RX_ERR       | \
  88          NETIF_MSG_TX_ERR)
  89
  90 /* length of time before we decide the hardware is borked,
  91  * and dev->tx_timeout() should be called to fix the problem
  92  */
  93 #define TG3_TX_TIMEOUT                  (5 * HZ)
  94
  95 /* hardware minimum and maximum for a single frame's data payload */
  96 #define TG3_MIN_MTU                     60
  97 #define TG3_MAX_MTU(tp) \
  98         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  99
 100 /* These numbers seem to be hard coded in the NIC firmware somehow.
 101  * You can't change the ring sizes, but you can change where you place
 102  * them in the NIC onboard memory.
 103  */
 104 #define TG3_RX_STD_RING_SIZE(tp) \
 105         ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \
 106           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \
 107          RX_STD_MAX_SIZE_5717 : 512)
 108 #define TG3_DEF_RX_RING_PENDING         200
 109 #define TG3_RX_JMB_RING_SIZE(tp) \
 110         ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \
 111           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \
 112          1024 : 256)
 113 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 114 #define TG3_RSS_INDIR_TBL_SIZE          128
 115
 116 /* Do not place this n-ring entries value into the tp struct itself,
 117  * we really want to expose these constants to GCC so that modulo et
 118  * al.  operations are done with shifts and masks instead of with
 119  * hw multiply/modulo instructions.  Another solution would be to
 120  * replace things like '% foo' with '& (foo - 1)'.
 121  */
 122
 123 #define TG3_TX_RING_SIZE                512
 124 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 125
 126 #define TG3_RX_STD_RING_BYTES(tp) \
 127         (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
 128 #define TG3_RX_JMB_RING_BYTES(tp) \
 129         (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
 130 #define TG3_RX_RCB_RING_BYTES(tp) \
 131         (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
 132 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 133                                  TG3_TX_RING_SIZE)
 134 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 135
 136 #define TG3_RX_DMA_ALIGN                16
 137 #define TG3_RX_HEADROOM                 ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
 138
 139 #define TG3_DMA_BYTE_ENAB               64
 140
 141 #define TG3_RX_STD_DMA_SZ               1536
 142 #define TG3_RX_JMB_DMA_SZ               9046
 143
 144 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 145
 146 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 147 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 148
 149 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
 150         (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
 151
 152 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
 153         (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
 154
 155 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
 156  * that are at least dword aligned when used in PCIX mode.  The driver
 157  * works around this bug by double copying the packet.  This workaround
 158  * is built into the normal double copy length check for efficiency.
 159  *
 160  * However, the double copy is only necessary on those architectures
 161  * where unaligned memory accesses are inefficient.  For those architectures
 162  * where unaligned memory accesses incur little penalty, we can reintegrate
 163  * the 5701 in the normal rx path.  Doing so saves a device structure
 164  * dereference by hardcoding the double copy threshold in place.
 165  */
 166 #define TG3_RX_COPY_THRESHOLD           256
 167 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
 168         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
 169 #else
 170         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
 171 #endif
 172
 173 /* minimum number of free TX descriptors required to wake up TX process */
 174 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 175
 176 #define TG3_RAW_IP_ALIGN 2
 177
 178 /* number of ETHTOOL_GSTATS u64's */
 179 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 180
 181 #define TG3_NUM_TEST            6
 182
 183 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
 184
 185 #define FIRMWARE_TG3            "tigon/tg3.bin"
 186 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 187 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 188
 189 static char version[] __devinitdata =
 190         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
 191
 192 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 193 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 194 MODULE_LICENSE("GPL");
 195 MODULE_VERSION(DRV_MODULE_VERSION);
 196 MODULE_FIRMWARE(FIRMWARE_TG3);
 197 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 198 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 199
 200 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 201 module_param(tg3_debug, int, 0);
 202 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 203
 204 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 255         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 256         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 257         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 258         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 259         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 260         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 261         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 262         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 263         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 264         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 265         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 266         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 267         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 268         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
 269         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
 270         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
 271         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
 272         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
 273         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
 274         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
 275         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
 276         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
 277         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 278         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 279         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 280         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 281         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 282         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 283         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 284         {}
 285 };
 286
 287 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 288
 289 static const struct {
 290         const char string[ETH_GSTRING_LEN];
 291 } ethtool_stats_keys[TG3_NUM_STATS] = {
 292         { "rx_octets" },
 293         { "rx_fragments" },
 294         { "rx_ucast_packets" },
 295         { "rx_mcast_packets" },
 296         { "rx_bcast_packets" },
 297         { "rx_fcs_errors" },
 298         { "rx_align_errors" },
 299         { "rx_xon_pause_rcvd" },
 300         { "rx_xoff_pause_rcvd" },
 301         { "rx_mac_ctrl_rcvd" },
 302         { "rx_xoff_entered" },
 303         { "rx_frame_too_long_errors" },
 304         { "rx_jabbers" },
 305         { "rx_undersize_packets" },
 306         { "rx_in_length_errors" },
 307         { "rx_out_length_errors" },
 308         { "rx_64_or_less_octet_packets" },
 309         { "rx_65_to_127_octet_packets" },
 310         { "rx_128_to_255_octet_packets" },
 311         { "rx_256_to_511_octet_packets" },
 312         { "rx_512_to_1023_octet_packets" },
 313         { "rx_1024_to_1522_octet_packets" },
 314         { "rx_1523_to_2047_octet_packets" },
 315         { "rx_2048_to_4095_octet_packets" },
 316         { "rx_4096_to_8191_octet_packets" },
 317         { "rx_8192_to_9022_octet_packets" },
 318
 319         { "tx_octets" },
 320         { "tx_collisions" },
 321
 322         { "tx_xon_sent" },
 323         { "tx_xoff_sent" },
 324         { "tx_flow_control" },
 325         { "tx_mac_errors" },
 326         { "tx_single_collisions" },
 327         { "tx_mult_collisions" },
 328         { "tx_deferred" },
 329         { "tx_excessive_collisions" },
 330         { "tx_late_collisions" },
 331         { "tx_collide_2times" },
 332         { "tx_collide_3times" },
 333         { "tx_collide_4times" },
 334         { "tx_collide_5times" },
 335         { "tx_collide_6times" },
 336         { "tx_collide_7times" },
 337         { "tx_collide_8times" },
 338         { "tx_collide_9times" },
 339         { "tx_collide_10times" },
 340         { "tx_collide_11times" },
 341         { "tx_collide_12times" },
 342         { "tx_collide_13times" },
 343         { "tx_collide_14times" },
 344         { "tx_collide_15times" },
 345         { "tx_ucast_packets" },
 346         { "tx_mcast_packets" },
 347         { "tx_bcast_packets" },
 348         { "tx_carrier_sense_errors" },
 349         { "tx_discards" },
 350         { "tx_errors" },
 351
 352         { "dma_writeq_full" },
 353         { "dma_write_prioq_full" },
 354         { "rxbds_empty" },
 355         { "rx_discards" },
 356         { "rx_errors" },
 357         { "rx_threshold_hit" },
 358
 359         { "dma_readq_full" },
 360         { "dma_read_prioq_full" },
 361         { "tx_comp_queue_full" },
 362
 363         { "ring_set_send_prod_index" },
 364         { "ring_status_update" },
 365         { "nic_irqs" },
 366         { "nic_avoided_irqs" },
 367         { "nic_tx_threshold_hit" }
 368 };
 369
 370 static const struct {
 371         const char string[ETH_GSTRING_LEN];
 372 } ethtool_test_keys[TG3_NUM_TEST] = {
 373         { "nvram test     (online) " },
 374         { "link test      (online) " },
 375         { "register test  (offline)" },
 376         { "memory test    (offline)" },
 377         { "loopback test  (offline)" },
 378         { "interrupt test (offline)" },
 379 };
 380
 381 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 382 {
 383         writel(val, tp->regs + off);
 384 }
 385
 386 static u32 tg3_read32(struct tg3 *tp, u32 off)
 387 {
 388         return readl(tp->regs + off);
 389 }
 390
 391 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 392 {
 393         writel(val, tp->aperegs + off);
 394 }
 395
 396 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 397 {
 398         return readl(tp->aperegs + off);
 399 }
 400
 401 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 402 {
 403         unsigned long flags;
 404
 405         spin_lock_irqsave(&tp->indirect_lock, flags);
 406         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 407         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 408         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 409 }
 410
 411 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 412 {
 413         writel(val, tp->regs + off);
 414         readl(tp->regs + off);
 415 }
 416
 417 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 418 {
 419         unsigned long flags;
 420         u32 val;
 421
 422         spin_lock_irqsave(&tp->indirect_lock, flags);
 423         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 424         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 425         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 426         return val;
 427 }
 428
 429 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 430 {
 431         unsigned long flags;
 432
 433         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 434                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 435                                        TG3_64BIT_REG_LOW, val);
 436                 return;
 437         }
 438         if (off == TG3_RX_STD_PROD_IDX_REG) {
 439                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 440                                        TG3_64BIT_REG_LOW, val);
 441                 return;
 442         }
 443
 444         spin_lock_irqsave(&tp->indirect_lock, flags);
 445         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 446         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 447         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 448
 449         /* In indirect mode when disabling interrupts, we also need
 450          * to clear the interrupt bit in the GRC local ctrl register.
 451          */
 452         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 453             (val == 0x1)) {
 454                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 455                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 456         }
 457 }
 458
 459 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 460 {
 461         unsigned long flags;
 462         u32 val;
 463
 464         spin_lock_irqsave(&tp->indirect_lock, flags);
 465         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 466         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 467         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 468         return val;
 469 }
 470
 471 /* usec_wait specifies the wait time in usec when writing to certain registers
 472  * where it is unsafe to read back the register without some delay.
 473  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 474  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 475  */
 476 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 477 {
 478         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 479             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 480                 /* Non-posted methods */
 481                 tp->write32(tp, off, val);
 482         else {
 483                 /* Posted method */
 484                 tg3_write32(tp, off, val);
 485                 if (usec_wait)
 486                         udelay(usec_wait);
 487                 tp->read32(tp, off);
 488         }
 489         /* Wait again after the read for the posted method to guarantee that
 490          * the wait time is met.
 491          */
 492         if (usec_wait)
 493                 udelay(usec_wait);
 494 }
 495
 496 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 497 {
 498         tp->write32_mbox(tp, off, val);
 499         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 500             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 501                 tp->read32_mbox(tp, off);
 502 }
 503
 504 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 505 {
 506         void __iomem *mbox = tp->regs + off;
 507         writel(val, mbox);
 508         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 509                 writel(val, mbox);
 510         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 511                 readl(mbox);
 512 }
 513
 514 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 515 {
 516         return readl(tp->regs + off + GRCMBOX_BASE);
 517 }
 518
 519 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 520 {
 521         writel(val, tp->regs + off + GRCMBOX_BASE);
 522 }
 523
 524 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
 525 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 526 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
 527 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
 528 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
 529
 530 #define tw32(reg, val)                  tp->write32(tp, reg, val)
 531 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
 532 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
 533 #define tr32(reg)                       tp->read32(tp, reg)
 534
 535 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 536 {
 537         unsigned long flags;
 538
 539         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 540             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 541                 return;
 542
 543         spin_lock_irqsave(&tp->indirect_lock, flags);
 544         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 545                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 546                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 547
 548                 /* Always leave this as zero. */
 549                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 550         } else {
 551                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 552                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 553
 554                 /* Always leave this as zero. */
 555                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 556         }
 557         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 558 }
 559
 560 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 561 {
 562         unsigned long flags;
 563
 564         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 565             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 566                 *val = 0;
 567                 return;
 568         }
 569
 570         spin_lock_irqsave(&tp->indirect_lock, flags);
 571         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 572                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 573                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 574
 575                 /* Always leave this as zero. */
 576                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 577         } else {
 578                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 579                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 580
 581                 /* Always leave this as zero. */
 582                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 583         }
 584         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 585 }
 586
 587 static void tg3_ape_lock_init(struct tg3 *tp)
 588 {
 589         int i;
 590         u32 regbase;
 591
 592         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 593                 regbase = TG3_APE_LOCK_GRANT;
 594         else
 595                 regbase = TG3_APE_PER_LOCK_GRANT;
 596
 597         /* Make sure the driver hasn't any stale locks. */
 598         for (i = 0; i < 8; i++)
 599                 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
 600 }
 601
 602 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 603 {
 604         int i, off;
 605         int ret = 0;
 606         u32 status, req, gnt;
 607
 608         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 609                 return 0;
 610
 611         switch (locknum) {
 612         case TG3_APE_LOCK_GRC:
 613         case TG3_APE_LOCK_MEM:
 614                 break;
 615         default:
 616                 return -EINVAL;
 617         }
 618
 619         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
 620                 req = TG3_APE_LOCK_REQ;
 621                 gnt = TG3_APE_LOCK_GRANT;
 622         } else {
 623                 req = TG3_APE_PER_LOCK_REQ;
 624                 gnt = TG3_APE_PER_LOCK_GRANT;
 625         }
 626
 627         off = 4 * locknum;
 628
 629         tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
 630
 631         /* Wait for up to 1 millisecond to acquire lock. */
 632         for (i = 0; i < 100; i++) {
 633                 status = tg3_ape_read32(tp, gnt + off);
 634                 if (status == APE_LOCK_GRANT_DRIVER)
 635                         break;
 636                 udelay(10);
 637         }
 638
 639         if (status != APE_LOCK_GRANT_DRIVER) {
 640                 /* Revoke the lock request. */
 641                 tg3_ape_write32(tp, gnt + off,
 642                                 APE_LOCK_GRANT_DRIVER);
 643
 644                 ret = -EBUSY;
 645         }
 646
 647         return ret;
 648 }
 649
 650 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 651 {
 652         u32 gnt;
 653
 654         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 655                 return;
 656
 657         switch (locknum) {
 658         case TG3_APE_LOCK_GRC:
 659         case TG3_APE_LOCK_MEM:
 660                 break;
 661         default:
 662                 return;
 663         }
 664
 665         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 666                 gnt = TG3_APE_LOCK_GRANT;
 667         else
 668                 gnt = TG3_APE_PER_LOCK_GRANT;
 669
 670         tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
 671 }
 672
 673 static void tg3_disable_ints(struct tg3 *tp)
 674 {
 675         int i;
 676
 677         tw32(TG3PCI_MISC_HOST_CTRL,
 678              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 679         for (i = 0; i < tp->irq_max; i++)
 680                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 681 }
 682
 683 static void tg3_enable_ints(struct tg3 *tp)
 684 {
 685         int i;
 686
 687         tp->irq_sync = 0;
 688         wmb();
 689
 690         tw32(TG3PCI_MISC_HOST_CTRL,
 691              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 692
 693         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
 694         for (i = 0; i < tp->irq_cnt; i++) {
 695                 struct tg3_napi *tnapi = &tp->napi[i];
 696
 697                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 698                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 699                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 700
 701                 tp->coal_now |= tnapi->coal_now;
 702         }
 703
 704         /* Force an initial interrupt */
 705         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 706             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 707                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 708         else
 709                 tw32(HOSTCC_MODE, tp->coal_now);
 710
 711         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
 712 }
 713
 714 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 715 {
 716         struct tg3 *tp = tnapi->tp;
 717         struct tg3_hw_status *sblk = tnapi->hw_status;
 718         unsigned int work_exists = 0;
 719
 720         /* check for phy events */
 721         if (!(tp->tg3_flags &
 722               (TG3_FLAG_USE_LINKCHG_REG |
 723                TG3_FLAG_POLL_SERDES))) {
 724                 if (sblk->status & SD_STATUS_LINK_CHG)
 725                         work_exists = 1;
 726         }
 727         /* check for RX/TX work to do */
 728         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 729             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
 730                 work_exists = 1;
 731
 732         return work_exists;
 733 }
 734
 735 /* tg3_int_reenable
 736  *  similar to tg3_enable_ints, but it accurately determines whether there
 737  *  is new work pending and can return without flushing the PIO write
 738  *  which reenables interrupts
 739  */
 740 static void tg3_int_reenable(struct tg3_napi *tnapi)
 741 {
 742         struct tg3 *tp = tnapi->tp;
 743
 744         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 745         mmiowb();
 746
 747         /* When doing tagged status, this work check is unnecessary.
 748          * The last_tag we write above tells the chip which piece of
 749          * work we've completed.
 750          */
 751         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 752             tg3_has_work(tnapi))
 753                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 754                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 755 }
 756
 757 static void tg3_switch_clocks(struct tg3 *tp)
 758 {
 759         u32 clock_ctrl;
 760         u32 orig_clock_ctrl;
 761
 762         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 763             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 764                 return;
 765
 766         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 767
 768         orig_clock_ctrl = clock_ctrl;
 769         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 770                        CLOCK_CTRL_CLKRUN_OENABLE |
 771                        0x1f);
 772         tp->pci_clock_ctrl = clock_ctrl;
 773
 774         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 775                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 776                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 777                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 778                 }
 779         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 780                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 781                             clock_ctrl |
 782                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 783                             40);
 784                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 785                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 786                             40);
 787         }
 788         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 789 }
 790
 791 #define PHY_BUSY_LOOPS  5000
 792
 793 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 794 {
 795         u32 frame_val;
 796         unsigned int loops;
 797         int ret;
 798
 799         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 800                 tw32_f(MAC_MI_MODE,
 801                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 802                 udelay(80);
 803         }
 804
 805         *val = 0x0;
 806
 807         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 808                       MI_COM_PHY_ADDR_MASK);
 809         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 810                       MI_COM_REG_ADDR_MASK);
 811         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 812
 813         tw32_f(MAC_MI_COM, frame_val);
 814
 815         loops = PHY_BUSY_LOOPS;
 816         while (loops != 0) {
 817                 udelay(10);
 818                 frame_val = tr32(MAC_MI_COM);
 819
 820                 if ((frame_val & MI_COM_BUSY) == 0) {
 821                         udelay(5);
 822                         frame_val = tr32(MAC_MI_COM);
 823                         break;
 824                 }
 825                 loops -= 1;
 826         }
 827
 828         ret = -EBUSY;
 829         if (loops != 0) {
 830                 *val = frame_val & MI_COM_DATA_MASK;
 831                 ret = 0;
 832         }
 833
 834         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 835                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 836                 udelay(80);
 837         }
 838
 839         return ret;
 840 }
 841
 842 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 843 {
 844         u32 frame_val;
 845         unsigned int loops;
 846         int ret;
 847
 848         if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
 849             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 850                 return 0;
 851
 852         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 853                 tw32_f(MAC_MI_MODE,
 854                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 855                 udelay(80);
 856         }
 857
 858         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 859                       MI_COM_PHY_ADDR_MASK);
 860         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 861                       MI_COM_REG_ADDR_MASK);
 862         frame_val |= (val & MI_COM_DATA_MASK);
 863         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 864
 865         tw32_f(MAC_MI_COM, frame_val);
 866
 867         loops = PHY_BUSY_LOOPS;
 868         while (loops != 0) {
 869                 udelay(10);
 870                 frame_val = tr32(MAC_MI_COM);
 871                 if ((frame_val & MI_COM_BUSY) == 0) {
 872                         udelay(5);
 873                         frame_val = tr32(MAC_MI_COM);
 874                         break;
 875                 }
 876                 loops -= 1;
 877         }
 878
 879         ret = -EBUSY;
 880         if (loops != 0)
 881                 ret = 0;
 882
 883         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 884                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 885                 udelay(80);
 886         }
 887
 888         return ret;
 889 }
 890
 891 static int tg3_bmcr_reset(struct tg3 *tp)
 892 {
 893         u32 phy_control;
 894         int limit, err;
 895
 896         /* OK, reset it, and poll the BMCR_RESET bit until it
 897          * clears or we time out.
 898          */
 899         phy_control = BMCR_RESET;
 900         err = tg3_writephy(tp, MII_BMCR, phy_control);
 901         if (err != 0)
 902                 return -EBUSY;
 903
 904         limit = 5000;
 905         while (limit--) {
 906                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 907                 if (err != 0)
 908                         return -EBUSY;
 909
 910                 if ((phy_control & BMCR_RESET) == 0) {
 911                         udelay(40);
 912                         break;
 913                 }
 914                 udelay(10);
 915         }
 916         if (limit < 0)
 917                 return -EBUSY;
 918
 919         return 0;
 920 }
 921
 922 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 923 {
 924         struct tg3 *tp = bp->priv;
 925         u32 val;
 926
 927         spin_lock_bh(&tp->lock);
 928
 929         if (tg3_readphy(tp, reg, &val))
 930                 val = -EIO;
 931
 932         spin_unlock_bh(&tp->lock);
 933
 934         return val;
 935 }
 936
 937 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 938 {
 939         struct tg3 *tp = bp->priv;
 940         u32 ret = 0;
 941
 942         spin_lock_bh(&tp->lock);
 943
 944         if (tg3_writephy(tp, reg, val))
 945                 ret = -EIO;
 946
 947         spin_unlock_bh(&tp->lock);
 948
 949         return ret;
 950 }
 951
 952 static int tg3_mdio_reset(struct mii_bus *bp)
 953 {
 954         return 0;
 955 }
 956
 957 static void tg3_mdio_config_5785(struct tg3 *tp)
 958 {
 959         u32 val;
 960         struct phy_device *phydev;
 961
 962         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
 963         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 964         case PHY_ID_BCM50610:
 965         case PHY_ID_BCM50610M:
 966                 val = MAC_PHYCFG2_50610_LED_MODES;
 967                 break;
 968         case PHY_ID_BCMAC131:
 969                 val = MAC_PHYCFG2_AC131_LED_MODES;
 970                 break;
 971         case PHY_ID_RTL8211C:
 972                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
 973                 break;
 974         case PHY_ID_RTL8201E:
 975                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
 976                 break;
 977         default:
 978                 return;
 979         }
 980
 981         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
 982                 tw32(MAC_PHYCFG2, val);
 983
 984                 val = tr32(MAC_PHYCFG1);
 985                 val &= ~(MAC_PHYCFG1_RGMII_INT |
 986                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
 987                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
 988                 tw32(MAC_PHYCFG1, val);
 989
 990                 return;
 991         }
 992
 993         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
 994                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
 995                        MAC_PHYCFG2_FMODE_MASK_MASK |
 996                        MAC_PHYCFG2_GMODE_MASK_MASK |
 997                        MAC_PHYCFG2_ACT_MASK_MASK   |
 998                        MAC_PHYCFG2_QUAL_MASK_MASK |
 999                        MAC_PHYCFG2_INBAND_ENABLE;
1000
1001         tw32(MAC_PHYCFG2, val);
1002
1003         val = tr32(MAC_PHYCFG1);
1004         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1005                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1006         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1007                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1008                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1009                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1010                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1011         }
1012         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1013                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1014         tw32(MAC_PHYCFG1, val);
1015
1016         val = tr32(MAC_EXT_RGMII_MODE);
1017         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1018                  MAC_RGMII_MODE_RX_QUALITY |
1019                  MAC_RGMII_MODE_RX_ACTIVITY |
1020                  MAC_RGMII_MODE_RX_ENG_DET |
1021                  MAC_RGMII_MODE_TX_ENABLE |
1022                  MAC_RGMII_MODE_TX_LOWPWR |
1023                  MAC_RGMII_MODE_TX_RESET);
1024         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1025                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1026                         val |= MAC_RGMII_MODE_RX_INT_B |
1027                                MAC_RGMII_MODE_RX_QUALITY |
1028                                MAC_RGMII_MODE_RX_ACTIVITY |
1029                                MAC_RGMII_MODE_RX_ENG_DET;
1030                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1031                         val |= MAC_RGMII_MODE_TX_ENABLE |
1032                                MAC_RGMII_MODE_TX_LOWPWR |
1033                                MAC_RGMII_MODE_TX_RESET;
1034         }
1035         tw32(MAC_EXT_RGMII_MODE, val);
1036 }
1037
1038 static void tg3_mdio_start(struct tg3 *tp)
1039 {
1040         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1041         tw32_f(MAC_MI_MODE, tp->mi_mode);
1042         udelay(80);
1043
1044         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1045             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1046                 tg3_mdio_config_5785(tp);
1047 }
1048
1049 static int tg3_mdio_init(struct tg3 *tp)
1050 {
1051         int i;
1052         u32 reg;
1053         struct phy_device *phydev;
1054
1055         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1056             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
1057                 u32 is_serdes;
1058
1059                 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1060
1061                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1062                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1063                 else
1064                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1065                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1066                 if (is_serdes)
1067                         tp->phy_addr += 7;
1068         } else
1069                 tp->phy_addr = TG3_PHY_MII_ADDR;
1070
1071         tg3_mdio_start(tp);
1072
1073         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1074             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1075                 return 0;
1076
1077         tp->mdio_bus = mdiobus_alloc();
1078         if (tp->mdio_bus == NULL)
1079                 return -ENOMEM;
1080
1081         tp->mdio_bus->name     = "tg3 mdio bus";
1082         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1083                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1084         tp->mdio_bus->priv     = tp;
1085         tp->mdio_bus->parent   = &tp->pdev->dev;
1086         tp->mdio_bus->read     = &tg3_mdio_read;
1087         tp->mdio_bus->write    = &tg3_mdio_write;
1088         tp->mdio_bus->reset    = &tg3_mdio_reset;
1089         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1090         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1091
1092         for (i = 0; i < PHY_MAX_ADDR; i++)
1093                 tp->mdio_bus->irq[i] = PHY_POLL;
1094
1095         /* The bus registration will look for all the PHYs on the mdio bus.
1096          * Unfortunately, it does not ensure the PHY is powered up before
1097          * accessing the PHY ID registers.  A chip reset is the
1098          * quickest way to bring the device back to an operational state..
1099          */
1100         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1101                 tg3_bmcr_reset(tp);
1102
1103         i = mdiobus_register(tp->mdio_bus);
1104         if (i) {
1105                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1106                 mdiobus_free(tp->mdio_bus);
1107                 return i;
1108         }
1109
1110         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1111
1112         if (!phydev || !phydev->drv) {
1113                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1114                 mdiobus_unregister(tp->mdio_bus);
1115                 mdiobus_free(tp->mdio_bus);
1116                 return -ENODEV;
1117         }
1118
1119         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1120         case PHY_ID_BCM57780:
1121                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1122                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1123                 break;
1124         case PHY_ID_BCM50610:
1125         case PHY_ID_BCM50610M:
1126                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1127                                      PHY_BRCM_RX_REFCLK_UNUSED |
1128                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1129                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1130                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1131                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1132                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1133                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1134                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1135                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1136                 /* fallthru */
1137         case PHY_ID_RTL8211C:
1138                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1139                 break;
1140         case PHY_ID_RTL8201E:
1141         case PHY_ID_BCMAC131:
1142                 phydev->interface = PHY_INTERFACE_MODE_MII;
1143                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1144                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1145                 break;
1146         }
1147
1148         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1149
1150         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1151                 tg3_mdio_config_5785(tp);
1152
1153         return 0;
1154 }
1155
1156 static void tg3_mdio_fini(struct tg3 *tp)
1157 {
1158         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1159                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1160                 mdiobus_unregister(tp->mdio_bus);
1161                 mdiobus_free(tp->mdio_bus);
1162         }
1163 }
1164
1165 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1166 {
1167         int err;
1168
1169         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1170         if (err)
1171                 goto done;
1172
1173         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1174         if (err)
1175                 goto done;
1176
1177         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1178                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1179         if (err)
1180                 goto done;
1181
1182         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1183
1184 done:
1185         return err;
1186 }
1187
1188 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1189 {
1190         int err;
1191
1192         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1193         if (err)
1194                 goto done;
1195
1196         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1197         if (err)
1198                 goto done;
1199
1200         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1201                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1202         if (err)
1203                 goto done;
1204
1205         err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1206
1207 done:
1208         return err;
1209 }
1210
1211 /* tp->lock is held. */
1212 static inline void tg3_generate_fw_event(struct tg3 *tp)
1213 {
1214         u32 val;
1215
1216         val = tr32(GRC_RX_CPU_EVENT);
1217         val |= GRC_RX_CPU_DRIVER_EVENT;
1218         tw32_f(GRC_RX_CPU_EVENT, val);
1219
1220         tp->last_event_jiffies = jiffies;
1221 }
1222
1223 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1224
1225 /* tp->lock is held. */
1226 static void tg3_wait_for_event_ack(struct tg3 *tp)
1227 {
1228         int i;
1229         unsigned int delay_cnt;
1230         long time_remain;
1231
1232         /* If enough time has passed, no wait is necessary. */
1233         time_remain = (long)(tp->last_event_jiffies + 1 +
1234                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1235                       (long)jiffies;
1236         if (time_remain < 0)
1237                 return;
1238
1239         /* Check if we can shorten the wait time. */
1240         delay_cnt = jiffies_to_usecs(time_remain);
1241         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1242                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1243         delay_cnt = (delay_cnt >> 3) + 1;
1244
1245         for (i = 0; i < delay_cnt; i++) {
1246                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1247                         break;
1248                 udelay(8);
1249         }
1250 }
1251
1252 /* tp->lock is held. */
1253 static void tg3_ump_link_report(struct tg3 *tp)
1254 {
1255         u32 reg;
1256         u32 val;
1257
1258         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1259             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1260                 return;
1261
1262         tg3_wait_for_event_ack(tp);
1263
1264         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1265
1266         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1267
1268         val = 0;
1269         if (!tg3_readphy(tp, MII_BMCR, &reg))
1270                 val = reg << 16;
1271         if (!tg3_readphy(tp, MII_BMSR, &reg))
1272                 val |= (reg & 0xffff);
1273         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1274
1275         val = 0;
1276         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1277                 val = reg << 16;
1278         if (!tg3_readphy(tp, MII_LPA, &reg))
1279                 val |= (reg & 0xffff);
1280         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1281
1282         val = 0;
1283         if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1284                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1285                         val = reg << 16;
1286                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1287                         val |= (reg & 0xffff);
1288         }
1289         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1290
1291         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1292                 val = reg << 16;
1293         else
1294                 val = 0;
1295         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1296
1297         tg3_generate_fw_event(tp);
1298 }
1299
1300 static void tg3_link_report(struct tg3 *tp)
1301 {
1302         if (!netif_carrier_ok(tp->dev)) {
1303                 netif_info(tp, link, tp->dev, "Link is down\n");
1304                 tg3_ump_link_report(tp);
1305         } else if (netif_msg_link(tp)) {
1306                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1307                             (tp->link_config.active_speed == SPEED_1000 ?
1308                              1000 :
1309                              (tp->link_config.active_speed == SPEED_100 ?
1310                               100 : 10)),
1311                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1312                              "full" : "half"));
1313
1314                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1315                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1316                             "on" : "off",
1317                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1318                             "on" : "off");
1319                 tg3_ump_link_report(tp);
1320         }
1321 }
1322
1323 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1324 {
1325         u16 miireg;
1326
1327         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1328                 miireg = ADVERTISE_PAUSE_CAP;
1329         else if (flow_ctrl & FLOW_CTRL_TX)
1330                 miireg = ADVERTISE_PAUSE_ASYM;
1331         else if (flow_ctrl & FLOW_CTRL_RX)
1332                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1333         else
1334                 miireg = 0;
1335
1336         return miireg;
1337 }
1338
1339 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1340 {
1341         u16 miireg;
1342
1343         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1344                 miireg = ADVERTISE_1000XPAUSE;
1345         else if (flow_ctrl & FLOW_CTRL_TX)
1346                 miireg = ADVERTISE_1000XPSE_ASYM;
1347         else if (flow_ctrl & FLOW_CTRL_RX)
1348                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1349         else
1350                 miireg = 0;
1351
1352         return miireg;
1353 }
1354
1355 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1356 {
1357         u8 cap = 0;
1358
1359         if (lcladv & ADVERTISE_1000XPAUSE) {
1360                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1361                         if (rmtadv & LPA_1000XPAUSE)
1362                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1363                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1364                                 cap = FLOW_CTRL_RX;
1365                 } else {
1366                         if (rmtadv & LPA_1000XPAUSE)
1367                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1368                 }
1369         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1370                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1371                         cap = FLOW_CTRL_TX;
1372         }
1373
1374         return cap;
1375 }
1376
1377 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1378 {
1379         u8 autoneg;
1380         u8 flowctrl = 0;
1381         u32 old_rx_mode = tp->rx_mode;
1382         u32 old_tx_mode = tp->tx_mode;
1383
1384         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1385                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1386         else
1387                 autoneg = tp->link_config.autoneg;
1388
1389         if (autoneg == AUTONEG_ENABLE &&
1390             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1391                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1392                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1393                 else
1394                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1395         } else
1396                 flowctrl = tp->link_config.flowctrl;
1397
1398         tp->link_config.active_flowctrl = flowctrl;
1399
1400         if (flowctrl & FLOW_CTRL_RX)
1401                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1402         else
1403                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1404
1405         if (old_rx_mode != tp->rx_mode)
1406                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1407
1408         if (flowctrl & FLOW_CTRL_TX)
1409                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1410         else
1411                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1412
1413         if (old_tx_mode != tp->tx_mode)
1414                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1415 }
1416
1417 static void tg3_adjust_link(struct net_device *dev)
1418 {
1419         u8 oldflowctrl, linkmesg = 0;
1420         u32 mac_mode, lcl_adv, rmt_adv;
1421         struct tg3 *tp = netdev_priv(dev);
1422         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1423
1424         spin_lock_bh(&tp->lock);
1425
1426         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1427                                     MAC_MODE_HALF_DUPLEX);
1428
1429         oldflowctrl = tp->link_config.active_flowctrl;
1430
1431         if (phydev->link) {
1432                 lcl_adv = 0;
1433                 rmt_adv = 0;
1434
1435                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1436                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1437                 else if (phydev->speed == SPEED_1000 ||
1438                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1439                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1440                 else
1441                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1442
1443                 if (phydev->duplex == DUPLEX_HALF)
1444                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1445                 else {
1446                         lcl_adv = tg3_advert_flowctrl_1000T(
1447                                   tp->link_config.flowctrl);
1448
1449                         if (phydev->pause)
1450                                 rmt_adv = LPA_PAUSE_CAP;
1451                         if (phydev->asym_pause)
1452                                 rmt_adv |= LPA_PAUSE_ASYM;
1453                 }
1454
1455                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1456         } else
1457                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1458
1459         if (mac_mode != tp->mac_mode) {
1460                 tp->mac_mode = mac_mode;
1461                 tw32_f(MAC_MODE, tp->mac_mode);
1462                 udelay(40);
1463         }
1464
1465         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1466                 if (phydev->speed == SPEED_10)
1467                         tw32(MAC_MI_STAT,
1468                              MAC_MI_STAT_10MBPS_MODE |
1469                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1470                 else
1471                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1472         }
1473
1474         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1475                 tw32(MAC_TX_LENGTHS,
1476                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1477                       (6 << TX_LENGTHS_IPG_SHIFT) |
1478                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1479         else
1480                 tw32(MAC_TX_LENGTHS,
1481                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1482                       (6 << TX_LENGTHS_IPG_SHIFT) |
1483                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1484
1485         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1486             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1487             phydev->speed != tp->link_config.active_speed ||
1488             phydev->duplex != tp->link_config.active_duplex ||
1489             oldflowctrl != tp->link_config.active_flowctrl)
1490                 linkmesg = 1;
1491
1492         tp->link_config.active_speed = phydev->speed;
1493         tp->link_config.active_duplex = phydev->duplex;
1494
1495         spin_unlock_bh(&tp->lock);
1496
1497         if (linkmesg)
1498                 tg3_link_report(tp);
1499 }
1500
1501 static int tg3_phy_init(struct tg3 *tp)
1502 {
1503         struct phy_device *phydev;
1504
1505         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1506                 return 0;
1507
1508         /* Bring the PHY back to a known state. */
1509         tg3_bmcr_reset(tp);
1510
1511         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1512
1513         /* Attach the MAC to the PHY. */
1514         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1515                              phydev->dev_flags, phydev->interface);
1516         if (IS_ERR(phydev)) {
1517                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1518                 return PTR_ERR(phydev);
1519         }
1520
1521         /* Mask with MAC supported features. */
1522         switch (phydev->interface) {
1523         case PHY_INTERFACE_MODE_GMII:
1524         case PHY_INTERFACE_MODE_RGMII:
1525                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1526                         phydev->supported &= (PHY_GBIT_FEATURES |
1527                                               SUPPORTED_Pause |
1528                                               SUPPORTED_Asym_Pause);
1529                         break;
1530                 }
1531                 /* fallthru */
1532         case PHY_INTERFACE_MODE_MII:
1533                 phydev->supported &= (PHY_BASIC_FEATURES |
1534                                       SUPPORTED_Pause |
1535                                       SUPPORTED_Asym_Pause);
1536                 break;
1537         default:
1538                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1539                 return -EINVAL;
1540         }
1541
1542         tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1543
1544         phydev->advertising = phydev->supported;
1545
1546         return 0;
1547 }
1548
1549 static void tg3_phy_start(struct tg3 *tp)
1550 {
1551         struct phy_device *phydev;
1552
1553         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1554                 return;
1555
1556         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1557
1558         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1559                 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1560                 phydev->speed = tp->link_config.orig_speed;
1561                 phydev->duplex = tp->link_config.orig_duplex;
1562                 phydev->autoneg = tp->link_config.orig_autoneg;
1563                 phydev->advertising = tp->link_config.orig_advertising;
1564         }
1565
1566         phy_start(phydev);
1567
1568         phy_start_aneg(phydev);
1569 }
1570
1571 static void tg3_phy_stop(struct tg3 *tp)
1572 {
1573         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1574                 return;
1575
1576         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1577 }
1578
1579 static void tg3_phy_fini(struct tg3 *tp)
1580 {
1581         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1582                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1583                 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1584         }
1585 }
1586
1587 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1588 {
1589         int err;
1590
1591         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1592         if (!err)
1593                 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1594
1595         return err;
1596 }
1597
1598 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1599 {
1600         int err;
1601
1602         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1603         if (!err)
1604                 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1605
1606         return err;
1607 }
1608
1609 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1610 {
1611         u32 phytest;
1612
1613         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1614                 u32 phy;
1615
1616                 tg3_writephy(tp, MII_TG3_FET_TEST,
1617                              phytest | MII_TG3_FET_SHADOW_EN);
1618                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1619                         if (enable)
1620                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1621                         else
1622                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1623                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1624                 }
1625                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1626         }
1627 }
1628
1629 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1630 {
1631         u32 reg;
1632
1633         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1634             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1635               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1636              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1637                 return;
1638
1639         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1640                 tg3_phy_fet_toggle_apd(tp, enable);
1641                 return;
1642         }
1643
1644         reg = MII_TG3_MISC_SHDW_WREN |
1645               MII_TG3_MISC_SHDW_SCR5_SEL |
1646               MII_TG3_MISC_SHDW_SCR5_LPED |
1647               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1648               MII_TG3_MISC_SHDW_SCR5_SDTL |
1649               MII_TG3_MISC_SHDW_SCR5_C125OE;
1650         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1651                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1652
1653         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1654
1655
1656         reg = MII_TG3_MISC_SHDW_WREN |
1657               MII_TG3_MISC_SHDW_APD_SEL |
1658               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1659         if (enable)
1660                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1661
1662         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1663 }
1664
1665 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1666 {
1667         u32 phy;
1668
1669         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1670             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
1671                 return;
1672
1673         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1674                 u32 ephy;
1675
1676                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1677                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1678
1679                         tg3_writephy(tp, MII_TG3_FET_TEST,
1680                                      ephy | MII_TG3_FET_SHADOW_EN);
1681                         if (!tg3_readphy(tp, reg, &phy)) {
1682                                 if (enable)
1683                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1684                                 else
1685                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1686                                 tg3_writephy(tp, reg, phy);
1687                         }
1688                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1689                 }
1690         } else {
1691                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1692                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1693                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1694                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1695                         if (enable)
1696                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1697                         else
1698                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1699                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1700                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1701                 }
1702         }
1703 }
1704
1705 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1706 {
1707         u32 val;
1708
1709         if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1710                 return;
1711
1712         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1713             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1714                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1715                              (val | (1 << 15) | (1 << 4)));
1716 }
1717
1718 static void tg3_phy_apply_otp(struct tg3 *tp)
1719 {
1720         u32 otp, phy;
1721
1722         if (!tp->phy_otp)
1723                 return;
1724
1725         otp = tp->phy_otp;
1726
1727         /* Enable SM_DSP clock and tx 6dB coding. */
1728         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1729               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1730               MII_TG3_AUXCTL_ACTL_TX_6DB;
1731         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1732
1733         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1734         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1735         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1736
1737         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1738               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1739         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1740
1741         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1742         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1743         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1744
1745         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1746         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1747
1748         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1749         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1750
1751         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1752               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1753         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1754
1755         /* Turn off SM_DSP clock. */
1756         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1757               MII_TG3_AUXCTL_ACTL_TX_6DB;
1758         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1759 }
1760
1761 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
1762 {
1763         u32 val;
1764
1765         if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
1766                 return;
1767
1768         tp->setlpicnt = 0;
1769
1770         if (tp->link_config.autoneg == AUTONEG_ENABLE &&
1771             current_link_up == 1 &&
1772             (tp->link_config.active_speed == SPEED_1000 ||
1773              (tp->link_config.active_speed == SPEED_100 &&
1774               tp->link_config.active_duplex == DUPLEX_FULL))) {
1775                 u32 eeectl;
1776
1777                 if (tp->link_config.active_speed == SPEED_1000)
1778                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
1779                 else
1780                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
1781
1782                 tw32(TG3_CPMU_EEE_CTRL, eeectl);
1783
1784                 tg3_phy_cl45_read(tp, 0x7, TG3_CL45_D7_EEERES_STAT, &val);
1785
1786                 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
1787                     val == TG3_CL45_D7_EEERES_STAT_LP_100TX)
1788                         tp->setlpicnt = 2;
1789         }
1790
1791         if (!tp->setlpicnt) {
1792                 val = tr32(TG3_CPMU_EEE_MODE);
1793                 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
1794         }
1795 }
1796
1797 static int tg3_wait_macro_done(struct tg3 *tp)
1798 {
1799         int limit = 100;
1800
1801         while (limit--) {
1802                 u32 tmp32;
1803
1804                 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1805                         if ((tmp32 & 0x1000) == 0)
1806                                 break;
1807                 }
1808         }
1809         if (limit < 0)
1810                 return -EBUSY;
1811
1812         return 0;
1813 }
1814
1815 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1816 {
1817         static const u32 test_pat[4][6] = {
1818         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1819         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1820         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1821         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1822         };
1823         int chan;
1824
1825         for (chan = 0; chan < 4; chan++) {
1826                 int i;
1827
1828                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1829                              (chan * 0x2000) | 0x0200);
1830                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1831
1832                 for (i = 0; i < 6; i++)
1833                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1834                                      test_pat[chan][i]);
1835
1836                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1837                 if (tg3_wait_macro_done(tp)) {
1838                         *resetp = 1;
1839                         return -EBUSY;
1840                 }
1841
1842                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1843                              (chan * 0x2000) | 0x0200);
1844                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1845                 if (tg3_wait_macro_done(tp)) {
1846                         *resetp = 1;
1847                         return -EBUSY;
1848                 }
1849
1850                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1851                 if (tg3_wait_macro_done(tp)) {
1852                         *resetp = 1;
1853                         return -EBUSY;
1854                 }
1855
1856                 for (i = 0; i < 6; i += 2) {
1857                         u32 low, high;
1858
1859                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1860                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1861                             tg3_wait_macro_done(tp)) {
1862                                 *resetp = 1;
1863                                 return -EBUSY;
1864                         }
1865                         low &= 0x7fff;
1866                         high &= 0x000f;
1867                         if (low != test_pat[chan][i] ||
1868                             high != test_pat[chan][i+1]) {
1869                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1870                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1871                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1872
1873                                 return -EBUSY;
1874                         }
1875                 }
1876         }
1877
1878         return 0;
1879 }
1880
1881 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1882 {
1883         int chan;
1884
1885         for (chan = 0; chan < 4; chan++) {
1886                 int i;
1887
1888                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1889                              (chan * 0x2000) | 0x0200);
1890                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1891                 for (i = 0; i < 6; i++)
1892                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1893                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1894                 if (tg3_wait_macro_done(tp))
1895                         return -EBUSY;
1896         }
1897
1898         return 0;
1899 }
1900
1901 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1902 {
1903         u32 reg32, phy9_orig;
1904         int retries, do_phy_reset, err;
1905
1906         retries = 10;
1907         do_phy_reset = 1;
1908         do {
1909                 if (do_phy_reset) {
1910                         err = tg3_bmcr_reset(tp);
1911                         if (err)
1912                                 return err;
1913                         do_phy_reset = 0;
1914                 }
1915
1916                 /* Disable transmitter and interrupt.  */
1917                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1918                         continue;
1919
1920                 reg32 |= 0x3000;
1921                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1922
1923                 /* Set full-duplex, 1000 mbps.  */
1924                 tg3_writephy(tp, MII_BMCR,
1925                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1926
1927                 /* Set to master mode.  */
1928                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1929                         continue;
1930
1931                 tg3_writephy(tp, MII_TG3_CTRL,
1932                              (MII_TG3_CTRL_AS_MASTER |
1933                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1934
1935                 /* Enable SM_DSP_CLOCK and 6dB.  */
1936                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1937
1938                 /* Block the PHY control access.  */
1939                 tg3_phydsp_write(tp, 0x8005, 0x0800);
1940
1941                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1942                 if (!err)
1943                         break;
1944         } while (--retries);
1945
1946         err = tg3_phy_reset_chanpat(tp);
1947         if (err)
1948                 return err;
1949
1950         tg3_phydsp_write(tp, 0x8005, 0x0000);
1951
1952         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1953         tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1954
1955         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1956             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1957                 /* Set Extended packet length bit for jumbo frames */
1958                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1959         } else {
1960                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1961         }
1962
1963         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1964
1965         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1966                 reg32 &= ~0x3000;
1967                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1968         } else if (!err)
1969                 err = -EBUSY;
1970
1971         return err;
1972 }
1973
1974 /* This will reset the tigon3 PHY if there is no valid
1975  * link unless the FORCE argument is non-zero.
1976  */
1977 static int tg3_phy_reset(struct tg3 *tp)
1978 {
1979         u32 val, cpmuctrl;
1980         int err;
1981
1982         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1983                 val = tr32(GRC_MISC_CFG);
1984                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1985                 udelay(40);
1986         }
1987         err  = tg3_readphy(tp, MII_BMSR, &val);
1988         err |= tg3_readphy(tp, MII_BMSR, &val);
1989         if (err != 0)
1990                 return -EBUSY;
1991
1992         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1993                 netif_carrier_off(tp->dev);
1994                 tg3_link_report(tp);
1995         }
1996
1997         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1998             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1999             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2000                 err = tg3_phy_reset_5703_4_5(tp);
2001                 if (err)
2002                         return err;
2003                 goto out;
2004         }
2005
2006         cpmuctrl = 0;
2007         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
2008             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
2009                 cpmuctrl = tr32(TG3_CPMU_CTRL);
2010                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2011                         tw32(TG3_CPMU_CTRL,
2012                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2013         }
2014
2015         err = tg3_bmcr_reset(tp);
2016         if (err)
2017                 return err;
2018
2019         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2020                 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2021                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2022
2023                 tw32(TG3_CPMU_CTRL, cpmuctrl);
2024         }
2025
2026         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2027             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2028                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2029                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2030                     CPMU_LSPD_1000MB_MACCLK_12_5) {
2031                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2032                         udelay(40);
2033                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2034                 }
2035         }
2036
2037         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2038              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
2039             (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2040                 return 0;
2041
2042         tg3_phy_apply_otp(tp);
2043
2044         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2045                 tg3_phy_toggle_apd(tp, true);
2046         else
2047                 tg3_phy_toggle_apd(tp, false);
2048
2049 out:
2050         if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) {
2051                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2052                 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2053                 tg3_phydsp_write(tp, 0x000a, 0x0323);
2054                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2055         }
2056         if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2057                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2058                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2059         }
2060         if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2061                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2062                 tg3_phydsp_write(tp, 0x000a, 0x310b);
2063                 tg3_phydsp_write(tp, 0x201f, 0x9506);
2064                 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2065                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2066         } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2067                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2068                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2069                 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2070                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2071                         tg3_writephy(tp, MII_TG3_TEST1,
2072                                      MII_TG3_TEST1_TRIM_EN | 0x4);
2073                 } else
2074                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2075                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2076         }
2077         /* Set Extended packet length bit (bit 14) on all chips that */
2078         /* support jumbo frames */
2079         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2080                 /* Cannot do read-modify-write on 5401 */
2081                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2082         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2083                 /* Set bit 14 with read-modify-write to preserve other bits */
2084                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2085                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
2086                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val | 0x4000);
2087         }
2088
2089         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2090          * jumbo frames transmission.
2091          */
2092         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2093                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2094                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2095                                      val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2096         }
2097
2098         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2099                 /* adjust output voltage */
2100                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2101         }
2102
2103         tg3_phy_toggle_automdix(tp, 1);
2104         tg3_phy_set_wirespeed(tp);
2105         return 0;
2106 }
2107
2108 static void tg3_frob_aux_power(struct tg3 *tp)
2109 {
2110         struct tg3 *tp_peer = tp;
2111
2112         /* The GPIOs do something completely different on 57765. */
2113         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2114             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2115             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2116                 return;
2117
2118         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2119             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2120             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2121                 struct net_device *dev_peer;
2122
2123                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2124                 /* remove_one() may have been run on the peer. */
2125                 if (!dev_peer)
2126                         tp_peer = tp;
2127                 else
2128                         tp_peer = netdev_priv(dev_peer);
2129         }
2130
2131         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2132             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2133             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2134             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2135                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2136                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2137                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2138                                     (GRC_LCLCTRL_GPIO_OE0 |
2139                                      GRC_LCLCTRL_GPIO_OE1 |
2140                                      GRC_LCLCTRL_GPIO_OE2 |
2141                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2142                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2143                                     100);
2144                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2145                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2146                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2147                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2148                                              GRC_LCLCTRL_GPIO_OE1 |
2149                                              GRC_LCLCTRL_GPIO_OE2 |
2150                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2151                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2152                                              tp->grc_local_ctrl;
2153                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2154
2155                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2156                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2157
2158                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2159                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2160                 } else {
2161                         u32 no_gpio2;
2162                         u32 grc_local_ctrl = 0;
2163
2164                         if (tp_peer != tp &&
2165                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2166                                 return;
2167
2168                         /* Workaround to prevent overdrawing Amps. */
2169                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2170                             ASIC_REV_5714) {
2171                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2172                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2173                                             grc_local_ctrl, 100);
2174                         }
2175
2176                         /* On 5753 and variants, GPIO2 cannot be used. */
2177                         no_gpio2 = tp->nic_sram_data_cfg &
2178                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2179
2180                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2181                                          GRC_LCLCTRL_GPIO_OE1 |
2182                                          GRC_LCLCTRL_GPIO_OE2 |
2183                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2184                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2185                         if (no_gpio2) {
2186                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2187                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2188                         }
2189                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2190                                                     grc_local_ctrl, 100);
2191
2192                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2193
2194                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2195                                                     grc_local_ctrl, 100);
2196
2197                         if (!no_gpio2) {
2198                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2199                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2200                                             grc_local_ctrl, 100);
2201                         }
2202                 }
2203         } else {
2204                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2205                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2206                         if (tp_peer != tp &&
2207                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2208                                 return;
2209
2210                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2211                                     (GRC_LCLCTRL_GPIO_OE1 |
2212                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2213
2214                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2215                                     GRC_LCLCTRL_GPIO_OE1, 100);
2216
2217                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2218                                     (GRC_LCLCTRL_GPIO_OE1 |
2219                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2220                 }
2221         }
2222 }
2223
2224 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2225 {
2226         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2227                 return 1;
2228         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2229                 if (speed != SPEED_10)
2230                         return 1;
2231         } else if (speed == SPEED_10)
2232                 return 1;
2233
2234         return 0;
2235 }
2236
2237 static int tg3_setup_phy(struct tg3 *, int);
2238
2239 #define RESET_KIND_SHUTDOWN     0
2240 #define RESET_KIND_INIT         1
2241 #define RESET_KIND_SUSPEND      2
2242
2243 static void tg3_write_sig_post_reset(struct tg3 *, int);
2244 static int tg3_halt_cpu(struct tg3 *, u32);
2245
2246 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2247 {
2248         u32 val;
2249
2250         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2251                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2252                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2253                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2254
2255                         sg_dig_ctrl |=
2256                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2257                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2258                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2259                 }
2260                 return;
2261         }
2262
2263         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2264                 tg3_bmcr_reset(tp);
2265                 val = tr32(GRC_MISC_CFG);
2266                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2267                 udelay(40);
2268                 return;
2269         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2270                 u32 phytest;
2271                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2272                         u32 phy;
2273
2274                         tg3_writephy(tp, MII_ADVERTISE, 0);
2275                         tg3_writephy(tp, MII_BMCR,
2276                                      BMCR_ANENABLE | BMCR_ANRESTART);
2277
2278                         tg3_writephy(tp, MII_TG3_FET_TEST,
2279                                      phytest | MII_TG3_FET_SHADOW_EN);
2280                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2281                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2282                                 tg3_writephy(tp,
2283                                              MII_TG3_FET_SHDW_AUXMODE4,
2284                                              phy);
2285                         }
2286                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2287                 }
2288                 return;
2289         } else if (do_low_power) {
2290                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2291                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2292
2293                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2294                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2295                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2296                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2297                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2298         }
2299
2300         /* The PHY should not be powered down on some chips because
2301          * of bugs.
2302          */
2303         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2304             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2305             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2306              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2307                 return;
2308
2309         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2310             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2311                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2312                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2313                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2314                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2315         }
2316
2317         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2318 }
2319
2320 /* tp->lock is held. */
2321 static int tg3_nvram_lock(struct tg3 *tp)
2322 {
2323         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2324                 int i;
2325
2326                 if (tp->nvram_lock_cnt == 0) {
2327                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2328                         for (i = 0; i < 8000; i++) {
2329                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2330                                         break;
2331                                 udelay(20);
2332                         }
2333                         if (i == 8000) {
2334                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2335                                 return -ENODEV;
2336                         }
2337                 }
2338                 tp->nvram_lock_cnt++;
2339         }
2340         return 0;
2341 }
2342
2343 /* tp->lock is held. */
2344 static void tg3_nvram_unlock(struct tg3 *tp)
2345 {
2346         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2347                 if (tp->nvram_lock_cnt > 0)
2348                         tp->nvram_lock_cnt--;
2349                 if (tp->nvram_lock_cnt == 0)
2350                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2351         }
2352 }
2353
2354 /* tp->lock is held. */
2355 static void tg3_enable_nvram_access(struct tg3 *tp)
2356 {
2357         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2358             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2359                 u32 nvaccess = tr32(NVRAM_ACCESS);
2360
2361                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2362         }
2363 }
2364
2365 /* tp->lock is held. */
2366 static void tg3_disable_nvram_access(struct tg3 *tp)
2367 {
2368         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2369             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2370                 u32 nvaccess = tr32(NVRAM_ACCESS);
2371
2372                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2373         }
2374 }
2375
2376 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2377                                         u32 offset, u32 *val)
2378 {
2379         u32 tmp;
2380         int i;
2381
2382         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2383                 return -EINVAL;
2384
2385         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2386                                         EEPROM_ADDR_DEVID_MASK |
2387                                         EEPROM_ADDR_READ);
2388         tw32(GRC_EEPROM_ADDR,
2389              tmp |
2390              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2391              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2392               EEPROM_ADDR_ADDR_MASK) |
2393              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2394
2395         for (i = 0; i < 1000; i++) {
2396                 tmp = tr32(GRC_EEPROM_ADDR);
2397
2398                 if (tmp & EEPROM_ADDR_COMPLETE)
2399                         break;
2400                 msleep(1);
2401         }
2402         if (!(tmp & EEPROM_ADDR_COMPLETE))
2403                 return -EBUSY;
2404
2405         tmp = tr32(GRC_EEPROM_DATA);
2406
2407         /*
2408          * The data will always be opposite the native endian
2409          * format.  Perform a blind byteswap to compensate.
2410          */
2411         *val = swab32(tmp);
2412
2413         return 0;
2414 }
2415
2416 #define NVRAM_CMD_TIMEOUT 10000
2417
2418 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2419 {
2420         int i;
2421
2422         tw32(NVRAM_CMD, nvram_cmd);
2423         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2424                 udelay(10);
2425                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2426                         udelay(10);
2427                         break;
2428                 }
2429         }
2430
2431         if (i == NVRAM_CMD_TIMEOUT)
2432                 return -EBUSY;
2433
2434         return 0;
2435 }
2436
2437 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2438 {
2439         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2440             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2441             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2442            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2443             (tp->nvram_jedecnum == JEDEC_ATMEL))
2444
2445                 addr = ((addr / tp->nvram_pagesize) <<
2446                         ATMEL_AT45DB0X1B_PAGE_POS) +
2447                        (addr % tp->nvram_pagesize);
2448
2449         return addr;
2450 }
2451
2452 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2453 {
2454         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2455             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2456             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2457            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2458             (tp->nvram_jedecnum == JEDEC_ATMEL))
2459
2460                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2461                         tp->nvram_pagesize) +
2462                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2463
2464         return addr;
2465 }
2466
2467 /* NOTE: Data read in from NVRAM is byteswapped according to
2468  * the byteswapping settings for all other register accesses.
2469  * tg3 devices are BE devices, so on a BE machine, the data
2470  * returned will be exactly as it is seen in NVRAM.  On a LE
2471  * machine, the 32-bit value will be byteswapped.
2472  */
2473 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2474 {
2475         int ret;
2476
2477         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2478                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2479
2480         offset = tg3_nvram_phys_addr(tp, offset);
2481
2482         if (offset > NVRAM_ADDR_MSK)
2483                 return -EINVAL;
2484
2485         ret = tg3_nvram_lock(tp);
2486         if (ret)
2487                 return ret;
2488
2489         tg3_enable_nvram_access(tp);
2490
2491         tw32(NVRAM_ADDR, offset);
2492         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2493                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2494
2495         if (ret == 0)
2496                 *val = tr32(NVRAM_RDDATA);
2497
2498         tg3_disable_nvram_access(tp);
2499
2500         tg3_nvram_unlock(tp);
2501
2502         return ret;
2503 }
2504
2505 /* Ensures NVRAM data is in bytestream format. */
2506 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2507 {
2508         u32 v;
2509         int res = tg3_nvram_read(tp, offset, &v);
2510         if (!res)
2511                 *val = cpu_to_be32(v);
2512         return res;
2513 }
2514
2515 /* tp->lock is held. */
2516 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2517 {
2518         u32 addr_high, addr_low;
2519         int i;
2520
2521         addr_high = ((tp->dev->dev_addr[0] << 8) |
2522                      tp->dev->dev_addr[1]);
2523         addr_low = ((tp->dev->dev_addr[2] << 24) |
2524                     (tp->dev->dev_addr[3] << 16) |
2525                     (tp->dev->dev_addr[4] <<  8) |
2526                     (tp->dev->dev_addr[5] <<  0));
2527         for (i = 0; i < 4; i++) {
2528                 if (i == 1 && skip_mac_1)
2529                         continue;
2530                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2531                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2532         }
2533
2534         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2535             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2536                 for (i = 0; i < 12; i++) {
2537                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2538                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2539                 }
2540         }
2541
2542         addr_high = (tp->dev->dev_addr[0] +
2543                      tp->dev->dev_addr[1] +
2544                      tp->dev->dev_addr[2] +
2545                      tp->dev->dev_addr[3] +
2546                      tp->dev->dev_addr[4] +
2547                      tp->dev->dev_addr[5]) &
2548                 TX_BACKOFF_SEED_MASK;
2549         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2550 }
2551
2552 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2553 {
2554         u32 misc_host_ctrl;
2555         bool device_should_wake, do_low_power;
2556
2557         /* Make sure register accesses (indirect or otherwise)
2558          * will function correctly.
2559          */
2560         pci_write_config_dword(tp->pdev,
2561                                TG3PCI_MISC_HOST_CTRL,
2562                                tp->misc_host_ctrl);
2563
2564         switch (state) {
2565         case PCI_D0:
2566                 pci_enable_wake(tp->pdev, state, false);
2567                 pci_set_power_state(tp->pdev, PCI_D0);
2568
2569                 /* Switch out of Vaux if it is a NIC */
2570                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2571                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2572
2573                 return 0;
2574
2575         case PCI_D1:
2576         case PCI_D2:
2577         case PCI_D3hot:
2578                 break;
2579
2580         default:
2581                 netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
2582                            state);
2583                 return -EINVAL;
2584         }
2585
2586         /* Restore the CLKREQ setting. */
2587         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2588                 u16 lnkctl;
2589
2590                 pci_read_config_word(tp->pdev,
2591                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2592                                      &lnkctl);
2593                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2594                 pci_write_config_word(tp->pdev,
2595                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2596                                       lnkctl);
2597         }
2598
2599         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2600         tw32(TG3PCI_MISC_HOST_CTRL,
2601              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2602
2603         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2604                              device_may_wakeup(&tp->pdev->dev) &&
2605                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2606
2607         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2608                 do_low_power = false;
2609                 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
2610                     !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2611                         struct phy_device *phydev;
2612                         u32 phyid, advertising;
2613
2614                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2615
2616                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2617
2618                         tp->link_config.orig_speed = phydev->speed;
2619                         tp->link_config.orig_duplex = phydev->duplex;
2620                         tp->link_config.orig_autoneg = phydev->autoneg;
2621                         tp->link_config.orig_advertising = phydev->advertising;
2622
2623                         advertising = ADVERTISED_TP |
2624                                       ADVERTISED_Pause |
2625                                       ADVERTISED_Autoneg |
2626                                       ADVERTISED_10baseT_Half;
2627
2628                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2629                             device_should_wake) {
2630                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2631                                         advertising |=
2632                                                 ADVERTISED_100baseT_Half |
2633                                                 ADVERTISED_100baseT_Full |
2634                                                 ADVERTISED_10baseT_Full;
2635                                 else
2636                                         advertising |= ADVERTISED_10baseT_Full;
2637                         }
2638
2639                         phydev->advertising = advertising;
2640
2641                         phy_start_aneg(phydev);
2642
2643                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2644                         if (phyid != PHY_ID_BCMAC131) {
2645                                 phyid &= PHY_BCM_OUI_MASK;
2646                                 if (phyid == PHY_BCM_OUI_1 ||
2647                                     phyid == PHY_BCM_OUI_2 ||
2648                                     phyid == PHY_BCM_OUI_3)
2649                                         do_low_power = true;
2650                         }
2651                 }
2652         } else {
2653                 do_low_power = true;
2654
2655                 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2656                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2657                         tp->link_config.orig_speed = tp->link_config.speed;
2658                         tp->link_config.orig_duplex = tp->link_config.duplex;
2659                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2660                 }
2661
2662                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
2663                         tp->link_config.speed = SPEED_10;
2664                         tp->link_config.duplex = DUPLEX_HALF;
2665                         tp->link_config.autoneg = AUTONEG_ENABLE;
2666                         tg3_setup_phy(tp, 0);
2667                 }
2668         }
2669
2670         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2671                 u32 val;
2672
2673                 val = tr32(GRC_VCPU_EXT_CTRL);
2674                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2675         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2676                 int i;
2677                 u32 val;
2678
2679                 for (i = 0; i < 200; i++) {
2680                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2681                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2682                                 break;
2683                         msleep(1);
2684                 }
2685         }
2686         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2687                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2688                                                      WOL_DRV_STATE_SHUTDOWN |
2689                                                      WOL_DRV_WOL |
2690                                                      WOL_SET_MAGIC_PKT);
2691
2692         if (device_should_wake) {
2693                 u32 mac_mode;
2694
2695                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
2696                         if (do_low_power) {
2697                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2698                                 udelay(40);
2699                         }
2700
2701                         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
2702                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2703                         else
2704                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2705
2706                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2707                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2708                             ASIC_REV_5700) {
2709                                 u32 speed = (tp->tg3_flags &
2710                                              TG3_FLAG_WOL_SPEED_100MB) ?
2711                                              SPEED_100 : SPEED_10;
2712                                 if (tg3_5700_link_polarity(tp, speed))
2713                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2714                                 else
2715                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2716                         }
2717                 } else {
2718                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2719                 }
2720
2721                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2722                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2723
2724                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2725                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2726                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2727                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2728                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2729                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2730
2731                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2732                         mac_mode |= tp->mac_mode &
2733                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2734                         if (mac_mode & MAC_MODE_APE_TX_EN)
2735                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2736                 }
2737
2738                 tw32_f(MAC_MODE, mac_mode);
2739                 udelay(100);
2740
2741                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2742                 udelay(10);
2743         }
2744
2745         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2746             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2747              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2748                 u32 base_val;
2749
2750                 base_val = tp->pci_clock_ctrl;
2751                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2752                              CLOCK_CTRL_TXCLK_DISABLE);
2753
2754                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2755                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2756         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2757                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2758                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2759                 /* do nothing */
2760         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2761                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2762                 u32 newbits1, newbits2;
2763
2764                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2765                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2766                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2767                                     CLOCK_CTRL_TXCLK_DISABLE |
2768                                     CLOCK_CTRL_ALTCLK);
2769                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2770                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2771                         newbits1 = CLOCK_CTRL_625_CORE;
2772                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2773                 } else {
2774                         newbits1 = CLOCK_CTRL_ALTCLK;
2775                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2776                 }
2777
2778                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2779                             40);
2780
2781                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2782                             40);
2783
2784                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2785                         u32 newbits3;
2786
2787                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2788                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2789                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2790                                             CLOCK_CTRL_TXCLK_DISABLE |
2791                                             CLOCK_CTRL_44MHZ_CORE);
2792                         } else {
2793                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2794                         }
2795
2796                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2797                                     tp->pci_clock_ctrl | newbits3, 40);
2798                 }
2799         }
2800
2801         if (!(device_should_wake) &&
2802             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2803                 tg3_power_down_phy(tp, do_low_power);
2804
2805         tg3_frob_aux_power(tp);
2806
2807         /* Workaround for unstable PLL clock */
2808         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2809             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2810                 u32 val = tr32(0x7d00);
2811
2812                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2813                 tw32(0x7d00, val);
2814                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2815                         int err;
2816
2817                         err = tg3_nvram_lock(tp);
2818                         tg3_halt_cpu(tp, RX_CPU_BASE);
2819                         if (!err)
2820                                 tg3_nvram_unlock(tp);
2821                 }
2822         }
2823
2824         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2825
2826         if (device_should_wake)
2827                 pci_enable_wake(tp->pdev, state, true);
2828
2829         /* Finally, set the new power state. */
2830         pci_set_power_state(tp->pdev, state);
2831
2832         return 0;
2833 }
2834
2835 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2836 {
2837         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2838         case MII_TG3_AUX_STAT_10HALF:
2839                 *speed = SPEED_10;
2840                 *duplex = DUPLEX_HALF;
2841                 break;
2842
2843         case MII_TG3_AUX_STAT_10FULL:
2844                 *speed = SPEED_10;
2845                 *duplex = DUPLEX_FULL;
2846                 break;
2847
2848         case MII_TG3_AUX_STAT_100HALF:
2849                 *speed = SPEED_100;
2850                 *duplex = DUPLEX_HALF;
2851                 break;
2852
2853         case MII_TG3_AUX_STAT_100FULL:
2854                 *speed = SPEED_100;
2855                 *duplex = DUPLEX_FULL;
2856                 break;
2857
2858         case MII_TG3_AUX_STAT_1000HALF:
2859                 *speed = SPEED_1000;
2860                 *duplex = DUPLEX_HALF;
2861                 break;
2862
2863         case MII_TG3_AUX_STAT_1000FULL:
2864                 *speed = SPEED_1000;
2865                 *duplex = DUPLEX_FULL;
2866                 break;
2867
2868         default:
2869                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2870                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2871                                  SPEED_10;
2872                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2873                                   DUPLEX_HALF;
2874                         break;
2875                 }
2876                 *speed = SPEED_INVALID;
2877                 *duplex = DUPLEX_INVALID;
2878                 break;
2879         }
2880 }
2881
2882 static void tg3_phy_copper_begin(struct tg3 *tp)
2883 {
2884         u32 new_adv;
2885         int i;
2886
2887         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2888                 /* Entering low power mode.  Disable gigabit and
2889                  * 100baseT advertisements.
2890                  */
2891                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2892
2893                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2894                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2895                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2896                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2897
2898                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2899         } else if (tp->link_config.speed == SPEED_INVALID) {
2900                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
2901                         tp->link_config.advertising &=
2902                                 ~(ADVERTISED_1000baseT_Half |
2903                                   ADVERTISED_1000baseT_Full);
2904
2905                 new_adv = ADVERTISE_CSMA;
2906                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2907                         new_adv |= ADVERTISE_10HALF;
2908                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2909                         new_adv |= ADVERTISE_10FULL;
2910                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2911                         new_adv |= ADVERTISE_100HALF;
2912                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2913                         new_adv |= ADVERTISE_100FULL;
2914
2915                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2916
2917                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2918
2919                 if (tp->link_config.advertising &
2920                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2921                         new_adv = 0;
2922                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2923                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2924                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2925                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2926                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) &&
2927                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2928                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2929                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2930                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2931                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2932                 } else {
2933                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2934                 }
2935         } else {
2936                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2937                 new_adv |= ADVERTISE_CSMA;
2938
2939                 /* Asking for a specific link mode. */
2940                 if (tp->link_config.speed == SPEED_1000) {
2941                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2942
2943                         if (tp->link_config.duplex == DUPLEX_FULL)
2944                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2945                         else
2946                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2947                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2948                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2949                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2950                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2951                 } else {
2952                         if (tp->link_config.speed == SPEED_100) {
2953                                 if (tp->link_config.duplex == DUPLEX_FULL)
2954                                         new_adv |= ADVERTISE_100FULL;
2955                                 else
2956                                         new_adv |= ADVERTISE_100HALF;
2957                         } else {
2958                                 if (tp->link_config.duplex == DUPLEX_FULL)
2959                                         new_adv |= ADVERTISE_10FULL;
2960                                 else
2961                                         new_adv |= ADVERTISE_10HALF;
2962                         }
2963                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2964
2965                         new_adv = 0;
2966                 }
2967
2968                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2969         }
2970
2971         if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
2972                 u32 val = 0;
2973
2974                 tw32(TG3_CPMU_EEE_MODE,
2975                      tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2976
2977                 /* Enable SM_DSP clock and tx 6dB coding. */
2978                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
2979                       MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
2980                       MII_TG3_AUXCTL_ACTL_TX_6DB;
2981                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2982
2983                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2984                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
2985                     !tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
2986                         tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2,
2987                                          val | MII_TG3_DSP_CH34TP2_HIBW01);
2988
2989                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2990                         /* Advertise 100-BaseTX EEE ability */
2991                         if (tp->link_config.advertising &
2992                             (ADVERTISED_100baseT_Half |
2993                              ADVERTISED_100baseT_Full))
2994                                 val |= TG3_CL45_D7_EEEADV_CAP_100TX;
2995                         /* Advertise 1000-BaseT EEE ability */
2996                         if (tp->link_config.advertising &
2997                             (ADVERTISED_1000baseT_Half |
2998                              ADVERTISED_1000baseT_Full))
2999                                 val |= TG3_CL45_D7_EEEADV_CAP_1000T;
3000                 }
3001                 tg3_phy_cl45_write(tp, 0x7, TG3_CL45_D7_EEEADV_CAP, val);
3002
3003                 /* Turn off SM_DSP clock. */
3004                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
3005                       MII_TG3_AUXCTL_ACTL_TX_6DB;
3006                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3007         }
3008
3009         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
3010             tp->link_config.speed != SPEED_INVALID) {
3011                 u32 bmcr, orig_bmcr;
3012
3013                 tp->link_config.active_speed = tp->link_config.speed;
3014                 tp->link_config.active_duplex = tp->link_config.duplex;
3015
3016                 bmcr = 0;
3017                 switch (tp->link_config.speed) {
3018                 default:
3019                 case SPEED_10:
3020                         break;
3021
3022                 case SPEED_100:
3023                         bmcr |= BMCR_SPEED100;
3024                         break;
3025
3026                 case SPEED_1000:
3027                         bmcr |= TG3_BMCR_SPEED1000;
3028                         break;
3029                 }
3030
3031                 if (tp->link_config.duplex == DUPLEX_FULL)
3032                         bmcr |= BMCR_FULLDPLX;
3033
3034                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
3035                     (bmcr != orig_bmcr)) {
3036                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
3037                         for (i = 0; i < 1500; i++) {
3038                                 u32 tmp;
3039
3040                                 udelay(10);
3041                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
3042                                     tg3_readphy(tp, MII_BMSR, &tmp))
3043                                         continue;
3044                                 if (!(tmp & BMSR_LSTATUS)) {
3045                                         udelay(40);
3046                                         break;
3047                                 }
3048                         }
3049                         tg3_writephy(tp, MII_BMCR, bmcr);
3050                         udelay(40);
3051                 }
3052         } else {
3053                 tg3_writephy(tp, MII_BMCR,
3054                              BMCR_ANENABLE | BMCR_ANRESTART);
3055         }
3056 }
3057
3058 static int tg3_init_5401phy_dsp(struct tg3 *tp)
3059 {
3060         int err;
3061
3062         /* Turn off tap power management. */
3063         /* Set Extended packet length bit */
3064         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
3065
3066         err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
3067         err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
3068         err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
3069         err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
3070         err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
3071
3072         udelay(40);
3073
3074         return err;
3075 }
3076
3077 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
3078 {
3079         u32 adv_reg, all_mask = 0;
3080
3081         if (mask & ADVERTISED_10baseT_Half)
3082                 all_mask |= ADVERTISE_10HALF;
3083         if (mask & ADVERTISED_10baseT_Full)
3084                 all_mask |= ADVERTISE_10FULL;
3085         if (mask & ADVERTISED_100baseT_Half)
3086                 all_mask |= ADVERTISE_100HALF;
3087         if (mask & ADVERTISED_100baseT_Full)
3088                 all_mask |= ADVERTISE_100FULL;
3089
3090         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3091                 return 0;
3092
3093         if ((adv_reg & all_mask) != all_mask)
3094                 return 0;
3095         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3096                 u32 tg3_ctrl;
3097
3098                 all_mask = 0;
3099                 if (mask & ADVERTISED_1000baseT_Half)
3100                         all_mask |= ADVERTISE_1000HALF;
3101                 if (mask & ADVERTISED_1000baseT_Full)
3102                         all_mask |= ADVERTISE_1000FULL;
3103
3104                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3105                         return 0;
3106
3107                 if ((tg3_ctrl & all_mask) != all_mask)
3108                         return 0;
3109         }
3110         return 1;
3111 }
3112
3113 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3114 {
3115         u32 curadv, reqadv;
3116
3117         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3118                 return 1;
3119
3120         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3121         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3122
3123         if (tp->link_config.active_duplex == DUPLEX_FULL) {
3124                 if (curadv != reqadv)
3125                         return 0;
3126
3127                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3128                         tg3_readphy(tp, MII_LPA, rmtadv);
3129         } else {
3130                 /* Reprogram the advertisement register, even if it
3131                  * does not affect the current link.  If the link
3132                  * gets renegotiated in the future, we can save an
3133                  * additional renegotiation cycle by advertising
3134                  * it correctly in the first place.
3135                  */
3136                 if (curadv != reqadv) {
3137                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3138                                      ADVERTISE_PAUSE_ASYM);
3139                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3140                 }
3141         }
3142
3143         return 1;
3144 }
3145
3146 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3147 {
3148         int current_link_up;
3149         u32 bmsr, val;
3150         u32 lcl_adv, rmt_adv;
3151         u16 current_speed;
3152         u8 current_duplex;
3153         int i, err;
3154
3155         tw32(MAC_EVENT, 0);
3156
3157         tw32_f(MAC_STATUS,
3158              (MAC_STATUS_SYNC_CHANGED |
3159               MAC_STATUS_CFG_CHANGED |
3160               MAC_STATUS_MI_COMPLETION |
3161               MAC_STATUS_LNKSTATE_CHANGED));
3162         udelay(40);
3163
3164         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3165                 tw32_f(MAC_MI_MODE,
3166                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3167                 udelay(80);
3168         }
3169
3170         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3171
3172         /* Some third-party PHYs need to be reset on link going
3173          * down.
3174          */
3175         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3176              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3177              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3178             netif_carrier_ok(tp->dev)) {
3179                 tg3_readphy(tp, MII_BMSR, &bmsr);
3180                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3181                     !(bmsr & BMSR_LSTATUS))
3182                         force_reset = 1;
3183         }
3184         if (force_reset)
3185                 tg3_phy_reset(tp);
3186
3187         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3188                 tg3_readphy(tp, MII_BMSR, &bmsr);
3189                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3190                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3191                         bmsr = 0;
3192
3193                 if (!(bmsr & BMSR_LSTATUS)) {
3194                         err = tg3_init_5401phy_dsp(tp);
3195                         if (err)
3196                                 return err;
3197
3198                         tg3_readphy(tp, MII_BMSR, &bmsr);
3199                         for (i = 0; i < 1000; i++) {
3200                                 udelay(10);
3201                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3202                                     (bmsr & BMSR_LSTATUS)) {
3203                                         udelay(40);
3204                                         break;
3205                                 }
3206                         }
3207
3208                         if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3209                             TG3_PHY_REV_BCM5401_B0 &&
3210                             !(bmsr & BMSR_LSTATUS) &&
3211                             tp->link_config.active_speed == SPEED_1000) {
3212                                 err = tg3_phy_reset(tp);
3213                                 if (!err)
3214                                         err = tg3_init_5401phy_dsp(tp);
3215                                 if (err)
3216                                         return err;
3217                         }
3218                 }
3219         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3220                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3221                 /* 5701 {A0,B0} CRC bug workaround */
3222                 tg3_writephy(tp, 0x15, 0x0a75);
3223                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3224                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3225                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3226         }
3227
3228         /* Clear pending interrupts... */
3229         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3230         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3231
3232         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3233                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3234         else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3235                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3236
3237         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3238             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3239                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3240                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3241                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3242                 else
3243                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3244         }
3245
3246         current_link_up = 0;
3247         current_speed = SPEED_INVALID;
3248         current_duplex = DUPLEX_INVALID;
3249
3250         if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3251                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3252                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3253                 if (!(val & (1 << 10))) {
3254                         val |= (1 << 10);
3255                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3256                         goto relink;
3257                 }
3258         }
3259
3260         bmsr = 0;
3261         for (i = 0; i < 100; i++) {
3262                 tg3_readphy(tp, MII_BMSR, &bmsr);
3263                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3264                     (bmsr & BMSR_LSTATUS))
3265                         break;
3266                 udelay(40);
3267         }
3268
3269         if (bmsr & BMSR_LSTATUS) {
3270                 u32 aux_stat, bmcr;
3271
3272                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3273                 for (i = 0; i < 2000; i++) {
3274                         udelay(10);
3275                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3276                             aux_stat)
3277                                 break;
3278                 }
3279
3280                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3281                                              &current_speed,
3282                                              &current_duplex);
3283
3284                 bmcr = 0;
3285                 for (i = 0; i < 200; i++) {
3286                         tg3_readphy(tp, MII_BMCR, &bmcr);
3287                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3288                                 continue;
3289                         if (bmcr && bmcr != 0x7fff)
3290                                 break;
3291                         udelay(10);
3292                 }
3293
3294                 lcl_adv = 0;
3295                 rmt_adv = 0;
3296
3297                 tp->link_config.active_speed = current_speed;
3298                 tp->link_config.active_duplex = current_duplex;
3299
3300                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3301                         if ((bmcr & BMCR_ANENABLE) &&
3302                             tg3_copper_is_advertising_all(tp,
3303                                                 tp->link_config.advertising)) {
3304                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3305                                                                   &rmt_adv))
3306                                         current_link_up = 1;
3307                         }
3308                 } else {
3309                         if (!(bmcr & BMCR_ANENABLE) &&
3310                             tp->link_config.speed == current_speed &&
3311                             tp->link_config.duplex == current_duplex &&
3312                             tp->link_config.flowctrl ==
3313                             tp->link_config.active_flowctrl) {
3314                                 current_link_up = 1;
3315                         }
3316                 }
3317
3318                 if (current_link_up == 1 &&
3319                     tp->link_config.active_duplex == DUPLEX_FULL)
3320                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3321         }
3322
3323 relink:
3324         if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3325                 tg3_phy_copper_begin(tp);
3326
3327                 tg3_readphy(tp, MII_BMSR, &bmsr);
3328                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3329                     (bmsr & BMSR_LSTATUS))
3330                         current_link_up = 1;
3331         }
3332
3333         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3334         if (current_link_up == 1) {
3335                 if (tp->link_config.active_speed == SPEED_100 ||
3336                     tp->link_config.active_speed == SPEED_10)
3337                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3338                 else
3339                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3340         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
3341                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3342         else
3343                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3344
3345         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3346         if (tp->link_config.active_duplex == DUPLEX_HALF)
3347                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3348
3349         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3350                 if (current_link_up == 1 &&
3351                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3352                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3353                 else
3354                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3355         }
3356
3357         /* ??? Without this setting Netgear GA302T PHY does not
3358          * ??? send/receive packets...
3359          */
3360         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3361             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3362                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3363                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3364                 udelay(80);
3365         }
3366
3367         tw32_f(MAC_MODE, tp->mac_mode);
3368         udelay(40);
3369
3370         tg3_phy_eee_adjust(tp, current_link_up);
3371
3372         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3373                 /* Polled via timer. */
3374                 tw32_f(MAC_EVENT, 0);
3375         } else {
3376                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3377         }
3378         udelay(40);
3379
3380         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3381             current_link_up == 1 &&
3382             tp->link_config.active_speed == SPEED_1000 &&
3383             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3384              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3385                 udelay(120);
3386                 tw32_f(MAC_STATUS,
3387                      (MAC_STATUS_SYNC_CHANGED |
3388                       MAC_STATUS_CFG_CHANGED));
3389                 udelay(40);
3390                 tg3_write_mem(tp,
3391                               NIC_SRAM_FIRMWARE_MBOX,
3392                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3393         }
3394
3395         /* Prevent send BD corruption. */
3396         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3397                 u16 oldlnkctl, newlnkctl;
3398
3399                 pci_read_config_word(tp->pdev,
3400                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3401                                      &oldlnkctl);
3402                 if (tp->link_config.active_speed == SPEED_100 ||
3403                     tp->link_config.active_speed == SPEED_10)
3404                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3405                 else
3406                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3407                 if (newlnkctl != oldlnkctl)
3408                         pci_write_config_word(tp->pdev,
3409                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3410                                               newlnkctl);
3411         }
3412
3413         if (current_link_up != netif_carrier_ok(tp->dev)) {
3414                 if (current_link_up)
3415                         netif_carrier_on(tp->dev);
3416                 else
3417                         netif_carrier_off(tp->dev);
3418                 tg3_link_report(tp);
3419         }
3420
3421         return 0;
3422 }
3423
3424 struct tg3_fiber_aneginfo {
3425         int state;
3426 #define ANEG_STATE_UNKNOWN              0
3427 #define ANEG_STATE_AN_ENABLE            1
3428 #define ANEG_STATE_RESTART_INIT         2
3429 #define ANEG_STATE_RESTART              3
3430 #define ANEG_STATE_DISABLE_LINK_OK      4
3431 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3432 #define ANEG_STATE_ABILITY_DETECT       6
3433 #define ANEG_STATE_ACK_DETECT_INIT      7
3434 #define ANEG_STATE_ACK_DETECT           8
3435 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3436 #define ANEG_STATE_COMPLETE_ACK         10
3437 #define ANEG_STATE_IDLE_DETECT_INIT     11
3438 #define ANEG_STATE_IDLE_DETECT          12
3439 #define ANEG_STATE_LINK_OK              13
3440 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3441 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3442
3443         u32 flags;
3444 #define MR_AN_ENABLE            0x00000001
3445 #define MR_RESTART_AN           0x00000002
3446 #define MR_AN_COMPLETE          0x00000004
3447 #define MR_PAGE_RX              0x00000008
3448 #define MR_NP_LOADED            0x00000010
3449 #define MR_TOGGLE_TX            0x00000020
3450 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3451 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3452 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3453 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3454 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3455 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3456 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3457 #define MR_TOGGLE_RX            0x00002000
3458 #define MR_NP_RX                0x00004000
3459
3460 #define MR_LINK_OK              0x80000000
3461
3462         unsigned long link_time, cur_time;
3463
3464         u32 ability_match_cfg;
3465         int ability_match_count;
3466
3467         char ability_match, idle_match, ack_match;
3468
3469         u32 txconfig, rxconfig;
3470 #define ANEG_CFG_NP             0x00000080
3471 #define ANEG_CFG_ACK            0x00000040
3472 #define ANEG_CFG_RF2            0x00000020
3473 #define ANEG_CFG_RF1            0x00000010
3474 #define ANEG_CFG_PS2            0x00000001
3475 #define ANEG_CFG_PS1            0x00008000
3476 #define ANEG_CFG_HD             0x00004000
3477 #define ANEG_CFG_FD             0x00002000
3478 #define ANEG_CFG_INVAL          0x00001f06
3479
3480 };
3481 #define ANEG_OK         0
3482 #define ANEG_DONE       1
3483 #define ANEG_TIMER_ENAB 2
3484 #define ANEG_FAILED     -1
3485
3486 #define ANEG_STATE_SETTLE_TIME  10000
3487
3488 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3489                                    struct tg3_fiber_aneginfo *ap)
3490 {
3491         u16 flowctrl;
3492         unsigned long delta;
3493         u32 rx_cfg_reg;
3494         int ret;
3495
3496         if (ap->state == ANEG_STATE_UNKNOWN) {
3497                 ap->rxconfig = 0;
3498                 ap->link_time = 0;
3499                 ap->cur_time = 0;
3500                 ap->ability_match_cfg = 0;
3501                 ap->ability_match_count = 0;
3502                 ap->ability_match = 0;
3503                 ap->idle_match = 0;
3504                 ap->ack_match = 0;
3505         }
3506         ap->cur_time++;
3507
3508         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3509                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3510
3511                 if (rx_cfg_reg != ap->ability_match_cfg) {
3512                         ap->ability_match_cfg = rx_cfg_reg;
3513                         ap->ability_match = 0;
3514                         ap->ability_match_count = 0;
3515                 } else {
3516                         if (++ap->ability_match_count > 1) {
3517                                 ap->ability_match = 1;
3518                                 ap->ability_match_cfg = rx_cfg_reg;
3519                         }
3520                 }
3521                 if (rx_cfg_reg & ANEG_CFG_ACK)
3522                         ap->ack_match = 1;
3523                 else
3524                         ap->ack_match = 0;
3525
3526                 ap->idle_match = 0;
3527         } else {
3528                 ap->idle_match = 1;
3529                 ap->ability_match_cfg = 0;
3530                 ap->ability_match_count = 0;
3531                 ap->ability_match = 0;
3532                 ap->ack_match = 0;
3533
3534                 rx_cfg_reg = 0;
3535         }
3536
3537         ap->rxconfig = rx_cfg_reg;
3538         ret = ANEG_OK;
3539
3540         switch (ap->state) {
3541         case ANEG_STATE_UNKNOWN:
3542                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3543                         ap->state = ANEG_STATE_AN_ENABLE;
3544
3545                 /* fallthru */
3546         case ANEG_STATE_AN_ENABLE:
3547                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3548                 if (ap->flags & MR_AN_ENABLE) {
3549                         ap->link_time = 0;
3550                         ap->cur_time = 0;
3551                         ap->ability_match_cfg = 0;
3552                         ap->ability_match_count = 0;
3553                         ap->ability_match = 0;
3554                         ap->idle_match = 0;
3555                         ap->ack_match = 0;
3556
3557                         ap->state = ANEG_STATE_RESTART_INIT;
3558                 } else {
3559                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3560                 }
3561                 break;
3562
3563         case ANEG_STATE_RESTART_INIT:
3564                 ap->link_time = ap->cur_time;
3565                 ap->flags &= ~(MR_NP_LOADED);
3566                 ap->txconfig = 0;
3567                 tw32(MAC_TX_AUTO_NEG, 0);
3568                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3569                 tw32_f(MAC_MODE, tp->mac_mode);
3570                 udelay(40);
3571
3572                 ret = ANEG_TIMER_ENAB;
3573                 ap->state = ANEG_STATE_RESTART;
3574
3575                 /* fallthru */
3576         case ANEG_STATE_RESTART:
3577                 delta = ap->cur_time - ap->link_time;
3578                 if (delta > ANEG_STATE_SETTLE_TIME)
3579                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3580                 else
3581                         ret = ANEG_TIMER_ENAB;
3582                 break;
3583
3584         case ANEG_STATE_DISABLE_LINK_OK:
3585                 ret = ANEG_DONE;
3586                 break;
3587
3588         case ANEG_STATE_ABILITY_DETECT_INIT:
3589                 ap->flags &= ~(MR_TOGGLE_TX);
3590                 ap->txconfig = ANEG_CFG_FD;
3591                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3592                 if (flowctrl & ADVERTISE_1000XPAUSE)
3593                         ap->txconfig |= ANEG_CFG_PS1;
3594                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3595                         ap->txconfig |= ANEG_CFG_PS2;
3596                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3597                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3598                 tw32_f(MAC_MODE, tp->mac_mode);
3599                 udelay(40);
3600
3601                 ap->state = ANEG_STATE_ABILITY_DETECT;
3602                 break;
3603
3604         case ANEG_STATE_ABILITY_DETECT:
3605                 if (ap->ability_match != 0 && ap->rxconfig != 0)
3606                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3607                 break;
3608
3609         case ANEG_STATE_ACK_DETECT_INIT:
3610                 ap->txconfig |= ANEG_CFG_ACK;
3611                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3612                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3613                 tw32_f(MAC_MODE, tp->mac_mode);
3614                 udelay(40);
3615
3616                 ap->state = ANEG_STATE_ACK_DETECT;
3617
3618                 /* fallthru */
3619         case ANEG_STATE_ACK_DETECT:
3620                 if (ap->ack_match != 0) {
3621                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3622                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3623                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3624                         } else {
3625                                 ap->state = ANEG_STATE_AN_ENABLE;
3626                         }
3627                 } else if (ap->ability_match != 0 &&
3628                            ap->rxconfig == 0) {
3629                         ap->state = ANEG_STATE_AN_ENABLE;
3630                 }
3631                 break;
3632
3633         case ANEG_STATE_COMPLETE_ACK_INIT:
3634                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3635                         ret = ANEG_FAILED;
3636                         break;
3637                 }
3638                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3639                                MR_LP_ADV_HALF_DUPLEX |
3640                                MR_LP_ADV_SYM_PAUSE |
3641                                MR_LP_ADV_ASYM_PAUSE |
3642                                MR_LP_ADV_REMOTE_FAULT1 |
3643                                MR_LP_ADV_REMOTE_FAULT2 |
3644                                MR_LP_ADV_NEXT_PAGE |
3645                                MR_TOGGLE_RX |
3646                                MR_NP_RX);
3647                 if (ap->rxconfig & ANEG_CFG_FD)
3648                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3649                 if (ap->rxconfig & ANEG_CFG_HD)
3650                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3651                 if (ap->rxconfig & ANEG_CFG_PS1)
3652                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3653                 if (ap->rxconfig & ANEG_CFG_PS2)
3654                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3655                 if (ap->rxconfig & ANEG_CFG_RF1)
3656                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3657                 if (ap->rxconfig & ANEG_CFG_RF2)
3658                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3659                 if (ap->rxconfig & ANEG_CFG_NP)
3660                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3661
3662                 ap->link_time = ap->cur_time;
3663
3664                 ap->flags ^= (MR_TOGGLE_TX);
3665                 if (ap->rxconfig & 0x0008)
3666                         ap->flags |= MR_TOGGLE_RX;
3667                 if (ap->rxconfig & ANEG_CFG_NP)
3668                         ap->flags |= MR_NP_RX;
3669                 ap->flags |= MR_PAGE_RX;
3670
3671                 ap->state = ANEG_STATE_COMPLETE_ACK;
3672                 ret = ANEG_TIMER_ENAB;
3673                 break;
3674
3675         case ANEG_STATE_COMPLETE_ACK:
3676                 if (ap->ability_match != 0 &&
3677                     ap->rxconfig == 0) {
3678                         ap->state = ANEG_STATE_AN_ENABLE;
3679                         break;
3680                 }
3681                 delta = ap->cur_time - ap->link_time;
3682                 if (delta > ANEG_STATE_SETTLE_TIME) {
3683                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3684                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3685                         } else {
3686                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3687                                     !(ap->flags & MR_NP_RX)) {
3688                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3689                                 } else {
3690                                         ret = ANEG_FAILED;
3691                                 }
3692                         }
3693                 }
3694                 break;
3695
3696         case ANEG_STATE_IDLE_DETECT_INIT:
3697                 ap->link_time = ap->cur_time;
3698                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3699                 tw32_f(MAC_MODE, tp->mac_mode);
3700                 udelay(40);
3701
3702                 ap->state = ANEG_STATE_IDLE_DETECT;
3703                 ret = ANEG_TIMER_ENAB;
3704                 break;
3705
3706         case ANEG_STATE_IDLE_DETECT:
3707                 if (ap->ability_match != 0 &&
3708                     ap->rxconfig == 0) {
3709                         ap->state = ANEG_STATE_AN_ENABLE;
3710                         break;
3711                 }
3712                 delta = ap->cur_time - ap->link_time;
3713                 if (delta > ANEG_STATE_SETTLE_TIME) {
3714                         /* XXX another gem from the Broadcom driver :( */
3715                         ap->state = ANEG_STATE_LINK_OK;
3716                 }
3717                 break;
3718
3719         case ANEG_STATE_LINK_OK:
3720                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3721                 ret = ANEG_DONE;
3722                 break;
3723
3724         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3725                 /* ??? unimplemented */
3726                 break;
3727
3728         case ANEG_STATE_NEXT_PAGE_WAIT:
3729                 /* ??? unimplemented */
3730                 break;
3731
3732         default:
3733                 ret = ANEG_FAILED;
3734                 break;
3735         }
3736
3737         return ret;
3738 }
3739
3740 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3741 {
3742         int res = 0;
3743         struct tg3_fiber_aneginfo aninfo;
3744         int status = ANEG_FAILED;
3745         unsigned int tick;
3746         u32 tmp;
3747
3748         tw32_f(MAC_TX_AUTO_NEG, 0);
3749
3750         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3751         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3752         udelay(40);
3753
3754         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3755         udelay(40);
3756
3757         memset(&aninfo, 0, sizeof(aninfo));
3758         aninfo.flags |= MR_AN_ENABLE;
3759         aninfo.state = ANEG_STATE_UNKNOWN;
3760         aninfo.cur_time = 0;
3761         tick = 0;
3762         while (++tick < 195000) {
3763                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3764                 if (status == ANEG_DONE || status == ANEG_FAILED)
3765                         break;
3766
3767                 udelay(1);
3768         }
3769
3770         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3771         tw32_f(MAC_MODE, tp->mac_mode);
3772         udelay(40);
3773
3774         *txflags = aninfo.txconfig;
3775         *rxflags = aninfo.flags;
3776
3777         if (status == ANEG_DONE &&
3778             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3779                              MR_LP_ADV_FULL_DUPLEX)))
3780                 res = 1;
3781
3782         return res;
3783 }
3784
3785 static void tg3_init_bcm8002(struct tg3 *tp)
3786 {
3787         u32 mac_status = tr32(MAC_STATUS);
3788         int i;
3789
3790         /* Reset when initting first time or we have a link. */
3791         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3792             !(mac_status & MAC_STATUS_PCS_SYNCED))
3793                 return;
3794
3795         /* Set PLL lock range. */
3796         tg3_writephy(tp, 0x16, 0x8007);
3797
3798         /* SW reset */
3799         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3800
3801         /* Wait for reset to complete. */
3802         /* XXX schedule_timeout() ... */
3803         for (i = 0; i < 500; i++)
3804                 udelay(10);
3805
3806         /* Config mode; select PMA/Ch 1 regs. */
3807         tg3_writephy(tp, 0x10, 0x8411);
3808
3809         /* Enable auto-lock and comdet, select txclk for tx. */
3810         tg3_writephy(tp, 0x11, 0x0a10);
3811
3812         tg3_writephy(tp, 0x18, 0x00a0);
3813         tg3_writephy(tp, 0x16, 0x41ff);
3814
3815         /* Assert and deassert POR. */
3816         tg3_writephy(tp, 0x13, 0x0400);
3817         udelay(40);
3818         tg3_writephy(tp, 0x13, 0x0000);
3819
3820         tg3_writephy(tp, 0x11, 0x0a50);
3821         udelay(40);
3822         tg3_writephy(tp, 0x11, 0x0a10);
3823
3824         /* Wait for signal to stabilize */
3825         /* XXX schedule_timeout() ... */
3826         for (i = 0; i < 15000; i++)
3827                 udelay(10);
3828
3829         /* Deselect the channel register so we can read the PHYID
3830          * later.
3831          */
3832         tg3_writephy(tp, 0x10, 0x8011);
3833 }
3834
3835 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3836 {
3837         u16 flowctrl;
3838         u32 sg_dig_ctrl, sg_dig_status;
3839         u32 serdes_cfg, expected_sg_dig_ctrl;
3840         int workaround, port_a;
3841         int current_link_up;
3842
3843         serdes_cfg = 0;
3844         expected_sg_dig_ctrl = 0;
3845         workaround = 0;
3846         port_a = 1;
3847         current_link_up = 0;
3848
3849         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3850             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3851                 workaround = 1;
3852                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3853                         port_a = 0;
3854
3855                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3856                 /* preserve bits 20-23 for voltage regulator */
3857                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3858         }
3859
3860         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3861
3862         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3863                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3864                         if (workaround) {
3865                                 u32 val = serdes_cfg;
3866
3867                                 if (port_a)
3868                                         val |= 0xc010000;
3869                                 else
3870                                         val |= 0x4010000;
3871                                 tw32_f(MAC_SERDES_CFG, val);
3872                         }
3873
3874                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3875                 }
3876                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3877                         tg3_setup_flow_control(tp, 0, 0);
3878                         current_link_up = 1;
3879                 }
3880                 goto out;
3881         }
3882
3883         /* Want auto-negotiation.  */
3884         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3885
3886         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3887         if (flowctrl & ADVERTISE_1000XPAUSE)
3888                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3889         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3890                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3891
3892         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3893                 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3894                     tp->serdes_counter &&
3895                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3896                                     MAC_STATUS_RCVD_CFG)) ==
3897                      MAC_STATUS_PCS_SYNCED)) {
3898                         tp->serdes_counter--;
3899                         current_link_up = 1;
3900                         goto out;
3901                 }
3902 restart_autoneg:
3903                 if (workaround)
3904                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3905                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3906                 udelay(5);
3907                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3908
3909                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3910                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3911         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3912                                  MAC_STATUS_SIGNAL_DET)) {
3913                 sg_dig_status = tr32(SG_DIG_STATUS);
3914                 mac_status = tr32(MAC_STATUS);
3915
3916                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3917                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3918                         u32 local_adv = 0, remote_adv = 0;
3919
3920                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3921                                 local_adv |= ADVERTISE_1000XPAUSE;
3922                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3923                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3924
3925                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3926                                 remote_adv |= LPA_1000XPAUSE;
3927                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3928                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3929
3930                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3931                         current_link_up = 1;
3932                         tp->serdes_counter = 0;
3933                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3934                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3935                         if (tp->serdes_counter)
3936                                 tp->serdes_counter--;
3937                         else {
3938                                 if (workaround) {
3939                                         u32 val = serdes_cfg;
3940
3941                                         if (port_a)
3942                                                 val |= 0xc010000;
3943                                         else
3944                                                 val |= 0x4010000;
3945
3946                                         tw32_f(MAC_SERDES_CFG, val);
3947                                 }
3948
3949                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3950                                 udelay(40);
3951
3952                                 /* Link parallel detection - link is up */
3953                                 /* only if we have PCS_SYNC and not */
3954                                 /* receiving config code words */
3955                                 mac_status = tr32(MAC_STATUS);
3956                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3957                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3958                                         tg3_setup_flow_control(tp, 0, 0);
3959                                         current_link_up = 1;
3960                                         tp->phy_flags |=
3961                                                 TG3_PHYFLG_PARALLEL_DETECT;
3962                                         tp->serdes_counter =
3963                                                 SERDES_PARALLEL_DET_TIMEOUT;
3964                                 } else
3965                                         goto restart_autoneg;
3966                         }
3967                 }
3968         } else {
3969                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3970                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3971         }
3972
3973 out:
3974         return current_link_up;
3975 }
3976
3977 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3978 {
3979         int current_link_up = 0;
3980
3981         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3982                 goto out;
3983
3984         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3985                 u32 txflags, rxflags;
3986                 int i;
3987
3988                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3989                         u32 local_adv = 0, remote_adv = 0;
3990
3991                         if (txflags & ANEG_CFG_PS1)
3992                                 local_adv |= ADVERTISE_1000XPAUSE;
3993                         if (txflags & ANEG_CFG_PS2)
3994                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3995
3996                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3997                                 remote_adv |= LPA_1000XPAUSE;
3998                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3999                                 remote_adv |= LPA_1000XPAUSE_ASYM;
4000
4001                         tg3_setup_flow_control(tp, local_adv, remote_adv);
4002
4003                         current_link_up = 1;
4004                 }
4005                 for (i = 0; i < 30; i++) {
4006                         udelay(20);
4007                         tw32_f(MAC_STATUS,
4008                                (MAC_STATUS_SYNC_CHANGED |
4009                                 MAC_STATUS_CFG_CHANGED));
4010                         udelay(40);
4011                         if ((tr32(MAC_STATUS) &
4012                              (MAC_STATUS_SYNC_CHANGED |
4013                               MAC_STATUS_CFG_CHANGED)) == 0)
4014                                 break;
4015                 }
4016
4017                 mac_status = tr32(MAC_STATUS);
4018                 if (current_link_up == 0 &&
4019                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
4020                     !(mac_status & MAC_STATUS_RCVD_CFG))
4021                         current_link_up = 1;
4022         } else {
4023                 tg3_setup_flow_control(tp, 0, 0);
4024
4025                 /* Forcing 1000FD link up. */
4026                 current_link_up = 1;
4027
4028                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
4029                 udelay(40);
4030
4031                 tw32_f(MAC_MODE, tp->mac_mode);
4032                 udelay(40);
4033         }
4034
4035 out:
4036         return current_link_up;
4037 }
4038
4039 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
4040 {
4041         u32 orig_pause_cfg;
4042         u16 orig_active_speed;
4043         u8 orig_active_duplex;
4044         u32 mac_status;
4045         int current_link_up;
4046         int i;
4047
4048         orig_pause_cfg = tp->link_config.active_flowctrl;
4049         orig_active_speed = tp->link_config.active_speed;
4050         orig_active_duplex = tp->link_config.active_duplex;
4051
4052         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
4053             netif_carrier_ok(tp->dev) &&
4054             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
4055                 mac_status = tr32(MAC_STATUS);
4056                 mac_status &= (MAC_STATUS_PCS_SYNCED |
4057                                MAC_STATUS_SIGNAL_DET |
4058                                MAC_STATUS_CFG_CHANGED |
4059                                MAC_STATUS_RCVD_CFG);
4060                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
4061                                    MAC_STATUS_SIGNAL_DET)) {
4062                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4063                                             MAC_STATUS_CFG_CHANGED));
4064                         return 0;
4065                 }
4066         }
4067
4068         tw32_f(MAC_TX_AUTO_NEG, 0);
4069
4070         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
4071         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
4072         tw32_f(MAC_MODE, tp->mac_mode);
4073         udelay(40);
4074
4075         if (tp->phy_id == TG3_PHY_ID_BCM8002)
4076                 tg3_init_bcm8002(tp);
4077
4078         /* Enable link change event even when serdes polling.  */
4079         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4080         udelay(40);
4081
4082         current_link_up = 0;
4083         mac_status = tr32(MAC_STATUS);
4084
4085         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
4086                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4087         else
4088                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4089
4090         tp->napi[0].hw_status->status =
4091                 (SD_STATUS_UPDATED |
4092                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4093
4094         for (i = 0; i < 100; i++) {
4095                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4096                                     MAC_STATUS_CFG_CHANGED));
4097                 udelay(5);
4098                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4099                                          MAC_STATUS_CFG_CHANGED |
4100                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4101                         break;
4102         }
4103
4104         mac_status = tr32(MAC_STATUS);
4105         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4106                 current_link_up = 0;
4107                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4108                     tp->serdes_counter == 0) {
4109                         tw32_f(MAC_MODE, (tp->mac_mode |
4110                                           MAC_MODE_SEND_CONFIGS));
4111                         udelay(1);
4112                         tw32_f(MAC_MODE, tp->mac_mode);
4113                 }
4114         }
4115
4116         if (current_link_up == 1) {
4117                 tp->link_config.active_speed = SPEED_1000;
4118                 tp->link_config.active_duplex = DUPLEX_FULL;
4119                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4120                                     LED_CTRL_LNKLED_OVERRIDE |
4121                                     LED_CTRL_1000MBPS_ON));
4122         } else {
4123                 tp->link_config.active_speed = SPEED_INVALID;
4124                 tp->link_config.active_duplex = DUPLEX_INVALID;
4125                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4126                                     LED_CTRL_LNKLED_OVERRIDE |
4127                                     LED_CTRL_TRAFFIC_OVERRIDE));
4128         }
4129
4130         if (current_link_up != netif_carrier_ok(tp->dev)) {
4131                 if (current_link_up)
4132                         netif_carrier_on(tp->dev);
4133                 else
4134                         netif_carrier_off(tp->dev);
4135                 tg3_link_report(tp);
4136         } else {
4137                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4138                 if (orig_pause_cfg != now_pause_cfg ||
4139                     orig_active_speed != tp->link_config.active_speed ||
4140                     orig_active_duplex != tp->link_config.active_duplex)
4141                         tg3_link_report(tp);
4142         }
4143
4144         return 0;
4145 }
4146
4147 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4148 {
4149         int current_link_up, err = 0;
4150         u32 bmsr, bmcr;
4151         u16 current_speed;
4152         u8 current_duplex;
4153         u32 local_adv, remote_adv;
4154
4155         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4156         tw32_f(MAC_MODE, tp->mac_mode);
4157         udelay(40);
4158
4159         tw32(MAC_EVENT, 0);
4160
4161         tw32_f(MAC_STATUS,
4162              (MAC_STATUS_SYNC_CHANGED |
4163               MAC_STATUS_CFG_CHANGED |
4164               MAC_STATUS_MI_COMPLETION |
4165               MAC_STATUS_LNKSTATE_CHANGED));
4166         udelay(40);
4167
4168         if (force_reset)
4169                 tg3_phy_reset(tp);
4170
4171         current_link_up = 0;
4172         current_speed = SPEED_INVALID;
4173         current_duplex = DUPLEX_INVALID;
4174
4175         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4176         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4177         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4178                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4179                         bmsr |= BMSR_LSTATUS;
4180                 else
4181                         bmsr &= ~BMSR_LSTATUS;
4182         }
4183
4184         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4185
4186         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4187             (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4188                 /* do nothing, just check for link up at the end */
4189         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4190                 u32 adv, new_adv;
4191
4192                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4193                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4194                                   ADVERTISE_1000XPAUSE |
4195                                   ADVERTISE_1000XPSE_ASYM |
4196                                   ADVERTISE_SLCT);
4197
4198                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4199
4200                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4201                         new_adv |= ADVERTISE_1000XHALF;
4202                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4203                         new_adv |= ADVERTISE_1000XFULL;
4204
4205                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4206                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4207                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4208                         tg3_writephy(tp, MII_BMCR, bmcr);
4209
4210                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4211                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4212                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4213
4214                         return err;
4215                 }
4216         } else {
4217                 u32 new_bmcr;
4218
4219                 bmcr &= ~BMCR_SPEED1000;
4220                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4221
4222                 if (tp->link_config.duplex == DUPLEX_FULL)
4223                         new_bmcr |= BMCR_FULLDPLX;
4224
4225                 if (new_bmcr != bmcr) {
4226                         /* BMCR_SPEED1000 is a reserved bit that needs
4227                          * to be set on write.
4228                          */
4229                         new_bmcr |= BMCR_SPEED1000;
4230
4231                         /* Force a linkdown */
4232                         if (netif_carrier_ok(tp->dev)) {
4233                                 u32 adv;
4234
4235                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4236                                 adv &= ~(ADVERTISE_1000XFULL |
4237                                          ADVERTISE_1000XHALF |
4238                                          ADVERTISE_SLCT);
4239                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4240                                 tg3_writephy(tp, MII_BMCR, bmcr |
4241                                                            BMCR_ANRESTART |
4242                                                            BMCR_ANENABLE);
4243                                 udelay(10);
4244                                 netif_carrier_off(tp->dev);
4245                         }
4246                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4247                         bmcr = new_bmcr;
4248                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4249                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4250                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4251                             ASIC_REV_5714) {
4252                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4253                                         bmsr |= BMSR_LSTATUS;
4254                                 else
4255                                         bmsr &= ~BMSR_LSTATUS;
4256                         }
4257                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4258                 }
4259         }
4260
4261         if (bmsr & BMSR_LSTATUS) {
4262                 current_speed = SPEED_1000;
4263                 current_link_up = 1;
4264                 if (bmcr & BMCR_FULLDPLX)
4265                         current_duplex = DUPLEX_FULL;
4266                 else
4267                         current_duplex = DUPLEX_HALF;
4268
4269                 local_adv = 0;
4270                 remote_adv = 0;
4271
4272                 if (bmcr & BMCR_ANENABLE) {
4273                         u32 common;
4274
4275                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4276                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4277                         common = local_adv & remote_adv;
4278                         if (common & (ADVERTISE_1000XHALF |
4279                                       ADVERTISE_1000XFULL)) {
4280                                 if (common & ADVERTISE_1000XFULL)
4281                                         current_duplex = DUPLEX_FULL;
4282                                 else
4283                                         current_duplex = DUPLEX_HALF;
4284                         } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4285                                 /* Link is up via parallel detect */
4286                         } else {
4287                                 current_link_up = 0;
4288                         }
4289                 }
4290         }
4291
4292         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4293                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4294
4295         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4296         if (tp->link_config.active_duplex == DUPLEX_HALF)
4297                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4298
4299         tw32_f(MAC_MODE, tp->mac_mode);
4300         udelay(40);
4301
4302         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4303
4304         tp->link_config.active_speed = current_speed;
4305         tp->link_config.active_duplex = current_duplex;
4306
4307         if (current_link_up != netif_carrier_ok(tp->dev)) {
4308                 if (current_link_up)
4309                         netif_carrier_on(tp->dev);
4310                 else {
4311                         netif_carrier_off(tp->dev);
4312                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4313                 }
4314                 tg3_link_report(tp);
4315         }
4316         return err;
4317 }
4318
4319 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4320 {
4321         if (tp->serdes_counter) {
4322                 /* Give autoneg time to complete. */
4323                 tp->serdes_counter--;
4324                 return;
4325         }
4326
4327         if (!netif_carrier_ok(tp->dev) &&
4328             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4329                 u32 bmcr;
4330
4331                 tg3_readphy(tp, MII_BMCR, &bmcr);
4332                 if (bmcr & BMCR_ANENABLE) {
4333                         u32 phy1, phy2;
4334
4335                         /* Select shadow register 0x1f */
4336                         tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
4337                         tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
4338
4339                         /* Select expansion interrupt status register */
4340                         tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4341                                          MII_TG3_DSP_EXP1_INT_STAT);
4342                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4343                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4344
4345                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4346                                 /* We have signal detect and not receiving
4347                                  * config code words, link is up by parallel
4348                                  * detection.
4349                                  */
4350
4351                                 bmcr &= ~BMCR_ANENABLE;
4352                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4353                                 tg3_writephy(tp, MII_BMCR, bmcr);
4354                                 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
4355                         }
4356                 }
4357         } else if (netif_carrier_ok(tp->dev) &&
4358                    (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4359                    (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4360                 u32 phy2;
4361
4362                 /* Select expansion interrupt status register */
4363                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4364                                  MII_TG3_DSP_EXP1_INT_STAT);
4365                 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4366                 if (phy2 & 0x20) {
4367                         u32 bmcr;
4368
4369                         /* Config code words received, turn on autoneg. */
4370                         tg3_readphy(tp, MII_BMCR, &bmcr);
4371                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4372
4373                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4374
4375                 }
4376         }
4377 }
4378
4379 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4380 {
4381         int err;
4382
4383         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
4384                 err = tg3_setup_fiber_phy(tp, force_reset);
4385         else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4386                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4387         else
4388                 err = tg3_setup_copper_phy(tp, force_reset);
4389
4390         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4391                 u32 val, scale;
4392
4393                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4394                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4395                         scale = 65;
4396                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4397                         scale = 6;
4398                 else
4399                         scale = 12;
4400
4401                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4402                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4403                 tw32(GRC_MISC_CFG, val);
4404         }
4405
4406         if (tp->link_config.active_speed == SPEED_1000 &&
4407             tp->link_config.active_duplex == DUPLEX_HALF)
4408                 tw32(MAC_TX_LENGTHS,
4409                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4410                       (6 << TX_LENGTHS_IPG_SHIFT) |
4411                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4412         else
4413                 tw32(MAC_TX_LENGTHS,
4414                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4415                       (6 << TX_LENGTHS_IPG_SHIFT) |
4416                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4417
4418         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4419                 if (netif_carrier_ok(tp->dev)) {
4420                         tw32(HOSTCC_STAT_COAL_TICKS,
4421                              tp->coal.stats_block_coalesce_usecs);
4422                 } else {
4423                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4424                 }
4425         }
4426
4427         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4428                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4429                 if (!netif_carrier_ok(tp->dev))
4430                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4431                               tp->pwrmgmt_thresh;
4432                 else
4433                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4434                 tw32(PCIE_PWR_MGMT_THRESH, val);
4435         }
4436
4437         return err;
4438 }
4439
4440 static inline int tg3_irq_sync(struct tg3 *tp)
4441 {
4442         return tp->irq_sync;
4443 }
4444
4445 /* This is called whenever we suspect that the system chipset is re-
4446  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4447  * is bogus tx completions. We try to recover by setting the
4448  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4449  * in the workqueue.
4450  */
4451 static void tg3_tx_recover(struct tg3 *tp)
4452 {
4453         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4454                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4455
4456         netdev_warn(tp->dev,
4457                     "The system may be re-ordering memory-mapped I/O "
4458                     "cycles to the network device, attempting to recover. "
4459                     "Please report the problem to the driver maintainer "
4460                     "and include system chipset information.\n");
4461
4462         spin_lock(&tp->lock);
4463         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4464         spin_unlock(&tp->lock);
4465 }
4466
4467 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4468 {
4469         /* Tell compiler to fetch tx indices from memory. */
4470         barrier();
4471         return tnapi->tx_pending -
4472                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4473 }
4474
4475 /* Tigon3 never reports partial packet sends.  So we do not
4476  * need special logic to handle SKBs that have not had all
4477  * of their frags sent yet, like SunGEM does.
4478  */
4479 static void tg3_tx(struct tg3_napi *tnapi)
4480 {
4481         struct tg3 *tp = tnapi->tp;
4482         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4483         u32 sw_idx = tnapi->tx_cons;
4484         struct netdev_queue *txq;
4485         int index = tnapi - tp->napi;
4486
4487         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4488                 index--;
4489
4490         txq = netdev_get_tx_queue(tp->dev, index);
4491
4492         while (sw_idx != hw_idx) {
4493                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4494                 struct sk_buff *skb = ri->skb;
4495                 int i, tx_bug = 0;
4496
4497                 if (unlikely(skb == NULL)) {
4498                         tg3_tx_recover(tp);
4499                         return;
4500                 }
4501
4502                 pci_unmap_single(tp->pdev,
4503                                  dma_unmap_addr(ri, mapping),
4504                                  skb_headlen(skb),
4505                                  PCI_DMA_TODEVICE);
4506
4507                 ri->skb = NULL;
4508
4509                 sw_idx = NEXT_TX(sw_idx);
4510
4511                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4512                         ri = &tnapi->tx_buffers[sw_idx];
4513                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4514                                 tx_bug = 1;
4515
4516                         pci_unmap_page(tp->pdev,
4517                                        dma_unmap_addr(ri, mapping),
4518                                        skb_shinfo(skb)->frags[i].size,
4519                                        PCI_DMA_TODEVICE);
4520                         sw_idx = NEXT_TX(sw_idx);
4521                 }
4522
4523                 dev_kfree_skb(skb);
4524
4525                 if (unlikely(tx_bug)) {
4526                         tg3_tx_recover(tp);
4527                         return;
4528                 }
4529         }
4530
4531         tnapi->tx_cons = sw_idx;
4532
4533         /* Need to make the tx_cons update visible to tg3_start_xmit()
4534          * before checking for netif_queue_stopped().  Without the
4535          * memory barrier, there is a small possibility that tg3_start_xmit()
4536          * will miss it and cause the queue to be stopped forever.
4537          */
4538         smp_mb();
4539
4540         if (unlikely(netif_tx_queue_stopped(txq) &&
4541                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4542                 __netif_tx_lock(txq, smp_processor_id());
4543                 if (netif_tx_queue_stopped(txq) &&
4544                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4545                         netif_tx_wake_queue(txq);
4546                 __netif_tx_unlock(txq);
4547         }
4548 }
4549
4550 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4551 {
4552         if (!ri->skb)
4553                 return;
4554
4555         pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4556                          map_sz, PCI_DMA_FROMDEVICE);
4557         dev_kfree_skb_any(ri->skb);
4558         ri->skb = NULL;
4559 }
4560
4561 /* Returns size of skb allocated or < 0 on error.
4562  *
4563  * We only need to fill in the address because the other members
4564  * of the RX descriptor are invariant, see tg3_init_rings.
4565  *
4566  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4567  * posting buffers we only dirty the first cache line of the RX
4568  * descriptor (containing the address).  Whereas for the RX status
4569  * buffers the cpu only reads the last cacheline of the RX descriptor
4570  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4571  */
4572 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4573                             u32 opaque_key, u32 dest_idx_unmasked)
4574 {
4575         struct tg3_rx_buffer_desc *desc;
4576         struct ring_info *map;
4577         struct sk_buff *skb;
4578         dma_addr_t mapping;
4579         int skb_size, dest_idx;
4580
4581         switch (opaque_key) {
4582         case RXD_OPAQUE_RING_STD:
4583                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4584                 desc = &tpr->rx_std[dest_idx];
4585                 map = &tpr->rx_std_buffers[dest_idx];
4586                 skb_size = tp->rx_pkt_map_sz;
4587                 break;
4588
4589         case RXD_OPAQUE_RING_JUMBO:
4590                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4591                 desc = &tpr->rx_jmb[dest_idx].std;
4592                 map = &tpr->rx_jmb_buffers[dest_idx];
4593                 skb_size = TG3_RX_JMB_MAP_SZ;
4594                 break;
4595
4596         default:
4597                 return -EINVAL;
4598         }
4599
4600         /* Do not overwrite any of the map or rp information
4601          * until we are sure we can commit to a new buffer.
4602          *
4603          * Callers depend upon this behavior and assume that
4604          * we leave everything unchanged if we fail.
4605          */
4606         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4607         if (skb == NULL)
4608                 return -ENOMEM;
4609
4610         skb_reserve(skb, tp->rx_offset);
4611
4612         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4613                                  PCI_DMA_FROMDEVICE);
4614         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4615                 dev_kfree_skb(skb);
4616                 return -EIO;
4617         }
4618
4619         map->skb = skb;
4620         dma_unmap_addr_set(map, mapping, mapping);
4621
4622         desc->addr_hi = ((u64)mapping >> 32);
4623         desc->addr_lo = ((u64)mapping & 0xffffffff);
4624
4625         return skb_size;
4626 }
4627
4628 /* We only need to move over in the address because the other
4629  * members of the RX descriptor are invariant.  See notes above
4630  * tg3_alloc_rx_skb for full details.
4631  */
4632 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4633                            struct tg3_rx_prodring_set *dpr,
4634                            u32 opaque_key, int src_idx,
4635                            u32 dest_idx_unmasked)
4636 {
4637         struct tg3 *tp = tnapi->tp;
4638         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4639         struct ring_info *src_map, *dest_map;
4640         struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
4641         int dest_idx;
4642
4643         switch (opaque_key) {
4644         case RXD_OPAQUE_RING_STD:
4645                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4646                 dest_desc = &dpr->rx_std[dest_idx];
4647                 dest_map = &dpr->rx_std_buffers[dest_idx];
4648                 src_desc = &spr->rx_std[src_idx];
4649                 src_map = &spr->rx_std_buffers[src_idx];
4650                 break;
4651
4652         case RXD_OPAQUE_RING_JUMBO:
4653                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4654                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4655                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4656                 src_desc = &spr->rx_jmb[src_idx].std;
4657                 src_map = &spr->rx_jmb_buffers[src_idx];
4658                 break;
4659
4660         default:
4661                 return;
4662         }
4663
4664         dest_map->skb = src_map->skb;
4665         dma_unmap_addr_set(dest_map, mapping,
4666                            dma_unmap_addr(src_map, mapping));
4667         dest_desc->addr_hi = src_desc->addr_hi;
4668         dest_desc->addr_lo = src_desc->addr_lo;
4669
4670         /* Ensure that the update to the skb happens after the physical
4671          * addresses have been transferred to the new BD location.
4672          */
4673         smp_wmb();
4674
4675         src_map->skb = NULL;
4676 }
4677
4678 /* The RX ring scheme is composed of multiple rings which post fresh
4679  * buffers to the chip, and one special ring the chip uses to report
4680  * status back to the host.
4681  *
4682  * The special ring reports the status of received packets to the
4683  * host.  The chip does not write into the original descriptor the
4684  * RX buffer was obtained from.  The chip simply takes the original
4685  * descriptor as provided by the host, updates the status and length
4686  * field, then writes this into the next status ring entry.
4687  *
4688  * Each ring the host uses to post buffers to the chip is described
4689  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4690  * it is first placed into the on-chip ram.  When the packet's length
4691  * is known, it walks down the TG3_BDINFO entries to select the ring.
4692  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4693  * which is within the range of the new packet's length is chosen.
4694  *
4695  * The "separate ring for rx status" scheme may sound queer, but it makes
4696  * sense from a cache coherency perspective.  If only the host writes
4697  * to the buffer post rings, and only the chip writes to the rx status
4698  * rings, then cache lines never move beyond shared-modified state.
4699  * If both the host and chip were to write into the same ring, cache line
4700  * eviction could occur since both entities want it in an exclusive state.
4701  */
4702 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4703 {
4704         struct tg3 *tp = tnapi->tp;
4705         u32 work_mask, rx_std_posted = 0;
4706         u32 std_prod_idx, jmb_prod_idx;
4707         u32 sw_idx = tnapi->rx_rcb_ptr;
4708         u16 hw_idx;
4709         int received;
4710         struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
4711
4712         hw_idx = *(tnapi->rx_rcb_prod_idx);
4713         /*
4714          * We need to order the read of hw_idx and the read of
4715          * the opaque cookie.
4716          */
4717         rmb();
4718         work_mask = 0;
4719         received = 0;
4720         std_prod_idx = tpr->rx_std_prod_idx;
4721         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4722         while (sw_idx != hw_idx && budget > 0) {
4723                 struct ring_info *ri;
4724                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4725                 unsigned int len;
4726                 struct sk_buff *skb;
4727                 dma_addr_t dma_addr;
4728                 u32 opaque_key, desc_idx, *post_ptr;
4729                 bool hw_vlan __maybe_unused = false;
4730                 u16 vtag __maybe_unused = 0;
4731
4732                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4733                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4734                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4735                         ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4736                         dma_addr = dma_unmap_addr(ri, mapping);
4737                         skb = ri->skb;
4738                         post_ptr = &std_prod_idx;
4739                         rx_std_posted++;
4740                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4741                         ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4742                         dma_addr = dma_unmap_addr(ri, mapping);
4743                         skb = ri->skb;
4744                         post_ptr = &jmb_prod_idx;
4745                 } else
4746                         goto next_pkt_nopost;
4747
4748                 work_mask |= opaque_key;
4749
4750                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4751                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4752                 drop_it:
4753                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4754                                        desc_idx, *post_ptr);
4755                 drop_it_no_recycle:
4756                         /* Other statistics kept track of by card. */
4757                         tp->net_stats.rx_dropped++;
4758                         goto next_pkt;
4759                 }
4760
4761                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4762                       ETH_FCS_LEN;
4763
4764                 if (len > TG3_RX_COPY_THRESH(tp)) {
4765                         int skb_size;
4766
4767                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4768                                                     *post_ptr);
4769                         if (skb_size < 0)
4770                                 goto drop_it;
4771
4772                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4773                                          PCI_DMA_FROMDEVICE);
4774
4775                         /* Ensure that the update to the skb happens
4776                          * after the usage of the old DMA mapping.
4777                          */
4778                         smp_wmb();
4779
4780                         ri->skb = NULL;
4781
4782                         skb_put(skb, len);
4783                 } else {
4784                         struct sk_buff *copy_skb;
4785
4786                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4787                                        desc_idx, *post_ptr);
4788
4789                         copy_skb = netdev_alloc_skb(tp->dev, len + VLAN_HLEN +
4790                                                     TG3_RAW_IP_ALIGN);
4791                         if (copy_skb == NULL)
4792                                 goto drop_it_no_recycle;
4793
4794                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN + VLAN_HLEN);
4795                         skb_put(copy_skb, len);
4796                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4797                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4798                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4799
4800                         /* We'll reuse the original ring buffer. */
4801                         skb = copy_skb;
4802                 }
4803
4804                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4805                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4806                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4807                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4808                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4809                 else
4810                         skb_checksum_none_assert(skb);
4811
4812                 skb->protocol = eth_type_trans(skb, tp->dev);
4813
4814                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4815                     skb->protocol != htons(ETH_P_8021Q)) {
4816                         dev_kfree_skb(skb);
4817                         goto next_pkt;
4818                 }
4819
4820                 if (desc->type_flags & RXD_FLAG_VLAN &&
4821                     !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) {
4822                         vtag = desc->err_vlan & RXD_VLAN_MASK;
4823 #if TG3_VLAN_TAG_USED
4824                         if (tp->vlgrp)
4825                                 hw_vlan = true;
4826                         else
4827 #endif
4828                         {
4829                                 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
4830                                                     __skb_push(skb, VLAN_HLEN);
4831
4832                                 memmove(ve, skb->data + VLAN_HLEN,
4833                                         ETH_ALEN * 2);
4834                                 ve->h_vlan_proto = htons(ETH_P_8021Q);
4835                                 ve->h_vlan_TCI = htons(vtag);
4836                         }
4837                 }
4838
4839 #if TG3_VLAN_TAG_USED
4840                 if (hw_vlan)
4841                         vlan_gro_receive(&tnapi->napi, tp->vlgrp, vtag, skb);
4842                 else
4843 #endif
4844                         napi_gro_receive(&tnapi->napi, skb);
4845
4846                 received++;
4847                 budget--;
4848
4849 next_pkt:
4850                 (*post_ptr)++;
4851
4852                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4853                         tpr->rx_std_prod_idx = std_prod_idx &
4854                                                tp->rx_std_ring_mask;
4855                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4856                                      tpr->rx_std_prod_idx);
4857                         work_mask &= ~RXD_OPAQUE_RING_STD;
4858                         rx_std_posted = 0;
4859                 }
4860 next_pkt_nopost:
4861                 sw_idx++;
4862                 sw_idx &= tp->rx_ret_ring_mask;
4863
4864                 /* Refresh hw_idx to see if there is new work */
4865                 if (sw_idx == hw_idx) {
4866                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4867                         rmb();
4868                 }
4869         }
4870
4871         /* ACK the status ring. */
4872         tnapi->rx_rcb_ptr = sw_idx;
4873         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4874
4875         /* Refill RX ring(s). */
4876         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4877                 if (work_mask & RXD_OPAQUE_RING_STD) {
4878                         tpr->rx_std_prod_idx = std_prod_idx &
4879                                                tp->rx_std_ring_mask;
4880                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4881                                      tpr->rx_std_prod_idx);
4882                 }
4883                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4884                         tpr->rx_jmb_prod_idx = jmb_prod_idx &
4885                                                tp->rx_jmb_ring_mask;
4886                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4887                                      tpr->rx_jmb_prod_idx);
4888                 }
4889                 mmiowb();
4890         } else if (work_mask) {
4891                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4892                  * updated before the producer indices can be updated.
4893                  */
4894                 smp_wmb();
4895
4896                 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
4897                 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
4898
4899                 if (tnapi != &tp->napi[1])
4900                         napi_schedule(&tp->napi[1].napi);
4901         }
4902
4903         return received;
4904 }
4905
4906 static void tg3_poll_link(struct tg3 *tp)
4907 {
4908         /* handle link change and other phy events */
4909         if (!(tp->tg3_flags &
4910               (TG3_FLAG_USE_LINKCHG_REG |
4911                TG3_FLAG_POLL_SERDES))) {
4912                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4913
4914                 if (sblk->status & SD_STATUS_LINK_CHG) {
4915                         sblk->status = SD_STATUS_UPDATED |
4916                                        (sblk->status & ~SD_STATUS_LINK_CHG);
4917                         spin_lock(&tp->lock);
4918                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4919                                 tw32_f(MAC_STATUS,
4920                                      (MAC_STATUS_SYNC_CHANGED |
4921                                       MAC_STATUS_CFG_CHANGED |
4922                                       MAC_STATUS_MI_COMPLETION |
4923                                       MAC_STATUS_LNKSTATE_CHANGED));
4924                                 udelay(40);
4925                         } else
4926                                 tg3_setup_phy(tp, 0);
4927                         spin_unlock(&tp->lock);
4928                 }
4929         }
4930 }
4931
4932 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4933                                 struct tg3_rx_prodring_set *dpr,
4934                                 struct tg3_rx_prodring_set *spr)
4935 {
4936         u32 si, di, cpycnt, src_prod_idx;
4937         int i, err = 0;
4938
4939         while (1) {
4940                 src_prod_idx = spr->rx_std_prod_idx;
4941
4942                 /* Make sure updates to the rx_std_buffers[] entries and the
4943                  * standard producer index are seen in the correct order.
4944                  */
4945                 smp_rmb();
4946
4947                 if (spr->rx_std_cons_idx == src_prod_idx)
4948                         break;
4949
4950                 if (spr->rx_std_cons_idx < src_prod_idx)
4951                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4952                 else
4953                         cpycnt = tp->rx_std_ring_mask + 1 -
4954                                  spr->rx_std_cons_idx;
4955
4956                 cpycnt = min(cpycnt,
4957                              tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
4958
4959                 si = spr->rx_std_cons_idx;
4960                 di = dpr->rx_std_prod_idx;
4961
4962                 for (i = di; i < di + cpycnt; i++) {
4963                         if (dpr->rx_std_buffers[i].skb) {
4964                                 cpycnt = i - di;
4965                                 err = -ENOSPC;
4966                                 break;
4967                         }
4968                 }
4969
4970                 if (!cpycnt)
4971                         break;
4972
4973                 /* Ensure that updates to the rx_std_buffers ring and the
4974                  * shadowed hardware producer ring from tg3_recycle_skb() are
4975                  * ordered correctly WRT the skb check above.
4976                  */
4977                 smp_rmb();
4978
4979                 memcpy(&dpr->rx_std_buffers[di],
4980                        &spr->rx_std_buffers[si],
4981                        cpycnt * sizeof(struct ring_info));
4982
4983                 for (i = 0; i < cpycnt; i++, di++, si++) {
4984                         struct tg3_rx_buffer_desc *sbd, *dbd;
4985                         sbd = &spr->rx_std[si];
4986                         dbd = &dpr->rx_std[di];
4987                         dbd->addr_hi = sbd->addr_hi;
4988                         dbd->addr_lo = sbd->addr_lo;
4989                 }
4990
4991                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
4992                                        tp->rx_std_ring_mask;
4993                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
4994                                        tp->rx_std_ring_mask;
4995         }
4996
4997         while (1) {
4998                 src_prod_idx = spr->rx_jmb_prod_idx;
4999
5000                 /* Make sure updates to the rx_jmb_buffers[] entries and
5001                  * the jumbo producer index are seen in the correct order.
5002                  */
5003                 smp_rmb();
5004
5005                 if (spr->rx_jmb_cons_idx == src_prod_idx)
5006                         break;
5007
5008                 if (spr->rx_jmb_cons_idx < src_prod_idx)
5009                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
5010                 else
5011                         cpycnt = tp->rx_jmb_ring_mask + 1 -
5012                                  spr->rx_jmb_cons_idx;
5013
5014                 cpycnt = min(cpycnt,
5015                              tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
5016
5017                 si = spr->rx_jmb_cons_idx;
5018                 di = dpr->rx_jmb_prod_idx;
5019
5020                 for (i = di; i < di + cpycnt; i++) {
5021                         if (dpr->rx_jmb_buffers[i].skb) {
5022                                 cpycnt = i - di;
5023                                 err = -ENOSPC;
5024                                 break;
5025                         }
5026                 }
5027
5028                 if (!cpycnt)
5029                         break;
5030
5031                 /* Ensure that updates to the rx_jmb_buffers ring and the
5032                  * shadowed hardware producer ring from tg3_recycle_skb() are
5033                  * ordered correctly WRT the skb check above.
5034                  */
5035                 smp_rmb();
5036
5037                 memcpy(&dpr->rx_jmb_buffers[di],
5038                        &spr->rx_jmb_buffers[si],
5039                        cpycnt * sizeof(struct ring_info));
5040
5041                 for (i = 0; i < cpycnt; i++, di++, si++) {
5042                         struct tg3_rx_buffer_desc *sbd, *dbd;
5043                         sbd = &spr->rx_jmb[si].std;
5044                         dbd = &dpr->rx_jmb[di].std;
5045                         dbd->addr_hi = sbd->addr_hi;
5046                         dbd->addr_lo = sbd->addr_lo;
5047                 }
5048
5049                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
5050                                        tp->rx_jmb_ring_mask;
5051                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
5052                                        tp->rx_jmb_ring_mask;
5053         }
5054
5055         return err;
5056 }
5057
5058 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
5059 {
5060         struct tg3 *tp = tnapi->tp;
5061
5062         /* run TX completion thread */
5063         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
5064                 tg3_tx(tnapi);
5065                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5066                         return work_done;
5067         }
5068
5069         /* run RX thread, within the bounds set by NAPI.
5070          * All RX "locking" is done by ensuring outside
5071          * code synchronizes with tg3->napi.poll()
5072          */
5073         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
5074                 work_done += tg3_rx(tnapi, budget - work_done);
5075
5076         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
5077                 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
5078                 int i, err = 0;
5079                 u32 std_prod_idx = dpr->rx_std_prod_idx;
5080                 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
5081
5082                 for (i = 1; i < tp->irq_cnt; i++)
5083                         err |= tg3_rx_prodring_xfer(tp, dpr,
5084                                                     &tp->napi[i].prodring);
5085
5086                 wmb();
5087
5088                 if (std_prod_idx != dpr->rx_std_prod_idx)
5089                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5090                                      dpr->rx_std_prod_idx);
5091
5092                 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5093                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5094                                      dpr->rx_jmb_prod_idx);
5095
5096                 mmiowb();
5097
5098                 if (err)
5099                         tw32_f(HOSTCC_MODE, tp->coal_now);
5100         }
5101
5102         return work_done;
5103 }
5104
5105 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5106 {
5107         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5108         struct tg3 *tp = tnapi->tp;
5109         int work_done = 0;
5110         struct tg3_hw_status *sblk = tnapi->hw_status;
5111
5112         while (1) {
5113                 work_done = tg3_poll_work(tnapi, work_done, budget);
5114
5115                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5116                         goto tx_recovery;
5117
5118                 if (unlikely(work_done >= budget))
5119                         break;
5120
5121                 /* tp->last_tag is used in tg3_int_reenable() below
5122                  * to tell the hw how much work has been processed,
5123                  * so we must read it before checking for more work.
5124                  */
5125                 tnapi->last_tag = sblk->status_tag;
5126                 tnapi->last_irq_tag = tnapi->last_tag;
5127                 rmb();
5128
5129                 /* check for RX/TX work to do */
5130                 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5131                            *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5132                         napi_complete(napi);
5133                         /* Reenable interrupts. */
5134                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5135                         mmiowb();
5136                         break;
5137                 }
5138         }
5139
5140         return work_done;
5141
5142 tx_recovery:
5143         /* work_done is guaranteed to be less than budget. */
5144         napi_complete(napi);
5145         schedule_work(&tp->reset_task);
5146         return work_done;
5147 }
5148
5149 static int tg3_poll(struct napi_struct *napi, int budget)
5150 {
5151         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5152         struct tg3 *tp = tnapi->tp;
5153         int work_done = 0;
5154         struct tg3_hw_status *sblk = tnapi->hw_status;
5155
5156         while (1) {
5157                 tg3_poll_link(tp);
5158
5159                 work_done = tg3_poll_work(tnapi, work_done, budget);
5160
5161                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5162                         goto tx_recovery;
5163
5164                 if (unlikely(work_done >= budget))
5165                         break;
5166
5167                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5168                         /* tp->last_tag is used in tg3_int_reenable() below
5169                          * to tell the hw how much work has been processed,
5170                          * so we must read it before checking for more work.
5171                          */
5172                         tnapi->last_tag = sblk->status_tag;
5173                         tnapi->last_irq_tag = tnapi->last_tag;
5174                         rmb();
5175                 } else
5176                         sblk->status &= ~SD_STATUS_UPDATED;
5177
5178                 if (likely(!tg3_has_work(tnapi))) {
5179                         napi_complete(napi);
5180                         tg3_int_reenable(tnapi);
5181                         break;
5182                 }
5183         }
5184
5185         return work_done;
5186
5187 tx_recovery:
5188         /* work_done is guaranteed to be less than budget. */
5189         napi_complete(napi);
5190         schedule_work(&tp->reset_task);
5191         return work_done;
5192 }
5193
5194 static void tg3_napi_disable(struct tg3 *tp)
5195 {
5196         int i;
5197
5198         for (i = tp->irq_cnt - 1; i >= 0; i--)
5199                 napi_disable(&tp->napi[i].napi);
5200 }
5201
5202 static void tg3_napi_enable(struct tg3 *tp)
5203 {
5204         int i;
5205
5206         for (i = 0; i < tp->irq_cnt; i++)
5207                 napi_enable(&tp->napi[i].napi);
5208 }
5209
5210 static void tg3_napi_init(struct tg3 *tp)
5211 {
5212         int i;
5213
5214         netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
5215         for (i = 1; i < tp->irq_cnt; i++)
5216                 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
5217 }
5218
5219 static void tg3_napi_fini(struct tg3 *tp)
5220 {
5221         int i;
5222
5223         for (i = 0; i < tp->irq_cnt; i++)
5224                 netif_napi_del(&tp->napi[i].napi);
5225 }
5226
5227 static inline void tg3_netif_stop(struct tg3 *tp)
5228 {
5229         tp->dev->trans_start = jiffies; /* prevent tx timeout */
5230         tg3_napi_disable(tp);
5231         netif_tx_disable(tp->dev);
5232 }
5233
5234 static inline void tg3_netif_start(struct tg3 *tp)
5235 {
5236         /* NOTE: unconditional netif_tx_wake_all_queues is only
5237          * appropriate so long as all callers are assured to
5238          * have free tx slots (such as after tg3_init_hw)
5239          */
5240         netif_tx_wake_all_queues(tp->dev);
5241
5242         tg3_napi_enable(tp);
5243         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
5244         tg3_enable_ints(tp);
5245 }
5246
5247 static void tg3_irq_quiesce(struct tg3 *tp)
5248 {
5249         int i;
5250
5251         BUG_ON(tp->irq_sync);
5252
5253         tp->irq_sync = 1;
5254         smp_mb();
5255
5256         for (i = 0; i < tp->irq_cnt; i++)
5257                 synchronize_irq(tp->napi[i].irq_vec);
5258 }
5259
5260 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5261  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5262  * with as well.  Most of the time, this is not necessary except when
5263  * shutting down the device.
5264  */
5265 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5266 {
5267         spin_lock_bh(&tp->lock);
5268         if (irq_sync)
5269                 tg3_irq_quiesce(tp);
5270 }
5271
5272 static inline void tg3_full_unlock(struct tg3 *tp)
5273 {
5274         spin_unlock_bh(&tp->lock);
5275 }
5276
5277 /* One-shot MSI handler - Chip automatically disables interrupt
5278  * after sending MSI so driver doesn't have to do it.
5279  */
5280 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5281 {
5282         struct tg3_napi *tnapi = dev_id;
5283         struct tg3 *tp = tnapi->tp;
5284
5285         prefetch(tnapi->hw_status);
5286         if (tnapi->rx_rcb)
5287                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5288
5289         if (likely(!tg3_irq_sync(tp)))
5290                 napi_schedule(&tnapi->napi);
5291
5292         return IRQ_HANDLED;
5293 }
5294
5295 /* MSI ISR - No need to check for interrupt sharing and no need to
5296  * flush status block and interrupt mailbox. PCI ordering rules
5297  * guarantee that MSI will arrive after the status block.
5298  */
5299 static irqreturn_t tg3_msi(int irq, void *dev_id)
5300 {
5301         struct tg3_napi *tnapi = dev_id;
5302         struct tg3 *tp = tnapi->tp;
5303
5304         prefetch(tnapi->hw_status);
5305         if (tnapi->rx_rcb)
5306                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5307         /*
5308          * Writing any value to intr-mbox-0 clears PCI INTA# and
5309          * chip-internal interrupt pending events.
5310          * Writing non-zero to intr-mbox-0 additional tells the
5311          * NIC to stop sending us irqs, engaging "in-intr-handler"
5312          * event coalescing.
5313          */
5314         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5315         if (likely(!tg3_irq_sync(tp)))
5316                 napi_schedule(&tnapi->napi);
5317
5318         return IRQ_RETVAL(1);
5319 }
5320
5321 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5322 {
5323         struct tg3_napi *tnapi = dev_id;
5324         struct tg3 *tp = tnapi->tp;
5325         struct tg3_hw_status *sblk = tnapi->hw_status;
5326         unsigned int handled = 1;
5327
5328         /* In INTx mode, it is possible for the interrupt to arrive at
5329          * the CPU before the status block posted prior to the interrupt.
5330          * Reading the PCI State register will confirm whether the
5331          * interrupt is ours and will flush the status block.
5332          */
5333         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5334                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5335                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5336                         handled = 0;
5337                         goto out;
5338                 }
5339         }
5340
5341         /*
5342          * Writing any value to intr-mbox-0 clears PCI INTA# and
5343          * chip-internal interrupt pending events.
5344          * Writing non-zero to intr-mbox-0 additional tells the
5345          * NIC to stop sending us irqs, engaging "in-intr-handler"
5346          * event coalescing.
5347          *
5348          * Flush the mailbox to de-assert the IRQ immediately to prevent
5349          * spurious interrupts.  The flush impacts performance but
5350          * excessive spurious interrupts can be worse in some cases.
5351          */
5352         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5353         if (tg3_irq_sync(tp))
5354                 goto out;
5355         sblk->status &= ~SD_STATUS_UPDATED;
5356         if (likely(tg3_has_work(tnapi))) {
5357                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5358                 napi_schedule(&tnapi->napi);
5359         } else {
5360                 /* No work, shared interrupt perhaps?  re-enable
5361                  * interrupts, and flush that PCI write
5362                  */
5363                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5364                                0x00000000);
5365         }
5366 out:
5367         return IRQ_RETVAL(handled);
5368 }
5369
5370 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5371 {
5372         struct tg3_napi *tnapi = dev_id;
5373         struct tg3 *tp = tnapi->tp;
5374         struct tg3_hw_status *sblk = tnapi->hw_status;
5375         unsigned int handled = 1;
5376
5377         /* In INTx mode, it is possible for the interrupt to arrive at
5378          * the CPU before the status block posted prior to the interrupt.
5379          * Reading the PCI State register will confirm whether the
5380          * interrupt is ours and will flush the status block.
5381          */
5382         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5383                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5384                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5385                         handled = 0;
5386                         goto out;
5387                 }
5388         }
5389
5390         /*
5391          * writing any value to intr-mbox-0 clears PCI INTA# and
5392          * chip-internal interrupt pending events.
5393          * writing non-zero to intr-mbox-0 additional tells the
5394          * NIC to stop sending us irqs, engaging "in-intr-handler"
5395          * event coalescing.
5396          *
5397          * Flush the mailbox to de-assert the IRQ immediately to prevent
5398          * spurious interrupts.  The flush impacts performance but
5399          * excessive spurious interrupts can be worse in some cases.
5400          */
5401         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5402
5403         /*
5404          * In a shared interrupt configuration, sometimes other devices'
5405          * interrupts will scream.  We record the current status tag here
5406          * so that the above check can report that the screaming interrupts
5407          * are unhandled.  Eventually they will be silenced.
5408          */
5409         tnapi->last_irq_tag = sblk->status_tag;
5410
5411         if (tg3_irq_sync(tp))
5412                 goto out;
5413
5414         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5415
5416         napi_schedule(&tnapi->napi);
5417
5418 out:
5419         return IRQ_RETVAL(handled);
5420 }
5421
5422 /* ISR for interrupt test */
5423 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5424 {
5425         struct tg3_napi *tnapi = dev_id;
5426         struct tg3 *tp = tnapi->tp;
5427         struct tg3_hw_status *sblk = tnapi->hw_status;
5428
5429         if ((sblk->status & SD_STATUS_UPDATED) ||
5430             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5431                 tg3_disable_ints(tp);
5432                 return IRQ_RETVAL(1);
5433         }
5434         return IRQ_RETVAL(0);
5435 }
5436
5437 static int tg3_init_hw(struct tg3 *, int);
5438 static int tg3_halt(struct tg3 *, int, int);
5439
5440 /* Restart hardware after configuration changes, self-test, etc.
5441  * Invoked with tp->lock held.
5442  */
5443 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5444         __releases(tp->lock)
5445         __acquires(tp->lock)
5446 {
5447         int err;
5448
5449         err = tg3_init_hw(tp, reset_phy);
5450         if (err) {
5451                 netdev_err(tp->dev,
5452                            "Failed to re-initialize device, aborting\n");
5453                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5454                 tg3_full_unlock(tp);
5455                 del_timer_sync(&tp->timer);
5456                 tp->irq_sync = 0;
5457                 tg3_napi_enable(tp);
5458                 dev_close(tp->dev);
5459                 tg3_full_lock(tp, 0);
5460         }
5461         return err;
5462 }
5463
5464 #ifdef CONFIG_NET_POLL_CONTROLLER
5465 static void tg3_poll_controller(struct net_device *dev)
5466 {
5467         int i;
5468         struct tg3 *tp = netdev_priv(dev);
5469
5470         for (i = 0; i < tp->irq_cnt; i++)
5471                 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5472 }
5473 #endif
5474
5475 static void tg3_reset_task(struct work_struct *work)
5476 {
5477         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5478         int err;
5479         unsigned int restart_timer;
5480
5481         tg3_full_lock(tp, 0);
5482
5483         if (!netif_running(tp->dev)) {
5484                 tg3_full_unlock(tp);
5485                 return;
5486         }
5487
5488         tg3_full_unlock(tp);
5489
5490         tg3_phy_stop(tp);
5491
5492         tg3_netif_stop(tp);
5493
5494         tg3_full_lock(tp, 1);
5495
5496         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5497         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5498
5499         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5500                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5501                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5502                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5503                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5504         }
5505
5506         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5507         err = tg3_init_hw(tp, 1);
5508         if (err)
5509                 goto out;
5510
5511         tg3_netif_start(tp);
5512
5513         if (restart_timer)
5514                 mod_timer(&tp->timer, jiffies + 1);
5515
5516 out:
5517         tg3_full_unlock(tp);
5518
5519         if (!err)
5520                 tg3_phy_start(tp);
5521 }
5522
5523 static void tg3_dump_short_state(struct tg3 *tp)
5524 {
5525         netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5526                    tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5527         netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5528                    tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5529 }
5530
5531 static void tg3_tx_timeout(struct net_device *dev)
5532 {
5533         struct tg3 *tp = netdev_priv(dev);
5534
5535         if (netif_msg_tx_err(tp)) {
5536                 netdev_err(dev, "transmit timed out, resetting\n");
5537                 tg3_dump_short_state(tp);
5538         }
5539
5540         schedule_work(&tp->reset_task);
5541 }
5542
5543 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5544 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5545 {
5546         u32 base = (u32) mapping & 0xffffffff;
5547
5548         return (base > 0xffffdcc0) && (base + len + 8 < base);
5549 }
5550
5551 /* Test for DMA addresses > 40-bit */
5552 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5553                                           int len)
5554 {
5555 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5556         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5557                 return ((u64) mapping + len) > DMA_BIT_MASK(40);
5558         return 0;
5559 #else
5560         return 0;
5561 #endif
5562 }
5563
5564 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5565
5566 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5567 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5568                                        struct sk_buff *skb, u32 last_plus_one,
5569                                        u32 *start, u32 base_flags, u32 mss)
5570 {
5571         struct tg3 *tp = tnapi->tp;
5572         struct sk_buff *new_skb;
5573         dma_addr_t new_addr = 0;
5574         u32 entry = *start;
5575         int i, ret = 0;
5576
5577         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5578                 new_skb = skb_copy(skb, GFP_ATOMIC);
5579         else {
5580                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5581
5582                 new_skb = skb_copy_expand(skb,
5583                                           skb_headroom(skb) + more_headroom,
5584                                           skb_tailroom(skb), GFP_ATOMIC);
5585         }
5586
5587         if (!new_skb) {
5588                 ret = -1;
5589         } else {
5590                 /* New SKB is guaranteed to be linear. */
5591                 entry = *start;
5592                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5593                                           PCI_DMA_TODEVICE);
5594                 /* Make sure the mapping succeeded */
5595                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5596                         ret = -1;
5597                         dev_kfree_skb(new_skb);
5598                         new_skb = NULL;
5599
5600                 /* Make sure new skb does not cross any 4G boundaries.
5601                  * Drop the packet if it does.
5602                  */
5603                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5604                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5605                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5606                                          PCI_DMA_TODEVICE);
5607                         ret = -1;
5608                         dev_kfree_skb(new_skb);
5609                         new_skb = NULL;
5610                 } else {
5611                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5612                                     base_flags, 1 | (mss << 1));
5613                         *start = NEXT_TX(entry);
5614                 }
5615         }
5616
5617         /* Now clean up the sw ring entries. */
5618         i = 0;
5619         while (entry != last_plus_one) {
5620                 int len;
5621
5622                 if (i == 0)
5623                         len = skb_headlen(skb);
5624                 else
5625                         len = skb_shinfo(skb)->frags[i-1].size;
5626
5627                 pci_unmap_single(tp->pdev,
5628                                  dma_unmap_addr(&tnapi->tx_buffers[entry],
5629                                                 mapping),
5630                                  len, PCI_DMA_TODEVICE);
5631                 if (i == 0) {
5632                         tnapi->tx_buffers[entry].skb = new_skb;
5633                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5634                                            new_addr);
5635                 } else {
5636                         tnapi->tx_buffers[entry].skb = NULL;
5637                 }
5638                 entry = NEXT_TX(entry);
5639                 i++;
5640         }
5641
5642         dev_kfree_skb(skb);
5643
5644         return ret;
5645 }
5646
5647 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5648                         dma_addr_t mapping, int len, u32 flags,
5649                         u32 mss_and_is_end)
5650 {
5651         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5652         int is_end = (mss_and_is_end & 0x1);
5653         u32 mss = (mss_and_is_end >> 1);
5654         u32 vlan_tag = 0;
5655
5656         if (is_end)
5657                 flags |= TXD_FLAG_END;
5658         if (flags & TXD_FLAG_VLAN) {
5659                 vlan_tag = flags >> 16;
5660                 flags &= 0xffff;
5661         }
5662         vlan_tag |= (mss << TXD_MSS_SHIFT);
5663
5664         txd->addr_hi = ((u64) mapping >> 32);
5665         txd->addr_lo = ((u64) mapping & 0xffffffff);
5666         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5667         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5668 }
5669
5670 /* hard_start_xmit for devices that don't have any bugs and
5671  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5672  */
5673 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5674                                   struct net_device *dev)
5675 {
5676         struct tg3 *tp = netdev_priv(dev);
5677         u32 len, entry, base_flags, mss;
5678         dma_addr_t mapping;
5679         struct tg3_napi *tnapi;
5680         struct netdev_queue *txq;
5681         unsigned int i, last;
5682
5683         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5684         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5685         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5686                 tnapi++;
5687
5688         /* We are running in BH disabled context with netif_tx_lock
5689          * and TX reclaim runs via tp->napi.poll inside of a software
5690          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5691          * no IRQ context deadlocks to worry about either.  Rejoice!
5692          */
5693         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5694                 if (!netif_tx_queue_stopped(txq)) {
5695                         netif_tx_stop_queue(txq);
5696
5697                         /* This is a hard error, log it. */
5698                         netdev_err(dev,
5699                                    "BUG! Tx Ring full when queue awake!\n");
5700                 }
5701                 return NETDEV_TX_BUSY;
5702         }
5703
5704         entry = tnapi->tx_prod;
5705         base_flags = 0;
5706         mss = skb_shinfo(skb)->gso_size;
5707         if (mss) {
5708                 int tcp_opt_len, ip_tcp_len;
5709                 u32 hdrlen;
5710
5711                 if (skb_header_cloned(skb) &&
5712                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5713                         dev_kfree_skb(skb);
5714                         goto out_unlock;
5715                 }
5716
5717                 if (skb_is_gso_v6(skb)) {
5718                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5719                 } else {
5720                         struct iphdr *iph = ip_hdr(skb);
5721
5722                         tcp_opt_len = tcp_optlen(skb);
5723                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5724
5725                         iph->check = 0;
5726                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5727                         hdrlen = ip_tcp_len + tcp_opt_len;
5728                 }
5729
5730                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5731                         mss |= (hdrlen & 0xc) << 12;
5732                         if (hdrlen & 0x10)
5733                                 base_flags |= 0x00000010;
5734                         base_flags |= (hdrlen & 0x3e0) << 5;
5735                 } else
5736                         mss |= hdrlen << 9;
5737
5738                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5739                                TXD_FLAG_CPU_POST_DMA);
5740
5741                 tcp_hdr(skb)->check = 0;
5742
5743         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5744                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5745         }
5746
5747 #if TG3_VLAN_TAG_USED
5748         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5749                 base_flags |= (TXD_FLAG_VLAN |
5750                                (vlan_tx_tag_get(skb) << 16));
5751 #endif
5752
5753         len = skb_headlen(skb);
5754
5755         /* Queue skb data, a.k.a. the main skb fragment. */
5756         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5757         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5758                 dev_kfree_skb(skb);
5759                 goto out_unlock;
5760         }
5761
5762         tnapi->tx_buffers[entry].skb = skb;
5763         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5764
5765         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5766             !mss && skb->len > ETH_DATA_LEN)
5767                 base_flags |= TXD_FLAG_JMB_PKT;
5768
5769         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5770                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5771
5772         entry = NEXT_TX(entry);
5773
5774         /* Now loop through additional data fragments, and queue them. */
5775         if (skb_shinfo(skb)->nr_frags > 0) {
5776                 last = skb_shinfo(skb)->nr_frags - 1;
5777                 for (i = 0; i <= last; i++) {
5778                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5779
5780                         len = frag->size;
5781                         mapping = pci_map_page(tp->pdev,
5782                                                frag->page,
5783                                                frag->page_offset,
5784                                                len, PCI_DMA_TODEVICE);
5785                         if (pci_dma_mapping_error(tp->pdev, mapping))
5786                                 goto dma_error;
5787
5788                         tnapi->tx_buffers[entry].skb = NULL;
5789                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5790                                            mapping);
5791
5792                         tg3_set_txd(tnapi, entry, mapping, len,
5793                                     base_flags, (i == last) | (mss << 1));
5794
5795                         entry = NEXT_TX(entry);
5796                 }
5797         }
5798
5799         /* Packets are ready, update Tx producer idx local and on card. */
5800         tw32_tx_mbox(tnapi->prodmbox, entry);
5801
5802         tnapi->tx_prod = entry;
5803         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5804                 netif_tx_stop_queue(txq);
5805
5806                 /* netif_tx_stop_queue() must be done before checking
5807                  * checking tx index in tg3_tx_avail() below, because in
5808                  * tg3_tx(), we update tx index before checking for
5809                  * netif_tx_queue_stopped().
5810                  */
5811                 smp_mb();
5812                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5813                         netif_tx_wake_queue(txq);
5814         }
5815
5816 out_unlock:
5817         mmiowb();
5818
5819         return NETDEV_TX_OK;
5820
5821 dma_error:
5822         last = i;
5823         entry = tnapi->tx_prod;
5824         tnapi->tx_buffers[entry].skb = NULL;
5825         pci_unmap_single(tp->pdev,
5826                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5827                          skb_headlen(skb),
5828                          PCI_DMA_TODEVICE);
5829         for (i = 0; i <= last; i++) {
5830                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5831                 entry = NEXT_TX(entry);
5832
5833                 pci_unmap_page(tp->pdev,
5834                                dma_unmap_addr(&tnapi->tx_buffers[entry],
5835                                               mapping),
5836                                frag->size, PCI_DMA_TODEVICE);
5837         }
5838
5839         dev_kfree_skb(skb);
5840         return NETDEV_TX_OK;
5841 }
5842
5843 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5844                                           struct net_device *);
5845
5846 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5847  * TSO header is greater than 80 bytes.
5848  */
5849 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5850 {
5851         struct sk_buff *segs, *nskb;
5852         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5853
5854         /* Estimate the number of fragments in the worst case */
5855         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5856                 netif_stop_queue(tp->dev);
5857
5858                 /* netif_tx_stop_queue() must be done before checking
5859                  * checking tx index in tg3_tx_avail() below, because in
5860                  * tg3_tx(), we update tx index before checking for
5861                  * netif_tx_queue_stopped().
5862                  */
5863                 smp_mb();
5864                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5865                         return NETDEV_TX_BUSY;
5866
5867                 netif_wake_queue(tp->dev);
5868         }
5869
5870         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5871         if (IS_ERR(segs))
5872                 goto tg3_tso_bug_end;
5873
5874         do {
5875                 nskb = segs;
5876                 segs = segs->next;
5877                 nskb->next = NULL;
5878                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5879         } while (segs);
5880
5881 tg3_tso_bug_end:
5882         dev_kfree_skb(skb);
5883
5884         return NETDEV_TX_OK;
5885 }
5886
5887 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5888  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5889  */
5890 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5891                                           struct net_device *dev)
5892 {
5893         struct tg3 *tp = netdev_priv(dev);
5894         u32 len, entry, base_flags, mss;
5895         int would_hit_hwbug;
5896         dma_addr_t mapping;
5897         struct tg3_napi *tnapi;
5898         struct netdev_queue *txq;
5899         unsigned int i, last;
5900
5901         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5902         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5903         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5904                 tnapi++;
5905
5906         /* We are running in BH disabled context with netif_tx_lock
5907          * and TX reclaim runs via tp->napi.poll inside of a software
5908          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5909          * no IRQ context deadlocks to worry about either.  Rejoice!
5910          */
5911         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5912                 if (!netif_tx_queue_stopped(txq)) {
5913                         netif_tx_stop_queue(txq);
5914
5915                         /* This is a hard error, log it. */
5916                         netdev_err(dev,
5917                                    "BUG! Tx Ring full when queue awake!\n");
5918                 }
5919                 return NETDEV_TX_BUSY;
5920         }
5921
5922         entry = tnapi->tx_prod;
5923         base_flags = 0;
5924         if (skb->ip_summed == CHECKSUM_PARTIAL)
5925                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5926
5927         mss = skb_shinfo(skb)->gso_size;
5928         if (mss) {
5929                 struct iphdr *iph;
5930                 u32 tcp_opt_len, hdr_len;
5931
5932                 if (skb_header_cloned(skb) &&
5933                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5934                         dev_kfree_skb(skb);
5935                         goto out_unlock;
5936                 }
5937
5938                 iph = ip_hdr(skb);
5939                 tcp_opt_len = tcp_optlen(skb);
5940
5941                 if (skb_is_gso_v6(skb)) {
5942                         hdr_len = skb_headlen(skb) - ETH_HLEN;
5943                 } else {
5944                         u32 ip_tcp_len;
5945
5946                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5947                         hdr_len = ip_tcp_len + tcp_opt_len;
5948
5949                         iph->check = 0;
5950                         iph->tot_len = htons(mss + hdr_len);
5951                 }
5952
5953                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5954                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5955                         return tg3_tso_bug(tp, skb);
5956
5957                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5958                                TXD_FLAG_CPU_POST_DMA);
5959
5960                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5961                         tcp_hdr(skb)->check = 0;
5962                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5963                 } else
5964                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5965                                                                  iph->daddr, 0,
5966                                                                  IPPROTO_TCP,
5967                                                                  0);
5968
5969                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5970                         mss |= (hdr_len & 0xc) << 12;
5971                         if (hdr_len & 0x10)
5972                                 base_flags |= 0x00000010;
5973                         base_flags |= (hdr_len & 0x3e0) << 5;
5974                 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5975                         mss |= hdr_len << 9;
5976                 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5977                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5978                         if (tcp_opt_len || iph->ihl > 5) {
5979                                 int tsflags;
5980
5981                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5982                                 mss |= (tsflags << 11);
5983                         }
5984                 } else {
5985                         if (tcp_opt_len || iph->ihl > 5) {
5986                                 int tsflags;
5987
5988                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5989                                 base_flags |= tsflags << 12;
5990                         }
5991                 }
5992         }
5993 #if TG3_VLAN_TAG_USED
5994         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5995                 base_flags |= (TXD_FLAG_VLAN |
5996                                (vlan_tx_tag_get(skb) << 16));
5997 #endif
5998
5999         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
6000             !mss && skb->len > ETH_DATA_LEN)
6001                 base_flags |= TXD_FLAG_JMB_PKT;
6002
6003         len = skb_headlen(skb);
6004
6005         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
6006         if (pci_dma_mapping_error(tp->pdev, mapping)) {
6007                 dev_kfree_skb(skb);
6008                 goto out_unlock;
6009         }
6010
6011         tnapi->tx_buffers[entry].skb = skb;
6012         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
6013
6014         would_hit_hwbug = 0;
6015
6016         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
6017                 would_hit_hwbug = 1;
6018
6019         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
6020             tg3_4g_overflow_test(mapping, len))
6021                 would_hit_hwbug = 1;
6022
6023         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
6024             tg3_40bit_overflow_test(tp, mapping, len))
6025                 would_hit_hwbug = 1;
6026
6027         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
6028                 would_hit_hwbug = 1;
6029
6030         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
6031                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
6032
6033         entry = NEXT_TX(entry);
6034
6035         /* Now loop through additional data fragments, and queue them. */
6036         if (skb_shinfo(skb)->nr_frags > 0) {
6037                 last = skb_shinfo(skb)->nr_frags - 1;
6038                 for (i = 0; i <= last; i++) {
6039                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6040
6041                         len = frag->size;
6042                         mapping = pci_map_page(tp->pdev,
6043                                                frag->page,
6044                                                frag->page_offset,
6045                                                len, PCI_DMA_TODEVICE);
6046
6047                         tnapi->tx_buffers[entry].skb = NULL;
6048                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
6049                                            mapping);
6050                         if (pci_dma_mapping_error(tp->pdev, mapping))
6051                                 goto dma_error;
6052
6053                         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
6054                             len <= 8)
6055                                 would_hit_hwbug = 1;
6056
6057                         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
6058                             tg3_4g_overflow_test(mapping, len))
6059                                 would_hit_hwbug = 1;
6060
6061                         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
6062                             tg3_40bit_overflow_test(tp, mapping, len))
6063                                 would_hit_hwbug = 1;
6064
6065                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6066                                 tg3_set_txd(tnapi, entry, mapping, len,
6067                                             base_flags, (i == last)|(mss << 1));
6068                         else
6069                                 tg3_set_txd(tnapi, entry, mapping, len,
6070                                             base_flags, (i == last));
6071
6072                         entry = NEXT_TX(entry);
6073                 }
6074         }
6075
6076         if (would_hit_hwbug) {
6077                 u32 last_plus_one = entry;
6078                 u32 start;
6079
6080                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
6081                 start &= (TG3_TX_RING_SIZE - 1);
6082
6083                 /* If the workaround fails due to memory/mapping
6084                  * failure, silently drop this packet.
6085                  */
6086                 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
6087                                                 &start, base_flags, mss))
6088                         goto out_unlock;
6089
6090                 entry = start;
6091         }
6092
6093         /* Packets are ready, update Tx producer idx local and on card. */
6094         tw32_tx_mbox(tnapi->prodmbox, entry);
6095
6096         tnapi->tx_prod = entry;
6097         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
6098                 netif_tx_stop_queue(txq);
6099
6100                 /* netif_tx_stop_queue() must be done before checking
6101                  * checking tx index in tg3_tx_avail() below, because in
6102                  * tg3_tx(), we update tx index before checking for
6103                  * netif_tx_queue_stopped().
6104                  */
6105                 smp_mb();
6106                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
6107                         netif_tx_wake_queue(txq);
6108         }
6109
6110 out_unlock:
6111         mmiowb();
6112
6113         return NETDEV_TX_OK;
6114
6115 dma_error:
6116         last = i;
6117         entry = tnapi->tx_prod;
6118         tnapi->tx_buffers[entry].skb = NULL;
6119         pci_unmap_single(tp->pdev,
6120                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
6121                          skb_headlen(skb),
6122                          PCI_DMA_TODEVICE);
6123         for (i = 0; i <= last; i++) {
6124                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6125                 entry = NEXT_TX(entry);
6126
6127                 pci_unmap_page(tp->pdev,
6128                                dma_unmap_addr(&tnapi->tx_buffers[entry],
6129                                               mapping),
6130                                frag->size, PCI_DMA_TODEVICE);
6131         }
6132
6133         dev_kfree_skb(skb);
6134         return NETDEV_TX_OK;
6135 }
6136
6137 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
6138                                int new_mtu)
6139 {
6140         dev->mtu = new_mtu;
6141
6142         if (new_mtu > ETH_DATA_LEN) {
6143                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6144                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
6145                         ethtool_op_set_tso(dev, 0);
6146                 } else {
6147                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
6148                 }
6149         } else {
6150                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6151                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
6152                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
6153         }
6154 }
6155
6156 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
6157 {
6158         struct tg3 *tp = netdev_priv(dev);
6159         int err;
6160
6161         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
6162                 return -EINVAL;
6163
6164         if (!netif_running(dev)) {
6165                 /* We'll just catch it later when the
6166                  * device is up'd.
6167                  */
6168                 tg3_set_mtu(dev, tp, new_mtu);
6169                 return 0;
6170         }
6171
6172         tg3_phy_stop(tp);
6173
6174         tg3_netif_stop(tp);
6175
6176         tg3_full_lock(tp, 1);
6177
6178         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6179
6180         tg3_set_mtu(dev, tp, new_mtu);
6181
6182         err = tg3_restart_hw(tp, 0);
6183
6184         if (!err)
6185                 tg3_netif_start(tp);
6186
6187         tg3_full_unlock(tp);
6188
6189         if (!err)
6190                 tg3_phy_start(tp);
6191
6192         return err;
6193 }
6194
6195 static void tg3_rx_prodring_free(struct tg3 *tp,
6196                                  struct tg3_rx_prodring_set *tpr)
6197 {
6198         int i;
6199
6200         if (tpr != &tp->napi[0].prodring) {
6201                 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
6202                      i = (i + 1) & tp->rx_std_ring_mask)
6203                         tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6204                                         tp->rx_pkt_map_sz);
6205
6206                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6207                         for (i = tpr->rx_jmb_cons_idx;
6208                              i != tpr->rx_jmb_prod_idx;
6209                              i = (i + 1) & tp->rx_jmb_ring_mask) {
6210                                 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6211                                                 TG3_RX_JMB_MAP_SZ);
6212                         }
6213                 }
6214
6215                 return;
6216         }
6217
6218         for (i = 0; i <= tp->rx_std_ring_mask; i++)
6219                 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6220                                 tp->rx_pkt_map_sz);
6221
6222         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6223                 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
6224                         tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6225                                         TG3_RX_JMB_MAP_SZ);
6226         }
6227 }
6228
6229 /* Initialize rx rings for packet processing.
6230  *
6231  * The chip has been shut down and the driver detached from
6232  * the networking, so no interrupts or new tx packets will
6233  * end up in the driver.  tp->{tx,}lock are held and thus
6234  * we may not sleep.
6235  */
6236 static int tg3_rx_prodring_alloc(struct tg3 *tp,
6237                                  struct tg3_rx_prodring_set *tpr)
6238 {
6239         u32 i, rx_pkt_dma_sz;
6240
6241         tpr->rx_std_cons_idx = 0;
6242         tpr->rx_std_prod_idx = 0;
6243         tpr->rx_jmb_cons_idx = 0;
6244         tpr->rx_jmb_prod_idx = 0;
6245
6246         if (tpr != &tp->napi[0].prodring) {
6247                 memset(&tpr->rx_std_buffers[0], 0,
6248                        TG3_RX_STD_BUFF_RING_SIZE(tp));
6249                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
6250                         memset(&tpr->rx_jmb_buffers[0], 0,
6251                                TG3_RX_JMB_BUFF_RING_SIZE(tp));
6252                 goto done;
6253         }
6254
6255         /* Zero out all descriptors. */
6256         memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
6257
6258         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6259         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
6260             tp->dev->mtu > ETH_DATA_LEN)
6261                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6262         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6263
6264         /* Initialize invariants of the rings, we only set this
6265          * stuff once.  This works because the card does not
6266          * write into the rx buffer posting rings.
6267          */
6268         for (i = 0; i <= tp->rx_std_ring_mask; i++) {
6269                 struct tg3_rx_buffer_desc *rxd;
6270
6271                 rxd = &tpr->rx_std[i];
6272                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6273                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6274                 rxd->opaque = (RXD_OPAQUE_RING_STD |
6275                                (i << RXD_OPAQUE_INDEX_SHIFT));
6276         }
6277
6278         /* Now allocate fresh SKBs for each rx ring. */
6279         for (i = 0; i < tp->rx_pending; i++) {
6280                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6281                         netdev_warn(tp->dev,
6282                                     "Using a smaller RX standard ring. Only "
6283                                     "%d out of %d buffers were allocated "
6284                                     "successfully\n", i, tp->rx_pending);
6285                         if (i == 0)
6286                                 goto initfail;
6287                         tp->rx_pending = i;
6288                         break;
6289                 }
6290         }
6291
6292         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6293                 goto done;
6294
6295         memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
6296
6297         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
6298                 goto done;
6299
6300         for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
6301                 struct tg3_rx_buffer_desc *rxd;
6302
6303                 rxd = &tpr->rx_jmb[i].std;
6304                 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6305                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6306                                   RXD_FLAG_JUMBO;
6307                 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6308                        (i << RXD_OPAQUE_INDEX_SHIFT));
6309         }
6310
6311         for (i = 0; i < tp->rx_jumbo_pending; i++) {
6312                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
6313                         netdev_warn(tp->dev,
6314                                     "Using a smaller RX jumbo ring. Only %d "
6315                                     "out of %d buffers were allocated "
6316                                     "successfully\n", i, tp->rx_jumbo_pending);
6317                         if (i == 0)
6318                                 goto initfail;
6319                         tp->rx_jumbo_pending = i;
6320                         break;
6321                 }
6322         }
6323
6324 done:
6325         return 0;
6326
6327 initfail:
6328         tg3_rx_prodring_free(tp, tpr);
6329         return -ENOMEM;
6330 }
6331
6332 static void tg3_rx_prodring_fini(struct tg3 *tp,
6333                                  struct tg3_rx_prodring_set *tpr)
6334 {
6335         kfree(tpr->rx_std_buffers);
6336         tpr->rx_std_buffers = NULL;
6337         kfree(tpr->rx_jmb_buffers);
6338         tpr->rx_jmb_buffers = NULL;
6339         if (tpr->rx_std) {
6340                 pci_free_consistent(tp->pdev, TG3_RX_STD_RING_BYTES(tp),
6341                                     tpr->rx_std, tpr->rx_std_mapping);
6342                 tpr->rx_std = NULL;
6343         }
6344         if (tpr->rx_jmb) {
6345                 pci_free_consistent(tp->pdev, TG3_RX_JMB_RING_BYTES(tp),
6346                                     tpr->rx_jmb, tpr->rx_jmb_mapping);
6347                 tpr->rx_jmb = NULL;
6348         }
6349 }
6350
6351 static int tg3_rx_prodring_init(struct tg3 *tp,
6352                                 struct tg3_rx_prodring_set *tpr)
6353 {
6354         tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
6355                                       GFP_KERNEL);
6356         if (!tpr->rx_std_buffers)
6357                 return -ENOMEM;
6358
6359         tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_STD_RING_BYTES(tp),
6360                                            &tpr->rx_std_mapping);
6361         if (!tpr->rx_std)
6362                 goto err_out;
6363
6364         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6365                 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
6366                                               GFP_KERNEL);
6367                 if (!tpr->rx_jmb_buffers)
6368                         goto err_out;
6369
6370                 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6371                                                    TG3_RX_JMB_RING_BYTES(tp),
6372                                                    &tpr->rx_jmb_mapping);
6373                 if (!tpr->rx_jmb)
6374                         goto err_out;
6375         }
6376
6377         return 0;
6378
6379 err_out:
6380         tg3_rx_prodring_fini(tp, tpr);
6381         return -ENOMEM;
6382 }
6383
6384 /* Free up pending packets in all rx/tx rings.
6385  *
6386  * The chip has been shut down and the driver detached from
6387  * the networking, so no interrupts or new tx packets will
6388  * end up in the driver.  tp->{tx,}lock is not held and we are not
6389  * in an interrupt context and thus may sleep.
6390  */
6391 static void tg3_free_rings(struct tg3 *tp)
6392 {
6393         int i, j;
6394
6395         for (j = 0; j < tp->irq_cnt; j++) {
6396                 struct tg3_napi *tnapi = &tp->napi[j];
6397
6398                 tg3_rx_prodring_free(tp, &tnapi->prodring);
6399
6400                 if (!tnapi->tx_buffers)
6401                         continue;
6402
6403                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6404                         struct ring_info *txp;
6405                         struct sk_buff *skb;
6406                         unsigned int k;
6407
6408                         txp = &tnapi->tx_buffers[i];
6409                         skb = txp->skb;
6410
6411                         if (skb == NULL) {
6412                                 i++;
6413                                 continue;
6414                         }
6415
6416                         pci_unmap_single(tp->pdev,
6417                                          dma_unmap_addr(txp, mapping),
6418                                          skb_headlen(skb),
6419                                          PCI_DMA_TODEVICE);
6420                         txp->skb = NULL;
6421
6422                         i++;
6423
6424                         for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6425                                 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6426                                 pci_unmap_page(tp->pdev,
6427                                                dma_unmap_addr(txp, mapping),
6428                                                skb_shinfo(skb)->frags[k].size,
6429                                                PCI_DMA_TODEVICE);
6430                                 i++;
6431                         }
6432
6433                         dev_kfree_skb_any(skb);
6434                 }
6435         }
6436 }
6437
6438 /* Initialize tx/rx rings for packet processing.
6439  *
6440  * The chip has been shut down and the driver detached from
6441  * the networking, so no interrupts or new tx packets will
6442  * end up in the driver.  tp->{tx,}lock are held and thus
6443  * we may not sleep.
6444  */
6445 static int tg3_init_rings(struct tg3 *tp)
6446 {
6447         int i;
6448
6449         /* Free up all the SKBs. */
6450         tg3_free_rings(tp);
6451
6452         for (i = 0; i < tp->irq_cnt; i++) {
6453                 struct tg3_napi *tnapi = &tp->napi[i];
6454
6455                 tnapi->last_tag = 0;
6456                 tnapi->last_irq_tag = 0;
6457                 tnapi->hw_status->status = 0;
6458                 tnapi->hw_status->status_tag = 0;
6459                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6460
6461                 tnapi->tx_prod = 0;
6462                 tnapi->tx_cons = 0;
6463                 if (tnapi->tx_ring)
6464                         memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6465
6466                 tnapi->rx_rcb_ptr = 0;
6467                 if (tnapi->rx_rcb)
6468                         memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6469
6470                 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
6471                         tg3_free_rings(tp);
6472                         return -ENOMEM;
6473                 }
6474         }
6475
6476         return 0;
6477 }
6478
6479 /*
6480  * Must not be invoked with interrupt sources disabled and
6481  * the hardware shutdown down.
6482  */
6483 static void tg3_free_consistent(struct tg3 *tp)
6484 {
6485         int i;
6486
6487         for (i = 0; i < tp->irq_cnt; i++) {
6488                 struct tg3_napi *tnapi = &tp->napi[i];
6489
6490                 if (tnapi->tx_ring) {
6491                         pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6492                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
6493                         tnapi->tx_ring = NULL;
6494                 }
6495
6496                 kfree(tnapi->tx_buffers);
6497                 tnapi->tx_buffers = NULL;
6498
6499                 if (tnapi->rx_rcb) {
6500                         pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6501                                             tnapi->rx_rcb,
6502                                             tnapi->rx_rcb_mapping);
6503                         tnapi->rx_rcb = NULL;
6504                 }
6505
6506                 tg3_rx_prodring_fini(tp, &tnapi->prodring);
6507
6508                 if (tnapi->hw_status) {
6509                         pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6510                                             tnapi->hw_status,
6511                                             tnapi->status_mapping);
6512                         tnapi->hw_status = NULL;
6513                 }
6514         }
6515
6516         if (tp->hw_stats) {
6517                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6518                                     tp->hw_stats, tp->stats_mapping);
6519                 tp->hw_stats = NULL;
6520         }
6521 }
6522
6523 /*
6524  * Must not be invoked with interrupt sources disabled and
6525  * the hardware shutdown down.  Can sleep.
6526  */
6527 static int tg3_alloc_consistent(struct tg3 *tp)
6528 {
6529         int i;
6530
6531         tp->hw_stats = pci_alloc_consistent(tp->pdev,
6532                                             sizeof(struct tg3_hw_stats),
6533                                             &tp->stats_mapping);
6534         if (!tp->hw_stats)
6535                 goto err_out;
6536
6537         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6538
6539         for (i = 0; i < tp->irq_cnt; i++) {
6540                 struct tg3_napi *tnapi = &tp->napi[i];
6541                 struct tg3_hw_status *sblk;
6542
6543                 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6544                                                         TG3_HW_STATUS_SIZE,
6545                                                         &tnapi->status_mapping);
6546                 if (!tnapi->hw_status)
6547                         goto err_out;
6548
6549                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6550                 sblk = tnapi->hw_status;
6551
6552                 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
6553                         goto err_out;
6554
6555                 /* If multivector TSS is enabled, vector 0 does not handle
6556                  * tx interrupts.  Don't allocate any resources for it.
6557                  */
6558                 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6559                     (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6560                         tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6561                                                     TG3_TX_RING_SIZE,
6562                                                     GFP_KERNEL);
6563                         if (!tnapi->tx_buffers)
6564                                 goto err_out;
6565
6566                         tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6567                                                               TG3_TX_RING_BYTES,
6568                                                        &tnapi->tx_desc_mapping);
6569                         if (!tnapi->tx_ring)
6570                                 goto err_out;
6571                 }
6572
6573                 /*
6574                  * When RSS is enabled, the status block format changes
6575                  * slightly.  The "rx_jumbo_consumer", "reserved",
6576                  * and "rx_mini_consumer" members get mapped to the
6577                  * other three rx return ring producer indexes.
6578                  */
6579                 switch (i) {
6580                 default:
6581                         tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6582                         break;
6583                 case 2:
6584                         tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6585                         break;
6586                 case 3:
6587                         tnapi->rx_rcb_prod_idx = &sblk->reserved;
6588                         break;
6589                 case 4:
6590                         tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6591                         break;
6592                 }
6593
6594                 /*
6595                  * If multivector RSS is enabled, vector 0 does not handle
6596                  * rx or tx interrupts.  Don't allocate any resources for it.
6597                  */
6598                 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6599                         continue;
6600
6601                 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6602                                                      TG3_RX_RCB_RING_BYTES(tp),
6603                                                      &tnapi->rx_rcb_mapping);
6604                 if (!tnapi->rx_rcb)
6605                         goto err_out;
6606
6607                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6608         }
6609
6610         return 0;
6611
6612 err_out:
6613         tg3_free_consistent(tp);
6614         return -ENOMEM;
6615 }
6616
6617 #define MAX_WAIT_CNT 1000
6618
6619 /* To stop a block, clear the enable bit and poll till it
6620  * clears.  tp->lock is held.
6621  */
6622 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6623 {
6624         unsigned int i;
6625         u32 val;
6626
6627         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6628                 switch (ofs) {
6629                 case RCVLSC_MODE:
6630                 case DMAC_MODE:
6631                 case MBFREE_MODE:
6632                 case BUFMGR_MODE:
6633                 case MEMARB_MODE:
6634                         /* We can't enable/disable these bits of the
6635                          * 5705/5750, just say success.
6636                          */
6637                         return 0;
6638
6639                 default:
6640                         break;
6641                 }
6642         }
6643
6644         val = tr32(ofs);
6645         val &= ~enable_bit;
6646         tw32_f(ofs, val);
6647
6648         for (i = 0; i < MAX_WAIT_CNT; i++) {
6649                 udelay(100);
6650                 val = tr32(ofs);
6651                 if ((val & enable_bit) == 0)
6652                         break;
6653         }
6654
6655         if (i == MAX_WAIT_CNT && !silent) {
6656                 dev_err(&tp->pdev->dev,
6657                         "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6658                         ofs, enable_bit);
6659                 return -ENODEV;
6660         }
6661
6662         return 0;
6663 }
6664
6665 /* tp->lock is held. */
6666 static int tg3_abort_hw(struct tg3 *tp, int silent)
6667 {
6668         int i, err;
6669
6670         tg3_disable_ints(tp);
6671
6672         tp->rx_mode &= ~RX_MODE_ENABLE;
6673         tw32_f(MAC_RX_MODE, tp->rx_mode);
6674         udelay(10);
6675
6676         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6677         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6678         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6679         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6680         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6681         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6682
6683         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6684         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6685         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6686         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6687         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6688         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6689         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6690
6691         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6692         tw32_f(MAC_MODE, tp->mac_mode);
6693         udelay(40);
6694
6695         tp->tx_mode &= ~TX_MODE_ENABLE;
6696         tw32_f(MAC_TX_MODE, tp->tx_mode);
6697
6698         for (i = 0; i < MAX_WAIT_CNT; i++) {
6699                 udelay(100);
6700                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6701                         break;
6702         }
6703         if (i >= MAX_WAIT_CNT) {
6704                 dev_err(&tp->pdev->dev,
6705                         "%s timed out, TX_MODE_ENABLE will not clear "
6706                         "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
6707                 err |= -ENODEV;
6708         }
6709
6710         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6711         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6712         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6713
6714         tw32(FTQ_RESET, 0xffffffff);
6715         tw32(FTQ_RESET, 0x00000000);
6716
6717         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6718         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6719
6720         for (i = 0; i < tp->irq_cnt; i++) {
6721                 struct tg3_napi *tnapi = &tp->napi[i];
6722                 if (tnapi->hw_status)
6723                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6724         }
6725         if (tp->hw_stats)
6726                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6727
6728         return err;
6729 }
6730
6731 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6732 {
6733         int i;
6734         u32 apedata;
6735
6736         /* NCSI does not support APE events */
6737         if (tp->tg3_flags3 & TG3_FLG3_APE_HAS_NCSI)
6738                 return;
6739
6740         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6741         if (apedata != APE_SEG_SIG_MAGIC)
6742                 return;
6743
6744         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6745         if (!(apedata & APE_FW_STATUS_READY))
6746                 return;
6747
6748         /* Wait for up to 1 millisecond for APE to service previous event. */
6749         for (i = 0; i < 10; i++) {
6750                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6751                         return;
6752
6753                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6754
6755                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6756                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6757                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6758
6759                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6760
6761                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6762                         break;
6763
6764                 udelay(100);
6765         }
6766
6767         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6768                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6769 }
6770
6771 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6772 {
6773         u32 event;
6774         u32 apedata;
6775
6776         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6777                 return;
6778
6779         switch (kind) {
6780         case RESET_KIND_INIT:
6781                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6782                                 APE_HOST_SEG_SIG_MAGIC);
6783                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6784                                 APE_HOST_SEG_LEN_MAGIC);
6785                 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6786                 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6787                 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6788                         APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
6789                 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6790                                 APE_HOST_BEHAV_NO_PHYLOCK);
6791                 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
6792                                     TG3_APE_HOST_DRVR_STATE_START);
6793
6794                 event = APE_EVENT_STATUS_STATE_START;
6795                 break;
6796         case RESET_KIND_SHUTDOWN:
6797                 /* With the interface we are currently using,
6798                  * APE does not track driver state.  Wiping
6799                  * out the HOST SEGMENT SIGNATURE forces
6800                  * the APE to assume OS absent status.
6801                  */
6802                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6803
6804                 if (device_may_wakeup(&tp->pdev->dev) &&
6805                     (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) {
6806                         tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
6807                                             TG3_APE_HOST_WOL_SPEED_AUTO);
6808                         apedata = TG3_APE_HOST_DRVR_STATE_WOL;
6809                 } else
6810                         apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
6811
6812                 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
6813
6814                 event = APE_EVENT_STATUS_STATE_UNLOAD;
6815                 break;
6816         case RESET_KIND_SUSPEND:
6817                 event = APE_EVENT_STATUS_STATE_SUSPEND;
6818                 break;
6819         default:
6820                 return;
6821         }
6822
6823         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6824
6825         tg3_ape_send_event(tp, event);
6826 }
6827
6828 /* tp->lock is held. */
6829 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6830 {
6831         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6832                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6833
6834         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6835                 switch (kind) {
6836                 case RESET_KIND_INIT:
6837                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6838                                       DRV_STATE_START);
6839                         break;
6840
6841                 case RESET_KIND_SHUTDOWN:
6842                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6843                                       DRV_STATE_UNLOAD);
6844                         break;
6845
6846                 case RESET_KIND_SUSPEND:
6847                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6848                                       DRV_STATE_SUSPEND);
6849                         break;
6850
6851                 default:
6852                         break;
6853                 }
6854         }
6855
6856         if (kind == RESET_KIND_INIT ||
6857             kind == RESET_KIND_SUSPEND)
6858                 tg3_ape_driver_state_change(tp, kind);
6859 }
6860
6861 /* tp->lock is held. */
6862 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6863 {
6864         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6865                 switch (kind) {
6866                 case RESET_KIND_INIT:
6867                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6868                                       DRV_STATE_START_DONE);
6869                         break;
6870
6871                 case RESET_KIND_SHUTDOWN:
6872                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6873                                       DRV_STATE_UNLOAD_DONE);
6874                         break;
6875
6876                 default:
6877                         break;
6878                 }
6879         }
6880
6881         if (kind == RESET_KIND_SHUTDOWN)
6882                 tg3_ape_driver_state_change(tp, kind);
6883 }
6884
6885 /* tp->lock is held. */
6886 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6887 {
6888         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6889                 switch (kind) {
6890                 case RESET_KIND_INIT:
6891                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6892                                       DRV_STATE_START);
6893                         break;
6894
6895                 case RESET_KIND_SHUTDOWN:
6896                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6897                                       DRV_STATE_UNLOAD);
6898                         break;
6899
6900                 case RESET_KIND_SUSPEND:
6901                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6902                                       DRV_STATE_SUSPEND);
6903                         break;
6904
6905                 default:
6906                         break;
6907                 }
6908         }
6909 }
6910
6911 static int tg3_poll_fw(struct tg3 *tp)
6912 {
6913         int i;
6914         u32 val;
6915
6916         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6917                 /* Wait up to 20ms for init done. */
6918                 for (i = 0; i < 200; i++) {
6919                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6920                                 return 0;
6921                         udelay(100);
6922                 }
6923                 return -ENODEV;
6924         }
6925
6926         /* Wait for firmware initialization to complete. */
6927         for (i = 0; i < 100000; i++) {
6928                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6929                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6930                         break;
6931                 udelay(10);
6932         }
6933
6934         /* Chip might not be fitted with firmware.  Some Sun onboard
6935          * parts are configured like that.  So don't signal the timeout
6936          * of the above loop as an error, but do report the lack of
6937          * running firmware once.
6938          */
6939         if (i >= 100000 &&
6940             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6941                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6942
6943                 netdev_info(tp->dev, "No firmware running\n");
6944         }
6945
6946         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6947                 /* The 57765 A0 needs a little more
6948                  * time to do some important work.
6949                  */
6950                 mdelay(10);
6951         }
6952
6953         return 0;
6954 }
6955
6956 /* Save PCI command register before chip reset */
6957 static void tg3_save_pci_state(struct tg3 *tp)
6958 {
6959         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6960 }
6961
6962 /* Restore PCI state after chip reset */
6963 static void tg3_restore_pci_state(struct tg3 *tp)
6964 {
6965         u32 val;
6966
6967         /* Re-enable indirect register accesses. */
6968         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6969                                tp->misc_host_ctrl);
6970
6971         /* Set MAX PCI retry to zero. */
6972         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6973         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6974             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6975                 val |= PCISTATE_RETRY_SAME_DMA;
6976         /* Allow reads and writes to the APE register and memory space. */
6977         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6978                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6979                        PCISTATE_ALLOW_APE_SHMEM_WR |
6980                        PCISTATE_ALLOW_APE_PSPACE_WR;
6981         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6982
6983         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6984
6985         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6986                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6987                         pcie_set_readrq(tp->pdev, 4096);
6988                 else {
6989                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6990                                               tp->pci_cacheline_sz);
6991                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6992                                               tp->pci_lat_timer);
6993                 }
6994         }
6995
6996         /* Make sure PCI-X relaxed ordering bit is clear. */
6997         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6998                 u16 pcix_cmd;
6999
7000                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7001                                      &pcix_cmd);
7002                 pcix_cmd &= ~PCI_X_CMD_ERO;
7003                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7004                                       pcix_cmd);
7005         }
7006
7007         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
7008
7009                 /* Chip reset on 5780 will reset MSI enable bit,
7010                  * so need to restore it.
7011                  */
7012                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7013                         u16 ctrl;
7014
7015                         pci_read_config_word(tp->pdev,
7016                                              tp->msi_cap + PCI_MSI_FLAGS,
7017                                              &ctrl);
7018                         pci_write_config_word(tp->pdev,
7019                                               tp->msi_cap + PCI_MSI_FLAGS,
7020                                               ctrl | PCI_MSI_FLAGS_ENABLE);
7021                         val = tr32(MSGINT_MODE);
7022                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
7023                 }
7024         }
7025 }
7026
7027 static void tg3_stop_fw(struct tg3 *);
7028
7029 /* tp->lock is held. */
7030 static int tg3_chip_reset(struct tg3 *tp)
7031 {
7032         u32 val;
7033         void (*write_op)(struct tg3 *, u32, u32);
7034         int i, err;
7035
7036         tg3_nvram_lock(tp);
7037
7038         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
7039
7040         /* No matching tg3_nvram_unlock() after this because
7041          * chip reset below will undo the nvram lock.
7042          */
7043         tp->nvram_lock_cnt = 0;
7044
7045         /* GRC_MISC_CFG core clock reset will clear the memory
7046          * enable bit in PCI register 4 and the MSI enable bit
7047          * on some chips, so we save relevant registers here.
7048          */
7049         tg3_save_pci_state(tp);
7050
7051         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
7052             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
7053                 tw32(GRC_FASTBOOT_PC, 0);
7054
7055         /*
7056          * We must avoid the readl() that normally takes place.
7057          * It locks machines, causes machine checks, and other
7058          * fun things.  So, temporarily disable the 5701
7059          * hardware workaround, while we do the reset.
7060          */
7061         write_op = tp->write32;
7062         if (write_op == tg3_write_flush_reg32)
7063                 tp->write32 = tg3_write32;
7064
7065         /* Prevent the irq handler from reading or writing PCI registers
7066          * during chip reset when the memory enable bit in the PCI command
7067          * register may be cleared.  The chip does not generate interrupt
7068          * at this time, but the irq handler may still be called due to irq
7069          * sharing or irqpoll.
7070          */
7071         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
7072         for (i = 0; i < tp->irq_cnt; i++) {
7073                 struct tg3_napi *tnapi = &tp->napi[i];
7074                 if (tnapi->hw_status) {
7075                         tnapi->hw_status->status = 0;
7076                         tnapi->hw_status->status_tag = 0;
7077                 }
7078                 tnapi->last_tag = 0;
7079                 tnapi->last_irq_tag = 0;
7080         }
7081         smp_mb();
7082
7083         for (i = 0; i < tp->irq_cnt; i++)
7084                 synchronize_irq(tp->napi[i].irq_vec);
7085
7086         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7087                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7088                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7089         }
7090
7091         /* do the reset */
7092         val = GRC_MISC_CFG_CORECLK_RESET;
7093
7094         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
7095                 /* Force PCIe 1.0a mode */
7096                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7097                     !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
7098                     tr32(TG3_PCIE_PHY_TSTCTL) ==
7099                     (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
7100                         tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
7101
7102                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
7103                         tw32(GRC_MISC_CFG, (1 << 29));
7104                         val |= (1 << 29);
7105                 }
7106         }
7107
7108         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7109                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
7110                 tw32(GRC_VCPU_EXT_CTRL,
7111                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
7112         }
7113
7114         /* Manage gphy power for all CPMU absent PCIe devices. */
7115         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7116             !(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7117                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
7118
7119         tw32(GRC_MISC_CFG, val);
7120
7121         /* restore 5701 hardware bug workaround write method */
7122         tp->write32 = write_op;
7123
7124         /* Unfortunately, we have to delay before the PCI read back.
7125          * Some 575X chips even will not respond to a PCI cfg access
7126          * when the reset command is given to the chip.
7127          *
7128          * How do these hardware designers expect things to work
7129          * properly if the PCI write is posted for a long period
7130          * of time?  It is always necessary to have some method by
7131          * which a register read back can occur to push the write
7132          * out which does the reset.
7133          *
7134          * For most tg3 variants the trick below was working.
7135          * Ho hum...
7136          */
7137         udelay(120);
7138
7139         /* Flush PCI posted writes.  The normal MMIO registers
7140          * are inaccessible at this time so this is the only
7141          * way to make this reliably (actually, this is no longer
7142          * the case, see above).  I tried to use indirect
7143          * register read/write but this upset some 5701 variants.
7144          */
7145         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
7146
7147         udelay(120);
7148
7149         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
7150                 u16 val16;
7151
7152                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
7153                         int i;
7154                         u32 cfg_val;
7155
7156                         /* Wait for link training to complete.  */
7157                         for (i = 0; i < 5000; i++)
7158                                 udelay(100);
7159
7160                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
7161                         pci_write_config_dword(tp->pdev, 0xc4,
7162                                                cfg_val | (1 << 15));
7163                 }
7164
7165                 /* Clear the "no snoop" and "relaxed ordering" bits. */
7166                 pci_read_config_word(tp->pdev,
7167                                      tp->pcie_cap + PCI_EXP_DEVCTL,
7168                                      &val16);
7169                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
7170                            PCI_EXP_DEVCTL_NOSNOOP_EN);
7171                 /*
7172                  * Older PCIe devices only support the 128 byte
7173                  * MPS setting.  Enforce the restriction.
7174                  */
7175                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7176                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
7177                 pci_write_config_word(tp->pdev,
7178                                       tp->pcie_cap + PCI_EXP_DEVCTL,
7179                                       val16);
7180
7181                 pcie_set_readrq(tp->pdev, 4096);
7182
7183                 /* Clear error status */
7184                 pci_write_config_word(tp->pdev,
7185                                       tp->pcie_cap + PCI_EXP_DEVSTA,
7186                                       PCI_EXP_DEVSTA_CED |
7187                                       PCI_EXP_DEVSTA_NFED |
7188                                       PCI_EXP_DEVSTA_FED |
7189                                       PCI_EXP_DEVSTA_URD);
7190         }
7191
7192         tg3_restore_pci_state(tp);
7193
7194         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
7195
7196         val = 0;
7197         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
7198                 val = tr32(MEMARB_MODE);
7199         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7200
7201         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7202                 tg3_stop_fw(tp);
7203                 tw32(0x5000, 0x400);
7204         }
7205
7206         tw32(GRC_MODE, tp->grc_mode);
7207
7208         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
7209                 val = tr32(0xc4);
7210
7211                 tw32(0xc4, val | (1 << 15));
7212         }
7213
7214         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7215             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7216                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7217                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7218                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7219                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7220         }
7221
7222         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
7223                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
7224                 tw32_f(MAC_MODE, tp->mac_mode);
7225         } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
7226                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
7227                 tw32_f(MAC_MODE, tp->mac_mode);
7228         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7229                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
7230                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
7231                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
7232                 tw32_f(MAC_MODE, tp->mac_mode);
7233         } else
7234                 tw32_f(MAC_MODE, 0);
7235         udelay(40);
7236
7237         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7238
7239         err = tg3_poll_fw(tp);
7240         if (err)
7241                 return err;
7242
7243         tg3_mdio_start(tp);
7244
7245         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
7246             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7247             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7248             !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
7249                 val = tr32(0x7c00);
7250
7251                 tw32(0x7c00, val | (1 << 25));
7252         }
7253
7254         /* Reprobe ASF enable state.  */
7255         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7256         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7257         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7258         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7259                 u32 nic_cfg;
7260
7261                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7262                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7263                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7264                         tp->last_event_jiffies = jiffies;
7265                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7266                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7267                 }
7268         }
7269
7270         return 0;
7271 }
7272
7273 /* tp->lock is held. */
7274 static void tg3_stop_fw(struct tg3 *tp)
7275 {
7276         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7277            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7278                 /* Wait for RX cpu to ACK the previous event. */
7279                 tg3_wait_for_event_ack(tp);
7280
7281                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7282
7283                 tg3_generate_fw_event(tp);
7284
7285                 /* Wait for RX cpu to ACK this event. */
7286                 tg3_wait_for_event_ack(tp);
7287         }
7288 }
7289
7290 /* tp->lock is held. */
7291 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7292 {
7293         int err;
7294
7295         tg3_stop_fw(tp);
7296
7297         tg3_write_sig_pre_reset(tp, kind);
7298
7299         tg3_abort_hw(tp, silent);
7300         err = tg3_chip_reset(tp);
7301
7302         __tg3_set_mac_addr(tp, 0);
7303
7304         tg3_write_sig_legacy(tp, kind);
7305         tg3_write_sig_post_reset(tp, kind);
7306
7307         if (err)
7308                 return err;
7309
7310         return 0;
7311 }
7312
7313 #define RX_CPU_SCRATCH_BASE     0x30000
7314 #define RX_CPU_SCRATCH_SIZE     0x04000
7315 #define TX_CPU_SCRATCH_BASE     0x34000
7316 #define TX_CPU_SCRATCH_SIZE     0x04000
7317
7318 /* tp->lock is held. */
7319 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7320 {
7321         int i;
7322
7323         BUG_ON(offset == TX_CPU_BASE &&
7324             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7325
7326         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7327                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7328
7329                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7330                 return 0;
7331         }
7332         if (offset == RX_CPU_BASE) {
7333                 for (i = 0; i < 10000; i++) {
7334                         tw32(offset + CPU_STATE, 0xffffffff);
7335                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7336                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7337                                 break;
7338                 }
7339
7340                 tw32(offset + CPU_STATE, 0xffffffff);
7341                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
7342                 udelay(10);
7343         } else {
7344                 for (i = 0; i < 10000; i++) {
7345                         tw32(offset + CPU_STATE, 0xffffffff);
7346                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7347                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7348                                 break;
7349                 }
7350         }
7351
7352         if (i >= 10000) {
7353                 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7354                            __func__, offset == RX_CPU_BASE ? "RX" : "TX");
7355                 return -ENODEV;
7356         }
7357
7358         /* Clear firmware's nvram arbitration. */
7359         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7360                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7361         return 0;
7362 }
7363
7364 struct fw_info {
7365         unsigned int fw_base;
7366         unsigned int fw_len;
7367         const __be32 *fw_data;
7368 };
7369
7370 /* tp->lock is held. */
7371 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7372                                  int cpu_scratch_size, struct fw_info *info)
7373 {
7374         int err, lock_err, i;
7375         void (*write_op)(struct tg3 *, u32, u32);
7376
7377         if (cpu_base == TX_CPU_BASE &&
7378             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7379                 netdev_err(tp->dev,
7380                            "%s: Trying to load TX cpu firmware which is 5705\n",
7381                            __func__);
7382                 return -EINVAL;
7383         }
7384
7385         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7386                 write_op = tg3_write_mem;
7387         else
7388                 write_op = tg3_write_indirect_reg32;
7389
7390         /* It is possible that bootcode is still loading at this point.
7391          * Get the nvram lock first before halting the cpu.
7392          */
7393         lock_err = tg3_nvram_lock(tp);
7394         err = tg3_halt_cpu(tp, cpu_base);
7395         if (!lock_err)
7396                 tg3_nvram_unlock(tp);
7397         if (err)
7398                 goto out;
7399
7400         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7401                 write_op(tp, cpu_scratch_base + i, 0);
7402         tw32(cpu_base + CPU_STATE, 0xffffffff);
7403         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7404         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7405                 write_op(tp, (cpu_scratch_base +
7406                               (info->fw_base & 0xffff) +
7407                               (i * sizeof(u32))),
7408                               be32_to_cpu(info->fw_data[i]));
7409
7410         err = 0;
7411
7412 out:
7413         return err;
7414 }
7415
7416 /* tp->lock is held. */
7417 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7418 {
7419         struct fw_info info;
7420         const __be32 *fw_data;
7421         int err, i;
7422
7423         fw_data = (void *)tp->fw->data;
7424
7425         /* Firmware blob starts with version numbers, followed by
7426            start address and length. We are setting complete length.
7427            length = end_address_of_bss - start_address_of_text.
7428            Remainder is the blob to be loaded contiguously
7429            from start address. */
7430
7431         info.fw_base = be32_to_cpu(fw_data[1]);
7432         info.fw_len = tp->fw->size - 12;
7433         info.fw_data = &fw_data[3];
7434
7435         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7436                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7437                                     &info);
7438         if (err)
7439                 return err;
7440
7441         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7442                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7443                                     &info);
7444         if (err)
7445                 return err;
7446
7447         /* Now startup only the RX cpu. */
7448         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7449         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7450
7451         for (i = 0; i < 5; i++) {
7452                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7453                         break;
7454                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7455                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
7456                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7457                 udelay(1000);
7458         }
7459         if (i >= 5) {
7460                 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7461                            "should be %08x\n", __func__,
7462                            tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
7463                 return -ENODEV;
7464         }
7465         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7466         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
7467
7468         return 0;
7469 }
7470
7471 /* 5705 needs a special version of the TSO firmware.  */
7472
7473 /* tp->lock is held. */
7474 static int tg3_load_tso_firmware(struct tg3 *tp)
7475 {
7476         struct fw_info info;
7477         const __be32 *fw_data;
7478         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7479         int err, i;
7480
7481         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7482                 return 0;
7483
7484         fw_data = (void *)tp->fw->data;
7485
7486         /* Firmware blob starts with version numbers, followed by
7487            start address and length. We are setting complete length.
7488            length = end_address_of_bss - start_address_of_text.
7489            Remainder is the blob to be loaded contiguously
7490            from start address. */
7491
7492         info.fw_base = be32_to_cpu(fw_data[1]);
7493         cpu_scratch_size = tp->fw_len;
7494         info.fw_len = tp->fw->size - 12;
7495         info.fw_data = &fw_data[3];
7496
7497         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7498                 cpu_base = RX_CPU_BASE;
7499                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7500         } else {
7501                 cpu_base = TX_CPU_BASE;
7502                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7503                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7504         }
7505
7506         err = tg3_load_firmware_cpu(tp, cpu_base,
7507                                     cpu_scratch_base, cpu_scratch_size,
7508                                     &info);
7509         if (err)
7510                 return err;
7511
7512         /* Now startup the cpu. */
7513         tw32(cpu_base + CPU_STATE, 0xffffffff);
7514         tw32_f(cpu_base + CPU_PC, info.fw_base);
7515
7516         for (i = 0; i < 5; i++) {
7517                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7518                         break;
7519                 tw32(cpu_base + CPU_STATE, 0xffffffff);
7520                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
7521                 tw32_f(cpu_base + CPU_PC, info.fw_base);
7522                 udelay(1000);
7523         }
7524         if (i >= 5) {
7525                 netdev_err(tp->dev,
7526                            "%s fails to set CPU PC, is %08x should be %08x\n",
7527                            __func__, tr32(cpu_base + CPU_PC), info.fw_base);
7528                 return -ENODEV;
7529         }
7530         tw32(cpu_base + CPU_STATE, 0xffffffff);
7531         tw32_f(cpu_base + CPU_MODE,  0x00000000);
7532         return 0;
7533 }
7534
7535
7536 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7537 {
7538         struct tg3 *tp = netdev_priv(dev);
7539         struct sockaddr *addr = p;
7540         int err = 0, skip_mac_1 = 0;
7541
7542         if (!is_valid_ether_addr(addr->sa_data))
7543                 return -EINVAL;
7544
7545         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7546
7547         if (!netif_running(dev))
7548                 return 0;
7549
7550         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7551                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7552
7553                 addr0_high = tr32(MAC_ADDR_0_HIGH);
7554                 addr0_low = tr32(MAC_ADDR_0_LOW);
7555                 addr1_high = tr32(MAC_ADDR_1_HIGH);
7556                 addr1_low = tr32(MAC_ADDR_1_LOW);
7557
7558                 /* Skip MAC addr 1 if ASF is using it. */
7559                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7560                     !(addr1_high == 0 && addr1_low == 0))
7561                         skip_mac_1 = 1;
7562         }
7563         spin_lock_bh(&tp->lock);
7564         __tg3_set_mac_addr(tp, skip_mac_1);
7565         spin_unlock_bh(&tp->lock);
7566
7567         return err;
7568 }
7569
7570 /* tp->lock is held. */
7571 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7572                            dma_addr_t mapping, u32 maxlen_flags,
7573                            u32 nic_addr)
7574 {
7575         tg3_write_mem(tp,
7576                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7577                       ((u64) mapping >> 32));
7578         tg3_write_mem(tp,
7579                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7580                       ((u64) mapping & 0xffffffff));
7581         tg3_write_mem(tp,
7582                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7583                        maxlen_flags);
7584
7585         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7586                 tg3_write_mem(tp,
7587                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7588                               nic_addr);
7589 }
7590
7591 static void __tg3_set_rx_mode(struct net_device *);
7592 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7593 {
7594         int i;
7595
7596         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7597                 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7598                 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7599                 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7600         } else {
7601                 tw32(HOSTCC_TXCOL_TICKS, 0);
7602                 tw32(HOSTCC_TXMAX_FRAMES, 0);
7603                 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7604         }
7605
7606         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
7607                 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7608                 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7609                 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7610         } else {
7611                 tw32(HOSTCC_RXCOL_TICKS, 0);
7612                 tw32(HOSTCC_RXMAX_FRAMES, 0);
7613                 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7614         }
7615
7616         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7617                 u32 val = ec->stats_block_coalesce_usecs;
7618
7619                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7620                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7621
7622                 if (!netif_carrier_ok(tp->dev))
7623                         val = 0;
7624
7625                 tw32(HOSTCC_STAT_COAL_TICKS, val);
7626         }
7627
7628         for (i = 0; i < tp->irq_cnt - 1; i++) {
7629                 u32 reg;
7630
7631                 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7632                 tw32(reg, ec->rx_coalesce_usecs);
7633                 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7634                 tw32(reg, ec->rx_max_coalesced_frames);
7635                 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7636                 tw32(reg, ec->rx_max_coalesced_frames_irq);
7637
7638                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7639                         reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7640                         tw32(reg, ec->tx_coalesce_usecs);
7641                         reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7642                         tw32(reg, ec->tx_max_coalesced_frames);
7643                         reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7644                         tw32(reg, ec->tx_max_coalesced_frames_irq);
7645                 }
7646         }
7647
7648         for (; i < tp->irq_max - 1; i++) {
7649                 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7650                 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7651                 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7652
7653                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7654                         tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7655                         tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7656                         tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7657                 }
7658         }
7659 }
7660
7661 /* tp->lock is held. */
7662 static void tg3_rings_reset(struct tg3 *tp)
7663 {
7664         int i;
7665         u32 stblk, txrcb, rxrcb, limit;
7666         struct tg3_napi *tnapi = &tp->napi[0];
7667
7668         /* Disable all transmit rings but the first. */
7669         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7670                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7671         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7672                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7673                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
7674         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7675                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7676         else
7677                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7678
7679         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7680              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7681                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7682                               BDINFO_FLAGS_DISABLED);
7683
7684
7685         /* Disable all receive return rings but the first. */
7686         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7687             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7688                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7689         else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7690                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7691         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7692                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7693                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7694         else
7695                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7696
7697         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7698              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7699                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7700                               BDINFO_FLAGS_DISABLED);
7701
7702         /* Disable interrupts */
7703         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7704
7705         /* Zero mailbox registers. */
7706         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7707                 for (i = 1; i < tp->irq_max; i++) {
7708                         tp->napi[i].tx_prod = 0;
7709                         tp->napi[i].tx_cons = 0;
7710                         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7711                                 tw32_mailbox(tp->napi[i].prodmbox, 0);
7712                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
7713                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7714                 }
7715                 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7716                         tw32_mailbox(tp->napi[0].prodmbox, 0);
7717         } else {
7718                 tp->napi[0].tx_prod = 0;
7719                 tp->napi[0].tx_cons = 0;
7720                 tw32_mailbox(tp->napi[0].prodmbox, 0);
7721                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7722         }
7723
7724         /* Make sure the NIC-based send BD rings are disabled. */
7725         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7726                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7727                 for (i = 0; i < 16; i++)
7728                         tw32_tx_mbox(mbox + i * 8, 0);
7729         }
7730
7731         txrcb = NIC_SRAM_SEND_RCB;
7732         rxrcb = NIC_SRAM_RCV_RET_RCB;
7733
7734         /* Clear status block in ram. */
7735         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7736
7737         /* Set status block DMA address */
7738         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7739              ((u64) tnapi->status_mapping >> 32));
7740         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7741              ((u64) tnapi->status_mapping & 0xffffffff));
7742
7743         if (tnapi->tx_ring) {
7744                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7745                                (TG3_TX_RING_SIZE <<
7746                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7747                                NIC_SRAM_TX_BUFFER_DESC);
7748                 txrcb += TG3_BDINFO_SIZE;
7749         }
7750
7751         if (tnapi->rx_rcb) {
7752                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7753                                (tp->rx_ret_ring_mask + 1) <<
7754                                 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
7755                 rxrcb += TG3_BDINFO_SIZE;
7756         }
7757
7758         stblk = HOSTCC_STATBLCK_RING1;
7759
7760         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7761                 u64 mapping = (u64)tnapi->status_mapping;
7762                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7763                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7764
7765                 /* Clear status block in ram. */
7766                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7767
7768                 if (tnapi->tx_ring) {
7769                         tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7770                                        (TG3_TX_RING_SIZE <<
7771                                         BDINFO_FLAGS_MAXLEN_SHIFT),
7772                                        NIC_SRAM_TX_BUFFER_DESC);
7773                         txrcb += TG3_BDINFO_SIZE;
7774                 }
7775
7776                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7777                                ((tp->rx_ret_ring_mask + 1) <<
7778                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7779
7780                 stblk += 8;
7781                 rxrcb += TG3_BDINFO_SIZE;
7782         }
7783 }
7784
7785 /* tp->lock is held. */
7786 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7787 {
7788         u32 val, rdmac_mode;
7789         int i, err, limit;
7790         struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
7791
7792         tg3_disable_ints(tp);
7793
7794         tg3_stop_fw(tp);
7795
7796         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7797
7798         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
7799                 tg3_abort_hw(tp, 1);
7800
7801         if (reset_phy)
7802                 tg3_phy_reset(tp);
7803
7804         err = tg3_chip_reset(tp);
7805         if (err)
7806                 return err;
7807
7808         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7809
7810         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7811                 val = tr32(TG3_CPMU_CTRL);
7812                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7813                 tw32(TG3_CPMU_CTRL, val);
7814
7815                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7816                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7817                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7818                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7819
7820                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7821                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7822                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7823                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7824
7825                 val = tr32(TG3_CPMU_HST_ACC);
7826                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7827                 val |= CPMU_HST_ACC_MACCLK_6_25;
7828                 tw32(TG3_CPMU_HST_ACC, val);
7829         }
7830
7831         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7832                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7833                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7834                        PCIE_PWR_MGMT_L1_THRESH_4MS;
7835                 tw32(PCIE_PWR_MGMT_THRESH, val);
7836
7837                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7838                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7839
7840                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7841
7842                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7843                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7844         }
7845
7846         if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7847                 u32 grc_mode = tr32(GRC_MODE);
7848
7849                 /* Access the lower 1K of PL PCIE block registers. */
7850                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7851                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7852
7853                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7854                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7855                      val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7856
7857                 tw32(GRC_MODE, grc_mode);
7858         }
7859
7860         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
7861                 u32 grc_mode = tr32(GRC_MODE);
7862
7863                 /* Access the lower 1K of PL PCIE block registers. */
7864                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7865                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7866
7867                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5);
7868                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
7869                      val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
7870
7871                 tw32(GRC_MODE, grc_mode);
7872
7873                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7874                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7875                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7876                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7877         }
7878
7879         /* Enable MAC control of LPI */
7880         if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
7881                 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL,
7882                        TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
7883                        TG3_CPMU_EEE_LNKIDL_UART_IDL);
7884
7885                 tw32_f(TG3_CPMU_EEE_CTRL,
7886                        TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
7887
7888                 tw32_f(TG3_CPMU_EEE_MODE,
7889                        TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
7890                        TG3_CPMU_EEEMD_LPI_IN_TX |
7891                        TG3_CPMU_EEEMD_LPI_IN_RX |
7892                        TG3_CPMU_EEEMD_EEE_ENABLE);
7893         }
7894
7895         /* This works around an issue with Athlon chipsets on
7896          * B3 tigon3 silicon.  This bit has no effect on any
7897          * other revision.  But do not set this on PCI Express
7898          * chips and don't even touch the clocks if the CPMU is present.
7899          */
7900         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7901                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7902                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7903                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7904         }
7905
7906         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7907             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7908                 val = tr32(TG3PCI_PCISTATE);
7909                 val |= PCISTATE_RETRY_SAME_DMA;
7910                 tw32(TG3PCI_PCISTATE, val);
7911         }
7912
7913         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7914                 /* Allow reads and writes to the
7915                  * APE register and memory space.
7916                  */
7917                 val = tr32(TG3PCI_PCISTATE);
7918                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7919                        PCISTATE_ALLOW_APE_SHMEM_WR |
7920                        PCISTATE_ALLOW_APE_PSPACE_WR;
7921                 tw32(TG3PCI_PCISTATE, val);
7922         }
7923
7924         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7925                 /* Enable some hw fixes.  */
7926                 val = tr32(TG3PCI_MSI_DATA);
7927                 val |= (1 << 26) | (1 << 28) | (1 << 29);
7928                 tw32(TG3PCI_MSI_DATA, val);
7929         }
7930
7931         /* Descriptor ring init may make accesses to the
7932          * NIC SRAM area to setup the TX descriptors, so we
7933          * can only do this after the hardware has been
7934          * successfully reset.
7935          */
7936         err = tg3_init_rings(tp);
7937         if (err)
7938                 return err;
7939
7940         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
7941                 val = tr32(TG3PCI_DMA_RW_CTRL) &
7942                       ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7943                 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
7944                         val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
7945                 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7946         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7947                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7948                 /* This value is determined during the probe time DMA
7949                  * engine test, tg3_test_dma.
7950                  */
7951                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7952         }
7953
7954         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7955                           GRC_MODE_4X_NIC_SEND_RINGS |
7956                           GRC_MODE_NO_TX_PHDR_CSUM |
7957                           GRC_MODE_NO_RX_PHDR_CSUM);
7958         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7959
7960         /* Pseudo-header checksum is done by hardware logic and not
7961          * the offload processers, so make the chip do the pseudo-
7962          * header checksums on receive.  For transmit it is more
7963          * convenient to do the pseudo-header checksum in software
7964          * as Linux does that on transmit for us in all cases.
7965          */
7966         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7967
7968         tw32(GRC_MODE,
7969              tp->grc_mode |
7970              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7971
7972         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7973         val = tr32(GRC_MISC_CFG);
7974         val &= ~0xff;
7975         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7976         tw32(GRC_MISC_CFG, val);
7977
7978         /* Initialize MBUF/DESC pool. */
7979         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7980                 /* Do nothing.  */
7981         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7982                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7983                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7984                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7985                 else
7986                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7987                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7988                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7989         } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7990                 int fw_len;
7991
7992                 fw_len = tp->fw_len;
7993                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7994                 tw32(BUFMGR_MB_POOL_ADDR,
7995                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7996                 tw32(BUFMGR_MB_POOL_SIZE,
7997                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7998         }
7999
8000         if (tp->dev->mtu <= ETH_DATA_LEN) {
8001                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8002                      tp->bufmgr_config.mbuf_read_dma_low_water);
8003                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8004                      tp->bufmgr_config.mbuf_mac_rx_low_water);
8005                 tw32(BUFMGR_MB_HIGH_WATER,
8006                      tp->bufmgr_config.mbuf_high_water);
8007         } else {
8008                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8009                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
8010                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8011                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
8012                 tw32(BUFMGR_MB_HIGH_WATER,
8013                      tp->bufmgr_config.mbuf_high_water_jumbo);
8014         }
8015         tw32(BUFMGR_DMA_LOW_WATER,
8016              tp->bufmgr_config.dma_low_water);
8017         tw32(BUFMGR_DMA_HIGH_WATER,
8018              tp->bufmgr_config.dma_high_water);
8019
8020         val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
8021         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8022                 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
8023         tw32(BUFMGR_MODE, val);
8024         for (i = 0; i < 2000; i++) {
8025                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
8026                         break;
8027                 udelay(10);
8028         }
8029         if (i >= 2000) {
8030                 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
8031                 return -ENODEV;
8032         }
8033
8034         /* Setup replenish threshold. */
8035         val = tp->rx_pending / 8;
8036         if (val == 0)
8037                 val = 1;
8038         else if (val > tp->rx_std_max_post)
8039                 val = tp->rx_std_max_post;
8040         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8041                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
8042                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
8043
8044                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
8045                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
8046         }
8047
8048         tw32(RCVBDI_STD_THRESH, val);
8049
8050         /* Initialize TG3_BDINFO's at:
8051          *  RCVDBDI_STD_BD:     standard eth size rx ring
8052          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
8053          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
8054          *
8055          * like so:
8056          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
8057          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
8058          *                              ring attribute flags
8059          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
8060          *
8061          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
8062          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
8063          *
8064          * The size of each ring is fixed in the firmware, but the location is
8065          * configurable.
8066          */
8067         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8068              ((u64) tpr->rx_std_mapping >> 32));
8069         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8070              ((u64) tpr->rx_std_mapping & 0xffffffff));
8071         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8072             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
8073                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
8074                      NIC_SRAM_RX_BUFFER_DESC);
8075
8076         /* Disable the mini ring */
8077         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8078                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
8079                      BDINFO_FLAGS_DISABLED);
8080
8081         /* Program the jumbo buffer descriptor ring control
8082          * blocks on those devices that have them.
8083          */
8084         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
8085             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8086                 /* Setup replenish threshold. */
8087                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
8088
8089                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
8090                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8091                              ((u64) tpr->rx_jmb_mapping >> 32));
8092                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8093                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
8094                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8095                              (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
8096                              BDINFO_FLAGS_USE_EXT_RECV);
8097                         if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) ||
8098                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8099                                 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
8100                                      NIC_SRAM_RX_JUMBO_BUFFER_DESC);
8101                 } else {
8102                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8103                              BDINFO_FLAGS_DISABLED);
8104                 }
8105
8106                 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
8107                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8108                                 val = RX_STD_MAX_SIZE_5705;
8109                         else
8110                                 val = RX_STD_MAX_SIZE_5717;
8111                         val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
8112                         val |= (TG3_RX_STD_DMA_SZ << 2);
8113                 } else
8114                         val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
8115         } else
8116                 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
8117
8118         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
8119
8120         tpr->rx_std_prod_idx = tp->rx_pending;
8121         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
8122
8123         tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
8124                           tp->rx_jumbo_pending : 0;
8125         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
8126
8127         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
8128                 tw32(STD_REPLENISH_LWM, 32);
8129                 tw32(JMB_REPLENISH_LWM, 16);
8130         }
8131
8132         tg3_rings_reset(tp);
8133
8134         /* Initialize MAC address and backoff seed. */
8135         __tg3_set_mac_addr(tp, 0);
8136
8137         /* MTU + ethernet header + FCS + optional VLAN tag */
8138         tw32(MAC_RX_MTU_SIZE,
8139              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
8140
8141         /* The slot time is changed by tg3_setup_phy if we
8142          * run at gigabit with half duplex.
8143          */
8144         tw32(MAC_TX_LENGTHS,
8145              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
8146              (6 << TX_LENGTHS_IPG_SHIFT) |
8147              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
8148
8149         /* Receive rules. */
8150         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
8151         tw32(RCVLPC_CONFIG, 0x0181);
8152
8153         /* Calculate RDMAC_MODE setting early, we need it to determine
8154          * the RCVLPC_STATE_ENABLE mask.
8155          */
8156         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
8157                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
8158                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
8159                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
8160                       RDMAC_MODE_LNGREAD_ENAB);
8161
8162         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8163             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8164                 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
8165
8166         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8167             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8168             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8169                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
8170                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
8171                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
8172
8173         /* If statement applies to 5705 and 5750 PCI devices only */
8174         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8175              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8176             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
8177                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
8178                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
8179                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
8180                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8181                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
8182                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8183                 }
8184         }
8185
8186         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
8187                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8188
8189         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8190                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8191
8192         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
8193             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8194             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8195                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
8196
8197         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8198             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8199             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8200             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
8201             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
8202                 val = tr32(TG3_RDMA_RSRVCTRL_REG);
8203                 tw32(TG3_RDMA_RSRVCTRL_REG,
8204                      val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
8205         }
8206
8207         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
8208                 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
8209                 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val |
8210                      TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
8211                      TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
8212         }
8213
8214         /* Receive/send statistics. */
8215         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
8216                 val = tr32(RCVLPC_STATS_ENABLE);
8217                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8218                 tw32(RCVLPC_STATS_ENABLE, val);
8219         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8220                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8221                 val = tr32(RCVLPC_STATS_ENABLE);
8222                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8223                 tw32(RCVLPC_STATS_ENABLE, val);
8224         } else {
8225                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8226         }
8227         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8228         tw32(SNDDATAI_STATSENAB, 0xffffff);
8229         tw32(SNDDATAI_STATSCTRL,
8230              (SNDDATAI_SCTRL_ENABLE |
8231               SNDDATAI_SCTRL_FASTUPD));
8232
8233         /* Setup host coalescing engine. */
8234         tw32(HOSTCC_MODE, 0);
8235         for (i = 0; i < 2000; i++) {
8236                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8237                         break;
8238                 udelay(10);
8239         }
8240
8241         __tg3_set_coalesce(tp, &tp->coal);
8242
8243         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8244                 /* Status/statistics block address.  See tg3_timer,
8245                  * the tg3_periodic_fetch_stats call there, and
8246                  * tg3_get_stats to see how this works for 5705/5750 chips.
8247                  */
8248                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8249                      ((u64) tp->stats_mapping >> 32));
8250                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8251                      ((u64) tp->stats_mapping & 0xffffffff));
8252                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8253
8254                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
8255
8256                 /* Clear statistics and status block memory areas */
8257                 for (i = NIC_SRAM_STATS_BLK;
8258                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8259                      i += sizeof(u32)) {
8260                         tg3_write_mem(tp, i, 0);
8261                         udelay(40);
8262                 }
8263         }
8264
8265         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8266
8267         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8268         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8269         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8270                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8271
8272         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
8273                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
8274                 /* reset to prevent losing 1st rx packet intermittently */
8275                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8276                 udelay(10);
8277         }
8278
8279         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8280                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8281         else
8282                 tp->mac_mode = 0;
8283         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8284                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
8285         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8286             !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8287             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8288                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8289         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8290         udelay(40);
8291
8292         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8293          * If TG3_FLG2_IS_NIC is zero, we should read the
8294          * register to preserve the GPIO settings for LOMs. The GPIOs,
8295          * whether used as inputs or outputs, are set by boot code after
8296          * reset.
8297          */
8298         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
8299                 u32 gpio_mask;
8300
8301                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8302                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8303                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8304
8305                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8306                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8307                                      GRC_LCLCTRL_GPIO_OUTPUT3;
8308
8309                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8310                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8311
8312                 tp->grc_local_ctrl &= ~gpio_mask;
8313                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8314
8315                 /* GPIO1 must be driven high for eeprom write protect */
8316                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8317                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8318                                                GRC_LCLCTRL_GPIO_OUTPUT1);
8319         }
8320         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8321         udelay(100);
8322
8323         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
8324                 val = tr32(MSGINT_MODE);
8325                 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8326                 tw32(MSGINT_MODE, val);
8327         }
8328
8329         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8330                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8331                 udelay(40);
8332         }
8333
8334         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8335                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8336                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8337                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8338                WDMAC_MODE_LNGREAD_ENAB);
8339
8340         /* If statement applies to 5705 and 5750 PCI devices only */
8341         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8342              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8343             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
8344                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8345                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8346                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8347                         /* nothing */
8348                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8349                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8350                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8351                         val |= WDMAC_MODE_RX_ACCEL;
8352                 }
8353         }
8354
8355         /* Enable host coalescing bug fix */
8356         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8357                 val |= WDMAC_MODE_STATUS_TAG_FIX;
8358
8359         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8360                 val |= WDMAC_MODE_BURST_ALL_DATA;
8361
8362         tw32_f(WDMAC_MODE, val);
8363         udelay(40);
8364
8365         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8366                 u16 pcix_cmd;
8367
8368                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8369                                      &pcix_cmd);
8370                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8371                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8372                         pcix_cmd |= PCI_X_CMD_READ_2K;
8373                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8374                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8375                         pcix_cmd |= PCI_X_CMD_READ_2K;
8376                 }
8377                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8378                                       pcix_cmd);
8379         }
8380
8381         tw32_f(RDMAC_MODE, rdmac_mode);
8382         udelay(40);
8383
8384         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8385         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8386                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8387
8388         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8389                 tw32(SNDDATAC_MODE,
8390                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8391         else
8392                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8393
8394         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8395         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8396         val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
8397         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8398             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8399                 val |= RCVDBDI_MODE_LRG_RING_SZ;
8400         tw32(RCVDBDI_MODE, val);
8401         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8402         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8403                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8404         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8405         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8406                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8407         tw32(SNDBDI_MODE, val);
8408         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8409
8410         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8411                 err = tg3_load_5701_a0_firmware_fix(tp);
8412                 if (err)
8413                         return err;
8414         }
8415
8416         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8417                 err = tg3_load_tso_firmware(tp);
8418                 if (err)
8419                         return err;
8420         }
8421
8422         tp->tx_mode = TX_MODE_ENABLE;
8423         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
8424             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8425                 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
8426         tw32_f(MAC_TX_MODE, tp->tx_mode);
8427         udelay(100);
8428
8429         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8430                 u32 reg = MAC_RSS_INDIR_TBL_0;
8431                 u8 *ent = (u8 *)&val;
8432
8433                 /* Setup the indirection table */
8434                 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8435                         int idx = i % sizeof(val);
8436
8437                         ent[idx] = i % (tp->irq_cnt - 1);
8438                         if (idx == sizeof(val) - 1) {
8439                                 tw32(reg, val);
8440                                 reg += 4;
8441                         }
8442                 }
8443
8444                 /* Setup the "secret" hash key. */
8445                 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8446                 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8447                 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8448                 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8449                 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8450                 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8451                 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8452                 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8453                 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8454                 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8455         }
8456
8457         tp->rx_mode = RX_MODE_ENABLE;
8458         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8459                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8460
8461         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8462                 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8463                                RX_MODE_RSS_ITBL_HASH_BITS_7 |
8464                                RX_MODE_RSS_IPV6_HASH_EN |
8465                                RX_MODE_RSS_TCP_IPV6_HASH_EN |
8466                                RX_MODE_RSS_IPV4_HASH_EN |
8467                                RX_MODE_RSS_TCP_IPV4_HASH_EN;
8468
8469         tw32_f(MAC_RX_MODE, tp->rx_mode);
8470         udelay(10);
8471
8472         tw32(MAC_LED_CTRL, tp->led_ctrl);
8473
8474         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8475         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8476                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8477                 udelay(10);
8478         }
8479         tw32_f(MAC_RX_MODE, tp->rx_mode);
8480         udelay(10);
8481
8482         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8483                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8484                         !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
8485                         /* Set drive transmission level to 1.2V  */
8486                         /* only if the signal pre-emphasis bit is not set  */
8487                         val = tr32(MAC_SERDES_CFG);
8488                         val &= 0xfffff000;
8489                         val |= 0x880;
8490                         tw32(MAC_SERDES_CFG, val);
8491                 }
8492                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8493                         tw32(MAC_SERDES_CFG, 0x616000);
8494         }
8495
8496         /* Prevent chip from dropping frames when flow control
8497          * is enabled.
8498          */
8499         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8500                 val = 1;
8501         else
8502                 val = 2;
8503         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8504
8505         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8506             (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
8507                 /* Use hardware link auto-negotiation */
8508                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8509         }
8510
8511         if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8512             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8513                 u32 tmp;
8514
8515                 tmp = tr32(SERDES_RX_CTRL);
8516                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8517                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8518                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8519                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8520         }
8521
8522         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8523                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
8524                         tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
8525                         tp->link_config.speed = tp->link_config.orig_speed;
8526                         tp->link_config.duplex = tp->link_config.orig_duplex;
8527                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
8528                 }
8529
8530                 err = tg3_setup_phy(tp, 0);
8531                 if (err)
8532                         return err;
8533
8534                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8535                     !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8536                         u32 tmp;
8537
8538                         /* Clear CRC stats. */
8539                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8540                                 tg3_writephy(tp, MII_TG3_TEST1,
8541                                              tmp | MII_TG3_TEST1_CRC_EN);
8542                                 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
8543                         }
8544                 }
8545         }
8546
8547         __tg3_set_rx_mode(tp->dev);
8548
8549         /* Initialize receive rules. */
8550         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
8551         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8552         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
8553         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8554
8555         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8556             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8557                 limit = 8;
8558         else
8559                 limit = 16;
8560         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8561                 limit -= 4;
8562         switch (limit) {
8563         case 16:
8564                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
8565         case 15:
8566                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
8567         case 14:
8568                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
8569         case 13:
8570                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
8571         case 12:
8572                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
8573         case 11:
8574                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
8575         case 10:
8576                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
8577         case 9:
8578                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
8579         case 8:
8580                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
8581         case 7:
8582                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
8583         case 6:
8584                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
8585         case 5:
8586                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
8587         case 4:
8588                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
8589         case 3:
8590                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
8591         case 2:
8592         case 1:
8593
8594         default:
8595                 break;
8596         }
8597
8598         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8599                 /* Write our heartbeat update interval to APE. */
8600                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8601                                 APE_HOST_HEARTBEAT_INT_DISABLE);
8602
8603         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8604
8605         return 0;
8606 }
8607
8608 /* Called at device open time to get the chip ready for
8609  * packet processing.  Invoked with tp->lock held.
8610  */
8611 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8612 {
8613         tg3_switch_clocks(tp);
8614
8615         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8616
8617         return tg3_reset_hw(tp, reset_phy);
8618 }
8619
8620 #define TG3_STAT_ADD32(PSTAT, REG) \
8621 do {    u32 __val = tr32(REG); \
8622         (PSTAT)->low += __val; \
8623         if ((PSTAT)->low < __val) \
8624                 (PSTAT)->high += 1; \
8625 } while (0)
8626
8627 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8628 {
8629         struct tg3_hw_stats *sp = tp->hw_stats;
8630
8631         if (!netif_carrier_ok(tp->dev))
8632                 return;
8633
8634         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8635         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8636         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8637         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8638         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8639         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8640         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8641         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8642         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8643         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8644         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8645         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8646         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8647
8648         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8649         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8650         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8651         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8652         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8653         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8654         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8655         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8656         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8657         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8658         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8659         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8660         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8661         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8662
8663         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8664         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8665         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8666 }
8667
8668 static void tg3_timer(unsigned long __opaque)
8669 {
8670         struct tg3 *tp = (struct tg3 *) __opaque;
8671
8672         if (tp->irq_sync)
8673                 goto restart_timer;
8674
8675         spin_lock(&tp->lock);
8676
8677         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8678                 /* All of this garbage is because when using non-tagged
8679                  * IRQ status the mailbox/status_block protocol the chip
8680                  * uses with the cpu is race prone.
8681                  */
8682                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8683                         tw32(GRC_LOCAL_CTRL,
8684                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8685                 } else {
8686                         tw32(HOSTCC_MODE, tp->coalesce_mode |
8687                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8688                 }
8689
8690                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8691                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8692                         spin_unlock(&tp->lock);
8693                         schedule_work(&tp->reset_task);
8694                         return;
8695                 }
8696         }
8697
8698         /* This part only runs once per second. */
8699         if (!--tp->timer_counter) {
8700                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8701                         tg3_periodic_fetch_stats(tp);
8702
8703                 if (tp->setlpicnt && !--tp->setlpicnt) {
8704                         u32 val = tr32(TG3_CPMU_EEE_MODE);
8705                         tw32(TG3_CPMU_EEE_MODE,
8706                              val | TG3_CPMU_EEEMD_LPI_ENABLE);
8707                 }
8708
8709                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8710                         u32 mac_stat;
8711                         int phy_event;
8712
8713                         mac_stat = tr32(MAC_STATUS);
8714
8715                         phy_event = 0;
8716                         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
8717                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8718                                         phy_event = 1;
8719                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8720                                 phy_event = 1;
8721
8722                         if (phy_event)
8723                                 tg3_setup_phy(tp, 0);
8724                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8725                         u32 mac_stat = tr32(MAC_STATUS);
8726                         int need_setup = 0;
8727
8728                         if (netif_carrier_ok(tp->dev) &&
8729                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8730                                 need_setup = 1;
8731                         }
8732                         if (!netif_carrier_ok(tp->dev) &&
8733                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
8734                                          MAC_STATUS_SIGNAL_DET))) {
8735                                 need_setup = 1;
8736                         }
8737                         if (need_setup) {
8738                                 if (!tp->serdes_counter) {
8739                                         tw32_f(MAC_MODE,
8740                                              (tp->mac_mode &
8741                                               ~MAC_MODE_PORT_MODE_MASK));
8742                                         udelay(40);
8743                                         tw32_f(MAC_MODE, tp->mac_mode);
8744                                         udelay(40);
8745                                 }
8746                                 tg3_setup_phy(tp, 0);
8747                         }
8748                 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8749                            (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8750                         tg3_serdes_parallel_detect(tp);
8751                 }
8752
8753                 tp->timer_counter = tp->timer_multiplier;
8754         }
8755
8756         /* Heartbeat is only sent once every 2 seconds.
8757          *
8758          * The heartbeat is to tell the ASF firmware that the host
8759          * driver is still alive.  In the event that the OS crashes,
8760          * ASF needs to reset the hardware to free up the FIFO space
8761          * that may be filled with rx packets destined for the host.
8762          * If the FIFO is full, ASF will no longer function properly.
8763          *
8764          * Unintended resets have been reported on real time kernels
8765          * where the timer doesn't run on time.  Netpoll will also have
8766          * same problem.
8767          *
8768          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8769          * to check the ring condition when the heartbeat is expiring
8770          * before doing the reset.  This will prevent most unintended
8771          * resets.
8772          */
8773         if (!--tp->asf_counter) {
8774                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8775                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8776                         tg3_wait_for_event_ack(tp);
8777
8778                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8779                                       FWCMD_NICDRV_ALIVE3);
8780                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8781                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
8782                                       TG3_FW_UPDATE_TIMEOUT_SEC);
8783
8784                         tg3_generate_fw_event(tp);
8785                 }
8786                 tp->asf_counter = tp->asf_multiplier;
8787         }
8788
8789         spin_unlock(&tp->lock);
8790
8791 restart_timer:
8792         tp->timer.expires = jiffies + tp->timer_offset;
8793         add_timer(&tp->timer);
8794 }
8795
8796 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8797 {
8798         irq_handler_t fn;
8799         unsigned long flags;
8800         char *name;
8801         struct tg3_napi *tnapi = &tp->napi[irq_num];
8802
8803         if (tp->irq_cnt == 1)
8804                 name = tp->dev->name;
8805         else {
8806                 name = &tnapi->irq_lbl[0];
8807                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8808                 name[IFNAMSIZ-1] = 0;
8809         }
8810
8811         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8812                 fn = tg3_msi;
8813                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8814                         fn = tg3_msi_1shot;
8815                 flags = IRQF_SAMPLE_RANDOM;
8816         } else {
8817                 fn = tg3_interrupt;
8818                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8819                         fn = tg3_interrupt_tagged;
8820                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8821         }
8822
8823         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8824 }
8825
8826 static int tg3_test_interrupt(struct tg3 *tp)
8827 {
8828         struct tg3_napi *tnapi = &tp->napi[0];
8829         struct net_device *dev = tp->dev;
8830         int err, i, intr_ok = 0;
8831         u32 val;
8832
8833         if (!netif_running(dev))
8834                 return -ENODEV;
8835
8836         tg3_disable_ints(tp);
8837
8838         free_irq(tnapi->irq_vec, tnapi);
8839
8840         /*
8841          * Turn off MSI one shot mode.  Otherwise this test has no
8842          * observable way to know whether the interrupt was delivered.
8843          */
8844         if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8845             (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8846                 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8847                 tw32(MSGINT_MODE, val);
8848         }
8849
8850         err = request_irq(tnapi->irq_vec, tg3_test_isr,
8851                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8852         if (err)
8853                 return err;
8854
8855         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8856         tg3_enable_ints(tp);
8857
8858         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8859                tnapi->coal_now);
8860
8861         for (i = 0; i < 5; i++) {
8862                 u32 int_mbox, misc_host_ctrl;
8863
8864                 int_mbox = tr32_mailbox(tnapi->int_mbox);
8865                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8866
8867                 if ((int_mbox != 0) ||
8868                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8869                         intr_ok = 1;
8870                         break;
8871                 }
8872
8873                 msleep(10);
8874         }
8875
8876         tg3_disable_ints(tp);
8877
8878         free_irq(tnapi->irq_vec, tnapi);
8879
8880         err = tg3_request_irq(tp, 0);
8881
8882         if (err)
8883                 return err;
8884
8885         if (intr_ok) {
8886                 /* Reenable MSI one shot mode. */
8887                 if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8888                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8889                         val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8890                         tw32(MSGINT_MODE, val);
8891                 }
8892                 return 0;
8893         }
8894
8895         return -EIO;
8896 }
8897
8898 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8899  * successfully restored
8900  */
8901 static int tg3_test_msi(struct tg3 *tp)
8902 {
8903         int err;
8904         u16 pci_cmd;
8905
8906         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8907                 return 0;
8908
8909         /* Turn off SERR reporting in case MSI terminates with Master
8910          * Abort.
8911          */
8912         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8913         pci_write_config_word(tp->pdev, PCI_COMMAND,
8914                               pci_cmd & ~PCI_COMMAND_SERR);
8915
8916         err = tg3_test_interrupt(tp);
8917
8918         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8919
8920         if (!err)
8921                 return 0;
8922
8923         /* other failures */
8924         if (err != -EIO)
8925                 return err;
8926
8927         /* MSI test failed, go back to INTx mode */
8928         netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
8929                     "to INTx mode. Please report this failure to the PCI "
8930                     "maintainer and include system chipset information\n");
8931
8932         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8933
8934         pci_disable_msi(tp->pdev);
8935
8936         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8937         tp->napi[0].irq_vec = tp->pdev->irq;
8938
8939         err = tg3_request_irq(tp, 0);
8940         if (err)
8941                 return err;
8942
8943         /* Need to reset the chip because the MSI cycle may have terminated
8944          * with Master Abort.
8945          */
8946         tg3_full_lock(tp, 1);
8947
8948         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8949         err = tg3_init_hw(tp, 1);
8950
8951         tg3_full_unlock(tp);
8952
8953         if (err)
8954                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8955
8956         return err;
8957 }
8958
8959 static int tg3_request_firmware(struct tg3 *tp)
8960 {
8961         const __be32 *fw_data;
8962
8963         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8964                 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
8965                            tp->fw_needed);
8966                 return -ENOENT;
8967         }
8968
8969         fw_data = (void *)tp->fw->data;
8970
8971         /* Firmware blob starts with version numbers, followed by
8972          * start address and _full_ length including BSS sections
8973          * (which must be longer than the actual data, of course
8974          */
8975
8976         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
8977         if (tp->fw_len < (tp->fw->size - 12)) {
8978                 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
8979                            tp->fw_len, tp->fw_needed);
8980                 release_firmware(tp->fw);
8981                 tp->fw = NULL;
8982                 return -EINVAL;
8983         }
8984
8985         /* We no longer need firmware; we have it. */
8986         tp->fw_needed = NULL;
8987         return 0;
8988 }
8989
8990 static bool tg3_enable_msix(struct tg3 *tp)
8991 {
8992         int i, rc, cpus = num_online_cpus();
8993         struct msix_entry msix_ent[tp->irq_max];
8994
8995         if (cpus == 1)
8996                 /* Just fallback to the simpler MSI mode. */
8997                 return false;
8998
8999         /*
9000          * We want as many rx rings enabled as there are cpus.
9001          * The first MSIX vector only deals with link interrupts, etc,
9002          * so we add one to the number of vectors we are requesting.
9003          */
9004         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
9005
9006         for (i = 0; i < tp->irq_max; i++) {
9007                 msix_ent[i].entry  = i;
9008                 msix_ent[i].vector = 0;
9009         }
9010
9011         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
9012         if (rc < 0) {
9013                 return false;
9014         } else if (rc != 0) {
9015                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
9016                         return false;
9017                 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
9018                               tp->irq_cnt, rc);
9019                 tp->irq_cnt = rc;
9020         }
9021
9022         for (i = 0; i < tp->irq_max; i++)
9023                 tp->napi[i].irq_vec = msix_ent[i].vector;
9024
9025         netif_set_real_num_tx_queues(tp->dev, 1);
9026         rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1;
9027         if (netif_set_real_num_rx_queues(tp->dev, rc)) {
9028                 pci_disable_msix(tp->pdev);
9029                 return false;
9030         }
9031         if (tp->irq_cnt > 1)
9032                 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
9033
9034         return true;
9035 }
9036
9037 static void tg3_ints_init(struct tg3 *tp)
9038 {
9039         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
9040             !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
9041                 /* All MSI supporting chips should support tagged
9042                  * status.  Assert that this is the case.
9043                  */
9044                 netdev_warn(tp->dev,
9045                             "MSI without TAGGED_STATUS? Not using MSI\n");
9046                 goto defcfg;
9047         }
9048
9049         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
9050                 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
9051         else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
9052                  pci_enable_msi(tp->pdev) == 0)
9053                 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
9054
9055         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
9056                 u32 msi_mode = tr32(MSGINT_MODE);
9057                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
9058                         msi_mode |= MSGINT_MODE_MULTIVEC_EN;
9059                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
9060         }
9061 defcfg:
9062         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
9063                 tp->irq_cnt = 1;
9064                 tp->napi[0].irq_vec = tp->pdev->irq;
9065                 netif_set_real_num_tx_queues(tp->dev, 1);
9066                 netif_set_real_num_rx_queues(tp->dev, 1);
9067         }
9068 }
9069
9070 static void tg3_ints_fini(struct tg3 *tp)
9071 {
9072         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
9073                 pci_disable_msix(tp->pdev);
9074         else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
9075                 pci_disable_msi(tp->pdev);
9076         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
9077         tp->tg3_flags3 &= ~(TG3_FLG3_ENABLE_RSS | TG3_FLG3_ENABLE_TSS);
9078 }
9079
9080 static int tg3_open(struct net_device *dev)
9081 {
9082         struct tg3 *tp = netdev_priv(dev);
9083         int i, err;
9084
9085         if (tp->fw_needed) {
9086                 err = tg3_request_firmware(tp);
9087                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
9088                         if (err)
9089                                 return err;
9090                 } else if (err) {
9091                         netdev_warn(tp->dev, "TSO capability disabled\n");
9092                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
9093                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9094                         netdev_notice(tp->dev, "TSO capability restored\n");
9095                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
9096                 }
9097         }
9098
9099         netif_carrier_off(tp->dev);
9100
9101         err = tg3_set_power_state(tp, PCI_D0);
9102         if (err)
9103                 return err;
9104
9105         tg3_full_lock(tp, 0);
9106
9107         tg3_disable_ints(tp);
9108         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9109
9110         tg3_full_unlock(tp);
9111
9112         /*
9113          * Setup interrupts first so we know how
9114          * many NAPI resources to allocate
9115          */
9116         tg3_ints_init(tp);
9117
9118         /* The placement of this call is tied
9119          * to the setup and use of Host TX descriptors.
9120          */
9121         err = tg3_alloc_consistent(tp);
9122         if (err)
9123                 goto err_out1;
9124
9125         tg3_napi_init(tp);
9126
9127         tg3_napi_enable(tp);
9128
9129         for (i = 0; i < tp->irq_cnt; i++) {
9130                 struct tg3_napi *tnapi = &tp->napi[i];
9131                 err = tg3_request_irq(tp, i);
9132                 if (err) {
9133                         for (i--; i >= 0; i--)
9134                                 free_irq(tnapi->irq_vec, tnapi);
9135                         break;
9136                 }
9137         }
9138
9139         if (err)
9140                 goto err_out2;
9141
9142         tg3_full_lock(tp, 0);
9143
9144         err = tg3_init_hw(tp, 1);
9145         if (err) {
9146                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9147                 tg3_free_rings(tp);
9148         } else {
9149                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
9150                         tp->timer_offset = HZ;
9151                 else
9152                         tp->timer_offset = HZ / 10;
9153
9154                 BUG_ON(tp->timer_offset > HZ);
9155                 tp->timer_counter = tp->timer_multiplier =
9156                         (HZ / tp->timer_offset);
9157                 tp->asf_counter = tp->asf_multiplier =
9158                         ((HZ / tp->timer_offset) * 2);
9159
9160                 init_timer(&tp->timer);
9161                 tp->timer.expires = jiffies + tp->timer_offset;
9162                 tp->timer.data = (unsigned long) tp;
9163                 tp->timer.function = tg3_timer;
9164         }
9165
9166         tg3_full_unlock(tp);
9167
9168         if (err)
9169                 goto err_out3;
9170
9171         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
9172                 err = tg3_test_msi(tp);
9173
9174                 if (err) {
9175                         tg3_full_lock(tp, 0);
9176                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9177                         tg3_free_rings(tp);
9178                         tg3_full_unlock(tp);
9179
9180                         goto err_out2;
9181                 }
9182
9183                 if (!(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
9184                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
9185                         u32 val = tr32(PCIE_TRANSACTION_CFG);
9186
9187                         tw32(PCIE_TRANSACTION_CFG,
9188                              val | PCIE_TRANS_CFG_1SHOT_MSI);
9189                 }
9190         }
9191
9192         tg3_phy_start(tp);
9193
9194         tg3_full_lock(tp, 0);
9195
9196         add_timer(&tp->timer);
9197         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9198         tg3_enable_ints(tp);
9199
9200         tg3_full_unlock(tp);
9201
9202         netif_tx_start_all_queues(dev);
9203
9204         return 0;
9205
9206 err_out3:
9207         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9208                 struct tg3_napi *tnapi = &tp->napi[i];
9209                 free_irq(tnapi->irq_vec, tnapi);
9210         }
9211
9212 err_out2:
9213         tg3_napi_disable(tp);
9214         tg3_napi_fini(tp);
9215         tg3_free_consistent(tp);
9216
9217 err_out1:
9218         tg3_ints_fini(tp);
9219         return err;
9220 }
9221
9222 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
9223                                                  struct rtnl_link_stats64 *);
9224 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9225
9226 static int tg3_close(struct net_device *dev)
9227 {
9228         int i;
9229         struct tg3 *tp = netdev_priv(dev);
9230
9231         tg3_napi_disable(tp);
9232         cancel_work_sync(&tp->reset_task);
9233
9234         netif_tx_stop_all_queues(dev);
9235
9236         del_timer_sync(&tp->timer);
9237
9238         tg3_phy_stop(tp);
9239
9240         tg3_full_lock(tp, 1);
9241
9242         tg3_disable_ints(tp);
9243
9244         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9245         tg3_free_rings(tp);
9246         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9247
9248         tg3_full_unlock(tp);
9249
9250         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9251                 struct tg3_napi *tnapi = &tp->napi[i];
9252                 free_irq(tnapi->irq_vec, tnapi);
9253         }
9254
9255         tg3_ints_fini(tp);
9256
9257         tg3_get_stats64(tp->dev, &tp->net_stats_prev);
9258
9259         memcpy(&tp->estats_prev, tg3_get_estats(tp),
9260                sizeof(tp->estats_prev));
9261
9262         tg3_napi_fini(tp);
9263
9264         tg3_free_consistent(tp);
9265
9266         tg3_set_power_state(tp, PCI_D3hot);
9267
9268         netif_carrier_off(tp->dev);
9269
9270         return 0;
9271 }
9272
9273 static inline u64 get_stat64(tg3_stat64_t *val)
9274 {
9275        return ((u64)val->high << 32) | ((u64)val->low);
9276 }
9277
9278 static u64 calc_crc_errors(struct tg3 *tp)
9279 {
9280         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9281
9282         if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9283             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9284              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9285                 u32 val;
9286
9287                 spin_lock_bh(&tp->lock);
9288                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9289                         tg3_writephy(tp, MII_TG3_TEST1,
9290                                      val | MII_TG3_TEST1_CRC_EN);
9291                         tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
9292                 } else
9293                         val = 0;
9294                 spin_unlock_bh(&tp->lock);
9295
9296                 tp->phy_crc_errors += val;
9297
9298                 return tp->phy_crc_errors;
9299         }
9300
9301         return get_stat64(&hw_stats->rx_fcs_errors);
9302 }
9303
9304 #define ESTAT_ADD(member) \
9305         estats->member =        old_estats->member + \
9306                                 get_stat64(&hw_stats->member)
9307
9308 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9309 {
9310         struct tg3_ethtool_stats *estats = &tp->estats;
9311         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9312         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9313
9314         if (!hw_stats)
9315                 return old_estats;
9316
9317         ESTAT_ADD(rx_octets);
9318         ESTAT_ADD(rx_fragments);
9319         ESTAT_ADD(rx_ucast_packets);
9320         ESTAT_ADD(rx_mcast_packets);
9321         ESTAT_ADD(rx_bcast_packets);
9322         ESTAT_ADD(rx_fcs_errors);
9323         ESTAT_ADD(rx_align_errors);
9324         ESTAT_ADD(rx_xon_pause_rcvd);
9325         ESTAT_ADD(rx_xoff_pause_rcvd);
9326         ESTAT_ADD(rx_mac_ctrl_rcvd);
9327         ESTAT_ADD(rx_xoff_entered);
9328         ESTAT_ADD(rx_frame_too_long_errors);
9329         ESTAT_ADD(rx_jabbers);
9330         ESTAT_ADD(rx_undersize_packets);
9331         ESTAT_ADD(rx_in_length_errors);
9332         ESTAT_ADD(rx_out_length_errors);
9333         ESTAT_ADD(rx_64_or_less_octet_packets);
9334         ESTAT_ADD(rx_65_to_127_octet_packets);
9335         ESTAT_ADD(rx_128_to_255_octet_packets);
9336         ESTAT_ADD(rx_256_to_511_octet_packets);
9337         ESTAT_ADD(rx_512_to_1023_octet_packets);
9338         ESTAT_ADD(rx_1024_to_1522_octet_packets);
9339         ESTAT_ADD(rx_1523_to_2047_octet_packets);
9340         ESTAT_ADD(rx_2048_to_4095_octet_packets);
9341         ESTAT_ADD(rx_4096_to_8191_octet_packets);
9342         ESTAT_ADD(rx_8192_to_9022_octet_packets);
9343
9344         ESTAT_ADD(tx_octets);
9345         ESTAT_ADD(tx_collisions);
9346         ESTAT_ADD(tx_xon_sent);
9347         ESTAT_ADD(tx_xoff_sent);
9348         ESTAT_ADD(tx_flow_control);
9349         ESTAT_ADD(tx_mac_errors);
9350         ESTAT_ADD(tx_single_collisions);
9351         ESTAT_ADD(tx_mult_collisions);
9352         ESTAT_ADD(tx_deferred);
9353         ESTAT_ADD(tx_excessive_collisions);
9354         ESTAT_ADD(tx_late_collisions);
9355         ESTAT_ADD(tx_collide_2times);
9356         ESTAT_ADD(tx_collide_3times);
9357         ESTAT_ADD(tx_collide_4times);
9358         ESTAT_ADD(tx_collide_5times);
9359         ESTAT_ADD(tx_collide_6times);
9360         ESTAT_ADD(tx_collide_7times);
9361         ESTAT_ADD(tx_collide_8times);
9362         ESTAT_ADD(tx_collide_9times);
9363         ESTAT_ADD(tx_collide_10times);
9364         ESTAT_ADD(tx_collide_11times);
9365         ESTAT_ADD(tx_collide_12times);
9366         ESTAT_ADD(tx_collide_13times);
9367         ESTAT_ADD(tx_collide_14times);
9368         ESTAT_ADD(tx_collide_15times);
9369         ESTAT_ADD(tx_ucast_packets);
9370         ESTAT_ADD(tx_mcast_packets);
9371         ESTAT_ADD(tx_bcast_packets);
9372         ESTAT_ADD(tx_carrier_sense_errors);
9373         ESTAT_ADD(tx_discards);
9374         ESTAT_ADD(tx_errors);
9375
9376         ESTAT_ADD(dma_writeq_full);
9377         ESTAT_ADD(dma_write_prioq_full);
9378         ESTAT_ADD(rxbds_empty);
9379         ESTAT_ADD(rx_discards);
9380         ESTAT_ADD(rx_errors);
9381         ESTAT_ADD(rx_threshold_hit);
9382
9383         ESTAT_ADD(dma_readq_full);
9384         ESTAT_ADD(dma_read_prioq_full);
9385         ESTAT_ADD(tx_comp_queue_full);
9386
9387         ESTAT_ADD(ring_set_send_prod_index);
9388         ESTAT_ADD(ring_status_update);
9389         ESTAT_ADD(nic_irqs);
9390         ESTAT_ADD(nic_avoided_irqs);
9391         ESTAT_ADD(nic_tx_threshold_hit);
9392
9393         return estats;
9394 }
9395
9396 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
9397                                                  struct rtnl_link_stats64 *stats)
9398 {
9399         struct tg3 *tp = netdev_priv(dev);
9400         struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
9401         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9402
9403         if (!hw_stats)
9404                 return old_stats;
9405
9406         stats->rx_packets = old_stats->rx_packets +
9407                 get_stat64(&hw_stats->rx_ucast_packets) +
9408                 get_stat64(&hw_stats->rx_mcast_packets) +
9409                 get_stat64(&hw_stats->rx_bcast_packets);
9410
9411         stats->tx_packets = old_stats->tx_packets +
9412                 get_stat64(&hw_stats->tx_ucast_packets) +
9413                 get_stat64(&hw_stats->tx_mcast_packets) +
9414                 get_stat64(&hw_stats->tx_bcast_packets);
9415
9416         stats->rx_bytes = old_stats->rx_bytes +
9417                 get_stat64(&hw_stats->rx_octets);
9418         stats->tx_bytes = old_stats->tx_bytes +
9419                 get_stat64(&hw_stats->tx_octets);
9420
9421         stats->rx_errors = old_stats->rx_errors +
9422                 get_stat64(&hw_stats->rx_errors);
9423         stats->tx_errors = old_stats->tx_errors +
9424                 get_stat64(&hw_stats->tx_errors) +
9425                 get_stat64(&hw_stats->tx_mac_errors) +
9426                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9427                 get_stat64(&hw_stats->tx_discards);
9428
9429         stats->multicast = old_stats->multicast +
9430                 get_stat64(&hw_stats->rx_mcast_packets);
9431         stats->collisions = old_stats->collisions +
9432                 get_stat64(&hw_stats->tx_collisions);
9433
9434         stats->rx_length_errors = old_stats->rx_length_errors +
9435                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9436                 get_stat64(&hw_stats->rx_undersize_packets);
9437
9438         stats->rx_over_errors = old_stats->rx_over_errors +
9439                 get_stat64(&hw_stats->rxbds_empty);
9440         stats->rx_frame_errors = old_stats->rx_frame_errors +
9441                 get_stat64(&hw_stats->rx_align_errors);
9442         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9443                 get_stat64(&hw_stats->tx_discards);
9444         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9445                 get_stat64(&hw_stats->tx_carrier_sense_errors);
9446
9447         stats->rx_crc_errors = old_stats->rx_crc_errors +
9448                 calc_crc_errors(tp);
9449
9450         stats->rx_missed_errors = old_stats->rx_missed_errors +
9451                 get_stat64(&hw_stats->rx_discards);
9452
9453         return stats;
9454 }
9455
9456 static inline u32 calc_crc(unsigned char *buf, int len)
9457 {
9458         u32 reg;
9459         u32 tmp;
9460         int j, k;
9461
9462         reg = 0xffffffff;
9463
9464         for (j = 0; j < len; j++) {
9465                 reg ^= buf[j];
9466
9467                 for (k = 0; k < 8; k++) {
9468                         tmp = reg & 0x01;
9469
9470                         reg >>= 1;
9471
9472                         if (tmp)
9473                                 reg ^= 0xedb88320;
9474                 }
9475         }
9476
9477         return ~reg;
9478 }
9479
9480 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9481 {
9482         /* accept or reject all multicast frames */
9483         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9484         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9485         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9486         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9487 }
9488
9489 static void __tg3_set_rx_mode(struct net_device *dev)
9490 {
9491         struct tg3 *tp = netdev_priv(dev);
9492         u32 rx_mode;
9493
9494         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9495                                   RX_MODE_KEEP_VLAN_TAG);
9496
9497         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9498          * flag clear.
9499          */
9500 #if TG3_VLAN_TAG_USED
9501         if (!tp->vlgrp &&
9502             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9503                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9504 #else
9505         /* By definition, VLAN is disabled always in this
9506          * case.
9507          */
9508         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9509                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9510 #endif
9511
9512         if (dev->flags & IFF_PROMISC) {
9513                 /* Promiscuous mode. */
9514                 rx_mode |= RX_MODE_PROMISC;
9515         } else if (dev->flags & IFF_ALLMULTI) {
9516                 /* Accept all multicast. */
9517                 tg3_set_multi(tp, 1);
9518         } else if (netdev_mc_empty(dev)) {
9519                 /* Reject all multicast. */
9520                 tg3_set_multi(tp, 0);
9521         } else {
9522                 /* Accept one or more multicast(s). */
9523                 struct netdev_hw_addr *ha;
9524                 u32 mc_filter[4] = { 0, };
9525                 u32 regidx;
9526                 u32 bit;
9527                 u32 crc;
9528
9529                 netdev_for_each_mc_addr(ha, dev) {
9530                         crc = calc_crc(ha->addr, ETH_ALEN);
9531                         bit = ~crc & 0x7f;
9532                         regidx = (bit & 0x60) >> 5;
9533                         bit &= 0x1f;
9534                         mc_filter[regidx] |= (1 << bit);
9535                 }
9536
9537                 tw32(MAC_HASH_REG_0, mc_filter[0]);
9538                 tw32(MAC_HASH_REG_1, mc_filter[1]);
9539                 tw32(MAC_HASH_REG_2, mc_filter[2]);
9540                 tw32(MAC_HASH_REG_3, mc_filter[3]);
9541         }
9542
9543         if (rx_mode != tp->rx_mode) {
9544                 tp->rx_mode = rx_mode;
9545                 tw32_f(MAC_RX_MODE, rx_mode);
9546                 udelay(10);
9547         }
9548 }
9549
9550 static void tg3_set_rx_mode(struct net_device *dev)
9551 {
9552         struct tg3 *tp = netdev_priv(dev);
9553
9554         if (!netif_running(dev))
9555                 return;
9556
9557         tg3_full_lock(tp, 0);
9558         __tg3_set_rx_mode(dev);
9559         tg3_full_unlock(tp);
9560 }
9561
9562 #define TG3_REGDUMP_LEN         (32 * 1024)
9563
9564 static int tg3_get_regs_len(struct net_device *dev)
9565 {
9566         return TG3_REGDUMP_LEN;
9567 }
9568
9569 static void tg3_get_regs(struct net_device *dev,
9570                 struct ethtool_regs *regs, void *_p)
9571 {
9572         u32 *p = _p;
9573         struct tg3 *tp = netdev_priv(dev);
9574         u8 *orig_p = _p;
9575         int i;
9576
9577         regs->version = 0;
9578
9579         memset(p, 0, TG3_REGDUMP_LEN);
9580
9581         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9582                 return;
9583
9584         tg3_full_lock(tp, 0);
9585
9586 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
9587 #define GET_REG32_LOOP(base, len)               \
9588 do {    p = (u32 *)(orig_p + (base));           \
9589         for (i = 0; i < len; i += 4)            \
9590                 __GET_REG32((base) + i);        \
9591 } while (0)
9592 #define GET_REG32_1(reg)                        \
9593 do {    p = (u32 *)(orig_p + (reg));            \
9594         __GET_REG32((reg));                     \
9595 } while (0)
9596
9597         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9598         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9599         GET_REG32_LOOP(MAC_MODE, 0x4f0);
9600         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9601         GET_REG32_1(SNDDATAC_MODE);
9602         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9603         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9604         GET_REG32_1(SNDBDC_MODE);
9605         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9606         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9607         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9608         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9609         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9610         GET_REG32_1(RCVDCC_MODE);
9611         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9612         GET_REG32_LOOP(RCVCC_MODE, 0x14);
9613         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9614         GET_REG32_1(MBFREE_MODE);
9615         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9616         GET_REG32_LOOP(MEMARB_MODE, 0x10);
9617         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9618         GET_REG32_LOOP(RDMAC_MODE, 0x08);
9619         GET_REG32_LOOP(WDMAC_MODE, 0x08);
9620         GET_REG32_1(RX_CPU_MODE);
9621         GET_REG32_1(RX_CPU_STATE);
9622         GET_REG32_1(RX_CPU_PGMCTR);
9623         GET_REG32_1(RX_CPU_HWBKPT);
9624         GET_REG32_1(TX_CPU_MODE);
9625         GET_REG32_1(TX_CPU_STATE);
9626         GET_REG32_1(TX_CPU_PGMCTR);
9627         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9628         GET_REG32_LOOP(FTQ_RESET, 0x120);
9629         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9630         GET_REG32_1(DMAC_MODE);
9631         GET_REG32_LOOP(GRC_MODE, 0x4c);
9632         if (tp->tg3_flags & TG3_FLAG_NVRAM)
9633                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9634
9635 #undef __GET_REG32
9636 #undef GET_REG32_LOOP
9637 #undef GET_REG32_1
9638
9639         tg3_full_unlock(tp);
9640 }
9641
9642 static int tg3_get_eeprom_len(struct net_device *dev)
9643 {
9644         struct tg3 *tp = netdev_priv(dev);
9645
9646         return tp->nvram_size;
9647 }
9648
9649 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9650 {
9651         struct tg3 *tp = netdev_priv(dev);
9652         int ret;
9653         u8  *pd;
9654         u32 i, offset, len, b_offset, b_count;
9655         __be32 val;
9656
9657         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9658                 return -EINVAL;
9659
9660         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9661                 return -EAGAIN;
9662
9663         offset = eeprom->offset;
9664         len = eeprom->len;
9665         eeprom->len = 0;
9666
9667         eeprom->magic = TG3_EEPROM_MAGIC;
9668
9669         if (offset & 3) {
9670                 /* adjustments to start on required 4 byte boundary */
9671                 b_offset = offset & 3;
9672                 b_count = 4 - b_offset;
9673                 if (b_count > len) {
9674                         /* i.e. offset=1 len=2 */
9675                         b_count = len;
9676                 }
9677                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9678                 if (ret)
9679                         return ret;
9680                 memcpy(data, ((char *)&val) + b_offset, b_count);
9681                 len -= b_count;
9682                 offset += b_count;
9683                 eeprom->len += b_count;
9684         }
9685
9686         /* read bytes upto the last 4 byte boundary */
9687         pd = &data[eeprom->len];
9688         for (i = 0; i < (len - (len & 3)); i += 4) {
9689                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9690                 if (ret) {
9691                         eeprom->len += i;
9692                         return ret;
9693                 }
9694                 memcpy(pd + i, &val, 4);
9695         }
9696         eeprom->len += i;
9697
9698         if (len & 3) {
9699                 /* read last bytes not ending on 4 byte boundary */
9700                 pd = &data[eeprom->len];
9701                 b_count = len & 3;
9702                 b_offset = offset + len - b_count;
9703                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9704                 if (ret)
9705                         return ret;
9706                 memcpy(pd, &val, b_count);
9707                 eeprom->len += b_count;
9708         }
9709         return 0;
9710 }
9711
9712 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9713
9714 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9715 {
9716         struct tg3 *tp = netdev_priv(dev);
9717         int ret;
9718         u32 offset, len, b_offset, odd_len;
9719         u8 *buf;
9720         __be32 start, end;
9721
9722         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9723                 return -EAGAIN;
9724
9725         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9726             eeprom->magic != TG3_EEPROM_MAGIC)
9727                 return -EINVAL;
9728
9729         offset = eeprom->offset;
9730         len = eeprom->len;
9731
9732         if ((b_offset = (offset & 3))) {
9733                 /* adjustments to start on required 4 byte boundary */
9734                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9735                 if (ret)
9736                         return ret;
9737                 len += b_offset;
9738                 offset &= ~3;
9739                 if (len < 4)
9740                         len = 4;
9741         }
9742
9743         odd_len = 0;
9744         if (len & 3) {
9745                 /* adjustments to end on required 4 byte boundary */
9746                 odd_len = 1;
9747                 len = (len + 3) & ~3;
9748                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9749                 if (ret)
9750                         return ret;
9751         }
9752
9753         buf = data;
9754         if (b_offset || odd_len) {
9755                 buf = kmalloc(len, GFP_KERNEL);
9756                 if (!buf)
9757                         return -ENOMEM;
9758                 if (b_offset)
9759                         memcpy(buf, &start, 4);
9760                 if (odd_len)
9761                         memcpy(buf+len-4, &end, 4);
9762                 memcpy(buf + b_offset, data, eeprom->len);
9763         }
9764
9765         ret = tg3_nvram_write_block(tp, offset, len, buf);
9766
9767         if (buf != data)
9768                 kfree(buf);
9769
9770         return ret;
9771 }
9772
9773 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9774 {
9775         struct tg3 *tp = netdev_priv(dev);
9776
9777         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9778                 struct phy_device *phydev;
9779                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9780                         return -EAGAIN;
9781                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9782                 return phy_ethtool_gset(phydev, cmd);
9783         }
9784
9785         cmd->supported = (SUPPORTED_Autoneg);
9786
9787         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9788                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9789                                    SUPPORTED_1000baseT_Full);
9790
9791         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
9792                 cmd->supported |= (SUPPORTED_100baseT_Half |
9793                                   SUPPORTED_100baseT_Full |
9794                                   SUPPORTED_10baseT_Half |
9795                                   SUPPORTED_10baseT_Full |
9796                                   SUPPORTED_TP);
9797                 cmd->port = PORT_TP;
9798         } else {
9799                 cmd->supported |= SUPPORTED_FIBRE;
9800                 cmd->port = PORT_FIBRE;
9801         }
9802
9803         cmd->advertising = tp->link_config.advertising;
9804         if (netif_running(dev)) {
9805                 cmd->speed = tp->link_config.active_speed;
9806                 cmd->duplex = tp->link_config.active_duplex;
9807         }
9808         cmd->phy_address = tp->phy_addr;
9809         cmd->transceiver = XCVR_INTERNAL;
9810         cmd->autoneg = tp->link_config.autoneg;
9811         cmd->maxtxpkt = 0;
9812         cmd->maxrxpkt = 0;
9813         return 0;
9814 }
9815
9816 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9817 {
9818         struct tg3 *tp = netdev_priv(dev);
9819
9820         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9821                 struct phy_device *phydev;
9822                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9823                         return -EAGAIN;
9824                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9825                 return phy_ethtool_sset(phydev, cmd);
9826         }
9827
9828         if (cmd->autoneg != AUTONEG_ENABLE &&
9829             cmd->autoneg != AUTONEG_DISABLE)
9830                 return -EINVAL;
9831
9832         if (cmd->autoneg == AUTONEG_DISABLE &&
9833             cmd->duplex != DUPLEX_FULL &&
9834             cmd->duplex != DUPLEX_HALF)
9835                 return -EINVAL;
9836
9837         if (cmd->autoneg == AUTONEG_ENABLE) {
9838                 u32 mask = ADVERTISED_Autoneg |
9839                            ADVERTISED_Pause |
9840                            ADVERTISED_Asym_Pause;
9841
9842                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9843                         mask |= ADVERTISED_1000baseT_Half |
9844                                 ADVERTISED_1000baseT_Full;
9845
9846                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
9847                         mask |= ADVERTISED_100baseT_Half |
9848                                 ADVERTISED_100baseT_Full |
9849                                 ADVERTISED_10baseT_Half |
9850                                 ADVERTISED_10baseT_Full |
9851                                 ADVERTISED_TP;
9852                 else
9853                         mask |= ADVERTISED_FIBRE;
9854
9855                 if (cmd->advertising & ~mask)
9856                         return -EINVAL;
9857
9858                 mask &= (ADVERTISED_1000baseT_Half |
9859                          ADVERTISED_1000baseT_Full |
9860                          ADVERTISED_100baseT_Half |
9861                          ADVERTISED_100baseT_Full |
9862                          ADVERTISED_10baseT_Half |
9863                          ADVERTISED_10baseT_Full);
9864
9865                 cmd->advertising &= mask;
9866         } else {
9867                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
9868                         if (cmd->speed != SPEED_1000)
9869                                 return -EINVAL;
9870
9871                         if (cmd->duplex != DUPLEX_FULL)
9872                                 return -EINVAL;
9873                 } else {
9874                         if (cmd->speed != SPEED_100 &&
9875                             cmd->speed != SPEED_10)
9876                                 return -EINVAL;
9877                 }
9878         }
9879
9880         tg3_full_lock(tp, 0);
9881
9882         tp->link_config.autoneg = cmd->autoneg;
9883         if (cmd->autoneg == AUTONEG_ENABLE) {
9884                 tp->link_config.advertising = (cmd->advertising |
9885                                               ADVERTISED_Autoneg);
9886                 tp->link_config.speed = SPEED_INVALID;
9887                 tp->link_config.duplex = DUPLEX_INVALID;
9888         } else {
9889                 tp->link_config.advertising = 0;
9890                 tp->link_config.speed = cmd->speed;
9891                 tp->link_config.duplex = cmd->duplex;
9892         }
9893
9894         tp->link_config.orig_speed = tp->link_config.speed;
9895         tp->link_config.orig_duplex = tp->link_config.duplex;
9896         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9897
9898         if (netif_running(dev))
9899                 tg3_setup_phy(tp, 1);
9900
9901         tg3_full_unlock(tp);
9902
9903         return 0;
9904 }
9905
9906 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9907 {
9908         struct tg3 *tp = netdev_priv(dev);
9909
9910         strcpy(info->driver, DRV_MODULE_NAME);
9911         strcpy(info->version, DRV_MODULE_VERSION);
9912         strcpy(info->fw_version, tp->fw_ver);
9913         strcpy(info->bus_info, pci_name(tp->pdev));
9914 }
9915
9916 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9917 {
9918         struct tg3 *tp = netdev_priv(dev);
9919
9920         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9921             device_can_wakeup(&tp->pdev->dev))
9922                 wol->supported = WAKE_MAGIC;
9923         else
9924                 wol->supported = 0;
9925         wol->wolopts = 0;
9926         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9927             device_can_wakeup(&tp->pdev->dev))
9928                 wol->wolopts = WAKE_MAGIC;
9929         memset(&wol->sopass, 0, sizeof(wol->sopass));
9930 }
9931
9932 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9933 {
9934         struct tg3 *tp = netdev_priv(dev);
9935         struct device *dp = &tp->pdev->dev;
9936
9937         if (wol->wolopts & ~WAKE_MAGIC)
9938                 return -EINVAL;
9939         if ((wol->wolopts & WAKE_MAGIC) &&
9940             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9941                 return -EINVAL;
9942
9943         spin_lock_bh(&tp->lock);
9944         if (wol->wolopts & WAKE_MAGIC) {
9945                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9946                 device_set_wakeup_enable(dp, true);
9947         } else {
9948                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9949                 device_set_wakeup_enable(dp, false);
9950         }
9951         spin_unlock_bh(&tp->lock);
9952
9953         return 0;
9954 }
9955
9956 static u32 tg3_get_msglevel(struct net_device *dev)
9957 {
9958         struct tg3 *tp = netdev_priv(dev);
9959         return tp->msg_enable;
9960 }
9961
9962 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9963 {
9964         struct tg3 *tp = netdev_priv(dev);
9965         tp->msg_enable = value;
9966 }
9967
9968 static int tg3_set_tso(struct net_device *dev, u32 value)
9969 {
9970         struct tg3 *tp = netdev_priv(dev);
9971
9972         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9973                 if (value)
9974                         return -EINVAL;
9975                 return 0;
9976         }
9977         if ((dev->features & NETIF_F_IPV6_CSUM) &&
9978             ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9979              (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9980                 if (value) {
9981                         dev->features |= NETIF_F_TSO6;
9982                         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9983                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9984                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9985                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9986                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9987                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9988                                 dev->features |= NETIF_F_TSO_ECN;
9989                 } else
9990                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9991         }
9992         return ethtool_op_set_tso(dev, value);
9993 }
9994
9995 static int tg3_nway_reset(struct net_device *dev)
9996 {
9997         struct tg3 *tp = netdev_priv(dev);
9998         int r;
9999
10000         if (!netif_running(dev))
10001                 return -EAGAIN;
10002
10003         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
10004                 return -EINVAL;
10005
10006         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10007                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10008                         return -EAGAIN;
10009                 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
10010         } else {
10011                 u32 bmcr;
10012
10013                 spin_lock_bh(&tp->lock);
10014                 r = -EINVAL;
10015                 tg3_readphy(tp, MII_BMCR, &bmcr);
10016                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
10017                     ((bmcr & BMCR_ANENABLE) ||
10018                      (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
10019                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
10020                                                    BMCR_ANENABLE);
10021                         r = 0;
10022                 }
10023                 spin_unlock_bh(&tp->lock);
10024         }
10025
10026         return r;
10027 }
10028
10029 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10030 {
10031         struct tg3 *tp = netdev_priv(dev);
10032
10033         ering->rx_max_pending = tp->rx_std_ring_mask;
10034         ering->rx_mini_max_pending = 0;
10035         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
10036                 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
10037         else
10038                 ering->rx_jumbo_max_pending = 0;
10039
10040         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
10041
10042         ering->rx_pending = tp->rx_pending;
10043         ering->rx_mini_pending = 0;
10044         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
10045                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
10046         else
10047                 ering->rx_jumbo_pending = 0;
10048
10049         ering->tx_pending = tp->napi[0].tx_pending;
10050 }
10051
10052 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10053 {
10054         struct tg3 *tp = netdev_priv(dev);
10055         int i, irq_sync = 0, err = 0;
10056
10057         if ((ering->rx_pending > tp->rx_std_ring_mask) ||
10058             (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
10059             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
10060             (ering->tx_pending <= MAX_SKB_FRAGS) ||
10061             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
10062              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
10063                 return -EINVAL;
10064
10065         if (netif_running(dev)) {
10066                 tg3_phy_stop(tp);
10067                 tg3_netif_stop(tp);
10068                 irq_sync = 1;
10069         }
10070
10071         tg3_full_lock(tp, irq_sync);
10072
10073         tp->rx_pending = ering->rx_pending;
10074
10075         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
10076             tp->rx_pending > 63)
10077                 tp->rx_pending = 63;
10078         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
10079
10080         for (i = 0; i < tp->irq_max; i++)
10081                 tp->napi[i].tx_pending = ering->tx_pending;
10082
10083         if (netif_running(dev)) {
10084                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10085                 err = tg3_restart_hw(tp, 1);
10086                 if (!err)
10087                         tg3_netif_start(tp);
10088         }
10089
10090         tg3_full_unlock(tp);
10091
10092         if (irq_sync && !err)
10093                 tg3_phy_start(tp);
10094
10095         return err;
10096 }
10097
10098 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10099 {
10100         struct tg3 *tp = netdev_priv(dev);
10101
10102         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
10103
10104         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
10105                 epause->rx_pause = 1;
10106         else
10107                 epause->rx_pause = 0;
10108
10109         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
10110                 epause->tx_pause = 1;
10111         else
10112                 epause->tx_pause = 0;
10113 }
10114
10115 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10116 {
10117         struct tg3 *tp = netdev_priv(dev);
10118         int err = 0;
10119
10120         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10121                 u32 newadv;
10122                 struct phy_device *phydev;
10123
10124                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10125
10126                 if (!(phydev->supported & SUPPORTED_Pause) ||
10127                     (!(phydev->supported & SUPPORTED_Asym_Pause) &&
10128                      (epause->rx_pause != epause->tx_pause)))
10129                         return -EINVAL;
10130
10131                 tp->link_config.flowctrl = 0;
10132                 if (epause->rx_pause) {
10133                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
10134
10135                         if (epause->tx_pause) {
10136                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10137                                 newadv = ADVERTISED_Pause;
10138                         } else
10139                                 newadv = ADVERTISED_Pause |
10140                                          ADVERTISED_Asym_Pause;
10141                 } else if (epause->tx_pause) {
10142                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
10143                         newadv = ADVERTISED_Asym_Pause;
10144                 } else
10145                         newadv = 0;
10146
10147                 if (epause->autoneg)
10148                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10149                 else
10150                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10151
10152                 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
10153                         u32 oldadv = phydev->advertising &
10154                                      (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
10155                         if (oldadv != newadv) {
10156                                 phydev->advertising &=
10157                                         ~(ADVERTISED_Pause |
10158                                           ADVERTISED_Asym_Pause);
10159                                 phydev->advertising |= newadv;
10160                                 if (phydev->autoneg) {
10161                                         /*
10162                                          * Always renegotiate the link to
10163                                          * inform our link partner of our
10164                                          * flow control settings, even if the
10165                                          * flow control is forced.  Let
10166                                          * tg3_adjust_link() do the final
10167                                          * flow control setup.
10168                                          */
10169                                         return phy_start_aneg(phydev);
10170                                 }
10171                         }
10172
10173                         if (!epause->autoneg)
10174                                 tg3_setup_flow_control(tp, 0, 0);
10175                 } else {
10176                         tp->link_config.orig_advertising &=
10177                                         ~(ADVERTISED_Pause |
10178                                           ADVERTISED_Asym_Pause);
10179                         tp->link_config.orig_advertising |= newadv;
10180                 }
10181         } else {
10182                 int irq_sync = 0;
10183
10184                 if (netif_running(dev)) {
10185                         tg3_netif_stop(tp);
10186                         irq_sync = 1;
10187                 }
10188
10189                 tg3_full_lock(tp, irq_sync);
10190
10191                 if (epause->autoneg)
10192                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10193                 else
10194                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10195                 if (epause->rx_pause)
10196                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
10197                 else
10198                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10199                 if (epause->tx_pause)
10200                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
10201                 else
10202                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10203
10204                 if (netif_running(dev)) {
10205                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10206                         err = tg3_restart_hw(tp, 1);
10207                         if (!err)
10208                                 tg3_netif_start(tp);
10209                 }
10210
10211                 tg3_full_unlock(tp);
10212         }
10213
10214         return err;
10215 }
10216
10217 static u32 tg3_get_rx_csum(struct net_device *dev)
10218 {
10219         struct tg3 *tp = netdev_priv(dev);
10220         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10221 }
10222
10223 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10224 {
10225         struct tg3 *tp = netdev_priv(dev);
10226
10227         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10228                 if (data != 0)
10229                         return -EINVAL;
10230                 return 0;
10231         }
10232
10233         spin_lock_bh(&tp->lock);
10234         if (data)
10235                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10236         else
10237                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10238         spin_unlock_bh(&tp->lock);
10239
10240         return 0;
10241 }
10242
10243 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10244 {
10245         struct tg3 *tp = netdev_priv(dev);
10246
10247         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10248                 if (data != 0)
10249                         return -EINVAL;
10250                 return 0;
10251         }
10252
10253         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10254                 ethtool_op_set_tx_ipv6_csum(dev, data);
10255         else
10256                 ethtool_op_set_tx_csum(dev, data);
10257
10258         return 0;
10259 }
10260
10261 static int tg3_get_sset_count(struct net_device *dev, int sset)
10262 {
10263         switch (sset) {
10264         case ETH_SS_TEST:
10265                 return TG3_NUM_TEST;
10266         case ETH_SS_STATS:
10267                 return TG3_NUM_STATS;
10268         default:
10269                 return -EOPNOTSUPP;
10270         }
10271 }
10272
10273 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
10274 {
10275         switch (stringset) {
10276         case ETH_SS_STATS:
10277                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10278                 break;
10279         case ETH_SS_TEST:
10280                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10281                 break;
10282         default:
10283                 WARN_ON(1);     /* we need a WARN() */
10284                 break;
10285         }
10286 }
10287
10288 static int tg3_phys_id(struct net_device *dev, u32 data)
10289 {
10290         struct tg3 *tp = netdev_priv(dev);
10291         int i;
10292
10293         if (!netif_running(tp->dev))
10294                 return -EAGAIN;
10295
10296         if (data == 0)
10297                 data = UINT_MAX / 2;
10298
10299         for (i = 0; i < (data * 2); i++) {
10300                 if ((i % 2) == 0)
10301                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10302                                            LED_CTRL_1000MBPS_ON |
10303                                            LED_CTRL_100MBPS_ON |
10304                                            LED_CTRL_10MBPS_ON |
10305                                            LED_CTRL_TRAFFIC_OVERRIDE |
10306                                            LED_CTRL_TRAFFIC_BLINK |
10307                                            LED_CTRL_TRAFFIC_LED);
10308
10309                 else
10310                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10311                                            LED_CTRL_TRAFFIC_OVERRIDE);
10312
10313                 if (msleep_interruptible(500))
10314                         break;
10315         }
10316         tw32(MAC_LED_CTRL, tp->led_ctrl);
10317         return 0;
10318 }
10319
10320 static void tg3_get_ethtool_stats(struct net_device *dev,
10321                                    struct ethtool_stats *estats, u64 *tmp_stats)
10322 {
10323         struct tg3 *tp = netdev_priv(dev);
10324         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10325 }
10326
10327 #define NVRAM_TEST_SIZE 0x100
10328 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
10329 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
10330 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
10331 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10332 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10333
10334 static int tg3_test_nvram(struct tg3 *tp)
10335 {
10336         u32 csum, magic;
10337         __be32 *buf;
10338         int i, j, k, err = 0, size;
10339
10340         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10341                 return 0;
10342
10343         if (tg3_nvram_read(tp, 0, &magic) != 0)
10344                 return -EIO;
10345
10346         if (magic == TG3_EEPROM_MAGIC)
10347                 size = NVRAM_TEST_SIZE;
10348         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10349                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10350                     TG3_EEPROM_SB_FORMAT_1) {
10351                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10352                         case TG3_EEPROM_SB_REVISION_0:
10353                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10354                                 break;
10355                         case TG3_EEPROM_SB_REVISION_2:
10356                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10357                                 break;
10358                         case TG3_EEPROM_SB_REVISION_3:
10359                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10360                                 break;
10361                         default:
10362                                 return 0;
10363                         }
10364                 } else
10365                         return 0;
10366         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10367                 size = NVRAM_SELFBOOT_HW_SIZE;
10368         else
10369                 return -EIO;
10370
10371         buf = kmalloc(size, GFP_KERNEL);
10372         if (buf == NULL)
10373                 return -ENOMEM;
10374
10375         err = -EIO;
10376         for (i = 0, j = 0; i < size; i += 4, j++) {
10377                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10378                 if (err)
10379                         break;
10380         }
10381         if (i < size)
10382                 goto out;
10383
10384         /* Selfboot format */
10385         magic = be32_to_cpu(buf[0]);
10386         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10387             TG3_EEPROM_MAGIC_FW) {
10388                 u8 *buf8 = (u8 *) buf, csum8 = 0;
10389
10390                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10391                     TG3_EEPROM_SB_REVISION_2) {
10392                         /* For rev 2, the csum doesn't include the MBA. */
10393                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10394                                 csum8 += buf8[i];
10395                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10396                                 csum8 += buf8[i];
10397                 } else {
10398                         for (i = 0; i < size; i++)
10399                                 csum8 += buf8[i];
10400                 }
10401
10402                 if (csum8 == 0) {
10403                         err = 0;
10404                         goto out;
10405                 }
10406
10407                 err = -EIO;
10408                 goto out;
10409         }
10410
10411         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10412             TG3_EEPROM_MAGIC_HW) {
10413                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10414                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10415                 u8 *buf8 = (u8 *) buf;
10416
10417                 /* Separate the parity bits and the data bytes.  */
10418                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10419                         if ((i == 0) || (i == 8)) {
10420                                 int l;
10421                                 u8 msk;
10422
10423                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10424                                         parity[k++] = buf8[i] & msk;
10425                                 i++;
10426                         } else if (i == 16) {
10427                                 int l;
10428                                 u8 msk;
10429
10430                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10431                                         parity[k++] = buf8[i] & msk;
10432                                 i++;
10433
10434                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10435                                         parity[k++] = buf8[i] & msk;
10436                                 i++;
10437                         }
10438                         data[j++] = buf8[i];
10439                 }
10440
10441                 err = -EIO;
10442                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10443                         u8 hw8 = hweight8(data[i]);
10444
10445                         if ((hw8 & 0x1) && parity[i])
10446                                 goto out;
10447                         else if (!(hw8 & 0x1) && !parity[i])
10448                                 goto out;
10449                 }
10450                 err = 0;
10451                 goto out;
10452         }
10453
10454         /* Bootstrap checksum at offset 0x10 */
10455         csum = calc_crc((unsigned char *) buf, 0x10);
10456         if (csum != be32_to_cpu(buf[0x10/4]))
10457                 goto out;
10458
10459         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10460         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10461         if (csum != be32_to_cpu(buf[0xfc/4]))
10462                 goto out;
10463
10464         err = 0;
10465
10466 out:
10467         kfree(buf);
10468         return err;
10469 }
10470
10471 #define TG3_SERDES_TIMEOUT_SEC  2
10472 #define TG3_COPPER_TIMEOUT_SEC  6
10473
10474 static int tg3_test_link(struct tg3 *tp)
10475 {
10476         int i, max;
10477
10478         if (!netif_running(tp->dev))
10479                 return -ENODEV;
10480
10481         if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
10482                 max = TG3_SERDES_TIMEOUT_SEC;
10483         else
10484                 max = TG3_COPPER_TIMEOUT_SEC;
10485
10486         for (i = 0; i < max; i++) {
10487                 if (netif_carrier_ok(tp->dev))
10488                         return 0;
10489
10490                 if (msleep_interruptible(1000))
10491                         break;
10492         }
10493
10494         return -EIO;
10495 }
10496
10497 /* Only test the commonly used registers */
10498 static int tg3_test_registers(struct tg3 *tp)
10499 {
10500         int i, is_5705, is_5750;
10501         u32 offset, read_mask, write_mask, val, save_val, read_val;
10502         static struct {
10503                 u16 offset;
10504                 u16 flags;
10505 #define TG3_FL_5705     0x1
10506 #define TG3_FL_NOT_5705 0x2
10507 #define TG3_FL_NOT_5788 0x4
10508 #define TG3_FL_NOT_5750 0x8
10509                 u32 read_mask;
10510                 u32 write_mask;
10511         } reg_tbl[] = {
10512                 /* MAC Control Registers */
10513                 { MAC_MODE, TG3_FL_NOT_5705,
10514                         0x00000000, 0x00ef6f8c },
10515                 { MAC_MODE, TG3_FL_5705,
10516                         0x00000000, 0x01ef6b8c },
10517                 { MAC_STATUS, TG3_FL_NOT_5705,
10518                         0x03800107, 0x00000000 },
10519                 { MAC_STATUS, TG3_FL_5705,
10520                         0x03800100, 0x00000000 },
10521                 { MAC_ADDR_0_HIGH, 0x0000,
10522                         0x00000000, 0x0000ffff },
10523                 { MAC_ADDR_0_LOW, 0x0000,
10524                         0x00000000, 0xffffffff },
10525                 { MAC_RX_MTU_SIZE, 0x0000,
10526                         0x00000000, 0x0000ffff },
10527                 { MAC_TX_MODE, 0x0000,
10528                         0x00000000, 0x00000070 },
10529                 { MAC_TX_LENGTHS, 0x0000,
10530                         0x00000000, 0x00003fff },
10531                 { MAC_RX_MODE, TG3_FL_NOT_5705,
10532                         0x00000000, 0x000007fc },
10533                 { MAC_RX_MODE, TG3_FL_5705,
10534                         0x00000000, 0x000007dc },
10535                 { MAC_HASH_REG_0, 0x0000,
10536                         0x00000000, 0xffffffff },
10537                 { MAC_HASH_REG_1, 0x0000,
10538                         0x00000000, 0xffffffff },
10539                 { MAC_HASH_REG_2, 0x0000,
10540                         0x00000000, 0xffffffff },
10541                 { MAC_HASH_REG_3, 0x0000,
10542                         0x00000000, 0xffffffff },
10543
10544                 /* Receive Data and Receive BD Initiator Control Registers. */
10545                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10546                         0x00000000, 0xffffffff },
10547                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10548                         0x00000000, 0xffffffff },
10549                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10550                         0x00000000, 0x00000003 },
10551                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10552                         0x00000000, 0xffffffff },
10553                 { RCVDBDI_STD_BD+0, 0x0000,
10554                         0x00000000, 0xffffffff },
10555                 { RCVDBDI_STD_BD+4, 0x0000,
10556                         0x00000000, 0xffffffff },
10557                 { RCVDBDI_STD_BD+8, 0x0000,
10558                         0x00000000, 0xffff0002 },
10559                 { RCVDBDI_STD_BD+0xc, 0x0000,
10560                         0x00000000, 0xffffffff },
10561
10562                 /* Receive BD Initiator Control Registers. */
10563                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10564                         0x00000000, 0xffffffff },
10565                 { RCVBDI_STD_THRESH, TG3_FL_5705,
10566                         0x00000000, 0x000003ff },
10567                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10568                         0x00000000, 0xffffffff },
10569
10570                 /* Host Coalescing Control Registers. */
10571                 { HOSTCC_MODE, TG3_FL_NOT_5705,
10572                         0x00000000, 0x00000004 },
10573                 { HOSTCC_MODE, TG3_FL_5705,
10574                         0x00000000, 0x000000f6 },
10575                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10576                         0x00000000, 0xffffffff },
10577                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10578                         0x00000000, 0x000003ff },
10579                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10580                         0x00000000, 0xffffffff },
10581                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10582                         0x00000000, 0x000003ff },
10583                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10584                         0x00000000, 0xffffffff },
10585                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10586                         0x00000000, 0x000000ff },
10587                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10588                         0x00000000, 0xffffffff },
10589                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10590                         0x00000000, 0x000000ff },
10591                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10592                         0x00000000, 0xffffffff },
10593                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10594                         0x00000000, 0xffffffff },
10595                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10596                         0x00000000, 0xffffffff },
10597                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10598                         0x00000000, 0x000000ff },
10599                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10600                         0x00000000, 0xffffffff },
10601                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10602                         0x00000000, 0x000000ff },
10603                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10604                         0x00000000, 0xffffffff },
10605                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10606                         0x00000000, 0xffffffff },
10607                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10608                         0x00000000, 0xffffffff },
10609                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10610                         0x00000000, 0xffffffff },
10611                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10612                         0x00000000, 0xffffffff },
10613                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10614                         0xffffffff, 0x00000000 },
10615                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10616                         0xffffffff, 0x00000000 },
10617
10618                 /* Buffer Manager Control Registers. */
10619                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10620                         0x00000000, 0x007fff80 },
10621                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10622                         0x00000000, 0x007fffff },
10623                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10624                         0x00000000, 0x0000003f },
10625                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10626                         0x00000000, 0x000001ff },
10627                 { BUFMGR_MB_HIGH_WATER, 0x0000,
10628                         0x00000000, 0x000001ff },
10629                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10630                         0xffffffff, 0x00000000 },
10631                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10632                         0xffffffff, 0x00000000 },
10633
10634                 /* Mailbox Registers */
10635                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10636                         0x00000000, 0x000001ff },
10637                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10638                         0x00000000, 0x000001ff },
10639                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10640                         0x00000000, 0x000007ff },
10641                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10642                         0x00000000, 0x000001ff },
10643
10644                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10645         };
10646
10647         is_5705 = is_5750 = 0;
10648         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10649                 is_5705 = 1;
10650                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10651                         is_5750 = 1;
10652         }
10653
10654         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10655                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10656                         continue;
10657
10658                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10659                         continue;
10660
10661                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10662                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
10663                         continue;
10664
10665                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10666                         continue;
10667
10668                 offset = (u32) reg_tbl[i].offset;
10669                 read_mask = reg_tbl[i].read_mask;
10670                 write_mask = reg_tbl[i].write_mask;
10671
10672                 /* Save the original register content */
10673                 save_val = tr32(offset);
10674
10675                 /* Determine the read-only value. */
10676                 read_val = save_val & read_mask;
10677
10678                 /* Write zero to the register, then make sure the read-only bits
10679                  * are not changed and the read/write bits are all zeros.
10680                  */
10681                 tw32(offset, 0);
10682
10683                 val = tr32(offset);
10684
10685                 /* Test the read-only and read/write bits. */
10686                 if (((val & read_mask) != read_val) || (val & write_mask))
10687                         goto out;
10688
10689                 /* Write ones to all the bits defined by RdMask and WrMask, then
10690                  * make sure the read-only bits are not changed and the
10691                  * read/write bits are all ones.
10692                  */
10693                 tw32(offset, read_mask | write_mask);
10694
10695                 val = tr32(offset);
10696
10697                 /* Test the read-only bits. */
10698                 if ((val & read_mask) != read_val)
10699                         goto out;
10700
10701                 /* Test the read/write bits. */
10702                 if ((val & write_mask) != write_mask)
10703                         goto out;
10704
10705                 tw32(offset, save_val);
10706         }
10707
10708         return 0;
10709
10710 out:
10711         if (netif_msg_hw(tp))
10712                 netdev_err(tp->dev,
10713                            "Register test failed at offset %x\n", offset);
10714         tw32(offset, save_val);
10715         return -EIO;
10716 }
10717
10718 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10719 {
10720         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10721         int i;
10722         u32 j;
10723
10724         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10725                 for (j = 0; j < len; j += 4) {
10726                         u32 val;
10727
10728                         tg3_write_mem(tp, offset + j, test_pattern[i]);
10729                         tg3_read_mem(tp, offset + j, &val);
10730                         if (val != test_pattern[i])
10731                                 return -EIO;
10732                 }
10733         }
10734         return 0;
10735 }
10736
10737 static int tg3_test_memory(struct tg3 *tp)
10738 {
10739         static struct mem_entry {
10740                 u32 offset;
10741                 u32 len;
10742         } mem_tbl_570x[] = {
10743                 { 0x00000000, 0x00b50},
10744                 { 0x00002000, 0x1c000},
10745                 { 0xffffffff, 0x00000}
10746         }, mem_tbl_5705[] = {
10747                 { 0x00000100, 0x0000c},
10748                 { 0x00000200, 0x00008},
10749                 { 0x00004000, 0x00800},
10750                 { 0x00006000, 0x01000},
10751                 { 0x00008000, 0x02000},
10752                 { 0x00010000, 0x0e000},
10753                 { 0xffffffff, 0x00000}
10754         }, mem_tbl_5755[] = {
10755                 { 0x00000200, 0x00008},
10756                 { 0x00004000, 0x00800},
10757                 { 0x00006000, 0x00800},
10758                 { 0x00008000, 0x02000},
10759                 { 0x00010000, 0x0c000},
10760                 { 0xffffffff, 0x00000}
10761         }, mem_tbl_5906[] = {
10762                 { 0x00000200, 0x00008},
10763                 { 0x00004000, 0x00400},
10764                 { 0x00006000, 0x00400},
10765                 { 0x00008000, 0x01000},
10766                 { 0x00010000, 0x01000},
10767                 { 0xffffffff, 0x00000}
10768         }, mem_tbl_5717[] = {
10769                 { 0x00000200, 0x00008},
10770                 { 0x00010000, 0x0a000},
10771                 { 0x00020000, 0x13c00},
10772                 { 0xffffffff, 0x00000}
10773         }, mem_tbl_57765[] = {
10774                 { 0x00000200, 0x00008},
10775                 { 0x00004000, 0x00800},
10776                 { 0x00006000, 0x09800},
10777                 { 0x00010000, 0x0a000},
10778                 { 0xffffffff, 0x00000}
10779         };
10780         struct mem_entry *mem_tbl;
10781         int err = 0;
10782         int i;
10783
10784         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
10785             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
10786                 mem_tbl = mem_tbl_5717;
10787         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10788                 mem_tbl = mem_tbl_57765;
10789         else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10790                 mem_tbl = mem_tbl_5755;
10791         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10792                 mem_tbl = mem_tbl_5906;
10793         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10794                 mem_tbl = mem_tbl_5705;
10795         else
10796                 mem_tbl = mem_tbl_570x;
10797
10798         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10799                 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
10800                 if (err)
10801                         break;
10802         }
10803
10804         return err;
10805 }
10806
10807 #define TG3_MAC_LOOPBACK        0
10808 #define TG3_PHY_LOOPBACK        1
10809
10810 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10811 {
10812         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10813         u32 desc_idx, coal_now;
10814         struct sk_buff *skb, *rx_skb;
10815         u8 *tx_data;
10816         dma_addr_t map;
10817         int num_pkts, tx_len, rx_len, i, err;
10818         struct tg3_rx_buffer_desc *desc;
10819         struct tg3_napi *tnapi, *rnapi;
10820         struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
10821
10822         tnapi = &tp->napi[0];
10823         rnapi = &tp->napi[0];
10824         if (tp->irq_cnt > 1) {
10825                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
10826                         rnapi = &tp->napi[1];
10827                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
10828                         tnapi = &tp->napi[1];
10829         }
10830         coal_now = tnapi->coal_now | rnapi->coal_now;
10831
10832         if (loopback_mode == TG3_MAC_LOOPBACK) {
10833                 /* HW errata - mac loopback fails in some cases on 5780.
10834                  * Normal traffic and PHY loopback are not affected by
10835                  * errata.
10836                  */
10837                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10838                         return 0;
10839
10840                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10841                            MAC_MODE_PORT_INT_LPBACK;
10842                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10843                         mac_mode |= MAC_MODE_LINK_POLARITY;
10844                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
10845                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10846                 else
10847                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10848                 tw32(MAC_MODE, mac_mode);
10849         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10850                 u32 val;
10851
10852                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10853                         tg3_phy_fet_toggle_apd(tp, false);
10854                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10855                 } else
10856                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10857
10858                 tg3_phy_toggle_automdix(tp, 0);
10859
10860                 tg3_writephy(tp, MII_BMCR, val);
10861                 udelay(40);
10862
10863                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10864                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10865                         tg3_writephy(tp, MII_TG3_FET_PTEST,
10866                                      MII_TG3_FET_PTEST_FRC_TX_LINK |
10867                                      MII_TG3_FET_PTEST_FRC_TX_LOCK);
10868                         /* The write needs to be flushed for the AC131 */
10869                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10870                                 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
10871                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10872                 } else
10873                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10874
10875                 /* reset to prevent losing 1st rx packet intermittently */
10876                 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10877                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10878                         udelay(10);
10879                         tw32_f(MAC_RX_MODE, tp->rx_mode);
10880                 }
10881                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10882                         u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
10883                         if (masked_phy_id == TG3_PHY_ID_BCM5401)
10884                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10885                         else if (masked_phy_id == TG3_PHY_ID_BCM5411)
10886                                 mac_mode |= MAC_MODE_LINK_POLARITY;
10887                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
10888                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10889                 }
10890                 tw32(MAC_MODE, mac_mode);
10891         } else {
10892                 return -EINVAL;
10893         }
10894
10895         err = -EIO;
10896
10897         tx_len = 1514;
10898         skb = netdev_alloc_skb(tp->dev, tx_len);
10899         if (!skb)
10900                 return -ENOMEM;
10901
10902         tx_data = skb_put(skb, tx_len);
10903         memcpy(tx_data, tp->dev->dev_addr, 6);
10904         memset(tx_data + 6, 0x0, 8);
10905
10906         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10907
10908         for (i = 14; i < tx_len; i++)
10909                 tx_data[i] = (u8) (i & 0xff);
10910
10911         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10912         if (pci_dma_mapping_error(tp->pdev, map)) {
10913                 dev_kfree_skb(skb);
10914                 return -EIO;
10915         }
10916
10917         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10918                rnapi->coal_now);
10919
10920         udelay(10);
10921
10922         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10923
10924         num_pkts = 0;
10925
10926         tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10927
10928         tnapi->tx_prod++;
10929         num_pkts++;
10930
10931         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10932         tr32_mailbox(tnapi->prodmbox);
10933
10934         udelay(10);
10935
10936         /* 350 usec to allow enough time on some 10/100 Mbps devices.  */
10937         for (i = 0; i < 35; i++) {
10938                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10939                        coal_now);
10940
10941                 udelay(10);
10942
10943                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10944                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10945                 if ((tx_idx == tnapi->tx_prod) &&
10946                     (rx_idx == (rx_start_idx + num_pkts)))
10947                         break;
10948         }
10949
10950         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10951         dev_kfree_skb(skb);
10952
10953         if (tx_idx != tnapi->tx_prod)
10954                 goto out;
10955
10956         if (rx_idx != rx_start_idx + num_pkts)
10957                 goto out;
10958
10959         desc = &rnapi->rx_rcb[rx_start_idx];
10960         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10961         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10962         if (opaque_key != RXD_OPAQUE_RING_STD)
10963                 goto out;
10964
10965         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10966             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10967                 goto out;
10968
10969         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10970         if (rx_len != tx_len)
10971                 goto out;
10972
10973         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10974
10975         map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10976         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10977
10978         for (i = 14; i < tx_len; i++) {
10979                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10980                         goto out;
10981         }
10982         err = 0;
10983
10984         /* tg3_free_rings will unmap and free the rx_skb */
10985 out:
10986         return err;
10987 }
10988
10989 #define TG3_MAC_LOOPBACK_FAILED         1
10990 #define TG3_PHY_LOOPBACK_FAILED         2
10991 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
10992                                          TG3_PHY_LOOPBACK_FAILED)
10993
10994 static int tg3_test_loopback(struct tg3 *tp)
10995 {
10996         int err = 0;
10997         u32 cpmuctrl = 0;
10998
10999         if (!netif_running(tp->dev))
11000                 return TG3_LOOPBACK_FAILED;
11001
11002         err = tg3_reset_hw(tp, 1);
11003         if (err)
11004                 return TG3_LOOPBACK_FAILED;
11005
11006         /* Turn off gphy autopowerdown. */
11007         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11008                 tg3_phy_toggle_apd(tp, false);
11009
11010         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
11011                 int i;
11012                 u32 status;
11013
11014                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
11015
11016                 /* Wait for up to 40 microseconds to acquire lock. */
11017                 for (i = 0; i < 4; i++) {
11018                         status = tr32(TG3_CPMU_MUTEX_GNT);
11019                         if (status == CPMU_MUTEX_GNT_DRIVER)
11020                                 break;
11021                         udelay(10);
11022                 }
11023
11024                 if (status != CPMU_MUTEX_GNT_DRIVER)
11025                         return TG3_LOOPBACK_FAILED;
11026
11027                 /* Turn off link-based power management. */
11028                 cpmuctrl = tr32(TG3_CPMU_CTRL);
11029                 tw32(TG3_CPMU_CTRL,
11030                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
11031                                   CPMU_CTRL_LINK_AWARE_MODE));
11032         }
11033
11034         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
11035                 err |= TG3_MAC_LOOPBACK_FAILED;
11036
11037         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
11038                 tw32(TG3_CPMU_CTRL, cpmuctrl);
11039
11040                 /* Release the mutex */
11041                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
11042         }
11043
11044         if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
11045             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
11046                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
11047                         err |= TG3_PHY_LOOPBACK_FAILED;
11048         }
11049
11050         /* Re-enable gphy autopowerdown. */
11051         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11052                 tg3_phy_toggle_apd(tp, true);
11053
11054         return err;
11055 }
11056
11057 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
11058                           u64 *data)
11059 {
11060         struct tg3 *tp = netdev_priv(dev);
11061
11062         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11063                 tg3_set_power_state(tp, PCI_D0);
11064
11065         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
11066
11067         if (tg3_test_nvram(tp) != 0) {
11068                 etest->flags |= ETH_TEST_FL_FAILED;
11069                 data[0] = 1;
11070         }
11071         if (tg3_test_link(tp) != 0) {
11072                 etest->flags |= ETH_TEST_FL_FAILED;
11073                 data[1] = 1;
11074         }
11075         if (etest->flags & ETH_TEST_FL_OFFLINE) {
11076                 int err, err2 = 0, irq_sync = 0;
11077
11078                 if (netif_running(dev)) {
11079                         tg3_phy_stop(tp);
11080                         tg3_netif_stop(tp);
11081                         irq_sync = 1;
11082                 }
11083
11084                 tg3_full_lock(tp, irq_sync);
11085
11086                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
11087                 err = tg3_nvram_lock(tp);
11088                 tg3_halt_cpu(tp, RX_CPU_BASE);
11089                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11090                         tg3_halt_cpu(tp, TX_CPU_BASE);
11091                 if (!err)
11092                         tg3_nvram_unlock(tp);
11093
11094                 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
11095                         tg3_phy_reset(tp);
11096
11097                 if (tg3_test_registers(tp) != 0) {
11098                         etest->flags |= ETH_TEST_FL_FAILED;
11099                         data[2] = 1;
11100                 }
11101                 if (tg3_test_memory(tp) != 0) {
11102                         etest->flags |= ETH_TEST_FL_FAILED;
11103                         data[3] = 1;
11104                 }
11105                 if ((data[4] = tg3_test_loopback(tp)) != 0)
11106                         etest->flags |= ETH_TEST_FL_FAILED;
11107
11108                 tg3_full_unlock(tp);
11109
11110                 if (tg3_test_interrupt(tp) != 0) {
11111                         etest->flags |= ETH_TEST_FL_FAILED;
11112                         data[5] = 1;
11113                 }
11114
11115                 tg3_full_lock(tp, 0);
11116
11117                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11118                 if (netif_running(dev)) {
11119                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11120                         err2 = tg3_restart_hw(tp, 1);
11121                         if (!err2)
11122                                 tg3_netif_start(tp);
11123                 }
11124
11125                 tg3_full_unlock(tp);
11126
11127                 if (irq_sync && !err2)
11128                         tg3_phy_start(tp);
11129         }
11130         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11131                 tg3_set_power_state(tp, PCI_D3hot);
11132
11133 }
11134
11135 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11136 {
11137         struct mii_ioctl_data *data = if_mii(ifr);
11138         struct tg3 *tp = netdev_priv(dev);
11139         int err;
11140
11141         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
11142                 struct phy_device *phydev;
11143                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
11144                         return -EAGAIN;
11145                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11146                 return phy_mii_ioctl(phydev, ifr, cmd);
11147         }
11148
11149         switch (cmd) {
11150         case SIOCGMIIPHY:
11151                 data->phy_id = tp->phy_addr;
11152
11153                 /* fallthru */
11154         case SIOCGMIIREG: {
11155                 u32 mii_regval;
11156
11157                 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11158                         break;                  /* We have no PHY */
11159
11160                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11161                         return -EAGAIN;
11162
11163                 spin_lock_bh(&tp->lock);
11164                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
11165                 spin_unlock_bh(&tp->lock);
11166
11167                 data->val_out = mii_regval;
11168
11169                 return err;
11170         }
11171
11172         case SIOCSMIIREG:
11173                 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11174                         break;                  /* We have no PHY */
11175
11176                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11177                         return -EAGAIN;
11178
11179                 spin_lock_bh(&tp->lock);
11180                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
11181                 spin_unlock_bh(&tp->lock);
11182
11183                 return err;
11184
11185         default:
11186                 /* do nothing */
11187                 break;
11188         }
11189         return -EOPNOTSUPP;
11190 }
11191
11192 #if TG3_VLAN_TAG_USED
11193 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
11194 {
11195         struct tg3 *tp = netdev_priv(dev);
11196
11197         if (!netif_running(dev)) {
11198                 tp->vlgrp = grp;
11199                 return;
11200         }
11201
11202         tg3_netif_stop(tp);
11203
11204         tg3_full_lock(tp, 0);
11205
11206         tp->vlgrp = grp;
11207
11208         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11209         __tg3_set_rx_mode(dev);
11210
11211         tg3_netif_start(tp);
11212
11213         tg3_full_unlock(tp);
11214 }
11215 #endif
11216
11217 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11218 {
11219         struct tg3 *tp = netdev_priv(dev);
11220
11221         memcpy(ec, &tp->coal, sizeof(*ec));
11222         return 0;
11223 }
11224
11225 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11226 {
11227         struct tg3 *tp = netdev_priv(dev);
11228         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11229         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11230
11231         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11232                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11233                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11234                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11235                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11236         }
11237
11238         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11239             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11240             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11241             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11242             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11243             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11244             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11245             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11246             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11247             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11248                 return -EINVAL;
11249
11250         /* No rx interrupts will be generated if both are zero */
11251         if ((ec->rx_coalesce_usecs == 0) &&
11252             (ec->rx_max_coalesced_frames == 0))
11253                 return -EINVAL;
11254
11255         /* No tx interrupts will be generated if both are zero */
11256         if ((ec->tx_coalesce_usecs == 0) &&
11257             (ec->tx_max_coalesced_frames == 0))
11258                 return -EINVAL;
11259
11260         /* Only copy relevant parameters, ignore all others. */
11261         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11262         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11263         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11264         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11265         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11266         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11267         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11268         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11269         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11270
11271         if (netif_running(dev)) {
11272                 tg3_full_lock(tp, 0);
11273                 __tg3_set_coalesce(tp, &tp->coal);
11274                 tg3_full_unlock(tp);
11275         }
11276         return 0;
11277 }
11278
11279 static const struct ethtool_ops tg3_ethtool_ops = {
11280         .get_settings           = tg3_get_settings,
11281         .set_settings           = tg3_set_settings,
11282         .get_drvinfo            = tg3_get_drvinfo,
11283         .get_regs_len           = tg3_get_regs_len,
11284         .get_regs               = tg3_get_regs,
11285         .get_wol                = tg3_get_wol,
11286         .set_wol                = tg3_set_wol,
11287         .get_msglevel           = tg3_get_msglevel,
11288         .set_msglevel           = tg3_set_msglevel,
11289         .nway_reset             = tg3_nway_reset,
11290         .get_link               = ethtool_op_get_link,
11291         .get_eeprom_len         = tg3_get_eeprom_len,
11292         .get_eeprom             = tg3_get_eeprom,
11293         .set_eeprom             = tg3_set_eeprom,
11294         .get_ringparam          = tg3_get_ringparam,
11295         .set_ringparam          = tg3_set_ringparam,
11296         .get_pauseparam         = tg3_get_pauseparam,
11297         .set_pauseparam         = tg3_set_pauseparam,
11298         .get_rx_csum            = tg3_get_rx_csum,
11299         .set_rx_csum            = tg3_set_rx_csum,
11300         .set_tx_csum            = tg3_set_tx_csum,
11301         .set_sg                 = ethtool_op_set_sg,
11302         .set_tso                = tg3_set_tso,
11303         .self_test              = tg3_self_test,
11304         .get_strings            = tg3_get_strings,
11305         .phys_id                = tg3_phys_id,
11306         .get_ethtool_stats      = tg3_get_ethtool_stats,
11307         .get_coalesce           = tg3_get_coalesce,
11308         .set_coalesce           = tg3_set_coalesce,
11309         .get_sset_count         = tg3_get_sset_count,
11310 };
11311
11312 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11313 {
11314         u32 cursize, val, magic;
11315
11316         tp->nvram_size = EEPROM_CHIP_SIZE;
11317
11318         if (tg3_nvram_read(tp, 0, &magic) != 0)
11319                 return;
11320
11321         if ((magic != TG3_EEPROM_MAGIC) &&
11322             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11323             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11324                 return;
11325
11326         /*
11327          * Size the chip by reading offsets at increasing powers of two.
11328          * When we encounter our validation signature, we know the addressing
11329          * has wrapped around, and thus have our chip size.
11330          */
11331         cursize = 0x10;
11332
11333         while (cursize < tp->nvram_size) {
11334                 if (tg3_nvram_read(tp, cursize, &val) != 0)
11335                         return;
11336
11337                 if (val == magic)
11338                         break;
11339
11340                 cursize <<= 1;
11341         }
11342
11343         tp->nvram_size = cursize;
11344 }
11345
11346 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11347 {
11348         u32 val;
11349
11350         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11351             tg3_nvram_read(tp, 0, &val) != 0)
11352                 return;
11353
11354         /* Selfboot format */
11355         if (val != TG3_EEPROM_MAGIC) {
11356                 tg3_get_eeprom_size(tp);
11357                 return;
11358         }
11359
11360         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11361                 if (val != 0) {
11362                         /* This is confusing.  We want to operate on the
11363                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
11364                          * call will read from NVRAM and byteswap the data
11365                          * according to the byteswapping settings for all
11366                          * other register accesses.  This ensures the data we
11367                          * want will always reside in the lower 16-bits.
11368                          * However, the data in NVRAM is in LE format, which
11369                          * means the data from the NVRAM read will always be
11370                          * opposite the endianness of the CPU.  The 16-bit
11371                          * byteswap then brings the data to CPU endianness.
11372                          */
11373                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11374                         return;
11375                 }
11376         }
11377         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11378 }
11379
11380 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11381 {
11382         u32 nvcfg1;
11383
11384         nvcfg1 = tr32(NVRAM_CFG1);
11385         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11386                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11387         } else {
11388                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11389                 tw32(NVRAM_CFG1, nvcfg1);
11390         }
11391
11392         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11393             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11394                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11395                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11396                         tp->nvram_jedecnum = JEDEC_ATMEL;
11397                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11398                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11399                         break;
11400                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11401                         tp->nvram_jedecnum = JEDEC_ATMEL;
11402                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11403                         break;
11404                 case FLASH_VENDOR_ATMEL_EEPROM:
11405                         tp->nvram_jedecnum = JEDEC_ATMEL;
11406                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11407                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11408                         break;
11409                 case FLASH_VENDOR_ST:
11410                         tp->nvram_jedecnum = JEDEC_ST;
11411                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11412                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11413                         break;
11414                 case FLASH_VENDOR_SAIFUN:
11415                         tp->nvram_jedecnum = JEDEC_SAIFUN;
11416                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11417                         break;
11418                 case FLASH_VENDOR_SST_SMALL:
11419                 case FLASH_VENDOR_SST_LARGE:
11420                         tp->nvram_jedecnum = JEDEC_SST;
11421                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11422                         break;
11423                 }
11424         } else {
11425                 tp->nvram_jedecnum = JEDEC_ATMEL;
11426                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11427                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11428         }
11429 }
11430
11431 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11432 {
11433         switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11434         case FLASH_5752PAGE_SIZE_256:
11435                 tp->nvram_pagesize = 256;
11436                 break;
11437         case FLASH_5752PAGE_SIZE_512:
11438                 tp->nvram_pagesize = 512;
11439                 break;
11440         case FLASH_5752PAGE_SIZE_1K:
11441                 tp->nvram_pagesize = 1024;
11442                 break;
11443         case FLASH_5752PAGE_SIZE_2K:
11444                 tp->nvram_pagesize = 2048;
11445                 break;
11446         case FLASH_5752PAGE_SIZE_4K:
11447                 tp->nvram_pagesize = 4096;
11448                 break;
11449         case FLASH_5752PAGE_SIZE_264:
11450                 tp->nvram_pagesize = 264;
11451                 break;
11452         case FLASH_5752PAGE_SIZE_528:
11453                 tp->nvram_pagesize = 528;
11454                 break;
11455         }
11456 }
11457
11458 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11459 {
11460         u32 nvcfg1;
11461
11462         nvcfg1 = tr32(NVRAM_CFG1);
11463
11464         /* NVRAM protection for TPM */
11465         if (nvcfg1 & (1 << 27))
11466                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11467
11468         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11469         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11470         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11471                 tp->nvram_jedecnum = JEDEC_ATMEL;
11472                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11473                 break;
11474         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11475                 tp->nvram_jedecnum = JEDEC_ATMEL;
11476                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11477                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11478                 break;
11479         case FLASH_5752VENDOR_ST_M45PE10:
11480         case FLASH_5752VENDOR_ST_M45PE20:
11481         case FLASH_5752VENDOR_ST_M45PE40:
11482                 tp->nvram_jedecnum = JEDEC_ST;
11483                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11484                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11485                 break;
11486         }
11487
11488         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11489                 tg3_nvram_get_pagesize(tp, nvcfg1);
11490         } else {
11491                 /* For eeprom, set pagesize to maximum eeprom size */
11492                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11493
11494                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11495                 tw32(NVRAM_CFG1, nvcfg1);
11496         }
11497 }
11498
11499 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11500 {
11501         u32 nvcfg1, protect = 0;
11502
11503         nvcfg1 = tr32(NVRAM_CFG1);
11504
11505         /* NVRAM protection for TPM */
11506         if (nvcfg1 & (1 << 27)) {
11507                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11508                 protect = 1;
11509         }
11510
11511         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11512         switch (nvcfg1) {
11513         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11514         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11515         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11516         case FLASH_5755VENDOR_ATMEL_FLASH_5:
11517                 tp->nvram_jedecnum = JEDEC_ATMEL;
11518                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11519                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11520                 tp->nvram_pagesize = 264;
11521                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11522                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11523                         tp->nvram_size = (protect ? 0x3e200 :
11524                                           TG3_NVRAM_SIZE_512KB);
11525                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11526                         tp->nvram_size = (protect ? 0x1f200 :
11527                                           TG3_NVRAM_SIZE_256KB);
11528                 else
11529                         tp->nvram_size = (protect ? 0x1f200 :
11530                                           TG3_NVRAM_SIZE_128KB);
11531                 break;
11532         case FLASH_5752VENDOR_ST_M45PE10:
11533         case FLASH_5752VENDOR_ST_M45PE20:
11534         case FLASH_5752VENDOR_ST_M45PE40:
11535                 tp->nvram_jedecnum = JEDEC_ST;
11536                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11537                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11538                 tp->nvram_pagesize = 256;
11539                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11540                         tp->nvram_size = (protect ?
11541                                           TG3_NVRAM_SIZE_64KB :
11542                                           TG3_NVRAM_SIZE_128KB);
11543                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11544                         tp->nvram_size = (protect ?
11545                                           TG3_NVRAM_SIZE_64KB :
11546                                           TG3_NVRAM_SIZE_256KB);
11547                 else
11548                         tp->nvram_size = (protect ?
11549                                           TG3_NVRAM_SIZE_128KB :
11550                                           TG3_NVRAM_SIZE_512KB);
11551                 break;
11552         }
11553 }
11554
11555 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11556 {
11557         u32 nvcfg1;
11558
11559         nvcfg1 = tr32(NVRAM_CFG1);
11560
11561         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11562         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11563         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11564         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11565         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11566                 tp->nvram_jedecnum = JEDEC_ATMEL;
11567                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11568                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11569
11570                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11571                 tw32(NVRAM_CFG1, nvcfg1);
11572                 break;
11573         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11574         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11575         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11576         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11577                 tp->nvram_jedecnum = JEDEC_ATMEL;
11578                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11579                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11580                 tp->nvram_pagesize = 264;
11581                 break;
11582         case FLASH_5752VENDOR_ST_M45PE10:
11583         case FLASH_5752VENDOR_ST_M45PE20:
11584         case FLASH_5752VENDOR_ST_M45PE40:
11585                 tp->nvram_jedecnum = JEDEC_ST;
11586                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11587                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11588                 tp->nvram_pagesize = 256;
11589                 break;
11590         }
11591 }
11592
11593 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11594 {
11595         u32 nvcfg1, protect = 0;
11596
11597         nvcfg1 = tr32(NVRAM_CFG1);
11598
11599         /* NVRAM protection for TPM */
11600         if (nvcfg1 & (1 << 27)) {
11601                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11602                 protect = 1;
11603         }
11604
11605         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11606         switch (nvcfg1) {
11607         case FLASH_5761VENDOR_ATMEL_ADB021D:
11608         case FLASH_5761VENDOR_ATMEL_ADB041D:
11609         case FLASH_5761VENDOR_ATMEL_ADB081D:
11610         case FLASH_5761VENDOR_ATMEL_ADB161D:
11611         case FLASH_5761VENDOR_ATMEL_MDB021D:
11612         case FLASH_5761VENDOR_ATMEL_MDB041D:
11613         case FLASH_5761VENDOR_ATMEL_MDB081D:
11614         case FLASH_5761VENDOR_ATMEL_MDB161D:
11615                 tp->nvram_jedecnum = JEDEC_ATMEL;
11616                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11617                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11618                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11619                 tp->nvram_pagesize = 256;
11620                 break;
11621         case FLASH_5761VENDOR_ST_A_M45PE20:
11622         case FLASH_5761VENDOR_ST_A_M45PE40:
11623         case FLASH_5761VENDOR_ST_A_M45PE80:
11624         case FLASH_5761VENDOR_ST_A_M45PE16:
11625         case FLASH_5761VENDOR_ST_M_M45PE20:
11626         case FLASH_5761VENDOR_ST_M_M45PE40:
11627         case FLASH_5761VENDOR_ST_M_M45PE80:
11628         case FLASH_5761VENDOR_ST_M_M45PE16:
11629                 tp->nvram_jedecnum = JEDEC_ST;
11630                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11631                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11632                 tp->nvram_pagesize = 256;
11633                 break;
11634         }
11635
11636         if (protect) {
11637                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11638         } else {
11639                 switch (nvcfg1) {
11640                 case FLASH_5761VENDOR_ATMEL_ADB161D:
11641                 case FLASH_5761VENDOR_ATMEL_MDB161D:
11642                 case FLASH_5761VENDOR_ST_A_M45PE16:
11643                 case FLASH_5761VENDOR_ST_M_M45PE16:
11644                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11645                         break;
11646                 case FLASH_5761VENDOR_ATMEL_ADB081D:
11647                 case FLASH_5761VENDOR_ATMEL_MDB081D:
11648                 case FLASH_5761VENDOR_ST_A_M45PE80:
11649                 case FLASH_5761VENDOR_ST_M_M45PE80:
11650                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11651                         break;
11652                 case FLASH_5761VENDOR_ATMEL_ADB041D:
11653                 case FLASH_5761VENDOR_ATMEL_MDB041D:
11654                 case FLASH_5761VENDOR_ST_A_M45PE40:
11655                 case FLASH_5761VENDOR_ST_M_M45PE40:
11656                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11657                         break;
11658                 case FLASH_5761VENDOR_ATMEL_ADB021D:
11659                 case FLASH_5761VENDOR_ATMEL_MDB021D:
11660                 case FLASH_5761VENDOR_ST_A_M45PE20:
11661                 case FLASH_5761VENDOR_ST_M_M45PE20:
11662                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11663                         break;
11664                 }
11665         }
11666 }
11667
11668 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11669 {
11670         tp->nvram_jedecnum = JEDEC_ATMEL;
11671         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11672         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11673 }
11674
11675 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11676 {
11677         u32 nvcfg1;
11678
11679         nvcfg1 = tr32(NVRAM_CFG1);
11680
11681         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11682         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11683         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11684                 tp->nvram_jedecnum = JEDEC_ATMEL;
11685                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11686                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11687
11688                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11689                 tw32(NVRAM_CFG1, nvcfg1);
11690                 return;
11691         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11692         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11693         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11694         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11695         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11696         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11697         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11698                 tp->nvram_jedecnum = JEDEC_ATMEL;
11699                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11700                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11701
11702                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11703                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11704                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11705                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11706                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11707                         break;
11708                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11709                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11710                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11711                         break;
11712                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11713                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11714                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11715                         break;
11716                 }
11717                 break;
11718         case FLASH_5752VENDOR_ST_M45PE10:
11719         case FLASH_5752VENDOR_ST_M45PE20:
11720         case FLASH_5752VENDOR_ST_M45PE40:
11721                 tp->nvram_jedecnum = JEDEC_ST;
11722                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11723                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11724
11725                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11726                 case FLASH_5752VENDOR_ST_M45PE10:
11727                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11728                         break;
11729                 case FLASH_5752VENDOR_ST_M45PE20:
11730                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11731                         break;
11732                 case FLASH_5752VENDOR_ST_M45PE40:
11733                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11734                         break;
11735                 }
11736                 break;
11737         default:
11738                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11739                 return;
11740         }
11741
11742         tg3_nvram_get_pagesize(tp, nvcfg1);
11743         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11744                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11745 }
11746
11747
11748 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11749 {
11750         u32 nvcfg1;
11751
11752         nvcfg1 = tr32(NVRAM_CFG1);
11753
11754         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11755         case FLASH_5717VENDOR_ATMEL_EEPROM:
11756         case FLASH_5717VENDOR_MICRO_EEPROM:
11757                 tp->nvram_jedecnum = JEDEC_ATMEL;
11758                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11759                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11760
11761                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11762                 tw32(NVRAM_CFG1, nvcfg1);
11763                 return;
11764         case FLASH_5717VENDOR_ATMEL_MDB011D:
11765         case FLASH_5717VENDOR_ATMEL_ADB011B:
11766         case FLASH_5717VENDOR_ATMEL_ADB011D:
11767         case FLASH_5717VENDOR_ATMEL_MDB021D:
11768         case FLASH_5717VENDOR_ATMEL_ADB021B:
11769         case FLASH_5717VENDOR_ATMEL_ADB021D:
11770         case FLASH_5717VENDOR_ATMEL_45USPT:
11771                 tp->nvram_jedecnum = JEDEC_ATMEL;
11772                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11773                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11774
11775                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11776                 case FLASH_5717VENDOR_ATMEL_MDB021D:
11777                 case FLASH_5717VENDOR_ATMEL_ADB021B:
11778                 case FLASH_5717VENDOR_ATMEL_ADB021D:
11779                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11780                         break;
11781                 default:
11782                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11783                         break;
11784                 }
11785                 break;
11786         case FLASH_5717VENDOR_ST_M_M25PE10:
11787         case FLASH_5717VENDOR_ST_A_M25PE10:
11788         case FLASH_5717VENDOR_ST_M_M45PE10:
11789         case FLASH_5717VENDOR_ST_A_M45PE10:
11790         case FLASH_5717VENDOR_ST_M_M25PE20:
11791         case FLASH_5717VENDOR_ST_A_M25PE20:
11792         case FLASH_5717VENDOR_ST_M_M45PE20:
11793         case FLASH_5717VENDOR_ST_A_M45PE20:
11794         case FLASH_5717VENDOR_ST_25USPT:
11795         case FLASH_5717VENDOR_ST_45USPT:
11796                 tp->nvram_jedecnum = JEDEC_ST;
11797                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11798                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11799
11800                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11801                 case FLASH_5717VENDOR_ST_M_M25PE20:
11802                 case FLASH_5717VENDOR_ST_A_M25PE20:
11803                 case FLASH_5717VENDOR_ST_M_M45PE20:
11804                 case FLASH_5717VENDOR_ST_A_M45PE20:
11805                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11806                         break;
11807                 default:
11808                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11809                         break;
11810                 }
11811                 break;
11812         default:
11813                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11814                 return;
11815         }
11816
11817         tg3_nvram_get_pagesize(tp, nvcfg1);
11818         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11819                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11820 }
11821
11822 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11823 static void __devinit tg3_nvram_init(struct tg3 *tp)
11824 {
11825         tw32_f(GRC_EEPROM_ADDR,
11826              (EEPROM_ADDR_FSM_RESET |
11827               (EEPROM_DEFAULT_CLOCK_PERIOD <<
11828                EEPROM_ADDR_CLKPERD_SHIFT)));
11829
11830         msleep(1);
11831
11832         /* Enable seeprom accesses. */
11833         tw32_f(GRC_LOCAL_CTRL,
11834              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11835         udelay(100);
11836
11837         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11838             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11839                 tp->tg3_flags |= TG3_FLAG_NVRAM;
11840
11841                 if (tg3_nvram_lock(tp)) {
11842                         netdev_warn(tp->dev,
11843                                     "Cannot get nvram lock, %s failed\n",
11844                                     __func__);
11845                         return;
11846                 }
11847                 tg3_enable_nvram_access(tp);
11848
11849                 tp->nvram_size = 0;
11850
11851                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11852                         tg3_get_5752_nvram_info(tp);
11853                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11854                         tg3_get_5755_nvram_info(tp);
11855                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11856                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11857                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11858                         tg3_get_5787_nvram_info(tp);
11859                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11860                         tg3_get_5761_nvram_info(tp);
11861                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11862                         tg3_get_5906_nvram_info(tp);
11863                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11864                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11865                         tg3_get_57780_nvram_info(tp);
11866                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
11867                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
11868                         tg3_get_5717_nvram_info(tp);
11869                 else
11870                         tg3_get_nvram_info(tp);
11871
11872                 if (tp->nvram_size == 0)
11873                         tg3_get_nvram_size(tp);
11874
11875                 tg3_disable_nvram_access(tp);
11876                 tg3_nvram_unlock(tp);
11877
11878         } else {
11879                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11880
11881                 tg3_get_eeprom_size(tp);
11882         }
11883 }
11884
11885 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11886                                     u32 offset, u32 len, u8 *buf)
11887 {
11888         int i, j, rc = 0;
11889         u32 val;
11890
11891         for (i = 0; i < len; i += 4) {
11892                 u32 addr;
11893                 __be32 data;
11894
11895                 addr = offset + i;
11896
11897                 memcpy(&data, buf + i, 4);
11898
11899                 /*
11900                  * The SEEPROM interface expects the data to always be opposite
11901                  * the native endian format.  We accomplish this by reversing
11902                  * all the operations that would have been performed on the
11903                  * data from a call to tg3_nvram_read_be32().
11904                  */
11905                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11906
11907                 val = tr32(GRC_EEPROM_ADDR);
11908                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11909
11910                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11911                         EEPROM_ADDR_READ);
11912                 tw32(GRC_EEPROM_ADDR, val |
11913                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
11914                         (addr & EEPROM_ADDR_ADDR_MASK) |
11915                         EEPROM_ADDR_START |
11916                         EEPROM_ADDR_WRITE);
11917
11918                 for (j = 0; j < 1000; j++) {
11919                         val = tr32(GRC_EEPROM_ADDR);
11920
11921                         if (val & EEPROM_ADDR_COMPLETE)
11922                                 break;
11923                         msleep(1);
11924                 }
11925                 if (!(val & EEPROM_ADDR_COMPLETE)) {
11926                         rc = -EBUSY;
11927                         break;
11928                 }
11929         }
11930
11931         return rc;
11932 }
11933
11934 /* offset and length are dword aligned */
11935 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11936                 u8 *buf)
11937 {
11938         int ret = 0;
11939         u32 pagesize = tp->nvram_pagesize;
11940         u32 pagemask = pagesize - 1;
11941         u32 nvram_cmd;
11942         u8 *tmp;
11943
11944         tmp = kmalloc(pagesize, GFP_KERNEL);
11945         if (tmp == NULL)
11946                 return -ENOMEM;
11947
11948         while (len) {
11949                 int j;
11950                 u32 phy_addr, page_off, size;
11951
11952                 phy_addr = offset & ~pagemask;
11953
11954                 for (j = 0; j < pagesize; j += 4) {
11955                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
11956                                                   (__be32 *) (tmp + j));
11957                         if (ret)
11958                                 break;
11959                 }
11960                 if (ret)
11961                         break;
11962
11963                 page_off = offset & pagemask;
11964                 size = pagesize;
11965                 if (len < size)
11966                         size = len;
11967
11968                 len -= size;
11969
11970                 memcpy(tmp + page_off, buf, size);
11971
11972                 offset = offset + (pagesize - page_off);
11973
11974                 tg3_enable_nvram_access(tp);
11975
11976                 /*
11977                  * Before we can erase the flash page, we need
11978                  * to issue a special "write enable" command.
11979                  */
11980                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11981
11982                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11983                         break;
11984
11985                 /* Erase the target page */
11986                 tw32(NVRAM_ADDR, phy_addr);
11987
11988                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11989                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11990
11991                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11992                         break;
11993
11994                 /* Issue another write enable to start the write. */
11995                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11996
11997                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11998                         break;
11999
12000                 for (j = 0; j < pagesize; j += 4) {
12001                         __be32 data;
12002
12003                         data = *((__be32 *) (tmp + j));
12004
12005                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
12006
12007                         tw32(NVRAM_ADDR, phy_addr + j);
12008
12009                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
12010                                 NVRAM_CMD_WR;
12011
12012                         if (j == 0)
12013                                 nvram_cmd |= NVRAM_CMD_FIRST;
12014                         else if (j == (pagesize - 4))
12015                                 nvram_cmd |= NVRAM_CMD_LAST;
12016
12017                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12018                                 break;
12019                 }
12020                 if (ret)
12021                         break;
12022         }
12023
12024         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12025         tg3_nvram_exec_cmd(tp, nvram_cmd);
12026
12027         kfree(tmp);
12028
12029         return ret;
12030 }
12031
12032 /* offset and length are dword aligned */
12033 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
12034                 u8 *buf)
12035 {
12036         int i, ret = 0;
12037
12038         for (i = 0; i < len; i += 4, offset += 4) {
12039                 u32 page_off, phy_addr, nvram_cmd;
12040                 __be32 data;
12041
12042                 memcpy(&data, buf + i, 4);
12043                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
12044
12045                 page_off = offset % tp->nvram_pagesize;
12046
12047                 phy_addr = tg3_nvram_phys_addr(tp, offset);
12048
12049                 tw32(NVRAM_ADDR, phy_addr);
12050
12051                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
12052
12053                 if (page_off == 0 || i == 0)
12054                         nvram_cmd |= NVRAM_CMD_FIRST;
12055                 if (page_off == (tp->nvram_pagesize - 4))
12056                         nvram_cmd |= NVRAM_CMD_LAST;
12057
12058                 if (i == (len - 4))
12059                         nvram_cmd |= NVRAM_CMD_LAST;
12060
12061                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
12062                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
12063                     (tp->nvram_jedecnum == JEDEC_ST) &&
12064                     (nvram_cmd & NVRAM_CMD_FIRST)) {
12065
12066                         if ((ret = tg3_nvram_exec_cmd(tp,
12067                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
12068                                 NVRAM_CMD_DONE)))
12069
12070                                 break;
12071                 }
12072                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12073                         /* We always do complete word writes to eeprom. */
12074                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
12075                 }
12076
12077                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12078                         break;
12079         }
12080         return ret;
12081 }
12082
12083 /* offset and length are dword aligned */
12084 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
12085 {
12086         int ret;
12087
12088         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12089                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
12090                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
12091                 udelay(40);
12092         }
12093
12094         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
12095                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
12096         } else {
12097                 u32 grc_mode;
12098
12099                 ret = tg3_nvram_lock(tp);
12100                 if (ret)
12101                         return ret;
12102
12103                 tg3_enable_nvram_access(tp);
12104                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
12105                     !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
12106                         tw32(NVRAM_WRITE1, 0x406);
12107
12108                 grc_mode = tr32(GRC_MODE);
12109                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
12110
12111                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
12112                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12113
12114                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
12115                                 buf);
12116                 } else {
12117                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12118                                 buf);
12119                 }
12120
12121                 grc_mode = tr32(GRC_MODE);
12122                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
12123
12124                 tg3_disable_nvram_access(tp);
12125                 tg3_nvram_unlock(tp);
12126         }
12127
12128         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12129                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
12130                 udelay(40);
12131         }
12132
12133         return ret;
12134 }
12135
12136 struct subsys_tbl_ent {
12137         u16 subsys_vendor, subsys_devid;
12138         u32 phy_id;
12139 };
12140
12141 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
12142         /* Broadcom boards. */
12143         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12144           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
12145         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12146           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
12147         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12148           TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
12149         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12150           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
12151         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12152           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
12153         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12154           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
12155         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12156           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
12157         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12158           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
12159         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12160           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
12161         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12162           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
12163         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12164           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
12165
12166         /* 3com boards. */
12167         { TG3PCI_SUBVENDOR_ID_3COM,
12168           TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
12169         { TG3PCI_SUBVENDOR_ID_3COM,
12170           TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
12171         { TG3PCI_SUBVENDOR_ID_3COM,
12172           TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
12173         { TG3PCI_SUBVENDOR_ID_3COM,
12174           TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
12175         { TG3PCI_SUBVENDOR_ID_3COM,
12176           TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
12177
12178         /* DELL boards. */
12179         { TG3PCI_SUBVENDOR_ID_DELL,
12180           TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
12181         { TG3PCI_SUBVENDOR_ID_DELL,
12182           TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
12183         { TG3PCI_SUBVENDOR_ID_DELL,
12184           TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
12185         { TG3PCI_SUBVENDOR_ID_DELL,
12186           TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
12187
12188         /* Compaq boards. */
12189         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12190           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
12191         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12192           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
12193         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12194           TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
12195         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12196           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
12197         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12198           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
12199
12200         /* IBM boards. */
12201         { TG3PCI_SUBVENDOR_ID_IBM,
12202           TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
12203 };
12204
12205 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
12206 {
12207         int i;
12208
12209         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12210                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12211                      tp->pdev->subsystem_vendor) &&
12212                     (subsys_id_to_phy_id[i].subsys_devid ==
12213                      tp->pdev->subsystem_device))
12214                         return &subsys_id_to_phy_id[i];
12215         }
12216         return NULL;
12217 }
12218
12219 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12220 {
12221         u32 val;
12222         u16 pmcsr;
12223
12224         /* On some early chips the SRAM cannot be accessed in D3hot state,
12225          * so need make sure we're in D0.
12226          */
12227         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12228         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12229         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12230         msleep(1);
12231
12232         /* Make sure register accesses (indirect or otherwise)
12233          * will function correctly.
12234          */
12235         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12236                                tp->misc_host_ctrl);
12237
12238         /* The memory arbiter has to be enabled in order for SRAM accesses
12239          * to succeed.  Normally on powerup the tg3 chip firmware will make
12240          * sure it is enabled, but other entities such as system netboot
12241          * code might disable it.
12242          */
12243         val = tr32(MEMARB_MODE);
12244         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12245
12246         tp->phy_id = TG3_PHY_ID_INVALID;
12247         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12248
12249         /* Assume an onboard device and WOL capable by default.  */
12250         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12251
12252         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12253                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12254                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12255                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12256                 }
12257                 val = tr32(VCPU_CFGSHDW);
12258                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12259                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12260                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12261                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
12262                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12263                 goto done;
12264         }
12265
12266         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12267         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12268                 u32 nic_cfg, led_cfg;
12269                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12270                 int eeprom_phy_serdes = 0;
12271
12272                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12273                 tp->nic_sram_data_cfg = nic_cfg;
12274
12275                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12276                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12277                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12278                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12279                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12280                     (ver > 0) && (ver < 0x100))
12281                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12282
12283                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12284                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12285
12286                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12287                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12288                         eeprom_phy_serdes = 1;
12289
12290                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12291                 if (nic_phy_id != 0) {
12292                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12293                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12294
12295                         eeprom_phy_id  = (id1 >> 16) << 10;
12296                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
12297                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
12298                 } else
12299                         eeprom_phy_id = 0;
12300
12301                 tp->phy_id = eeprom_phy_id;
12302                 if (eeprom_phy_serdes) {
12303                         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12304                                 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12305                         else
12306                                 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
12307                 }
12308
12309                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12310                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12311                                     SHASTA_EXT_LED_MODE_MASK);
12312                 else
12313                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12314
12315                 switch (led_cfg) {
12316                 default:
12317                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12318                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12319                         break;
12320
12321                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12322                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12323                         break;
12324
12325                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12326                         tp->led_ctrl = LED_CTRL_MODE_MAC;
12327
12328                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12329                          * read on some older 5700/5701 bootcode.
12330                          */
12331                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12332                             ASIC_REV_5700 ||
12333                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
12334                             ASIC_REV_5701)
12335                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12336
12337                         break;
12338
12339                 case SHASTA_EXT_LED_SHARED:
12340                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
12341                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12342                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12343                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12344                                                  LED_CTRL_MODE_PHY_2);
12345                         break;
12346
12347                 case SHASTA_EXT_LED_MAC:
12348                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12349                         break;
12350
12351                 case SHASTA_EXT_LED_COMBO:
12352                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
12353                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12354                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12355                                                  LED_CTRL_MODE_PHY_2);
12356                         break;
12357
12358                 }
12359
12360                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12361                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12362                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12363                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12364
12365                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12366                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12367
12368                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12369                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12370                         if ((tp->pdev->subsystem_vendor ==
12371                              PCI_VENDOR_ID_ARIMA) &&
12372                             (tp->pdev->subsystem_device == 0x205a ||
12373                              tp->pdev->subsystem_device == 0x2063))
12374                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12375                 } else {
12376                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12377                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12378                 }
12379
12380                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12381                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12382                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12383                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12384                 }
12385
12386                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12387                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12388                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12389
12390                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
12391                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12392                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12393
12394                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12395                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12396                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12397
12398                 if (cfg2 & (1 << 17))
12399                         tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
12400
12401                 /* serdes signal pre-emphasis in register 0x590 set by */
12402                 /* bootcode if bit 18 is set */
12403                 if (cfg2 & (1 << 18))
12404                         tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
12405
12406                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12407                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
12408                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12409                         tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
12410
12411                 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12412                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12413                     !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
12414                         u32 cfg3;
12415
12416                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12417                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12418                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12419                 }
12420
12421                 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12422                         tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
12423                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12424                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12425                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12426                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12427         }
12428 done:
12429         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12430         device_set_wakeup_enable(&tp->pdev->dev,
12431                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12432 }
12433
12434 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12435 {
12436         int i;
12437         u32 val;
12438
12439         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12440         tw32(OTP_CTRL, cmd);
12441
12442         /* Wait for up to 1 ms for command to execute. */
12443         for (i = 0; i < 100; i++) {
12444                 val = tr32(OTP_STATUS);
12445                 if (val & OTP_STATUS_CMD_DONE)
12446                         break;
12447                 udelay(10);
12448         }
12449
12450         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12451 }
12452
12453 /* Read the gphy configuration from the OTP region of the chip.  The gphy
12454  * configuration is a 32-bit value that straddles the alignment boundary.
12455  * We do two 32-bit reads and then shift and merge the results.
12456  */
12457 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12458 {
12459         u32 bhalf_otp, thalf_otp;
12460
12461         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12462
12463         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12464                 return 0;
12465
12466         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12467
12468         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12469                 return 0;
12470
12471         thalf_otp = tr32(OTP_READ_DATA);
12472
12473         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12474
12475         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12476                 return 0;
12477
12478         bhalf_otp = tr32(OTP_READ_DATA);
12479
12480         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12481 }
12482
12483 static int __devinit tg3_phy_probe(struct tg3 *tp)
12484 {
12485         u32 hw_phy_id_1, hw_phy_id_2;
12486         u32 hw_phy_id, hw_phy_id_masked;
12487         int err;
12488
12489         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12490                 return tg3_phy_init(tp);
12491
12492         /* Reading the PHY ID register can conflict with ASF
12493          * firmware access to the PHY hardware.
12494          */
12495         err = 0;
12496         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12497             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12498                 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
12499         } else {
12500                 /* Now read the physical PHY_ID from the chip and verify
12501                  * that it is sane.  If it doesn't look good, we fall back
12502                  * to either the hard-coded table based PHY_ID and failing
12503                  * that the value found in the eeprom area.
12504                  */
12505                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12506                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12507
12508                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
12509                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12510                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
12511
12512                 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
12513         }
12514
12515         if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
12516                 tp->phy_id = hw_phy_id;
12517                 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
12518                         tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12519                 else
12520                         tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
12521         } else {
12522                 if (tp->phy_id != TG3_PHY_ID_INVALID) {
12523                         /* Do nothing, phy ID already set up in
12524                          * tg3_get_eeprom_hw_cfg().
12525                          */
12526                 } else {
12527                         struct subsys_tbl_ent *p;
12528
12529                         /* No eeprom signature?  Try the hardcoded
12530                          * subsys device table.
12531                          */
12532                         p = tg3_lookup_by_subsys(tp);
12533                         if (!p)
12534                                 return -ENODEV;
12535
12536                         tp->phy_id = p->phy_id;
12537                         if (!tp->phy_id ||
12538                             tp->phy_id == TG3_PHY_ID_BCM8002)
12539                                 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12540                 }
12541         }
12542
12543         if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12544             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12545              tp->pci_chip_rev_id != CHIPREV_ID_57765_A0))
12546                 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
12547
12548         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
12549             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12550             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12551                 u32 bmsr, adv_reg, tg3_ctrl, mask;
12552
12553                 tg3_readphy(tp, MII_BMSR, &bmsr);
12554                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12555                     (bmsr & BMSR_LSTATUS))
12556                         goto skip_phy_reset;
12557
12558                 err = tg3_phy_reset(tp);
12559                 if (err)
12560                         return err;
12561
12562                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12563                            ADVERTISE_100HALF | ADVERTISE_100FULL |
12564                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12565                 tg3_ctrl = 0;
12566                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
12567                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12568                                     MII_TG3_CTRL_ADV_1000_FULL);
12569                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12570                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12571                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12572                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
12573                 }
12574
12575                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12576                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12577                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12578                 if (!tg3_copper_is_advertising_all(tp, mask)) {
12579                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12580
12581                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12582                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12583
12584                         tg3_writephy(tp, MII_BMCR,
12585                                      BMCR_ANENABLE | BMCR_ANRESTART);
12586                 }
12587                 tg3_phy_set_wirespeed(tp);
12588
12589                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12590                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12591                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12592         }
12593
12594 skip_phy_reset:
12595         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
12596                 err = tg3_init_5401phy_dsp(tp);
12597                 if (err)
12598                         return err;
12599
12600                 err = tg3_init_5401phy_dsp(tp);
12601         }
12602
12603         if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
12604                 tp->link_config.advertising =
12605                         (ADVERTISED_1000baseT_Half |
12606                          ADVERTISED_1000baseT_Full |
12607                          ADVERTISED_Autoneg |
12608                          ADVERTISED_FIBRE);
12609         if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
12610                 tp->link_config.advertising &=
12611                         ~(ADVERTISED_1000baseT_Half |
12612                           ADVERTISED_1000baseT_Full);
12613
12614         return err;
12615 }
12616
12617 static void __devinit tg3_read_vpd(struct tg3 *tp)
12618 {
12619         u8 *vpd_data;
12620         unsigned int block_end, rosize, len;
12621         int j, i = 0;
12622         u32 magic;
12623
12624         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12625             tg3_nvram_read(tp, 0x0, &magic))
12626                 goto out_no_vpd;
12627
12628         vpd_data = kmalloc(TG3_NVM_VPD_LEN, GFP_KERNEL);
12629         if (!vpd_data)
12630                 goto out_no_vpd;
12631
12632         if (magic == TG3_EEPROM_MAGIC) {
12633                 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12634                         u32 tmp;
12635
12636                         /* The data is in little-endian format in NVRAM.
12637                          * Use the big-endian read routines to preserve
12638                          * the byte order as it exists in NVRAM.
12639                          */
12640                         if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12641                                 goto out_not_found;
12642
12643                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12644                 }
12645         } else {
12646                 ssize_t cnt;
12647                 unsigned int pos = 0;
12648
12649                 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12650                         cnt = pci_read_vpd(tp->pdev, pos,
12651                                            TG3_NVM_VPD_LEN - pos,
12652                                            &vpd_data[pos]);
12653                         if (cnt == -ETIMEDOUT || -EINTR)
12654                                 cnt = 0;
12655                         else if (cnt < 0)
12656                                 goto out_not_found;
12657                 }
12658                 if (pos != TG3_NVM_VPD_LEN)
12659                         goto out_not_found;
12660         }
12661
12662         i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
12663                              PCI_VPD_LRDT_RO_DATA);
12664         if (i < 0)
12665                 goto out_not_found;
12666
12667         rosize = pci_vpd_lrdt_size(&vpd_data[i]);
12668         block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
12669         i += PCI_VPD_LRDT_TAG_SIZE;
12670
12671         if (block_end > TG3_NVM_VPD_LEN)
12672                 goto out_not_found;
12673
12674         j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12675                                       PCI_VPD_RO_KEYWORD_MFR_ID);
12676         if (j > 0) {
12677                 len = pci_vpd_info_field_size(&vpd_data[j]);
12678
12679                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12680                 if (j + len > block_end || len != 4 ||
12681                     memcmp(&vpd_data[j], "1028", 4))
12682                         goto partno;
12683
12684                 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12685                                               PCI_VPD_RO_KEYWORD_VENDOR0);
12686                 if (j < 0)
12687                         goto partno;
12688
12689                 len = pci_vpd_info_field_size(&vpd_data[j]);
12690
12691                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12692                 if (j + len > block_end)
12693                         goto partno;
12694
12695                 memcpy(tp->fw_ver, &vpd_data[j], len);
12696                 strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
12697         }
12698
12699 partno:
12700         i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12701                                       PCI_VPD_RO_KEYWORD_PARTNO);
12702         if (i < 0)
12703                 goto out_not_found;
12704
12705         len = pci_vpd_info_field_size(&vpd_data[i]);
12706
12707         i += PCI_VPD_INFO_FLD_HDR_SIZE;
12708         if (len > TG3_BPN_SIZE ||
12709             (len + i) > TG3_NVM_VPD_LEN)
12710                 goto out_not_found;
12711
12712         memcpy(tp->board_part_number, &vpd_data[i], len);
12713
12714 out_not_found:
12715         kfree(vpd_data);
12716         if (tp->board_part_number[0])
12717                 return;
12718
12719 out_no_vpd:
12720         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
12721                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717)
12722                         strcpy(tp->board_part_number, "BCM5717");
12723                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
12724                         strcpy(tp->board_part_number, "BCM5718");
12725                 else
12726                         goto nomatch;
12727         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
12728                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12729                         strcpy(tp->board_part_number, "BCM57780");
12730                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12731                         strcpy(tp->board_part_number, "BCM57760");
12732                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12733                         strcpy(tp->board_part_number, "BCM57790");
12734                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12735                         strcpy(tp->board_part_number, "BCM57788");
12736                 else
12737                         goto nomatch;
12738         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
12739                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
12740                         strcpy(tp->board_part_number, "BCM57761");
12741                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
12742                         strcpy(tp->board_part_number, "BCM57765");
12743                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
12744                         strcpy(tp->board_part_number, "BCM57781");
12745                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
12746                         strcpy(tp->board_part_number, "BCM57785");
12747                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
12748                         strcpy(tp->board_part_number, "BCM57791");
12749                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12750                         strcpy(tp->board_part_number, "BCM57795");
12751                 else
12752                         goto nomatch;
12753         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12754                 strcpy(tp->board_part_number, "BCM95906");
12755         } else {
12756 nomatch:
12757                 strcpy(tp->board_part_number, "none");
12758         }
12759 }
12760
12761 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12762 {
12763         u32 val;
12764
12765         if (tg3_nvram_read(tp, offset, &val) ||
12766             (val & 0xfc000000) != 0x0c000000 ||
12767             tg3_nvram_read(tp, offset + 4, &val) ||
12768             val != 0)
12769                 return 0;
12770
12771         return 1;
12772 }
12773
12774 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12775 {
12776         u32 val, offset, start, ver_offset;
12777         int i, dst_off;
12778         bool newver = false;
12779
12780         if (tg3_nvram_read(tp, 0xc, &offset) ||
12781             tg3_nvram_read(tp, 0x4, &start))
12782                 return;
12783
12784         offset = tg3_nvram_logical_addr(tp, offset);
12785
12786         if (tg3_nvram_read(tp, offset, &val))
12787                 return;
12788
12789         if ((val & 0xfc000000) == 0x0c000000) {
12790                 if (tg3_nvram_read(tp, offset + 4, &val))
12791                         return;
12792
12793                 if (val == 0)
12794                         newver = true;
12795         }
12796
12797         dst_off = strlen(tp->fw_ver);
12798
12799         if (newver) {
12800                 if (TG3_VER_SIZE - dst_off < 16 ||
12801                     tg3_nvram_read(tp, offset + 8, &ver_offset))
12802                         return;
12803
12804                 offset = offset + ver_offset - start;
12805                 for (i = 0; i < 16; i += 4) {
12806                         __be32 v;
12807                         if (tg3_nvram_read_be32(tp, offset + i, &v))
12808                                 return;
12809
12810                         memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
12811                 }
12812         } else {
12813                 u32 major, minor;
12814
12815                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12816                         return;
12817
12818                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12819                         TG3_NVM_BCVER_MAJSFT;
12820                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12821                 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
12822                          "v%d.%02d", major, minor);
12823         }
12824 }
12825
12826 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12827 {
12828         u32 val, major, minor;
12829
12830         /* Use native endian representation */
12831         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12832                 return;
12833
12834         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12835                 TG3_NVM_HWSB_CFG1_MAJSFT;
12836         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12837                 TG3_NVM_HWSB_CFG1_MINSFT;
12838
12839         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12840 }
12841
12842 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12843 {
12844         u32 offset, major, minor, build;
12845
12846         strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
12847
12848         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12849                 return;
12850
12851         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12852         case TG3_EEPROM_SB_REVISION_0:
12853                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12854                 break;
12855         case TG3_EEPROM_SB_REVISION_2:
12856                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12857                 break;
12858         case TG3_EEPROM_SB_REVISION_3:
12859                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12860                 break;
12861         case TG3_EEPROM_SB_REVISION_4:
12862                 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
12863                 break;
12864         case TG3_EEPROM_SB_REVISION_5:
12865                 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
12866                 break;
12867         case TG3_EEPROM_SB_REVISION_6:
12868                 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
12869                 break;
12870         default:
12871                 return;
12872         }
12873
12874         if (tg3_nvram_read(tp, offset, &val))
12875                 return;
12876
12877         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12878                 TG3_EEPROM_SB_EDH_BLD_SHFT;
12879         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12880                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12881         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
12882
12883         if (minor > 99 || build > 26)
12884                 return;
12885
12886         offset = strlen(tp->fw_ver);
12887         snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
12888                  " v%d.%02d", major, minor);
12889
12890         if (build > 0) {
12891                 offset = strlen(tp->fw_ver);
12892                 if (offset < TG3_VER_SIZE - 1)
12893                         tp->fw_ver[offset] = 'a' + build - 1;
12894         }
12895 }
12896
12897 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12898 {
12899         u32 val, offset, start;
12900         int i, vlen;
12901
12902         for (offset = TG3_NVM_DIR_START;
12903              offset < TG3_NVM_DIR_END;
12904              offset += TG3_NVM_DIRENT_SIZE) {
12905                 if (tg3_nvram_read(tp, offset, &val))
12906                         return;
12907
12908                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12909                         break;
12910         }
12911
12912         if (offset == TG3_NVM_DIR_END)
12913                 return;
12914
12915         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12916                 start = 0x08000000;
12917         else if (tg3_nvram_read(tp, offset - 4, &start))
12918                 return;
12919
12920         if (tg3_nvram_read(tp, offset + 4, &offset) ||
12921             !tg3_fw_img_is_valid(tp, offset) ||
12922             tg3_nvram_read(tp, offset + 8, &val))
12923                 return;
12924
12925         offset += val - start;
12926
12927         vlen = strlen(tp->fw_ver);
12928
12929         tp->fw_ver[vlen++] = ',';
12930         tp->fw_ver[vlen++] = ' ';
12931
12932         for (i = 0; i < 4; i++) {
12933                 __be32 v;
12934                 if (tg3_nvram_read_be32(tp, offset, &v))
12935                         return;
12936
12937                 offset += sizeof(v);
12938
12939                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12940                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12941                         break;
12942                 }
12943
12944                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12945                 vlen += sizeof(v);
12946         }
12947 }
12948
12949 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12950 {
12951         int vlen;
12952         u32 apedata;
12953         char *fwtype;
12954
12955         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12956             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
12957                 return;
12958
12959         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12960         if (apedata != APE_SEG_SIG_MAGIC)
12961                 return;
12962
12963         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12964         if (!(apedata & APE_FW_STATUS_READY))
12965                 return;
12966
12967         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12968
12969         if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) {
12970                 tp->tg3_flags3 |= TG3_FLG3_APE_HAS_NCSI;
12971                 fwtype = "NCSI";
12972         } else {
12973                 fwtype = "DASH";
12974         }
12975
12976         vlen = strlen(tp->fw_ver);
12977
12978         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
12979                  fwtype,
12980                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12981                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12982                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12983                  (apedata & APE_FW_VERSION_BLDMSK));
12984 }
12985
12986 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12987 {
12988         u32 val;
12989         bool vpd_vers = false;
12990
12991         if (tp->fw_ver[0] != 0)
12992                 vpd_vers = true;
12993
12994         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12995                 strcat(tp->fw_ver, "sb");
12996                 return;
12997         }
12998
12999         if (tg3_nvram_read(tp, 0, &val))
13000                 return;
13001
13002         if (val == TG3_EEPROM_MAGIC)
13003                 tg3_read_bc_ver(tp);
13004         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
13005                 tg3_read_sb_ver(tp, val);
13006         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
13007                 tg3_read_hwsb_ver(tp);
13008         else
13009                 return;
13010
13011         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
13012              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
13013                 goto done;
13014
13015         tg3_read_mgmtfw_ver(tp);
13016
13017 done:
13018         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
13019 }
13020
13021 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
13022
13023 static void inline vlan_features_add(struct net_device *dev, unsigned long flags)
13024 {
13025 #if TG3_VLAN_TAG_USED
13026         dev->vlan_features |= flags;
13027 #endif
13028 }
13029
13030 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
13031 {
13032         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13033             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
13034                 return 4096;
13035         else if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
13036                  !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13037                 return 1024;
13038         else
13039                 return 512;
13040 }
13041
13042 static int __devinit tg3_get_invariants(struct tg3 *tp)
13043 {
13044         static struct pci_device_id write_reorder_chipsets[] = {
13045                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
13046                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
13047                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
13048                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
13049                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
13050                              PCI_DEVICE_ID_VIA_8385_0) },
13051                 { },
13052         };
13053         u32 misc_ctrl_reg;
13054         u32 pci_state_reg, grc_misc_cfg;
13055         u32 val;
13056         u16 pci_cmd;
13057         int err;
13058
13059         /* Force memory write invalidate off.  If we leave it on,
13060          * then on 5700_BX chips we have to enable a workaround.
13061          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
13062          * to match the cacheline size.  The Broadcom driver have this
13063          * workaround but turns MWI off all the times so never uses
13064          * it.  This seems to suggest that the workaround is insufficient.
13065          */
13066         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13067         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
13068         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13069
13070         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
13071          * has the register indirect write enable bit set before
13072          * we try to access any of the MMIO registers.  It is also
13073          * critical that the PCI-X hw workaround situation is decided
13074          * before that as well.
13075          */
13076         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13077                               &misc_ctrl_reg);
13078
13079         tp->pci_chip_rev_id = (misc_ctrl_reg >>
13080                                MISC_HOST_CTRL_CHIPREV_SHIFT);
13081         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
13082                 u32 prod_id_asic_rev;
13083
13084                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
13085                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
13086                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719)
13087                         pci_read_config_dword(tp->pdev,
13088                                               TG3PCI_GEN2_PRODID_ASICREV,
13089                                               &prod_id_asic_rev);
13090                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
13091                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
13092                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
13093                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
13094                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13095                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
13096                         pci_read_config_dword(tp->pdev,
13097                                               TG3PCI_GEN15_PRODID_ASICREV,
13098                                               &prod_id_asic_rev);
13099                 else
13100                         pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
13101                                               &prod_id_asic_rev);
13102
13103                 tp->pci_chip_rev_id = prod_id_asic_rev;
13104         }
13105
13106         /* Wrong chip ID in 5752 A0. This code can be removed later
13107          * as A0 is not in production.
13108          */
13109         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
13110                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
13111
13112         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
13113          * we need to disable memory and use config. cycles
13114          * only to access all registers. The 5702/03 chips
13115          * can mistakenly decode the special cycles from the
13116          * ICH chipsets as memory write cycles, causing corruption
13117          * of register and memory space. Only certain ICH bridges
13118          * will drive special cycles with non-zero data during the
13119          * address phase which can fall within the 5703's address
13120          * range. This is not an ICH bug as the PCI spec allows
13121          * non-zero address during special cycles. However, only
13122          * these ICH bridges are known to drive non-zero addresses
13123          * during special cycles.
13124          *
13125          * Since special cycles do not cross PCI bridges, we only
13126          * enable this workaround if the 5703 is on the secondary
13127          * bus of these ICH bridges.
13128          */
13129         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
13130             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
13131                 static struct tg3_dev_id {
13132                         u32     vendor;
13133                         u32     device;
13134                         u32     rev;
13135                 } ich_chipsets[] = {
13136                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
13137                           PCI_ANY_ID },
13138                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
13139                           PCI_ANY_ID },
13140                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
13141                           0xa },
13142                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
13143                           PCI_ANY_ID },
13144                         { },
13145                 };
13146                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
13147                 struct pci_dev *bridge = NULL;
13148
13149                 while (pci_id->vendor != 0) {
13150                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
13151                                                 bridge);
13152                         if (!bridge) {
13153                                 pci_id++;
13154                                 continue;
13155                         }
13156                         if (pci_id->rev != PCI_ANY_ID) {
13157                                 if (bridge->revision > pci_id->rev)
13158                                         continue;
13159                         }
13160                         if (bridge->subordinate &&
13161                             (bridge->subordinate->number ==
13162                              tp->pdev->bus->number)) {
13163
13164                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
13165                                 pci_dev_put(bridge);
13166                                 break;
13167                         }
13168                 }
13169         }
13170
13171         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
13172                 static struct tg3_dev_id {
13173                         u32     vendor;
13174                         u32     device;
13175                 } bridge_chipsets[] = {
13176                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
13177                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
13178                         { },
13179                 };
13180                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
13181                 struct pci_dev *bridge = NULL;
13182
13183                 while (pci_id->vendor != 0) {
13184                         bridge = pci_get_device(pci_id->vendor,
13185                                                 pci_id->device,
13186                                                 bridge);
13187                         if (!bridge) {
13188                                 pci_id++;
13189                                 continue;
13190                         }
13191                         if (bridge->subordinate &&
13192                             (bridge->subordinate->number <=
13193                              tp->pdev->bus->number) &&
13194                             (bridge->subordinate->subordinate >=
13195                              tp->pdev->bus->number)) {
13196                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
13197                                 pci_dev_put(bridge);
13198                                 break;
13199                         }
13200                 }
13201         }
13202
13203         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
13204          * DMA addresses > 40-bit. This bridge may have other additional
13205          * 57xx devices behind it in some 4-port NIC designs for example.
13206          * Any tg3 device found behind the bridge will also need the 40-bit
13207          * DMA workaround.
13208          */
13209         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
13210             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13211                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
13212                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13213                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
13214         } else {
13215                 struct pci_dev *bridge = NULL;
13216
13217                 do {
13218                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
13219                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
13220                                                 bridge);
13221                         if (bridge && bridge->subordinate &&
13222                             (bridge->subordinate->number <=
13223                              tp->pdev->bus->number) &&
13224                             (bridge->subordinate->subordinate >=
13225                              tp->pdev->bus->number)) {
13226                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13227                                 pci_dev_put(bridge);
13228                                 break;
13229                         }
13230                 } while (bridge);
13231         }
13232
13233         /* Initialize misc host control in PCI block. */
13234         tp->misc_host_ctrl |= (misc_ctrl_reg &
13235                                MISC_HOST_CTRL_CHIPREV);
13236         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13237                                tp->misc_host_ctrl);
13238
13239         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13240             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13241             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13242                 tp->pdev_peer = tg3_find_peer(tp);
13243
13244         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13245             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13246             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13247                 tp->tg3_flags3 |= TG3_FLG3_5717_PLUS;
13248
13249         /* Intentionally exclude ASIC_REV_5906 */
13250         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13251             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13252             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13253             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13254             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13255             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13256             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13257                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13258
13259         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13260             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13261             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13262             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13263             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13264                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13265
13266         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13267             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13268                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13269
13270         /* 5700 B0 chips do not support checksumming correctly due
13271          * to hardware bugs.
13272          */
13273         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13274                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13275         else {
13276                 unsigned long features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_GRO;
13277
13278                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13279                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13280                         features |= NETIF_F_IPV6_CSUM;
13281                 tp->dev->features |= features;
13282                 vlan_features_add(tp->dev, features);
13283         }
13284
13285         /* Determine TSO capabilities */
13286         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13287                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13288         else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13289                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13290                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13291         else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13292                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13293                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13294                     tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13295                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13296         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13297                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13298                    tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13299                 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13300                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13301                         tp->fw_needed = FIRMWARE_TG3TSO5;
13302                 else
13303                         tp->fw_needed = FIRMWARE_TG3TSO;
13304         }
13305
13306         tp->irq_max = 1;
13307
13308         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13309                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13310                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13311                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13312                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13313                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13314                      tp->pdev_peer == tp->pdev))
13315                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13316
13317                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13318                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13319                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13320                 }
13321
13322                 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
13323                         tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13324                         tp->irq_max = TG3_IRQ_MAX_VECS;
13325                 }
13326         }
13327
13328         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13329             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13330             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13331                 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13332         else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13333                 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13334                 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13335         }
13336
13337         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13338                 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13339
13340         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13341             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13342             (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13343                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13344
13345         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13346                               &pci_state_reg);
13347
13348         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13349         if (tp->pcie_cap != 0) {
13350                 u16 lnkctl;
13351
13352                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13353
13354                 pcie_set_readrq(tp->pdev, 4096);
13355
13356                 pci_read_config_word(tp->pdev,
13357                                      tp->pcie_cap + PCI_EXP_LNKCTL,
13358                                      &lnkctl);
13359                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13360                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13361                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13362                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13363                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13364                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13365                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13366                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13367                 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13368                         tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13369                 }
13370         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13371                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13372         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13373                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13374                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13375                 if (!tp->pcix_cap) {
13376                         dev_err(&tp->pdev->dev,
13377                                 "Cannot find PCI-X capability, aborting\n");
13378                         return -EIO;
13379                 }
13380
13381                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13382                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13383         }
13384
13385         /* If we have an AMD 762 or VIA K8T800 chipset, write
13386          * reordering to the mailbox registers done by the host
13387          * controller can cause major troubles.  We read back from
13388          * every mailbox register write to force the writes to be
13389          * posted to the chip in order.
13390          */
13391         if (pci_dev_present(write_reorder_chipsets) &&
13392             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13393                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13394
13395         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13396                              &tp->pci_cacheline_sz);
13397         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13398                              &tp->pci_lat_timer);
13399         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13400             tp->pci_lat_timer < 64) {
13401                 tp->pci_lat_timer = 64;
13402                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13403                                       tp->pci_lat_timer);
13404         }
13405
13406         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13407                 /* 5700 BX chips need to have their TX producer index
13408                  * mailboxes written twice to workaround a bug.
13409                  */
13410                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13411
13412                 /* If we are in PCI-X mode, enable register write workaround.
13413                  *
13414                  * The workaround is to use indirect register accesses
13415                  * for all chip writes not to mailbox registers.
13416                  */
13417                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13418                         u32 pm_reg;
13419
13420                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13421
13422                         /* The chip can have it's power management PCI config
13423                          * space registers clobbered due to this bug.
13424                          * So explicitly force the chip into D0 here.
13425                          */
13426                         pci_read_config_dword(tp->pdev,
13427                                               tp->pm_cap + PCI_PM_CTRL,
13428                                               &pm_reg);
13429                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13430                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13431                         pci_write_config_dword(tp->pdev,
13432                                                tp->pm_cap + PCI_PM_CTRL,
13433                                                pm_reg);
13434
13435                         /* Also, force SERR#/PERR# in PCI command. */
13436                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13437                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13438                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13439                 }
13440         }
13441
13442         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13443                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13444         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13445                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13446
13447         /* Chip-specific fixup from Broadcom driver */
13448         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13449             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13450                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13451                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13452         }
13453
13454         /* Default fast path register access methods */
13455         tp->read32 = tg3_read32;
13456         tp->write32 = tg3_write32;
13457         tp->read32_mbox = tg3_read32;
13458         tp->write32_mbox = tg3_write32;
13459         tp->write32_tx_mbox = tg3_write32;
13460         tp->write32_rx_mbox = tg3_write32;
13461
13462         /* Various workaround register access methods */
13463         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13464                 tp->write32 = tg3_write_indirect_reg32;
13465         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13466                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13467                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13468                 /*
13469                  * Back to back register writes can cause problems on these
13470                  * chips, the workaround is to read back all reg writes
13471                  * except those to mailbox regs.
13472                  *
13473                  * See tg3_write_indirect_reg32().
13474                  */
13475                 tp->write32 = tg3_write_flush_reg32;
13476         }
13477
13478         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13479             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13480                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13481                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13482                         tp->write32_rx_mbox = tg3_write_flush_reg32;
13483         }
13484
13485         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13486                 tp->read32 = tg3_read_indirect_reg32;
13487                 tp->write32 = tg3_write_indirect_reg32;
13488                 tp->read32_mbox = tg3_read_indirect_mbox;
13489                 tp->write32_mbox = tg3_write_indirect_mbox;
13490                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13491                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13492
13493                 iounmap(tp->regs);
13494                 tp->regs = NULL;
13495
13496                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13497                 pci_cmd &= ~PCI_COMMAND_MEMORY;
13498                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13499         }
13500         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13501                 tp->read32_mbox = tg3_read32_mbox_5906;
13502                 tp->write32_mbox = tg3_write32_mbox_5906;
13503                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13504                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13505         }
13506
13507         if (tp->write32 == tg3_write_indirect_reg32 ||
13508             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13509              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13510               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13511                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13512
13513         /* Get eeprom hw config before calling tg3_set_power_state().
13514          * In particular, the TG3_FLG2_IS_NIC flag must be
13515          * determined before calling tg3_set_power_state() so that
13516          * we know whether or not to switch out of Vaux power.
13517          * When the flag is set, it means that GPIO1 is used for eeprom
13518          * write protect and also implies that it is a LOM where GPIOs
13519          * are not used to switch power.
13520          */
13521         tg3_get_eeprom_hw_cfg(tp);
13522
13523         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13524                 /* Allow reads and writes to the
13525                  * APE register and memory space.
13526                  */
13527                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13528                                  PCISTATE_ALLOW_APE_SHMEM_WR |
13529                                  PCISTATE_ALLOW_APE_PSPACE_WR;
13530                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13531                                        pci_state_reg);
13532         }
13533
13534         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13535             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13536             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13537             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13538             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13539                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13540
13541         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13542          * GPIO1 driven high will bring 5700's external PHY out of reset.
13543          * It is also used as eeprom write protect on LOMs.
13544          */
13545         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13546         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13547             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13548                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13549                                        GRC_LCLCTRL_GPIO_OUTPUT1);
13550         /* Unused GPIO3 must be driven as output on 5752 because there
13551          * are no pull-up resistors on unused GPIO pins.
13552          */
13553         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13554                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13555
13556         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13557             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13558             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13559                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13560
13561         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13562             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13563                 /* Turn off the debug UART. */
13564                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13565                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13566                         /* Keep VMain power. */
13567                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13568                                               GRC_LCLCTRL_GPIO_OUTPUT0;
13569         }
13570
13571         /* Force the chip into D0. */
13572         err = tg3_set_power_state(tp, PCI_D0);
13573         if (err) {
13574                 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
13575                 return err;
13576         }
13577
13578         /* Derive initial jumbo mode from MTU assigned in
13579          * ether_setup() via the alloc_etherdev() call
13580          */
13581         if (tp->dev->mtu > ETH_DATA_LEN &&
13582             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13583                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13584
13585         /* Determine WakeOnLan speed to use. */
13586         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13587             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13588             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13589             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13590                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13591         } else {
13592                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13593         }
13594
13595         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13596                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
13597
13598         /* A few boards don't want Ethernet@WireSpeed phy feature */
13599         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13600             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13601              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13602              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13603             (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
13604             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
13605                 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
13606
13607         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13608             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13609                 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
13610         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13611                 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
13612
13613         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13614             !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
13615             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13616             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13617             !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
13618                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13619                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13620                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13621                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13622                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13623                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13624                                 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
13625                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13626                                 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
13627                 } else
13628                         tp->phy_flags |= TG3_PHYFLG_BER_BUG;
13629         }
13630
13631         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13632             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13633                 tp->phy_otp = tg3_read_otp_phycfg(tp);
13634                 if (tp->phy_otp == 0)
13635                         tp->phy_otp = TG3_OTP_DEFAULT;
13636         }
13637
13638         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13639                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13640         else
13641                 tp->mi_mode = MAC_MI_MODE_BASE;
13642
13643         tp->coalesce_mode = 0;
13644         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13645             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13646                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13647
13648         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13649             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13650                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13651
13652         err = tg3_mdio_init(tp);
13653         if (err)
13654                 return err;
13655
13656         /* Initialize data/descriptor byte/word swapping. */
13657         val = tr32(GRC_MODE);
13658         val &= GRC_MODE_HOST_STACKUP;
13659         tw32(GRC_MODE, val | tp->grc_mode);
13660
13661         tg3_switch_clocks(tp);
13662
13663         /* Clear this out for sanity. */
13664         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13665
13666         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13667                               &pci_state_reg);
13668         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13669             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13670                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13671
13672                 if (chiprevid == CHIPREV_ID_5701_A0 ||
13673                     chiprevid == CHIPREV_ID_5701_B0 ||
13674                     chiprevid == CHIPREV_ID_5701_B2 ||
13675                     chiprevid == CHIPREV_ID_5701_B5) {
13676                         void __iomem *sram_base;
13677
13678                         /* Write some dummy words into the SRAM status block
13679                          * area, see if it reads back correctly.  If the return
13680                          * value is bad, force enable the PCIX workaround.
13681                          */
13682                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13683
13684                         writel(0x00000000, sram_base);
13685                         writel(0x00000000, sram_base + 4);
13686                         writel(0xffffffff, sram_base + 4);
13687                         if (readl(sram_base) != 0x00000000)
13688                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13689                 }
13690         }
13691
13692         udelay(50);
13693         tg3_nvram_init(tp);
13694
13695         grc_misc_cfg = tr32(GRC_MISC_CFG);
13696         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13697
13698         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13699             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13700              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13701                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13702
13703         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13704             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13705                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13706         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13707                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13708                                       HOSTCC_MODE_CLRTICK_TXBD);
13709
13710                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13711                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13712                                        tp->misc_host_ctrl);
13713         }
13714
13715         /* Preserve the APE MAC_MODE bits */
13716         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13717                 tp->mac_mode = tr32(MAC_MODE) |
13718                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13719         else
13720                 tp->mac_mode = TG3_DEF_MAC_MODE;
13721
13722         /* these are limited to 10/100 only */
13723         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13724              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13725             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13726              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13727              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13728               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13729               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13730             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13731              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13732               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13733               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13734             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13735             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13736             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
13737             (tp->phy_flags & TG3_PHYFLG_IS_FET))
13738                 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
13739
13740         err = tg3_phy_probe(tp);
13741         if (err) {
13742                 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
13743                 /* ... but do not return immediately ... */
13744                 tg3_mdio_fini(tp);
13745         }
13746
13747         tg3_read_vpd(tp);
13748         tg3_read_fw_ver(tp);
13749
13750         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
13751                 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
13752         } else {
13753                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13754                         tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
13755                 else
13756                         tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
13757         }
13758
13759         /* 5700 {AX,BX} chips have a broken status block link
13760          * change bit implementation, so we must use the
13761          * status register in those cases.
13762          */
13763         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13764                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13765         else
13766                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13767
13768         /* The led_ctrl is set during tg3_phy_probe, here we might
13769          * have to force the link status polling mechanism based
13770          * upon subsystem IDs.
13771          */
13772         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13773             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13774             !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
13775                 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
13776                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13777         }
13778
13779         /* For all SERDES we poll the MAC status register. */
13780         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
13781                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13782         else
13783                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13784
13785         tp->rx_offset = NET_IP_ALIGN + TG3_RX_HEADROOM;
13786         tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
13787         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13788             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
13789                 tp->rx_offset -= NET_IP_ALIGN;
13790 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
13791                 tp->rx_copy_thresh = ~(u16)0;
13792 #endif
13793         }
13794
13795         tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
13796         tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
13797         tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
13798
13799         tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
13800
13801         /* Increment the rx prod index on the rx std ring by at most
13802          * 8 for these chips to workaround hw errata.
13803          */
13804         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13805             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13806             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13807                 tp->rx_std_max_post = 8;
13808
13809         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13810                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13811                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
13812
13813         return err;
13814 }
13815
13816 #ifdef CONFIG_SPARC
13817 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13818 {
13819         struct net_device *dev = tp->dev;
13820         struct pci_dev *pdev = tp->pdev;
13821         struct device_node *dp = pci_device_to_OF_node(pdev);
13822         const unsigned char *addr;
13823         int len;
13824
13825         addr = of_get_property(dp, "local-mac-address", &len);
13826         if (addr && len == 6) {
13827                 memcpy(dev->dev_addr, addr, 6);
13828                 memcpy(dev->perm_addr, dev->dev_addr, 6);
13829                 return 0;
13830         }
13831         return -ENODEV;
13832 }
13833
13834 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13835 {
13836         struct net_device *dev = tp->dev;
13837
13838         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13839         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13840         return 0;
13841 }
13842 #endif
13843
13844 static int __devinit tg3_get_device_address(struct tg3 *tp)
13845 {
13846         struct net_device *dev = tp->dev;
13847         u32 hi, lo, mac_offset;
13848         int addr_ok = 0;
13849
13850 #ifdef CONFIG_SPARC
13851         if (!tg3_get_macaddr_sparc(tp))
13852                 return 0;
13853 #endif
13854
13855         mac_offset = 0x7c;
13856         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13857             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13858                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13859                         mac_offset = 0xcc;
13860                 if (tg3_nvram_lock(tp))
13861                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13862                 else
13863                         tg3_nvram_unlock(tp);
13864         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13865                    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
13866                 if (PCI_FUNC(tp->pdev->devfn) & 1)
13867                         mac_offset = 0xcc;
13868                 if (PCI_FUNC(tp->pdev->devfn) > 1)
13869                         mac_offset += 0x18c;
13870         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13871                 mac_offset = 0x10;
13872
13873         /* First try to get it from MAC address mailbox. */
13874         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13875         if ((hi >> 16) == 0x484b) {
13876                 dev->dev_addr[0] = (hi >>  8) & 0xff;
13877                 dev->dev_addr[1] = (hi >>  0) & 0xff;
13878
13879                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13880                 dev->dev_addr[2] = (lo >> 24) & 0xff;
13881                 dev->dev_addr[3] = (lo >> 16) & 0xff;
13882                 dev->dev_addr[4] = (lo >>  8) & 0xff;
13883                 dev->dev_addr[5] = (lo >>  0) & 0xff;
13884
13885                 /* Some old bootcode may report a 0 MAC address in SRAM */
13886                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13887         }
13888         if (!addr_ok) {
13889                 /* Next, try NVRAM. */
13890                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13891                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13892                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13893                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13894                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13895                 }
13896                 /* Finally just fetch it out of the MAC control regs. */
13897                 else {
13898                         hi = tr32(MAC_ADDR_0_HIGH);
13899                         lo = tr32(MAC_ADDR_0_LOW);
13900
13901                         dev->dev_addr[5] = lo & 0xff;
13902                         dev->dev_addr[4] = (lo >> 8) & 0xff;
13903                         dev->dev_addr[3] = (lo >> 16) & 0xff;
13904                         dev->dev_addr[2] = (lo >> 24) & 0xff;
13905                         dev->dev_addr[1] = hi & 0xff;
13906                         dev->dev_addr[0] = (hi >> 8) & 0xff;
13907                 }
13908         }
13909
13910         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13911 #ifdef CONFIG_SPARC
13912                 if (!tg3_get_default_macaddr_sparc(tp))
13913                         return 0;
13914 #endif
13915                 return -EINVAL;
13916         }
13917         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13918         return 0;
13919 }
13920
13921 #define BOUNDARY_SINGLE_CACHELINE       1
13922 #define BOUNDARY_MULTI_CACHELINE        2
13923
13924 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13925 {
13926         int cacheline_size;
13927         u8 byte;
13928         int goal;
13929
13930         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13931         if (byte == 0)
13932                 cacheline_size = 1024;
13933         else
13934                 cacheline_size = (int) byte * 4;
13935
13936         /* On 5703 and later chips, the boundary bits have no
13937          * effect.
13938          */
13939         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13940             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13941             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13942                 goto out;
13943
13944 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13945         goal = BOUNDARY_MULTI_CACHELINE;
13946 #else
13947 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13948         goal = BOUNDARY_SINGLE_CACHELINE;
13949 #else
13950         goal = 0;
13951 #endif
13952 #endif
13953
13954         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
13955                 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13956                 goto out;
13957         }
13958
13959         if (!goal)
13960                 goto out;
13961
13962         /* PCI controllers on most RISC systems tend to disconnect
13963          * when a device tries to burst across a cache-line boundary.
13964          * Therefore, letting tg3 do so just wastes PCI bandwidth.
13965          *
13966          * Unfortunately, for PCI-E there are only limited
13967          * write-side controls for this, and thus for reads
13968          * we will still get the disconnects.  We'll also waste
13969          * these PCI cycles for both read and write for chips
13970          * other than 5700 and 5701 which do not implement the
13971          * boundary bits.
13972          */
13973         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13974             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13975                 switch (cacheline_size) {
13976                 case 16:
13977                 case 32:
13978                 case 64:
13979                 case 128:
13980                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13981                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13982                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13983                         } else {
13984                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13985                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13986                         }
13987                         break;
13988
13989                 case 256:
13990                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13991                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13992                         break;
13993
13994                 default:
13995                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13996                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13997                         break;
13998                 }
13999         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14000                 switch (cacheline_size) {
14001                 case 16:
14002                 case 32:
14003                 case 64:
14004                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14005                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14006                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
14007                                 break;
14008                         }
14009                         /* fallthrough */
14010                 case 128:
14011                 default:
14012                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14013                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
14014                         break;
14015                 }
14016         } else {
14017                 switch (cacheline_size) {
14018                 case 16:
14019                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14020                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
14021                                         DMA_RWCTRL_WRITE_BNDRY_16);
14022                                 break;
14023                         }
14024                         /* fallthrough */
14025                 case 32:
14026                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14027                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
14028                                         DMA_RWCTRL_WRITE_BNDRY_32);
14029                                 break;
14030                         }
14031                         /* fallthrough */
14032                 case 64:
14033                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14034                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
14035                                         DMA_RWCTRL_WRITE_BNDRY_64);
14036                                 break;
14037                         }
14038                         /* fallthrough */
14039                 case 128:
14040                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14041                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
14042                                         DMA_RWCTRL_WRITE_BNDRY_128);
14043                                 break;
14044                         }
14045                         /* fallthrough */
14046                 case 256:
14047                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
14048                                 DMA_RWCTRL_WRITE_BNDRY_256);
14049                         break;
14050                 case 512:
14051                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
14052                                 DMA_RWCTRL_WRITE_BNDRY_512);
14053                         break;
14054                 case 1024:
14055                 default:
14056                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
14057                                 DMA_RWCTRL_WRITE_BNDRY_1024);
14058                         break;
14059                 }
14060         }
14061
14062 out:
14063         return val;
14064 }
14065
14066 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
14067 {
14068         struct tg3_internal_buffer_desc test_desc;
14069         u32 sram_dma_descs;
14070         int i, ret;
14071
14072         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
14073
14074         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
14075         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
14076         tw32(RDMAC_STATUS, 0);
14077         tw32(WDMAC_STATUS, 0);
14078
14079         tw32(BUFMGR_MODE, 0);
14080         tw32(FTQ_RESET, 0);
14081
14082         test_desc.addr_hi = ((u64) buf_dma) >> 32;
14083         test_desc.addr_lo = buf_dma & 0xffffffff;
14084         test_desc.nic_mbuf = 0x00002100;
14085         test_desc.len = size;
14086
14087         /*
14088          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
14089          * the *second* time the tg3 driver was getting loaded after an
14090          * initial scan.
14091          *
14092          * Broadcom tells me:
14093          *   ...the DMA engine is connected to the GRC block and a DMA
14094          *   reset may affect the GRC block in some unpredictable way...
14095          *   The behavior of resets to individual blocks has not been tested.
14096          *
14097          * Broadcom noted the GRC reset will also reset all sub-components.
14098          */
14099         if (to_device) {
14100                 test_desc.cqid_sqid = (13 << 8) | 2;
14101
14102                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
14103                 udelay(40);
14104         } else {
14105                 test_desc.cqid_sqid = (16 << 8) | 7;
14106
14107                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
14108                 udelay(40);
14109         }
14110         test_desc.flags = 0x00000005;
14111
14112         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
14113                 u32 val;
14114
14115                 val = *(((u32 *)&test_desc) + i);
14116                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
14117                                        sram_dma_descs + (i * sizeof(u32)));
14118                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
14119         }
14120         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
14121
14122         if (to_device)
14123                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
14124         else
14125                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
14126
14127         ret = -ENODEV;
14128         for (i = 0; i < 40; i++) {
14129                 u32 val;
14130
14131                 if (to_device)
14132                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
14133                 else
14134                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
14135                 if ((val & 0xffff) == sram_dma_descs) {
14136                         ret = 0;
14137                         break;
14138                 }
14139
14140                 udelay(100);
14141         }
14142
14143         return ret;
14144 }
14145
14146 #define TEST_BUFFER_SIZE        0x2000
14147
14148 static int __devinit tg3_test_dma(struct tg3 *tp)
14149 {
14150         dma_addr_t buf_dma;
14151         u32 *buf, saved_dma_rwctrl;
14152         int ret = 0;
14153
14154         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
14155         if (!buf) {
14156                 ret = -ENOMEM;
14157                 goto out_nofree;
14158         }
14159
14160         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
14161                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
14162
14163         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
14164
14165         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
14166                 goto out;
14167
14168         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14169                 /* DMA read watermark not used on PCIE */
14170                 tp->dma_rwctrl |= 0x00180000;
14171         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
14172                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
14173                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
14174                         tp->dma_rwctrl |= 0x003f0000;
14175                 else
14176                         tp->dma_rwctrl |= 0x003f000f;
14177         } else {
14178                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14179                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
14180                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
14181                         u32 read_water = 0x7;
14182
14183                         /* If the 5704 is behind the EPB bridge, we can
14184                          * do the less restrictive ONE_DMA workaround for
14185                          * better performance.
14186                          */
14187                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
14188                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14189                                 tp->dma_rwctrl |= 0x8000;
14190                         else if (ccval == 0x6 || ccval == 0x7)
14191                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
14192
14193                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
14194                                 read_water = 4;
14195                         /* Set bit 23 to enable PCIX hw bug fix */
14196                         tp->dma_rwctrl |=
14197                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
14198                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
14199                                 (1 << 23);
14200                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
14201                         /* 5780 always in PCIX mode */
14202                         tp->dma_rwctrl |= 0x00144000;
14203                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
14204                         /* 5714 always in PCIX mode */
14205                         tp->dma_rwctrl |= 0x00148000;
14206                 } else {
14207                         tp->dma_rwctrl |= 0x001b000f;
14208                 }
14209         }
14210
14211         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14212             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14213                 tp->dma_rwctrl &= 0xfffffff0;
14214
14215         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14216             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
14217                 /* Remove this if it causes problems for some boards. */
14218                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
14219
14220                 /* On 5700/5701 chips, we need to set this bit.
14221                  * Otherwise the chip will issue cacheline transactions
14222                  * to streamable DMA memory with not all the byte
14223                  * enables turned on.  This is an error on several
14224                  * RISC PCI controllers, in particular sparc64.
14225                  *
14226                  * On 5703/5704 chips, this bit has been reassigned
14227                  * a different meaning.  In particular, it is used
14228                  * on those chips to enable a PCI-X workaround.
14229                  */
14230                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
14231         }
14232
14233         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14234
14235 #if 0
14236         /* Unneeded, already done by tg3_get_invariants.  */
14237         tg3_switch_clocks(tp);
14238 #endif
14239
14240         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14241             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14242                 goto out;
14243
14244         /* It is best to perform DMA test with maximum write burst size
14245          * to expose the 5700/5701 write DMA bug.
14246          */
14247         saved_dma_rwctrl = tp->dma_rwctrl;
14248         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14249         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14250
14251         while (1) {
14252                 u32 *p = buf, i;
14253
14254                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14255                         p[i] = i;
14256
14257                 /* Send the buffer to the chip. */
14258                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14259                 if (ret) {
14260                         dev_err(&tp->pdev->dev,
14261                                 "%s: Buffer write failed. err = %d\n",
14262                                 __func__, ret);
14263                         break;
14264                 }
14265
14266 #if 0
14267                 /* validate data reached card RAM correctly. */
14268                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14269                         u32 val;
14270                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
14271                         if (le32_to_cpu(val) != p[i]) {
14272                                 dev_err(&tp->pdev->dev,
14273                                         "%s: Buffer corrupted on device! "
14274                                         "(%d != %d)\n", __func__, val, i);
14275                                 /* ret = -ENODEV here? */
14276                         }
14277                         p[i] = 0;
14278                 }
14279 #endif
14280                 /* Now read it back. */
14281                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14282                 if (ret) {
14283                         dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
14284                                 "err = %d\n", __func__, ret);
14285                         break;
14286                 }
14287
14288                 /* Verify it. */
14289                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14290                         if (p[i] == i)
14291                                 continue;
14292
14293                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14294                             DMA_RWCTRL_WRITE_BNDRY_16) {
14295                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14296                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14297                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14298                                 break;
14299                         } else {
14300                                 dev_err(&tp->pdev->dev,
14301                                         "%s: Buffer corrupted on read back! "
14302                                         "(%d != %d)\n", __func__, p[i], i);
14303                                 ret = -ENODEV;
14304                                 goto out;
14305                         }
14306                 }
14307
14308                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14309                         /* Success. */
14310                         ret = 0;
14311                         break;
14312                 }
14313         }
14314         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14315             DMA_RWCTRL_WRITE_BNDRY_16) {
14316                 static struct pci_device_id dma_wait_state_chipsets[] = {
14317                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14318                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14319                         { },
14320                 };
14321
14322                 /* DMA test passed without adjusting DMA boundary,
14323                  * now look for chipsets that are known to expose the
14324                  * DMA bug without failing the test.
14325                  */
14326                 if (pci_dev_present(dma_wait_state_chipsets)) {
14327                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14328                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14329                 } else {
14330                         /* Safe to use the calculated DMA boundary. */
14331                         tp->dma_rwctrl = saved_dma_rwctrl;
14332                 }
14333
14334                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14335         }
14336
14337 out:
14338         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14339 out_nofree:
14340         return ret;
14341 }
14342
14343 static void __devinit tg3_init_link_config(struct tg3 *tp)
14344 {
14345         tp->link_config.advertising =
14346                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14347                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14348                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14349                  ADVERTISED_Autoneg | ADVERTISED_MII);
14350         tp->link_config.speed = SPEED_INVALID;
14351         tp->link_config.duplex = DUPLEX_INVALID;
14352         tp->link_config.autoneg = AUTONEG_ENABLE;
14353         tp->link_config.active_speed = SPEED_INVALID;
14354         tp->link_config.active_duplex = DUPLEX_INVALID;
14355         tp->link_config.orig_speed = SPEED_INVALID;
14356         tp->link_config.orig_duplex = DUPLEX_INVALID;
14357         tp->link_config.orig_autoneg = AUTONEG_INVALID;
14358 }
14359
14360 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14361 {
14362         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
14363                 tp->bufmgr_config.mbuf_read_dma_low_water =
14364                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14365                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14366                         DEFAULT_MB_MACRX_LOW_WATER_57765;
14367                 tp->bufmgr_config.mbuf_high_water =
14368                         DEFAULT_MB_HIGH_WATER_57765;
14369
14370                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14371                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14372                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14373                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14374                 tp->bufmgr_config.mbuf_high_water_jumbo =
14375                         DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14376         } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14377                 tp->bufmgr_config.mbuf_read_dma_low_water =
14378                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14379                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14380                         DEFAULT_MB_MACRX_LOW_WATER_5705;
14381                 tp->bufmgr_config.mbuf_high_water =
14382                         DEFAULT_MB_HIGH_WATER_5705;
14383                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14384                         tp->bufmgr_config.mbuf_mac_rx_low_water =
14385                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
14386                         tp->bufmgr_config.mbuf_high_water =
14387                                 DEFAULT_MB_HIGH_WATER_5906;
14388                 }
14389
14390                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14391                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14392                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14393                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14394                 tp->bufmgr_config.mbuf_high_water_jumbo =
14395                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14396         } else {
14397                 tp->bufmgr_config.mbuf_read_dma_low_water =
14398                         DEFAULT_MB_RDMA_LOW_WATER;
14399                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14400                         DEFAULT_MB_MACRX_LOW_WATER;
14401                 tp->bufmgr_config.mbuf_high_water =
14402                         DEFAULT_MB_HIGH_WATER;
14403
14404                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14405                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14406                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14407                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14408                 tp->bufmgr_config.mbuf_high_water_jumbo =
14409                         DEFAULT_MB_HIGH_WATER_JUMBO;
14410         }
14411
14412         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14413         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14414 }
14415
14416 static char * __devinit tg3_phy_string(struct tg3 *tp)
14417 {
14418         switch (tp->phy_id & TG3_PHY_ID_MASK) {
14419         case TG3_PHY_ID_BCM5400:        return "5400";
14420         case TG3_PHY_ID_BCM5401:        return "5401";
14421         case TG3_PHY_ID_BCM5411:        return "5411";
14422         case TG3_PHY_ID_BCM5701:        return "5701";
14423         case TG3_PHY_ID_BCM5703:        return "5703";
14424         case TG3_PHY_ID_BCM5704:        return "5704";
14425         case TG3_PHY_ID_BCM5705:        return "5705";
14426         case TG3_PHY_ID_BCM5750:        return "5750";
14427         case TG3_PHY_ID_BCM5752:        return "5752";
14428         case TG3_PHY_ID_BCM5714:        return "5714";
14429         case TG3_PHY_ID_BCM5780:        return "5780";
14430         case TG3_PHY_ID_BCM5755:        return "5755";
14431         case TG3_PHY_ID_BCM5787:        return "5787";
14432         case TG3_PHY_ID_BCM5784:        return "5784";
14433         case TG3_PHY_ID_BCM5756:        return "5722/5756";
14434         case TG3_PHY_ID_BCM5906:        return "5906";
14435         case TG3_PHY_ID_BCM5761:        return "5761";
14436         case TG3_PHY_ID_BCM5718C:       return "5718C";
14437         case TG3_PHY_ID_BCM5718S:       return "5718S";
14438         case TG3_PHY_ID_BCM57765:       return "57765";
14439         case TG3_PHY_ID_BCM5719C:       return "5719C";
14440         case TG3_PHY_ID_BCM8002:        return "8002/serdes";
14441         case 0:                 return "serdes";
14442         default:                return "unknown";
14443         }
14444 }
14445
14446 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14447 {
14448         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14449                 strcpy(str, "PCI Express");
14450                 return str;
14451         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14452                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14453
14454                 strcpy(str, "PCIX:");
14455
14456                 if ((clock_ctrl == 7) ||
14457                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14458                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14459                         strcat(str, "133MHz");
14460                 else if (clock_ctrl == 0)
14461                         strcat(str, "33MHz");
14462                 else if (clock_ctrl == 2)
14463                         strcat(str, "50MHz");
14464                 else if (clock_ctrl == 4)
14465                         strcat(str, "66MHz");
14466                 else if (clock_ctrl == 6)
14467                         strcat(str, "100MHz");
14468         } else {
14469                 strcpy(str, "PCI:");
14470                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14471                         strcat(str, "66MHz");
14472                 else
14473                         strcat(str, "33MHz");
14474         }
14475         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14476                 strcat(str, ":32-bit");
14477         else
14478                 strcat(str, ":64-bit");
14479         return str;
14480 }
14481
14482 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14483 {
14484         struct pci_dev *peer;
14485         unsigned int func, devnr = tp->pdev->devfn & ~7;
14486
14487         for (func = 0; func < 8; func++) {
14488                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14489                 if (peer && peer != tp->pdev)
14490                         break;
14491                 pci_dev_put(peer);
14492         }
14493         /* 5704 can be configured in single-port mode, set peer to
14494          * tp->pdev in that case.
14495          */
14496         if (!peer) {
14497                 peer = tp->pdev;
14498                 return peer;
14499         }
14500
14501         /*
14502          * We don't need to keep the refcount elevated; there's no way
14503          * to remove one half of this device without removing the other
14504          */
14505         pci_dev_put(peer);
14506
14507         return peer;
14508 }
14509
14510 static void __devinit tg3_init_coal(struct tg3 *tp)
14511 {
14512         struct ethtool_coalesce *ec = &tp->coal;
14513
14514         memset(ec, 0, sizeof(*ec));
14515         ec->cmd = ETHTOOL_GCOALESCE;
14516         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14517         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14518         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14519         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14520         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14521         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14522         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14523         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14524         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14525
14526         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14527                                  HOSTCC_MODE_CLRTICK_TXBD)) {
14528                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14529                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14530                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14531                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14532         }
14533
14534         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14535                 ec->rx_coalesce_usecs_irq = 0;
14536                 ec->tx_coalesce_usecs_irq = 0;
14537                 ec->stats_block_coalesce_usecs = 0;
14538         }
14539 }
14540
14541 static const struct net_device_ops tg3_netdev_ops = {
14542         .ndo_open               = tg3_open,
14543         .ndo_stop               = tg3_close,
14544         .ndo_start_xmit         = tg3_start_xmit,
14545         .ndo_get_stats64        = tg3_get_stats64,
14546         .ndo_validate_addr      = eth_validate_addr,
14547         .ndo_set_multicast_list = tg3_set_rx_mode,
14548         .ndo_set_mac_address    = tg3_set_mac_addr,
14549         .ndo_do_ioctl           = tg3_ioctl,
14550         .ndo_tx_timeout         = tg3_tx_timeout,
14551         .ndo_change_mtu         = tg3_change_mtu,
14552 #if TG3_VLAN_TAG_USED
14553         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14554 #endif
14555 #ifdef CONFIG_NET_POLL_CONTROLLER
14556         .ndo_poll_controller    = tg3_poll_controller,
14557 #endif
14558 };
14559
14560 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14561         .ndo_open               = tg3_open,
14562         .ndo_stop               = tg3_close,
14563         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
14564         .ndo_get_stats64        = tg3_get_stats64,
14565         .ndo_validate_addr      = eth_validate_addr,
14566         .ndo_set_multicast_list = tg3_set_rx_mode,
14567         .ndo_set_mac_address    = tg3_set_mac_addr,
14568         .ndo_do_ioctl           = tg3_ioctl,
14569         .ndo_tx_timeout         = tg3_tx_timeout,
14570         .ndo_change_mtu         = tg3_change_mtu,
14571 #if TG3_VLAN_TAG_USED
14572         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14573 #endif
14574 #ifdef CONFIG_NET_POLL_CONTROLLER
14575         .ndo_poll_controller    = tg3_poll_controller,
14576 #endif
14577 };
14578
14579 static int __devinit tg3_init_one(struct pci_dev *pdev,
14580                                   const struct pci_device_id *ent)
14581 {
14582         struct net_device *dev;
14583         struct tg3 *tp;
14584         int i, err, pm_cap;
14585         u32 sndmbx, rcvmbx, intmbx;
14586         char str[40];
14587         u64 dma_mask, persist_dma_mask;
14588
14589         printk_once(KERN_INFO "%s\n", version);
14590
14591         err = pci_enable_device(pdev);
14592         if (err) {
14593                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
14594                 return err;
14595         }
14596
14597         err = pci_request_regions(pdev, DRV_MODULE_NAME);
14598         if (err) {
14599                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
14600                 goto err_out_disable_pdev;
14601         }
14602
14603         pci_set_master(pdev);
14604
14605         /* Find power-management capability. */
14606         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14607         if (pm_cap == 0) {
14608                 dev_err(&pdev->dev,
14609                         "Cannot find Power Management capability, aborting\n");
14610                 err = -EIO;
14611                 goto err_out_free_res;
14612         }
14613
14614         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14615         if (!dev) {
14616                 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
14617                 err = -ENOMEM;
14618                 goto err_out_free_res;
14619         }
14620
14621         SET_NETDEV_DEV(dev, &pdev->dev);
14622
14623 #if TG3_VLAN_TAG_USED
14624         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14625 #endif
14626
14627         tp = netdev_priv(dev);
14628         tp->pdev = pdev;
14629         tp->dev = dev;
14630         tp->pm_cap = pm_cap;
14631         tp->rx_mode = TG3_DEF_RX_MODE;
14632         tp->tx_mode = TG3_DEF_TX_MODE;
14633
14634         if (tg3_debug > 0)
14635                 tp->msg_enable = tg3_debug;
14636         else
14637                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14638
14639         /* The word/byte swap controls here control register access byte
14640          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
14641          * setting below.
14642          */
14643         tp->misc_host_ctrl =
14644                 MISC_HOST_CTRL_MASK_PCI_INT |
14645                 MISC_HOST_CTRL_WORD_SWAP |
14646                 MISC_HOST_CTRL_INDIR_ACCESS |
14647                 MISC_HOST_CTRL_PCISTATE_RW;
14648
14649         /* The NONFRM (non-frame) byte/word swap controls take effect
14650          * on descriptor entries, anything which isn't packet data.
14651          *
14652          * The StrongARM chips on the board (one for tx, one for rx)
14653          * are running in big-endian mode.
14654          */
14655         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14656                         GRC_MODE_WSWAP_NONFRM_DATA);
14657 #ifdef __BIG_ENDIAN
14658         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14659 #endif
14660         spin_lock_init(&tp->lock);
14661         spin_lock_init(&tp->indirect_lock);
14662         INIT_WORK(&tp->reset_task, tg3_reset_task);
14663
14664         tp->regs = pci_ioremap_bar(pdev, BAR_0);
14665         if (!tp->regs) {
14666                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
14667                 err = -ENOMEM;
14668                 goto err_out_free_dev;
14669         }
14670
14671         tg3_init_link_config(tp);
14672
14673         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14674         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14675
14676         dev->ethtool_ops = &tg3_ethtool_ops;
14677         dev->watchdog_timeo = TG3_TX_TIMEOUT;
14678         dev->irq = pdev->irq;
14679
14680         err = tg3_get_invariants(tp);
14681         if (err) {
14682                 dev_err(&pdev->dev,
14683                         "Problem fetching invariants of chip, aborting\n");
14684                 goto err_out_iounmap;
14685         }
14686
14687         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14688             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
14689             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
14690                 dev->netdev_ops = &tg3_netdev_ops;
14691         else
14692                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14693
14694
14695         /* The EPB bridge inside 5714, 5715, and 5780 and any
14696          * device behind the EPB cannot support DMA addresses > 40-bit.
14697          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14698          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14699          * do DMA address check in tg3_start_xmit().
14700          */
14701         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14702                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14703         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14704                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14705 #ifdef CONFIG_HIGHMEM
14706                 dma_mask = DMA_BIT_MASK(64);
14707 #endif
14708         } else
14709                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14710
14711         /* Configure DMA attributes. */
14712         if (dma_mask > DMA_BIT_MASK(32)) {
14713                 err = pci_set_dma_mask(pdev, dma_mask);
14714                 if (!err) {
14715                         dev->features |= NETIF_F_HIGHDMA;
14716                         err = pci_set_consistent_dma_mask(pdev,
14717                                                           persist_dma_mask);
14718                         if (err < 0) {
14719                                 dev_err(&pdev->dev, "Unable to obtain 64 bit "
14720                                         "DMA for consistent allocations\n");
14721                                 goto err_out_iounmap;
14722                         }
14723                 }
14724         }
14725         if (err || dma_mask == DMA_BIT_MASK(32)) {
14726                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14727                 if (err) {
14728                         dev_err(&pdev->dev,
14729                                 "No usable DMA configuration, aborting\n");
14730                         goto err_out_iounmap;
14731                 }
14732         }
14733
14734         tg3_init_bufmgr_config(tp);
14735
14736         /* Selectively allow TSO based on operating conditions */
14737         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14738             (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14739                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14740         else {
14741                 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14742                 tp->fw_needed = NULL;
14743         }
14744
14745         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14746                 tp->fw_needed = FIRMWARE_TG3;
14747
14748         /* TSO is on by default on chips that support hardware TSO.
14749          * Firmware TSO on older chips gives lower performance, so it
14750          * is off by default, but can be enabled using ethtool.
14751          */
14752         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14753             (dev->features & NETIF_F_IP_CSUM)) {
14754                 dev->features |= NETIF_F_TSO;
14755                 vlan_features_add(dev, NETIF_F_TSO);
14756         }
14757         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14758             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14759                 if (dev->features & NETIF_F_IPV6_CSUM) {
14760                         dev->features |= NETIF_F_TSO6;
14761                         vlan_features_add(dev, NETIF_F_TSO6);
14762                 }
14763                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14764                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14765                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14766                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14767                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14768                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
14769                         dev->features |= NETIF_F_TSO_ECN;
14770                         vlan_features_add(dev, NETIF_F_TSO_ECN);
14771                 }
14772         }
14773
14774         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14775             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14776             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14777                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14778                 tp->rx_pending = 63;
14779         }
14780
14781         err = tg3_get_device_address(tp);
14782         if (err) {
14783                 dev_err(&pdev->dev,
14784                         "Could not obtain valid ethernet address, aborting\n");
14785                 goto err_out_iounmap;
14786         }
14787
14788         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14789                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14790                 if (!tp->aperegs) {
14791                         dev_err(&pdev->dev,
14792                                 "Cannot map APE registers, aborting\n");
14793                         err = -ENOMEM;
14794                         goto err_out_iounmap;
14795                 }
14796
14797                 tg3_ape_lock_init(tp);
14798
14799                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14800                         tg3_read_dash_ver(tp);
14801         }
14802
14803         /*
14804          * Reset chip in case UNDI or EFI driver did not shutdown
14805          * DMA self test will enable WDMAC and we'll see (spurious)
14806          * pending DMA on the PCI bus at that point.
14807          */
14808         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14809             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14810                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14811                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14812         }
14813
14814         err = tg3_test_dma(tp);
14815         if (err) {
14816                 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
14817                 goto err_out_apeunmap;
14818         }
14819
14820         /* flow control autonegotiation is default behavior */
14821         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14822         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14823
14824         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14825         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14826         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14827         for (i = 0; i < tp->irq_max; i++) {
14828                 struct tg3_napi *tnapi = &tp->napi[i];
14829
14830                 tnapi->tp = tp;
14831                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14832
14833                 tnapi->int_mbox = intmbx;
14834                 if (i < 4)
14835                         intmbx += 0x8;
14836                 else
14837                         intmbx += 0x4;
14838
14839                 tnapi->consmbox = rcvmbx;
14840                 tnapi->prodmbox = sndmbx;
14841
14842                 if (i)
14843                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14844                 else
14845                         tnapi->coal_now = HOSTCC_MODE_NOW;
14846
14847                 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14848                         break;
14849
14850                 /*
14851                  * If we support MSIX, we'll be using RSS.  If we're using
14852                  * RSS, the first vector only handles link interrupts and the
14853                  * remaining vectors handle rx and tx interrupts.  Reuse the
14854                  * mailbox values for the next iteration.  The values we setup
14855                  * above are still useful for the single vectored mode.
14856                  */
14857                 if (!i)
14858                         continue;
14859
14860                 rcvmbx += 0x8;
14861
14862                 if (sndmbx & 0x4)
14863                         sndmbx -= 0x4;
14864                 else
14865                         sndmbx += 0xc;
14866         }
14867
14868         tg3_init_coal(tp);
14869
14870         pci_set_drvdata(pdev, dev);
14871
14872         err = register_netdev(dev);
14873         if (err) {
14874                 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
14875                 goto err_out_apeunmap;
14876         }
14877
14878         netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14879                     tp->board_part_number,
14880                     tp->pci_chip_rev_id,
14881                     tg3_bus_string(tp, str),
14882                     dev->dev_addr);
14883
14884         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
14885                 struct phy_device *phydev;
14886                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14887                 netdev_info(dev,
14888                             "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14889                             phydev->drv->name, dev_name(&phydev->dev));
14890         } else {
14891                 char *ethtype;
14892
14893                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
14894                         ethtype = "10/100Base-TX";
14895                 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
14896                         ethtype = "1000Base-SX";
14897                 else
14898                         ethtype = "10/100/1000Base-T";
14899
14900                 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
14901                             "(WireSpeed[%d])\n", tg3_phy_string(tp), ethtype,
14902                           (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0);
14903         }
14904
14905         netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14906                     (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14907                     (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14908                     (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
14909                     (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14910                     (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14911         netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14912                     tp->dma_rwctrl,
14913                     pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
14914                     ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
14915
14916         return 0;
14917
14918 err_out_apeunmap:
14919         if (tp->aperegs) {
14920                 iounmap(tp->aperegs);
14921                 tp->aperegs = NULL;
14922         }
14923
14924 err_out_iounmap:
14925         if (tp->regs) {
14926                 iounmap(tp->regs);
14927                 tp->regs = NULL;
14928         }
14929
14930 err_out_free_dev:
14931         free_netdev(dev);
14932
14933 err_out_free_res:
14934         pci_release_regions(pdev);
14935
14936 err_out_disable_pdev:
14937         pci_disable_device(pdev);
14938         pci_set_drvdata(pdev, NULL);
14939         return err;
14940 }
14941
14942 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14943 {
14944         struct net_device *dev = pci_get_drvdata(pdev);
14945
14946         if (dev) {
14947                 struct tg3 *tp = netdev_priv(dev);
14948
14949                 if (tp->fw)
14950                         release_firmware(tp->fw);
14951
14952                 flush_scheduled_work();
14953
14954                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14955                         tg3_phy_fini(tp);
14956                         tg3_mdio_fini(tp);
14957                 }
14958
14959                 unregister_netdev(dev);
14960                 if (tp->aperegs) {
14961                         iounmap(tp->aperegs);
14962                         tp->aperegs = NULL;
14963                 }
14964                 if (tp->regs) {
14965                         iounmap(tp->regs);
14966                         tp->regs = NULL;
14967                 }
14968                 free_netdev(dev);
14969                 pci_release_regions(pdev);
14970                 pci_disable_device(pdev);
14971                 pci_set_drvdata(pdev, NULL);
14972         }
14973 }
14974
14975 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14976 {
14977         struct net_device *dev = pci_get_drvdata(pdev);
14978         struct tg3 *tp = netdev_priv(dev);
14979         pci_power_t target_state;
14980         int err;
14981
14982         /* PCI register 4 needs to be saved whether netif_running() or not.
14983          * MSI address and data need to be saved if using MSI and
14984          * netif_running().
14985          */
14986         pci_save_state(pdev);
14987
14988         if (!netif_running(dev))
14989                 return 0;
14990
14991         flush_scheduled_work();
14992         tg3_phy_stop(tp);
14993         tg3_netif_stop(tp);
14994
14995         del_timer_sync(&tp->timer);
14996
14997         tg3_full_lock(tp, 1);
14998         tg3_disable_ints(tp);
14999         tg3_full_unlock(tp);
15000
15001         netif_device_detach(dev);
15002
15003         tg3_full_lock(tp, 0);
15004         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
15005         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
15006         tg3_full_unlock(tp);
15007
15008         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
15009
15010         err = tg3_set_power_state(tp, target_state);
15011         if (err) {
15012                 int err2;
15013
15014                 tg3_full_lock(tp, 0);
15015
15016                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
15017                 err2 = tg3_restart_hw(tp, 1);
15018                 if (err2)
15019                         goto out;
15020
15021                 tp->timer.expires = jiffies + tp->timer_offset;
15022                 add_timer(&tp->timer);
15023
15024                 netif_device_attach(dev);
15025                 tg3_netif_start(tp);
15026
15027 out:
15028                 tg3_full_unlock(tp);
15029
15030                 if (!err2)
15031                         tg3_phy_start(tp);
15032         }
15033
15034         return err;
15035 }
15036
15037 static int tg3_resume(struct pci_dev *pdev)
15038 {
15039         struct net_device *dev = pci_get_drvdata(pdev);
15040         struct tg3 *tp = netdev_priv(dev);
15041         int err;
15042
15043         pci_restore_state(tp->pdev);
15044
15045         if (!netif_running(dev))
15046                 return 0;
15047
15048         err = tg3_set_power_state(tp, PCI_D0);
15049         if (err)
15050                 return err;
15051
15052         netif_device_attach(dev);
15053
15054         tg3_full_lock(tp, 0);
15055
15056         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
15057         err = tg3_restart_hw(tp, 1);
15058         if (err)
15059                 goto out;
15060
15061         tp->timer.expires = jiffies + tp->timer_offset;
15062         add_timer(&tp->timer);
15063
15064         tg3_netif_start(tp);
15065
15066 out:
15067         tg3_full_unlock(tp);
15068
15069         if (!err)
15070                 tg3_phy_start(tp);
15071
15072         return err;
15073 }
15074
15075 static struct pci_driver tg3_driver = {
15076         .name           = DRV_MODULE_NAME,
15077         .id_table       = tg3_pci_tbl,
15078         .probe          = tg3_init_one,
15079         .remove         = __devexit_p(tg3_remove_one),
15080         .suspend        = tg3_suspend,
15081         .resume         = tg3_resume
15082 };
15083
15084 static int __init tg3_init(void)
15085 {
15086         return pci_register_driver(&tg3_driver);
15087 }
15088
15089 static void __exit tg3_cleanup(void)
15090 {
15091         pci_unregister_driver(&tg3_driver);
15092 }
15093
15094 module_init(tg3_init);
15095 module_exit(tg3_cleanup);