drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2010 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/stringify.h>
  22 #include <linux/kernel.h>
  23 #include <linux/types.h>
  24 #include <linux/compiler.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/in.h>
  28 #include <linux/init.h>
  29 #include <linux/ioport.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/ethtool.h>
  35 #include <linux/mii.h>
  36 #include <linux/phy.h>
  37 #include <linux/brcmphy.h>
  38 #include <linux/if_vlan.h>
  39 #include <linux/ip.h>
  40 #include <linux/tcp.h>
  41 #include <linux/workqueue.h>
  42 #include <linux/prefetch.h>
  43 #include <linux/dma-mapping.h>
  44 #include <linux/firmware.h>
  45
  46 #include <net/checksum.h>
  47 #include <net/ip.h>
  48
  49 #include <asm/system.h>
  50 #include <asm/io.h>
  51 #include <asm/byteorder.h>
  52 #include <asm/uaccess.h>
  53
  54 #ifdef CONFIG_SPARC
  55 #include <asm/idprom.h>
  56 #include <asm/prom.h>
  57 #endif
  58
  59 #define BAR_0   0
  60 #define BAR_2   2
  61
  62 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  63 #define TG3_VLAN_TAG_USED 1
  64 #else
  65 #define TG3_VLAN_TAG_USED 0
  66 #endif
  67
  68 #include "tg3.h"
  69
  70 #define DRV_MODULE_NAME         "tg3"
  71 #define TG3_MAJ_NUM                     3
  72 #define TG3_MIN_NUM                     112
  73 #define DRV_MODULE_VERSION      \
  74         __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
  75 #define DRV_MODULE_RELDATE      "July 11, 2010"
  76
  77 #define TG3_DEF_MAC_MODE        0
  78 #define TG3_DEF_RX_MODE         0
  79 #define TG3_DEF_TX_MODE         0
  80 #define TG3_DEF_MSG_ENABLE        \
  81         (NETIF_MSG_DRV          | \
  82          NETIF_MSG_PROBE        | \
  83          NETIF_MSG_LINK         | \
  84          NETIF_MSG_TIMER        | \
  85          NETIF_MSG_IFDOWN       | \
  86          NETIF_MSG_IFUP         | \
  87          NETIF_MSG_RX_ERR       | \
  88          NETIF_MSG_TX_ERR)
  89
  90 /* length of time before we decide the hardware is borked,
  91  * and dev->tx_timeout() should be called to fix the problem
  92  */
  93 #define TG3_TX_TIMEOUT                  (5 * HZ)
  94
  95 /* hardware minimum and maximum for a single frame's data payload */
  96 #define TG3_MIN_MTU                     60
  97 #define TG3_MAX_MTU(tp) \
  98         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  99
 100 /* These numbers seem to be hard coded in the NIC firmware somehow.
 101  * You can't change the ring sizes, but you can change where you place
 102  * them in the NIC onboard memory.
 103  */
 104 #define TG3_RX_RING_SIZE                512
 105 #define TG3_DEF_RX_RING_PENDING         200
 106 #define TG3_RX_JUMBO_RING_SIZE          256
 107 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 108 #define TG3_RSS_INDIR_TBL_SIZE          128
 109
 110 /* Do not place this n-ring entries value into the tp struct itself,
 111  * we really want to expose these constants to GCC so that modulo et
 112  * al.  operations are done with shifts and masks instead of with
 113  * hw multiply/modulo instructions.  Another solution would be to
 114  * replace things like '% foo' with '& (foo - 1)'.
 115  */
 116 #define TG3_RX_RCB_RING_SIZE(tp)        \
 117         (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
 118           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
 119
 120 #define TG3_TX_RING_SIZE                512
 121 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 122
 123 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 124                                  TG3_RX_RING_SIZE)
 125 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
 126                                  TG3_RX_JUMBO_RING_SIZE)
 127 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 128                                  TG3_RX_RCB_RING_SIZE(tp))
 129 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 130                                  TG3_TX_RING_SIZE)
 131 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 132
 133 #define TG3_RX_DMA_ALIGN                16
 134 #define TG3_RX_HEADROOM                 ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
 135
 136 #define TG3_DMA_BYTE_ENAB               64
 137
 138 #define TG3_RX_STD_DMA_SZ               1536
 139 #define TG3_RX_JMB_DMA_SZ               9046
 140
 141 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 142
 143 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 144 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 145
 146 #define TG3_RX_STD_BUFF_RING_SIZE \
 147         (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
 148
 149 #define TG3_RX_JMB_BUFF_RING_SIZE \
 150         (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
 151
 152 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
 153  * that are at least dword aligned when used in PCIX mode.  The driver
 154  * works around this bug by double copying the packet.  This workaround
 155  * is built into the normal double copy length check for efficiency.
 156  *
 157  * However, the double copy is only necessary on those architectures
 158  * where unaligned memory accesses are inefficient.  For those architectures
 159  * where unaligned memory accesses incur little penalty, we can reintegrate
 160  * the 5701 in the normal rx path.  Doing so saves a device structure
 161  * dereference by hardcoding the double copy threshold in place.
 162  */
 163 #define TG3_RX_COPY_THRESHOLD           256
 164 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
 165         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
 166 #else
 167         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
 168 #endif
 169
 170 /* minimum number of free TX descriptors required to wake up TX process */
 171 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 172
 173 #define TG3_RAW_IP_ALIGN 2
 174
 175 /* number of ETHTOOL_GSTATS u64's */
 176 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 177
 178 #define TG3_NUM_TEST            6
 179
 180 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
 181
 182 #define FIRMWARE_TG3            "tigon/tg3.bin"
 183 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 184 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 185
 186 static char version[] __devinitdata =
 187         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
 188
 189 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 190 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 191 MODULE_LICENSE("GPL");
 192 MODULE_VERSION(DRV_MODULE_VERSION);
 193 MODULE_FIRMWARE(FIRMWARE_TG3);
 194 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 195 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 196
 197 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 198 module_param(tg3_debug, int, 0);
 199 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 200
 201 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 255         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 256         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 257         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 258         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 259         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 260         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 261         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 262         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 263         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 264         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 265         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
 266         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
 267         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
 268         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
 269         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
 270         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
 271         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
 272         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
 273         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
 274         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
 275         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 276         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 277         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 278         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 279         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 280         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 281         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 282         {}
 283 };
 284
 285 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 286
 287 static const struct {
 288         const char string[ETH_GSTRING_LEN];
 289 } ethtool_stats_keys[TG3_NUM_STATS] = {
 290         { "rx_octets" },
 291         { "rx_fragments" },
 292         { "rx_ucast_packets" },
 293         { "rx_mcast_packets" },
 294         { "rx_bcast_packets" },
 295         { "rx_fcs_errors" },
 296         { "rx_align_errors" },
 297         { "rx_xon_pause_rcvd" },
 298         { "rx_xoff_pause_rcvd" },
 299         { "rx_mac_ctrl_rcvd" },
 300         { "rx_xoff_entered" },
 301         { "rx_frame_too_long_errors" },
 302         { "rx_jabbers" },
 303         { "rx_undersize_packets" },
 304         { "rx_in_length_errors" },
 305         { "rx_out_length_errors" },
 306         { "rx_64_or_less_octet_packets" },
 307         { "rx_65_to_127_octet_packets" },
 308         { "rx_128_to_255_octet_packets" },
 309         { "rx_256_to_511_octet_packets" },
 310         { "rx_512_to_1023_octet_packets" },
 311         { "rx_1024_to_1522_octet_packets" },
 312         { "rx_1523_to_2047_octet_packets" },
 313         { "rx_2048_to_4095_octet_packets" },
 314         { "rx_4096_to_8191_octet_packets" },
 315         { "rx_8192_to_9022_octet_packets" },
 316
 317         { "tx_octets" },
 318         { "tx_collisions" },
 319
 320         { "tx_xon_sent" },
 321         { "tx_xoff_sent" },
 322         { "tx_flow_control" },
 323         { "tx_mac_errors" },
 324         { "tx_single_collisions" },
 325         { "tx_mult_collisions" },
 326         { "tx_deferred" },
 327         { "tx_excessive_collisions" },
 328         { "tx_late_collisions" },
 329         { "tx_collide_2times" },
 330         { "tx_collide_3times" },
 331         { "tx_collide_4times" },
 332         { "tx_collide_5times" },
 333         { "tx_collide_6times" },
 334         { "tx_collide_7times" },
 335         { "tx_collide_8times" },
 336         { "tx_collide_9times" },
 337         { "tx_collide_10times" },
 338         { "tx_collide_11times" },
 339         { "tx_collide_12times" },
 340         { "tx_collide_13times" },
 341         { "tx_collide_14times" },
 342         { "tx_collide_15times" },
 343         { "tx_ucast_packets" },
 344         { "tx_mcast_packets" },
 345         { "tx_bcast_packets" },
 346         { "tx_carrier_sense_errors" },
 347         { "tx_discards" },
 348         { "tx_errors" },
 349
 350         { "dma_writeq_full" },
 351         { "dma_write_prioq_full" },
 352         { "rxbds_empty" },
 353         { "rx_discards" },
 354         { "rx_errors" },
 355         { "rx_threshold_hit" },
 356
 357         { "dma_readq_full" },
 358         { "dma_read_prioq_full" },
 359         { "tx_comp_queue_full" },
 360
 361         { "ring_set_send_prod_index" },
 362         { "ring_status_update" },
 363         { "nic_irqs" },
 364         { "nic_avoided_irqs" },
 365         { "nic_tx_threshold_hit" }
 366 };
 367
 368 static const struct {
 369         const char string[ETH_GSTRING_LEN];
 370 } ethtool_test_keys[TG3_NUM_TEST] = {
 371         { "nvram test     (online) " },
 372         { "link test      (online) " },
 373         { "register test  (offline)" },
 374         { "memory test    (offline)" },
 375         { "loopback test  (offline)" },
 376         { "interrupt test (offline)" },
 377 };
 378
 379 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 380 {
 381         writel(val, tp->regs + off);
 382 }
 383
 384 static u32 tg3_read32(struct tg3 *tp, u32 off)
 385 {
 386         return readl(tp->regs + off);
 387 }
 388
 389 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 390 {
 391         writel(val, tp->aperegs + off);
 392 }
 393
 394 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 395 {
 396         return readl(tp->aperegs + off);
 397 }
 398
 399 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 400 {
 401         unsigned long flags;
 402
 403         spin_lock_irqsave(&tp->indirect_lock, flags);
 404         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 405         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 406         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 407 }
 408
 409 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 410 {
 411         writel(val, tp->regs + off);
 412         readl(tp->regs + off);
 413 }
 414
 415 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 416 {
 417         unsigned long flags;
 418         u32 val;
 419
 420         spin_lock_irqsave(&tp->indirect_lock, flags);
 421         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 422         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 423         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 424         return val;
 425 }
 426
 427 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 428 {
 429         unsigned long flags;
 430
 431         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 432                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 433                                        TG3_64BIT_REG_LOW, val);
 434                 return;
 435         }
 436         if (off == TG3_RX_STD_PROD_IDX_REG) {
 437                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 438                                        TG3_64BIT_REG_LOW, val);
 439                 return;
 440         }
 441
 442         spin_lock_irqsave(&tp->indirect_lock, flags);
 443         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 444         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 445         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 446
 447         /* In indirect mode when disabling interrupts, we also need
 448          * to clear the interrupt bit in the GRC local ctrl register.
 449          */
 450         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 451             (val == 0x1)) {
 452                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 453                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 454         }
 455 }
 456
 457 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 458 {
 459         unsigned long flags;
 460         u32 val;
 461
 462         spin_lock_irqsave(&tp->indirect_lock, flags);
 463         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 464         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 465         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 466         return val;
 467 }
 468
 469 /* usec_wait specifies the wait time in usec when writing to certain registers
 470  * where it is unsafe to read back the register without some delay.
 471  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 472  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 473  */
 474 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 475 {
 476         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 477             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 478                 /* Non-posted methods */
 479                 tp->write32(tp, off, val);
 480         else {
 481                 /* Posted method */
 482                 tg3_write32(tp, off, val);
 483                 if (usec_wait)
 484                         udelay(usec_wait);
 485                 tp->read32(tp, off);
 486         }
 487         /* Wait again after the read for the posted method to guarantee that
 488          * the wait time is met.
 489          */
 490         if (usec_wait)
 491                 udelay(usec_wait);
 492 }
 493
 494 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 495 {
 496         tp->write32_mbox(tp, off, val);
 497         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 498             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 499                 tp->read32_mbox(tp, off);
 500 }
 501
 502 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 503 {
 504         void __iomem *mbox = tp->regs + off;
 505         writel(val, mbox);
 506         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 507                 writel(val, mbox);
 508         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 509                 readl(mbox);
 510 }
 511
 512 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 513 {
 514         return readl(tp->regs + off + GRCMBOX_BASE);
 515 }
 516
 517 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 518 {
 519         writel(val, tp->regs + off + GRCMBOX_BASE);
 520 }
 521
 522 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
 523 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 524 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
 525 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
 526 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
 527
 528 #define tw32(reg, val)                  tp->write32(tp, reg, val)
 529 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
 530 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
 531 #define tr32(reg)                       tp->read32(tp, reg)
 532
 533 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 534 {
 535         unsigned long flags;
 536
 537         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 538             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 539                 return;
 540
 541         spin_lock_irqsave(&tp->indirect_lock, flags);
 542         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 543                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 544                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 545
 546                 /* Always leave this as zero. */
 547                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 548         } else {
 549                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 550                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 551
 552                 /* Always leave this as zero. */
 553                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 554         }
 555         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 556 }
 557
 558 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 559 {
 560         unsigned long flags;
 561
 562         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 563             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 564                 *val = 0;
 565                 return;
 566         }
 567
 568         spin_lock_irqsave(&tp->indirect_lock, flags);
 569         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 570                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 571                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 572
 573                 /* Always leave this as zero. */
 574                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 575         } else {
 576                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 577                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 578
 579                 /* Always leave this as zero. */
 580                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 581         }
 582         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 583 }
 584
 585 static void tg3_ape_lock_init(struct tg3 *tp)
 586 {
 587         int i;
 588         u32 regbase;
 589
 590         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 591                 regbase = TG3_APE_LOCK_GRANT;
 592         else
 593                 regbase = TG3_APE_PER_LOCK_GRANT;
 594
 595         /* Make sure the driver hasn't any stale locks. */
 596         for (i = 0; i < 8; i++)
 597                 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
 598 }
 599
 600 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 601 {
 602         int i, off;
 603         int ret = 0;
 604         u32 status, req, gnt;
 605
 606         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 607                 return 0;
 608
 609         switch (locknum) {
 610         case TG3_APE_LOCK_GRC:
 611         case TG3_APE_LOCK_MEM:
 612                 break;
 613         default:
 614                 return -EINVAL;
 615         }
 616
 617         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
 618                 req = TG3_APE_LOCK_REQ;
 619                 gnt = TG3_APE_LOCK_GRANT;
 620         } else {
 621                 req = TG3_APE_PER_LOCK_REQ;
 622                 gnt = TG3_APE_PER_LOCK_GRANT;
 623         }
 624
 625         off = 4 * locknum;
 626
 627         tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
 628
 629         /* Wait for up to 1 millisecond to acquire lock. */
 630         for (i = 0; i < 100; i++) {
 631                 status = tg3_ape_read32(tp, gnt + off);
 632                 if (status == APE_LOCK_GRANT_DRIVER)
 633                         break;
 634                 udelay(10);
 635         }
 636
 637         if (status != APE_LOCK_GRANT_DRIVER) {
 638                 /* Revoke the lock request. */
 639                 tg3_ape_write32(tp, gnt + off,
 640                                 APE_LOCK_GRANT_DRIVER);
 641
 642                 ret = -EBUSY;
 643         }
 644
 645         return ret;
 646 }
 647
 648 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 649 {
 650         u32 gnt;
 651
 652         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 653                 return;
 654
 655         switch (locknum) {
 656         case TG3_APE_LOCK_GRC:
 657         case TG3_APE_LOCK_MEM:
 658                 break;
 659         default:
 660                 return;
 661         }
 662
 663         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 664                 gnt = TG3_APE_LOCK_GRANT;
 665         else
 666                 gnt = TG3_APE_PER_LOCK_GRANT;
 667
 668         tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
 669 }
 670
 671 static void tg3_disable_ints(struct tg3 *tp)
 672 {
 673         int i;
 674
 675         tw32(TG3PCI_MISC_HOST_CTRL,
 676              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 677         for (i = 0; i < tp->irq_max; i++)
 678                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 679 }
 680
 681 static void tg3_enable_ints(struct tg3 *tp)
 682 {
 683         int i;
 684
 685         tp->irq_sync = 0;
 686         wmb();
 687
 688         tw32(TG3PCI_MISC_HOST_CTRL,
 689              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 690
 691         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
 692         for (i = 0; i < tp->irq_cnt; i++) {
 693                 struct tg3_napi *tnapi = &tp->napi[i];
 694
 695                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 696                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 697                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 698
 699                 tp->coal_now |= tnapi->coal_now;
 700         }
 701
 702         /* Force an initial interrupt */
 703         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 704             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 705                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 706         else
 707                 tw32(HOSTCC_MODE, tp->coal_now);
 708
 709         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
 710 }
 711
 712 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 713 {
 714         struct tg3 *tp = tnapi->tp;
 715         struct tg3_hw_status *sblk = tnapi->hw_status;
 716         unsigned int work_exists = 0;
 717
 718         /* check for phy events */
 719         if (!(tp->tg3_flags &
 720               (TG3_FLAG_USE_LINKCHG_REG |
 721                TG3_FLAG_POLL_SERDES))) {
 722                 if (sblk->status & SD_STATUS_LINK_CHG)
 723                         work_exists = 1;
 724         }
 725         /* check for RX/TX work to do */
 726         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 727             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
 728                 work_exists = 1;
 729
 730         return work_exists;
 731 }
 732
 733 /* tg3_int_reenable
 734  *  similar to tg3_enable_ints, but it accurately determines whether there
 735  *  is new work pending and can return without flushing the PIO write
 736  *  which reenables interrupts
 737  */
 738 static void tg3_int_reenable(struct tg3_napi *tnapi)
 739 {
 740         struct tg3 *tp = tnapi->tp;
 741
 742         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 743         mmiowb();
 744
 745         /* When doing tagged status, this work check is unnecessary.
 746          * The last_tag we write above tells the chip which piece of
 747          * work we've completed.
 748          */
 749         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 750             tg3_has_work(tnapi))
 751                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 752                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 753 }
 754
 755 static void tg3_napi_disable(struct tg3 *tp)
 756 {
 757         int i;
 758
 759         for (i = tp->irq_cnt - 1; i >= 0; i--)
 760                 napi_disable(&tp->napi[i].napi);
 761 }
 762
 763 static void tg3_napi_enable(struct tg3 *tp)
 764 {
 765         int i;
 766
 767         for (i = 0; i < tp->irq_cnt; i++)
 768                 napi_enable(&tp->napi[i].napi);
 769 }
 770
 771 static inline void tg3_netif_stop(struct tg3 *tp)
 772 {
 773         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 774         tg3_napi_disable(tp);
 775         netif_tx_disable(tp->dev);
 776 }
 777
 778 static inline void tg3_netif_start(struct tg3 *tp)
 779 {
 780         /* NOTE: unconditional netif_tx_wake_all_queues is only
 781          * appropriate so long as all callers are assured to
 782          * have free tx slots (such as after tg3_init_hw)
 783          */
 784         netif_tx_wake_all_queues(tp->dev);
 785
 786         tg3_napi_enable(tp);
 787         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
 788         tg3_enable_ints(tp);
 789 }
 790
 791 static void tg3_switch_clocks(struct tg3 *tp)
 792 {
 793         u32 clock_ctrl;
 794         u32 orig_clock_ctrl;
 795
 796         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 797             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 798                 return;
 799
 800         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 801
 802         orig_clock_ctrl = clock_ctrl;
 803         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 804                        CLOCK_CTRL_CLKRUN_OENABLE |
 805                        0x1f);
 806         tp->pci_clock_ctrl = clock_ctrl;
 807
 808         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 809                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 810                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 811                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 812                 }
 813         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 814                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 815                             clock_ctrl |
 816                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 817                             40);
 818                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 819                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 820                             40);
 821         }
 822         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 823 }
 824
 825 #define PHY_BUSY_LOOPS  5000
 826
 827 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 828 {
 829         u32 frame_val;
 830         unsigned int loops;
 831         int ret;
 832
 833         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 834                 tw32_f(MAC_MI_MODE,
 835                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 836                 udelay(80);
 837         }
 838
 839         *val = 0x0;
 840
 841         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 842                       MI_COM_PHY_ADDR_MASK);
 843         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 844                       MI_COM_REG_ADDR_MASK);
 845         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 846
 847         tw32_f(MAC_MI_COM, frame_val);
 848
 849         loops = PHY_BUSY_LOOPS;
 850         while (loops != 0) {
 851                 udelay(10);
 852                 frame_val = tr32(MAC_MI_COM);
 853
 854                 if ((frame_val & MI_COM_BUSY) == 0) {
 855                         udelay(5);
 856                         frame_val = tr32(MAC_MI_COM);
 857                         break;
 858                 }
 859                 loops -= 1;
 860         }
 861
 862         ret = -EBUSY;
 863         if (loops != 0) {
 864                 *val = frame_val & MI_COM_DATA_MASK;
 865                 ret = 0;
 866         }
 867
 868         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 869                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 870                 udelay(80);
 871         }
 872
 873         return ret;
 874 }
 875
 876 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 877 {
 878         u32 frame_val;
 879         unsigned int loops;
 880         int ret;
 881
 882         if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
 883             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 884                 return 0;
 885
 886         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 887                 tw32_f(MAC_MI_MODE,
 888                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 889                 udelay(80);
 890         }
 891
 892         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 893                       MI_COM_PHY_ADDR_MASK);
 894         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 895                       MI_COM_REG_ADDR_MASK);
 896         frame_val |= (val & MI_COM_DATA_MASK);
 897         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 898
 899         tw32_f(MAC_MI_COM, frame_val);
 900
 901         loops = PHY_BUSY_LOOPS;
 902         while (loops != 0) {
 903                 udelay(10);
 904                 frame_val = tr32(MAC_MI_COM);
 905                 if ((frame_val & MI_COM_BUSY) == 0) {
 906                         udelay(5);
 907                         frame_val = tr32(MAC_MI_COM);
 908                         break;
 909                 }
 910                 loops -= 1;
 911         }
 912
 913         ret = -EBUSY;
 914         if (loops != 0)
 915                 ret = 0;
 916
 917         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 918                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 919                 udelay(80);
 920         }
 921
 922         return ret;
 923 }
 924
 925 static int tg3_bmcr_reset(struct tg3 *tp)
 926 {
 927         u32 phy_control;
 928         int limit, err;
 929
 930         /* OK, reset it, and poll the BMCR_RESET bit until it
 931          * clears or we time out.
 932          */
 933         phy_control = BMCR_RESET;
 934         err = tg3_writephy(tp, MII_BMCR, phy_control);
 935         if (err != 0)
 936                 return -EBUSY;
 937
 938         limit = 5000;
 939         while (limit--) {
 940                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 941                 if (err != 0)
 942                         return -EBUSY;
 943
 944                 if ((phy_control & BMCR_RESET) == 0) {
 945                         udelay(40);
 946                         break;
 947                 }
 948                 udelay(10);
 949         }
 950         if (limit < 0)
 951                 return -EBUSY;
 952
 953         return 0;
 954 }
 955
 956 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 957 {
 958         struct tg3 *tp = bp->priv;
 959         u32 val;
 960
 961         spin_lock_bh(&tp->lock);
 962
 963         if (tg3_readphy(tp, reg, &val))
 964                 val = -EIO;
 965
 966         spin_unlock_bh(&tp->lock);
 967
 968         return val;
 969 }
 970
 971 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 972 {
 973         struct tg3 *tp = bp->priv;
 974         u32 ret = 0;
 975
 976         spin_lock_bh(&tp->lock);
 977
 978         if (tg3_writephy(tp, reg, val))
 979                 ret = -EIO;
 980
 981         spin_unlock_bh(&tp->lock);
 982
 983         return ret;
 984 }
 985
 986 static int tg3_mdio_reset(struct mii_bus *bp)
 987 {
 988         return 0;
 989 }
 990
 991 static void tg3_mdio_config_5785(struct tg3 *tp)
 992 {
 993         u32 val;
 994         struct phy_device *phydev;
 995
 996         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
 997         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 998         case PHY_ID_BCM50610:
 999         case PHY_ID_BCM50610M:
1000                 val = MAC_PHYCFG2_50610_LED_MODES;
1001                 break;
1002         case PHY_ID_BCMAC131:
1003                 val = MAC_PHYCFG2_AC131_LED_MODES;
1004                 break;
1005         case PHY_ID_RTL8211C:
1006                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1007                 break;
1008         case PHY_ID_RTL8201E:
1009                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1010                 break;
1011         default:
1012                 return;
1013         }
1014
1015         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1016                 tw32(MAC_PHYCFG2, val);
1017
1018                 val = tr32(MAC_PHYCFG1);
1019                 val &= ~(MAC_PHYCFG1_RGMII_INT |
1020                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1021                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1022                 tw32(MAC_PHYCFG1, val);
1023
1024                 return;
1025         }
1026
1027         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
1028                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1029                        MAC_PHYCFG2_FMODE_MASK_MASK |
1030                        MAC_PHYCFG2_GMODE_MASK_MASK |
1031                        MAC_PHYCFG2_ACT_MASK_MASK   |
1032                        MAC_PHYCFG2_QUAL_MASK_MASK |
1033                        MAC_PHYCFG2_INBAND_ENABLE;
1034
1035         tw32(MAC_PHYCFG2, val);
1036
1037         val = tr32(MAC_PHYCFG1);
1038         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1039                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1040         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1041                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1042                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1043                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1044                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1045         }
1046         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1047                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1048         tw32(MAC_PHYCFG1, val);
1049
1050         val = tr32(MAC_EXT_RGMII_MODE);
1051         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1052                  MAC_RGMII_MODE_RX_QUALITY |
1053                  MAC_RGMII_MODE_RX_ACTIVITY |
1054                  MAC_RGMII_MODE_RX_ENG_DET |
1055                  MAC_RGMII_MODE_TX_ENABLE |
1056                  MAC_RGMII_MODE_TX_LOWPWR |
1057                  MAC_RGMII_MODE_TX_RESET);
1058         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1059                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1060                         val |= MAC_RGMII_MODE_RX_INT_B |
1061                                MAC_RGMII_MODE_RX_QUALITY |
1062                                MAC_RGMII_MODE_RX_ACTIVITY |
1063                                MAC_RGMII_MODE_RX_ENG_DET;
1064                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1065                         val |= MAC_RGMII_MODE_TX_ENABLE |
1066                                MAC_RGMII_MODE_TX_LOWPWR |
1067                                MAC_RGMII_MODE_TX_RESET;
1068         }
1069         tw32(MAC_EXT_RGMII_MODE, val);
1070 }
1071
1072 static void tg3_mdio_start(struct tg3 *tp)
1073 {
1074         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1075         tw32_f(MAC_MI_MODE, tp->mi_mode);
1076         udelay(80);
1077
1078         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1079             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1080                 tg3_mdio_config_5785(tp);
1081 }
1082
1083 static int tg3_mdio_init(struct tg3 *tp)
1084 {
1085         int i;
1086         u32 reg;
1087         struct phy_device *phydev;
1088
1089         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1090             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
1091                 u32 is_serdes;
1092
1093                 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1094
1095                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1096                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1097                 else
1098                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1099                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1100                 if (is_serdes)
1101                         tp->phy_addr += 7;
1102         } else
1103                 tp->phy_addr = TG3_PHY_MII_ADDR;
1104
1105         tg3_mdio_start(tp);
1106
1107         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1108             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1109                 return 0;
1110
1111         tp->mdio_bus = mdiobus_alloc();
1112         if (tp->mdio_bus == NULL)
1113                 return -ENOMEM;
1114
1115         tp->mdio_bus->name     = "tg3 mdio bus";
1116         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1117                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1118         tp->mdio_bus->priv     = tp;
1119         tp->mdio_bus->parent   = &tp->pdev->dev;
1120         tp->mdio_bus->read     = &tg3_mdio_read;
1121         tp->mdio_bus->write    = &tg3_mdio_write;
1122         tp->mdio_bus->reset    = &tg3_mdio_reset;
1123         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1124         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1125
1126         for (i = 0; i < PHY_MAX_ADDR; i++)
1127                 tp->mdio_bus->irq[i] = PHY_POLL;
1128
1129         /* The bus registration will look for all the PHYs on the mdio bus.
1130          * Unfortunately, it does not ensure the PHY is powered up before
1131          * accessing the PHY ID registers.  A chip reset is the
1132          * quickest way to bring the device back to an operational state..
1133          */
1134         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1135                 tg3_bmcr_reset(tp);
1136
1137         i = mdiobus_register(tp->mdio_bus);
1138         if (i) {
1139                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1140                 mdiobus_free(tp->mdio_bus);
1141                 return i;
1142         }
1143
1144         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1145
1146         if (!phydev || !phydev->drv) {
1147                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1148                 mdiobus_unregister(tp->mdio_bus);
1149                 mdiobus_free(tp->mdio_bus);
1150                 return -ENODEV;
1151         }
1152
1153         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1154         case PHY_ID_BCM57780:
1155                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1156                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1157                 break;
1158         case PHY_ID_BCM50610:
1159         case PHY_ID_BCM50610M:
1160                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1161                                      PHY_BRCM_RX_REFCLK_UNUSED |
1162                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1163                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1164                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1165                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1166                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1167                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1168                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1169                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1170                 /* fallthru */
1171         case PHY_ID_RTL8211C:
1172                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1173                 break;
1174         case PHY_ID_RTL8201E:
1175         case PHY_ID_BCMAC131:
1176                 phydev->interface = PHY_INTERFACE_MODE_MII;
1177                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1178                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1179                 break;
1180         }
1181
1182         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1183
1184         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1185                 tg3_mdio_config_5785(tp);
1186
1187         return 0;
1188 }
1189
1190 static void tg3_mdio_fini(struct tg3 *tp)
1191 {
1192         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1193                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1194                 mdiobus_unregister(tp->mdio_bus);
1195                 mdiobus_free(tp->mdio_bus);
1196         }
1197 }
1198
1199 /* tp->lock is held. */
1200 static inline void tg3_generate_fw_event(struct tg3 *tp)
1201 {
1202         u32 val;
1203
1204         val = tr32(GRC_RX_CPU_EVENT);
1205         val |= GRC_RX_CPU_DRIVER_EVENT;
1206         tw32_f(GRC_RX_CPU_EVENT, val);
1207
1208         tp->last_event_jiffies = jiffies;
1209 }
1210
1211 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1212
1213 /* tp->lock is held. */
1214 static void tg3_wait_for_event_ack(struct tg3 *tp)
1215 {
1216         int i;
1217         unsigned int delay_cnt;
1218         long time_remain;
1219
1220         /* If enough time has passed, no wait is necessary. */
1221         time_remain = (long)(tp->last_event_jiffies + 1 +
1222                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1223                       (long)jiffies;
1224         if (time_remain < 0)
1225                 return;
1226
1227         /* Check if we can shorten the wait time. */
1228         delay_cnt = jiffies_to_usecs(time_remain);
1229         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1230                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1231         delay_cnt = (delay_cnt >> 3) + 1;
1232
1233         for (i = 0; i < delay_cnt; i++) {
1234                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1235                         break;
1236                 udelay(8);
1237         }
1238 }
1239
1240 /* tp->lock is held. */
1241 static void tg3_ump_link_report(struct tg3 *tp)
1242 {
1243         u32 reg;
1244         u32 val;
1245
1246         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1247             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1248                 return;
1249
1250         tg3_wait_for_event_ack(tp);
1251
1252         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1253
1254         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1255
1256         val = 0;
1257         if (!tg3_readphy(tp, MII_BMCR, &reg))
1258                 val = reg << 16;
1259         if (!tg3_readphy(tp, MII_BMSR, &reg))
1260                 val |= (reg & 0xffff);
1261         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1262
1263         val = 0;
1264         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1265                 val = reg << 16;
1266         if (!tg3_readphy(tp, MII_LPA, &reg))
1267                 val |= (reg & 0xffff);
1268         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1269
1270         val = 0;
1271         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1272                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1273                         val = reg << 16;
1274                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1275                         val |= (reg & 0xffff);
1276         }
1277         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1278
1279         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1280                 val = reg << 16;
1281         else
1282                 val = 0;
1283         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1284
1285         tg3_generate_fw_event(tp);
1286 }
1287
1288 static void tg3_link_report(struct tg3 *tp)
1289 {
1290         if (!netif_carrier_ok(tp->dev)) {
1291                 netif_info(tp, link, tp->dev, "Link is down\n");
1292                 tg3_ump_link_report(tp);
1293         } else if (netif_msg_link(tp)) {
1294                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1295                             (tp->link_config.active_speed == SPEED_1000 ?
1296                              1000 :
1297                              (tp->link_config.active_speed == SPEED_100 ?
1298                               100 : 10)),
1299                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1300                              "full" : "half"));
1301
1302                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1303                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1304                             "on" : "off",
1305                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1306                             "on" : "off");
1307                 tg3_ump_link_report(tp);
1308         }
1309 }
1310
1311 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1312 {
1313         u16 miireg;
1314
1315         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1316                 miireg = ADVERTISE_PAUSE_CAP;
1317         else if (flow_ctrl & FLOW_CTRL_TX)
1318                 miireg = ADVERTISE_PAUSE_ASYM;
1319         else if (flow_ctrl & FLOW_CTRL_RX)
1320                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1321         else
1322                 miireg = 0;
1323
1324         return miireg;
1325 }
1326
1327 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1328 {
1329         u16 miireg;
1330
1331         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1332                 miireg = ADVERTISE_1000XPAUSE;
1333         else if (flow_ctrl & FLOW_CTRL_TX)
1334                 miireg = ADVERTISE_1000XPSE_ASYM;
1335         else if (flow_ctrl & FLOW_CTRL_RX)
1336                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1337         else
1338                 miireg = 0;
1339
1340         return miireg;
1341 }
1342
1343 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1344 {
1345         u8 cap = 0;
1346
1347         if (lcladv & ADVERTISE_1000XPAUSE) {
1348                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1349                         if (rmtadv & LPA_1000XPAUSE)
1350                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1351                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1352                                 cap = FLOW_CTRL_RX;
1353                 } else {
1354                         if (rmtadv & LPA_1000XPAUSE)
1355                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1356                 }
1357         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1358                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1359                         cap = FLOW_CTRL_TX;
1360         }
1361
1362         return cap;
1363 }
1364
1365 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1366 {
1367         u8 autoneg;
1368         u8 flowctrl = 0;
1369         u32 old_rx_mode = tp->rx_mode;
1370         u32 old_tx_mode = tp->tx_mode;
1371
1372         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1373                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1374         else
1375                 autoneg = tp->link_config.autoneg;
1376
1377         if (autoneg == AUTONEG_ENABLE &&
1378             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1379                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1380                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1381                 else
1382                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1383         } else
1384                 flowctrl = tp->link_config.flowctrl;
1385
1386         tp->link_config.active_flowctrl = flowctrl;
1387
1388         if (flowctrl & FLOW_CTRL_RX)
1389                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1390         else
1391                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1392
1393         if (old_rx_mode != tp->rx_mode)
1394                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1395
1396         if (flowctrl & FLOW_CTRL_TX)
1397                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1398         else
1399                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1400
1401         if (old_tx_mode != tp->tx_mode)
1402                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1403 }
1404
1405 static void tg3_adjust_link(struct net_device *dev)
1406 {
1407         u8 oldflowctrl, linkmesg = 0;
1408         u32 mac_mode, lcl_adv, rmt_adv;
1409         struct tg3 *tp = netdev_priv(dev);
1410         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1411
1412         spin_lock_bh(&tp->lock);
1413
1414         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1415                                     MAC_MODE_HALF_DUPLEX);
1416
1417         oldflowctrl = tp->link_config.active_flowctrl;
1418
1419         if (phydev->link) {
1420                 lcl_adv = 0;
1421                 rmt_adv = 0;
1422
1423                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1424                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1425                 else if (phydev->speed == SPEED_1000 ||
1426                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1427                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1428                 else
1429                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1430
1431                 if (phydev->duplex == DUPLEX_HALF)
1432                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1433                 else {
1434                         lcl_adv = tg3_advert_flowctrl_1000T(
1435                                   tp->link_config.flowctrl);
1436
1437                         if (phydev->pause)
1438                                 rmt_adv = LPA_PAUSE_CAP;
1439                         if (phydev->asym_pause)
1440                                 rmt_adv |= LPA_PAUSE_ASYM;
1441                 }
1442
1443                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1444         } else
1445                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1446
1447         if (mac_mode != tp->mac_mode) {
1448                 tp->mac_mode = mac_mode;
1449                 tw32_f(MAC_MODE, tp->mac_mode);
1450                 udelay(40);
1451         }
1452
1453         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1454                 if (phydev->speed == SPEED_10)
1455                         tw32(MAC_MI_STAT,
1456                              MAC_MI_STAT_10MBPS_MODE |
1457                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1458                 else
1459                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1460         }
1461
1462         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1463                 tw32(MAC_TX_LENGTHS,
1464                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1465                       (6 << TX_LENGTHS_IPG_SHIFT) |
1466                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1467         else
1468                 tw32(MAC_TX_LENGTHS,
1469                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1470                       (6 << TX_LENGTHS_IPG_SHIFT) |
1471                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1472
1473         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1474             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1475             phydev->speed != tp->link_config.active_speed ||
1476             phydev->duplex != tp->link_config.active_duplex ||
1477             oldflowctrl != tp->link_config.active_flowctrl)
1478                 linkmesg = 1;
1479
1480         tp->link_config.active_speed = phydev->speed;
1481         tp->link_config.active_duplex = phydev->duplex;
1482
1483         spin_unlock_bh(&tp->lock);
1484
1485         if (linkmesg)
1486                 tg3_link_report(tp);
1487 }
1488
1489 static int tg3_phy_init(struct tg3 *tp)
1490 {
1491         struct phy_device *phydev;
1492
1493         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1494                 return 0;
1495
1496         /* Bring the PHY back to a known state. */
1497         tg3_bmcr_reset(tp);
1498
1499         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1500
1501         /* Attach the MAC to the PHY. */
1502         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1503                              phydev->dev_flags, phydev->interface);
1504         if (IS_ERR(phydev)) {
1505                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1506                 return PTR_ERR(phydev);
1507         }
1508
1509         /* Mask with MAC supported features. */
1510         switch (phydev->interface) {
1511         case PHY_INTERFACE_MODE_GMII:
1512         case PHY_INTERFACE_MODE_RGMII:
1513                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1514                         phydev->supported &= (PHY_GBIT_FEATURES |
1515                                               SUPPORTED_Pause |
1516                                               SUPPORTED_Asym_Pause);
1517                         break;
1518                 }
1519                 /* fallthru */
1520         case PHY_INTERFACE_MODE_MII:
1521                 phydev->supported &= (PHY_BASIC_FEATURES |
1522                                       SUPPORTED_Pause |
1523                                       SUPPORTED_Asym_Pause);
1524                 break;
1525         default:
1526                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1527                 return -EINVAL;
1528         }
1529
1530         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1531
1532         phydev->advertising = phydev->supported;
1533
1534         return 0;
1535 }
1536
1537 static void tg3_phy_start(struct tg3 *tp)
1538 {
1539         struct phy_device *phydev;
1540
1541         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1542                 return;
1543
1544         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1545
1546         if (tp->link_config.phy_is_low_power) {
1547                 tp->link_config.phy_is_low_power = 0;
1548                 phydev->speed = tp->link_config.orig_speed;
1549                 phydev->duplex = tp->link_config.orig_duplex;
1550                 phydev->autoneg = tp->link_config.orig_autoneg;
1551                 phydev->advertising = tp->link_config.orig_advertising;
1552         }
1553
1554         phy_start(phydev);
1555
1556         phy_start_aneg(phydev);
1557 }
1558
1559 static void tg3_phy_stop(struct tg3 *tp)
1560 {
1561         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1562                 return;
1563
1564         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1565 }
1566
1567 static void tg3_phy_fini(struct tg3 *tp)
1568 {
1569         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1570                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1571                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1572         }
1573 }
1574
1575 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1576 {
1577         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1578         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1579 }
1580
1581 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1582 {
1583         u32 phytest;
1584
1585         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1586                 u32 phy;
1587
1588                 tg3_writephy(tp, MII_TG3_FET_TEST,
1589                              phytest | MII_TG3_FET_SHADOW_EN);
1590                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1591                         if (enable)
1592                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1593                         else
1594                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1595                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1596                 }
1597                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1598         }
1599 }
1600
1601 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1602 {
1603         u32 reg;
1604
1605         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1606             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1607               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1608              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1609                 return;
1610
1611         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1612                 tg3_phy_fet_toggle_apd(tp, enable);
1613                 return;
1614         }
1615
1616         reg = MII_TG3_MISC_SHDW_WREN |
1617               MII_TG3_MISC_SHDW_SCR5_SEL |
1618               MII_TG3_MISC_SHDW_SCR5_LPED |
1619               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1620               MII_TG3_MISC_SHDW_SCR5_SDTL |
1621               MII_TG3_MISC_SHDW_SCR5_C125OE;
1622         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1623                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1624
1625         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1626
1627
1628         reg = MII_TG3_MISC_SHDW_WREN |
1629               MII_TG3_MISC_SHDW_APD_SEL |
1630               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1631         if (enable)
1632                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1633
1634         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1635 }
1636
1637 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1638 {
1639         u32 phy;
1640
1641         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1642             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1643                 return;
1644
1645         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1646                 u32 ephy;
1647
1648                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1649                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1650
1651                         tg3_writephy(tp, MII_TG3_FET_TEST,
1652                                      ephy | MII_TG3_FET_SHADOW_EN);
1653                         if (!tg3_readphy(tp, reg, &phy)) {
1654                                 if (enable)
1655                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1656                                 else
1657                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1658                                 tg3_writephy(tp, reg, phy);
1659                         }
1660                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1661                 }
1662         } else {
1663                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1664                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1665                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1666                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1667                         if (enable)
1668                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1669                         else
1670                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1671                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1672                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1673                 }
1674         }
1675 }
1676
1677 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1678 {
1679         u32 val;
1680
1681         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1682                 return;
1683
1684         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1685             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1686                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1687                              (val | (1 << 15) | (1 << 4)));
1688 }
1689
1690 static void tg3_phy_apply_otp(struct tg3 *tp)
1691 {
1692         u32 otp, phy;
1693
1694         if (!tp->phy_otp)
1695                 return;
1696
1697         otp = tp->phy_otp;
1698
1699         /* Enable SM_DSP clock and tx 6dB coding. */
1700         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1701               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1702               MII_TG3_AUXCTL_ACTL_TX_6DB;
1703         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1704
1705         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1706         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1707         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1708
1709         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1710               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1711         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1712
1713         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1714         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1715         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1716
1717         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1718         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1719
1720         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1721         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1722
1723         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1724               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1725         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1726
1727         /* Turn off SM_DSP clock. */
1728         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1729               MII_TG3_AUXCTL_ACTL_TX_6DB;
1730         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1731 }
1732
1733 static int tg3_wait_macro_done(struct tg3 *tp)
1734 {
1735         int limit = 100;
1736
1737         while (limit--) {
1738                 u32 tmp32;
1739
1740                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1741                         if ((tmp32 & 0x1000) == 0)
1742                                 break;
1743                 }
1744         }
1745         if (limit < 0)
1746                 return -EBUSY;
1747
1748         return 0;
1749 }
1750
1751 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1752 {
1753         static const u32 test_pat[4][6] = {
1754         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1755         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1756         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1757         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1758         };
1759         int chan;
1760
1761         for (chan = 0; chan < 4; chan++) {
1762                 int i;
1763
1764                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1765                              (chan * 0x2000) | 0x0200);
1766                 tg3_writephy(tp, 0x16, 0x0002);
1767
1768                 for (i = 0; i < 6; i++)
1769                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1770                                      test_pat[chan][i]);
1771
1772                 tg3_writephy(tp, 0x16, 0x0202);
1773                 if (tg3_wait_macro_done(tp)) {
1774                         *resetp = 1;
1775                         return -EBUSY;
1776                 }
1777
1778                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1779                              (chan * 0x2000) | 0x0200);
1780                 tg3_writephy(tp, 0x16, 0x0082);
1781                 if (tg3_wait_macro_done(tp)) {
1782                         *resetp = 1;
1783                         return -EBUSY;
1784                 }
1785
1786                 tg3_writephy(tp, 0x16, 0x0802);
1787                 if (tg3_wait_macro_done(tp)) {
1788                         *resetp = 1;
1789                         return -EBUSY;
1790                 }
1791
1792                 for (i = 0; i < 6; i += 2) {
1793                         u32 low, high;
1794
1795                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1796                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1797                             tg3_wait_macro_done(tp)) {
1798                                 *resetp = 1;
1799                                 return -EBUSY;
1800                         }
1801                         low &= 0x7fff;
1802                         high &= 0x000f;
1803                         if (low != test_pat[chan][i] ||
1804                             high != test_pat[chan][i+1]) {
1805                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1806                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1807                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1808
1809                                 return -EBUSY;
1810                         }
1811                 }
1812         }
1813
1814         return 0;
1815 }
1816
1817 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1818 {
1819         int chan;
1820
1821         for (chan = 0; chan < 4; chan++) {
1822                 int i;
1823
1824                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1825                              (chan * 0x2000) | 0x0200);
1826                 tg3_writephy(tp, 0x16, 0x0002);
1827                 for (i = 0; i < 6; i++)
1828                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1829                 tg3_writephy(tp, 0x16, 0x0202);
1830                 if (tg3_wait_macro_done(tp))
1831                         return -EBUSY;
1832         }
1833
1834         return 0;
1835 }
1836
1837 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1838 {
1839         u32 reg32, phy9_orig;
1840         int retries, do_phy_reset, err;
1841
1842         retries = 10;
1843         do_phy_reset = 1;
1844         do {
1845                 if (do_phy_reset) {
1846                         err = tg3_bmcr_reset(tp);
1847                         if (err)
1848                                 return err;
1849                         do_phy_reset = 0;
1850                 }
1851
1852                 /* Disable transmitter and interrupt.  */
1853                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1854                         continue;
1855
1856                 reg32 |= 0x3000;
1857                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1858
1859                 /* Set full-duplex, 1000 mbps.  */
1860                 tg3_writephy(tp, MII_BMCR,
1861                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1862
1863                 /* Set to master mode.  */
1864                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1865                         continue;
1866
1867                 tg3_writephy(tp, MII_TG3_CTRL,
1868                              (MII_TG3_CTRL_AS_MASTER |
1869                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1870
1871                 /* Enable SM_DSP_CLOCK and 6dB.  */
1872                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1873
1874                 /* Block the PHY control access.  */
1875                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1876                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1877
1878                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1879                 if (!err)
1880                         break;
1881         } while (--retries);
1882
1883         err = tg3_phy_reset_chanpat(tp);
1884         if (err)
1885                 return err;
1886
1887         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1888         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1889
1890         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1891         tg3_writephy(tp, 0x16, 0x0000);
1892
1893         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1894             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1895                 /* Set Extended packet length bit for jumbo frames */
1896                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1897         } else {
1898                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1899         }
1900
1901         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1902
1903         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1904                 reg32 &= ~0x3000;
1905                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1906         } else if (!err)
1907                 err = -EBUSY;
1908
1909         return err;
1910 }
1911
1912 /* This will reset the tigon3 PHY if there is no valid
1913  * link unless the FORCE argument is non-zero.
1914  */
1915 static int tg3_phy_reset(struct tg3 *tp)
1916 {
1917         u32 cpmuctrl;
1918         u32 phy_status;
1919         int err;
1920
1921         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1922                 u32 val;
1923
1924                 val = tr32(GRC_MISC_CFG);
1925                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1926                 udelay(40);
1927         }
1928         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1929         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1930         if (err != 0)
1931                 return -EBUSY;
1932
1933         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1934                 netif_carrier_off(tp->dev);
1935                 tg3_link_report(tp);
1936         }
1937
1938         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1939             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1940             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1941                 err = tg3_phy_reset_5703_4_5(tp);
1942                 if (err)
1943                         return err;
1944                 goto out;
1945         }
1946
1947         cpmuctrl = 0;
1948         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1949             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1950                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1951                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1952                         tw32(TG3_CPMU_CTRL,
1953                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1954         }
1955
1956         err = tg3_bmcr_reset(tp);
1957         if (err)
1958                 return err;
1959
1960         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1961                 u32 phy;
1962
1963                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1964                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1965
1966                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1967         }
1968
1969         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1970             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1971                 u32 val;
1972
1973                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1974                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1975                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1976                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1977                         udelay(40);
1978                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1979                 }
1980         }
1981
1982         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1983              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1984             (tp->tg3_flags2 & TG3_FLG2_MII_SERDES))
1985                 return 0;
1986
1987         tg3_phy_apply_otp(tp);
1988
1989         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1990                 tg3_phy_toggle_apd(tp, true);
1991         else
1992                 tg3_phy_toggle_apd(tp, false);
1993
1994 out:
1995         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1996                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1997                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1998                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1999                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2000                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
2001                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2002         }
2003         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
2004                 tg3_writephy(tp, 0x1c, 0x8d68);
2005                 tg3_writephy(tp, 0x1c, 0x8d68);
2006         }
2007         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
2008                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2009                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2010                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
2011                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2012                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
2013                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
2014                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
2015                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2016         } else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
2017                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2018                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2019                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
2020                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2021                         tg3_writephy(tp, MII_TG3_TEST1,
2022                                      MII_TG3_TEST1_TRIM_EN | 0x4);
2023                 } else
2024                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2025                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2026         }
2027         /* Set Extended packet length bit (bit 14) on all chips that */
2028         /* support jumbo frames */
2029         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2030                 /* Cannot do read-modify-write on 5401 */
2031                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2032         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2033                 u32 phy_reg;
2034
2035                 /* Set bit 14 with read-modify-write to preserve other bits */
2036                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2037                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
2038                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
2039         }
2040
2041         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2042          * jumbo frames transmission.
2043          */
2044         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2045                 u32 phy_reg;
2046
2047                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
2048                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2049                                      phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2050         }
2051
2052         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2053                 /* adjust output voltage */
2054                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2055         }
2056
2057         tg3_phy_toggle_automdix(tp, 1);
2058         tg3_phy_set_wirespeed(tp);
2059         return 0;
2060 }
2061
2062 static void tg3_frob_aux_power(struct tg3 *tp)
2063 {
2064         struct tg3 *tp_peer = tp;
2065
2066         /* The GPIOs do something completely different on 57765. */
2067         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2068             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2069             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2070                 return;
2071
2072         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2073             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2074             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2075                 struct net_device *dev_peer;
2076
2077                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2078                 /* remove_one() may have been run on the peer. */
2079                 if (!dev_peer)
2080                         tp_peer = tp;
2081                 else
2082                         tp_peer = netdev_priv(dev_peer);
2083         }
2084
2085         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2086             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2087             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2088             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2089                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2090                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2091                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2092                                     (GRC_LCLCTRL_GPIO_OE0 |
2093                                      GRC_LCLCTRL_GPIO_OE1 |
2094                                      GRC_LCLCTRL_GPIO_OE2 |
2095                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2096                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2097                                     100);
2098                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2099                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2100                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2101                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2102                                              GRC_LCLCTRL_GPIO_OE1 |
2103                                              GRC_LCLCTRL_GPIO_OE2 |
2104                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2105                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2106                                              tp->grc_local_ctrl;
2107                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2108
2109                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2110                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2111
2112                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2113                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2114                 } else {
2115                         u32 no_gpio2;
2116                         u32 grc_local_ctrl = 0;
2117
2118                         if (tp_peer != tp &&
2119                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2120                                 return;
2121
2122                         /* Workaround to prevent overdrawing Amps. */
2123                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2124                             ASIC_REV_5714) {
2125                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2126                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2127                                             grc_local_ctrl, 100);
2128                         }
2129
2130                         /* On 5753 and variants, GPIO2 cannot be used. */
2131                         no_gpio2 = tp->nic_sram_data_cfg &
2132                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2133
2134                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2135                                          GRC_LCLCTRL_GPIO_OE1 |
2136                                          GRC_LCLCTRL_GPIO_OE2 |
2137                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2138                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2139                         if (no_gpio2) {
2140                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2141                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2142                         }
2143                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2144                                                     grc_local_ctrl, 100);
2145
2146                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2147
2148                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2149                                                     grc_local_ctrl, 100);
2150
2151                         if (!no_gpio2) {
2152                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2153                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2154                                             grc_local_ctrl, 100);
2155                         }
2156                 }
2157         } else {
2158                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2159                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2160                         if (tp_peer != tp &&
2161                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2162                                 return;
2163
2164                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2165                                     (GRC_LCLCTRL_GPIO_OE1 |
2166                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2167
2168                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2169                                     GRC_LCLCTRL_GPIO_OE1, 100);
2170
2171                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2172                                     (GRC_LCLCTRL_GPIO_OE1 |
2173                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2174                 }
2175         }
2176 }
2177
2178 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2179 {
2180         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2181                 return 1;
2182         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2183                 if (speed != SPEED_10)
2184                         return 1;
2185         } else if (speed == SPEED_10)
2186                 return 1;
2187
2188         return 0;
2189 }
2190
2191 static int tg3_setup_phy(struct tg3 *, int);
2192
2193 #define RESET_KIND_SHUTDOWN     0
2194 #define RESET_KIND_INIT         1
2195 #define RESET_KIND_SUSPEND      2
2196
2197 static void tg3_write_sig_post_reset(struct tg3 *, int);
2198 static int tg3_halt_cpu(struct tg3 *, u32);
2199
2200 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2201 {
2202         u32 val;
2203
2204         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2205                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2206                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2207                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2208
2209                         sg_dig_ctrl |=
2210                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2211                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2212                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2213                 }
2214                 return;
2215         }
2216
2217         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2218                 tg3_bmcr_reset(tp);
2219                 val = tr32(GRC_MISC_CFG);
2220                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2221                 udelay(40);
2222                 return;
2223         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2224                 u32 phytest;
2225                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2226                         u32 phy;
2227
2228                         tg3_writephy(tp, MII_ADVERTISE, 0);
2229                         tg3_writephy(tp, MII_BMCR,
2230                                      BMCR_ANENABLE | BMCR_ANRESTART);
2231
2232                         tg3_writephy(tp, MII_TG3_FET_TEST,
2233                                      phytest | MII_TG3_FET_SHADOW_EN);
2234                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2235                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2236                                 tg3_writephy(tp,
2237                                              MII_TG3_FET_SHDW_AUXMODE4,
2238                                              phy);
2239                         }
2240                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2241                 }
2242                 return;
2243         } else if (do_low_power) {
2244                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2245                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2246
2247                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2248                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2249                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2250                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2251                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2252         }
2253
2254         /* The PHY should not be powered down on some chips because
2255          * of bugs.
2256          */
2257         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2258             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2259             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2260              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2261                 return;
2262
2263         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2264             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2265                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2266                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2267                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2268                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2269         }
2270
2271         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2272 }
2273
2274 /* tp->lock is held. */
2275 static int tg3_nvram_lock(struct tg3 *tp)
2276 {
2277         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2278                 int i;
2279
2280                 if (tp->nvram_lock_cnt == 0) {
2281                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2282                         for (i = 0; i < 8000; i++) {
2283                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2284                                         break;
2285                                 udelay(20);
2286                         }
2287                         if (i == 8000) {
2288                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2289                                 return -ENODEV;
2290                         }
2291                 }
2292                 tp->nvram_lock_cnt++;
2293         }
2294         return 0;
2295 }
2296
2297 /* tp->lock is held. */
2298 static void tg3_nvram_unlock(struct tg3 *tp)
2299 {
2300         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2301                 if (tp->nvram_lock_cnt > 0)
2302                         tp->nvram_lock_cnt--;
2303                 if (tp->nvram_lock_cnt == 0)
2304                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2305         }
2306 }
2307
2308 /* tp->lock is held. */
2309 static void tg3_enable_nvram_access(struct tg3 *tp)
2310 {
2311         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2312             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2313                 u32 nvaccess = tr32(NVRAM_ACCESS);
2314
2315                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2316         }
2317 }
2318
2319 /* tp->lock is held. */
2320 static void tg3_disable_nvram_access(struct tg3 *tp)
2321 {
2322         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2323             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2324                 u32 nvaccess = tr32(NVRAM_ACCESS);
2325
2326                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2327         }
2328 }
2329
2330 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2331                                         u32 offset, u32 *val)
2332 {
2333         u32 tmp;
2334         int i;
2335
2336         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2337                 return -EINVAL;
2338
2339         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2340                                         EEPROM_ADDR_DEVID_MASK |
2341                                         EEPROM_ADDR_READ);
2342         tw32(GRC_EEPROM_ADDR,
2343              tmp |
2344              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2345              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2346               EEPROM_ADDR_ADDR_MASK) |
2347              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2348
2349         for (i = 0; i < 1000; i++) {
2350                 tmp = tr32(GRC_EEPROM_ADDR);
2351
2352                 if (tmp & EEPROM_ADDR_COMPLETE)
2353                         break;
2354                 msleep(1);
2355         }
2356         if (!(tmp & EEPROM_ADDR_COMPLETE))
2357                 return -EBUSY;
2358
2359         tmp = tr32(GRC_EEPROM_DATA);
2360
2361         /*
2362          * The data will always be opposite the native endian
2363          * format.  Perform a blind byteswap to compensate.
2364          */
2365         *val = swab32(tmp);
2366
2367         return 0;
2368 }
2369
2370 #define NVRAM_CMD_TIMEOUT 10000
2371
2372 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2373 {
2374         int i;
2375
2376         tw32(NVRAM_CMD, nvram_cmd);
2377         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2378                 udelay(10);
2379                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2380                         udelay(10);
2381                         break;
2382                 }
2383         }
2384
2385         if (i == NVRAM_CMD_TIMEOUT)
2386                 return -EBUSY;
2387
2388         return 0;
2389 }
2390
2391 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2392 {
2393         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2394             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2395             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2396            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2397             (tp->nvram_jedecnum == JEDEC_ATMEL))
2398
2399                 addr = ((addr / tp->nvram_pagesize) <<
2400                         ATMEL_AT45DB0X1B_PAGE_POS) +
2401                        (addr % tp->nvram_pagesize);
2402
2403         return addr;
2404 }
2405
2406 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2407 {
2408         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2409             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2410             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2411            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2412             (tp->nvram_jedecnum == JEDEC_ATMEL))
2413
2414                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2415                         tp->nvram_pagesize) +
2416                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2417
2418         return addr;
2419 }
2420
2421 /* NOTE: Data read in from NVRAM is byteswapped according to
2422  * the byteswapping settings for all other register accesses.
2423  * tg3 devices are BE devices, so on a BE machine, the data
2424  * returned will be exactly as it is seen in NVRAM.  On a LE
2425  * machine, the 32-bit value will be byteswapped.
2426  */
2427 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2428 {
2429         int ret;
2430
2431         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2432                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2433
2434         offset = tg3_nvram_phys_addr(tp, offset);
2435
2436         if (offset > NVRAM_ADDR_MSK)
2437                 return -EINVAL;
2438
2439         ret = tg3_nvram_lock(tp);
2440         if (ret)
2441                 return ret;
2442
2443         tg3_enable_nvram_access(tp);
2444
2445         tw32(NVRAM_ADDR, offset);
2446         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2447                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2448
2449         if (ret == 0)
2450                 *val = tr32(NVRAM_RDDATA);
2451
2452         tg3_disable_nvram_access(tp);
2453
2454         tg3_nvram_unlock(tp);
2455
2456         return ret;
2457 }
2458
2459 /* Ensures NVRAM data is in bytestream format. */
2460 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2461 {
2462         u32 v;
2463         int res = tg3_nvram_read(tp, offset, &v);
2464         if (!res)
2465                 *val = cpu_to_be32(v);
2466         return res;
2467 }
2468
2469 /* tp->lock is held. */
2470 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2471 {
2472         u32 addr_high, addr_low;
2473         int i;
2474
2475         addr_high = ((tp->dev->dev_addr[0] << 8) |
2476                      tp->dev->dev_addr[1]);
2477         addr_low = ((tp->dev->dev_addr[2] << 24) |
2478                     (tp->dev->dev_addr[3] << 16) |
2479                     (tp->dev->dev_addr[4] <<  8) |
2480                     (tp->dev->dev_addr[5] <<  0));
2481         for (i = 0; i < 4; i++) {
2482                 if (i == 1 && skip_mac_1)
2483                         continue;
2484                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2485                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2486         }
2487
2488         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2489             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2490                 for (i = 0; i < 12; i++) {
2491                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2492                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2493                 }
2494         }
2495
2496         addr_high = (tp->dev->dev_addr[0] +
2497                      tp->dev->dev_addr[1] +
2498                      tp->dev->dev_addr[2] +
2499                      tp->dev->dev_addr[3] +
2500                      tp->dev->dev_addr[4] +
2501                      tp->dev->dev_addr[5]) &
2502                 TX_BACKOFF_SEED_MASK;
2503         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2504 }
2505
2506 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2507 {
2508         u32 misc_host_ctrl;
2509         bool device_should_wake, do_low_power;
2510
2511         /* Make sure register accesses (indirect or otherwise)
2512          * will function correctly.
2513          */
2514         pci_write_config_dword(tp->pdev,
2515                                TG3PCI_MISC_HOST_CTRL,
2516                                tp->misc_host_ctrl);
2517
2518         switch (state) {
2519         case PCI_D0:
2520                 pci_enable_wake(tp->pdev, state, false);
2521                 pci_set_power_state(tp->pdev, PCI_D0);
2522
2523                 /* Switch out of Vaux if it is a NIC */
2524                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2525                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2526
2527                 return 0;
2528
2529         case PCI_D1:
2530         case PCI_D2:
2531         case PCI_D3hot:
2532                 break;
2533
2534         default:
2535                 netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
2536                            state);
2537                 return -EINVAL;
2538         }
2539
2540         /* Restore the CLKREQ setting. */
2541         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2542                 u16 lnkctl;
2543
2544                 pci_read_config_word(tp->pdev,
2545                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2546                                      &lnkctl);
2547                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2548                 pci_write_config_word(tp->pdev,
2549                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2550                                       lnkctl);
2551         }
2552
2553         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2554         tw32(TG3PCI_MISC_HOST_CTRL,
2555              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2556
2557         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2558                              device_may_wakeup(&tp->pdev->dev) &&
2559                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2560
2561         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2562                 do_low_power = false;
2563                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2564                     !tp->link_config.phy_is_low_power) {
2565                         struct phy_device *phydev;
2566                         u32 phyid, advertising;
2567
2568                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2569
2570                         tp->link_config.phy_is_low_power = 1;
2571
2572                         tp->link_config.orig_speed = phydev->speed;
2573                         tp->link_config.orig_duplex = phydev->duplex;
2574                         tp->link_config.orig_autoneg = phydev->autoneg;
2575                         tp->link_config.orig_advertising = phydev->advertising;
2576
2577                         advertising = ADVERTISED_TP |
2578                                       ADVERTISED_Pause |
2579                                       ADVERTISED_Autoneg |
2580                                       ADVERTISED_10baseT_Half;
2581
2582                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2583                             device_should_wake) {
2584                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2585                                         advertising |=
2586                                                 ADVERTISED_100baseT_Half |
2587                                                 ADVERTISED_100baseT_Full |
2588                                                 ADVERTISED_10baseT_Full;
2589                                 else
2590                                         advertising |= ADVERTISED_10baseT_Full;
2591                         }
2592
2593                         phydev->advertising = advertising;
2594
2595                         phy_start_aneg(phydev);
2596
2597                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2598                         if (phyid != PHY_ID_BCMAC131) {
2599                                 phyid &= PHY_BCM_OUI_MASK;
2600                                 if (phyid == PHY_BCM_OUI_1 ||
2601                                     phyid == PHY_BCM_OUI_2 ||
2602                                     phyid == PHY_BCM_OUI_3)
2603                                         do_low_power = true;
2604                         }
2605                 }
2606         } else {
2607                 do_low_power = true;
2608
2609                 if (tp->link_config.phy_is_low_power == 0) {
2610                         tp->link_config.phy_is_low_power = 1;
2611                         tp->link_config.orig_speed = tp->link_config.speed;
2612                         tp->link_config.orig_duplex = tp->link_config.duplex;
2613                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2614                 }
2615
2616                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2617                         tp->link_config.speed = SPEED_10;
2618                         tp->link_config.duplex = DUPLEX_HALF;
2619                         tp->link_config.autoneg = AUTONEG_ENABLE;
2620                         tg3_setup_phy(tp, 0);
2621                 }
2622         }
2623
2624         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2625                 u32 val;
2626
2627                 val = tr32(GRC_VCPU_EXT_CTRL);
2628                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2629         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2630                 int i;
2631                 u32 val;
2632
2633                 for (i = 0; i < 200; i++) {
2634                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2635                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2636                                 break;
2637                         msleep(1);
2638                 }
2639         }
2640         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2641                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2642                                                      WOL_DRV_STATE_SHUTDOWN |
2643                                                      WOL_DRV_WOL |
2644                                                      WOL_SET_MAGIC_PKT);
2645
2646         if (device_should_wake) {
2647                 u32 mac_mode;
2648
2649                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2650                         if (do_low_power) {
2651                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2652                                 udelay(40);
2653                         }
2654
2655                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2656                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2657                         else
2658                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2659
2660                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2661                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2662                             ASIC_REV_5700) {
2663                                 u32 speed = (tp->tg3_flags &
2664                                              TG3_FLAG_WOL_SPEED_100MB) ?
2665                                              SPEED_100 : SPEED_10;
2666                                 if (tg3_5700_link_polarity(tp, speed))
2667                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2668                                 else
2669                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2670                         }
2671                 } else {
2672                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2673                 }
2674
2675                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2676                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2677
2678                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2679                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2680                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2681                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2682                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2683                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2684
2685                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2686                         mac_mode |= tp->mac_mode &
2687                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2688                         if (mac_mode & MAC_MODE_APE_TX_EN)
2689                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2690                 }
2691
2692                 tw32_f(MAC_MODE, mac_mode);
2693                 udelay(100);
2694
2695                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2696                 udelay(10);
2697         }
2698
2699         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2700             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2701              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2702                 u32 base_val;
2703
2704                 base_val = tp->pci_clock_ctrl;
2705                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2706                              CLOCK_CTRL_TXCLK_DISABLE);
2707
2708                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2709                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2710         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2711                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2712                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2713                 /* do nothing */
2714         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2715                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2716                 u32 newbits1, newbits2;
2717
2718                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2719                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2720                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2721                                     CLOCK_CTRL_TXCLK_DISABLE |
2722                                     CLOCK_CTRL_ALTCLK);
2723                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2724                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2725                         newbits1 = CLOCK_CTRL_625_CORE;
2726                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2727                 } else {
2728                         newbits1 = CLOCK_CTRL_ALTCLK;
2729                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2730                 }
2731
2732                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2733                             40);
2734
2735                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2736                             40);
2737
2738                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2739                         u32 newbits3;
2740
2741                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2742                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2743                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2744                                             CLOCK_CTRL_TXCLK_DISABLE |
2745                                             CLOCK_CTRL_44MHZ_CORE);
2746                         } else {
2747                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2748                         }
2749
2750                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2751                                     tp->pci_clock_ctrl | newbits3, 40);
2752                 }
2753         }
2754
2755         if (!(device_should_wake) &&
2756             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2757                 tg3_power_down_phy(tp, do_low_power);
2758
2759         tg3_frob_aux_power(tp);
2760
2761         /* Workaround for unstable PLL clock */
2762         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2763             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2764                 u32 val = tr32(0x7d00);
2765
2766                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2767                 tw32(0x7d00, val);
2768                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2769                         int err;
2770
2771                         err = tg3_nvram_lock(tp);
2772                         tg3_halt_cpu(tp, RX_CPU_BASE);
2773                         if (!err)
2774                                 tg3_nvram_unlock(tp);
2775                 }
2776         }
2777
2778         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2779
2780         if (device_should_wake)
2781                 pci_enable_wake(tp->pdev, state, true);
2782
2783         /* Finally, set the new power state. */
2784         pci_set_power_state(tp->pdev, state);
2785
2786         return 0;
2787 }
2788
2789 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2790 {
2791         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2792         case MII_TG3_AUX_STAT_10HALF:
2793                 *speed = SPEED_10;
2794                 *duplex = DUPLEX_HALF;
2795                 break;
2796
2797         case MII_TG3_AUX_STAT_10FULL:
2798                 *speed = SPEED_10;
2799                 *duplex = DUPLEX_FULL;
2800                 break;
2801
2802         case MII_TG3_AUX_STAT_100HALF:
2803                 *speed = SPEED_100;
2804                 *duplex = DUPLEX_HALF;
2805                 break;
2806
2807         case MII_TG3_AUX_STAT_100FULL:
2808                 *speed = SPEED_100;
2809                 *duplex = DUPLEX_FULL;
2810                 break;
2811
2812         case MII_TG3_AUX_STAT_1000HALF:
2813                 *speed = SPEED_1000;
2814                 *duplex = DUPLEX_HALF;
2815                 break;
2816
2817         case MII_TG3_AUX_STAT_1000FULL:
2818                 *speed = SPEED_1000;
2819                 *duplex = DUPLEX_FULL;
2820                 break;
2821
2822         default:
2823                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2824                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2825                                  SPEED_10;
2826                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2827                                   DUPLEX_HALF;
2828                         break;
2829                 }
2830                 *speed = SPEED_INVALID;
2831                 *duplex = DUPLEX_INVALID;
2832                 break;
2833         }
2834 }
2835
2836 static void tg3_phy_copper_begin(struct tg3 *tp)
2837 {
2838         u32 new_adv;
2839         int i;
2840
2841         if (tp->link_config.phy_is_low_power) {
2842                 /* Entering low power mode.  Disable gigabit and
2843                  * 100baseT advertisements.
2844                  */
2845                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2846
2847                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2848                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2849                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2850                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2851
2852                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2853         } else if (tp->link_config.speed == SPEED_INVALID) {
2854                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2855                         tp->link_config.advertising &=
2856                                 ~(ADVERTISED_1000baseT_Half |
2857                                   ADVERTISED_1000baseT_Full);
2858
2859                 new_adv = ADVERTISE_CSMA;
2860                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2861                         new_adv |= ADVERTISE_10HALF;
2862                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2863                         new_adv |= ADVERTISE_10FULL;
2864                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2865                         new_adv |= ADVERTISE_100HALF;
2866                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2867                         new_adv |= ADVERTISE_100FULL;
2868
2869                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2870
2871                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2872
2873                 if (tp->link_config.advertising &
2874                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2875                         new_adv = 0;
2876                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2877                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2878                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2879                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2880                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2881                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2882                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2883                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2884                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2885                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2886                 } else {
2887                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2888                 }
2889         } else {
2890                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2891                 new_adv |= ADVERTISE_CSMA;
2892
2893                 /* Asking for a specific link mode. */
2894                 if (tp->link_config.speed == SPEED_1000) {
2895                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2896
2897                         if (tp->link_config.duplex == DUPLEX_FULL)
2898                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2899                         else
2900                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2901                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2902                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2903                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2904                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2905                 } else {
2906                         if (tp->link_config.speed == SPEED_100) {
2907                                 if (tp->link_config.duplex == DUPLEX_FULL)
2908                                         new_adv |= ADVERTISE_100FULL;
2909                                 else
2910                                         new_adv |= ADVERTISE_100HALF;
2911                         } else {
2912                                 if (tp->link_config.duplex == DUPLEX_FULL)
2913                                         new_adv |= ADVERTISE_10FULL;
2914                                 else
2915                                         new_adv |= ADVERTISE_10HALF;
2916                         }
2917                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2918
2919                         new_adv = 0;
2920                 }
2921
2922                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2923         }
2924
2925         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2926             tp->link_config.speed != SPEED_INVALID) {
2927                 u32 bmcr, orig_bmcr;
2928
2929                 tp->link_config.active_speed = tp->link_config.speed;
2930                 tp->link_config.active_duplex = tp->link_config.duplex;
2931
2932                 bmcr = 0;
2933                 switch (tp->link_config.speed) {
2934                 default:
2935                 case SPEED_10:
2936                         break;
2937
2938                 case SPEED_100:
2939                         bmcr |= BMCR_SPEED100;
2940                         break;
2941
2942                 case SPEED_1000:
2943                         bmcr |= TG3_BMCR_SPEED1000;
2944                         break;
2945                 }
2946
2947                 if (tp->link_config.duplex == DUPLEX_FULL)
2948                         bmcr |= BMCR_FULLDPLX;
2949
2950                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2951                     (bmcr != orig_bmcr)) {
2952                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2953                         for (i = 0; i < 1500; i++) {
2954                                 u32 tmp;
2955
2956                                 udelay(10);
2957                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2958                                     tg3_readphy(tp, MII_BMSR, &tmp))
2959                                         continue;
2960                                 if (!(tmp & BMSR_LSTATUS)) {
2961                                         udelay(40);
2962                                         break;
2963                                 }
2964                         }
2965                         tg3_writephy(tp, MII_BMCR, bmcr);
2966                         udelay(40);
2967                 }
2968         } else {
2969                 tg3_writephy(tp, MII_BMCR,
2970                              BMCR_ANENABLE | BMCR_ANRESTART);
2971         }
2972 }
2973
2974 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2975 {
2976         int err;
2977
2978         /* Turn off tap power management. */
2979         /* Set Extended packet length bit */
2980         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2981
2982         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2983         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2984
2985         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2986         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2987
2988         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2989         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2990
2991         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2992         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2993
2994         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2995         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2996
2997         udelay(40);
2998
2999         return err;
3000 }
3001
3002 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
3003 {
3004         u32 adv_reg, all_mask = 0;
3005
3006         if (mask & ADVERTISED_10baseT_Half)
3007                 all_mask |= ADVERTISE_10HALF;
3008         if (mask & ADVERTISED_10baseT_Full)
3009                 all_mask |= ADVERTISE_10FULL;
3010         if (mask & ADVERTISED_100baseT_Half)
3011                 all_mask |= ADVERTISE_100HALF;
3012         if (mask & ADVERTISED_100baseT_Full)
3013                 all_mask |= ADVERTISE_100FULL;
3014
3015         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3016                 return 0;
3017
3018         if ((adv_reg & all_mask) != all_mask)
3019                 return 0;
3020         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
3021                 u32 tg3_ctrl;
3022
3023                 all_mask = 0;
3024                 if (mask & ADVERTISED_1000baseT_Half)
3025                         all_mask |= ADVERTISE_1000HALF;
3026                 if (mask & ADVERTISED_1000baseT_Full)
3027                         all_mask |= ADVERTISE_1000FULL;
3028
3029                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3030                         return 0;
3031
3032                 if ((tg3_ctrl & all_mask) != all_mask)
3033                         return 0;
3034         }
3035         return 1;
3036 }
3037
3038 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3039 {
3040         u32 curadv, reqadv;
3041
3042         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3043                 return 1;
3044
3045         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3046         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3047
3048         if (tp->link_config.active_duplex == DUPLEX_FULL) {
3049                 if (curadv != reqadv)
3050                         return 0;
3051
3052                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3053                         tg3_readphy(tp, MII_LPA, rmtadv);
3054         } else {
3055                 /* Reprogram the advertisement register, even if it
3056                  * does not affect the current link.  If the link
3057                  * gets renegotiated in the future, we can save an
3058                  * additional renegotiation cycle by advertising
3059                  * it correctly in the first place.
3060                  */
3061                 if (curadv != reqadv) {
3062                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3063                                      ADVERTISE_PAUSE_ASYM);
3064                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3065                 }
3066         }
3067
3068         return 1;
3069 }
3070
3071 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3072 {
3073         int current_link_up;
3074         u32 bmsr, dummy;
3075         u32 lcl_adv, rmt_adv;
3076         u16 current_speed;
3077         u8 current_duplex;
3078         int i, err;
3079
3080         tw32(MAC_EVENT, 0);
3081
3082         tw32_f(MAC_STATUS,
3083              (MAC_STATUS_SYNC_CHANGED |
3084               MAC_STATUS_CFG_CHANGED |
3085               MAC_STATUS_MI_COMPLETION |
3086               MAC_STATUS_LNKSTATE_CHANGED));
3087         udelay(40);
3088
3089         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3090                 tw32_f(MAC_MI_MODE,
3091                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3092                 udelay(80);
3093         }
3094
3095         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3096
3097         /* Some third-party PHYs need to be reset on link going
3098          * down.
3099          */
3100         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3101              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3102              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3103             netif_carrier_ok(tp->dev)) {
3104                 tg3_readphy(tp, MII_BMSR, &bmsr);
3105                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3106                     !(bmsr & BMSR_LSTATUS))
3107                         force_reset = 1;
3108         }
3109         if (force_reset)
3110                 tg3_phy_reset(tp);
3111
3112         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3113                 tg3_readphy(tp, MII_BMSR, &bmsr);
3114                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3115                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3116                         bmsr = 0;
3117
3118                 if (!(bmsr & BMSR_LSTATUS)) {
3119                         err = tg3_init_5401phy_dsp(tp);
3120                         if (err)
3121                                 return err;
3122
3123                         tg3_readphy(tp, MII_BMSR, &bmsr);
3124                         for (i = 0; i < 1000; i++) {
3125                                 udelay(10);
3126                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3127                                     (bmsr & BMSR_LSTATUS)) {
3128                                         udelay(40);
3129                                         break;
3130                                 }
3131                         }
3132
3133                         if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3134                             TG3_PHY_REV_BCM5401_B0 &&
3135                             !(bmsr & BMSR_LSTATUS) &&
3136                             tp->link_config.active_speed == SPEED_1000) {
3137                                 err = tg3_phy_reset(tp);
3138                                 if (!err)
3139                                         err = tg3_init_5401phy_dsp(tp);
3140                                 if (err)
3141                                         return err;
3142                         }
3143                 }
3144         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3145                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3146                 /* 5701 {A0,B0} CRC bug workaround */
3147                 tg3_writephy(tp, 0x15, 0x0a75);
3148                 tg3_writephy(tp, 0x1c, 0x8c68);
3149                 tg3_writephy(tp, 0x1c, 0x8d68);
3150                 tg3_writephy(tp, 0x1c, 0x8c68);
3151         }
3152
3153         /* Clear pending interrupts... */
3154         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3155         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3156
3157         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3158                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3159         else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3160                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3161
3162         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3163             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3164                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3165                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3166                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3167                 else
3168                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3169         }
3170
3171         current_link_up = 0;
3172         current_speed = SPEED_INVALID;
3173         current_duplex = DUPLEX_INVALID;
3174
3175         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3176                 u32 val;
3177
3178                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3179                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3180                 if (!(val & (1 << 10))) {
3181                         val |= (1 << 10);
3182                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3183                         goto relink;
3184                 }
3185         }
3186
3187         bmsr = 0;
3188         for (i = 0; i < 100; i++) {
3189                 tg3_readphy(tp, MII_BMSR, &bmsr);
3190                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3191                     (bmsr & BMSR_LSTATUS))
3192                         break;
3193                 udelay(40);
3194         }
3195
3196         if (bmsr & BMSR_LSTATUS) {
3197                 u32 aux_stat, bmcr;
3198
3199                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3200                 for (i = 0; i < 2000; i++) {
3201                         udelay(10);
3202                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3203                             aux_stat)
3204                                 break;
3205                 }
3206
3207                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3208                                              &current_speed,
3209                                              &current_duplex);
3210
3211                 bmcr = 0;
3212                 for (i = 0; i < 200; i++) {
3213                         tg3_readphy(tp, MII_BMCR, &bmcr);
3214                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3215                                 continue;
3216                         if (bmcr && bmcr != 0x7fff)
3217                                 break;
3218                         udelay(10);
3219                 }
3220
3221                 lcl_adv = 0;
3222                 rmt_adv = 0;
3223
3224                 tp->link_config.active_speed = current_speed;
3225                 tp->link_config.active_duplex = current_duplex;
3226
3227                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3228                         if ((bmcr & BMCR_ANENABLE) &&
3229                             tg3_copper_is_advertising_all(tp,
3230                                                 tp->link_config.advertising)) {
3231                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3232                                                                   &rmt_adv))
3233                                         current_link_up = 1;
3234                         }
3235                 } else {
3236                         if (!(bmcr & BMCR_ANENABLE) &&
3237                             tp->link_config.speed == current_speed &&
3238                             tp->link_config.duplex == current_duplex &&
3239                             tp->link_config.flowctrl ==
3240                             tp->link_config.active_flowctrl) {
3241                                 current_link_up = 1;
3242                         }
3243                 }
3244
3245                 if (current_link_up == 1 &&
3246                     tp->link_config.active_duplex == DUPLEX_FULL)
3247                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3248         }
3249
3250 relink:
3251         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3252                 u32 tmp;
3253
3254                 tg3_phy_copper_begin(tp);
3255
3256                 tg3_readphy(tp, MII_BMSR, &tmp);
3257                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3258                     (tmp & BMSR_LSTATUS))
3259                         current_link_up = 1;
3260         }
3261
3262         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3263         if (current_link_up == 1) {
3264                 if (tp->link_config.active_speed == SPEED_100 ||
3265                     tp->link_config.active_speed == SPEED_10)
3266                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3267                 else
3268                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3269         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3270                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3271         else
3272                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3273
3274         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3275         if (tp->link_config.active_duplex == DUPLEX_HALF)
3276                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3277
3278         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3279                 if (current_link_up == 1 &&
3280                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3281                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3282                 else
3283                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3284         }
3285
3286         /* ??? Without this setting Netgear GA302T PHY does not
3287          * ??? send/receive packets...
3288          */
3289         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3290             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3291                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3292                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3293                 udelay(80);
3294         }
3295
3296         tw32_f(MAC_MODE, tp->mac_mode);
3297         udelay(40);
3298
3299         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3300                 /* Polled via timer. */
3301                 tw32_f(MAC_EVENT, 0);
3302         } else {
3303                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3304         }
3305         udelay(40);
3306
3307         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3308             current_link_up == 1 &&
3309             tp->link_config.active_speed == SPEED_1000 &&
3310             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3311              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3312                 udelay(120);
3313                 tw32_f(MAC_STATUS,
3314                      (MAC_STATUS_SYNC_CHANGED |
3315                       MAC_STATUS_CFG_CHANGED));
3316                 udelay(40);
3317                 tg3_write_mem(tp,
3318                               NIC_SRAM_FIRMWARE_MBOX,
3319                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3320         }
3321
3322         /* Prevent send BD corruption. */
3323         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3324                 u16 oldlnkctl, newlnkctl;
3325
3326                 pci_read_config_word(tp->pdev,
3327                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3328                                      &oldlnkctl);
3329                 if (tp->link_config.active_speed == SPEED_100 ||
3330                     tp->link_config.active_speed == SPEED_10)
3331                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3332                 else
3333                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3334                 if (newlnkctl != oldlnkctl)
3335                         pci_write_config_word(tp->pdev,
3336                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3337                                               newlnkctl);
3338         }
3339
3340         if (current_link_up != netif_carrier_ok(tp->dev)) {
3341                 if (current_link_up)
3342                         netif_carrier_on(tp->dev);
3343                 else
3344                         netif_carrier_off(tp->dev);
3345                 tg3_link_report(tp);
3346         }
3347
3348         return 0;
3349 }
3350
3351 struct tg3_fiber_aneginfo {
3352         int state;
3353 #define ANEG_STATE_UNKNOWN              0
3354 #define ANEG_STATE_AN_ENABLE            1
3355 #define ANEG_STATE_RESTART_INIT         2
3356 #define ANEG_STATE_RESTART              3
3357 #define ANEG_STATE_DISABLE_LINK_OK      4
3358 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3359 #define ANEG_STATE_ABILITY_DETECT       6
3360 #define ANEG_STATE_ACK_DETECT_INIT      7
3361 #define ANEG_STATE_ACK_DETECT           8
3362 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3363 #define ANEG_STATE_COMPLETE_ACK         10
3364 #define ANEG_STATE_IDLE_DETECT_INIT     11
3365 #define ANEG_STATE_IDLE_DETECT          12
3366 #define ANEG_STATE_LINK_OK              13
3367 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3368 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3369
3370         u32 flags;
3371 #define MR_AN_ENABLE            0x00000001
3372 #define MR_RESTART_AN           0x00000002
3373 #define MR_AN_COMPLETE          0x00000004
3374 #define MR_PAGE_RX              0x00000008
3375 #define MR_NP_LOADED            0x00000010
3376 #define MR_TOGGLE_TX            0x00000020
3377 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3378 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3379 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3380 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3381 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3382 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3383 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3384 #define MR_TOGGLE_RX            0x00002000
3385 #define MR_NP_RX                0x00004000
3386
3387 #define MR_LINK_OK              0x80000000
3388
3389         unsigned long link_time, cur_time;
3390
3391         u32 ability_match_cfg;
3392         int ability_match_count;
3393
3394         char ability_match, idle_match, ack_match;
3395
3396         u32 txconfig, rxconfig;
3397 #define ANEG_CFG_NP             0x00000080
3398 #define ANEG_CFG_ACK            0x00000040
3399 #define ANEG_CFG_RF2            0x00000020
3400 #define ANEG_CFG_RF1            0x00000010
3401 #define ANEG_CFG_PS2            0x00000001
3402 #define ANEG_CFG_PS1            0x00008000
3403 #define ANEG_CFG_HD             0x00004000
3404 #define ANEG_CFG_FD             0x00002000
3405 #define ANEG_CFG_INVAL          0x00001f06
3406
3407 };
3408 #define ANEG_OK         0
3409 #define ANEG_DONE       1
3410 #define ANEG_TIMER_ENAB 2
3411 #define ANEG_FAILED     -1
3412
3413 #define ANEG_STATE_SETTLE_TIME  10000
3414
3415 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3416                                    struct tg3_fiber_aneginfo *ap)
3417 {
3418         u16 flowctrl;
3419         unsigned long delta;
3420         u32 rx_cfg_reg;
3421         int ret;
3422
3423         if (ap->state == ANEG_STATE_UNKNOWN) {
3424                 ap->rxconfig = 0;
3425                 ap->link_time = 0;
3426                 ap->cur_time = 0;
3427                 ap->ability_match_cfg = 0;
3428                 ap->ability_match_count = 0;
3429                 ap->ability_match = 0;
3430                 ap->idle_match = 0;
3431                 ap->ack_match = 0;
3432         }
3433         ap->cur_time++;
3434
3435         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3436                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3437
3438                 if (rx_cfg_reg != ap->ability_match_cfg) {
3439                         ap->ability_match_cfg = rx_cfg_reg;
3440                         ap->ability_match = 0;
3441                         ap->ability_match_count = 0;
3442                 } else {
3443                         if (++ap->ability_match_count > 1) {
3444                                 ap->ability_match = 1;
3445                                 ap->ability_match_cfg = rx_cfg_reg;
3446                         }
3447                 }
3448                 if (rx_cfg_reg & ANEG_CFG_ACK)
3449                         ap->ack_match = 1;
3450                 else
3451                         ap->ack_match = 0;
3452
3453                 ap->idle_match = 0;
3454         } else {
3455                 ap->idle_match = 1;
3456                 ap->ability_match_cfg = 0;
3457                 ap->ability_match_count = 0;
3458                 ap->ability_match = 0;
3459                 ap->ack_match = 0;
3460
3461                 rx_cfg_reg = 0;
3462         }
3463
3464         ap->rxconfig = rx_cfg_reg;
3465         ret = ANEG_OK;
3466
3467         switch (ap->state) {
3468         case ANEG_STATE_UNKNOWN:
3469                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3470                         ap->state = ANEG_STATE_AN_ENABLE;
3471
3472                 /* fallthru */
3473         case ANEG_STATE_AN_ENABLE:
3474                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3475                 if (ap->flags & MR_AN_ENABLE) {
3476                         ap->link_time = 0;
3477                         ap->cur_time = 0;
3478                         ap->ability_match_cfg = 0;
3479                         ap->ability_match_count = 0;
3480                         ap->ability_match = 0;
3481                         ap->idle_match = 0;
3482                         ap->ack_match = 0;
3483
3484                         ap->state = ANEG_STATE_RESTART_INIT;
3485                 } else {
3486                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3487                 }
3488                 break;
3489
3490         case ANEG_STATE_RESTART_INIT:
3491                 ap->link_time = ap->cur_time;
3492                 ap->flags &= ~(MR_NP_LOADED);
3493                 ap->txconfig = 0;
3494                 tw32(MAC_TX_AUTO_NEG, 0);
3495                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3496                 tw32_f(MAC_MODE, tp->mac_mode);
3497                 udelay(40);
3498
3499                 ret = ANEG_TIMER_ENAB;
3500                 ap->state = ANEG_STATE_RESTART;
3501
3502                 /* fallthru */
3503         case ANEG_STATE_RESTART:
3504                 delta = ap->cur_time - ap->link_time;
3505                 if (delta > ANEG_STATE_SETTLE_TIME)
3506                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3507                 else
3508                         ret = ANEG_TIMER_ENAB;
3509                 break;
3510
3511         case ANEG_STATE_DISABLE_LINK_OK:
3512                 ret = ANEG_DONE;
3513                 break;
3514
3515         case ANEG_STATE_ABILITY_DETECT_INIT:
3516                 ap->flags &= ~(MR_TOGGLE_TX);
3517                 ap->txconfig = ANEG_CFG_FD;
3518                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3519                 if (flowctrl & ADVERTISE_1000XPAUSE)
3520                         ap->txconfig |= ANEG_CFG_PS1;
3521                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3522                         ap->txconfig |= ANEG_CFG_PS2;
3523                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3524                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3525                 tw32_f(MAC_MODE, tp->mac_mode);
3526                 udelay(40);
3527
3528                 ap->state = ANEG_STATE_ABILITY_DETECT;
3529                 break;
3530
3531         case ANEG_STATE_ABILITY_DETECT:
3532                 if (ap->ability_match != 0 && ap->rxconfig != 0)
3533                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3534                 break;
3535
3536         case ANEG_STATE_ACK_DETECT_INIT:
3537                 ap->txconfig |= ANEG_CFG_ACK;
3538                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3539                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3540                 tw32_f(MAC_MODE, tp->mac_mode);
3541                 udelay(40);
3542
3543                 ap->state = ANEG_STATE_ACK_DETECT;
3544
3545                 /* fallthru */
3546         case ANEG_STATE_ACK_DETECT:
3547                 if (ap->ack_match != 0) {
3548                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3549                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3550                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3551                         } else {
3552                                 ap->state = ANEG_STATE_AN_ENABLE;
3553                         }
3554                 } else if (ap->ability_match != 0 &&
3555                            ap->rxconfig == 0) {
3556                         ap->state = ANEG_STATE_AN_ENABLE;
3557                 }
3558                 break;
3559
3560         case ANEG_STATE_COMPLETE_ACK_INIT:
3561                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3562                         ret = ANEG_FAILED;
3563                         break;
3564                 }
3565                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3566                                MR_LP_ADV_HALF_DUPLEX |
3567                                MR_LP_ADV_SYM_PAUSE |
3568                                MR_LP_ADV_ASYM_PAUSE |
3569                                MR_LP_ADV_REMOTE_FAULT1 |
3570                                MR_LP_ADV_REMOTE_FAULT2 |
3571                                MR_LP_ADV_NEXT_PAGE |
3572                                MR_TOGGLE_RX |
3573                                MR_NP_RX);
3574                 if (ap->rxconfig & ANEG_CFG_FD)
3575                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3576                 if (ap->rxconfig & ANEG_CFG_HD)
3577                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3578                 if (ap->rxconfig & ANEG_CFG_PS1)
3579                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3580                 if (ap->rxconfig & ANEG_CFG_PS2)
3581                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3582                 if (ap->rxconfig & ANEG_CFG_RF1)
3583                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3584                 if (ap->rxconfig & ANEG_CFG_RF2)
3585                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3586                 if (ap->rxconfig & ANEG_CFG_NP)
3587                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3588
3589                 ap->link_time = ap->cur_time;
3590
3591                 ap->flags ^= (MR_TOGGLE_TX);
3592                 if (ap->rxconfig & 0x0008)
3593                         ap->flags |= MR_TOGGLE_RX;
3594                 if (ap->rxconfig & ANEG_CFG_NP)
3595                         ap->flags |= MR_NP_RX;
3596                 ap->flags |= MR_PAGE_RX;
3597
3598                 ap->state = ANEG_STATE_COMPLETE_ACK;
3599                 ret = ANEG_TIMER_ENAB;
3600                 break;
3601
3602         case ANEG_STATE_COMPLETE_ACK:
3603                 if (ap->ability_match != 0 &&
3604                     ap->rxconfig == 0) {
3605                         ap->state = ANEG_STATE_AN_ENABLE;
3606                         break;
3607                 }
3608                 delta = ap->cur_time - ap->link_time;
3609                 if (delta > ANEG_STATE_SETTLE_TIME) {
3610                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3611                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3612                         } else {
3613                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3614                                     !(ap->flags & MR_NP_RX)) {
3615                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3616                                 } else {
3617                                         ret = ANEG_FAILED;
3618                                 }
3619                         }
3620                 }
3621                 break;
3622
3623         case ANEG_STATE_IDLE_DETECT_INIT:
3624                 ap->link_time = ap->cur_time;
3625                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3626                 tw32_f(MAC_MODE, tp->mac_mode);
3627                 udelay(40);
3628
3629                 ap->state = ANEG_STATE_IDLE_DETECT;
3630                 ret = ANEG_TIMER_ENAB;
3631                 break;
3632
3633         case ANEG_STATE_IDLE_DETECT:
3634                 if (ap->ability_match != 0 &&
3635                     ap->rxconfig == 0) {
3636                         ap->state = ANEG_STATE_AN_ENABLE;
3637                         break;
3638                 }
3639                 delta = ap->cur_time - ap->link_time;
3640                 if (delta > ANEG_STATE_SETTLE_TIME) {
3641                         /* XXX another gem from the Broadcom driver :( */
3642                         ap->state = ANEG_STATE_LINK_OK;
3643                 }
3644                 break;
3645
3646         case ANEG_STATE_LINK_OK:
3647                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3648                 ret = ANEG_DONE;
3649                 break;
3650
3651         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3652                 /* ??? unimplemented */
3653                 break;
3654
3655         case ANEG_STATE_NEXT_PAGE_WAIT:
3656                 /* ??? unimplemented */
3657                 break;
3658
3659         default:
3660                 ret = ANEG_FAILED;
3661                 break;
3662         }
3663
3664         return ret;
3665 }
3666
3667 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3668 {
3669         int res = 0;
3670         struct tg3_fiber_aneginfo aninfo;
3671         int status = ANEG_FAILED;
3672         unsigned int tick;
3673         u32 tmp;
3674
3675         tw32_f(MAC_TX_AUTO_NEG, 0);
3676
3677         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3678         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3679         udelay(40);
3680
3681         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3682         udelay(40);
3683
3684         memset(&aninfo, 0, sizeof(aninfo));
3685         aninfo.flags |= MR_AN_ENABLE;
3686         aninfo.state = ANEG_STATE_UNKNOWN;
3687         aninfo.cur_time = 0;
3688         tick = 0;
3689         while (++tick < 195000) {
3690                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3691                 if (status == ANEG_DONE || status == ANEG_FAILED)
3692                         break;
3693
3694                 udelay(1);
3695         }
3696
3697         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3698         tw32_f(MAC_MODE, tp->mac_mode);
3699         udelay(40);
3700
3701         *txflags = aninfo.txconfig;
3702         *rxflags = aninfo.flags;
3703
3704         if (status == ANEG_DONE &&
3705             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3706                              MR_LP_ADV_FULL_DUPLEX)))
3707                 res = 1;
3708
3709         return res;
3710 }
3711
3712 static void tg3_init_bcm8002(struct tg3 *tp)
3713 {
3714         u32 mac_status = tr32(MAC_STATUS);
3715         int i;
3716
3717         /* Reset when initting first time or we have a link. */
3718         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3719             !(mac_status & MAC_STATUS_PCS_SYNCED))
3720                 return;
3721
3722         /* Set PLL lock range. */
3723         tg3_writephy(tp, 0x16, 0x8007);
3724
3725         /* SW reset */
3726         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3727
3728         /* Wait for reset to complete. */
3729         /* XXX schedule_timeout() ... */
3730         for (i = 0; i < 500; i++)
3731                 udelay(10);
3732
3733         /* Config mode; select PMA/Ch 1 regs. */
3734         tg3_writephy(tp, 0x10, 0x8411);
3735
3736         /* Enable auto-lock and comdet, select txclk for tx. */
3737         tg3_writephy(tp, 0x11, 0x0a10);
3738
3739         tg3_writephy(tp, 0x18, 0x00a0);
3740         tg3_writephy(tp, 0x16, 0x41ff);
3741
3742         /* Assert and deassert POR. */
3743         tg3_writephy(tp, 0x13, 0x0400);
3744         udelay(40);
3745         tg3_writephy(tp, 0x13, 0x0000);
3746
3747         tg3_writephy(tp, 0x11, 0x0a50);
3748         udelay(40);
3749         tg3_writephy(tp, 0x11, 0x0a10);
3750
3751         /* Wait for signal to stabilize */
3752         /* XXX schedule_timeout() ... */
3753         for (i = 0; i < 15000; i++)
3754                 udelay(10);
3755
3756         /* Deselect the channel register so we can read the PHYID
3757          * later.
3758          */
3759         tg3_writephy(tp, 0x10, 0x8011);
3760 }
3761
3762 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3763 {
3764         u16 flowctrl;
3765         u32 sg_dig_ctrl, sg_dig_status;
3766         u32 serdes_cfg, expected_sg_dig_ctrl;
3767         int workaround, port_a;
3768         int current_link_up;
3769
3770         serdes_cfg = 0;
3771         expected_sg_dig_ctrl = 0;
3772         workaround = 0;
3773         port_a = 1;
3774         current_link_up = 0;
3775
3776         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3777             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3778                 workaround = 1;
3779                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3780                         port_a = 0;
3781
3782                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3783                 /* preserve bits 20-23 for voltage regulator */
3784                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3785         }
3786
3787         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3788
3789         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3790                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3791                         if (workaround) {
3792                                 u32 val = serdes_cfg;
3793
3794                                 if (port_a)
3795                                         val |= 0xc010000;
3796                                 else
3797                                         val |= 0x4010000;
3798                                 tw32_f(MAC_SERDES_CFG, val);
3799                         }
3800
3801                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3802                 }
3803                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3804                         tg3_setup_flow_control(tp, 0, 0);
3805                         current_link_up = 1;
3806                 }
3807                 goto out;
3808         }
3809
3810         /* Want auto-negotiation.  */
3811         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3812
3813         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3814         if (flowctrl & ADVERTISE_1000XPAUSE)
3815                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3816         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3817                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3818
3819         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3820                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3821                     tp->serdes_counter &&
3822                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3823                                     MAC_STATUS_RCVD_CFG)) ==
3824                      MAC_STATUS_PCS_SYNCED)) {
3825                         tp->serdes_counter--;
3826                         current_link_up = 1;
3827                         goto out;
3828                 }
3829 restart_autoneg:
3830                 if (workaround)
3831                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3832                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3833                 udelay(5);
3834                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3835
3836                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3837                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3838         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3839                                  MAC_STATUS_SIGNAL_DET)) {
3840                 sg_dig_status = tr32(SG_DIG_STATUS);
3841                 mac_status = tr32(MAC_STATUS);
3842
3843                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3844                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3845                         u32 local_adv = 0, remote_adv = 0;
3846
3847                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3848                                 local_adv |= ADVERTISE_1000XPAUSE;
3849                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3850                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3851
3852                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3853                                 remote_adv |= LPA_1000XPAUSE;
3854                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3855                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3856
3857                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3858                         current_link_up = 1;
3859                         tp->serdes_counter = 0;
3860                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3861                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3862                         if (tp->serdes_counter)
3863                                 tp->serdes_counter--;
3864                         else {
3865                                 if (workaround) {
3866                                         u32 val = serdes_cfg;
3867
3868                                         if (port_a)
3869                                                 val |= 0xc010000;
3870                                         else
3871                                                 val |= 0x4010000;
3872
3873                                         tw32_f(MAC_SERDES_CFG, val);
3874                                 }
3875
3876                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3877                                 udelay(40);
3878
3879                                 /* Link parallel detection - link is up */
3880                                 /* only if we have PCS_SYNC and not */
3881                                 /* receiving config code words */
3882                                 mac_status = tr32(MAC_STATUS);
3883                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3884                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3885                                         tg3_setup_flow_control(tp, 0, 0);
3886                                         current_link_up = 1;
3887                                         tp->tg3_flags2 |=
3888                                                 TG3_FLG2_PARALLEL_DETECT;
3889                                         tp->serdes_counter =
3890                                                 SERDES_PARALLEL_DET_TIMEOUT;
3891                                 } else
3892                                         goto restart_autoneg;
3893                         }
3894                 }
3895         } else {
3896                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3897                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3898         }
3899
3900 out:
3901         return current_link_up;
3902 }
3903
3904 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3905 {
3906         int current_link_up = 0;
3907
3908         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3909                 goto out;
3910
3911         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3912                 u32 txflags, rxflags;
3913                 int i;
3914
3915                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3916                         u32 local_adv = 0, remote_adv = 0;
3917
3918                         if (txflags & ANEG_CFG_PS1)
3919                                 local_adv |= ADVERTISE_1000XPAUSE;
3920                         if (txflags & ANEG_CFG_PS2)
3921                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3922
3923                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3924                                 remote_adv |= LPA_1000XPAUSE;
3925                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3926                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3927
3928                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3929
3930                         current_link_up = 1;
3931                 }
3932                 for (i = 0; i < 30; i++) {
3933                         udelay(20);
3934                         tw32_f(MAC_STATUS,
3935                                (MAC_STATUS_SYNC_CHANGED |
3936                                 MAC_STATUS_CFG_CHANGED));
3937                         udelay(40);
3938                         if ((tr32(MAC_STATUS) &
3939                              (MAC_STATUS_SYNC_CHANGED |
3940                               MAC_STATUS_CFG_CHANGED)) == 0)
3941                                 break;
3942                 }
3943
3944                 mac_status = tr32(MAC_STATUS);
3945                 if (current_link_up == 0 &&
3946                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3947                     !(mac_status & MAC_STATUS_RCVD_CFG))
3948                         current_link_up = 1;
3949         } else {
3950                 tg3_setup_flow_control(tp, 0, 0);
3951
3952                 /* Forcing 1000FD link up. */
3953                 current_link_up = 1;
3954
3955                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3956                 udelay(40);
3957
3958                 tw32_f(MAC_MODE, tp->mac_mode);
3959                 udelay(40);
3960         }
3961
3962 out:
3963         return current_link_up;
3964 }
3965
3966 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3967 {
3968         u32 orig_pause_cfg;
3969         u16 orig_active_speed;
3970         u8 orig_active_duplex;
3971         u32 mac_status;
3972         int current_link_up;
3973         int i;
3974
3975         orig_pause_cfg = tp->link_config.active_flowctrl;
3976         orig_active_speed = tp->link_config.active_speed;
3977         orig_active_duplex = tp->link_config.active_duplex;
3978
3979         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3980             netif_carrier_ok(tp->dev) &&
3981             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3982                 mac_status = tr32(MAC_STATUS);
3983                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3984                                MAC_STATUS_SIGNAL_DET |
3985                                MAC_STATUS_CFG_CHANGED |
3986                                MAC_STATUS_RCVD_CFG);
3987                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3988                                    MAC_STATUS_SIGNAL_DET)) {
3989                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3990                                             MAC_STATUS_CFG_CHANGED));
3991                         return 0;
3992                 }
3993         }
3994
3995         tw32_f(MAC_TX_AUTO_NEG, 0);
3996
3997         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3998         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3999         tw32_f(MAC_MODE, tp->mac_mode);
4000         udelay(40);
4001
4002         if (tp->phy_id == TG3_PHY_ID_BCM8002)
4003                 tg3_init_bcm8002(tp);
4004
4005         /* Enable link change event even when serdes polling.  */
4006         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4007         udelay(40);
4008
4009         current_link_up = 0;
4010         mac_status = tr32(MAC_STATUS);
4011
4012         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
4013                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4014         else
4015                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4016
4017         tp->napi[0].hw_status->status =
4018                 (SD_STATUS_UPDATED |
4019                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4020
4021         for (i = 0; i < 100; i++) {
4022                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4023                                     MAC_STATUS_CFG_CHANGED));
4024                 udelay(5);
4025                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4026                                          MAC_STATUS_CFG_CHANGED |
4027                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4028                         break;
4029         }
4030
4031         mac_status = tr32(MAC_STATUS);
4032         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4033                 current_link_up = 0;
4034                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4035                     tp->serdes_counter == 0) {
4036                         tw32_f(MAC_MODE, (tp->mac_mode |
4037                                           MAC_MODE_SEND_CONFIGS));
4038                         udelay(1);
4039                         tw32_f(MAC_MODE, tp->mac_mode);
4040                 }
4041         }
4042
4043         if (current_link_up == 1) {
4044                 tp->link_config.active_speed = SPEED_1000;
4045                 tp->link_config.active_duplex = DUPLEX_FULL;
4046                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4047                                     LED_CTRL_LNKLED_OVERRIDE |
4048                                     LED_CTRL_1000MBPS_ON));
4049         } else {
4050                 tp->link_config.active_speed = SPEED_INVALID;
4051                 tp->link_config.active_duplex = DUPLEX_INVALID;
4052                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4053                                     LED_CTRL_LNKLED_OVERRIDE |
4054                                     LED_CTRL_TRAFFIC_OVERRIDE));
4055         }
4056
4057         if (current_link_up != netif_carrier_ok(tp->dev)) {
4058                 if (current_link_up)
4059                         netif_carrier_on(tp->dev);
4060                 else
4061                         netif_carrier_off(tp->dev);
4062                 tg3_link_report(tp);
4063         } else {
4064                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4065                 if (orig_pause_cfg != now_pause_cfg ||
4066                     orig_active_speed != tp->link_config.active_speed ||
4067                     orig_active_duplex != tp->link_config.active_duplex)
4068                         tg3_link_report(tp);
4069         }
4070
4071         return 0;
4072 }
4073
4074 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4075 {
4076         int current_link_up, err = 0;
4077         u32 bmsr, bmcr;
4078         u16 current_speed;
4079         u8 current_duplex;
4080         u32 local_adv, remote_adv;
4081
4082         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4083         tw32_f(MAC_MODE, tp->mac_mode);
4084         udelay(40);
4085
4086         tw32(MAC_EVENT, 0);
4087
4088         tw32_f(MAC_STATUS,
4089              (MAC_STATUS_SYNC_CHANGED |
4090               MAC_STATUS_CFG_CHANGED |
4091               MAC_STATUS_MI_COMPLETION |
4092               MAC_STATUS_LNKSTATE_CHANGED));
4093         udelay(40);
4094
4095         if (force_reset)
4096                 tg3_phy_reset(tp);
4097
4098         current_link_up = 0;
4099         current_speed = SPEED_INVALID;
4100         current_duplex = DUPLEX_INVALID;
4101
4102         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4103         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4104         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4105                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4106                         bmsr |= BMSR_LSTATUS;
4107                 else
4108                         bmsr &= ~BMSR_LSTATUS;
4109         }
4110
4111         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4112
4113         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4114             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4115                 /* do nothing, just check for link up at the end */
4116         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4117                 u32 adv, new_adv;
4118
4119                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4120                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4121                                   ADVERTISE_1000XPAUSE |
4122                                   ADVERTISE_1000XPSE_ASYM |
4123                                   ADVERTISE_SLCT);
4124
4125                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4126
4127                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4128                         new_adv |= ADVERTISE_1000XHALF;
4129                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4130                         new_adv |= ADVERTISE_1000XFULL;
4131
4132                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4133                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4134                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4135                         tg3_writephy(tp, MII_BMCR, bmcr);
4136
4137                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4138                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4139                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4140
4141                         return err;
4142                 }
4143         } else {
4144                 u32 new_bmcr;
4145
4146                 bmcr &= ~BMCR_SPEED1000;
4147                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4148
4149                 if (tp->link_config.duplex == DUPLEX_FULL)
4150                         new_bmcr |= BMCR_FULLDPLX;
4151
4152                 if (new_bmcr != bmcr) {
4153                         /* BMCR_SPEED1000 is a reserved bit that needs
4154                          * to be set on write.
4155                          */
4156                         new_bmcr |= BMCR_SPEED1000;
4157
4158                         /* Force a linkdown */
4159                         if (netif_carrier_ok(tp->dev)) {
4160                                 u32 adv;
4161
4162                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4163                                 adv &= ~(ADVERTISE_1000XFULL |
4164                                          ADVERTISE_1000XHALF |
4165                                          ADVERTISE_SLCT);
4166                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4167                                 tg3_writephy(tp, MII_BMCR, bmcr |
4168                                                            BMCR_ANRESTART |
4169                                                            BMCR_ANENABLE);
4170                                 udelay(10);
4171                                 netif_carrier_off(tp->dev);
4172                         }
4173                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4174                         bmcr = new_bmcr;
4175                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4176                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4177                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4178                             ASIC_REV_5714) {
4179                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4180                                         bmsr |= BMSR_LSTATUS;
4181                                 else
4182                                         bmsr &= ~BMSR_LSTATUS;
4183                         }
4184                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4185                 }
4186         }
4187
4188         if (bmsr & BMSR_LSTATUS) {
4189                 current_speed = SPEED_1000;
4190                 current_link_up = 1;
4191                 if (bmcr & BMCR_FULLDPLX)
4192                         current_duplex = DUPLEX_FULL;
4193                 else
4194                         current_duplex = DUPLEX_HALF;
4195
4196                 local_adv = 0;
4197                 remote_adv = 0;
4198
4199                 if (bmcr & BMCR_ANENABLE) {
4200                         u32 common;
4201
4202                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4203                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4204                         common = local_adv & remote_adv;
4205                         if (common & (ADVERTISE_1000XHALF |
4206                                       ADVERTISE_1000XFULL)) {
4207                                 if (common & ADVERTISE_1000XFULL)
4208                                         current_duplex = DUPLEX_FULL;
4209                                 else
4210                                         current_duplex = DUPLEX_HALF;
4211                         } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4212                                 /* Link is up via parallel detect */
4213                         } else {
4214                                 current_link_up = 0;
4215                         }
4216                 }
4217         }
4218
4219         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4220                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4221
4222         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4223         if (tp->link_config.active_duplex == DUPLEX_HALF)
4224                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4225
4226         tw32_f(MAC_MODE, tp->mac_mode);
4227         udelay(40);
4228
4229         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4230
4231         tp->link_config.active_speed = current_speed;
4232         tp->link_config.active_duplex = current_duplex;
4233
4234         if (current_link_up != netif_carrier_ok(tp->dev)) {
4235                 if (current_link_up)
4236                         netif_carrier_on(tp->dev);
4237                 else {
4238                         netif_carrier_off(tp->dev);
4239                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4240                 }
4241                 tg3_link_report(tp);
4242         }
4243         return err;
4244 }
4245
4246 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4247 {
4248         if (tp->serdes_counter) {
4249                 /* Give autoneg time to complete. */
4250                 tp->serdes_counter--;
4251                 return;
4252         }
4253
4254         if (!netif_carrier_ok(tp->dev) &&
4255             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4256                 u32 bmcr;
4257
4258                 tg3_readphy(tp, MII_BMCR, &bmcr);
4259                 if (bmcr & BMCR_ANENABLE) {
4260                         u32 phy1, phy2;
4261
4262                         /* Select shadow register 0x1f */
4263                         tg3_writephy(tp, 0x1c, 0x7c00);
4264                         tg3_readphy(tp, 0x1c, &phy1);
4265
4266                         /* Select expansion interrupt status register */
4267                         tg3_writephy(tp, 0x17, 0x0f01);
4268                         tg3_readphy(tp, 0x15, &phy2);
4269                         tg3_readphy(tp, 0x15, &phy2);
4270
4271                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4272                                 /* We have signal detect and not receiving
4273                                  * config code words, link is up by parallel
4274                                  * detection.
4275                                  */
4276
4277                                 bmcr &= ~BMCR_ANENABLE;
4278                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4279                                 tg3_writephy(tp, MII_BMCR, bmcr);
4280                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4281                         }
4282                 }
4283         } else if (netif_carrier_ok(tp->dev) &&
4284                    (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4285                    (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4286                 u32 phy2;
4287
4288                 /* Select expansion interrupt status register */
4289                 tg3_writephy(tp, 0x17, 0x0f01);
4290                 tg3_readphy(tp, 0x15, &phy2);
4291                 if (phy2 & 0x20) {
4292                         u32 bmcr;
4293
4294                         /* Config code words received, turn on autoneg. */
4295                         tg3_readphy(tp, MII_BMCR, &bmcr);
4296                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4297
4298                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4299
4300                 }
4301         }
4302 }
4303
4304 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4305 {
4306         int err;
4307
4308         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
4309                 err = tg3_setup_fiber_phy(tp, force_reset);
4310         else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
4311                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4312         else
4313                 err = tg3_setup_copper_phy(tp, force_reset);
4314
4315         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4316                 u32 val, scale;
4317
4318                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4319                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4320                         scale = 65;
4321                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4322                         scale = 6;
4323                 else
4324                         scale = 12;
4325
4326                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4327                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4328                 tw32(GRC_MISC_CFG, val);
4329         }
4330
4331         if (tp->link_config.active_speed == SPEED_1000 &&
4332             tp->link_config.active_duplex == DUPLEX_HALF)
4333                 tw32(MAC_TX_LENGTHS,
4334                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4335                       (6 << TX_LENGTHS_IPG_SHIFT) |
4336                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4337         else
4338                 tw32(MAC_TX_LENGTHS,
4339                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4340                       (6 << TX_LENGTHS_IPG_SHIFT) |
4341                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4342
4343         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4344                 if (netif_carrier_ok(tp->dev)) {
4345                         tw32(HOSTCC_STAT_COAL_TICKS,
4346                              tp->coal.stats_block_coalesce_usecs);
4347                 } else {
4348                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4349                 }
4350         }
4351
4352         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4353                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4354                 if (!netif_carrier_ok(tp->dev))
4355                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4356                               tp->pwrmgmt_thresh;
4357                 else
4358                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4359                 tw32(PCIE_PWR_MGMT_THRESH, val);
4360         }
4361
4362         return err;
4363 }
4364
4365 /* This is called whenever we suspect that the system chipset is re-
4366  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4367  * is bogus tx completions. We try to recover by setting the
4368  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4369  * in the workqueue.
4370  */
4371 static void tg3_tx_recover(struct tg3 *tp)
4372 {
4373         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4374                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4375
4376         netdev_warn(tp->dev,
4377                     "The system may be re-ordering memory-mapped I/O "
4378                     "cycles to the network device, attempting to recover. "
4379                     "Please report the problem to the driver maintainer "
4380                     "and include system chipset information.\n");
4381
4382         spin_lock(&tp->lock);
4383         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4384         spin_unlock(&tp->lock);
4385 }
4386
4387 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4388 {
4389         /* Tell compiler to fetch tx indices from memory. */
4390         barrier();
4391         return tnapi->tx_pending -
4392                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4393 }
4394
4395 /* Tigon3 never reports partial packet sends.  So we do not
4396  * need special logic to handle SKBs that have not had all
4397  * of their frags sent yet, like SunGEM does.
4398  */
4399 static void tg3_tx(struct tg3_napi *tnapi)
4400 {
4401         struct tg3 *tp = tnapi->tp;
4402         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4403         u32 sw_idx = tnapi->tx_cons;
4404         struct netdev_queue *txq;
4405         int index = tnapi - tp->napi;
4406
4407         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4408                 index--;
4409
4410         txq = netdev_get_tx_queue(tp->dev, index);
4411
4412         while (sw_idx != hw_idx) {
4413                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4414                 struct sk_buff *skb = ri->skb;
4415                 int i, tx_bug = 0;
4416
4417                 if (unlikely(skb == NULL)) {
4418                         tg3_tx_recover(tp);
4419                         return;
4420                 }
4421
4422                 pci_unmap_single(tp->pdev,
4423                                  dma_unmap_addr(ri, mapping),
4424                                  skb_headlen(skb),
4425                                  PCI_DMA_TODEVICE);
4426
4427                 ri->skb = NULL;
4428
4429                 sw_idx = NEXT_TX(sw_idx);
4430
4431                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4432                         ri = &tnapi->tx_buffers[sw_idx];
4433                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4434                                 tx_bug = 1;
4435
4436                         pci_unmap_page(tp->pdev,
4437                                        dma_unmap_addr(ri, mapping),
4438                                        skb_shinfo(skb)->frags[i].size,
4439                                        PCI_DMA_TODEVICE);
4440                         sw_idx = NEXT_TX(sw_idx);
4441                 }
4442
4443                 dev_kfree_skb(skb);
4444
4445                 if (unlikely(tx_bug)) {
4446                         tg3_tx_recover(tp);
4447                         return;
4448                 }
4449         }
4450
4451         tnapi->tx_cons = sw_idx;
4452
4453         /* Need to make the tx_cons update visible to tg3_start_xmit()
4454          * before checking for netif_queue_stopped().  Without the
4455          * memory barrier, there is a small possibility that tg3_start_xmit()
4456          * will miss it and cause the queue to be stopped forever.
4457          */
4458         smp_mb();
4459
4460         if (unlikely(netif_tx_queue_stopped(txq) &&
4461                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4462                 __netif_tx_lock(txq, smp_processor_id());
4463                 if (netif_tx_queue_stopped(txq) &&
4464                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4465                         netif_tx_wake_queue(txq);
4466                 __netif_tx_unlock(txq);
4467         }
4468 }
4469
4470 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4471 {
4472         if (!ri->skb)
4473                 return;
4474
4475         pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4476                          map_sz, PCI_DMA_FROMDEVICE);
4477         dev_kfree_skb_any(ri->skb);
4478         ri->skb = NULL;
4479 }
4480
4481 /* Returns size of skb allocated or < 0 on error.
4482  *
4483  * We only need to fill in the address because the other members
4484  * of the RX descriptor are invariant, see tg3_init_rings.
4485  *
4486  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4487  * posting buffers we only dirty the first cache line of the RX
4488  * descriptor (containing the address).  Whereas for the RX status
4489  * buffers the cpu only reads the last cacheline of the RX descriptor
4490  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4491  */
4492 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4493                             u32 opaque_key, u32 dest_idx_unmasked)
4494 {
4495         struct tg3_rx_buffer_desc *desc;
4496         struct ring_info *map, *src_map;
4497         struct sk_buff *skb;
4498         dma_addr_t mapping;
4499         int skb_size, dest_idx;
4500
4501         src_map = NULL;
4502         switch (opaque_key) {
4503         case RXD_OPAQUE_RING_STD:
4504                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4505                 desc = &tpr->rx_std[dest_idx];
4506                 map = &tpr->rx_std_buffers[dest_idx];
4507                 skb_size = tp->rx_pkt_map_sz;
4508                 break;
4509
4510         case RXD_OPAQUE_RING_JUMBO:
4511                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4512                 desc = &tpr->rx_jmb[dest_idx].std;
4513                 map = &tpr->rx_jmb_buffers[dest_idx];
4514                 skb_size = TG3_RX_JMB_MAP_SZ;
4515                 break;
4516
4517         default:
4518                 return -EINVAL;
4519         }
4520
4521         /* Do not overwrite any of the map or rp information
4522          * until we are sure we can commit to a new buffer.
4523          *
4524          * Callers depend upon this behavior and assume that
4525          * we leave everything unchanged if we fail.
4526          */
4527         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4528         if (skb == NULL)
4529                 return -ENOMEM;
4530
4531         skb_reserve(skb, tp->rx_offset);
4532
4533         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4534                                  PCI_DMA_FROMDEVICE);
4535         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4536                 dev_kfree_skb(skb);
4537                 return -EIO;
4538         }
4539
4540         map->skb = skb;
4541         dma_unmap_addr_set(map, mapping, mapping);
4542
4543         desc->addr_hi = ((u64)mapping >> 32);
4544         desc->addr_lo = ((u64)mapping & 0xffffffff);
4545
4546         return skb_size;
4547 }
4548
4549 /* We only need to move over in the address because the other
4550  * members of the RX descriptor are invariant.  See notes above
4551  * tg3_alloc_rx_skb for full details.
4552  */
4553 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4554                            struct tg3_rx_prodring_set *dpr,
4555                            u32 opaque_key, int src_idx,
4556                            u32 dest_idx_unmasked)
4557 {
4558         struct tg3 *tp = tnapi->tp;
4559         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4560         struct ring_info *src_map, *dest_map;
4561         struct tg3_rx_prodring_set *spr = &tp->prodring[0];
4562         int dest_idx;
4563
4564         switch (opaque_key) {
4565         case RXD_OPAQUE_RING_STD:
4566                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4567                 dest_desc = &dpr->rx_std[dest_idx];
4568                 dest_map = &dpr->rx_std_buffers[dest_idx];
4569                 src_desc = &spr->rx_std[src_idx];
4570                 src_map = &spr->rx_std_buffers[src_idx];
4571                 break;
4572
4573         case RXD_OPAQUE_RING_JUMBO:
4574                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4575                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4576                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4577                 src_desc = &spr->rx_jmb[src_idx].std;
4578                 src_map = &spr->rx_jmb_buffers[src_idx];
4579                 break;
4580
4581         default:
4582                 return;
4583         }
4584
4585         dest_map->skb = src_map->skb;
4586         dma_unmap_addr_set(dest_map, mapping,
4587                            dma_unmap_addr(src_map, mapping));
4588         dest_desc->addr_hi = src_desc->addr_hi;
4589         dest_desc->addr_lo = src_desc->addr_lo;
4590
4591         /* Ensure that the update to the skb happens after the physical
4592          * addresses have been transferred to the new BD location.
4593          */
4594         smp_wmb();
4595
4596         src_map->skb = NULL;
4597 }
4598
4599 /* The RX ring scheme is composed of multiple rings which post fresh
4600  * buffers to the chip, and one special ring the chip uses to report
4601  * status back to the host.
4602  *
4603  * The special ring reports the status of received packets to the
4604  * host.  The chip does not write into the original descriptor the
4605  * RX buffer was obtained from.  The chip simply takes the original
4606  * descriptor as provided by the host, updates the status and length
4607  * field, then writes this into the next status ring entry.
4608  *
4609  * Each ring the host uses to post buffers to the chip is described
4610  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4611  * it is first placed into the on-chip ram.  When the packet's length
4612  * is known, it walks down the TG3_BDINFO entries to select the ring.
4613  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4614  * which is within the range of the new packet's length is chosen.
4615  *
4616  * The "separate ring for rx status" scheme may sound queer, but it makes
4617  * sense from a cache coherency perspective.  If only the host writes
4618  * to the buffer post rings, and only the chip writes to the rx status
4619  * rings, then cache lines never move beyond shared-modified state.
4620  * If both the host and chip were to write into the same ring, cache line
4621  * eviction could occur since both entities want it in an exclusive state.
4622  */
4623 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4624 {
4625         struct tg3 *tp = tnapi->tp;
4626         u32 work_mask, rx_std_posted = 0;
4627         u32 std_prod_idx, jmb_prod_idx;
4628         u32 sw_idx = tnapi->rx_rcb_ptr;
4629         u16 hw_idx;
4630         int received;
4631         struct tg3_rx_prodring_set *tpr = tnapi->prodring;
4632
4633         hw_idx = *(tnapi->rx_rcb_prod_idx);
4634         /*
4635          * We need to order the read of hw_idx and the read of
4636          * the opaque cookie.
4637          */
4638         rmb();
4639         work_mask = 0;
4640         received = 0;
4641         std_prod_idx = tpr->rx_std_prod_idx;
4642         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4643         while (sw_idx != hw_idx && budget > 0) {
4644                 struct ring_info *ri;
4645                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4646                 unsigned int len;
4647                 struct sk_buff *skb;
4648                 dma_addr_t dma_addr;
4649                 u32 opaque_key, desc_idx, *post_ptr;
4650                 bool hw_vlan __maybe_unused = false;
4651                 u16 vtag __maybe_unused = 0;
4652
4653                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4654                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4655                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4656                         ri = &tp->prodring[0].rx_std_buffers[desc_idx];
4657                         dma_addr = dma_unmap_addr(ri, mapping);
4658                         skb = ri->skb;
4659                         post_ptr = &std_prod_idx;
4660                         rx_std_posted++;
4661                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4662                         ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
4663                         dma_addr = dma_unmap_addr(ri, mapping);
4664                         skb = ri->skb;
4665                         post_ptr = &jmb_prod_idx;
4666                 } else
4667                         goto next_pkt_nopost;
4668
4669                 work_mask |= opaque_key;
4670
4671                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4672                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4673                 drop_it:
4674                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4675                                        desc_idx, *post_ptr);
4676                 drop_it_no_recycle:
4677                         /* Other statistics kept track of by card. */
4678                         tp->net_stats.rx_dropped++;
4679                         goto next_pkt;
4680                 }
4681
4682                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4683                       ETH_FCS_LEN;
4684
4685                 if (len > TG3_RX_COPY_THRESH(tp)) {
4686                         int skb_size;
4687
4688                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4689                                                     *post_ptr);
4690                         if (skb_size < 0)
4691                                 goto drop_it;
4692
4693                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4694                                          PCI_DMA_FROMDEVICE);
4695
4696                         /* Ensure that the update to the skb happens
4697                          * after the usage of the old DMA mapping.
4698                          */
4699                         smp_wmb();
4700
4701                         ri->skb = NULL;
4702
4703                         skb_put(skb, len);
4704                 } else {
4705                         struct sk_buff *copy_skb;
4706
4707                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4708                                        desc_idx, *post_ptr);
4709
4710                         copy_skb = netdev_alloc_skb(tp->dev, len + VLAN_HLEN +
4711                                                     TG3_RAW_IP_ALIGN);
4712                         if (copy_skb == NULL)
4713                                 goto drop_it_no_recycle;
4714
4715                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN + VLAN_HLEN);
4716                         skb_put(copy_skb, len);
4717                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4718                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4719                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4720
4721                         /* We'll reuse the original ring buffer. */
4722                         skb = copy_skb;
4723                 }
4724
4725                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4726                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4727                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4728                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4729                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4730                 else
4731                         skb->ip_summed = CHECKSUM_NONE;
4732
4733                 skb->protocol = eth_type_trans(skb, tp->dev);
4734
4735                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4736                     skb->protocol != htons(ETH_P_8021Q)) {
4737                         dev_kfree_skb(skb);
4738                         goto next_pkt;
4739                 }
4740
4741                 if (desc->type_flags & RXD_FLAG_VLAN &&
4742                     !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) {
4743                         vtag = desc->err_vlan & RXD_VLAN_MASK;
4744 #if TG3_VLAN_TAG_USED
4745                         if (tp->vlgrp)
4746                                 hw_vlan = true;
4747                         else
4748 #endif
4749                         {
4750                                 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
4751                                                     __skb_push(skb, VLAN_HLEN);
4752
4753                                 memmove(ve, skb->data + VLAN_HLEN,
4754                                         ETH_ALEN * 2);
4755                                 ve->h_vlan_proto = htons(ETH_P_8021Q);
4756                                 ve->h_vlan_TCI = htons(vtag);
4757                         }
4758                 }
4759
4760 #if TG3_VLAN_TAG_USED
4761                 if (hw_vlan)
4762                         vlan_gro_receive(&tnapi->napi, tp->vlgrp, vtag, skb);
4763                 else
4764 #endif
4765                         napi_gro_receive(&tnapi->napi, skb);
4766
4767                 received++;
4768                 budget--;
4769
4770 next_pkt:
4771                 (*post_ptr)++;
4772
4773                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4774                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4775                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4776                                      tpr->rx_std_prod_idx);
4777                         work_mask &= ~RXD_OPAQUE_RING_STD;
4778                         rx_std_posted = 0;
4779                 }
4780 next_pkt_nopost:
4781                 sw_idx++;
4782                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4783
4784                 /* Refresh hw_idx to see if there is new work */
4785                 if (sw_idx == hw_idx) {
4786                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4787                         rmb();
4788                 }
4789         }
4790
4791         /* ACK the status ring. */
4792         tnapi->rx_rcb_ptr = sw_idx;
4793         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4794
4795         /* Refill RX ring(s). */
4796         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4797                 if (work_mask & RXD_OPAQUE_RING_STD) {
4798                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4799                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4800                                      tpr->rx_std_prod_idx);
4801                 }
4802                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4803                         tpr->rx_jmb_prod_idx = jmb_prod_idx %
4804                                                TG3_RX_JUMBO_RING_SIZE;
4805                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4806                                      tpr->rx_jmb_prod_idx);
4807                 }
4808                 mmiowb();
4809         } else if (work_mask) {
4810                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4811                  * updated before the producer indices can be updated.
4812                  */
4813                 smp_wmb();
4814
4815                 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4816                 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
4817
4818                 if (tnapi != &tp->napi[1])
4819                         napi_schedule(&tp->napi[1].napi);
4820         }
4821
4822         return received;
4823 }
4824
4825 static void tg3_poll_link(struct tg3 *tp)
4826 {
4827         /* handle link change and other phy events */
4828         if (!(tp->tg3_flags &
4829               (TG3_FLAG_USE_LINKCHG_REG |
4830                TG3_FLAG_POLL_SERDES))) {
4831                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4832
4833                 if (sblk->status & SD_STATUS_LINK_CHG) {
4834                         sblk->status = SD_STATUS_UPDATED |
4835                                        (sblk->status & ~SD_STATUS_LINK_CHG);
4836                         spin_lock(&tp->lock);
4837                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4838                                 tw32_f(MAC_STATUS,
4839                                      (MAC_STATUS_SYNC_CHANGED |
4840                                       MAC_STATUS_CFG_CHANGED |
4841                                       MAC_STATUS_MI_COMPLETION |
4842                                       MAC_STATUS_LNKSTATE_CHANGED));
4843                                 udelay(40);
4844                         } else
4845                                 tg3_setup_phy(tp, 0);
4846                         spin_unlock(&tp->lock);
4847                 }
4848         }
4849 }
4850
4851 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4852                                 struct tg3_rx_prodring_set *dpr,
4853                                 struct tg3_rx_prodring_set *spr)
4854 {
4855         u32 si, di, cpycnt, src_prod_idx;
4856         int i, err = 0;
4857
4858         while (1) {
4859                 src_prod_idx = spr->rx_std_prod_idx;
4860
4861                 /* Make sure updates to the rx_std_buffers[] entries and the
4862                  * standard producer index are seen in the correct order.
4863                  */
4864                 smp_rmb();
4865
4866                 if (spr->rx_std_cons_idx == src_prod_idx)
4867                         break;
4868
4869                 if (spr->rx_std_cons_idx < src_prod_idx)
4870                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4871                 else
4872                         cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4873
4874                 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4875
4876                 si = spr->rx_std_cons_idx;
4877                 di = dpr->rx_std_prod_idx;
4878
4879                 for (i = di; i < di + cpycnt; i++) {
4880                         if (dpr->rx_std_buffers[i].skb) {
4881                                 cpycnt = i - di;
4882                                 err = -ENOSPC;
4883                                 break;
4884                         }
4885                 }
4886
4887                 if (!cpycnt)
4888                         break;
4889
4890                 /* Ensure that updates to the rx_std_buffers ring and the
4891                  * shadowed hardware producer ring from tg3_recycle_skb() are
4892                  * ordered correctly WRT the skb check above.
4893                  */
4894                 smp_rmb();
4895
4896                 memcpy(&dpr->rx_std_buffers[di],
4897                        &spr->rx_std_buffers[si],
4898                        cpycnt * sizeof(struct ring_info));
4899
4900                 for (i = 0; i < cpycnt; i++, di++, si++) {
4901                         struct tg3_rx_buffer_desc *sbd, *dbd;
4902                         sbd = &spr->rx_std[si];
4903                         dbd = &dpr->rx_std[di];
4904                         dbd->addr_hi = sbd->addr_hi;
4905                         dbd->addr_lo = sbd->addr_lo;
4906                 }
4907
4908                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4909                                        TG3_RX_RING_SIZE;
4910                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4911                                        TG3_RX_RING_SIZE;
4912         }
4913
4914         while (1) {
4915                 src_prod_idx = spr->rx_jmb_prod_idx;
4916
4917                 /* Make sure updates to the rx_jmb_buffers[] entries and
4918                  * the jumbo producer index are seen in the correct order.
4919                  */
4920                 smp_rmb();
4921
4922                 if (spr->rx_jmb_cons_idx == src_prod_idx)
4923                         break;
4924
4925                 if (spr->rx_jmb_cons_idx < src_prod_idx)
4926                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4927                 else
4928                         cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4929
4930                 cpycnt = min(cpycnt,
4931                              TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4932
4933                 si = spr->rx_jmb_cons_idx;
4934                 di = dpr->rx_jmb_prod_idx;
4935
4936                 for (i = di; i < di + cpycnt; i++) {
4937                         if (dpr->rx_jmb_buffers[i].skb) {
4938                                 cpycnt = i - di;
4939                                 err = -ENOSPC;
4940                                 break;
4941                         }
4942                 }
4943
4944                 if (!cpycnt)
4945                         break;
4946
4947                 /* Ensure that updates to the rx_jmb_buffers ring and the
4948                  * shadowed hardware producer ring from tg3_recycle_skb() are
4949                  * ordered correctly WRT the skb check above.
4950                  */
4951                 smp_rmb();
4952
4953                 memcpy(&dpr->rx_jmb_buffers[di],
4954                        &spr->rx_jmb_buffers[si],
4955                        cpycnt * sizeof(struct ring_info));
4956
4957                 for (i = 0; i < cpycnt; i++, di++, si++) {
4958                         struct tg3_rx_buffer_desc *sbd, *dbd;
4959                         sbd = &spr->rx_jmb[si].std;
4960                         dbd = &dpr->rx_jmb[di].std;
4961                         dbd->addr_hi = sbd->addr_hi;
4962                         dbd->addr_lo = sbd->addr_lo;
4963                 }
4964
4965                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4966                                        TG3_RX_JUMBO_RING_SIZE;
4967                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4968                                        TG3_RX_JUMBO_RING_SIZE;
4969         }
4970
4971         return err;
4972 }
4973
4974 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4975 {
4976         struct tg3 *tp = tnapi->tp;
4977
4978         /* run TX completion thread */
4979         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4980                 tg3_tx(tnapi);
4981                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4982                         return work_done;
4983         }
4984
4985         /* run RX thread, within the bounds set by NAPI.
4986          * All RX "locking" is done by ensuring outside
4987          * code synchronizes with tg3->napi.poll()
4988          */
4989         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4990                 work_done += tg3_rx(tnapi, budget - work_done);
4991
4992         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4993                 struct tg3_rx_prodring_set *dpr = &tp->prodring[0];
4994                 int i, err = 0;
4995                 u32 std_prod_idx = dpr->rx_std_prod_idx;
4996                 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
4997
4998                 for (i = 1; i < tp->irq_cnt; i++)
4999                         err |= tg3_rx_prodring_xfer(tp, dpr,
5000                                                     tp->napi[i].prodring);
5001
5002                 wmb();
5003
5004                 if (std_prod_idx != dpr->rx_std_prod_idx)
5005                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5006                                      dpr->rx_std_prod_idx);
5007
5008                 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5009                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5010                                      dpr->rx_jmb_prod_idx);
5011
5012                 mmiowb();
5013
5014                 if (err)
5015                         tw32_f(HOSTCC_MODE, tp->coal_now);
5016         }
5017
5018         return work_done;
5019 }
5020
5021 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5022 {
5023         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5024         struct tg3 *tp = tnapi->tp;
5025         int work_done = 0;
5026         struct tg3_hw_status *sblk = tnapi->hw_status;
5027
5028         while (1) {
5029                 work_done = tg3_poll_work(tnapi, work_done, budget);
5030
5031                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5032                         goto tx_recovery;
5033
5034                 if (unlikely(work_done >= budget))
5035                         break;
5036
5037                 /* tp->last_tag is used in tg3_int_reenable() below
5038                  * to tell the hw how much work has been processed,
5039                  * so we must read it before checking for more work.
5040                  */
5041                 tnapi->last_tag = sblk->status_tag;
5042                 tnapi->last_irq_tag = tnapi->last_tag;
5043                 rmb();
5044
5045                 /* check for RX/TX work to do */
5046                 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5047                            *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5048                         napi_complete(napi);
5049                         /* Reenable interrupts. */
5050                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5051                         mmiowb();
5052                         break;
5053                 }
5054         }
5055
5056         return work_done;
5057
5058 tx_recovery:
5059         /* work_done is guaranteed to be less than budget. */
5060         napi_complete(napi);
5061         schedule_work(&tp->reset_task);
5062         return work_done;
5063 }
5064
5065 static int tg3_poll(struct napi_struct *napi, int budget)
5066 {
5067         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5068         struct tg3 *tp = tnapi->tp;
5069         int work_done = 0;
5070         struct tg3_hw_status *sblk = tnapi->hw_status;
5071
5072         while (1) {
5073                 tg3_poll_link(tp);
5074
5075                 work_done = tg3_poll_work(tnapi, work_done, budget);
5076
5077                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5078                         goto tx_recovery;
5079
5080                 if (unlikely(work_done >= budget))
5081                         break;
5082
5083                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5084                         /* tp->last_tag is used in tg3_int_reenable() below
5085                          * to tell the hw how much work has been processed,
5086                          * so we must read it before checking for more work.
5087                          */
5088                         tnapi->last_tag = sblk->status_tag;
5089                         tnapi->last_irq_tag = tnapi->last_tag;
5090                         rmb();
5091                 } else
5092                         sblk->status &= ~SD_STATUS_UPDATED;
5093
5094                 if (likely(!tg3_has_work(tnapi))) {
5095                         napi_complete(napi);
5096                         tg3_int_reenable(tnapi);
5097                         break;
5098                 }
5099         }
5100
5101         return work_done;
5102
5103 tx_recovery:
5104         /* work_done is guaranteed to be less than budget. */
5105         napi_complete(napi);
5106         schedule_work(&tp->reset_task);
5107         return work_done;
5108 }
5109
5110 static void tg3_irq_quiesce(struct tg3 *tp)
5111 {
5112         int i;
5113
5114         BUG_ON(tp->irq_sync);
5115
5116         tp->irq_sync = 1;
5117         smp_mb();
5118
5119         for (i = 0; i < tp->irq_cnt; i++)
5120                 synchronize_irq(tp->napi[i].irq_vec);
5121 }
5122
5123 static inline int tg3_irq_sync(struct tg3 *tp)
5124 {
5125         return tp->irq_sync;
5126 }
5127
5128 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5129  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5130  * with as well.  Most of the time, this is not necessary except when
5131  * shutting down the device.
5132  */
5133 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5134 {
5135         spin_lock_bh(&tp->lock);
5136         if (irq_sync)
5137                 tg3_irq_quiesce(tp);
5138 }
5139
5140 static inline void tg3_full_unlock(struct tg3 *tp)
5141 {
5142         spin_unlock_bh(&tp->lock);
5143 }
5144
5145 /* One-shot MSI handler - Chip automatically disables interrupt
5146  * after sending MSI so driver doesn't have to do it.
5147  */
5148 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5149 {
5150         struct tg3_napi *tnapi = dev_id;
5151         struct tg3 *tp = tnapi->tp;
5152
5153         prefetch(tnapi->hw_status);
5154         if (tnapi->rx_rcb)
5155                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5156
5157         if (likely(!tg3_irq_sync(tp)))
5158                 napi_schedule(&tnapi->napi);
5159
5160         return IRQ_HANDLED;
5161 }
5162
5163 /* MSI ISR - No need to check for interrupt sharing and no need to
5164  * flush status block and interrupt mailbox. PCI ordering rules
5165  * guarantee that MSI will arrive after the status block.
5166  */
5167 static irqreturn_t tg3_msi(int irq, void *dev_id)
5168 {
5169         struct tg3_napi *tnapi = dev_id;
5170         struct tg3 *tp = tnapi->tp;
5171
5172         prefetch(tnapi->hw_status);
5173         if (tnapi->rx_rcb)
5174                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5175         /*
5176          * Writing any value to intr-mbox-0 clears PCI INTA# and
5177          * chip-internal interrupt pending events.
5178          * Writing non-zero to intr-mbox-0 additional tells the
5179          * NIC to stop sending us irqs, engaging "in-intr-handler"
5180          * event coalescing.
5181          */
5182         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5183         if (likely(!tg3_irq_sync(tp)))
5184                 napi_schedule(&tnapi->napi);
5185
5186         return IRQ_RETVAL(1);
5187 }
5188
5189 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5190 {
5191         struct tg3_napi *tnapi = dev_id;
5192         struct tg3 *tp = tnapi->tp;
5193         struct tg3_hw_status *sblk = tnapi->hw_status;
5194         unsigned int handled = 1;
5195
5196         /* In INTx mode, it is possible for the interrupt to arrive at
5197          * the CPU before the status block posted prior to the interrupt.
5198          * Reading the PCI State register will confirm whether the
5199          * interrupt is ours and will flush the status block.
5200          */
5201         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5202                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5203                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5204                         handled = 0;
5205                         goto out;
5206                 }
5207         }
5208
5209         /*
5210          * Writing any value to intr-mbox-0 clears PCI INTA# and
5211          * chip-internal interrupt pending events.
5212          * Writing non-zero to intr-mbox-0 additional tells the
5213          * NIC to stop sending us irqs, engaging "in-intr-handler"
5214          * event coalescing.
5215          *
5216          * Flush the mailbox to de-assert the IRQ immediately to prevent
5217          * spurious interrupts.  The flush impacts performance but
5218          * excessive spurious interrupts can be worse in some cases.
5219          */
5220         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5221         if (tg3_irq_sync(tp))
5222                 goto out;
5223         sblk->status &= ~SD_STATUS_UPDATED;
5224         if (likely(tg3_has_work(tnapi))) {
5225                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5226                 napi_schedule(&tnapi->napi);
5227         } else {
5228                 /* No work, shared interrupt perhaps?  re-enable
5229                  * interrupts, and flush that PCI write
5230                  */
5231                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5232                                0x00000000);
5233         }
5234 out:
5235         return IRQ_RETVAL(handled);
5236 }
5237
5238 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5239 {
5240         struct tg3_napi *tnapi = dev_id;
5241         struct tg3 *tp = tnapi->tp;
5242         struct tg3_hw_status *sblk = tnapi->hw_status;
5243         unsigned int handled = 1;
5244
5245         /* In INTx mode, it is possible for the interrupt to arrive at
5246          * the CPU before the status block posted prior to the interrupt.
5247          * Reading the PCI State register will confirm whether the
5248          * interrupt is ours and will flush the status block.
5249          */
5250         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5251                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5252                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5253                         handled = 0;
5254                         goto out;
5255                 }
5256         }
5257
5258         /*
5259          * writing any value to intr-mbox-0 clears PCI INTA# and
5260          * chip-internal interrupt pending events.
5261          * writing non-zero to intr-mbox-0 additional tells the
5262          * NIC to stop sending us irqs, engaging "in-intr-handler"
5263          * event coalescing.
5264          *
5265          * Flush the mailbox to de-assert the IRQ immediately to prevent
5266          * spurious interrupts.  The flush impacts performance but
5267          * excessive spurious interrupts can be worse in some cases.
5268          */
5269         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5270
5271         /*
5272          * In a shared interrupt configuration, sometimes other devices'
5273          * interrupts will scream.  We record the current status tag here
5274          * so that the above check can report that the screaming interrupts
5275          * are unhandled.  Eventually they will be silenced.
5276          */
5277         tnapi->last_irq_tag = sblk->status_tag;
5278
5279         if (tg3_irq_sync(tp))
5280                 goto out;
5281
5282         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5283
5284         napi_schedule(&tnapi->napi);
5285
5286 out:
5287         return IRQ_RETVAL(handled);
5288 }
5289
5290 /* ISR for interrupt test */
5291 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5292 {
5293         struct tg3_napi *tnapi = dev_id;
5294         struct tg3 *tp = tnapi->tp;
5295         struct tg3_hw_status *sblk = tnapi->hw_status;
5296
5297         if ((sblk->status & SD_STATUS_UPDATED) ||
5298             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5299                 tg3_disable_ints(tp);
5300                 return IRQ_RETVAL(1);
5301         }
5302         return IRQ_RETVAL(0);
5303 }
5304
5305 static int tg3_init_hw(struct tg3 *, int);
5306 static int tg3_halt(struct tg3 *, int, int);
5307
5308 /* Restart hardware after configuration changes, self-test, etc.
5309  * Invoked with tp->lock held.
5310  */
5311 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5312         __releases(tp->lock)
5313         __acquires(tp->lock)
5314 {
5315         int err;
5316
5317         err = tg3_init_hw(tp, reset_phy);
5318         if (err) {
5319                 netdev_err(tp->dev,
5320                            "Failed to re-initialize device, aborting\n");
5321                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5322                 tg3_full_unlock(tp);
5323                 del_timer_sync(&tp->timer);
5324                 tp->irq_sync = 0;
5325                 tg3_napi_enable(tp);
5326                 dev_close(tp->dev);
5327                 tg3_full_lock(tp, 0);
5328         }
5329         return err;
5330 }
5331
5332 #ifdef CONFIG_NET_POLL_CONTROLLER
5333 static void tg3_poll_controller(struct net_device *dev)
5334 {
5335         int i;
5336         struct tg3 *tp = netdev_priv(dev);
5337
5338         for (i = 0; i < tp->irq_cnt; i++)
5339                 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5340 }
5341 #endif
5342
5343 static void tg3_reset_task(struct work_struct *work)
5344 {
5345         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5346         int err;
5347         unsigned int restart_timer;
5348
5349         tg3_full_lock(tp, 0);
5350
5351         if (!netif_running(tp->dev)) {
5352                 tg3_full_unlock(tp);
5353                 return;
5354         }
5355
5356         tg3_full_unlock(tp);
5357
5358         tg3_phy_stop(tp);
5359
5360         tg3_netif_stop(tp);
5361
5362         tg3_full_lock(tp, 1);
5363
5364         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5365         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5366
5367         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5368                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5369                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5370                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5371                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5372         }
5373
5374         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5375         err = tg3_init_hw(tp, 1);
5376         if (err)
5377                 goto out;
5378
5379         tg3_netif_start(tp);
5380
5381         if (restart_timer)
5382                 mod_timer(&tp->timer, jiffies + 1);
5383
5384 out:
5385         tg3_full_unlock(tp);
5386
5387         if (!err)
5388                 tg3_phy_start(tp);
5389 }
5390
5391 static void tg3_dump_short_state(struct tg3 *tp)
5392 {
5393         netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5394                    tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5395         netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5396                    tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5397 }
5398
5399 static void tg3_tx_timeout(struct net_device *dev)
5400 {
5401         struct tg3 *tp = netdev_priv(dev);
5402
5403         if (netif_msg_tx_err(tp)) {
5404                 netdev_err(dev, "transmit timed out, resetting\n");
5405                 tg3_dump_short_state(tp);
5406         }
5407
5408         schedule_work(&tp->reset_task);
5409 }
5410
5411 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5412 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5413 {
5414         u32 base = (u32) mapping & 0xffffffff;
5415
5416         return ((base > 0xffffdcc0) &&
5417                 (base + len + 8 < base));
5418 }
5419
5420 /* Test for DMA addresses > 40-bit */
5421 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5422                                           int len)
5423 {
5424 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5425         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5426                 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5427         return 0;
5428 #else
5429         return 0;
5430 #endif
5431 }
5432
5433 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5434
5435 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5436 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5437                                        struct sk_buff *skb, u32 last_plus_one,
5438                                        u32 *start, u32 base_flags, u32 mss)
5439 {
5440         struct tg3 *tp = tnapi->tp;
5441         struct sk_buff *new_skb;
5442         dma_addr_t new_addr = 0;
5443         u32 entry = *start;
5444         int i, ret = 0;
5445
5446         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5447                 new_skb = skb_copy(skb, GFP_ATOMIC);
5448         else {
5449                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5450
5451                 new_skb = skb_copy_expand(skb,
5452                                           skb_headroom(skb) + more_headroom,
5453                                           skb_tailroom(skb), GFP_ATOMIC);
5454         }
5455
5456         if (!new_skb) {
5457                 ret = -1;
5458         } else {
5459                 /* New SKB is guaranteed to be linear. */
5460                 entry = *start;
5461                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5462                                           PCI_DMA_TODEVICE);
5463                 /* Make sure the mapping succeeded */
5464                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5465                         ret = -1;
5466                         dev_kfree_skb(new_skb);
5467                         new_skb = NULL;
5468
5469                 /* Make sure new skb does not cross any 4G boundaries.
5470                  * Drop the packet if it does.
5471                  */
5472                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5473                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5474                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5475                                          PCI_DMA_TODEVICE);
5476                         ret = -1;
5477                         dev_kfree_skb(new_skb);
5478                         new_skb = NULL;
5479                 } else {
5480                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5481                                     base_flags, 1 | (mss << 1));
5482                         *start = NEXT_TX(entry);
5483                 }
5484         }
5485
5486         /* Now clean up the sw ring entries. */
5487         i = 0;
5488         while (entry != last_plus_one) {
5489                 int len;
5490
5491                 if (i == 0)
5492                         len = skb_headlen(skb);
5493                 else
5494                         len = skb_shinfo(skb)->frags[i-1].size;
5495
5496                 pci_unmap_single(tp->pdev,
5497                                  dma_unmap_addr(&tnapi->tx_buffers[entry],
5498                                                 mapping),
5499                                  len, PCI_DMA_TODEVICE);
5500                 if (i == 0) {
5501                         tnapi->tx_buffers[entry].skb = new_skb;
5502                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5503                                            new_addr);
5504                 } else {
5505                         tnapi->tx_buffers[entry].skb = NULL;
5506                 }
5507                 entry = NEXT_TX(entry);
5508                 i++;
5509         }
5510
5511         dev_kfree_skb(skb);
5512
5513         return ret;
5514 }
5515
5516 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5517                         dma_addr_t mapping, int len, u32 flags,
5518                         u32 mss_and_is_end)
5519 {
5520         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5521         int is_end = (mss_and_is_end & 0x1);
5522         u32 mss = (mss_and_is_end >> 1);
5523         u32 vlan_tag = 0;
5524
5525         if (is_end)
5526                 flags |= TXD_FLAG_END;
5527         if (flags & TXD_FLAG_VLAN) {
5528                 vlan_tag = flags >> 16;
5529                 flags &= 0xffff;
5530         }
5531         vlan_tag |= (mss << TXD_MSS_SHIFT);
5532
5533         txd->addr_hi = ((u64) mapping >> 32);
5534         txd->addr_lo = ((u64) mapping & 0xffffffff);
5535         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5536         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5537 }
5538
5539 /* hard_start_xmit for devices that don't have any bugs and
5540  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5541  */
5542 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5543                                   struct net_device *dev)
5544 {
5545         struct tg3 *tp = netdev_priv(dev);
5546         u32 len, entry, base_flags, mss;
5547         dma_addr_t mapping;
5548         struct tg3_napi *tnapi;
5549         struct netdev_queue *txq;
5550         unsigned int i, last;
5551
5552         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5553         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5554         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5555                 tnapi++;
5556
5557         /* We are running in BH disabled context with netif_tx_lock
5558          * and TX reclaim runs via tp->napi.poll inside of a software
5559          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5560          * no IRQ context deadlocks to worry about either.  Rejoice!
5561          */
5562         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5563                 if (!netif_tx_queue_stopped(txq)) {
5564                         netif_tx_stop_queue(txq);
5565
5566                         /* This is a hard error, log it. */
5567                         netdev_err(dev,
5568                                    "BUG! Tx Ring full when queue awake!\n");
5569                 }
5570                 return NETDEV_TX_BUSY;
5571         }
5572
5573         entry = tnapi->tx_prod;
5574         base_flags = 0;
5575         mss = skb_shinfo(skb)->gso_size;
5576         if (mss) {
5577                 int tcp_opt_len, ip_tcp_len;
5578                 u32 hdrlen;
5579
5580                 if (skb_header_cloned(skb) &&
5581                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5582                         dev_kfree_skb(skb);
5583                         goto out_unlock;
5584                 }
5585
5586                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5587                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5588                 else {
5589                         struct iphdr *iph = ip_hdr(skb);
5590
5591                         tcp_opt_len = tcp_optlen(skb);
5592                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5593
5594                         iph->check = 0;
5595                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5596                         hdrlen = ip_tcp_len + tcp_opt_len;
5597                 }
5598
5599                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5600                         mss |= (hdrlen & 0xc) << 12;
5601                         if (hdrlen & 0x10)
5602                                 base_flags |= 0x00000010;
5603                         base_flags |= (hdrlen & 0x3e0) << 5;
5604                 } else
5605                         mss |= hdrlen << 9;
5606
5607                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5608                                TXD_FLAG_CPU_POST_DMA);
5609
5610                 tcp_hdr(skb)->check = 0;
5611
5612         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5613                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5614         }
5615
5616 #if TG3_VLAN_TAG_USED
5617         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5618                 base_flags |= (TXD_FLAG_VLAN |
5619                                (vlan_tx_tag_get(skb) << 16));
5620 #endif
5621
5622         len = skb_headlen(skb);
5623
5624         /* Queue skb data, a.k.a. the main skb fragment. */
5625         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5626         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5627                 dev_kfree_skb(skb);
5628                 goto out_unlock;
5629         }
5630
5631         tnapi->tx_buffers[entry].skb = skb;
5632         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5633
5634         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5635             !mss && skb->len > ETH_DATA_LEN)
5636                 base_flags |= TXD_FLAG_JMB_PKT;
5637
5638         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5639                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5640
5641         entry = NEXT_TX(entry);
5642
5643         /* Now loop through additional data fragments, and queue them. */
5644         if (skb_shinfo(skb)->nr_frags > 0) {
5645                 last = skb_shinfo(skb)->nr_frags - 1;
5646                 for (i = 0; i <= last; i++) {
5647                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5648
5649                         len = frag->size;
5650                         mapping = pci_map_page(tp->pdev,
5651                                                frag->page,
5652                                                frag->page_offset,
5653                                                len, PCI_DMA_TODEVICE);
5654                         if (pci_dma_mapping_error(tp->pdev, mapping))
5655                                 goto dma_error;
5656
5657                         tnapi->tx_buffers[entry].skb = NULL;
5658                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5659                                            mapping);
5660
5661                         tg3_set_txd(tnapi, entry, mapping, len,
5662                                     base_flags, (i == last) | (mss << 1));
5663
5664                         entry = NEXT_TX(entry);
5665                 }
5666         }
5667
5668         /* Packets are ready, update Tx producer idx local and on card. */
5669         tw32_tx_mbox(tnapi->prodmbox, entry);
5670
5671         tnapi->tx_prod = entry;
5672         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5673                 netif_tx_stop_queue(txq);
5674
5675                 /* netif_tx_stop_queue() must be done before checking
5676                  * checking tx index in tg3_tx_avail() below, because in
5677                  * tg3_tx(), we update tx index before checking for
5678                  * netif_tx_queue_stopped().
5679                  */
5680                 smp_mb();
5681                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5682                         netif_tx_wake_queue(txq);
5683         }
5684
5685 out_unlock:
5686         mmiowb();
5687
5688         return NETDEV_TX_OK;
5689
5690 dma_error:
5691         last = i;
5692         entry = tnapi->tx_prod;
5693         tnapi->tx_buffers[entry].skb = NULL;
5694         pci_unmap_single(tp->pdev,
5695                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5696                          skb_headlen(skb),
5697                          PCI_DMA_TODEVICE);
5698         for (i = 0; i <= last; i++) {
5699                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5700                 entry = NEXT_TX(entry);
5701
5702                 pci_unmap_page(tp->pdev,
5703                                dma_unmap_addr(&tnapi->tx_buffers[entry],
5704                                               mapping),
5705                                frag->size, PCI_DMA_TODEVICE);
5706         }
5707
5708         dev_kfree_skb(skb);
5709         return NETDEV_TX_OK;
5710 }
5711
5712 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5713                                           struct net_device *);
5714
5715 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5716  * TSO header is greater than 80 bytes.
5717  */
5718 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5719 {
5720         struct sk_buff *segs, *nskb;
5721         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5722
5723         /* Estimate the number of fragments in the worst case */
5724         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5725                 netif_stop_queue(tp->dev);
5726
5727                 /* netif_tx_stop_queue() must be done before checking
5728                  * checking tx index in tg3_tx_avail() below, because in
5729                  * tg3_tx(), we update tx index before checking for
5730                  * netif_tx_queue_stopped().
5731                  */
5732                 smp_mb();
5733                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5734                         return NETDEV_TX_BUSY;
5735
5736                 netif_wake_queue(tp->dev);
5737         }
5738
5739         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5740         if (IS_ERR(segs))
5741                 goto tg3_tso_bug_end;
5742
5743         do {
5744                 nskb = segs;
5745                 segs = segs->next;
5746                 nskb->next = NULL;
5747                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5748         } while (segs);
5749
5750 tg3_tso_bug_end:
5751         dev_kfree_skb(skb);
5752
5753         return NETDEV_TX_OK;
5754 }
5755
5756 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5757  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5758  */
5759 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5760                                           struct net_device *dev)
5761 {
5762         struct tg3 *tp = netdev_priv(dev);
5763         u32 len, entry, base_flags, mss;
5764         int would_hit_hwbug;
5765         dma_addr_t mapping;
5766         struct tg3_napi *tnapi;
5767         struct netdev_queue *txq;
5768         unsigned int i, last;
5769
5770         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5771         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5772         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5773                 tnapi++;
5774
5775         /* We are running in BH disabled context with netif_tx_lock
5776          * and TX reclaim runs via tp->napi.poll inside of a software
5777          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5778          * no IRQ context deadlocks to worry about either.  Rejoice!
5779          */
5780         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5781                 if (!netif_tx_queue_stopped(txq)) {
5782                         netif_tx_stop_queue(txq);
5783
5784                         /* This is a hard error, log it. */
5785                         netdev_err(dev,
5786                                    "BUG! Tx Ring full when queue awake!\n");
5787                 }
5788                 return NETDEV_TX_BUSY;
5789         }
5790
5791         entry = tnapi->tx_prod;
5792         base_flags = 0;
5793         if (skb->ip_summed == CHECKSUM_PARTIAL)
5794                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5795
5796         mss = skb_shinfo(skb)->gso_size;
5797         if (mss) {
5798                 struct iphdr *iph;
5799                 u32 tcp_opt_len, hdr_len;
5800
5801                 if (skb_header_cloned(skb) &&
5802                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5803                         dev_kfree_skb(skb);
5804                         goto out_unlock;
5805                 }
5806
5807                 iph = ip_hdr(skb);
5808                 tcp_opt_len = tcp_optlen(skb);
5809
5810                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
5811                         hdr_len = skb_headlen(skb) - ETH_HLEN;
5812                 } else {
5813                         u32 ip_tcp_len;
5814
5815                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5816                         hdr_len = ip_tcp_len + tcp_opt_len;
5817
5818                         iph->check = 0;
5819                         iph->tot_len = htons(mss + hdr_len);
5820                 }
5821
5822                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5823                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5824                         return tg3_tso_bug(tp, skb);
5825
5826                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5827                                TXD_FLAG_CPU_POST_DMA);
5828
5829                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5830                         tcp_hdr(skb)->check = 0;
5831                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5832                 } else
5833                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5834                                                                  iph->daddr, 0,
5835                                                                  IPPROTO_TCP,
5836                                                                  0);
5837
5838                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5839                         mss |= (hdr_len & 0xc) << 12;
5840                         if (hdr_len & 0x10)
5841                                 base_flags |= 0x00000010;
5842                         base_flags |= (hdr_len & 0x3e0) << 5;
5843                 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5844                         mss |= hdr_len << 9;
5845                 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5846                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5847                         if (tcp_opt_len || iph->ihl > 5) {
5848                                 int tsflags;
5849
5850                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5851                                 mss |= (tsflags << 11);
5852                         }
5853                 } else {
5854                         if (tcp_opt_len || iph->ihl > 5) {
5855                                 int tsflags;
5856
5857                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5858                                 base_flags |= tsflags << 12;
5859                         }
5860                 }
5861         }
5862 #if TG3_VLAN_TAG_USED
5863         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5864                 base_flags |= (TXD_FLAG_VLAN |
5865                                (vlan_tx_tag_get(skb) << 16));
5866 #endif
5867
5868         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5869             !mss && skb->len > ETH_DATA_LEN)
5870                 base_flags |= TXD_FLAG_JMB_PKT;
5871
5872         len = skb_headlen(skb);
5873
5874         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5875         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5876                 dev_kfree_skb(skb);
5877                 goto out_unlock;
5878         }
5879
5880         tnapi->tx_buffers[entry].skb = skb;
5881         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5882
5883         would_hit_hwbug = 0;
5884
5885         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5886                 would_hit_hwbug = 1;
5887
5888         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5889             tg3_4g_overflow_test(mapping, len))
5890                 would_hit_hwbug = 1;
5891
5892         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5893             tg3_40bit_overflow_test(tp, mapping, len))
5894                 would_hit_hwbug = 1;
5895
5896         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5897                 would_hit_hwbug = 1;
5898
5899         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5900                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5901
5902         entry = NEXT_TX(entry);
5903
5904         /* Now loop through additional data fragments, and queue them. */
5905         if (skb_shinfo(skb)->nr_frags > 0) {
5906                 last = skb_shinfo(skb)->nr_frags - 1;
5907                 for (i = 0; i <= last; i++) {
5908                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5909
5910                         len = frag->size;
5911                         mapping = pci_map_page(tp->pdev,
5912                                                frag->page,
5913                                                frag->page_offset,
5914                                                len, PCI_DMA_TODEVICE);
5915
5916                         tnapi->tx_buffers[entry].skb = NULL;
5917                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5918                                            mapping);
5919                         if (pci_dma_mapping_error(tp->pdev, mapping))
5920                                 goto dma_error;
5921
5922                         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5923                             len <= 8)
5924                                 would_hit_hwbug = 1;
5925
5926                         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5927                             tg3_4g_overflow_test(mapping, len))
5928                                 would_hit_hwbug = 1;
5929
5930                         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5931                             tg3_40bit_overflow_test(tp, mapping, len))
5932                                 would_hit_hwbug = 1;
5933
5934                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5935                                 tg3_set_txd(tnapi, entry, mapping, len,
5936                                             base_flags, (i == last)|(mss << 1));
5937                         else
5938                                 tg3_set_txd(tnapi, entry, mapping, len,
5939                                             base_flags, (i == last));
5940
5941                         entry = NEXT_TX(entry);
5942                 }
5943         }
5944
5945         if (would_hit_hwbug) {
5946                 u32 last_plus_one = entry;
5947                 u32 start;
5948
5949                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5950                 start &= (TG3_TX_RING_SIZE - 1);
5951
5952                 /* If the workaround fails due to memory/mapping
5953                  * failure, silently drop this packet.
5954                  */
5955                 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
5956                                                 &start, base_flags, mss))
5957                         goto out_unlock;
5958
5959                 entry = start;
5960         }
5961
5962         /* Packets are ready, update Tx producer idx local and on card. */
5963         tw32_tx_mbox(tnapi->prodmbox, entry);
5964
5965         tnapi->tx_prod = entry;
5966         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5967                 netif_tx_stop_queue(txq);
5968
5969                 /* netif_tx_stop_queue() must be done before checking
5970                  * checking tx index in tg3_tx_avail() below, because in
5971                  * tg3_tx(), we update tx index before checking for
5972                  * netif_tx_queue_stopped().
5973                  */
5974                 smp_mb();
5975                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5976                         netif_tx_wake_queue(txq);
5977         }
5978
5979 out_unlock:
5980         mmiowb();
5981
5982         return NETDEV_TX_OK;
5983
5984 dma_error:
5985         last = i;
5986         entry = tnapi->tx_prod;
5987         tnapi->tx_buffers[entry].skb = NULL;
5988         pci_unmap_single(tp->pdev,
5989                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5990                          skb_headlen(skb),
5991                          PCI_DMA_TODEVICE);
5992         for (i = 0; i <= last; i++) {
5993                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5994                 entry = NEXT_TX(entry);
5995
5996                 pci_unmap_page(tp->pdev,
5997                                dma_unmap_addr(&tnapi->tx_buffers[entry],
5998                                               mapping),
5999                                frag->size, PCI_DMA_TODEVICE);
6000         }
6001
6002         dev_kfree_skb(skb);
6003         return NETDEV_TX_OK;
6004 }
6005
6006 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
6007                                int new_mtu)
6008 {
6009         dev->mtu = new_mtu;
6010
6011         if (new_mtu > ETH_DATA_LEN) {
6012                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6013                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
6014                         ethtool_op_set_tso(dev, 0);
6015                 } else {
6016                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
6017                 }
6018         } else {
6019                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6020                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
6021                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
6022         }
6023 }
6024
6025 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
6026 {
6027         struct tg3 *tp = netdev_priv(dev);
6028         int err;
6029
6030         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
6031                 return -EINVAL;
6032
6033         if (!netif_running(dev)) {
6034                 /* We'll just catch it later when the
6035                  * device is up'd.
6036                  */
6037                 tg3_set_mtu(dev, tp, new_mtu);
6038                 return 0;
6039         }
6040
6041         tg3_phy_stop(tp);
6042
6043         tg3_netif_stop(tp);
6044
6045         tg3_full_lock(tp, 1);
6046
6047         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6048
6049         tg3_set_mtu(dev, tp, new_mtu);
6050
6051         err = tg3_restart_hw(tp, 0);
6052
6053         if (!err)
6054                 tg3_netif_start(tp);
6055
6056         tg3_full_unlock(tp);
6057
6058         if (!err)
6059                 tg3_phy_start(tp);
6060
6061         return err;
6062 }
6063
6064 static void tg3_rx_prodring_free(struct tg3 *tp,
6065                                  struct tg3_rx_prodring_set *tpr)
6066 {
6067         int i;
6068
6069         if (tpr != &tp->prodring[0]) {
6070                 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
6071                      i = (i + 1) % TG3_RX_RING_SIZE)
6072                         tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6073                                         tp->rx_pkt_map_sz);
6074
6075                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6076                         for (i = tpr->rx_jmb_cons_idx;
6077                              i != tpr->rx_jmb_prod_idx;
6078                              i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
6079                                 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6080                                                 TG3_RX_JMB_MAP_SZ);
6081                         }
6082                 }
6083
6084                 return;
6085         }
6086
6087         for (i = 0; i < TG3_RX_RING_SIZE; i++)
6088                 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6089                                 tp->rx_pkt_map_sz);
6090
6091         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6092                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
6093                         tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6094                                         TG3_RX_JMB_MAP_SZ);
6095         }
6096 }
6097
6098 /* Initialize rx rings for packet processing.
6099  *
6100  * The chip has been shut down and the driver detached from
6101  * the networking, so no interrupts or new tx packets will
6102  * end up in the driver.  tp->{tx,}lock are held and thus
6103  * we may not sleep.
6104  */
6105 static int tg3_rx_prodring_alloc(struct tg3 *tp,
6106                                  struct tg3_rx_prodring_set *tpr)
6107 {
6108         u32 i, rx_pkt_dma_sz;
6109
6110         tpr->rx_std_cons_idx = 0;
6111         tpr->rx_std_prod_idx = 0;
6112         tpr->rx_jmb_cons_idx = 0;
6113         tpr->rx_jmb_prod_idx = 0;
6114
6115         if (tpr != &tp->prodring[0]) {
6116                 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
6117                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
6118                         memset(&tpr->rx_jmb_buffers[0], 0,
6119                                TG3_RX_JMB_BUFF_RING_SIZE);
6120                 goto done;
6121         }
6122
6123         /* Zero out all descriptors. */
6124         memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
6125
6126         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6127         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
6128             tp->dev->mtu > ETH_DATA_LEN)
6129                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6130         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6131
6132         /* Initialize invariants of the rings, we only set this
6133          * stuff once.  This works because the card does not
6134          * write into the rx buffer posting rings.
6135          */
6136         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
6137                 struct tg3_rx_buffer_desc *rxd;
6138
6139                 rxd = &tpr->rx_std[i];
6140                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6141                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6142                 rxd->opaque = (RXD_OPAQUE_RING_STD |
6143                                (i << RXD_OPAQUE_INDEX_SHIFT));
6144         }
6145
6146         /* Now allocate fresh SKBs for each rx ring. */
6147         for (i = 0; i < tp->rx_pending; i++) {
6148                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6149                         netdev_warn(tp->dev,
6150                                     "Using a smaller RX standard ring. Only "
6151                                     "%d out of %d buffers were allocated "
6152                                     "successfully\n", i, tp->rx_pending);
6153                         if (i == 0)
6154                                 goto initfail;
6155                         tp->rx_pending = i;
6156                         break;
6157                 }
6158         }
6159
6160         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6161                 goto done;
6162
6163         memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
6164
6165         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
6166                 goto done;
6167
6168         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
6169                 struct tg3_rx_buffer_desc *rxd;
6170
6171                 rxd = &tpr->rx_jmb[i].std;
6172                 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6173                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6174                                   RXD_FLAG_JUMBO;
6175                 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6176                        (i << RXD_OPAQUE_INDEX_SHIFT));
6177         }
6178
6179         for (i = 0; i < tp->rx_jumbo_pending; i++) {
6180                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
6181                         netdev_warn(tp->dev,
6182                                     "Using a smaller RX jumbo ring. Only %d "
6183                                     "out of %d buffers were allocated "
6184                                     "successfully\n", i, tp->rx_jumbo_pending);
6185                         if (i == 0)
6186                                 goto initfail;
6187                         tp->rx_jumbo_pending = i;
6188                         break;
6189                 }
6190         }
6191
6192 done:
6193         return 0;
6194
6195 initfail:
6196         tg3_rx_prodring_free(tp, tpr);
6197         return -ENOMEM;
6198 }
6199
6200 static void tg3_rx_prodring_fini(struct tg3 *tp,
6201                                  struct tg3_rx_prodring_set *tpr)
6202 {
6203         kfree(tpr->rx_std_buffers);
6204         tpr->rx_std_buffers = NULL;
6205         kfree(tpr->rx_jmb_buffers);
6206         tpr->rx_jmb_buffers = NULL;
6207         if (tpr->rx_std) {
6208                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
6209                                     tpr->rx_std, tpr->rx_std_mapping);
6210                 tpr->rx_std = NULL;
6211         }
6212         if (tpr->rx_jmb) {
6213                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
6214                                     tpr->rx_jmb, tpr->rx_jmb_mapping);
6215                 tpr->rx_jmb = NULL;
6216         }
6217 }
6218
6219 static int tg3_rx_prodring_init(struct tg3 *tp,
6220                                 struct tg3_rx_prodring_set *tpr)
6221 {
6222         tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
6223         if (!tpr->rx_std_buffers)
6224                 return -ENOMEM;
6225
6226         tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6227                                            &tpr->rx_std_mapping);
6228         if (!tpr->rx_std)
6229                 goto err_out;
6230
6231         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6232                 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
6233                                               GFP_KERNEL);
6234                 if (!tpr->rx_jmb_buffers)
6235                         goto err_out;
6236
6237                 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6238                                                    TG3_RX_JUMBO_RING_BYTES,
6239                                                    &tpr->rx_jmb_mapping);
6240                 if (!tpr->rx_jmb)
6241                         goto err_out;
6242         }
6243
6244         return 0;
6245
6246 err_out:
6247         tg3_rx_prodring_fini(tp, tpr);
6248         return -ENOMEM;
6249 }
6250
6251 /* Free up pending packets in all rx/tx rings.
6252  *
6253  * The chip has been shut down and the driver detached from
6254  * the networking, so no interrupts or new tx packets will
6255  * end up in the driver.  tp->{tx,}lock is not held and we are not
6256  * in an interrupt context and thus may sleep.
6257  */
6258 static void tg3_free_rings(struct tg3 *tp)
6259 {
6260         int i, j;
6261
6262         for (j = 0; j < tp->irq_cnt; j++) {
6263                 struct tg3_napi *tnapi = &tp->napi[j];
6264
6265                 tg3_rx_prodring_free(tp, &tp->prodring[j]);
6266
6267                 if (!tnapi->tx_buffers)
6268                         continue;
6269
6270                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6271                         struct ring_info *txp;
6272                         struct sk_buff *skb;
6273                         unsigned int k;
6274
6275                         txp = &tnapi->tx_buffers[i];
6276                         skb = txp->skb;
6277
6278                         if (skb == NULL) {
6279                                 i++;
6280                                 continue;
6281                         }
6282
6283                         pci_unmap_single(tp->pdev,
6284                                          dma_unmap_addr(txp, mapping),
6285                                          skb_headlen(skb),
6286                                          PCI_DMA_TODEVICE);
6287                         txp->skb = NULL;
6288
6289                         i++;
6290
6291                         for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6292                                 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6293                                 pci_unmap_page(tp->pdev,
6294                                                dma_unmap_addr(txp, mapping),
6295                                                skb_shinfo(skb)->frags[k].size,
6296                                                PCI_DMA_TODEVICE);
6297                                 i++;
6298                         }
6299
6300                         dev_kfree_skb_any(skb);
6301                 }
6302         }
6303 }
6304
6305 /* Initialize tx/rx rings for packet processing.
6306  *
6307  * The chip has been shut down and the driver detached from
6308  * the networking, so no interrupts or new tx packets will
6309  * end up in the driver.  tp->{tx,}lock are held and thus
6310  * we may not sleep.
6311  */
6312 static int tg3_init_rings(struct tg3 *tp)
6313 {
6314         int i;
6315
6316         /* Free up all the SKBs. */
6317         tg3_free_rings(tp);
6318
6319         for (i = 0; i < tp->irq_cnt; i++) {
6320                 struct tg3_napi *tnapi = &tp->napi[i];
6321
6322                 tnapi->last_tag = 0;
6323                 tnapi->last_irq_tag = 0;
6324                 tnapi->hw_status->status = 0;
6325                 tnapi->hw_status->status_tag = 0;
6326                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6327
6328                 tnapi->tx_prod = 0;
6329                 tnapi->tx_cons = 0;
6330                 if (tnapi->tx_ring)
6331                         memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6332
6333                 tnapi->rx_rcb_ptr = 0;
6334                 if (tnapi->rx_rcb)
6335                         memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6336
6337                 if (tg3_rx_prodring_alloc(tp, &tp->prodring[i])) {
6338                         tg3_free_rings(tp);
6339                         return -ENOMEM;
6340                 }
6341         }
6342
6343         return 0;
6344 }
6345
6346 /*
6347  * Must not be invoked with interrupt sources disabled and
6348  * the hardware shutdown down.
6349  */
6350 static void tg3_free_consistent(struct tg3 *tp)
6351 {
6352         int i;
6353
6354         for (i = 0; i < tp->irq_cnt; i++) {
6355                 struct tg3_napi *tnapi = &tp->napi[i];
6356
6357                 if (tnapi->tx_ring) {
6358                         pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6359                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
6360                         tnapi->tx_ring = NULL;
6361                 }
6362
6363                 kfree(tnapi->tx_buffers);
6364                 tnapi->tx_buffers = NULL;
6365
6366                 if (tnapi->rx_rcb) {
6367                         pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6368                                             tnapi->rx_rcb,
6369                                             tnapi->rx_rcb_mapping);
6370                         tnapi->rx_rcb = NULL;
6371                 }
6372
6373                 if (tnapi->hw_status) {
6374                         pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6375                                             tnapi->hw_status,
6376                                             tnapi->status_mapping);
6377                         tnapi->hw_status = NULL;
6378                 }
6379         }
6380
6381         if (tp->hw_stats) {
6382                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6383                                     tp->hw_stats, tp->stats_mapping);
6384                 tp->hw_stats = NULL;
6385         }
6386
6387         for (i = 0; i < tp->irq_cnt; i++)
6388                 tg3_rx_prodring_fini(tp, &tp->prodring[i]);
6389 }
6390
6391 /*
6392  * Must not be invoked with interrupt sources disabled and
6393  * the hardware shutdown down.  Can sleep.
6394  */
6395 static int tg3_alloc_consistent(struct tg3 *tp)
6396 {
6397         int i;
6398
6399         for (i = 0; i < tp->irq_cnt; i++) {
6400                 if (tg3_rx_prodring_init(tp, &tp->prodring[i]))
6401                         goto err_out;
6402         }
6403
6404         tp->hw_stats = pci_alloc_consistent(tp->pdev,
6405                                             sizeof(struct tg3_hw_stats),
6406                                             &tp->stats_mapping);
6407         if (!tp->hw_stats)
6408                 goto err_out;
6409
6410         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6411
6412         for (i = 0; i < tp->irq_cnt; i++) {
6413                 struct tg3_napi *tnapi = &tp->napi[i];
6414                 struct tg3_hw_status *sblk;
6415
6416                 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6417                                                         TG3_HW_STATUS_SIZE,
6418                                                         &tnapi->status_mapping);
6419                 if (!tnapi->hw_status)
6420                         goto err_out;
6421
6422                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6423                 sblk = tnapi->hw_status;
6424
6425                 /* If multivector TSS is enabled, vector 0 does not handle
6426                  * tx interrupts.  Don't allocate any resources for it.
6427                  */
6428                 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6429                     (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6430                         tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6431                                                     TG3_TX_RING_SIZE,
6432                                                     GFP_KERNEL);
6433                         if (!tnapi->tx_buffers)
6434                                 goto err_out;
6435
6436                         tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6437                                                               TG3_TX_RING_BYTES,
6438                                                        &tnapi->tx_desc_mapping);
6439                         if (!tnapi->tx_ring)
6440                                 goto err_out;
6441                 }
6442
6443                 /*
6444                  * When RSS is enabled, the status block format changes
6445                  * slightly.  The "rx_jumbo_consumer", "reserved",
6446                  * and "rx_mini_consumer" members get mapped to the
6447                  * other three rx return ring producer indexes.
6448                  */
6449                 switch (i) {
6450                 default:
6451                         tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6452                         break;
6453                 case 2:
6454                         tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6455                         break;
6456                 case 3:
6457                         tnapi->rx_rcb_prod_idx = &sblk->reserved;
6458                         break;
6459                 case 4:
6460                         tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6461                         break;
6462                 }
6463
6464                 tnapi->prodring = &tp->prodring[i];
6465
6466                 /*
6467                  * If multivector RSS is enabled, vector 0 does not handle
6468                  * rx or tx interrupts.  Don't allocate any resources for it.
6469                  */
6470                 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6471                         continue;
6472
6473                 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6474                                                      TG3_RX_RCB_RING_BYTES(tp),
6475                                                      &tnapi->rx_rcb_mapping);
6476                 if (!tnapi->rx_rcb)
6477                         goto err_out;
6478
6479                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6480         }
6481
6482         return 0;
6483
6484 err_out:
6485         tg3_free_consistent(tp);
6486         return -ENOMEM;
6487 }
6488
6489 #define MAX_WAIT_CNT 1000
6490
6491 /* To stop a block, clear the enable bit and poll till it
6492  * clears.  tp->lock is held.
6493  */
6494 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6495 {
6496         unsigned int i;
6497         u32 val;
6498
6499         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6500                 switch (ofs) {
6501                 case RCVLSC_MODE:
6502                 case DMAC_MODE:
6503                 case MBFREE_MODE:
6504                 case BUFMGR_MODE:
6505                 case MEMARB_MODE:
6506                         /* We can't enable/disable these bits of the
6507                          * 5705/5750, just say success.
6508                          */
6509                         return 0;
6510
6511                 default:
6512                         break;
6513                 }
6514         }
6515
6516         val = tr32(ofs);
6517         val &= ~enable_bit;
6518         tw32_f(ofs, val);
6519
6520         for (i = 0; i < MAX_WAIT_CNT; i++) {
6521                 udelay(100);
6522                 val = tr32(ofs);
6523                 if ((val & enable_bit) == 0)
6524                         break;
6525         }
6526
6527         if (i == MAX_WAIT_CNT && !silent) {
6528                 dev_err(&tp->pdev->dev,
6529                         "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6530                         ofs, enable_bit);
6531                 return -ENODEV;
6532         }
6533
6534         return 0;
6535 }
6536
6537 /* tp->lock is held. */
6538 static int tg3_abort_hw(struct tg3 *tp, int silent)
6539 {
6540         int i, err;
6541
6542         tg3_disable_ints(tp);
6543
6544         tp->rx_mode &= ~RX_MODE_ENABLE;
6545         tw32_f(MAC_RX_MODE, tp->rx_mode);
6546         udelay(10);
6547
6548         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6549         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6550         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6551         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6552         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6553         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6554
6555         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6556         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6557         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6558         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6559         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6560         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6561         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6562
6563         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6564         tw32_f(MAC_MODE, tp->mac_mode);
6565         udelay(40);
6566
6567         tp->tx_mode &= ~TX_MODE_ENABLE;
6568         tw32_f(MAC_TX_MODE, tp->tx_mode);
6569
6570         for (i = 0; i < MAX_WAIT_CNT; i++) {
6571                 udelay(100);
6572                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6573                         break;
6574         }
6575         if (i >= MAX_WAIT_CNT) {
6576                 dev_err(&tp->pdev->dev,
6577                         "%s timed out, TX_MODE_ENABLE will not clear "
6578                         "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
6579                 err |= -ENODEV;
6580         }
6581
6582         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6583         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6584         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6585
6586         tw32(FTQ_RESET, 0xffffffff);
6587         tw32(FTQ_RESET, 0x00000000);
6588
6589         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6590         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6591
6592         for (i = 0; i < tp->irq_cnt; i++) {
6593                 struct tg3_napi *tnapi = &tp->napi[i];
6594                 if (tnapi->hw_status)
6595                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6596         }
6597         if (tp->hw_stats)
6598                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6599
6600         return err;
6601 }
6602
6603 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6604 {
6605         int i;
6606         u32 apedata;
6607
6608         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6609         if (apedata != APE_SEG_SIG_MAGIC)
6610                 return;
6611
6612         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6613         if (!(apedata & APE_FW_STATUS_READY))
6614                 return;
6615
6616         /* Wait for up to 1 millisecond for APE to service previous event. */
6617         for (i = 0; i < 10; i++) {
6618                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6619                         return;
6620
6621                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6622
6623                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6624                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6625                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6626
6627                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6628
6629                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6630                         break;
6631
6632                 udelay(100);
6633         }
6634
6635         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6636                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6637 }
6638
6639 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6640 {
6641         u32 event;
6642         u32 apedata;
6643
6644         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6645                 return;
6646
6647         switch (kind) {
6648         case RESET_KIND_INIT:
6649                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6650                                 APE_HOST_SEG_SIG_MAGIC);
6651                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6652                                 APE_HOST_SEG_LEN_MAGIC);
6653                 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6654                 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6655                 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6656                         APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
6657                 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6658                                 APE_HOST_BEHAV_NO_PHYLOCK);
6659
6660                 event = APE_EVENT_STATUS_STATE_START;
6661                 break;
6662         case RESET_KIND_SHUTDOWN:
6663                 /* With the interface we are currently using,
6664                  * APE does not track driver state.  Wiping
6665                  * out the HOST SEGMENT SIGNATURE forces
6666                  * the APE to assume OS absent status.
6667                  */
6668                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6669
6670                 event = APE_EVENT_STATUS_STATE_UNLOAD;
6671                 break;
6672         case RESET_KIND_SUSPEND:
6673                 event = APE_EVENT_STATUS_STATE_SUSPEND;
6674                 break;
6675         default:
6676                 return;
6677         }
6678
6679         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6680
6681         tg3_ape_send_event(tp, event);
6682 }
6683
6684 /* tp->lock is held. */
6685 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6686 {
6687         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6688                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6689
6690         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6691                 switch (kind) {
6692                 case RESET_KIND_INIT:
6693                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6694                                       DRV_STATE_START);
6695                         break;
6696
6697                 case RESET_KIND_SHUTDOWN:
6698                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6699                                       DRV_STATE_UNLOAD);
6700                         break;
6701
6702                 case RESET_KIND_SUSPEND:
6703                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6704                                       DRV_STATE_SUSPEND);
6705                         break;
6706
6707                 default:
6708                         break;
6709                 }
6710         }
6711
6712         if (kind == RESET_KIND_INIT ||
6713             kind == RESET_KIND_SUSPEND)
6714                 tg3_ape_driver_state_change(tp, kind);
6715 }
6716
6717 /* tp->lock is held. */
6718 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6719 {
6720         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6721                 switch (kind) {
6722                 case RESET_KIND_INIT:
6723                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6724                                       DRV_STATE_START_DONE);
6725                         break;
6726
6727                 case RESET_KIND_SHUTDOWN:
6728                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6729                                       DRV_STATE_UNLOAD_DONE);
6730                         break;
6731
6732                 default:
6733                         break;
6734                 }
6735         }
6736
6737         if (kind == RESET_KIND_SHUTDOWN)
6738                 tg3_ape_driver_state_change(tp, kind);
6739 }
6740
6741 /* tp->lock is held. */
6742 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6743 {
6744         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6745                 switch (kind) {
6746                 case RESET_KIND_INIT:
6747                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6748                                       DRV_STATE_START);
6749                         break;
6750
6751                 case RESET_KIND_SHUTDOWN:
6752                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6753                                       DRV_STATE_UNLOAD);
6754                         break;
6755
6756                 case RESET_KIND_SUSPEND:
6757                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6758                                       DRV_STATE_SUSPEND);
6759                         break;
6760
6761                 default:
6762                         break;
6763                 }
6764         }
6765 }
6766
6767 static int tg3_poll_fw(struct tg3 *tp)
6768 {
6769         int i;
6770         u32 val;
6771
6772         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6773                 /* Wait up to 20ms for init done. */
6774                 for (i = 0; i < 200; i++) {
6775                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6776                                 return 0;
6777                         udelay(100);
6778                 }
6779                 return -ENODEV;
6780         }
6781
6782         /* Wait for firmware initialization to complete. */
6783         for (i = 0; i < 100000; i++) {
6784                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6785                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6786                         break;
6787                 udelay(10);
6788         }
6789
6790         /* Chip might not be fitted with firmware.  Some Sun onboard
6791          * parts are configured like that.  So don't signal the timeout
6792          * of the above loop as an error, but do report the lack of
6793          * running firmware once.
6794          */
6795         if (i >= 100000 &&
6796             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6797                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6798
6799                 netdev_info(tp->dev, "No firmware running\n");
6800         }
6801
6802         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6803                 /* The 57765 A0 needs a little more
6804                  * time to do some important work.
6805                  */
6806                 mdelay(10);
6807         }
6808
6809         return 0;
6810 }
6811
6812 /* Save PCI command register before chip reset */
6813 static void tg3_save_pci_state(struct tg3 *tp)
6814 {
6815         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6816 }
6817
6818 /* Restore PCI state after chip reset */
6819 static void tg3_restore_pci_state(struct tg3 *tp)
6820 {
6821         u32 val;
6822
6823         /* Re-enable indirect register accesses. */
6824         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6825                                tp->misc_host_ctrl);
6826
6827         /* Set MAX PCI retry to zero. */
6828         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6829         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6830             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6831                 val |= PCISTATE_RETRY_SAME_DMA;
6832         /* Allow reads and writes to the APE register and memory space. */
6833         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6834                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6835                        PCISTATE_ALLOW_APE_SHMEM_WR |
6836                        PCISTATE_ALLOW_APE_PSPACE_WR;
6837         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6838
6839         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6840
6841         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6842                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6843                         pcie_set_readrq(tp->pdev, 4096);
6844                 else {
6845                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6846                                               tp->pci_cacheline_sz);
6847                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6848                                               tp->pci_lat_timer);
6849                 }
6850         }
6851
6852         /* Make sure PCI-X relaxed ordering bit is clear. */
6853         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6854                 u16 pcix_cmd;
6855
6856                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6857                                      &pcix_cmd);
6858                 pcix_cmd &= ~PCI_X_CMD_ERO;
6859                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6860                                       pcix_cmd);
6861         }
6862
6863         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6864
6865                 /* Chip reset on 5780 will reset MSI enable bit,
6866                  * so need to restore it.
6867                  */
6868                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6869                         u16 ctrl;
6870
6871                         pci_read_config_word(tp->pdev,
6872                                              tp->msi_cap + PCI_MSI_FLAGS,
6873                                              &ctrl);
6874                         pci_write_config_word(tp->pdev,
6875                                               tp->msi_cap + PCI_MSI_FLAGS,
6876                                               ctrl | PCI_MSI_FLAGS_ENABLE);
6877                         val = tr32(MSGINT_MODE);
6878                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6879                 }
6880         }
6881 }
6882
6883 static void tg3_stop_fw(struct tg3 *);
6884
6885 /* tp->lock is held. */
6886 static int tg3_chip_reset(struct tg3 *tp)
6887 {
6888         u32 val;
6889         void (*write_op)(struct tg3 *, u32, u32);
6890         int i, err;
6891
6892         tg3_nvram_lock(tp);
6893
6894         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6895
6896         /* No matching tg3_nvram_unlock() after this because
6897          * chip reset below will undo the nvram lock.
6898          */
6899         tp->nvram_lock_cnt = 0;
6900
6901         /* GRC_MISC_CFG core clock reset will clear the memory
6902          * enable bit in PCI register 4 and the MSI enable bit
6903          * on some chips, so we save relevant registers here.
6904          */
6905         tg3_save_pci_state(tp);
6906
6907         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6908             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6909                 tw32(GRC_FASTBOOT_PC, 0);
6910
6911         /*
6912          * We must avoid the readl() that normally takes place.
6913          * It locks machines, causes machine checks, and other
6914          * fun things.  So, temporarily disable the 5701
6915          * hardware workaround, while we do the reset.
6916          */
6917         write_op = tp->write32;
6918         if (write_op == tg3_write_flush_reg32)
6919                 tp->write32 = tg3_write32;
6920
6921         /* Prevent the irq handler from reading or writing PCI registers
6922          * during chip reset when the memory enable bit in the PCI command
6923          * register may be cleared.  The chip does not generate interrupt
6924          * at this time, but the irq handler may still be called due to irq
6925          * sharing or irqpoll.
6926          */
6927         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6928         for (i = 0; i < tp->irq_cnt; i++) {
6929                 struct tg3_napi *tnapi = &tp->napi[i];
6930                 if (tnapi->hw_status) {
6931                         tnapi->hw_status->status = 0;
6932                         tnapi->hw_status->status_tag = 0;
6933                 }
6934                 tnapi->last_tag = 0;
6935                 tnapi->last_irq_tag = 0;
6936         }
6937         smp_mb();
6938
6939         for (i = 0; i < tp->irq_cnt; i++)
6940                 synchronize_irq(tp->napi[i].irq_vec);
6941
6942         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6943                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6944                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6945         }
6946
6947         /* do the reset */
6948         val = GRC_MISC_CFG_CORECLK_RESET;
6949
6950         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6951                 /* Force PCIe 1.0a mode */
6952                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
6953                     !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
6954                     tr32(TG3_PCIE_PHY_TSTCTL) ==
6955                     (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
6956                         tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
6957
6958                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6959                         tw32(GRC_MISC_CFG, (1 << 29));
6960                         val |= (1 << 29);
6961                 }
6962         }
6963
6964         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6965                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6966                 tw32(GRC_VCPU_EXT_CTRL,
6967                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6968         }
6969
6970         /* Manage gphy power for all CPMU absent PCIe devices. */
6971         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6972             !(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
6973                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6974
6975         tw32(GRC_MISC_CFG, val);
6976
6977         /* restore 5701 hardware bug workaround write method */
6978         tp->write32 = write_op;
6979
6980         /* Unfortunately, we have to delay before the PCI read back.
6981          * Some 575X chips even will not respond to a PCI cfg access
6982          * when the reset command is given to the chip.
6983          *
6984          * How do these hardware designers expect things to work
6985          * properly if the PCI write is posted for a long period
6986          * of time?  It is always necessary to have some method by
6987          * which a register read back can occur to push the write
6988          * out which does the reset.
6989          *
6990          * For most tg3 variants the trick below was working.
6991          * Ho hum...
6992          */
6993         udelay(120);
6994
6995         /* Flush PCI posted writes.  The normal MMIO registers
6996          * are inaccessible at this time so this is the only
6997          * way to make this reliably (actually, this is no longer
6998          * the case, see above).  I tried to use indirect
6999          * register read/write but this upset some 5701 variants.
7000          */
7001         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
7002
7003         udelay(120);
7004
7005         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
7006                 u16 val16;
7007
7008                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
7009                         int i;
7010                         u32 cfg_val;
7011
7012                         /* Wait for link training to complete.  */
7013                         for (i = 0; i < 5000; i++)
7014                                 udelay(100);
7015
7016                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
7017                         pci_write_config_dword(tp->pdev, 0xc4,
7018                                                cfg_val | (1 << 15));
7019                 }
7020
7021                 /* Clear the "no snoop" and "relaxed ordering" bits. */
7022                 pci_read_config_word(tp->pdev,
7023                                      tp->pcie_cap + PCI_EXP_DEVCTL,
7024                                      &val16);
7025                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
7026                            PCI_EXP_DEVCTL_NOSNOOP_EN);
7027                 /*
7028                  * Older PCIe devices only support the 128 byte
7029                  * MPS setting.  Enforce the restriction.
7030                  */
7031                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7032                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
7033                 pci_write_config_word(tp->pdev,
7034                                       tp->pcie_cap + PCI_EXP_DEVCTL,
7035                                       val16);
7036
7037                 pcie_set_readrq(tp->pdev, 4096);
7038
7039                 /* Clear error status */
7040                 pci_write_config_word(tp->pdev,
7041                                       tp->pcie_cap + PCI_EXP_DEVSTA,
7042                                       PCI_EXP_DEVSTA_CED |
7043                                       PCI_EXP_DEVSTA_NFED |
7044                                       PCI_EXP_DEVSTA_FED |
7045                                       PCI_EXP_DEVSTA_URD);
7046         }
7047
7048         tg3_restore_pci_state(tp);
7049
7050         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
7051
7052         val = 0;
7053         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
7054                 val = tr32(MEMARB_MODE);
7055         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7056
7057         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7058                 tg3_stop_fw(tp);
7059                 tw32(0x5000, 0x400);
7060         }
7061
7062         tw32(GRC_MODE, tp->grc_mode);
7063
7064         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
7065                 val = tr32(0xc4);
7066
7067                 tw32(0xc4, val | (1 << 15));
7068         }
7069
7070         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7071             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7072                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7073                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7074                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7075                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7076         }
7077
7078         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7079                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
7080                 tw32_f(MAC_MODE, tp->mac_mode);
7081         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7082                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
7083                 tw32_f(MAC_MODE, tp->mac_mode);
7084         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7085                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
7086                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
7087                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
7088                 tw32_f(MAC_MODE, tp->mac_mode);
7089         } else
7090                 tw32_f(MAC_MODE, 0);
7091         udelay(40);
7092
7093         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7094
7095         err = tg3_poll_fw(tp);
7096         if (err)
7097                 return err;
7098
7099         tg3_mdio_start(tp);
7100
7101         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
7102             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7103             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7104             !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
7105                 val = tr32(0x7c00);
7106
7107                 tw32(0x7c00, val | (1 << 25));
7108         }
7109
7110         /* Reprobe ASF enable state.  */
7111         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7112         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7113         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7114         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7115                 u32 nic_cfg;
7116
7117                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7118                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7119                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7120                         tp->last_event_jiffies = jiffies;
7121                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7122                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7123                 }
7124         }
7125
7126         return 0;
7127 }
7128
7129 /* tp->lock is held. */
7130 static void tg3_stop_fw(struct tg3 *tp)
7131 {
7132         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7133            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7134                 /* Wait for RX cpu to ACK the previous event. */
7135                 tg3_wait_for_event_ack(tp);
7136
7137                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7138
7139                 tg3_generate_fw_event(tp);
7140
7141                 /* Wait for RX cpu to ACK this event. */
7142                 tg3_wait_for_event_ack(tp);
7143         }
7144 }
7145
7146 /* tp->lock is held. */
7147 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7148 {
7149         int err;
7150
7151         tg3_stop_fw(tp);
7152
7153         tg3_write_sig_pre_reset(tp, kind);
7154
7155         tg3_abort_hw(tp, silent);
7156         err = tg3_chip_reset(tp);
7157
7158         __tg3_set_mac_addr(tp, 0);
7159
7160         tg3_write_sig_legacy(tp, kind);
7161         tg3_write_sig_post_reset(tp, kind);
7162
7163         if (err)
7164                 return err;
7165
7166         return 0;
7167 }
7168
7169 #define RX_CPU_SCRATCH_BASE     0x30000
7170 #define RX_CPU_SCRATCH_SIZE     0x04000
7171 #define TX_CPU_SCRATCH_BASE     0x34000
7172 #define TX_CPU_SCRATCH_SIZE     0x04000
7173
7174 /* tp->lock is held. */
7175 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7176 {
7177         int i;
7178
7179         BUG_ON(offset == TX_CPU_BASE &&
7180             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7181
7182         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7183                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7184
7185                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7186                 return 0;
7187         }
7188         if (offset == RX_CPU_BASE) {
7189                 for (i = 0; i < 10000; i++) {
7190                         tw32(offset + CPU_STATE, 0xffffffff);
7191                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7192                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7193                                 break;
7194                 }
7195
7196                 tw32(offset + CPU_STATE, 0xffffffff);
7197                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
7198                 udelay(10);
7199         } else {
7200                 for (i = 0; i < 10000; i++) {
7201                         tw32(offset + CPU_STATE, 0xffffffff);
7202                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7203                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7204                                 break;
7205                 }
7206         }
7207
7208         if (i >= 10000) {
7209                 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7210                            __func__, offset == RX_CPU_BASE ? "RX" : "TX");
7211                 return -ENODEV;
7212         }
7213
7214         /* Clear firmware's nvram arbitration. */
7215         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7216                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7217         return 0;
7218 }
7219
7220 struct fw_info {
7221         unsigned int fw_base;
7222         unsigned int fw_len;
7223         const __be32 *fw_data;
7224 };
7225
7226 /* tp->lock is held. */
7227 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7228                                  int cpu_scratch_size, struct fw_info *info)
7229 {
7230         int err, lock_err, i;
7231         void (*write_op)(struct tg3 *, u32, u32);
7232
7233         if (cpu_base == TX_CPU_BASE &&
7234             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7235                 netdev_err(tp->dev,
7236                            "%s: Trying to load TX cpu firmware which is 5705\n",
7237                            __func__);
7238                 return -EINVAL;
7239         }
7240
7241         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7242                 write_op = tg3_write_mem;
7243         else
7244                 write_op = tg3_write_indirect_reg32;
7245
7246         /* It is possible that bootcode is still loading at this point.
7247          * Get the nvram lock first before halting the cpu.
7248          */
7249         lock_err = tg3_nvram_lock(tp);
7250         err = tg3_halt_cpu(tp, cpu_base);
7251         if (!lock_err)
7252                 tg3_nvram_unlock(tp);
7253         if (err)
7254                 goto out;
7255
7256         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7257                 write_op(tp, cpu_scratch_base + i, 0);
7258         tw32(cpu_base + CPU_STATE, 0xffffffff);
7259         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7260         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7261                 write_op(tp, (cpu_scratch_base +
7262                               (info->fw_base & 0xffff) +
7263                               (i * sizeof(u32))),
7264                               be32_to_cpu(info->fw_data[i]));
7265
7266         err = 0;
7267
7268 out:
7269         return err;
7270 }
7271
7272 /* tp->lock is held. */
7273 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7274 {
7275         struct fw_info info;
7276         const __be32 *fw_data;
7277         int err, i;
7278
7279         fw_data = (void *)tp->fw->data;
7280
7281         /* Firmware blob starts with version numbers, followed by
7282            start address and length. We are setting complete length.
7283            length = end_address_of_bss - start_address_of_text.
7284            Remainder is the blob to be loaded contiguously
7285            from start address. */
7286
7287         info.fw_base = be32_to_cpu(fw_data[1]);
7288         info.fw_len = tp->fw->size - 12;
7289         info.fw_data = &fw_data[3];
7290
7291         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7292                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7293                                     &info);
7294         if (err)
7295                 return err;
7296
7297         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7298                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7299                                     &info);
7300         if (err)
7301                 return err;
7302
7303         /* Now startup only the RX cpu. */
7304         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7305         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7306
7307         for (i = 0; i < 5; i++) {
7308                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7309                         break;
7310                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7311                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
7312                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7313                 udelay(1000);
7314         }
7315         if (i >= 5) {
7316                 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7317                            "should be %08x\n", __func__,
7318                            tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
7319                 return -ENODEV;
7320         }
7321         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7322         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
7323
7324         return 0;
7325 }
7326
7327 /* 5705 needs a special version of the TSO firmware.  */
7328
7329 /* tp->lock is held. */
7330 static int tg3_load_tso_firmware(struct tg3 *tp)
7331 {
7332         struct fw_info info;
7333         const __be32 *fw_data;
7334         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7335         int err, i;
7336
7337         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7338                 return 0;
7339
7340         fw_data = (void *)tp->fw->data;
7341
7342         /* Firmware blob starts with version numbers, followed by
7343            start address and length. We are setting complete length.
7344            length = end_address_of_bss - start_address_of_text.
7345            Remainder is the blob to be loaded contiguously
7346            from start address. */
7347
7348         info.fw_base = be32_to_cpu(fw_data[1]);
7349         cpu_scratch_size = tp->fw_len;
7350         info.fw_len = tp->fw->size - 12;
7351         info.fw_data = &fw_data[3];
7352
7353         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7354                 cpu_base = RX_CPU_BASE;
7355                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7356         } else {
7357                 cpu_base = TX_CPU_BASE;
7358                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7359                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7360         }
7361
7362         err = tg3_load_firmware_cpu(tp, cpu_base,
7363                                     cpu_scratch_base, cpu_scratch_size,
7364                                     &info);
7365         if (err)
7366                 return err;
7367
7368         /* Now startup the cpu. */
7369         tw32(cpu_base + CPU_STATE, 0xffffffff);
7370         tw32_f(cpu_base + CPU_PC, info.fw_base);
7371
7372         for (i = 0; i < 5; i++) {
7373                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7374                         break;
7375                 tw32(cpu_base + CPU_STATE, 0xffffffff);
7376                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
7377                 tw32_f(cpu_base + CPU_PC, info.fw_base);
7378                 udelay(1000);
7379         }
7380         if (i >= 5) {
7381                 netdev_err(tp->dev,
7382                            "%s fails to set CPU PC, is %08x should be %08x\n",
7383                            __func__, tr32(cpu_base + CPU_PC), info.fw_base);
7384                 return -ENODEV;
7385         }
7386         tw32(cpu_base + CPU_STATE, 0xffffffff);
7387         tw32_f(cpu_base + CPU_MODE,  0x00000000);
7388         return 0;
7389 }
7390
7391
7392 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7393 {
7394         struct tg3 *tp = netdev_priv(dev);
7395         struct sockaddr *addr = p;
7396         int err = 0, skip_mac_1 = 0;
7397
7398         if (!is_valid_ether_addr(addr->sa_data))
7399                 return -EINVAL;
7400
7401         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7402
7403         if (!netif_running(dev))
7404                 return 0;
7405
7406         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7407                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7408
7409                 addr0_high = tr32(MAC_ADDR_0_HIGH);
7410                 addr0_low = tr32(MAC_ADDR_0_LOW);
7411                 addr1_high = tr32(MAC_ADDR_1_HIGH);
7412                 addr1_low = tr32(MAC_ADDR_1_LOW);
7413
7414                 /* Skip MAC addr 1 if ASF is using it. */
7415                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7416                     !(addr1_high == 0 && addr1_low == 0))
7417                         skip_mac_1 = 1;
7418         }
7419         spin_lock_bh(&tp->lock);
7420         __tg3_set_mac_addr(tp, skip_mac_1);
7421         spin_unlock_bh(&tp->lock);
7422
7423         return err;
7424 }
7425
7426 /* tp->lock is held. */
7427 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7428                            dma_addr_t mapping, u32 maxlen_flags,
7429                            u32 nic_addr)
7430 {
7431         tg3_write_mem(tp,
7432                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7433                       ((u64) mapping >> 32));
7434         tg3_write_mem(tp,
7435                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7436                       ((u64) mapping & 0xffffffff));
7437         tg3_write_mem(tp,
7438                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7439                        maxlen_flags);
7440
7441         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7442                 tg3_write_mem(tp,
7443                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7444                               nic_addr);
7445 }
7446
7447 static void __tg3_set_rx_mode(struct net_device *);
7448 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7449 {
7450         int i;
7451
7452         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7453                 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7454                 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7455                 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7456         } else {
7457                 tw32(HOSTCC_TXCOL_TICKS, 0);
7458                 tw32(HOSTCC_TXMAX_FRAMES, 0);
7459                 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7460         }
7461
7462         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
7463                 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7464                 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7465                 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7466         } else {
7467                 tw32(HOSTCC_RXCOL_TICKS, 0);
7468                 tw32(HOSTCC_RXMAX_FRAMES, 0);
7469                 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7470         }
7471
7472         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7473                 u32 val = ec->stats_block_coalesce_usecs;
7474
7475                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7476                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7477
7478                 if (!netif_carrier_ok(tp->dev))
7479                         val = 0;
7480
7481                 tw32(HOSTCC_STAT_COAL_TICKS, val);
7482         }
7483
7484         for (i = 0; i < tp->irq_cnt - 1; i++) {
7485                 u32 reg;
7486
7487                 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7488                 tw32(reg, ec->rx_coalesce_usecs);
7489                 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7490                 tw32(reg, ec->rx_max_coalesced_frames);
7491                 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7492                 tw32(reg, ec->rx_max_coalesced_frames_irq);
7493
7494                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7495                         reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7496                         tw32(reg, ec->tx_coalesce_usecs);
7497                         reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7498                         tw32(reg, ec->tx_max_coalesced_frames);
7499                         reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7500                         tw32(reg, ec->tx_max_coalesced_frames_irq);
7501                 }
7502         }
7503
7504         for (; i < tp->irq_max - 1; i++) {
7505                 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7506                 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7507                 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7508
7509                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7510                         tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7511                         tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7512                         tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7513                 }
7514         }
7515 }
7516
7517 /* tp->lock is held. */
7518 static void tg3_rings_reset(struct tg3 *tp)
7519 {
7520         int i;
7521         u32 stblk, txrcb, rxrcb, limit;
7522         struct tg3_napi *tnapi = &tp->napi[0];
7523
7524         /* Disable all transmit rings but the first. */
7525         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7526                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7527         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7528                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7529         else
7530                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7531
7532         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7533              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7534                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7535                               BDINFO_FLAGS_DISABLED);
7536
7537
7538         /* Disable all receive return rings but the first. */
7539         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7540             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7541                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7542         else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7543                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7544         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7545                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7546                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7547         else
7548                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7549
7550         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7551              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7552                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7553                               BDINFO_FLAGS_DISABLED);
7554
7555         /* Disable interrupts */
7556         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7557
7558         /* Zero mailbox registers. */
7559         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7560                 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7561                         tp->napi[i].tx_prod = 0;
7562                         tp->napi[i].tx_cons = 0;
7563                         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7564                                 tw32_mailbox(tp->napi[i].prodmbox, 0);
7565                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
7566                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7567                 }
7568                 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7569                         tw32_mailbox(tp->napi[0].prodmbox, 0);
7570         } else {
7571                 tp->napi[0].tx_prod = 0;
7572                 tp->napi[0].tx_cons = 0;
7573                 tw32_mailbox(tp->napi[0].prodmbox, 0);
7574                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7575         }
7576
7577         /* Make sure the NIC-based send BD rings are disabled. */
7578         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7579                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7580                 for (i = 0; i < 16; i++)
7581                         tw32_tx_mbox(mbox + i * 8, 0);
7582         }
7583
7584         txrcb = NIC_SRAM_SEND_RCB;
7585         rxrcb = NIC_SRAM_RCV_RET_RCB;
7586
7587         /* Clear status block in ram. */
7588         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7589
7590         /* Set status block DMA address */
7591         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7592              ((u64) tnapi->status_mapping >> 32));
7593         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7594              ((u64) tnapi->status_mapping & 0xffffffff));
7595
7596         if (tnapi->tx_ring) {
7597                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7598                                (TG3_TX_RING_SIZE <<
7599                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7600                                NIC_SRAM_TX_BUFFER_DESC);
7601                 txrcb += TG3_BDINFO_SIZE;
7602         }
7603
7604         if (tnapi->rx_rcb) {
7605                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7606                                (TG3_RX_RCB_RING_SIZE(tp) <<
7607                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7608                 rxrcb += TG3_BDINFO_SIZE;
7609         }
7610
7611         stblk = HOSTCC_STATBLCK_RING1;
7612
7613         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7614                 u64 mapping = (u64)tnapi->status_mapping;
7615                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7616                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7617
7618                 /* Clear status block in ram. */
7619                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7620
7621                 if (tnapi->tx_ring) {
7622                         tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7623                                        (TG3_TX_RING_SIZE <<
7624                                         BDINFO_FLAGS_MAXLEN_SHIFT),
7625                                        NIC_SRAM_TX_BUFFER_DESC);
7626                         txrcb += TG3_BDINFO_SIZE;
7627                 }
7628
7629                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7630                                (TG3_RX_RCB_RING_SIZE(tp) <<
7631                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7632
7633                 stblk += 8;
7634                 rxrcb += TG3_BDINFO_SIZE;
7635         }
7636 }
7637
7638 /* tp->lock is held. */
7639 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7640 {
7641         u32 val, rdmac_mode;
7642         int i, err, limit;
7643         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
7644
7645         tg3_disable_ints(tp);
7646
7647         tg3_stop_fw(tp);
7648
7649         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7650
7651         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
7652                 tg3_abort_hw(tp, 1);
7653
7654         if (reset_phy)
7655                 tg3_phy_reset(tp);
7656
7657         err = tg3_chip_reset(tp);
7658         if (err)
7659                 return err;
7660
7661         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7662
7663         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7664                 val = tr32(TG3_CPMU_CTRL);
7665                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7666                 tw32(TG3_CPMU_CTRL, val);
7667
7668                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7669                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7670                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7671                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7672
7673                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7674                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7675                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7676                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7677
7678                 val = tr32(TG3_CPMU_HST_ACC);
7679                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7680                 val |= CPMU_HST_ACC_MACCLK_6_25;
7681                 tw32(TG3_CPMU_HST_ACC, val);
7682         }
7683
7684         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7685                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7686                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7687                        PCIE_PWR_MGMT_L1_THRESH_4MS;
7688                 tw32(PCIE_PWR_MGMT_THRESH, val);
7689
7690                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7691                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7692
7693                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7694
7695                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7696                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7697         }
7698
7699         if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7700                 u32 grc_mode = tr32(GRC_MODE);
7701
7702                 /* Access the lower 1K of PL PCIE block registers. */
7703                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7704                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7705
7706                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7707                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7708                      val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7709
7710                 tw32(GRC_MODE, grc_mode);
7711         }
7712
7713         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
7714                 u32 grc_mode = tr32(GRC_MODE);
7715
7716                 /* Access the lower 1K of PL PCIE block registers. */
7717                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7718                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7719
7720                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5);
7721                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
7722                      val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
7723
7724                 tw32(GRC_MODE, grc_mode);
7725
7726                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7727                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7728                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7729                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7730         }
7731
7732         /* This works around an issue with Athlon chipsets on
7733          * B3 tigon3 silicon.  This bit has no effect on any
7734          * other revision.  But do not set this on PCI Express
7735          * chips and don't even touch the clocks if the CPMU is present.
7736          */
7737         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7738                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7739                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7740                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7741         }
7742
7743         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7744             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7745                 val = tr32(TG3PCI_PCISTATE);
7746                 val |= PCISTATE_RETRY_SAME_DMA;
7747                 tw32(TG3PCI_PCISTATE, val);
7748         }
7749
7750         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7751                 /* Allow reads and writes to the
7752                  * APE register and memory space.
7753                  */
7754                 val = tr32(TG3PCI_PCISTATE);
7755                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7756                        PCISTATE_ALLOW_APE_SHMEM_WR |
7757                        PCISTATE_ALLOW_APE_PSPACE_WR;
7758                 tw32(TG3PCI_PCISTATE, val);
7759         }
7760
7761         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7762                 /* Enable some hw fixes.  */
7763                 val = tr32(TG3PCI_MSI_DATA);
7764                 val |= (1 << 26) | (1 << 28) | (1 << 29);
7765                 tw32(TG3PCI_MSI_DATA, val);
7766         }
7767
7768         /* Descriptor ring init may make accesses to the
7769          * NIC SRAM area to setup the TX descriptors, so we
7770          * can only do this after the hardware has been
7771          * successfully reset.
7772          */
7773         err = tg3_init_rings(tp);
7774         if (err)
7775                 return err;
7776
7777         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
7778                 val = tr32(TG3PCI_DMA_RW_CTRL) &
7779                       ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7780                 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
7781                         val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
7782                 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7783         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7784                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7785                 /* This value is determined during the probe time DMA
7786                  * engine test, tg3_test_dma.
7787                  */
7788                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7789         }
7790
7791         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7792                           GRC_MODE_4X_NIC_SEND_RINGS |
7793                           GRC_MODE_NO_TX_PHDR_CSUM |
7794                           GRC_MODE_NO_RX_PHDR_CSUM);
7795         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7796
7797         /* Pseudo-header checksum is done by hardware logic and not
7798          * the offload processers, so make the chip do the pseudo-
7799          * header checksums on receive.  For transmit it is more
7800          * convenient to do the pseudo-header checksum in software
7801          * as Linux does that on transmit for us in all cases.
7802          */
7803         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7804
7805         tw32(GRC_MODE,
7806              tp->grc_mode |
7807              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7808
7809         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7810         val = tr32(GRC_MISC_CFG);
7811         val &= ~0xff;
7812         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7813         tw32(GRC_MISC_CFG, val);
7814
7815         /* Initialize MBUF/DESC pool. */
7816         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7817                 /* Do nothing.  */
7818         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7819                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7820                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7821                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7822                 else
7823                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7824                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7825                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7826         } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7827                 int fw_len;
7828
7829                 fw_len = tp->fw_len;
7830                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7831                 tw32(BUFMGR_MB_POOL_ADDR,
7832                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7833                 tw32(BUFMGR_MB_POOL_SIZE,
7834                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7835         }
7836
7837         if (tp->dev->mtu <= ETH_DATA_LEN) {
7838                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7839                      tp->bufmgr_config.mbuf_read_dma_low_water);
7840                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7841                      tp->bufmgr_config.mbuf_mac_rx_low_water);
7842                 tw32(BUFMGR_MB_HIGH_WATER,
7843                      tp->bufmgr_config.mbuf_high_water);
7844         } else {
7845                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7846                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7847                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7848                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7849                 tw32(BUFMGR_MB_HIGH_WATER,
7850                      tp->bufmgr_config.mbuf_high_water_jumbo);
7851         }
7852         tw32(BUFMGR_DMA_LOW_WATER,
7853              tp->bufmgr_config.dma_low_water);
7854         tw32(BUFMGR_DMA_HIGH_WATER,
7855              tp->bufmgr_config.dma_high_water);
7856
7857         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7858         for (i = 0; i < 2000; i++) {
7859                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7860                         break;
7861                 udelay(10);
7862         }
7863         if (i >= 2000) {
7864                 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
7865                 return -ENODEV;
7866         }
7867
7868         /* Setup replenish threshold. */
7869         val = tp->rx_pending / 8;
7870         if (val == 0)
7871                 val = 1;
7872         else if (val > tp->rx_std_max_post)
7873                 val = tp->rx_std_max_post;
7874         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7875                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7876                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7877
7878                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7879                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7880         }
7881
7882         tw32(RCVBDI_STD_THRESH, val);
7883
7884         /* Initialize TG3_BDINFO's at:
7885          *  RCVDBDI_STD_BD:     standard eth size rx ring
7886          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
7887          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
7888          *
7889          * like so:
7890          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
7891          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
7892          *                              ring attribute flags
7893          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
7894          *
7895          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7896          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7897          *
7898          * The size of each ring is fixed in the firmware, but the location is
7899          * configurable.
7900          */
7901         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7902              ((u64) tpr->rx_std_mapping >> 32));
7903         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7904              ((u64) tpr->rx_std_mapping & 0xffffffff));
7905         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
7906             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
7907                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7908                      NIC_SRAM_RX_BUFFER_DESC);
7909
7910         /* Disable the mini ring */
7911         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7912                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7913                      BDINFO_FLAGS_DISABLED);
7914
7915         /* Program the jumbo buffer descriptor ring control
7916          * blocks on those devices that have them.
7917          */
7918         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7919             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7920                 /* Setup replenish threshold. */
7921                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7922
7923                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7924                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7925                              ((u64) tpr->rx_jmb_mapping >> 32));
7926                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7927                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7928                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7929                              (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7930                              BDINFO_FLAGS_USE_EXT_RECV);
7931                         if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) ||
7932                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7933                                 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7934                                      NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7935                 } else {
7936                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7937                              BDINFO_FLAGS_DISABLED);
7938                 }
7939
7940                 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
7941                         val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7942                               (TG3_RX_STD_DMA_SZ << 2);
7943                 else
7944                         val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
7945         } else
7946                 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7947
7948         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7949
7950         tpr->rx_std_prod_idx = tp->rx_pending;
7951         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
7952
7953         tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7954                           tp->rx_jumbo_pending : 0;
7955         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
7956
7957         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
7958                 tw32(STD_REPLENISH_LWM, 32);
7959                 tw32(JMB_REPLENISH_LWM, 16);
7960         }
7961
7962         tg3_rings_reset(tp);
7963
7964         /* Initialize MAC address and backoff seed. */
7965         __tg3_set_mac_addr(tp, 0);
7966
7967         /* MTU + ethernet header + FCS + optional VLAN tag */
7968         tw32(MAC_RX_MTU_SIZE,
7969              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7970
7971         /* The slot time is changed by tg3_setup_phy if we
7972          * run at gigabit with half duplex.
7973          */
7974         tw32(MAC_TX_LENGTHS,
7975              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7976              (6 << TX_LENGTHS_IPG_SHIFT) |
7977              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7978
7979         /* Receive rules. */
7980         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7981         tw32(RCVLPC_CONFIG, 0x0181);
7982
7983         /* Calculate RDMAC_MODE setting early, we need it to determine
7984          * the RCVLPC_STATE_ENABLE mask.
7985          */
7986         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7987                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7988                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7989                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7990                       RDMAC_MODE_LNGREAD_ENAB);
7991
7992         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7993             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7994                 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
7995
7996         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7997             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7998             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7999                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
8000                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
8001                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
8002
8003         /* If statement applies to 5705 and 5750 PCI devices only */
8004         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8005              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8006             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
8007                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
8008                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
8009                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
8010                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8011                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
8012                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8013                 }
8014         }
8015
8016         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
8017                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8018
8019         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8020                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8021
8022         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
8023             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8024             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8025                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
8026
8027         /* Receive/send statistics. */
8028         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
8029                 val = tr32(RCVLPC_STATS_ENABLE);
8030                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8031                 tw32(RCVLPC_STATS_ENABLE, val);
8032         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8033                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8034                 val = tr32(RCVLPC_STATS_ENABLE);
8035                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8036                 tw32(RCVLPC_STATS_ENABLE, val);
8037         } else {
8038                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8039         }
8040         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8041         tw32(SNDDATAI_STATSENAB, 0xffffff);
8042         tw32(SNDDATAI_STATSCTRL,
8043              (SNDDATAI_SCTRL_ENABLE |
8044               SNDDATAI_SCTRL_FASTUPD));
8045
8046         /* Setup host coalescing engine. */
8047         tw32(HOSTCC_MODE, 0);
8048         for (i = 0; i < 2000; i++) {
8049                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8050                         break;
8051                 udelay(10);
8052         }
8053
8054         __tg3_set_coalesce(tp, &tp->coal);
8055
8056         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8057                 /* Status/statistics block address.  See tg3_timer,
8058                  * the tg3_periodic_fetch_stats call there, and
8059                  * tg3_get_stats to see how this works for 5705/5750 chips.
8060                  */
8061                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8062                      ((u64) tp->stats_mapping >> 32));
8063                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8064                      ((u64) tp->stats_mapping & 0xffffffff));
8065                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8066
8067                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
8068
8069                 /* Clear statistics and status block memory areas */
8070                 for (i = NIC_SRAM_STATS_BLK;
8071                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8072                      i += sizeof(u32)) {
8073                         tg3_write_mem(tp, i, 0);
8074                         udelay(40);
8075                 }
8076         }
8077
8078         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8079
8080         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8081         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8082         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8083                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8084
8085         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8086                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
8087                 /* reset to prevent losing 1st rx packet intermittently */
8088                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8089                 udelay(10);
8090         }
8091
8092         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8093                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8094         else
8095                 tp->mac_mode = 0;
8096         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8097                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
8098         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8099             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8100             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8101                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8102         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8103         udelay(40);
8104
8105         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8106          * If TG3_FLG2_IS_NIC is zero, we should read the
8107          * register to preserve the GPIO settings for LOMs. The GPIOs,
8108          * whether used as inputs or outputs, are set by boot code after
8109          * reset.
8110          */
8111         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
8112                 u32 gpio_mask;
8113
8114                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8115                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8116                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8117
8118                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8119                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8120                                      GRC_LCLCTRL_GPIO_OUTPUT3;
8121
8122                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8123                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8124
8125                 tp->grc_local_ctrl &= ~gpio_mask;
8126                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8127
8128                 /* GPIO1 must be driven high for eeprom write protect */
8129                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8130                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8131                                                GRC_LCLCTRL_GPIO_OUTPUT1);
8132         }
8133         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8134         udelay(100);
8135
8136         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
8137                 val = tr32(MSGINT_MODE);
8138                 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8139                 tw32(MSGINT_MODE, val);
8140         }
8141
8142         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8143                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8144                 udelay(40);
8145         }
8146
8147         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8148                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8149                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8150                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8151                WDMAC_MODE_LNGREAD_ENAB);
8152
8153         /* If statement applies to 5705 and 5750 PCI devices only */
8154         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8155              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8156             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
8157                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8158                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8159                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8160                         /* nothing */
8161                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8162                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8163                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8164                         val |= WDMAC_MODE_RX_ACCEL;
8165                 }
8166         }
8167
8168         /* Enable host coalescing bug fix */
8169         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8170                 val |= WDMAC_MODE_STATUS_TAG_FIX;
8171
8172         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8173                 val |= WDMAC_MODE_BURST_ALL_DATA;
8174
8175         tw32_f(WDMAC_MODE, val);
8176         udelay(40);
8177
8178         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8179                 u16 pcix_cmd;
8180
8181                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8182                                      &pcix_cmd);
8183                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8184                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8185                         pcix_cmd |= PCI_X_CMD_READ_2K;
8186                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8187                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8188                         pcix_cmd |= PCI_X_CMD_READ_2K;
8189                 }
8190                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8191                                       pcix_cmd);
8192         }
8193
8194         tw32_f(RDMAC_MODE, rdmac_mode);
8195         udelay(40);
8196
8197         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8198         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8199                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8200
8201         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8202                 tw32(SNDDATAC_MODE,
8203                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8204         else
8205                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8206
8207         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8208         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8209         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8210         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8211         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8212                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8213         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8214         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8215                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8216         tw32(SNDBDI_MODE, val);
8217         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8218
8219         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8220                 err = tg3_load_5701_a0_firmware_fix(tp);
8221                 if (err)
8222                         return err;
8223         }
8224
8225         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8226                 err = tg3_load_tso_firmware(tp);
8227                 if (err)
8228                         return err;
8229         }
8230
8231         tp->tx_mode = TX_MODE_ENABLE;
8232         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
8233             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8234                 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
8235         tw32_f(MAC_TX_MODE, tp->tx_mode);
8236         udelay(100);
8237
8238         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8239                 u32 reg = MAC_RSS_INDIR_TBL_0;
8240                 u8 *ent = (u8 *)&val;
8241
8242                 /* Setup the indirection table */
8243                 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8244                         int idx = i % sizeof(val);
8245
8246                         ent[idx] = i % (tp->irq_cnt - 1);
8247                         if (idx == sizeof(val) - 1) {
8248                                 tw32(reg, val);
8249                                 reg += 4;
8250                         }
8251                 }
8252
8253                 /* Setup the "secret" hash key. */
8254                 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8255                 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8256                 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8257                 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8258                 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8259                 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8260                 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8261                 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8262                 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8263                 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8264         }
8265
8266         tp->rx_mode = RX_MODE_ENABLE;
8267         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8268                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8269
8270         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8271                 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8272                                RX_MODE_RSS_ITBL_HASH_BITS_7 |
8273                                RX_MODE_RSS_IPV6_HASH_EN |
8274                                RX_MODE_RSS_TCP_IPV6_HASH_EN |
8275                                RX_MODE_RSS_IPV4_HASH_EN |
8276                                RX_MODE_RSS_TCP_IPV4_HASH_EN;
8277
8278         tw32_f(MAC_RX_MODE, tp->rx_mode);
8279         udelay(10);
8280
8281         tw32(MAC_LED_CTRL, tp->led_ctrl);
8282
8283         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8284         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8285                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8286                 udelay(10);
8287         }
8288         tw32_f(MAC_RX_MODE, tp->rx_mode);
8289         udelay(10);
8290
8291         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8292                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8293                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
8294                         /* Set drive transmission level to 1.2V  */
8295                         /* only if the signal pre-emphasis bit is not set  */
8296                         val = tr32(MAC_SERDES_CFG);
8297                         val &= 0xfffff000;
8298                         val |= 0x880;
8299                         tw32(MAC_SERDES_CFG, val);
8300                 }
8301                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8302                         tw32(MAC_SERDES_CFG, 0x616000);
8303         }
8304
8305         /* Prevent chip from dropping frames when flow control
8306          * is enabled.
8307          */
8308         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8309                 val = 1;
8310         else
8311                 val = 2;
8312         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8313
8314         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8315             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8316                 /* Use hardware link auto-negotiation */
8317                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8318         }
8319
8320         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8321             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8322                 u32 tmp;
8323
8324                 tmp = tr32(SERDES_RX_CTRL);
8325                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8326                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8327                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8328                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8329         }
8330
8331         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8332                 if (tp->link_config.phy_is_low_power) {
8333                         tp->link_config.phy_is_low_power = 0;
8334                         tp->link_config.speed = tp->link_config.orig_speed;
8335                         tp->link_config.duplex = tp->link_config.orig_duplex;
8336                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
8337                 }
8338
8339                 err = tg3_setup_phy(tp, 0);
8340                 if (err)
8341                         return err;
8342
8343                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8344                     !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
8345                         u32 tmp;
8346
8347                         /* Clear CRC stats. */
8348                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8349                                 tg3_writephy(tp, MII_TG3_TEST1,
8350                                              tmp | MII_TG3_TEST1_CRC_EN);
8351                                 tg3_readphy(tp, 0x14, &tmp);
8352                         }
8353                 }
8354         }
8355
8356         __tg3_set_rx_mode(tp->dev);
8357
8358         /* Initialize receive rules. */
8359         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
8360         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8361         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
8362         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8363
8364         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8365             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8366                 limit = 8;
8367         else
8368                 limit = 16;
8369         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8370                 limit -= 4;
8371         switch (limit) {
8372         case 16:
8373                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
8374         case 15:
8375                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
8376         case 14:
8377                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
8378         case 13:
8379                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
8380         case 12:
8381                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
8382         case 11:
8383                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
8384         case 10:
8385                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
8386         case 9:
8387                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
8388         case 8:
8389                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
8390         case 7:
8391                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
8392         case 6:
8393                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
8394         case 5:
8395                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
8396         case 4:
8397                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
8398         case 3:
8399                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
8400         case 2:
8401         case 1:
8402
8403         default:
8404                 break;
8405         }
8406
8407         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8408                 /* Write our heartbeat update interval to APE. */
8409                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8410                                 APE_HOST_HEARTBEAT_INT_DISABLE);
8411
8412         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8413
8414         return 0;
8415 }
8416
8417 /* Called at device open time to get the chip ready for
8418  * packet processing.  Invoked with tp->lock held.
8419  */
8420 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8421 {
8422         tg3_switch_clocks(tp);
8423
8424         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8425
8426         return tg3_reset_hw(tp, reset_phy);
8427 }
8428
8429 #define TG3_STAT_ADD32(PSTAT, REG) \
8430 do {    u32 __val = tr32(REG); \
8431         (PSTAT)->low += __val; \
8432         if ((PSTAT)->low < __val) \
8433                 (PSTAT)->high += 1; \
8434 } while (0)
8435
8436 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8437 {
8438         struct tg3_hw_stats *sp = tp->hw_stats;
8439
8440         if (!netif_carrier_ok(tp->dev))
8441                 return;
8442
8443         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8444         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8445         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8446         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8447         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8448         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8449         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8450         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8451         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8452         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8453         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8454         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8455         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8456
8457         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8458         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8459         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8460         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8461         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8462         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8463         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8464         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8465         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8466         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8467         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8468         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8469         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8470         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8471
8472         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8473         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8474         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8475 }
8476
8477 static void tg3_timer(unsigned long __opaque)
8478 {
8479         struct tg3 *tp = (struct tg3 *) __opaque;
8480
8481         if (tp->irq_sync)
8482                 goto restart_timer;
8483
8484         spin_lock(&tp->lock);
8485
8486         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8487                 /* All of this garbage is because when using non-tagged
8488                  * IRQ status the mailbox/status_block protocol the chip
8489                  * uses with the cpu is race prone.
8490                  */
8491                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8492                         tw32(GRC_LOCAL_CTRL,
8493                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8494                 } else {
8495                         tw32(HOSTCC_MODE, tp->coalesce_mode |
8496                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8497                 }
8498
8499                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8500                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8501                         spin_unlock(&tp->lock);
8502                         schedule_work(&tp->reset_task);
8503                         return;
8504                 }
8505         }
8506
8507         /* This part only runs once per second. */
8508         if (!--tp->timer_counter) {
8509                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8510                         tg3_periodic_fetch_stats(tp);
8511
8512                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8513                         u32 mac_stat;
8514                         int phy_event;
8515
8516                         mac_stat = tr32(MAC_STATUS);
8517
8518                         phy_event = 0;
8519                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8520                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8521                                         phy_event = 1;
8522                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8523                                 phy_event = 1;
8524
8525                         if (phy_event)
8526                                 tg3_setup_phy(tp, 0);
8527                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8528                         u32 mac_stat = tr32(MAC_STATUS);
8529                         int need_setup = 0;
8530
8531                         if (netif_carrier_ok(tp->dev) &&
8532                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8533                                 need_setup = 1;
8534                         }
8535                         if (!netif_carrier_ok(tp->dev) &&
8536                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
8537                                          MAC_STATUS_SIGNAL_DET))) {
8538                                 need_setup = 1;
8539                         }
8540                         if (need_setup) {
8541                                 if (!tp->serdes_counter) {
8542                                         tw32_f(MAC_MODE,
8543                                              (tp->mac_mode &
8544                                               ~MAC_MODE_PORT_MODE_MASK));
8545                                         udelay(40);
8546                                         tw32_f(MAC_MODE, tp->mac_mode);
8547                                         udelay(40);
8548                                 }
8549                                 tg3_setup_phy(tp, 0);
8550                         }
8551                 } else if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8552                            (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8553                         tg3_serdes_parallel_detect(tp);
8554                 }
8555
8556                 tp->timer_counter = tp->timer_multiplier;
8557         }
8558
8559         /* Heartbeat is only sent once every 2 seconds.
8560          *
8561          * The heartbeat is to tell the ASF firmware that the host
8562          * driver is still alive.  In the event that the OS crashes,
8563          * ASF needs to reset the hardware to free up the FIFO space
8564          * that may be filled with rx packets destined for the host.
8565          * If the FIFO is full, ASF will no longer function properly.
8566          *
8567          * Unintended resets have been reported on real time kernels
8568          * where the timer doesn't run on time.  Netpoll will also have
8569          * same problem.
8570          *
8571          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8572          * to check the ring condition when the heartbeat is expiring
8573          * before doing the reset.  This will prevent most unintended
8574          * resets.
8575          */
8576         if (!--tp->asf_counter) {
8577                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8578                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8579                         tg3_wait_for_event_ack(tp);
8580
8581                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8582                                       FWCMD_NICDRV_ALIVE3);
8583                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8584                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
8585                                       TG3_FW_UPDATE_TIMEOUT_SEC);
8586
8587                         tg3_generate_fw_event(tp);
8588                 }
8589                 tp->asf_counter = tp->asf_multiplier;
8590         }
8591
8592         spin_unlock(&tp->lock);
8593
8594 restart_timer:
8595         tp->timer.expires = jiffies + tp->timer_offset;
8596         add_timer(&tp->timer);
8597 }
8598
8599 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8600 {
8601         irq_handler_t fn;
8602         unsigned long flags;
8603         char *name;
8604         struct tg3_napi *tnapi = &tp->napi[irq_num];
8605
8606         if (tp->irq_cnt == 1)
8607                 name = tp->dev->name;
8608         else {
8609                 name = &tnapi->irq_lbl[0];
8610                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8611                 name[IFNAMSIZ-1] = 0;
8612         }
8613
8614         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8615                 fn = tg3_msi;
8616                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8617                         fn = tg3_msi_1shot;
8618                 flags = IRQF_SAMPLE_RANDOM;
8619         } else {
8620                 fn = tg3_interrupt;
8621                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8622                         fn = tg3_interrupt_tagged;
8623                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8624         }
8625
8626         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8627 }
8628
8629 static int tg3_test_interrupt(struct tg3 *tp)
8630 {
8631         struct tg3_napi *tnapi = &tp->napi[0];
8632         struct net_device *dev = tp->dev;
8633         int err, i, intr_ok = 0;
8634         u32 val;
8635
8636         if (!netif_running(dev))
8637                 return -ENODEV;
8638
8639         tg3_disable_ints(tp);
8640
8641         free_irq(tnapi->irq_vec, tnapi);
8642
8643         /*
8644          * Turn off MSI one shot mode.  Otherwise this test has no
8645          * observable way to know whether the interrupt was delivered.
8646          */
8647         if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8648             (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8649                 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8650                 tw32(MSGINT_MODE, val);
8651         }
8652
8653         err = request_irq(tnapi->irq_vec, tg3_test_isr,
8654                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8655         if (err)
8656                 return err;
8657
8658         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8659         tg3_enable_ints(tp);
8660
8661         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8662                tnapi->coal_now);
8663
8664         for (i = 0; i < 5; i++) {
8665                 u32 int_mbox, misc_host_ctrl;
8666
8667                 int_mbox = tr32_mailbox(tnapi->int_mbox);
8668                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8669
8670                 if ((int_mbox != 0) ||
8671                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8672                         intr_ok = 1;
8673                         break;
8674                 }
8675
8676                 msleep(10);
8677         }
8678
8679         tg3_disable_ints(tp);
8680
8681         free_irq(tnapi->irq_vec, tnapi);
8682
8683         err = tg3_request_irq(tp, 0);
8684
8685         if (err)
8686                 return err;
8687
8688         if (intr_ok) {
8689                 /* Reenable MSI one shot mode. */
8690                 if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8691                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8692                         val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8693                         tw32(MSGINT_MODE, val);
8694                 }
8695                 return 0;
8696         }
8697
8698         return -EIO;
8699 }
8700
8701 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8702  * successfully restored
8703  */
8704 static int tg3_test_msi(struct tg3 *tp)
8705 {
8706         int err;
8707         u16 pci_cmd;
8708
8709         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8710                 return 0;
8711
8712         /* Turn off SERR reporting in case MSI terminates with Master
8713          * Abort.
8714          */
8715         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8716         pci_write_config_word(tp->pdev, PCI_COMMAND,
8717                               pci_cmd & ~PCI_COMMAND_SERR);
8718
8719         err = tg3_test_interrupt(tp);
8720
8721         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8722
8723         if (!err)
8724                 return 0;
8725
8726         /* other failures */
8727         if (err != -EIO)
8728                 return err;
8729
8730         /* MSI test failed, go back to INTx mode */
8731         netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
8732                     "to INTx mode. Please report this failure to the PCI "
8733                     "maintainer and include system chipset information\n");
8734
8735         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8736
8737         pci_disable_msi(tp->pdev);
8738
8739         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8740         tp->napi[0].irq_vec = tp->pdev->irq;
8741
8742         err = tg3_request_irq(tp, 0);
8743         if (err)
8744                 return err;
8745
8746         /* Need to reset the chip because the MSI cycle may have terminated
8747          * with Master Abort.
8748          */
8749         tg3_full_lock(tp, 1);
8750
8751         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8752         err = tg3_init_hw(tp, 1);
8753
8754         tg3_full_unlock(tp);
8755
8756         if (err)
8757                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8758
8759         return err;
8760 }
8761
8762 static int tg3_request_firmware(struct tg3 *tp)
8763 {
8764         const __be32 *fw_data;
8765
8766         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8767                 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
8768                            tp->fw_needed);
8769                 return -ENOENT;
8770         }
8771
8772         fw_data = (void *)tp->fw->data;
8773
8774         /* Firmware blob starts with version numbers, followed by
8775          * start address and _full_ length including BSS sections
8776          * (which must be longer than the actual data, of course
8777          */
8778
8779         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
8780         if (tp->fw_len < (tp->fw->size - 12)) {
8781                 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
8782                            tp->fw_len, tp->fw_needed);
8783                 release_firmware(tp->fw);
8784                 tp->fw = NULL;
8785                 return -EINVAL;
8786         }
8787
8788         /* We no longer need firmware; we have it. */
8789         tp->fw_needed = NULL;
8790         return 0;
8791 }
8792
8793 static bool tg3_enable_msix(struct tg3 *tp)
8794 {
8795         int i, rc, cpus = num_online_cpus();
8796         struct msix_entry msix_ent[tp->irq_max];
8797
8798         if (cpus == 1)
8799                 /* Just fallback to the simpler MSI mode. */
8800                 return false;
8801
8802         /*
8803          * We want as many rx rings enabled as there are cpus.
8804          * The first MSIX vector only deals with link interrupts, etc,
8805          * so we add one to the number of vectors we are requesting.
8806          */
8807         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8808
8809         for (i = 0; i < tp->irq_max; i++) {
8810                 msix_ent[i].entry  = i;
8811                 msix_ent[i].vector = 0;
8812         }
8813
8814         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8815         if (rc < 0) {
8816                 return false;
8817         } else if (rc != 0) {
8818                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8819                         return false;
8820                 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
8821                               tp->irq_cnt, rc);
8822                 tp->irq_cnt = rc;
8823         }
8824
8825         for (i = 0; i < tp->irq_max; i++)
8826                 tp->napi[i].irq_vec = msix_ent[i].vector;
8827
8828         tp->dev->real_num_tx_queues = 1;
8829         if (tp->irq_cnt > 1) {
8830                 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8831
8832                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8833                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
8834                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
8835                         tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8836                 }
8837         }
8838
8839         return true;
8840 }
8841
8842 static void tg3_ints_init(struct tg3 *tp)
8843 {
8844         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8845             !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8846                 /* All MSI supporting chips should support tagged
8847                  * status.  Assert that this is the case.
8848                  */
8849                 netdev_warn(tp->dev,
8850                             "MSI without TAGGED_STATUS? Not using MSI\n");
8851                 goto defcfg;
8852         }
8853
8854         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8855                 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8856         else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8857                  pci_enable_msi(tp->pdev) == 0)
8858                 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8859
8860         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8861                 u32 msi_mode = tr32(MSGINT_MODE);
8862                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8863                         msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8864                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8865         }
8866 defcfg:
8867         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8868                 tp->irq_cnt = 1;
8869                 tp->napi[0].irq_vec = tp->pdev->irq;
8870                 tp->dev->real_num_tx_queues = 1;
8871         }
8872 }
8873
8874 static void tg3_ints_fini(struct tg3 *tp)
8875 {
8876         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8877                 pci_disable_msix(tp->pdev);
8878         else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8879                 pci_disable_msi(tp->pdev);
8880         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8881         tp->tg3_flags3 &= ~(TG3_FLG3_ENABLE_RSS | TG3_FLG3_ENABLE_TSS);
8882 }
8883
8884 static int tg3_open(struct net_device *dev)
8885 {
8886         struct tg3 *tp = netdev_priv(dev);
8887         int i, err;
8888
8889         if (tp->fw_needed) {
8890                 err = tg3_request_firmware(tp);
8891                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8892                         if (err)
8893                                 return err;
8894                 } else if (err) {
8895                         netdev_warn(tp->dev, "TSO capability disabled\n");
8896                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8897                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8898                         netdev_notice(tp->dev, "TSO capability restored\n");
8899                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8900                 }
8901         }
8902
8903         netif_carrier_off(tp->dev);
8904
8905         err = tg3_set_power_state(tp, PCI_D0);
8906         if (err)
8907                 return err;
8908
8909         tg3_full_lock(tp, 0);
8910
8911         tg3_disable_ints(tp);
8912         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8913
8914         tg3_full_unlock(tp);
8915
8916         /*
8917          * Setup interrupts first so we know how
8918          * many NAPI resources to allocate
8919          */
8920         tg3_ints_init(tp);
8921
8922         /* The placement of this call is tied
8923          * to the setup and use of Host TX descriptors.
8924          */
8925         err = tg3_alloc_consistent(tp);
8926         if (err)
8927                 goto err_out1;
8928
8929         tg3_napi_enable(tp);
8930
8931         for (i = 0; i < tp->irq_cnt; i++) {
8932                 struct tg3_napi *tnapi = &tp->napi[i];
8933                 err = tg3_request_irq(tp, i);
8934                 if (err) {
8935                         for (i--; i >= 0; i--)
8936                                 free_irq(tnapi->irq_vec, tnapi);
8937                         break;
8938                 }
8939         }
8940
8941         if (err)
8942                 goto err_out2;
8943
8944         tg3_full_lock(tp, 0);
8945
8946         err = tg3_init_hw(tp, 1);
8947         if (err) {
8948                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8949                 tg3_free_rings(tp);
8950         } else {
8951                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8952                         tp->timer_offset = HZ;
8953                 else
8954                         tp->timer_offset = HZ / 10;
8955
8956                 BUG_ON(tp->timer_offset > HZ);
8957                 tp->timer_counter = tp->timer_multiplier =
8958                         (HZ / tp->timer_offset);
8959                 tp->asf_counter = tp->asf_multiplier =
8960                         ((HZ / tp->timer_offset) * 2);
8961
8962                 init_timer(&tp->timer);
8963                 tp->timer.expires = jiffies + tp->timer_offset;
8964                 tp->timer.data = (unsigned long) tp;
8965                 tp->timer.function = tg3_timer;
8966         }
8967
8968         tg3_full_unlock(tp);
8969
8970         if (err)
8971                 goto err_out3;
8972
8973         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8974                 err = tg3_test_msi(tp);
8975
8976                 if (err) {
8977                         tg3_full_lock(tp, 0);
8978                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8979                         tg3_free_rings(tp);
8980                         tg3_full_unlock(tp);
8981
8982                         goto err_out2;
8983                 }
8984
8985                 if (!(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8986                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8987                         u32 val = tr32(PCIE_TRANSACTION_CFG);
8988
8989                         tw32(PCIE_TRANSACTION_CFG,
8990                              val | PCIE_TRANS_CFG_1SHOT_MSI);
8991                 }
8992         }
8993
8994         tg3_phy_start(tp);
8995
8996         tg3_full_lock(tp, 0);
8997
8998         add_timer(&tp->timer);
8999         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9000         tg3_enable_ints(tp);
9001
9002         tg3_full_unlock(tp);
9003
9004         netif_tx_start_all_queues(dev);
9005
9006         return 0;
9007
9008 err_out3:
9009         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9010                 struct tg3_napi *tnapi = &tp->napi[i];
9011                 free_irq(tnapi->irq_vec, tnapi);
9012         }
9013
9014 err_out2:
9015         tg3_napi_disable(tp);
9016         tg3_free_consistent(tp);
9017
9018 err_out1:
9019         tg3_ints_fini(tp);
9020         return err;
9021 }
9022
9023 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
9024                                                  struct rtnl_link_stats64 *);
9025 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9026
9027 static int tg3_close(struct net_device *dev)
9028 {
9029         int i;
9030         struct tg3 *tp = netdev_priv(dev);
9031
9032         tg3_napi_disable(tp);
9033         cancel_work_sync(&tp->reset_task);
9034
9035         netif_tx_stop_all_queues(dev);
9036
9037         del_timer_sync(&tp->timer);
9038
9039         tg3_phy_stop(tp);
9040
9041         tg3_full_lock(tp, 1);
9042
9043         tg3_disable_ints(tp);
9044
9045         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9046         tg3_free_rings(tp);
9047         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9048
9049         tg3_full_unlock(tp);
9050
9051         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9052                 struct tg3_napi *tnapi = &tp->napi[i];
9053                 free_irq(tnapi->irq_vec, tnapi);
9054         }
9055
9056         tg3_ints_fini(tp);
9057
9058         tg3_get_stats64(tp->dev, &tp->net_stats_prev);
9059
9060         memcpy(&tp->estats_prev, tg3_get_estats(tp),
9061                sizeof(tp->estats_prev));
9062
9063         tg3_free_consistent(tp);
9064
9065         tg3_set_power_state(tp, PCI_D3hot);
9066
9067         netif_carrier_off(tp->dev);
9068
9069         return 0;
9070 }
9071
9072 static inline u64 get_stat64(tg3_stat64_t *val)
9073 {
9074        return ((u64)val->high << 32) | ((u64)val->low);
9075 }
9076
9077 static u64 calc_crc_errors(struct tg3 *tp)
9078 {
9079         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9080
9081         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9082             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9083              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9084                 u32 val;
9085
9086                 spin_lock_bh(&tp->lock);
9087                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9088                         tg3_writephy(tp, MII_TG3_TEST1,
9089                                      val | MII_TG3_TEST1_CRC_EN);
9090                         tg3_readphy(tp, 0x14, &val);
9091                 } else
9092                         val = 0;
9093                 spin_unlock_bh(&tp->lock);
9094
9095                 tp->phy_crc_errors += val;
9096
9097                 return tp->phy_crc_errors;
9098         }
9099
9100         return get_stat64(&hw_stats->rx_fcs_errors);
9101 }
9102
9103 #define ESTAT_ADD(member) \
9104         estats->member =        old_estats->member + \
9105                                 get_stat64(&hw_stats->member)
9106
9107 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9108 {
9109         struct tg3_ethtool_stats *estats = &tp->estats;
9110         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9111         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9112
9113         if (!hw_stats)
9114                 return old_estats;
9115
9116         ESTAT_ADD(rx_octets);
9117         ESTAT_ADD(rx_fragments);
9118         ESTAT_ADD(rx_ucast_packets);
9119         ESTAT_ADD(rx_mcast_packets);
9120         ESTAT_ADD(rx_bcast_packets);
9121         ESTAT_ADD(rx_fcs_errors);
9122         ESTAT_ADD(rx_align_errors);
9123         ESTAT_ADD(rx_xon_pause_rcvd);
9124         ESTAT_ADD(rx_xoff_pause_rcvd);
9125         ESTAT_ADD(rx_mac_ctrl_rcvd);
9126         ESTAT_ADD(rx_xoff_entered);
9127         ESTAT_ADD(rx_frame_too_long_errors);
9128         ESTAT_ADD(rx_jabbers);
9129         ESTAT_ADD(rx_undersize_packets);
9130         ESTAT_ADD(rx_in_length_errors);
9131         ESTAT_ADD(rx_out_length_errors);
9132         ESTAT_ADD(rx_64_or_less_octet_packets);
9133         ESTAT_ADD(rx_65_to_127_octet_packets);
9134         ESTAT_ADD(rx_128_to_255_octet_packets);
9135         ESTAT_ADD(rx_256_to_511_octet_packets);
9136         ESTAT_ADD(rx_512_to_1023_octet_packets);
9137         ESTAT_ADD(rx_1024_to_1522_octet_packets);
9138         ESTAT_ADD(rx_1523_to_2047_octet_packets);
9139         ESTAT_ADD(rx_2048_to_4095_octet_packets);
9140         ESTAT_ADD(rx_4096_to_8191_octet_packets);
9141         ESTAT_ADD(rx_8192_to_9022_octet_packets);
9142
9143         ESTAT_ADD(tx_octets);
9144         ESTAT_ADD(tx_collisions);
9145         ESTAT_ADD(tx_xon_sent);
9146         ESTAT_ADD(tx_xoff_sent);
9147         ESTAT_ADD(tx_flow_control);
9148         ESTAT_ADD(tx_mac_errors);
9149         ESTAT_ADD(tx_single_collisions);
9150         ESTAT_ADD(tx_mult_collisions);
9151         ESTAT_ADD(tx_deferred);
9152         ESTAT_ADD(tx_excessive_collisions);
9153         ESTAT_ADD(tx_late_collisions);
9154         ESTAT_ADD(tx_collide_2times);
9155         ESTAT_ADD(tx_collide_3times);
9156         ESTAT_ADD(tx_collide_4times);
9157         ESTAT_ADD(tx_collide_5times);
9158         ESTAT_ADD(tx_collide_6times);
9159         ESTAT_ADD(tx_collide_7times);
9160         ESTAT_ADD(tx_collide_8times);
9161         ESTAT_ADD(tx_collide_9times);
9162         ESTAT_ADD(tx_collide_10times);
9163         ESTAT_ADD(tx_collide_11times);
9164         ESTAT_ADD(tx_collide_12times);
9165         ESTAT_ADD(tx_collide_13times);
9166         ESTAT_ADD(tx_collide_14times);
9167         ESTAT_ADD(tx_collide_15times);
9168         ESTAT_ADD(tx_ucast_packets);
9169         ESTAT_ADD(tx_mcast_packets);
9170         ESTAT_ADD(tx_bcast_packets);
9171         ESTAT_ADD(tx_carrier_sense_errors);
9172         ESTAT_ADD(tx_discards);
9173         ESTAT_ADD(tx_errors);
9174
9175         ESTAT_ADD(dma_writeq_full);
9176         ESTAT_ADD(dma_write_prioq_full);
9177         ESTAT_ADD(rxbds_empty);
9178         ESTAT_ADD(rx_discards);
9179         ESTAT_ADD(rx_errors);
9180         ESTAT_ADD(rx_threshold_hit);
9181
9182         ESTAT_ADD(dma_readq_full);
9183         ESTAT_ADD(dma_read_prioq_full);
9184         ESTAT_ADD(tx_comp_queue_full);
9185
9186         ESTAT_ADD(ring_set_send_prod_index);
9187         ESTAT_ADD(ring_status_update);
9188         ESTAT_ADD(nic_irqs);
9189         ESTAT_ADD(nic_avoided_irqs);
9190         ESTAT_ADD(nic_tx_threshold_hit);
9191
9192         return estats;
9193 }
9194
9195 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
9196                                                  struct rtnl_link_stats64 *stats)
9197 {
9198         struct tg3 *tp = netdev_priv(dev);
9199         struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
9200         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9201
9202         if (!hw_stats)
9203                 return old_stats;
9204
9205         stats->rx_packets = old_stats->rx_packets +
9206                 get_stat64(&hw_stats->rx_ucast_packets) +
9207                 get_stat64(&hw_stats->rx_mcast_packets) +
9208                 get_stat64(&hw_stats->rx_bcast_packets);
9209
9210         stats->tx_packets = old_stats->tx_packets +
9211                 get_stat64(&hw_stats->tx_ucast_packets) +
9212                 get_stat64(&hw_stats->tx_mcast_packets) +
9213                 get_stat64(&hw_stats->tx_bcast_packets);
9214
9215         stats->rx_bytes = old_stats->rx_bytes +
9216                 get_stat64(&hw_stats->rx_octets);
9217         stats->tx_bytes = old_stats->tx_bytes +
9218                 get_stat64(&hw_stats->tx_octets);
9219
9220         stats->rx_errors = old_stats->rx_errors +
9221                 get_stat64(&hw_stats->rx_errors);
9222         stats->tx_errors = old_stats->tx_errors +
9223                 get_stat64(&hw_stats->tx_errors) +
9224                 get_stat64(&hw_stats->tx_mac_errors) +
9225                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9226                 get_stat64(&hw_stats->tx_discards);
9227
9228         stats->multicast = old_stats->multicast +
9229                 get_stat64(&hw_stats->rx_mcast_packets);
9230         stats->collisions = old_stats->collisions +
9231                 get_stat64(&hw_stats->tx_collisions);
9232
9233         stats->rx_length_errors = old_stats->rx_length_errors +
9234                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9235                 get_stat64(&hw_stats->rx_undersize_packets);
9236
9237         stats->rx_over_errors = old_stats->rx_over_errors +
9238                 get_stat64(&hw_stats->rxbds_empty);
9239         stats->rx_frame_errors = old_stats->rx_frame_errors +
9240                 get_stat64(&hw_stats->rx_align_errors);
9241         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9242                 get_stat64(&hw_stats->tx_discards);
9243         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9244                 get_stat64(&hw_stats->tx_carrier_sense_errors);
9245
9246         stats->rx_crc_errors = old_stats->rx_crc_errors +
9247                 calc_crc_errors(tp);
9248
9249         stats->rx_missed_errors = old_stats->rx_missed_errors +
9250                 get_stat64(&hw_stats->rx_discards);
9251
9252         return stats;
9253 }
9254
9255 static inline u32 calc_crc(unsigned char *buf, int len)
9256 {
9257         u32 reg;
9258         u32 tmp;
9259         int j, k;
9260
9261         reg = 0xffffffff;
9262
9263         for (j = 0; j < len; j++) {
9264                 reg ^= buf[j];
9265
9266                 for (k = 0; k < 8; k++) {
9267                         tmp = reg & 0x01;
9268
9269                         reg >>= 1;
9270
9271                         if (tmp)
9272                                 reg ^= 0xedb88320;
9273                 }
9274         }
9275
9276         return ~reg;
9277 }
9278
9279 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9280 {
9281         /* accept or reject all multicast frames */
9282         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9283         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9284         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9285         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9286 }
9287
9288 static void __tg3_set_rx_mode(struct net_device *dev)
9289 {
9290         struct tg3 *tp = netdev_priv(dev);
9291         u32 rx_mode;
9292
9293         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9294                                   RX_MODE_KEEP_VLAN_TAG);
9295
9296         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9297          * flag clear.
9298          */
9299 #if TG3_VLAN_TAG_USED
9300         if (!tp->vlgrp &&
9301             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9302                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9303 #else
9304         /* By definition, VLAN is disabled always in this
9305          * case.
9306          */
9307         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9308                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9309 #endif
9310
9311         if (dev->flags & IFF_PROMISC) {
9312                 /* Promiscuous mode. */
9313                 rx_mode |= RX_MODE_PROMISC;
9314         } else if (dev->flags & IFF_ALLMULTI) {
9315                 /* Accept all multicast. */
9316                 tg3_set_multi(tp, 1);
9317         } else if (netdev_mc_empty(dev)) {
9318                 /* Reject all multicast. */
9319                 tg3_set_multi(tp, 0);
9320         } else {
9321                 /* Accept one or more multicast(s). */
9322                 struct netdev_hw_addr *ha;
9323                 u32 mc_filter[4] = { 0, };
9324                 u32 regidx;
9325                 u32 bit;
9326                 u32 crc;
9327
9328                 netdev_for_each_mc_addr(ha, dev) {
9329                         crc = calc_crc(ha->addr, ETH_ALEN);
9330                         bit = ~crc & 0x7f;
9331                         regidx = (bit & 0x60) >> 5;
9332                         bit &= 0x1f;
9333                         mc_filter[regidx] |= (1 << bit);
9334                 }
9335
9336                 tw32(MAC_HASH_REG_0, mc_filter[0]);
9337                 tw32(MAC_HASH_REG_1, mc_filter[1]);
9338                 tw32(MAC_HASH_REG_2, mc_filter[2]);
9339                 tw32(MAC_HASH_REG_3, mc_filter[3]);
9340         }
9341
9342         if (rx_mode != tp->rx_mode) {
9343                 tp->rx_mode = rx_mode;
9344                 tw32_f(MAC_RX_MODE, rx_mode);
9345                 udelay(10);
9346         }
9347 }
9348
9349 static void tg3_set_rx_mode(struct net_device *dev)
9350 {
9351         struct tg3 *tp = netdev_priv(dev);
9352
9353         if (!netif_running(dev))
9354                 return;
9355
9356         tg3_full_lock(tp, 0);
9357         __tg3_set_rx_mode(dev);
9358         tg3_full_unlock(tp);
9359 }
9360
9361 #define TG3_REGDUMP_LEN         (32 * 1024)
9362
9363 static int tg3_get_regs_len(struct net_device *dev)
9364 {
9365         return TG3_REGDUMP_LEN;
9366 }
9367
9368 static void tg3_get_regs(struct net_device *dev,
9369                 struct ethtool_regs *regs, void *_p)
9370 {
9371         u32 *p = _p;
9372         struct tg3 *tp = netdev_priv(dev);
9373         u8 *orig_p = _p;
9374         int i;
9375
9376         regs->version = 0;
9377
9378         memset(p, 0, TG3_REGDUMP_LEN);
9379
9380         if (tp->link_config.phy_is_low_power)
9381                 return;
9382
9383         tg3_full_lock(tp, 0);
9384
9385 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
9386 #define GET_REG32_LOOP(base, len)               \
9387 do {    p = (u32 *)(orig_p + (base));           \
9388         for (i = 0; i < len; i += 4)            \
9389                 __GET_REG32((base) + i);        \
9390 } while (0)
9391 #define GET_REG32_1(reg)                        \
9392 do {    p = (u32 *)(orig_p + (reg));            \
9393         __GET_REG32((reg));                     \
9394 } while (0)
9395
9396         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9397         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9398         GET_REG32_LOOP(MAC_MODE, 0x4f0);
9399         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9400         GET_REG32_1(SNDDATAC_MODE);
9401         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9402         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9403         GET_REG32_1(SNDBDC_MODE);
9404         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9405         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9406         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9407         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9408         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9409         GET_REG32_1(RCVDCC_MODE);
9410         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9411         GET_REG32_LOOP(RCVCC_MODE, 0x14);
9412         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9413         GET_REG32_1(MBFREE_MODE);
9414         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9415         GET_REG32_LOOP(MEMARB_MODE, 0x10);
9416         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9417         GET_REG32_LOOP(RDMAC_MODE, 0x08);
9418         GET_REG32_LOOP(WDMAC_MODE, 0x08);
9419         GET_REG32_1(RX_CPU_MODE);
9420         GET_REG32_1(RX_CPU_STATE);
9421         GET_REG32_1(RX_CPU_PGMCTR);
9422         GET_REG32_1(RX_CPU_HWBKPT);
9423         GET_REG32_1(TX_CPU_MODE);
9424         GET_REG32_1(TX_CPU_STATE);
9425         GET_REG32_1(TX_CPU_PGMCTR);
9426         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9427         GET_REG32_LOOP(FTQ_RESET, 0x120);
9428         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9429         GET_REG32_1(DMAC_MODE);
9430         GET_REG32_LOOP(GRC_MODE, 0x4c);
9431         if (tp->tg3_flags & TG3_FLAG_NVRAM)
9432                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9433
9434 #undef __GET_REG32
9435 #undef GET_REG32_LOOP
9436 #undef GET_REG32_1
9437
9438         tg3_full_unlock(tp);
9439 }
9440
9441 static int tg3_get_eeprom_len(struct net_device *dev)
9442 {
9443         struct tg3 *tp = netdev_priv(dev);
9444
9445         return tp->nvram_size;
9446 }
9447
9448 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9449 {
9450         struct tg3 *tp = netdev_priv(dev);
9451         int ret;
9452         u8  *pd;
9453         u32 i, offset, len, b_offset, b_count;
9454         __be32 val;
9455
9456         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9457                 return -EINVAL;
9458
9459         if (tp->link_config.phy_is_low_power)
9460                 return -EAGAIN;
9461
9462         offset = eeprom->offset;
9463         len = eeprom->len;
9464         eeprom->len = 0;
9465
9466         eeprom->magic = TG3_EEPROM_MAGIC;
9467
9468         if (offset & 3) {
9469                 /* adjustments to start on required 4 byte boundary */
9470                 b_offset = offset & 3;
9471                 b_count = 4 - b_offset;
9472                 if (b_count > len) {
9473                         /* i.e. offset=1 len=2 */
9474                         b_count = len;
9475                 }
9476                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9477                 if (ret)
9478                         return ret;
9479                 memcpy(data, ((char *)&val) + b_offset, b_count);
9480                 len -= b_count;
9481                 offset += b_count;
9482                 eeprom->len += b_count;
9483         }
9484
9485         /* read bytes upto the last 4 byte boundary */
9486         pd = &data[eeprom->len];
9487         for (i = 0; i < (len - (len & 3)); i += 4) {
9488                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9489                 if (ret) {
9490                         eeprom->len += i;
9491                         return ret;
9492                 }
9493                 memcpy(pd + i, &val, 4);
9494         }
9495         eeprom->len += i;
9496
9497         if (len & 3) {
9498                 /* read last bytes not ending on 4 byte boundary */
9499                 pd = &data[eeprom->len];
9500                 b_count = len & 3;
9501                 b_offset = offset + len - b_count;
9502                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9503                 if (ret)
9504                         return ret;
9505                 memcpy(pd, &val, b_count);
9506                 eeprom->len += b_count;
9507         }
9508         return 0;
9509 }
9510
9511 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9512
9513 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9514 {
9515         struct tg3 *tp = netdev_priv(dev);
9516         int ret;
9517         u32 offset, len, b_offset, odd_len;
9518         u8 *buf;
9519         __be32 start, end;
9520
9521         if (tp->link_config.phy_is_low_power)
9522                 return -EAGAIN;
9523
9524         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9525             eeprom->magic != TG3_EEPROM_MAGIC)
9526                 return -EINVAL;
9527
9528         offset = eeprom->offset;
9529         len = eeprom->len;
9530
9531         if ((b_offset = (offset & 3))) {
9532                 /* adjustments to start on required 4 byte boundary */
9533                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9534                 if (ret)
9535                         return ret;
9536                 len += b_offset;
9537                 offset &= ~3;
9538                 if (len < 4)
9539                         len = 4;
9540         }
9541
9542         odd_len = 0;
9543         if (len & 3) {
9544                 /* adjustments to end on required 4 byte boundary */
9545                 odd_len = 1;
9546                 len = (len + 3) & ~3;
9547                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9548                 if (ret)
9549                         return ret;
9550         }
9551
9552         buf = data;
9553         if (b_offset || odd_len) {
9554                 buf = kmalloc(len, GFP_KERNEL);
9555                 if (!buf)
9556                         return -ENOMEM;
9557                 if (b_offset)
9558                         memcpy(buf, &start, 4);
9559                 if (odd_len)
9560                         memcpy(buf+len-4, &end, 4);
9561                 memcpy(buf + b_offset, data, eeprom->len);
9562         }
9563
9564         ret = tg3_nvram_write_block(tp, offset, len, buf);
9565
9566         if (buf != data)
9567                 kfree(buf);
9568
9569         return ret;
9570 }
9571
9572 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9573 {
9574         struct tg3 *tp = netdev_priv(dev);
9575
9576         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9577                 struct phy_device *phydev;
9578                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9579                         return -EAGAIN;
9580                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9581                 return phy_ethtool_gset(phydev, cmd);
9582         }
9583
9584         cmd->supported = (SUPPORTED_Autoneg);
9585
9586         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9587                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9588                                    SUPPORTED_1000baseT_Full);
9589
9590         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
9591                 cmd->supported |= (SUPPORTED_100baseT_Half |
9592                                   SUPPORTED_100baseT_Full |
9593                                   SUPPORTED_10baseT_Half |
9594                                   SUPPORTED_10baseT_Full |
9595                                   SUPPORTED_TP);
9596                 cmd->port = PORT_TP;
9597         } else {
9598                 cmd->supported |= SUPPORTED_FIBRE;
9599                 cmd->port = PORT_FIBRE;
9600         }
9601
9602         cmd->advertising = tp->link_config.advertising;
9603         if (netif_running(dev)) {
9604                 cmd->speed = tp->link_config.active_speed;
9605                 cmd->duplex = tp->link_config.active_duplex;
9606         }
9607         cmd->phy_address = tp->phy_addr;
9608         cmd->transceiver = XCVR_INTERNAL;
9609         cmd->autoneg = tp->link_config.autoneg;
9610         cmd->maxtxpkt = 0;
9611         cmd->maxrxpkt = 0;
9612         return 0;
9613 }
9614
9615 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9616 {
9617         struct tg3 *tp = netdev_priv(dev);
9618
9619         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9620                 struct phy_device *phydev;
9621                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9622                         return -EAGAIN;
9623                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9624                 return phy_ethtool_sset(phydev, cmd);
9625         }
9626
9627         if (cmd->autoneg != AUTONEG_ENABLE &&
9628             cmd->autoneg != AUTONEG_DISABLE)
9629                 return -EINVAL;
9630
9631         if (cmd->autoneg == AUTONEG_DISABLE &&
9632             cmd->duplex != DUPLEX_FULL &&
9633             cmd->duplex != DUPLEX_HALF)
9634                 return -EINVAL;
9635
9636         if (cmd->autoneg == AUTONEG_ENABLE) {
9637                 u32 mask = ADVERTISED_Autoneg |
9638                            ADVERTISED_Pause |
9639                            ADVERTISED_Asym_Pause;
9640
9641                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9642                         mask |= ADVERTISED_1000baseT_Half |
9643                                 ADVERTISED_1000baseT_Full;
9644
9645                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9646                         mask |= ADVERTISED_100baseT_Half |
9647                                 ADVERTISED_100baseT_Full |
9648                                 ADVERTISED_10baseT_Half |
9649                                 ADVERTISED_10baseT_Full |
9650                                 ADVERTISED_TP;
9651                 else
9652                         mask |= ADVERTISED_FIBRE;
9653
9654                 if (cmd->advertising & ~mask)
9655                         return -EINVAL;
9656
9657                 mask &= (ADVERTISED_1000baseT_Half |
9658                          ADVERTISED_1000baseT_Full |
9659                          ADVERTISED_100baseT_Half |
9660                          ADVERTISED_100baseT_Full |
9661                          ADVERTISED_10baseT_Half |
9662                          ADVERTISED_10baseT_Full);
9663
9664                 cmd->advertising &= mask;
9665         } else {
9666                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9667                         if (cmd->speed != SPEED_1000)
9668                                 return -EINVAL;
9669
9670                         if (cmd->duplex != DUPLEX_FULL)
9671                                 return -EINVAL;
9672                 } else {
9673                         if (cmd->speed != SPEED_100 &&
9674                             cmd->speed != SPEED_10)
9675                                 return -EINVAL;
9676                 }
9677         }
9678
9679         tg3_full_lock(tp, 0);
9680
9681         tp->link_config.autoneg = cmd->autoneg;
9682         if (cmd->autoneg == AUTONEG_ENABLE) {
9683                 tp->link_config.advertising = (cmd->advertising |
9684                                               ADVERTISED_Autoneg);
9685                 tp->link_config.speed = SPEED_INVALID;
9686                 tp->link_config.duplex = DUPLEX_INVALID;
9687         } else {
9688                 tp->link_config.advertising = 0;
9689                 tp->link_config.speed = cmd->speed;
9690                 tp->link_config.duplex = cmd->duplex;
9691         }
9692
9693         tp->link_config.orig_speed = tp->link_config.speed;
9694         tp->link_config.orig_duplex = tp->link_config.duplex;
9695         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9696
9697         if (netif_running(dev))
9698                 tg3_setup_phy(tp, 1);
9699
9700         tg3_full_unlock(tp);
9701
9702         return 0;
9703 }
9704
9705 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9706 {
9707         struct tg3 *tp = netdev_priv(dev);
9708
9709         strcpy(info->driver, DRV_MODULE_NAME);
9710         strcpy(info->version, DRV_MODULE_VERSION);
9711         strcpy(info->fw_version, tp->fw_ver);
9712         strcpy(info->bus_info, pci_name(tp->pdev));
9713 }
9714
9715 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9716 {
9717         struct tg3 *tp = netdev_priv(dev);
9718
9719         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9720             device_can_wakeup(&tp->pdev->dev))
9721                 wol->supported = WAKE_MAGIC;
9722         else
9723                 wol->supported = 0;
9724         wol->wolopts = 0;
9725         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9726             device_can_wakeup(&tp->pdev->dev))
9727                 wol->wolopts = WAKE_MAGIC;
9728         memset(&wol->sopass, 0, sizeof(wol->sopass));
9729 }
9730
9731 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9732 {
9733         struct tg3 *tp = netdev_priv(dev);
9734         struct device *dp = &tp->pdev->dev;
9735
9736         if (wol->wolopts & ~WAKE_MAGIC)
9737                 return -EINVAL;
9738         if ((wol->wolopts & WAKE_MAGIC) &&
9739             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9740                 return -EINVAL;
9741
9742         spin_lock_bh(&tp->lock);
9743         if (wol->wolopts & WAKE_MAGIC) {
9744                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9745                 device_set_wakeup_enable(dp, true);
9746         } else {
9747                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9748                 device_set_wakeup_enable(dp, false);
9749         }
9750         spin_unlock_bh(&tp->lock);
9751
9752         return 0;
9753 }
9754
9755 static u32 tg3_get_msglevel(struct net_device *dev)
9756 {
9757         struct tg3 *tp = netdev_priv(dev);
9758         return tp->msg_enable;
9759 }
9760
9761 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9762 {
9763         struct tg3 *tp = netdev_priv(dev);
9764         tp->msg_enable = value;
9765 }
9766
9767 static int tg3_set_tso(struct net_device *dev, u32 value)
9768 {
9769         struct tg3 *tp = netdev_priv(dev);
9770
9771         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9772                 if (value)
9773                         return -EINVAL;
9774                 return 0;
9775         }
9776         if ((dev->features & NETIF_F_IPV6_CSUM) &&
9777             ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9778              (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9779                 if (value) {
9780                         dev->features |= NETIF_F_TSO6;
9781                         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9782                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9783                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9784                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9785                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9786                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9787                                 dev->features |= NETIF_F_TSO_ECN;
9788                 } else
9789                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9790         }
9791         return ethtool_op_set_tso(dev, value);
9792 }
9793
9794 static int tg3_nway_reset(struct net_device *dev)
9795 {
9796         struct tg3 *tp = netdev_priv(dev);
9797         int r;
9798
9799         if (!netif_running(dev))
9800                 return -EAGAIN;
9801
9802         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9803                 return -EINVAL;
9804
9805         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9806                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9807                         return -EAGAIN;
9808                 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9809         } else {
9810                 u32 bmcr;
9811
9812                 spin_lock_bh(&tp->lock);
9813                 r = -EINVAL;
9814                 tg3_readphy(tp, MII_BMCR, &bmcr);
9815                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9816                     ((bmcr & BMCR_ANENABLE) ||
9817                      (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9818                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9819                                                    BMCR_ANENABLE);
9820                         r = 0;
9821                 }
9822                 spin_unlock_bh(&tp->lock);
9823         }
9824
9825         return r;
9826 }
9827
9828 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9829 {
9830         struct tg3 *tp = netdev_priv(dev);
9831
9832         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9833         ering->rx_mini_max_pending = 0;
9834         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9835                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9836         else
9837                 ering->rx_jumbo_max_pending = 0;
9838
9839         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9840
9841         ering->rx_pending = tp->rx_pending;
9842         ering->rx_mini_pending = 0;
9843         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9844                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9845         else
9846                 ering->rx_jumbo_pending = 0;
9847
9848         ering->tx_pending = tp->napi[0].tx_pending;
9849 }
9850
9851 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9852 {
9853         struct tg3 *tp = netdev_priv(dev);
9854         int i, irq_sync = 0, err = 0;
9855
9856         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9857             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9858             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9859             (ering->tx_pending <= MAX_SKB_FRAGS) ||
9860             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9861              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9862                 return -EINVAL;
9863
9864         if (netif_running(dev)) {
9865                 tg3_phy_stop(tp);
9866                 tg3_netif_stop(tp);
9867                 irq_sync = 1;
9868         }
9869
9870         tg3_full_lock(tp, irq_sync);
9871
9872         tp->rx_pending = ering->rx_pending;
9873
9874         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9875             tp->rx_pending > 63)
9876                 tp->rx_pending = 63;
9877         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9878
9879         for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9880                 tp->napi[i].tx_pending = ering->tx_pending;
9881
9882         if (netif_running(dev)) {
9883                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9884                 err = tg3_restart_hw(tp, 1);
9885                 if (!err)
9886                         tg3_netif_start(tp);
9887         }
9888
9889         tg3_full_unlock(tp);
9890
9891         if (irq_sync && !err)
9892                 tg3_phy_start(tp);
9893
9894         return err;
9895 }
9896
9897 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9898 {
9899         struct tg3 *tp = netdev_priv(dev);
9900
9901         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9902
9903         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9904                 epause->rx_pause = 1;
9905         else
9906                 epause->rx_pause = 0;
9907
9908         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9909                 epause->tx_pause = 1;
9910         else
9911                 epause->tx_pause = 0;
9912 }
9913
9914 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9915 {
9916         struct tg3 *tp = netdev_priv(dev);
9917         int err = 0;
9918
9919         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9920                 u32 newadv;
9921                 struct phy_device *phydev;
9922
9923                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9924
9925                 if (!(phydev->supported & SUPPORTED_Pause) ||
9926                     (!(phydev->supported & SUPPORTED_Asym_Pause) &&
9927                      ((epause->rx_pause && !epause->tx_pause) ||
9928                       (!epause->rx_pause && epause->tx_pause))))
9929                         return -EINVAL;
9930
9931                 tp->link_config.flowctrl = 0;
9932                 if (epause->rx_pause) {
9933                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
9934
9935                         if (epause->tx_pause) {
9936                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9937                                 newadv = ADVERTISED_Pause;
9938                         } else
9939                                 newadv = ADVERTISED_Pause |
9940                                          ADVERTISED_Asym_Pause;
9941                 } else if (epause->tx_pause) {
9942                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
9943                         newadv = ADVERTISED_Asym_Pause;
9944                 } else
9945                         newadv = 0;
9946
9947                 if (epause->autoneg)
9948                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9949                 else
9950                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9951
9952                 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9953                         u32 oldadv = phydev->advertising &
9954                                      (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
9955                         if (oldadv != newadv) {
9956                                 phydev->advertising &=
9957                                         ~(ADVERTISED_Pause |
9958                                           ADVERTISED_Asym_Pause);
9959                                 phydev->advertising |= newadv;
9960                                 if (phydev->autoneg) {
9961                                         /*
9962                                          * Always renegotiate the link to
9963                                          * inform our link partner of our
9964                                          * flow control settings, even if the
9965                                          * flow control is forced.  Let
9966                                          * tg3_adjust_link() do the final
9967                                          * flow control setup.
9968                                          */
9969                                         return phy_start_aneg(phydev);
9970                                 }
9971                         }
9972
9973                         if (!epause->autoneg)
9974                                 tg3_setup_flow_control(tp, 0, 0);
9975                 } else {
9976                         tp->link_config.orig_advertising &=
9977                                         ~(ADVERTISED_Pause |
9978                                           ADVERTISED_Asym_Pause);
9979                         tp->link_config.orig_advertising |= newadv;
9980                 }
9981         } else {
9982                 int irq_sync = 0;
9983
9984                 if (netif_running(dev)) {
9985                         tg3_netif_stop(tp);
9986                         irq_sync = 1;
9987                 }
9988
9989                 tg3_full_lock(tp, irq_sync);
9990
9991                 if (epause->autoneg)
9992                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9993                 else
9994                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9995                 if (epause->rx_pause)
9996                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
9997                 else
9998                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9999                 if (epause->tx_pause)
10000                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
10001                 else
10002                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10003
10004                 if (netif_running(dev)) {
10005                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10006                         err = tg3_restart_hw(tp, 1);
10007                         if (!err)
10008                                 tg3_netif_start(tp);
10009                 }
10010
10011                 tg3_full_unlock(tp);
10012         }
10013
10014         return err;
10015 }
10016
10017 static u32 tg3_get_rx_csum(struct net_device *dev)
10018 {
10019         struct tg3 *tp = netdev_priv(dev);
10020         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10021 }
10022
10023 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10024 {
10025         struct tg3 *tp = netdev_priv(dev);
10026
10027         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10028                 if (data != 0)
10029                         return -EINVAL;
10030                 return 0;
10031         }
10032
10033         spin_lock_bh(&tp->lock);
10034         if (data)
10035                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10036         else
10037                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10038         spin_unlock_bh(&tp->lock);
10039
10040         return 0;
10041 }
10042
10043 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10044 {
10045         struct tg3 *tp = netdev_priv(dev);
10046
10047         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10048                 if (data != 0)
10049                         return -EINVAL;
10050                 return 0;
10051         }
10052
10053         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10054                 ethtool_op_set_tx_ipv6_csum(dev, data);
10055         else
10056                 ethtool_op_set_tx_csum(dev, data);
10057
10058         return 0;
10059 }
10060
10061 static int tg3_get_sset_count(struct net_device *dev, int sset)
10062 {
10063         switch (sset) {
10064         case ETH_SS_TEST:
10065                 return TG3_NUM_TEST;
10066         case ETH_SS_STATS:
10067                 return TG3_NUM_STATS;
10068         default:
10069                 return -EOPNOTSUPP;
10070         }
10071 }
10072
10073 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
10074 {
10075         switch (stringset) {
10076         case ETH_SS_STATS:
10077                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10078                 break;
10079         case ETH_SS_TEST:
10080                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10081                 break;
10082         default:
10083                 WARN_ON(1);     /* we need a WARN() */
10084                 break;
10085         }
10086 }
10087
10088 static int tg3_phys_id(struct net_device *dev, u32 data)
10089 {
10090         struct tg3 *tp = netdev_priv(dev);
10091         int i;
10092
10093         if (!netif_running(tp->dev))
10094                 return -EAGAIN;
10095
10096         if (data == 0)
10097                 data = UINT_MAX / 2;
10098
10099         for (i = 0; i < (data * 2); i++) {
10100                 if ((i % 2) == 0)
10101                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10102                                            LED_CTRL_1000MBPS_ON |
10103                                            LED_CTRL_100MBPS_ON |
10104                                            LED_CTRL_10MBPS_ON |
10105                                            LED_CTRL_TRAFFIC_OVERRIDE |
10106                                            LED_CTRL_TRAFFIC_BLINK |
10107                                            LED_CTRL_TRAFFIC_LED);
10108
10109                 else
10110                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10111                                            LED_CTRL_TRAFFIC_OVERRIDE);
10112
10113                 if (msleep_interruptible(500))
10114                         break;
10115         }
10116         tw32(MAC_LED_CTRL, tp->led_ctrl);
10117         return 0;
10118 }
10119
10120 static void tg3_get_ethtool_stats(struct net_device *dev,
10121                                    struct ethtool_stats *estats, u64 *tmp_stats)
10122 {
10123         struct tg3 *tp = netdev_priv(dev);
10124         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10125 }
10126
10127 #define NVRAM_TEST_SIZE 0x100
10128 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
10129 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
10130 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
10131 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10132 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10133
10134 static int tg3_test_nvram(struct tg3 *tp)
10135 {
10136         u32 csum, magic;
10137         __be32 *buf;
10138         int i, j, k, err = 0, size;
10139
10140         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10141                 return 0;
10142
10143         if (tg3_nvram_read(tp, 0, &magic) != 0)
10144                 return -EIO;
10145
10146         if (magic == TG3_EEPROM_MAGIC)
10147                 size = NVRAM_TEST_SIZE;
10148         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10149                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10150                     TG3_EEPROM_SB_FORMAT_1) {
10151                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10152                         case TG3_EEPROM_SB_REVISION_0:
10153                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10154                                 break;
10155                         case TG3_EEPROM_SB_REVISION_2:
10156                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10157                                 break;
10158                         case TG3_EEPROM_SB_REVISION_3:
10159                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10160                                 break;
10161                         default:
10162                                 return 0;
10163                         }
10164                 } else
10165                         return 0;
10166         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10167                 size = NVRAM_SELFBOOT_HW_SIZE;
10168         else
10169                 return -EIO;
10170
10171         buf = kmalloc(size, GFP_KERNEL);
10172         if (buf == NULL)
10173                 return -ENOMEM;
10174
10175         err = -EIO;
10176         for (i = 0, j = 0; i < size; i += 4, j++) {
10177                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10178                 if (err)
10179                         break;
10180         }
10181         if (i < size)
10182                 goto out;
10183
10184         /* Selfboot format */
10185         magic = be32_to_cpu(buf[0]);
10186         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10187             TG3_EEPROM_MAGIC_FW) {
10188                 u8 *buf8 = (u8 *) buf, csum8 = 0;
10189
10190                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10191                     TG3_EEPROM_SB_REVISION_2) {
10192                         /* For rev 2, the csum doesn't include the MBA. */
10193                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10194                                 csum8 += buf8[i];
10195                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10196                                 csum8 += buf8[i];
10197                 } else {
10198                         for (i = 0; i < size; i++)
10199                                 csum8 += buf8[i];
10200                 }
10201
10202                 if (csum8 == 0) {
10203                         err = 0;
10204                         goto out;
10205                 }
10206
10207                 err = -EIO;
10208                 goto out;
10209         }
10210
10211         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10212             TG3_EEPROM_MAGIC_HW) {
10213                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10214                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10215                 u8 *buf8 = (u8 *) buf;
10216
10217                 /* Separate the parity bits and the data bytes.  */
10218                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10219                         if ((i == 0) || (i == 8)) {
10220                                 int l;
10221                                 u8 msk;
10222
10223                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10224                                         parity[k++] = buf8[i] & msk;
10225                                 i++;
10226                         } else if (i == 16) {
10227                                 int l;
10228                                 u8 msk;
10229
10230                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10231                                         parity[k++] = buf8[i] & msk;
10232                                 i++;
10233
10234                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10235                                         parity[k++] = buf8[i] & msk;
10236                                 i++;
10237                         }
10238                         data[j++] = buf8[i];
10239                 }
10240
10241                 err = -EIO;
10242                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10243                         u8 hw8 = hweight8(data[i]);
10244
10245                         if ((hw8 & 0x1) && parity[i])
10246                                 goto out;
10247                         else if (!(hw8 & 0x1) && !parity[i])
10248                                 goto out;
10249                 }
10250                 err = 0;
10251                 goto out;
10252         }
10253
10254         /* Bootstrap checksum at offset 0x10 */
10255         csum = calc_crc((unsigned char *) buf, 0x10);
10256         if (csum != be32_to_cpu(buf[0x10/4]))
10257                 goto out;
10258
10259         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10260         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10261         if (csum != be32_to_cpu(buf[0xfc/4]))
10262                 goto out;
10263
10264         err = 0;
10265
10266 out:
10267         kfree(buf);
10268         return err;
10269 }
10270
10271 #define TG3_SERDES_TIMEOUT_SEC  2
10272 #define TG3_COPPER_TIMEOUT_SEC  6
10273
10274 static int tg3_test_link(struct tg3 *tp)
10275 {
10276         int i, max;
10277
10278         if (!netif_running(tp->dev))
10279                 return -ENODEV;
10280
10281         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10282                 max = TG3_SERDES_TIMEOUT_SEC;
10283         else
10284                 max = TG3_COPPER_TIMEOUT_SEC;
10285
10286         for (i = 0; i < max; i++) {
10287                 if (netif_carrier_ok(tp->dev))
10288                         return 0;
10289
10290                 if (msleep_interruptible(1000))
10291                         break;
10292         }
10293
10294         return -EIO;
10295 }
10296
10297 /* Only test the commonly used registers */
10298 static int tg3_test_registers(struct tg3 *tp)
10299 {
10300         int i, is_5705, is_5750;
10301         u32 offset, read_mask, write_mask, val, save_val, read_val;
10302         static struct {
10303                 u16 offset;
10304                 u16 flags;
10305 #define TG3_FL_5705     0x1
10306 #define TG3_FL_NOT_5705 0x2
10307 #define TG3_FL_NOT_5788 0x4
10308 #define TG3_FL_NOT_5750 0x8
10309                 u32 read_mask;
10310                 u32 write_mask;
10311         } reg_tbl[] = {
10312                 /* MAC Control Registers */
10313                 { MAC_MODE, TG3_FL_NOT_5705,
10314                         0x00000000, 0x00ef6f8c },
10315                 { MAC_MODE, TG3_FL_5705,
10316                         0x00000000, 0x01ef6b8c },
10317                 { MAC_STATUS, TG3_FL_NOT_5705,
10318                         0x03800107, 0x00000000 },
10319                 { MAC_STATUS, TG3_FL_5705,
10320                         0x03800100, 0x00000000 },
10321                 { MAC_ADDR_0_HIGH, 0x0000,
10322                         0x00000000, 0x0000ffff },
10323                 { MAC_ADDR_0_LOW, 0x0000,
10324                         0x00000000, 0xffffffff },
10325                 { MAC_RX_MTU_SIZE, 0x0000,
10326                         0x00000000, 0x0000ffff },
10327                 { MAC_TX_MODE, 0x0000,
10328                         0x00000000, 0x00000070 },
10329                 { MAC_TX_LENGTHS, 0x0000,
10330                         0x00000000, 0x00003fff },
10331                 { MAC_RX_MODE, TG3_FL_NOT_5705,
10332                         0x00000000, 0x000007fc },
10333                 { MAC_RX_MODE, TG3_FL_5705,
10334                         0x00000000, 0x000007dc },
10335                 { MAC_HASH_REG_0, 0x0000,
10336                         0x00000000, 0xffffffff },
10337                 { MAC_HASH_REG_1, 0x0000,
10338                         0x00000000, 0xffffffff },
10339                 { MAC_HASH_REG_2, 0x0000,
10340                         0x00000000, 0xffffffff },
10341                 { MAC_HASH_REG_3, 0x0000,
10342                         0x00000000, 0xffffffff },
10343
10344                 /* Receive Data and Receive BD Initiator Control Registers. */
10345                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10346                         0x00000000, 0xffffffff },
10347                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10348                         0x00000000, 0xffffffff },
10349                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10350                         0x00000000, 0x00000003 },
10351                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10352                         0x00000000, 0xffffffff },
10353                 { RCVDBDI_STD_BD+0, 0x0000,
10354                         0x00000000, 0xffffffff },
10355                 { RCVDBDI_STD_BD+4, 0x0000,
10356                         0x00000000, 0xffffffff },
10357                 { RCVDBDI_STD_BD+8, 0x0000,
10358                         0x00000000, 0xffff0002 },
10359                 { RCVDBDI_STD_BD+0xc, 0x0000,
10360                         0x00000000, 0xffffffff },
10361
10362                 /* Receive BD Initiator Control Registers. */
10363                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10364                         0x00000000, 0xffffffff },
10365                 { RCVBDI_STD_THRESH, TG3_FL_5705,
10366                         0x00000000, 0x000003ff },
10367                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10368                         0x00000000, 0xffffffff },
10369
10370                 /* Host Coalescing Control Registers. */
10371                 { HOSTCC_MODE, TG3_FL_NOT_5705,
10372                         0x00000000, 0x00000004 },
10373                 { HOSTCC_MODE, TG3_FL_5705,
10374                         0x00000000, 0x000000f6 },
10375                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10376                         0x00000000, 0xffffffff },
10377                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10378                         0x00000000, 0x000003ff },
10379                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10380                         0x00000000, 0xffffffff },
10381                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10382                         0x00000000, 0x000003ff },
10383                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10384                         0x00000000, 0xffffffff },
10385                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10386                         0x00000000, 0x000000ff },
10387                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10388                         0x00000000, 0xffffffff },
10389                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10390                         0x00000000, 0x000000ff },
10391                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10392                         0x00000000, 0xffffffff },
10393                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10394                         0x00000000, 0xffffffff },
10395                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10396                         0x00000000, 0xffffffff },
10397                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10398                         0x00000000, 0x000000ff },
10399                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10400                         0x00000000, 0xffffffff },
10401                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10402                         0x00000000, 0x000000ff },
10403                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10404                         0x00000000, 0xffffffff },
10405                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10406                         0x00000000, 0xffffffff },
10407                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10408                         0x00000000, 0xffffffff },
10409                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10410                         0x00000000, 0xffffffff },
10411                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10412                         0x00000000, 0xffffffff },
10413                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10414                         0xffffffff, 0x00000000 },
10415                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10416                         0xffffffff, 0x00000000 },
10417
10418                 /* Buffer Manager Control Registers. */
10419                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10420                         0x00000000, 0x007fff80 },
10421                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10422                         0x00000000, 0x007fffff },
10423                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10424                         0x00000000, 0x0000003f },
10425                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10426                         0x00000000, 0x000001ff },
10427                 { BUFMGR_MB_HIGH_WATER, 0x0000,
10428                         0x00000000, 0x000001ff },
10429                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10430                         0xffffffff, 0x00000000 },
10431                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10432                         0xffffffff, 0x00000000 },
10433
10434                 /* Mailbox Registers */
10435                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10436                         0x00000000, 0x000001ff },
10437                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10438                         0x00000000, 0x000001ff },
10439                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10440                         0x00000000, 0x000007ff },
10441                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10442                         0x00000000, 0x000001ff },
10443
10444                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10445         };
10446
10447         is_5705 = is_5750 = 0;
10448         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10449                 is_5705 = 1;
10450                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10451                         is_5750 = 1;
10452         }
10453
10454         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10455                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10456                         continue;
10457
10458                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10459                         continue;
10460
10461                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10462                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
10463                         continue;
10464
10465                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10466                         continue;
10467
10468                 offset = (u32) reg_tbl[i].offset;
10469                 read_mask = reg_tbl[i].read_mask;
10470                 write_mask = reg_tbl[i].write_mask;
10471
10472                 /* Save the original register content */
10473                 save_val = tr32(offset);
10474
10475                 /* Determine the read-only value. */
10476                 read_val = save_val & read_mask;
10477
10478                 /* Write zero to the register, then make sure the read-only bits
10479                  * are not changed and the read/write bits are all zeros.
10480                  */
10481                 tw32(offset, 0);
10482
10483                 val = tr32(offset);
10484
10485                 /* Test the read-only and read/write bits. */
10486                 if (((val & read_mask) != read_val) || (val & write_mask))
10487                         goto out;
10488
10489                 /* Write ones to all the bits defined by RdMask and WrMask, then
10490                  * make sure the read-only bits are not changed and the
10491                  * read/write bits are all ones.
10492                  */
10493                 tw32(offset, read_mask | write_mask);
10494
10495                 val = tr32(offset);
10496
10497                 /* Test the read-only bits. */
10498                 if ((val & read_mask) != read_val)
10499                         goto out;
10500
10501                 /* Test the read/write bits. */
10502                 if ((val & write_mask) != write_mask)
10503                         goto out;
10504
10505                 tw32(offset, save_val);
10506         }
10507
10508         return 0;
10509
10510 out:
10511         if (netif_msg_hw(tp))
10512                 netdev_err(tp->dev,
10513                            "Register test failed at offset %x\n", offset);
10514         tw32(offset, save_val);
10515         return -EIO;
10516 }
10517
10518 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10519 {
10520         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10521         int i;
10522         u32 j;
10523
10524         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10525                 for (j = 0; j < len; j += 4) {
10526                         u32 val;
10527
10528                         tg3_write_mem(tp, offset + j, test_pattern[i]);
10529                         tg3_read_mem(tp, offset + j, &val);
10530                         if (val != test_pattern[i])
10531                                 return -EIO;
10532                 }
10533         }
10534         return 0;
10535 }
10536
10537 static int tg3_test_memory(struct tg3 *tp)
10538 {
10539         static struct mem_entry {
10540                 u32 offset;
10541                 u32 len;
10542         } mem_tbl_570x[] = {
10543                 { 0x00000000, 0x00b50},
10544                 { 0x00002000, 0x1c000},
10545                 { 0xffffffff, 0x00000}
10546         }, mem_tbl_5705[] = {
10547                 { 0x00000100, 0x0000c},
10548                 { 0x00000200, 0x00008},
10549                 { 0x00004000, 0x00800},
10550                 { 0x00006000, 0x01000},
10551                 { 0x00008000, 0x02000},
10552                 { 0x00010000, 0x0e000},
10553                 { 0xffffffff, 0x00000}
10554         }, mem_tbl_5755[] = {
10555                 { 0x00000200, 0x00008},
10556                 { 0x00004000, 0x00800},
10557                 { 0x00006000, 0x00800},
10558                 { 0x00008000, 0x02000},
10559                 { 0x00010000, 0x0c000},
10560                 { 0xffffffff, 0x00000}
10561         }, mem_tbl_5906[] = {
10562                 { 0x00000200, 0x00008},
10563                 { 0x00004000, 0x00400},
10564                 { 0x00006000, 0x00400},
10565                 { 0x00008000, 0x01000},
10566                 { 0x00010000, 0x01000},
10567                 { 0xffffffff, 0x00000}
10568         }, mem_tbl_5717[] = {
10569                 { 0x00000200, 0x00008},
10570                 { 0x00010000, 0x0a000},
10571                 { 0x00020000, 0x13c00},
10572                 { 0xffffffff, 0x00000}
10573         }, mem_tbl_57765[] = {
10574                 { 0x00000200, 0x00008},
10575                 { 0x00004000, 0x00800},
10576                 { 0x00006000, 0x09800},
10577                 { 0x00010000, 0x0a000},
10578                 { 0xffffffff, 0x00000}
10579         };
10580         struct mem_entry *mem_tbl;
10581         int err = 0;
10582         int i;
10583
10584         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
10585             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
10586                 mem_tbl = mem_tbl_5717;
10587         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10588                 mem_tbl = mem_tbl_57765;
10589         else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10590                 mem_tbl = mem_tbl_5755;
10591         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10592                 mem_tbl = mem_tbl_5906;
10593         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10594                 mem_tbl = mem_tbl_5705;
10595         else
10596                 mem_tbl = mem_tbl_570x;
10597
10598         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10599                 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
10600                 if (err)
10601                         break;
10602         }
10603
10604         return err;
10605 }
10606
10607 #define TG3_MAC_LOOPBACK        0
10608 #define TG3_PHY_LOOPBACK        1
10609
10610 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10611 {
10612         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10613         u32 desc_idx, coal_now;
10614         struct sk_buff *skb, *rx_skb;
10615         u8 *tx_data;
10616         dma_addr_t map;
10617         int num_pkts, tx_len, rx_len, i, err;
10618         struct tg3_rx_buffer_desc *desc;
10619         struct tg3_napi *tnapi, *rnapi;
10620         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
10621
10622         tnapi = &tp->napi[0];
10623         rnapi = &tp->napi[0];
10624         if (tp->irq_cnt > 1) {
10625                 rnapi = &tp->napi[1];
10626                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
10627                         tnapi = &tp->napi[1];
10628         }
10629         coal_now = tnapi->coal_now | rnapi->coal_now;
10630
10631         if (loopback_mode == TG3_MAC_LOOPBACK) {
10632                 /* HW errata - mac loopback fails in some cases on 5780.
10633                  * Normal traffic and PHY loopback are not affected by
10634                  * errata.
10635                  */
10636                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10637                         return 0;
10638
10639                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10640                            MAC_MODE_PORT_INT_LPBACK;
10641                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10642                         mac_mode |= MAC_MODE_LINK_POLARITY;
10643                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10644                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10645                 else
10646                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10647                 tw32(MAC_MODE, mac_mode);
10648         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10649                 u32 val;
10650
10651                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10652                         tg3_phy_fet_toggle_apd(tp, false);
10653                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10654                 } else
10655                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10656
10657                 tg3_phy_toggle_automdix(tp, 0);
10658
10659                 tg3_writephy(tp, MII_BMCR, val);
10660                 udelay(40);
10661
10662                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10663                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10664                         tg3_writephy(tp, MII_TG3_FET_PTEST,
10665                                      MII_TG3_FET_PTEST_FRC_TX_LINK |
10666                                      MII_TG3_FET_PTEST_FRC_TX_LOCK);
10667                         /* The write needs to be flushed for the AC131 */
10668                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10669                                 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
10670                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10671                 } else
10672                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10673
10674                 /* reset to prevent losing 1st rx packet intermittently */
10675                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10676                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10677                         udelay(10);
10678                         tw32_f(MAC_RX_MODE, tp->rx_mode);
10679                 }
10680                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10681                         u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
10682                         if (masked_phy_id == TG3_PHY_ID_BCM5401)
10683                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10684                         else if (masked_phy_id == TG3_PHY_ID_BCM5411)
10685                                 mac_mode |= MAC_MODE_LINK_POLARITY;
10686                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
10687                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10688                 }
10689                 tw32(MAC_MODE, mac_mode);
10690         } else {
10691                 return -EINVAL;
10692         }
10693
10694         err = -EIO;
10695
10696         tx_len = 1514;
10697         skb = netdev_alloc_skb(tp->dev, tx_len);
10698         if (!skb)
10699                 return -ENOMEM;
10700
10701         tx_data = skb_put(skb, tx_len);
10702         memcpy(tx_data, tp->dev->dev_addr, 6);
10703         memset(tx_data + 6, 0x0, 8);
10704
10705         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10706
10707         for (i = 14; i < tx_len; i++)
10708                 tx_data[i] = (u8) (i & 0xff);
10709
10710         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10711         if (pci_dma_mapping_error(tp->pdev, map)) {
10712                 dev_kfree_skb(skb);
10713                 return -EIO;
10714         }
10715
10716         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10717                rnapi->coal_now);
10718
10719         udelay(10);
10720
10721         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10722
10723         num_pkts = 0;
10724
10725         tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10726
10727         tnapi->tx_prod++;
10728         num_pkts++;
10729
10730         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10731         tr32_mailbox(tnapi->prodmbox);
10732
10733         udelay(10);
10734
10735         /* 350 usec to allow enough time on some 10/100 Mbps devices.  */
10736         for (i = 0; i < 35; i++) {
10737                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10738                        coal_now);
10739
10740                 udelay(10);
10741
10742                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10743                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10744                 if ((tx_idx == tnapi->tx_prod) &&
10745                     (rx_idx == (rx_start_idx + num_pkts)))
10746                         break;
10747         }
10748
10749         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10750         dev_kfree_skb(skb);
10751
10752         if (tx_idx != tnapi->tx_prod)
10753                 goto out;
10754
10755         if (rx_idx != rx_start_idx + num_pkts)
10756                 goto out;
10757
10758         desc = &rnapi->rx_rcb[rx_start_idx];
10759         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10760         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10761         if (opaque_key != RXD_OPAQUE_RING_STD)
10762                 goto out;
10763
10764         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10765             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10766                 goto out;
10767
10768         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10769         if (rx_len != tx_len)
10770                 goto out;
10771
10772         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10773
10774         map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10775         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10776
10777         for (i = 14; i < tx_len; i++) {
10778                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10779                         goto out;
10780         }
10781         err = 0;
10782
10783         /* tg3_free_rings will unmap and free the rx_skb */
10784 out:
10785         return err;
10786 }
10787
10788 #define TG3_MAC_LOOPBACK_FAILED         1
10789 #define TG3_PHY_LOOPBACK_FAILED         2
10790 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
10791                                          TG3_PHY_LOOPBACK_FAILED)
10792
10793 static int tg3_test_loopback(struct tg3 *tp)
10794 {
10795         int err = 0;
10796         u32 cpmuctrl = 0;
10797
10798         if (!netif_running(tp->dev))
10799                 return TG3_LOOPBACK_FAILED;
10800
10801         err = tg3_reset_hw(tp, 1);
10802         if (err)
10803                 return TG3_LOOPBACK_FAILED;
10804
10805         /* Turn off gphy autopowerdown. */
10806         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10807                 tg3_phy_toggle_apd(tp, false);
10808
10809         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10810                 int i;
10811                 u32 status;
10812
10813                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10814
10815                 /* Wait for up to 40 microseconds to acquire lock. */
10816                 for (i = 0; i < 4; i++) {
10817                         status = tr32(TG3_CPMU_MUTEX_GNT);
10818                         if (status == CPMU_MUTEX_GNT_DRIVER)
10819                                 break;
10820                         udelay(10);
10821                 }
10822
10823                 if (status != CPMU_MUTEX_GNT_DRIVER)
10824                         return TG3_LOOPBACK_FAILED;
10825
10826                 /* Turn off link-based power management. */
10827                 cpmuctrl = tr32(TG3_CPMU_CTRL);
10828                 tw32(TG3_CPMU_CTRL,
10829                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10830                                   CPMU_CTRL_LINK_AWARE_MODE));
10831         }
10832
10833         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10834                 err |= TG3_MAC_LOOPBACK_FAILED;
10835
10836         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10837                 tw32(TG3_CPMU_CTRL, cpmuctrl);
10838
10839                 /* Release the mutex */
10840                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10841         }
10842
10843         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10844             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10845                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10846                         err |= TG3_PHY_LOOPBACK_FAILED;
10847         }
10848
10849         /* Re-enable gphy autopowerdown. */
10850         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10851                 tg3_phy_toggle_apd(tp, true);
10852
10853         return err;
10854 }
10855
10856 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10857                           u64 *data)
10858 {
10859         struct tg3 *tp = netdev_priv(dev);
10860
10861         if (tp->link_config.phy_is_low_power)
10862                 tg3_set_power_state(tp, PCI_D0);
10863
10864         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10865
10866         if (tg3_test_nvram(tp) != 0) {
10867                 etest->flags |= ETH_TEST_FL_FAILED;
10868                 data[0] = 1;
10869         }
10870         if (tg3_test_link(tp) != 0) {
10871                 etest->flags |= ETH_TEST_FL_FAILED;
10872                 data[1] = 1;
10873         }
10874         if (etest->flags & ETH_TEST_FL_OFFLINE) {
10875                 int err, err2 = 0, irq_sync = 0;
10876
10877                 if (netif_running(dev)) {
10878                         tg3_phy_stop(tp);
10879                         tg3_netif_stop(tp);
10880                         irq_sync = 1;
10881                 }
10882
10883                 tg3_full_lock(tp, irq_sync);
10884
10885                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10886                 err = tg3_nvram_lock(tp);
10887                 tg3_halt_cpu(tp, RX_CPU_BASE);
10888                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10889                         tg3_halt_cpu(tp, TX_CPU_BASE);
10890                 if (!err)
10891                         tg3_nvram_unlock(tp);
10892
10893                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10894                         tg3_phy_reset(tp);
10895
10896                 if (tg3_test_registers(tp) != 0) {
10897                         etest->flags |= ETH_TEST_FL_FAILED;
10898                         data[2] = 1;
10899                 }
10900                 if (tg3_test_memory(tp) != 0) {
10901                         etest->flags |= ETH_TEST_FL_FAILED;
10902                         data[3] = 1;
10903                 }
10904                 if ((data[4] = tg3_test_loopback(tp)) != 0)
10905                         etest->flags |= ETH_TEST_FL_FAILED;
10906
10907                 tg3_full_unlock(tp);
10908
10909                 if (tg3_test_interrupt(tp) != 0) {
10910                         etest->flags |= ETH_TEST_FL_FAILED;
10911                         data[5] = 1;
10912                 }
10913
10914                 tg3_full_lock(tp, 0);
10915
10916                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10917                 if (netif_running(dev)) {
10918                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10919                         err2 = tg3_restart_hw(tp, 1);
10920                         if (!err2)
10921                                 tg3_netif_start(tp);
10922                 }
10923
10924                 tg3_full_unlock(tp);
10925
10926                 if (irq_sync && !err2)
10927                         tg3_phy_start(tp);
10928         }
10929         if (tp->link_config.phy_is_low_power)
10930                 tg3_set_power_state(tp, PCI_D3hot);
10931
10932 }
10933
10934 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10935 {
10936         struct mii_ioctl_data *data = if_mii(ifr);
10937         struct tg3 *tp = netdev_priv(dev);
10938         int err;
10939
10940         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10941                 struct phy_device *phydev;
10942                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10943                         return -EAGAIN;
10944                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10945                 return phy_mii_ioctl(phydev, ifr, cmd);
10946         }
10947
10948         switch (cmd) {
10949         case SIOCGMIIPHY:
10950                 data->phy_id = tp->phy_addr;
10951
10952                 /* fallthru */
10953         case SIOCGMIIREG: {
10954                 u32 mii_regval;
10955
10956                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10957                         break;                  /* We have no PHY */
10958
10959                 if (tp->link_config.phy_is_low_power)
10960                         return -EAGAIN;
10961
10962                 spin_lock_bh(&tp->lock);
10963                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10964                 spin_unlock_bh(&tp->lock);
10965
10966                 data->val_out = mii_regval;
10967
10968                 return err;
10969         }
10970
10971         case SIOCSMIIREG:
10972                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10973                         break;                  /* We have no PHY */
10974
10975                 if (tp->link_config.phy_is_low_power)
10976                         return -EAGAIN;
10977
10978                 spin_lock_bh(&tp->lock);
10979                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10980                 spin_unlock_bh(&tp->lock);
10981
10982                 return err;
10983
10984         default:
10985                 /* do nothing */
10986                 break;
10987         }
10988         return -EOPNOTSUPP;
10989 }
10990
10991 #if TG3_VLAN_TAG_USED
10992 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10993 {
10994         struct tg3 *tp = netdev_priv(dev);
10995
10996         if (!netif_running(dev)) {
10997                 tp->vlgrp = grp;
10998                 return;
10999         }
11000
11001         tg3_netif_stop(tp);
11002
11003         tg3_full_lock(tp, 0);
11004
11005         tp->vlgrp = grp;
11006
11007         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11008         __tg3_set_rx_mode(dev);
11009
11010         tg3_netif_start(tp);
11011
11012         tg3_full_unlock(tp);
11013 }
11014 #endif
11015
11016 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11017 {
11018         struct tg3 *tp = netdev_priv(dev);
11019
11020         memcpy(ec, &tp->coal, sizeof(*ec));
11021         return 0;
11022 }
11023
11024 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11025 {
11026         struct tg3 *tp = netdev_priv(dev);
11027         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11028         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11029
11030         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11031                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11032                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11033                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11034                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11035         }
11036
11037         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11038             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11039             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11040             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11041             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11042             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11043             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11044             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11045             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11046             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11047                 return -EINVAL;
11048
11049         /* No rx interrupts will be generated if both are zero */
11050         if ((ec->rx_coalesce_usecs == 0) &&
11051             (ec->rx_max_coalesced_frames == 0))
11052                 return -EINVAL;
11053
11054         /* No tx interrupts will be generated if both are zero */
11055         if ((ec->tx_coalesce_usecs == 0) &&
11056             (ec->tx_max_coalesced_frames == 0))
11057                 return -EINVAL;
11058
11059         /* Only copy relevant parameters, ignore all others. */
11060         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11061         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11062         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11063         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11064         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11065         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11066         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11067         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11068         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11069
11070         if (netif_running(dev)) {
11071                 tg3_full_lock(tp, 0);
11072                 __tg3_set_coalesce(tp, &tp->coal);
11073                 tg3_full_unlock(tp);
11074         }
11075         return 0;
11076 }
11077
11078 static const struct ethtool_ops tg3_ethtool_ops = {
11079         .get_settings           = tg3_get_settings,
11080         .set_settings           = tg3_set_settings,
11081         .get_drvinfo            = tg3_get_drvinfo,
11082         .get_regs_len           = tg3_get_regs_len,
11083         .get_regs               = tg3_get_regs,
11084         .get_wol                = tg3_get_wol,
11085         .set_wol                = tg3_set_wol,
11086         .get_msglevel           = tg3_get_msglevel,
11087         .set_msglevel           = tg3_set_msglevel,
11088         .nway_reset             = tg3_nway_reset,
11089         .get_link               = ethtool_op_get_link,
11090         .get_eeprom_len         = tg3_get_eeprom_len,
11091         .get_eeprom             = tg3_get_eeprom,
11092         .set_eeprom             = tg3_set_eeprom,
11093         .get_ringparam          = tg3_get_ringparam,
11094         .set_ringparam          = tg3_set_ringparam,
11095         .get_pauseparam         = tg3_get_pauseparam,
11096         .set_pauseparam         = tg3_set_pauseparam,
11097         .get_rx_csum            = tg3_get_rx_csum,
11098         .set_rx_csum            = tg3_set_rx_csum,
11099         .set_tx_csum            = tg3_set_tx_csum,
11100         .set_sg                 = ethtool_op_set_sg,
11101         .set_tso                = tg3_set_tso,
11102         .self_test              = tg3_self_test,
11103         .get_strings            = tg3_get_strings,
11104         .phys_id                = tg3_phys_id,
11105         .get_ethtool_stats      = tg3_get_ethtool_stats,
11106         .get_coalesce           = tg3_get_coalesce,
11107         .set_coalesce           = tg3_set_coalesce,
11108         .get_sset_count         = tg3_get_sset_count,
11109 };
11110
11111 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11112 {
11113         u32 cursize, val, magic;
11114
11115         tp->nvram_size = EEPROM_CHIP_SIZE;
11116
11117         if (tg3_nvram_read(tp, 0, &magic) != 0)
11118                 return;
11119
11120         if ((magic != TG3_EEPROM_MAGIC) &&
11121             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11122             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11123                 return;
11124
11125         /*
11126          * Size the chip by reading offsets at increasing powers of two.
11127          * When we encounter our validation signature, we know the addressing
11128          * has wrapped around, and thus have our chip size.
11129          */
11130         cursize = 0x10;
11131
11132         while (cursize < tp->nvram_size) {
11133                 if (tg3_nvram_read(tp, cursize, &val) != 0)
11134                         return;
11135
11136                 if (val == magic)
11137                         break;
11138
11139                 cursize <<= 1;
11140         }
11141
11142         tp->nvram_size = cursize;
11143 }
11144
11145 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11146 {
11147         u32 val;
11148
11149         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11150             tg3_nvram_read(tp, 0, &val) != 0)
11151                 return;
11152
11153         /* Selfboot format */
11154         if (val != TG3_EEPROM_MAGIC) {
11155                 tg3_get_eeprom_size(tp);
11156                 return;
11157         }
11158
11159         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11160                 if (val != 0) {
11161                         /* This is confusing.  We want to operate on the
11162                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
11163                          * call will read from NVRAM and byteswap the data
11164                          * according to the byteswapping settings for all
11165                          * other register accesses.  This ensures the data we
11166                          * want will always reside in the lower 16-bits.
11167                          * However, the data in NVRAM is in LE format, which
11168                          * means the data from the NVRAM read will always be
11169                          * opposite the endianness of the CPU.  The 16-bit
11170                          * byteswap then brings the data to CPU endianness.
11171                          */
11172                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11173                         return;
11174                 }
11175         }
11176         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11177 }
11178
11179 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11180 {
11181         u32 nvcfg1;
11182
11183         nvcfg1 = tr32(NVRAM_CFG1);
11184         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11185                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11186         } else {
11187                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11188                 tw32(NVRAM_CFG1, nvcfg1);
11189         }
11190
11191         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11192             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11193                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11194                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11195                         tp->nvram_jedecnum = JEDEC_ATMEL;
11196                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11197                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11198                         break;
11199                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11200                         tp->nvram_jedecnum = JEDEC_ATMEL;
11201                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11202                         break;
11203                 case FLASH_VENDOR_ATMEL_EEPROM:
11204                         tp->nvram_jedecnum = JEDEC_ATMEL;
11205                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11206                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11207                         break;
11208                 case FLASH_VENDOR_ST:
11209                         tp->nvram_jedecnum = JEDEC_ST;
11210                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11211                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11212                         break;
11213                 case FLASH_VENDOR_SAIFUN:
11214                         tp->nvram_jedecnum = JEDEC_SAIFUN;
11215                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11216                         break;
11217                 case FLASH_VENDOR_SST_SMALL:
11218                 case FLASH_VENDOR_SST_LARGE:
11219                         tp->nvram_jedecnum = JEDEC_SST;
11220                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11221                         break;
11222                 }
11223         } else {
11224                 tp->nvram_jedecnum = JEDEC_ATMEL;
11225                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11226                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11227         }
11228 }
11229
11230 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11231 {
11232         switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11233         case FLASH_5752PAGE_SIZE_256:
11234                 tp->nvram_pagesize = 256;
11235                 break;
11236         case FLASH_5752PAGE_SIZE_512:
11237                 tp->nvram_pagesize = 512;
11238                 break;
11239         case FLASH_5752PAGE_SIZE_1K:
11240                 tp->nvram_pagesize = 1024;
11241                 break;
11242         case FLASH_5752PAGE_SIZE_2K:
11243                 tp->nvram_pagesize = 2048;
11244                 break;
11245         case FLASH_5752PAGE_SIZE_4K:
11246                 tp->nvram_pagesize = 4096;
11247                 break;
11248         case FLASH_5752PAGE_SIZE_264:
11249                 tp->nvram_pagesize = 264;
11250                 break;
11251         case FLASH_5752PAGE_SIZE_528:
11252                 tp->nvram_pagesize = 528;
11253                 break;
11254         }
11255 }
11256
11257 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11258 {
11259         u32 nvcfg1;
11260
11261         nvcfg1 = tr32(NVRAM_CFG1);
11262
11263         /* NVRAM protection for TPM */
11264         if (nvcfg1 & (1 << 27))
11265                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11266
11267         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11268         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11269         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11270                 tp->nvram_jedecnum = JEDEC_ATMEL;
11271                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11272                 break;
11273         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11274                 tp->nvram_jedecnum = JEDEC_ATMEL;
11275                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11276                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11277                 break;
11278         case FLASH_5752VENDOR_ST_M45PE10:
11279         case FLASH_5752VENDOR_ST_M45PE20:
11280         case FLASH_5752VENDOR_ST_M45PE40:
11281                 tp->nvram_jedecnum = JEDEC_ST;
11282                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11283                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11284                 break;
11285         }
11286
11287         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11288                 tg3_nvram_get_pagesize(tp, nvcfg1);
11289         } else {
11290                 /* For eeprom, set pagesize to maximum eeprom size */
11291                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11292
11293                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11294                 tw32(NVRAM_CFG1, nvcfg1);
11295         }
11296 }
11297
11298 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11299 {
11300         u32 nvcfg1, protect = 0;
11301
11302         nvcfg1 = tr32(NVRAM_CFG1);
11303
11304         /* NVRAM protection for TPM */
11305         if (nvcfg1 & (1 << 27)) {
11306                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11307                 protect = 1;
11308         }
11309
11310         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11311         switch (nvcfg1) {
11312         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11313         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11314         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11315         case FLASH_5755VENDOR_ATMEL_FLASH_5:
11316                 tp->nvram_jedecnum = JEDEC_ATMEL;
11317                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11318                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11319                 tp->nvram_pagesize = 264;
11320                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11321                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11322                         tp->nvram_size = (protect ? 0x3e200 :
11323                                           TG3_NVRAM_SIZE_512KB);
11324                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11325                         tp->nvram_size = (protect ? 0x1f200 :
11326                                           TG3_NVRAM_SIZE_256KB);
11327                 else
11328                         tp->nvram_size = (protect ? 0x1f200 :
11329                                           TG3_NVRAM_SIZE_128KB);
11330                 break;
11331         case FLASH_5752VENDOR_ST_M45PE10:
11332         case FLASH_5752VENDOR_ST_M45PE20:
11333         case FLASH_5752VENDOR_ST_M45PE40:
11334                 tp->nvram_jedecnum = JEDEC_ST;
11335                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11336                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11337                 tp->nvram_pagesize = 256;
11338                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11339                         tp->nvram_size = (protect ?
11340                                           TG3_NVRAM_SIZE_64KB :
11341                                           TG3_NVRAM_SIZE_128KB);
11342                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11343                         tp->nvram_size = (protect ?
11344                                           TG3_NVRAM_SIZE_64KB :
11345                                           TG3_NVRAM_SIZE_256KB);
11346                 else
11347                         tp->nvram_size = (protect ?
11348                                           TG3_NVRAM_SIZE_128KB :
11349                                           TG3_NVRAM_SIZE_512KB);
11350                 break;
11351         }
11352 }
11353
11354 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11355 {
11356         u32 nvcfg1;
11357
11358         nvcfg1 = tr32(NVRAM_CFG1);
11359
11360         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11361         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11362         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11363         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11364         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11365                 tp->nvram_jedecnum = JEDEC_ATMEL;
11366                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11367                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11368
11369                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11370                 tw32(NVRAM_CFG1, nvcfg1);
11371                 break;
11372         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11373         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11374         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11375         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11376                 tp->nvram_jedecnum = JEDEC_ATMEL;
11377                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11378                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11379                 tp->nvram_pagesize = 264;
11380                 break;
11381         case FLASH_5752VENDOR_ST_M45PE10:
11382         case FLASH_5752VENDOR_ST_M45PE20:
11383         case FLASH_5752VENDOR_ST_M45PE40:
11384                 tp->nvram_jedecnum = JEDEC_ST;
11385                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11386                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11387                 tp->nvram_pagesize = 256;
11388                 break;
11389         }
11390 }
11391
11392 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11393 {
11394         u32 nvcfg1, protect = 0;
11395
11396         nvcfg1 = tr32(NVRAM_CFG1);
11397
11398         /* NVRAM protection for TPM */
11399         if (nvcfg1 & (1 << 27)) {
11400                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11401                 protect = 1;
11402         }
11403
11404         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11405         switch (nvcfg1) {
11406         case FLASH_5761VENDOR_ATMEL_ADB021D:
11407         case FLASH_5761VENDOR_ATMEL_ADB041D:
11408         case FLASH_5761VENDOR_ATMEL_ADB081D:
11409         case FLASH_5761VENDOR_ATMEL_ADB161D:
11410         case FLASH_5761VENDOR_ATMEL_MDB021D:
11411         case FLASH_5761VENDOR_ATMEL_MDB041D:
11412         case FLASH_5761VENDOR_ATMEL_MDB081D:
11413         case FLASH_5761VENDOR_ATMEL_MDB161D:
11414                 tp->nvram_jedecnum = JEDEC_ATMEL;
11415                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11416                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11417                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11418                 tp->nvram_pagesize = 256;
11419                 break;
11420         case FLASH_5761VENDOR_ST_A_M45PE20:
11421         case FLASH_5761VENDOR_ST_A_M45PE40:
11422         case FLASH_5761VENDOR_ST_A_M45PE80:
11423         case FLASH_5761VENDOR_ST_A_M45PE16:
11424         case FLASH_5761VENDOR_ST_M_M45PE20:
11425         case FLASH_5761VENDOR_ST_M_M45PE40:
11426         case FLASH_5761VENDOR_ST_M_M45PE80:
11427         case FLASH_5761VENDOR_ST_M_M45PE16:
11428                 tp->nvram_jedecnum = JEDEC_ST;
11429                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11430                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11431                 tp->nvram_pagesize = 256;
11432                 break;
11433         }
11434
11435         if (protect) {
11436                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11437         } else {
11438                 switch (nvcfg1) {
11439                 case FLASH_5761VENDOR_ATMEL_ADB161D:
11440                 case FLASH_5761VENDOR_ATMEL_MDB161D:
11441                 case FLASH_5761VENDOR_ST_A_M45PE16:
11442                 case FLASH_5761VENDOR_ST_M_M45PE16:
11443                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11444                         break;
11445                 case FLASH_5761VENDOR_ATMEL_ADB081D:
11446                 case FLASH_5761VENDOR_ATMEL_MDB081D:
11447                 case FLASH_5761VENDOR_ST_A_M45PE80:
11448                 case FLASH_5761VENDOR_ST_M_M45PE80:
11449                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11450                         break;
11451                 case FLASH_5761VENDOR_ATMEL_ADB041D:
11452                 case FLASH_5761VENDOR_ATMEL_MDB041D:
11453                 case FLASH_5761VENDOR_ST_A_M45PE40:
11454                 case FLASH_5761VENDOR_ST_M_M45PE40:
11455                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11456                         break;
11457                 case FLASH_5761VENDOR_ATMEL_ADB021D:
11458                 case FLASH_5761VENDOR_ATMEL_MDB021D:
11459                 case FLASH_5761VENDOR_ST_A_M45PE20:
11460                 case FLASH_5761VENDOR_ST_M_M45PE20:
11461                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11462                         break;
11463                 }
11464         }
11465 }
11466
11467 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11468 {
11469         tp->nvram_jedecnum = JEDEC_ATMEL;
11470         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11471         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11472 }
11473
11474 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11475 {
11476         u32 nvcfg1;
11477
11478         nvcfg1 = tr32(NVRAM_CFG1);
11479
11480         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11481         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11482         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11483                 tp->nvram_jedecnum = JEDEC_ATMEL;
11484                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11485                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11486
11487                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11488                 tw32(NVRAM_CFG1, nvcfg1);
11489                 return;
11490         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11491         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11492         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11493         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11494         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11495         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11496         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11497                 tp->nvram_jedecnum = JEDEC_ATMEL;
11498                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11499                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11500
11501                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11502                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11503                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11504                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11505                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11506                         break;
11507                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11508                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11509                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11510                         break;
11511                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11512                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11513                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11514                         break;
11515                 }
11516                 break;
11517         case FLASH_5752VENDOR_ST_M45PE10:
11518         case FLASH_5752VENDOR_ST_M45PE20:
11519         case FLASH_5752VENDOR_ST_M45PE40:
11520                 tp->nvram_jedecnum = JEDEC_ST;
11521                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11522                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11523
11524                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11525                 case FLASH_5752VENDOR_ST_M45PE10:
11526                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11527                         break;
11528                 case FLASH_5752VENDOR_ST_M45PE20:
11529                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11530                         break;
11531                 case FLASH_5752VENDOR_ST_M45PE40:
11532                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11533                         break;
11534                 }
11535                 break;
11536         default:
11537                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11538                 return;
11539         }
11540
11541         tg3_nvram_get_pagesize(tp, nvcfg1);
11542         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11543                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11544 }
11545
11546
11547 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11548 {
11549         u32 nvcfg1;
11550
11551         nvcfg1 = tr32(NVRAM_CFG1);
11552
11553         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11554         case FLASH_5717VENDOR_ATMEL_EEPROM:
11555         case FLASH_5717VENDOR_MICRO_EEPROM:
11556                 tp->nvram_jedecnum = JEDEC_ATMEL;
11557                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11558                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11559
11560                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11561                 tw32(NVRAM_CFG1, nvcfg1);
11562                 return;
11563         case FLASH_5717VENDOR_ATMEL_MDB011D:
11564         case FLASH_5717VENDOR_ATMEL_ADB011B:
11565         case FLASH_5717VENDOR_ATMEL_ADB011D:
11566         case FLASH_5717VENDOR_ATMEL_MDB021D:
11567         case FLASH_5717VENDOR_ATMEL_ADB021B:
11568         case FLASH_5717VENDOR_ATMEL_ADB021D:
11569         case FLASH_5717VENDOR_ATMEL_45USPT:
11570                 tp->nvram_jedecnum = JEDEC_ATMEL;
11571                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11572                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11573
11574                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11575                 case FLASH_5717VENDOR_ATMEL_MDB021D:
11576                 case FLASH_5717VENDOR_ATMEL_ADB021B:
11577                 case FLASH_5717VENDOR_ATMEL_ADB021D:
11578                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11579                         break;
11580                 default:
11581                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11582                         break;
11583                 }
11584                 break;
11585         case FLASH_5717VENDOR_ST_M_M25PE10:
11586         case FLASH_5717VENDOR_ST_A_M25PE10:
11587         case FLASH_5717VENDOR_ST_M_M45PE10:
11588         case FLASH_5717VENDOR_ST_A_M45PE10:
11589         case FLASH_5717VENDOR_ST_M_M25PE20:
11590         case FLASH_5717VENDOR_ST_A_M25PE20:
11591         case FLASH_5717VENDOR_ST_M_M45PE20:
11592         case FLASH_5717VENDOR_ST_A_M45PE20:
11593         case FLASH_5717VENDOR_ST_25USPT:
11594         case FLASH_5717VENDOR_ST_45USPT:
11595                 tp->nvram_jedecnum = JEDEC_ST;
11596                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11597                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11598
11599                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11600                 case FLASH_5717VENDOR_ST_M_M25PE20:
11601                 case FLASH_5717VENDOR_ST_A_M25PE20:
11602                 case FLASH_5717VENDOR_ST_M_M45PE20:
11603                 case FLASH_5717VENDOR_ST_A_M45PE20:
11604                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11605                         break;
11606                 default:
11607                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11608                         break;
11609                 }
11610                 break;
11611         default:
11612                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11613                 return;
11614         }
11615
11616         tg3_nvram_get_pagesize(tp, nvcfg1);
11617         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11618                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11619 }
11620
11621 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11622 static void __devinit tg3_nvram_init(struct tg3 *tp)
11623 {
11624         tw32_f(GRC_EEPROM_ADDR,
11625              (EEPROM_ADDR_FSM_RESET |
11626               (EEPROM_DEFAULT_CLOCK_PERIOD <<
11627                EEPROM_ADDR_CLKPERD_SHIFT)));
11628
11629         msleep(1);
11630
11631         /* Enable seeprom accesses. */
11632         tw32_f(GRC_LOCAL_CTRL,
11633              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11634         udelay(100);
11635
11636         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11637             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11638                 tp->tg3_flags |= TG3_FLAG_NVRAM;
11639
11640                 if (tg3_nvram_lock(tp)) {
11641                         netdev_warn(tp->dev,
11642                                     "Cannot get nvram lock, %s failed\n",
11643                                     __func__);
11644                         return;
11645                 }
11646                 tg3_enable_nvram_access(tp);
11647
11648                 tp->nvram_size = 0;
11649
11650                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11651                         tg3_get_5752_nvram_info(tp);
11652                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11653                         tg3_get_5755_nvram_info(tp);
11654                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11655                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11656                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11657                         tg3_get_5787_nvram_info(tp);
11658                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11659                         tg3_get_5761_nvram_info(tp);
11660                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11661                         tg3_get_5906_nvram_info(tp);
11662                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11663                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11664                         tg3_get_57780_nvram_info(tp);
11665                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
11666                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
11667                         tg3_get_5717_nvram_info(tp);
11668                 else
11669                         tg3_get_nvram_info(tp);
11670
11671                 if (tp->nvram_size == 0)
11672                         tg3_get_nvram_size(tp);
11673
11674                 tg3_disable_nvram_access(tp);
11675                 tg3_nvram_unlock(tp);
11676
11677         } else {
11678                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11679
11680                 tg3_get_eeprom_size(tp);
11681         }
11682 }
11683
11684 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11685                                     u32 offset, u32 len, u8 *buf)
11686 {
11687         int i, j, rc = 0;
11688         u32 val;
11689
11690         for (i = 0; i < len; i += 4) {
11691                 u32 addr;
11692                 __be32 data;
11693
11694                 addr = offset + i;
11695
11696                 memcpy(&data, buf + i, 4);
11697
11698                 /*
11699                  * The SEEPROM interface expects the data to always be opposite
11700                  * the native endian format.  We accomplish this by reversing
11701                  * all the operations that would have been performed on the
11702                  * data from a call to tg3_nvram_read_be32().
11703                  */
11704                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11705
11706                 val = tr32(GRC_EEPROM_ADDR);
11707                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11708
11709                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11710                         EEPROM_ADDR_READ);
11711                 tw32(GRC_EEPROM_ADDR, val |
11712                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
11713                         (addr & EEPROM_ADDR_ADDR_MASK) |
11714                         EEPROM_ADDR_START |
11715                         EEPROM_ADDR_WRITE);
11716
11717                 for (j = 0; j < 1000; j++) {
11718                         val = tr32(GRC_EEPROM_ADDR);
11719
11720                         if (val & EEPROM_ADDR_COMPLETE)
11721                                 break;
11722                         msleep(1);
11723                 }
11724                 if (!(val & EEPROM_ADDR_COMPLETE)) {
11725                         rc = -EBUSY;
11726                         break;
11727                 }
11728         }
11729
11730         return rc;
11731 }
11732
11733 /* offset and length are dword aligned */
11734 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11735                 u8 *buf)
11736 {
11737         int ret = 0;
11738         u32 pagesize = tp->nvram_pagesize;
11739         u32 pagemask = pagesize - 1;
11740         u32 nvram_cmd;
11741         u8 *tmp;
11742
11743         tmp = kmalloc(pagesize, GFP_KERNEL);
11744         if (tmp == NULL)
11745                 return -ENOMEM;
11746
11747         while (len) {
11748                 int j;
11749                 u32 phy_addr, page_off, size;
11750
11751                 phy_addr = offset & ~pagemask;
11752
11753                 for (j = 0; j < pagesize; j += 4) {
11754                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
11755                                                   (__be32 *) (tmp + j));
11756                         if (ret)
11757                                 break;
11758                 }
11759                 if (ret)
11760                         break;
11761
11762                 page_off = offset & pagemask;
11763                 size = pagesize;
11764                 if (len < size)
11765                         size = len;
11766
11767                 len -= size;
11768
11769                 memcpy(tmp + page_off, buf, size);
11770
11771                 offset = offset + (pagesize - page_off);
11772
11773                 tg3_enable_nvram_access(tp);
11774
11775                 /*
11776                  * Before we can erase the flash page, we need
11777                  * to issue a special "write enable" command.
11778                  */
11779                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11780
11781                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11782                         break;
11783
11784                 /* Erase the target page */
11785                 tw32(NVRAM_ADDR, phy_addr);
11786
11787                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11788                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11789
11790                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11791                         break;
11792
11793                 /* Issue another write enable to start the write. */
11794                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11795
11796                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11797                         break;
11798
11799                 for (j = 0; j < pagesize; j += 4) {
11800                         __be32 data;
11801
11802                         data = *((__be32 *) (tmp + j));
11803
11804                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
11805
11806                         tw32(NVRAM_ADDR, phy_addr + j);
11807
11808                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11809                                 NVRAM_CMD_WR;
11810
11811                         if (j == 0)
11812                                 nvram_cmd |= NVRAM_CMD_FIRST;
11813                         else if (j == (pagesize - 4))
11814                                 nvram_cmd |= NVRAM_CMD_LAST;
11815
11816                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11817                                 break;
11818                 }
11819                 if (ret)
11820                         break;
11821         }
11822
11823         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11824         tg3_nvram_exec_cmd(tp, nvram_cmd);
11825
11826         kfree(tmp);
11827
11828         return ret;
11829 }
11830
11831 /* offset and length are dword aligned */
11832 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11833                 u8 *buf)
11834 {
11835         int i, ret = 0;
11836
11837         for (i = 0; i < len; i += 4, offset += 4) {
11838                 u32 page_off, phy_addr, nvram_cmd;
11839                 __be32 data;
11840
11841                 memcpy(&data, buf + i, 4);
11842                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11843
11844                 page_off = offset % tp->nvram_pagesize;
11845
11846                 phy_addr = tg3_nvram_phys_addr(tp, offset);
11847
11848                 tw32(NVRAM_ADDR, phy_addr);
11849
11850                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11851
11852                 if (page_off == 0 || i == 0)
11853                         nvram_cmd |= NVRAM_CMD_FIRST;
11854                 if (page_off == (tp->nvram_pagesize - 4))
11855                         nvram_cmd |= NVRAM_CMD_LAST;
11856
11857                 if (i == (len - 4))
11858                         nvram_cmd |= NVRAM_CMD_LAST;
11859
11860                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11861                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11862                     (tp->nvram_jedecnum == JEDEC_ST) &&
11863                     (nvram_cmd & NVRAM_CMD_FIRST)) {
11864
11865                         if ((ret = tg3_nvram_exec_cmd(tp,
11866                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11867                                 NVRAM_CMD_DONE)))
11868
11869                                 break;
11870                 }
11871                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11872                         /* We always do complete word writes to eeprom. */
11873                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11874                 }
11875
11876                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11877                         break;
11878         }
11879         return ret;
11880 }
11881
11882 /* offset and length are dword aligned */
11883 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11884 {
11885         int ret;
11886
11887         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11888                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11889                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
11890                 udelay(40);
11891         }
11892
11893         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11894                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11895         } else {
11896                 u32 grc_mode;
11897
11898                 ret = tg3_nvram_lock(tp);
11899                 if (ret)
11900                         return ret;
11901
11902                 tg3_enable_nvram_access(tp);
11903                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11904                     !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
11905                         tw32(NVRAM_WRITE1, 0x406);
11906
11907                 grc_mode = tr32(GRC_MODE);
11908                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11909
11910                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11911                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11912
11913                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
11914                                 buf);
11915                 } else {
11916                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11917                                 buf);
11918                 }
11919
11920                 grc_mode = tr32(GRC_MODE);
11921                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11922
11923                 tg3_disable_nvram_access(tp);
11924                 tg3_nvram_unlock(tp);
11925         }
11926
11927         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11928                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11929                 udelay(40);
11930         }
11931
11932         return ret;
11933 }
11934
11935 struct subsys_tbl_ent {
11936         u16 subsys_vendor, subsys_devid;
11937         u32 phy_id;
11938 };
11939
11940 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
11941         /* Broadcom boards. */
11942         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11943           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
11944         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11945           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
11946         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11947           TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
11948         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11949           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
11950         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11951           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
11952         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11953           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
11954         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11955           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
11956         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11957           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
11958         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11959           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
11960         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11961           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
11962         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11963           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
11964
11965         /* 3com boards. */
11966         { TG3PCI_SUBVENDOR_ID_3COM,
11967           TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
11968         { TG3PCI_SUBVENDOR_ID_3COM,
11969           TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
11970         { TG3PCI_SUBVENDOR_ID_3COM,
11971           TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
11972         { TG3PCI_SUBVENDOR_ID_3COM,
11973           TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
11974         { TG3PCI_SUBVENDOR_ID_3COM,
11975           TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
11976
11977         /* DELL boards. */
11978         { TG3PCI_SUBVENDOR_ID_DELL,
11979           TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
11980         { TG3PCI_SUBVENDOR_ID_DELL,
11981           TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
11982         { TG3PCI_SUBVENDOR_ID_DELL,
11983           TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
11984         { TG3PCI_SUBVENDOR_ID_DELL,
11985           TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
11986
11987         /* Compaq boards. */
11988         { TG3PCI_SUBVENDOR_ID_COMPAQ,
11989           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
11990         { TG3PCI_SUBVENDOR_ID_COMPAQ,
11991           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
11992         { TG3PCI_SUBVENDOR_ID_COMPAQ,
11993           TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
11994         { TG3PCI_SUBVENDOR_ID_COMPAQ,
11995           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
11996         { TG3PCI_SUBVENDOR_ID_COMPAQ,
11997           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
11998
11999         /* IBM boards. */
12000         { TG3PCI_SUBVENDOR_ID_IBM,
12001           TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
12002 };
12003
12004 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
12005 {
12006         int i;
12007
12008         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12009                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12010                      tp->pdev->subsystem_vendor) &&
12011                     (subsys_id_to_phy_id[i].subsys_devid ==
12012                      tp->pdev->subsystem_device))
12013                         return &subsys_id_to_phy_id[i];
12014         }
12015         return NULL;
12016 }
12017
12018 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12019 {
12020         u32 val;
12021         u16 pmcsr;
12022
12023         /* On some early chips the SRAM cannot be accessed in D3hot state,
12024          * so need make sure we're in D0.
12025          */
12026         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12027         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12028         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12029         msleep(1);
12030
12031         /* Make sure register accesses (indirect or otherwise)
12032          * will function correctly.
12033          */
12034         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12035                                tp->misc_host_ctrl);
12036
12037         /* The memory arbiter has to be enabled in order for SRAM accesses
12038          * to succeed.  Normally on powerup the tg3 chip firmware will make
12039          * sure it is enabled, but other entities such as system netboot
12040          * code might disable it.
12041          */
12042         val = tr32(MEMARB_MODE);
12043         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12044
12045         tp->phy_id = TG3_PHY_ID_INVALID;
12046         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12047
12048         /* Assume an onboard device and WOL capable by default.  */
12049         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12050
12051         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12052                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12053                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12054                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12055                 }
12056                 val = tr32(VCPU_CFGSHDW);
12057                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12058                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12059                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12060                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
12061                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12062                 goto done;
12063         }
12064
12065         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12066         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12067                 u32 nic_cfg, led_cfg;
12068                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12069                 int eeprom_phy_serdes = 0;
12070
12071                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12072                 tp->nic_sram_data_cfg = nic_cfg;
12073
12074                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12075                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12076                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12077                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12078                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12079                     (ver > 0) && (ver < 0x100))
12080                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12081
12082                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12083                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12084
12085                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12086                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12087                         eeprom_phy_serdes = 1;
12088
12089                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12090                 if (nic_phy_id != 0) {
12091                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12092                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12093
12094                         eeprom_phy_id  = (id1 >> 16) << 10;
12095                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
12096                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
12097                 } else
12098                         eeprom_phy_id = 0;
12099
12100                 tp->phy_id = eeprom_phy_id;
12101                 if (eeprom_phy_serdes) {
12102                         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12103                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12104                         else
12105                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
12106                 }
12107
12108                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12109                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12110                                     SHASTA_EXT_LED_MODE_MASK);
12111                 else
12112                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12113
12114                 switch (led_cfg) {
12115                 default:
12116                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12117                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12118                         break;
12119
12120                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12121                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12122                         break;
12123
12124                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12125                         tp->led_ctrl = LED_CTRL_MODE_MAC;
12126
12127                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12128                          * read on some older 5700/5701 bootcode.
12129                          */
12130                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12131                             ASIC_REV_5700 ||
12132                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
12133                             ASIC_REV_5701)
12134                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12135
12136                         break;
12137
12138                 case SHASTA_EXT_LED_SHARED:
12139                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
12140                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12141                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12142                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12143                                                  LED_CTRL_MODE_PHY_2);
12144                         break;
12145
12146                 case SHASTA_EXT_LED_MAC:
12147                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12148                         break;
12149
12150                 case SHASTA_EXT_LED_COMBO:
12151                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
12152                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12153                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12154                                                  LED_CTRL_MODE_PHY_2);
12155                         break;
12156
12157                 }
12158
12159                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12160                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12161                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12162                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12163
12164                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12165                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12166
12167                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12168                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12169                         if ((tp->pdev->subsystem_vendor ==
12170                              PCI_VENDOR_ID_ARIMA) &&
12171                             (tp->pdev->subsystem_device == 0x205a ||
12172                              tp->pdev->subsystem_device == 0x2063))
12173                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12174                 } else {
12175                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12176                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12177                 }
12178
12179                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12180                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12181                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12182                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12183                 }
12184
12185                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12186                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12187                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12188
12189                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
12190                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12191                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12192
12193                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12194                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12195                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12196
12197                 if (cfg2 & (1 << 17))
12198                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
12199
12200                 /* serdes signal pre-emphasis in register 0x590 set by */
12201                 /* bootcode if bit 18 is set */
12202                 if (cfg2 & (1 << 18))
12203                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
12204
12205                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12206                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
12207                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12208                         tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
12209
12210                 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12211                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12212                     !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
12213                         u32 cfg3;
12214
12215                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12216                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12217                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12218                 }
12219
12220                 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12221                         tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
12222                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12223                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12224                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12225                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12226         }
12227 done:
12228         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12229         device_set_wakeup_enable(&tp->pdev->dev,
12230                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12231 }
12232
12233 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12234 {
12235         int i;
12236         u32 val;
12237
12238         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12239         tw32(OTP_CTRL, cmd);
12240
12241         /* Wait for up to 1 ms for command to execute. */
12242         for (i = 0; i < 100; i++) {
12243                 val = tr32(OTP_STATUS);
12244                 if (val & OTP_STATUS_CMD_DONE)
12245                         break;
12246                 udelay(10);
12247         }
12248
12249         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12250 }
12251
12252 /* Read the gphy configuration from the OTP region of the chip.  The gphy
12253  * configuration is a 32-bit value that straddles the alignment boundary.
12254  * We do two 32-bit reads and then shift and merge the results.
12255  */
12256 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12257 {
12258         u32 bhalf_otp, thalf_otp;
12259
12260         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12261
12262         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12263                 return 0;
12264
12265         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12266
12267         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12268                 return 0;
12269
12270         thalf_otp = tr32(OTP_READ_DATA);
12271
12272         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12273
12274         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12275                 return 0;
12276
12277         bhalf_otp = tr32(OTP_READ_DATA);
12278
12279         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12280 }
12281
12282 static int __devinit tg3_phy_probe(struct tg3 *tp)
12283 {
12284         u32 hw_phy_id_1, hw_phy_id_2;
12285         u32 hw_phy_id, hw_phy_id_masked;
12286         int err;
12287
12288         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12289                 return tg3_phy_init(tp);
12290
12291         /* Reading the PHY ID register can conflict with ASF
12292          * firmware access to the PHY hardware.
12293          */
12294         err = 0;
12295         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12296             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12297                 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
12298         } else {
12299                 /* Now read the physical PHY_ID from the chip and verify
12300                  * that it is sane.  If it doesn't look good, we fall back
12301                  * to either the hard-coded table based PHY_ID and failing
12302                  * that the value found in the eeprom area.
12303                  */
12304                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12305                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12306
12307                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
12308                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12309                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
12310
12311                 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
12312         }
12313
12314         if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
12315                 tp->phy_id = hw_phy_id;
12316                 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
12317                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12318                 else
12319                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
12320         } else {
12321                 if (tp->phy_id != TG3_PHY_ID_INVALID) {
12322                         /* Do nothing, phy ID already set up in
12323                          * tg3_get_eeprom_hw_cfg().
12324                          */
12325                 } else {
12326                         struct subsys_tbl_ent *p;
12327
12328                         /* No eeprom signature?  Try the hardcoded
12329                          * subsys device table.
12330                          */
12331                         p = tg3_lookup_by_subsys(tp);
12332                         if (!p)
12333                                 return -ENODEV;
12334
12335                         tp->phy_id = p->phy_id;
12336                         if (!tp->phy_id ||
12337                             tp->phy_id == TG3_PHY_ID_BCM8002)
12338                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12339                 }
12340         }
12341
12342         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
12343             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12344             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12345                 u32 bmsr, adv_reg, tg3_ctrl, mask;
12346
12347                 tg3_readphy(tp, MII_BMSR, &bmsr);
12348                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12349                     (bmsr & BMSR_LSTATUS))
12350                         goto skip_phy_reset;
12351
12352                 err = tg3_phy_reset(tp);
12353                 if (err)
12354                         return err;
12355
12356                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12357                            ADVERTISE_100HALF | ADVERTISE_100FULL |
12358                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12359                 tg3_ctrl = 0;
12360                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12361                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12362                                     MII_TG3_CTRL_ADV_1000_FULL);
12363                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12364                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12365                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12366                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
12367                 }
12368
12369                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12370                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12371                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12372                 if (!tg3_copper_is_advertising_all(tp, mask)) {
12373                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12374
12375                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12376                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12377
12378                         tg3_writephy(tp, MII_BMCR,
12379                                      BMCR_ANENABLE | BMCR_ANRESTART);
12380                 }
12381                 tg3_phy_set_wirespeed(tp);
12382
12383                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12384                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12385                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12386         }
12387
12388 skip_phy_reset:
12389         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
12390                 err = tg3_init_5401phy_dsp(tp);
12391                 if (err)
12392                         return err;
12393
12394                 err = tg3_init_5401phy_dsp(tp);
12395         }
12396
12397         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
12398                 tp->link_config.advertising =
12399                         (ADVERTISED_1000baseT_Half |
12400                          ADVERTISED_1000baseT_Full |
12401                          ADVERTISED_Autoneg |
12402                          ADVERTISED_FIBRE);
12403         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12404                 tp->link_config.advertising &=
12405                         ~(ADVERTISED_1000baseT_Half |
12406                           ADVERTISED_1000baseT_Full);
12407
12408         return err;
12409 }
12410
12411 static void __devinit tg3_read_vpd(struct tg3 *tp)
12412 {
12413         u8 vpd_data[TG3_NVM_VPD_LEN];
12414         unsigned int block_end, rosize, len;
12415         int j, i = 0;
12416         u32 magic;
12417
12418         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12419             tg3_nvram_read(tp, 0x0, &magic))
12420                 goto out_not_found;
12421
12422         if (magic == TG3_EEPROM_MAGIC) {
12423                 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12424                         u32 tmp;
12425
12426                         /* The data is in little-endian format in NVRAM.
12427                          * Use the big-endian read routines to preserve
12428                          * the byte order as it exists in NVRAM.
12429                          */
12430                         if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12431                                 goto out_not_found;
12432
12433                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12434                 }
12435         } else {
12436                 ssize_t cnt;
12437                 unsigned int pos = 0;
12438
12439                 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12440                         cnt = pci_read_vpd(tp->pdev, pos,
12441                                            TG3_NVM_VPD_LEN - pos,
12442                                            &vpd_data[pos]);
12443                         if (cnt == -ETIMEDOUT || -EINTR)
12444                                 cnt = 0;
12445                         else if (cnt < 0)
12446                                 goto out_not_found;
12447                 }
12448                 if (pos != TG3_NVM_VPD_LEN)
12449                         goto out_not_found;
12450         }
12451
12452         i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
12453                              PCI_VPD_LRDT_RO_DATA);
12454         if (i < 0)
12455                 goto out_not_found;
12456
12457         rosize = pci_vpd_lrdt_size(&vpd_data[i]);
12458         block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
12459         i += PCI_VPD_LRDT_TAG_SIZE;
12460
12461         if (block_end > TG3_NVM_VPD_LEN)
12462                 goto out_not_found;
12463
12464         j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12465                                       PCI_VPD_RO_KEYWORD_MFR_ID);
12466         if (j > 0) {
12467                 len = pci_vpd_info_field_size(&vpd_data[j]);
12468
12469                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12470                 if (j + len > block_end || len != 4 ||
12471                     memcmp(&vpd_data[j], "1028", 4))
12472                         goto partno;
12473
12474                 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12475                                               PCI_VPD_RO_KEYWORD_VENDOR0);
12476                 if (j < 0)
12477                         goto partno;
12478
12479                 len = pci_vpd_info_field_size(&vpd_data[j]);
12480
12481                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12482                 if (j + len > block_end)
12483                         goto partno;
12484
12485                 memcpy(tp->fw_ver, &vpd_data[j], len);
12486                 strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
12487         }
12488
12489 partno:
12490         i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12491                                       PCI_VPD_RO_KEYWORD_PARTNO);
12492         if (i < 0)
12493                 goto out_not_found;
12494
12495         len = pci_vpd_info_field_size(&vpd_data[i]);
12496
12497         i += PCI_VPD_INFO_FLD_HDR_SIZE;
12498         if (len > TG3_BPN_SIZE ||
12499             (len + i) > TG3_NVM_VPD_LEN)
12500                 goto out_not_found;
12501
12502         memcpy(tp->board_part_number, &vpd_data[i], len);
12503
12504         return;
12505
12506 out_not_found:
12507         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12508                 strcpy(tp->board_part_number, "BCM95906");
12509         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12510                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12511                 strcpy(tp->board_part_number, "BCM57780");
12512         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12513                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12514                 strcpy(tp->board_part_number, "BCM57760");
12515         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12516                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12517                 strcpy(tp->board_part_number, "BCM57790");
12518         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12519                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12520                 strcpy(tp->board_part_number, "BCM57788");
12521         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12522                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
12523                 strcpy(tp->board_part_number, "BCM57761");
12524         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12525                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
12526                 strcpy(tp->board_part_number, "BCM57765");
12527         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12528                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
12529                 strcpy(tp->board_part_number, "BCM57781");
12530         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12531                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
12532                 strcpy(tp->board_part_number, "BCM57785");
12533         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12534                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
12535                 strcpy(tp->board_part_number, "BCM57791");
12536         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12537                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12538                 strcpy(tp->board_part_number, "BCM57795");
12539         else
12540                 strcpy(tp->board_part_number, "none");
12541 }
12542
12543 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12544 {
12545         u32 val;
12546
12547         if (tg3_nvram_read(tp, offset, &val) ||
12548             (val & 0xfc000000) != 0x0c000000 ||
12549             tg3_nvram_read(tp, offset + 4, &val) ||
12550             val != 0)
12551                 return 0;
12552
12553         return 1;
12554 }
12555
12556 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12557 {
12558         u32 val, offset, start, ver_offset;
12559         int i, dst_off;
12560         bool newver = false;
12561
12562         if (tg3_nvram_read(tp, 0xc, &offset) ||
12563             tg3_nvram_read(tp, 0x4, &start))
12564                 return;
12565
12566         offset = tg3_nvram_logical_addr(tp, offset);
12567
12568         if (tg3_nvram_read(tp, offset, &val))
12569                 return;
12570
12571         if ((val & 0xfc000000) == 0x0c000000) {
12572                 if (tg3_nvram_read(tp, offset + 4, &val))
12573                         return;
12574
12575                 if (val == 0)
12576                         newver = true;
12577         }
12578
12579         dst_off = strlen(tp->fw_ver);
12580
12581         if (newver) {
12582                 if (TG3_VER_SIZE - dst_off < 16 ||
12583                     tg3_nvram_read(tp, offset + 8, &ver_offset))
12584                         return;
12585
12586                 offset = offset + ver_offset - start;
12587                 for (i = 0; i < 16; i += 4) {
12588                         __be32 v;
12589                         if (tg3_nvram_read_be32(tp, offset + i, &v))
12590                                 return;
12591
12592                         memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
12593                 }
12594         } else {
12595                 u32 major, minor;
12596
12597                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12598                         return;
12599
12600                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12601                         TG3_NVM_BCVER_MAJSFT;
12602                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12603                 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
12604                          "v%d.%02d", major, minor);
12605         }
12606 }
12607
12608 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12609 {
12610         u32 val, major, minor;
12611
12612         /* Use native endian representation */
12613         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12614                 return;
12615
12616         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12617                 TG3_NVM_HWSB_CFG1_MAJSFT;
12618         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12619                 TG3_NVM_HWSB_CFG1_MINSFT;
12620
12621         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12622 }
12623
12624 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12625 {
12626         u32 offset, major, minor, build;
12627
12628         strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
12629
12630         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12631                 return;
12632
12633         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12634         case TG3_EEPROM_SB_REVISION_0:
12635                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12636                 break;
12637         case TG3_EEPROM_SB_REVISION_2:
12638                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12639                 break;
12640         case TG3_EEPROM_SB_REVISION_3:
12641                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12642                 break;
12643         case TG3_EEPROM_SB_REVISION_4:
12644                 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
12645                 break;
12646         case TG3_EEPROM_SB_REVISION_5:
12647                 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
12648                 break;
12649         default:
12650                 return;
12651         }
12652
12653         if (tg3_nvram_read(tp, offset, &val))
12654                 return;
12655
12656         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12657                 TG3_EEPROM_SB_EDH_BLD_SHFT;
12658         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12659                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12660         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
12661
12662         if (minor > 99 || build > 26)
12663                 return;
12664
12665         offset = strlen(tp->fw_ver);
12666         snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
12667                  " v%d.%02d", major, minor);
12668
12669         if (build > 0) {
12670                 offset = strlen(tp->fw_ver);
12671                 if (offset < TG3_VER_SIZE - 1)
12672                         tp->fw_ver[offset] = 'a' + build - 1;
12673         }
12674 }
12675
12676 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12677 {
12678         u32 val, offset, start;
12679         int i, vlen;
12680
12681         for (offset = TG3_NVM_DIR_START;
12682              offset < TG3_NVM_DIR_END;
12683              offset += TG3_NVM_DIRENT_SIZE) {
12684                 if (tg3_nvram_read(tp, offset, &val))
12685                         return;
12686
12687                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12688                         break;
12689         }
12690
12691         if (offset == TG3_NVM_DIR_END)
12692                 return;
12693
12694         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12695                 start = 0x08000000;
12696         else if (tg3_nvram_read(tp, offset - 4, &start))
12697                 return;
12698
12699         if (tg3_nvram_read(tp, offset + 4, &offset) ||
12700             !tg3_fw_img_is_valid(tp, offset) ||
12701             tg3_nvram_read(tp, offset + 8, &val))
12702                 return;
12703
12704         offset += val - start;
12705
12706         vlen = strlen(tp->fw_ver);
12707
12708         tp->fw_ver[vlen++] = ',';
12709         tp->fw_ver[vlen++] = ' ';
12710
12711         for (i = 0; i < 4; i++) {
12712                 __be32 v;
12713                 if (tg3_nvram_read_be32(tp, offset, &v))
12714                         return;
12715
12716                 offset += sizeof(v);
12717
12718                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12719                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12720                         break;
12721                 }
12722
12723                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12724                 vlen += sizeof(v);
12725         }
12726 }
12727
12728 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12729 {
12730         int vlen;
12731         u32 apedata;
12732         char *fwtype;
12733
12734         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12735             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
12736                 return;
12737
12738         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12739         if (apedata != APE_SEG_SIG_MAGIC)
12740                 return;
12741
12742         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12743         if (!(apedata & APE_FW_STATUS_READY))
12744                 return;
12745
12746         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12747
12748         if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI)
12749                 fwtype = "NCSI";
12750         else
12751                 fwtype = "DASH";
12752
12753         vlen = strlen(tp->fw_ver);
12754
12755         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
12756                  fwtype,
12757                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12758                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12759                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12760                  (apedata & APE_FW_VERSION_BLDMSK));
12761 }
12762
12763 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12764 {
12765         u32 val;
12766         bool vpd_vers = false;
12767
12768         if (tp->fw_ver[0] != 0)
12769                 vpd_vers = true;
12770
12771         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12772                 strcat(tp->fw_ver, "sb");
12773                 return;
12774         }
12775
12776         if (tg3_nvram_read(tp, 0, &val))
12777                 return;
12778
12779         if (val == TG3_EEPROM_MAGIC)
12780                 tg3_read_bc_ver(tp);
12781         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12782                 tg3_read_sb_ver(tp, val);
12783         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12784                 tg3_read_hwsb_ver(tp);
12785         else
12786                 return;
12787
12788         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12789              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
12790                 goto done;
12791
12792         tg3_read_mgmtfw_ver(tp);
12793
12794 done:
12795         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12796 }
12797
12798 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12799
12800 static void inline vlan_features_add(struct net_device *dev, unsigned long flags)
12801 {
12802 #if TG3_VLAN_TAG_USED
12803         dev->vlan_features |= flags;
12804 #endif
12805 }
12806
12807 static int __devinit tg3_get_invariants(struct tg3 *tp)
12808 {
12809         static struct pci_device_id write_reorder_chipsets[] = {
12810                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12811                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12812                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12813                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12814                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12815                              PCI_DEVICE_ID_VIA_8385_0) },
12816                 { },
12817         };
12818         u32 misc_ctrl_reg;
12819         u32 pci_state_reg, grc_misc_cfg;
12820         u32 val;
12821         u16 pci_cmd;
12822         int err;
12823
12824         /* Force memory write invalidate off.  If we leave it on,
12825          * then on 5700_BX chips we have to enable a workaround.
12826          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12827          * to match the cacheline size.  The Broadcom driver have this
12828          * workaround but turns MWI off all the times so never uses
12829          * it.  This seems to suggest that the workaround is insufficient.
12830          */
12831         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12832         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12833         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12834
12835         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12836          * has the register indirect write enable bit set before
12837          * we try to access any of the MMIO registers.  It is also
12838          * critical that the PCI-X hw workaround situation is decided
12839          * before that as well.
12840          */
12841         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12842                               &misc_ctrl_reg);
12843
12844         tp->pci_chip_rev_id = (misc_ctrl_reg >>
12845                                MISC_HOST_CTRL_CHIPREV_SHIFT);
12846         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12847                 u32 prod_id_asic_rev;
12848
12849                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12850                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12851                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724 ||
12852                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719)
12853                         pci_read_config_dword(tp->pdev,
12854                                               TG3PCI_GEN2_PRODID_ASICREV,
12855                                               &prod_id_asic_rev);
12856                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
12857                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
12858                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
12859                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
12860                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
12861                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12862                         pci_read_config_dword(tp->pdev,
12863                                               TG3PCI_GEN15_PRODID_ASICREV,
12864                                               &prod_id_asic_rev);
12865                 else
12866                         pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12867                                               &prod_id_asic_rev);
12868
12869                 tp->pci_chip_rev_id = prod_id_asic_rev;
12870         }
12871
12872         /* Wrong chip ID in 5752 A0. This code can be removed later
12873          * as A0 is not in production.
12874          */
12875         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12876                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12877
12878         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12879          * we need to disable memory and use config. cycles
12880          * only to access all registers. The 5702/03 chips
12881          * can mistakenly decode the special cycles from the
12882          * ICH chipsets as memory write cycles, causing corruption
12883          * of register and memory space. Only certain ICH bridges
12884          * will drive special cycles with non-zero data during the
12885          * address phase which can fall within the 5703's address
12886          * range. This is not an ICH bug as the PCI spec allows
12887          * non-zero address during special cycles. However, only
12888          * these ICH bridges are known to drive non-zero addresses
12889          * during special cycles.
12890          *
12891          * Since special cycles do not cross PCI bridges, we only
12892          * enable this workaround if the 5703 is on the secondary
12893          * bus of these ICH bridges.
12894          */
12895         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12896             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12897                 static struct tg3_dev_id {
12898                         u32     vendor;
12899                         u32     device;
12900                         u32     rev;
12901                 } ich_chipsets[] = {
12902                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12903                           PCI_ANY_ID },
12904                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12905                           PCI_ANY_ID },
12906                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12907                           0xa },
12908                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12909                           PCI_ANY_ID },
12910                         { },
12911                 };
12912                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12913                 struct pci_dev *bridge = NULL;
12914
12915                 while (pci_id->vendor != 0) {
12916                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
12917                                                 bridge);
12918                         if (!bridge) {
12919                                 pci_id++;
12920                                 continue;
12921                         }
12922                         if (pci_id->rev != PCI_ANY_ID) {
12923                                 if (bridge->revision > pci_id->rev)
12924                                         continue;
12925                         }
12926                         if (bridge->subordinate &&
12927                             (bridge->subordinate->number ==
12928                              tp->pdev->bus->number)) {
12929
12930                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12931                                 pci_dev_put(bridge);
12932                                 break;
12933                         }
12934                 }
12935         }
12936
12937         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12938                 static struct tg3_dev_id {
12939                         u32     vendor;
12940                         u32     device;
12941                 } bridge_chipsets[] = {
12942                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12943                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12944                         { },
12945                 };
12946                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12947                 struct pci_dev *bridge = NULL;
12948
12949                 while (pci_id->vendor != 0) {
12950                         bridge = pci_get_device(pci_id->vendor,
12951                                                 pci_id->device,
12952                                                 bridge);
12953                         if (!bridge) {
12954                                 pci_id++;
12955                                 continue;
12956                         }
12957                         if (bridge->subordinate &&
12958                             (bridge->subordinate->number <=
12959                              tp->pdev->bus->number) &&
12960                             (bridge->subordinate->subordinate >=
12961                              tp->pdev->bus->number)) {
12962                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12963                                 pci_dev_put(bridge);
12964                                 break;
12965                         }
12966                 }
12967         }
12968
12969         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12970          * DMA addresses > 40-bit. This bridge may have other additional
12971          * 57xx devices behind it in some 4-port NIC designs for example.
12972          * Any tg3 device found behind the bridge will also need the 40-bit
12973          * DMA workaround.
12974          */
12975         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12976             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12977                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
12978                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12979                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
12980         } else {
12981                 struct pci_dev *bridge = NULL;
12982
12983                 do {
12984                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12985                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
12986                                                 bridge);
12987                         if (bridge && bridge->subordinate &&
12988                             (bridge->subordinate->number <=
12989                              tp->pdev->bus->number) &&
12990                             (bridge->subordinate->subordinate >=
12991                              tp->pdev->bus->number)) {
12992                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12993                                 pci_dev_put(bridge);
12994                                 break;
12995                         }
12996                 } while (bridge);
12997         }
12998
12999         /* Initialize misc host control in PCI block. */
13000         tp->misc_host_ctrl |= (misc_ctrl_reg &
13001                                MISC_HOST_CTRL_CHIPREV);
13002         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13003                                tp->misc_host_ctrl);
13004
13005         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13006             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13007             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13008                 tp->pdev_peer = tg3_find_peer(tp);
13009
13010         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13011             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13012             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13013                 tp->tg3_flags3 |= TG3_FLG3_5717_PLUS;
13014
13015         /* Intentionally exclude ASIC_REV_5906 */
13016         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13017             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13018             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13019             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13020             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13021             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13022             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13023                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13024
13025         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13026             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13027             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13028             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13029             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13030                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13031
13032         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13033             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13034                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13035
13036         /* 5700 B0 chips do not support checksumming correctly due
13037          * to hardware bugs.
13038          */
13039         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13040                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13041         else {
13042                 unsigned long features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_GRO;
13043
13044                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13045                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13046                         features |= NETIF_F_IPV6_CSUM;
13047                 tp->dev->features |= features;
13048                 vlan_features_add(tp->dev, features);
13049         }
13050
13051         /* Determine TSO capabilities */
13052         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13053                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13054         else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13055                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13056                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13057         else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13058                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13059                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13060                     tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13061                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13062         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13063                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13064                    tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13065                 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13066                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13067                         tp->fw_needed = FIRMWARE_TG3TSO5;
13068                 else
13069                         tp->fw_needed = FIRMWARE_TG3TSO;
13070         }
13071
13072         tp->irq_max = 1;
13073
13074         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13075                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13076                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13077                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13078                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13079                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13080                      tp->pdev_peer == tp->pdev))
13081                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13082
13083                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13084                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13085                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13086                 }
13087
13088                 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
13089                         tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13090                         tp->irq_max = TG3_IRQ_MAX_VECS;
13091                 }
13092         }
13093
13094         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13095             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13096             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13097                 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13098         else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13099                 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13100                 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13101         }
13102
13103         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13104                 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13105
13106         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13107             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13108             (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13109                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13110
13111         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13112                               &pci_state_reg);
13113
13114         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13115         if (tp->pcie_cap != 0) {
13116                 u16 lnkctl;
13117
13118                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13119
13120                 pcie_set_readrq(tp->pdev, 4096);
13121
13122                 pci_read_config_word(tp->pdev,
13123                                      tp->pcie_cap + PCI_EXP_LNKCTL,
13124                                      &lnkctl);
13125                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13126                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13127                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13128                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13129                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13130                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13131                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13132                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13133                 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13134                         tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13135                 }
13136         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13137                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13138         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13139                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13140                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13141                 if (!tp->pcix_cap) {
13142                         dev_err(&tp->pdev->dev,
13143                                 "Cannot find PCI-X capability, aborting\n");
13144                         return -EIO;
13145                 }
13146
13147                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13148                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13149         }
13150
13151         /* If we have an AMD 762 or VIA K8T800 chipset, write
13152          * reordering to the mailbox registers done by the host
13153          * controller can cause major troubles.  We read back from
13154          * every mailbox register write to force the writes to be
13155          * posted to the chip in order.
13156          */
13157         if (pci_dev_present(write_reorder_chipsets) &&
13158             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13159                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13160
13161         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13162                              &tp->pci_cacheline_sz);
13163         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13164                              &tp->pci_lat_timer);
13165         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13166             tp->pci_lat_timer < 64) {
13167                 tp->pci_lat_timer = 64;
13168                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13169                                       tp->pci_lat_timer);
13170         }
13171
13172         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13173                 /* 5700 BX chips need to have their TX producer index
13174                  * mailboxes written twice to workaround a bug.
13175                  */
13176                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13177
13178                 /* If we are in PCI-X mode, enable register write workaround.
13179                  *
13180                  * The workaround is to use indirect register accesses
13181                  * for all chip writes not to mailbox registers.
13182                  */
13183                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13184                         u32 pm_reg;
13185
13186                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13187
13188                         /* The chip can have it's power management PCI config
13189                          * space registers clobbered due to this bug.
13190                          * So explicitly force the chip into D0 here.
13191                          */
13192                         pci_read_config_dword(tp->pdev,
13193                                               tp->pm_cap + PCI_PM_CTRL,
13194                                               &pm_reg);
13195                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13196                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13197                         pci_write_config_dword(tp->pdev,
13198                                                tp->pm_cap + PCI_PM_CTRL,
13199                                                pm_reg);
13200
13201                         /* Also, force SERR#/PERR# in PCI command. */
13202                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13203                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13204                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13205                 }
13206         }
13207
13208         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13209                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13210         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13211                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13212
13213         /* Chip-specific fixup from Broadcom driver */
13214         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13215             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13216                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13217                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13218         }
13219
13220         /* Default fast path register access methods */
13221         tp->read32 = tg3_read32;
13222         tp->write32 = tg3_write32;
13223         tp->read32_mbox = tg3_read32;
13224         tp->write32_mbox = tg3_write32;
13225         tp->write32_tx_mbox = tg3_write32;
13226         tp->write32_rx_mbox = tg3_write32;
13227
13228         /* Various workaround register access methods */
13229         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13230                 tp->write32 = tg3_write_indirect_reg32;
13231         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13232                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13233                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13234                 /*
13235                  * Back to back register writes can cause problems on these
13236                  * chips, the workaround is to read back all reg writes
13237                  * except those to mailbox regs.
13238                  *
13239                  * See tg3_write_indirect_reg32().
13240                  */
13241                 tp->write32 = tg3_write_flush_reg32;
13242         }
13243
13244         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13245             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13246                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13247                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13248                         tp->write32_rx_mbox = tg3_write_flush_reg32;
13249         }
13250
13251         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13252                 tp->read32 = tg3_read_indirect_reg32;
13253                 tp->write32 = tg3_write_indirect_reg32;
13254                 tp->read32_mbox = tg3_read_indirect_mbox;
13255                 tp->write32_mbox = tg3_write_indirect_mbox;
13256                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13257                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13258
13259                 iounmap(tp->regs);
13260                 tp->regs = NULL;
13261
13262                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13263                 pci_cmd &= ~PCI_COMMAND_MEMORY;
13264                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13265         }
13266         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13267                 tp->read32_mbox = tg3_read32_mbox_5906;
13268                 tp->write32_mbox = tg3_write32_mbox_5906;
13269                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13270                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13271         }
13272
13273         if (tp->write32 == tg3_write_indirect_reg32 ||
13274             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13275              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13276               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13277                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13278
13279         /* Get eeprom hw config before calling tg3_set_power_state().
13280          * In particular, the TG3_FLG2_IS_NIC flag must be
13281          * determined before calling tg3_set_power_state() so that
13282          * we know whether or not to switch out of Vaux power.
13283          * When the flag is set, it means that GPIO1 is used for eeprom
13284          * write protect and also implies that it is a LOM where GPIOs
13285          * are not used to switch power.
13286          */
13287         tg3_get_eeprom_hw_cfg(tp);
13288
13289         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13290                 /* Allow reads and writes to the
13291                  * APE register and memory space.
13292                  */
13293                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13294                                  PCISTATE_ALLOW_APE_SHMEM_WR |
13295                                  PCISTATE_ALLOW_APE_PSPACE_WR;
13296                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13297                                        pci_state_reg);
13298         }
13299
13300         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13301             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13302             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13303             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13304             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13305                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13306
13307         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13308          * GPIO1 driven high will bring 5700's external PHY out of reset.
13309          * It is also used as eeprom write protect on LOMs.
13310          */
13311         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13312         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13313             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13314                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13315                                        GRC_LCLCTRL_GPIO_OUTPUT1);
13316         /* Unused GPIO3 must be driven as output on 5752 because there
13317          * are no pull-up resistors on unused GPIO pins.
13318          */
13319         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13320                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13321
13322         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13323             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13324             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13325                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13326
13327         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13328             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13329                 /* Turn off the debug UART. */
13330                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13331                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13332                         /* Keep VMain power. */
13333                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13334                                               GRC_LCLCTRL_GPIO_OUTPUT0;
13335         }
13336
13337         /* Force the chip into D0. */
13338         err = tg3_set_power_state(tp, PCI_D0);
13339         if (err) {
13340                 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
13341                 return err;
13342         }
13343
13344         /* Derive initial jumbo mode from MTU assigned in
13345          * ether_setup() via the alloc_etherdev() call
13346          */
13347         if (tp->dev->mtu > ETH_DATA_LEN &&
13348             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13349                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13350
13351         /* Determine WakeOnLan speed to use. */
13352         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13353             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13354             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13355             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13356                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13357         } else {
13358                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13359         }
13360
13361         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13362                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
13363
13364         /* A few boards don't want Ethernet@WireSpeed phy feature */
13365         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13366             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13367              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13368              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13369             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
13370             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
13371                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
13372
13373         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13374             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13375                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
13376         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13377                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
13378
13379         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13380             !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
13381             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13382             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13383             !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
13384                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13385                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13386                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13387                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13388                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13389                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13390                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
13391                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13392                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
13393                 } else
13394                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
13395         }
13396
13397         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13398             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13399                 tp->phy_otp = tg3_read_otp_phycfg(tp);
13400                 if (tp->phy_otp == 0)
13401                         tp->phy_otp = TG3_OTP_DEFAULT;
13402         }
13403
13404         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13405                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13406         else
13407                 tp->mi_mode = MAC_MI_MODE_BASE;
13408
13409         tp->coalesce_mode = 0;
13410         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13411             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13412                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13413
13414         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13415             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13416                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13417
13418         err = tg3_mdio_init(tp);
13419         if (err)
13420                 return err;
13421
13422         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
13423             tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
13424                 return -ENOTSUPP;
13425
13426         /* Initialize data/descriptor byte/word swapping. */
13427         val = tr32(GRC_MODE);
13428         val &= GRC_MODE_HOST_STACKUP;
13429         tw32(GRC_MODE, val | tp->grc_mode);
13430
13431         tg3_switch_clocks(tp);
13432
13433         /* Clear this out for sanity. */
13434         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13435
13436         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13437                               &pci_state_reg);
13438         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13439             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13440                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13441
13442                 if (chiprevid == CHIPREV_ID_5701_A0 ||
13443                     chiprevid == CHIPREV_ID_5701_B0 ||
13444                     chiprevid == CHIPREV_ID_5701_B2 ||
13445                     chiprevid == CHIPREV_ID_5701_B5) {
13446                         void __iomem *sram_base;
13447
13448                         /* Write some dummy words into the SRAM status block
13449                          * area, see if it reads back correctly.  If the return
13450                          * value is bad, force enable the PCIX workaround.
13451                          */
13452                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13453
13454                         writel(0x00000000, sram_base);
13455                         writel(0x00000000, sram_base + 4);
13456                         writel(0xffffffff, sram_base + 4);
13457                         if (readl(sram_base) != 0x00000000)
13458                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13459                 }
13460         }
13461
13462         udelay(50);
13463         tg3_nvram_init(tp);
13464
13465         grc_misc_cfg = tr32(GRC_MISC_CFG);
13466         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13467
13468         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13469             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13470              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13471                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13472
13473         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13474             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13475                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13476         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13477                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13478                                       HOSTCC_MODE_CLRTICK_TXBD);
13479
13480                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13481                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13482                                        tp->misc_host_ctrl);
13483         }
13484
13485         /* Preserve the APE MAC_MODE bits */
13486         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13487                 tp->mac_mode = tr32(MAC_MODE) |
13488                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13489         else
13490                 tp->mac_mode = TG3_DEF_MAC_MODE;
13491
13492         /* these are limited to 10/100 only */
13493         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13494              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13495             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13496              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13497              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13498               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13499               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13500             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13501              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13502               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13503               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13504             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13505             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13506             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
13507             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
13508                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13509
13510         err = tg3_phy_probe(tp);
13511         if (err) {
13512                 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
13513                 /* ... but do not return immediately ... */
13514                 tg3_mdio_fini(tp);
13515         }
13516
13517         tg3_read_vpd(tp);
13518         tg3_read_fw_ver(tp);
13519
13520         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13521                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13522         } else {
13523                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13524                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13525                 else
13526                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13527         }
13528
13529         /* 5700 {AX,BX} chips have a broken status block link
13530          * change bit implementation, so we must use the
13531          * status register in those cases.
13532          */
13533         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13534                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13535         else
13536                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13537
13538         /* The led_ctrl is set during tg3_phy_probe, here we might
13539          * have to force the link status polling mechanism based
13540          * upon subsystem IDs.
13541          */
13542         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13543             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13544             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13545                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13546                                   TG3_FLAG_USE_LINKCHG_REG);
13547         }
13548
13549         /* For all SERDES we poll the MAC status register. */
13550         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13551                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13552         else
13553                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13554
13555         tp->rx_offset = NET_IP_ALIGN + TG3_RX_HEADROOM;
13556         tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
13557         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13558             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
13559                 tp->rx_offset -= NET_IP_ALIGN;
13560 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
13561                 tp->rx_copy_thresh = ~(u16)0;
13562 #endif
13563         }
13564
13565         tp->rx_std_max_post = TG3_RX_RING_SIZE;
13566
13567         /* Increment the rx prod index on the rx std ring by at most
13568          * 8 for these chips to workaround hw errata.
13569          */
13570         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13571             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13572             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13573                 tp->rx_std_max_post = 8;
13574
13575         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13576                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13577                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
13578
13579         return err;
13580 }
13581
13582 #ifdef CONFIG_SPARC
13583 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13584 {
13585         struct net_device *dev = tp->dev;
13586         struct pci_dev *pdev = tp->pdev;
13587         struct device_node *dp = pci_device_to_OF_node(pdev);
13588         const unsigned char *addr;
13589         int len;
13590
13591         addr = of_get_property(dp, "local-mac-address", &len);
13592         if (addr && len == 6) {
13593                 memcpy(dev->dev_addr, addr, 6);
13594                 memcpy(dev->perm_addr, dev->dev_addr, 6);
13595                 return 0;
13596         }
13597         return -ENODEV;
13598 }
13599
13600 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13601 {
13602         struct net_device *dev = tp->dev;
13603
13604         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13605         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13606         return 0;
13607 }
13608 #endif
13609
13610 static int __devinit tg3_get_device_address(struct tg3 *tp)
13611 {
13612         struct net_device *dev = tp->dev;
13613         u32 hi, lo, mac_offset;
13614         int addr_ok = 0;
13615
13616 #ifdef CONFIG_SPARC
13617         if (!tg3_get_macaddr_sparc(tp))
13618                 return 0;
13619 #endif
13620
13621         mac_offset = 0x7c;
13622         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13623             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13624                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13625                         mac_offset = 0xcc;
13626                 if (tg3_nvram_lock(tp))
13627                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13628                 else
13629                         tg3_nvram_unlock(tp);
13630         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13631                    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
13632                 if (PCI_FUNC(tp->pdev->devfn) & 1)
13633                         mac_offset = 0xcc;
13634                 if (PCI_FUNC(tp->pdev->devfn) > 1)
13635                         mac_offset += 0x18c;
13636         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13637                 mac_offset = 0x10;
13638
13639         /* First try to get it from MAC address mailbox. */
13640         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13641         if ((hi >> 16) == 0x484b) {
13642                 dev->dev_addr[0] = (hi >>  8) & 0xff;
13643                 dev->dev_addr[1] = (hi >>  0) & 0xff;
13644
13645                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13646                 dev->dev_addr[2] = (lo >> 24) & 0xff;
13647                 dev->dev_addr[3] = (lo >> 16) & 0xff;
13648                 dev->dev_addr[4] = (lo >>  8) & 0xff;
13649                 dev->dev_addr[5] = (lo >>  0) & 0xff;
13650
13651                 /* Some old bootcode may report a 0 MAC address in SRAM */
13652                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13653         }
13654         if (!addr_ok) {
13655                 /* Next, try NVRAM. */
13656                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13657                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13658                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13659                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13660                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13661                 }
13662                 /* Finally just fetch it out of the MAC control regs. */
13663                 else {
13664                         hi = tr32(MAC_ADDR_0_HIGH);
13665                         lo = tr32(MAC_ADDR_0_LOW);
13666
13667                         dev->dev_addr[5] = lo & 0xff;
13668                         dev->dev_addr[4] = (lo >> 8) & 0xff;
13669                         dev->dev_addr[3] = (lo >> 16) & 0xff;
13670                         dev->dev_addr[2] = (lo >> 24) & 0xff;
13671                         dev->dev_addr[1] = hi & 0xff;
13672                         dev->dev_addr[0] = (hi >> 8) & 0xff;
13673                 }
13674         }
13675
13676         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13677 #ifdef CONFIG_SPARC
13678                 if (!tg3_get_default_macaddr_sparc(tp))
13679                         return 0;
13680 #endif
13681                 return -EINVAL;
13682         }
13683         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13684         return 0;
13685 }
13686
13687 #define BOUNDARY_SINGLE_CACHELINE       1
13688 #define BOUNDARY_MULTI_CACHELINE        2
13689
13690 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13691 {
13692         int cacheline_size;
13693         u8 byte;
13694         int goal;
13695
13696         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13697         if (byte == 0)
13698                 cacheline_size = 1024;
13699         else
13700                 cacheline_size = (int) byte * 4;
13701
13702         /* On 5703 and later chips, the boundary bits have no
13703          * effect.
13704          */
13705         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13706             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13707             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13708                 goto out;
13709
13710 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13711         goal = BOUNDARY_MULTI_CACHELINE;
13712 #else
13713 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13714         goal = BOUNDARY_SINGLE_CACHELINE;
13715 #else
13716         goal = 0;
13717 #endif
13718 #endif
13719
13720         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
13721                 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13722                 goto out;
13723         }
13724
13725         if (!goal)
13726                 goto out;
13727
13728         /* PCI controllers on most RISC systems tend to disconnect
13729          * when a device tries to burst across a cache-line boundary.
13730          * Therefore, letting tg3 do so just wastes PCI bandwidth.
13731          *
13732          * Unfortunately, for PCI-E there are only limited
13733          * write-side controls for this, and thus for reads
13734          * we will still get the disconnects.  We'll also waste
13735          * these PCI cycles for both read and write for chips
13736          * other than 5700 and 5701 which do not implement the
13737          * boundary bits.
13738          */
13739         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13740             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13741                 switch (cacheline_size) {
13742                 case 16:
13743                 case 32:
13744                 case 64:
13745                 case 128:
13746                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13747                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13748                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13749                         } else {
13750                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13751                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13752                         }
13753                         break;
13754
13755                 case 256:
13756                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13757                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13758                         break;
13759
13760                 default:
13761                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13762                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13763                         break;
13764                 }
13765         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13766                 switch (cacheline_size) {
13767                 case 16:
13768                 case 32:
13769                 case 64:
13770                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13771                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13772                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13773                                 break;
13774                         }
13775                         /* fallthrough */
13776                 case 128:
13777                 default:
13778                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13779                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13780                         break;
13781                 }
13782         } else {
13783                 switch (cacheline_size) {
13784                 case 16:
13785                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13786                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13787                                         DMA_RWCTRL_WRITE_BNDRY_16);
13788                                 break;
13789                         }
13790                         /* fallthrough */
13791                 case 32:
13792                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13793                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13794                                         DMA_RWCTRL_WRITE_BNDRY_32);
13795                                 break;
13796                         }
13797                         /* fallthrough */
13798                 case 64:
13799                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13800                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13801                                         DMA_RWCTRL_WRITE_BNDRY_64);
13802                                 break;
13803                         }
13804                         /* fallthrough */
13805                 case 128:
13806                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13807                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13808                                         DMA_RWCTRL_WRITE_BNDRY_128);
13809                                 break;
13810                         }
13811                         /* fallthrough */
13812                 case 256:
13813                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
13814                                 DMA_RWCTRL_WRITE_BNDRY_256);
13815                         break;
13816                 case 512:
13817                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
13818                                 DMA_RWCTRL_WRITE_BNDRY_512);
13819                         break;
13820                 case 1024:
13821                 default:
13822                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13823                                 DMA_RWCTRL_WRITE_BNDRY_1024);
13824                         break;
13825                 }
13826         }
13827
13828 out:
13829         return val;
13830 }
13831
13832 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13833 {
13834         struct tg3_internal_buffer_desc test_desc;
13835         u32 sram_dma_descs;
13836         int i, ret;
13837
13838         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13839
13840         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13841         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13842         tw32(RDMAC_STATUS, 0);
13843         tw32(WDMAC_STATUS, 0);
13844
13845         tw32(BUFMGR_MODE, 0);
13846         tw32(FTQ_RESET, 0);
13847
13848         test_desc.addr_hi = ((u64) buf_dma) >> 32;
13849         test_desc.addr_lo = buf_dma & 0xffffffff;
13850         test_desc.nic_mbuf = 0x00002100;
13851         test_desc.len = size;
13852
13853         /*
13854          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13855          * the *second* time the tg3 driver was getting loaded after an
13856          * initial scan.
13857          *
13858          * Broadcom tells me:
13859          *   ...the DMA engine is connected to the GRC block and a DMA
13860          *   reset may affect the GRC block in some unpredictable way...
13861          *   The behavior of resets to individual blocks has not been tested.
13862          *
13863          * Broadcom noted the GRC reset will also reset all sub-components.
13864          */
13865         if (to_device) {
13866                 test_desc.cqid_sqid = (13 << 8) | 2;
13867
13868                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13869                 udelay(40);
13870         } else {
13871                 test_desc.cqid_sqid = (16 << 8) | 7;
13872
13873                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13874                 udelay(40);
13875         }
13876         test_desc.flags = 0x00000005;
13877
13878         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13879                 u32 val;
13880
13881                 val = *(((u32 *)&test_desc) + i);
13882                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13883                                        sram_dma_descs + (i * sizeof(u32)));
13884                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13885         }
13886         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13887
13888         if (to_device)
13889                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13890         else
13891                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13892
13893         ret = -ENODEV;
13894         for (i = 0; i < 40; i++) {
13895                 u32 val;
13896
13897                 if (to_device)
13898                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13899                 else
13900                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13901                 if ((val & 0xffff) == sram_dma_descs) {
13902                         ret = 0;
13903                         break;
13904                 }
13905
13906                 udelay(100);
13907         }
13908
13909         return ret;
13910 }
13911
13912 #define TEST_BUFFER_SIZE        0x2000
13913
13914 static int __devinit tg3_test_dma(struct tg3 *tp)
13915 {
13916         dma_addr_t buf_dma;
13917         u32 *buf, saved_dma_rwctrl;
13918         int ret = 0;
13919
13920         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13921         if (!buf) {
13922                 ret = -ENOMEM;
13923                 goto out_nofree;
13924         }
13925
13926         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13927                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13928
13929         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13930
13931         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13932                 goto out;
13933
13934         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13935                 /* DMA read watermark not used on PCIE */
13936                 tp->dma_rwctrl |= 0x00180000;
13937         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
13938                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13939                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
13940                         tp->dma_rwctrl |= 0x003f0000;
13941                 else
13942                         tp->dma_rwctrl |= 0x003f000f;
13943         } else {
13944                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13945                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13946                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
13947                         u32 read_water = 0x7;
13948
13949                         /* If the 5704 is behind the EPB bridge, we can
13950                          * do the less restrictive ONE_DMA workaround for
13951                          * better performance.
13952                          */
13953                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13954                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13955                                 tp->dma_rwctrl |= 0x8000;
13956                         else if (ccval == 0x6 || ccval == 0x7)
13957                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13958
13959                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13960                                 read_water = 4;
13961                         /* Set bit 23 to enable PCIX hw bug fix */
13962                         tp->dma_rwctrl |=
13963                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13964                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13965                                 (1 << 23);
13966                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13967                         /* 5780 always in PCIX mode */
13968                         tp->dma_rwctrl |= 0x00144000;
13969                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13970                         /* 5714 always in PCIX mode */
13971                         tp->dma_rwctrl |= 0x00148000;
13972                 } else {
13973                         tp->dma_rwctrl |= 0x001b000f;
13974                 }
13975         }
13976
13977         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13978             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13979                 tp->dma_rwctrl &= 0xfffffff0;
13980
13981         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13982             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13983                 /* Remove this if it causes problems for some boards. */
13984                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13985
13986                 /* On 5700/5701 chips, we need to set this bit.
13987                  * Otherwise the chip will issue cacheline transactions
13988                  * to streamable DMA memory with not all the byte
13989                  * enables turned on.  This is an error on several
13990                  * RISC PCI controllers, in particular sparc64.
13991                  *
13992                  * On 5703/5704 chips, this bit has been reassigned
13993                  * a different meaning.  In particular, it is used
13994                  * on those chips to enable a PCI-X workaround.
13995                  */
13996                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13997         }
13998
13999         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14000
14001 #if 0
14002         /* Unneeded, already done by tg3_get_invariants.  */
14003         tg3_switch_clocks(tp);
14004 #endif
14005
14006         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14007             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14008                 goto out;
14009
14010         /* It is best to perform DMA test with maximum write burst size
14011          * to expose the 5700/5701 write DMA bug.
14012          */
14013         saved_dma_rwctrl = tp->dma_rwctrl;
14014         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14015         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14016
14017         while (1) {
14018                 u32 *p = buf, i;
14019
14020                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14021                         p[i] = i;
14022
14023                 /* Send the buffer to the chip. */
14024                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14025                 if (ret) {
14026                         dev_err(&tp->pdev->dev,
14027                                 "%s: Buffer write failed. err = %d\n",
14028                                 __func__, ret);
14029                         break;
14030                 }
14031
14032 #if 0
14033                 /* validate data reached card RAM correctly. */
14034                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14035                         u32 val;
14036                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
14037                         if (le32_to_cpu(val) != p[i]) {
14038                                 dev_err(&tp->pdev->dev,
14039                                         "%s: Buffer corrupted on device! "
14040                                         "(%d != %d)\n", __func__, val, i);
14041                                 /* ret = -ENODEV here? */
14042                         }
14043                         p[i] = 0;
14044                 }
14045 #endif
14046                 /* Now read it back. */
14047                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14048                 if (ret) {
14049                         dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
14050                                 "err = %d\n", __func__, ret);
14051                         break;
14052                 }
14053
14054                 /* Verify it. */
14055                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14056                         if (p[i] == i)
14057                                 continue;
14058
14059                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14060                             DMA_RWCTRL_WRITE_BNDRY_16) {
14061                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14062                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14063                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14064                                 break;
14065                         } else {
14066                                 dev_err(&tp->pdev->dev,
14067                                         "%s: Buffer corrupted on read back! "
14068                                         "(%d != %d)\n", __func__, p[i], i);
14069                                 ret = -ENODEV;
14070                                 goto out;
14071                         }
14072                 }
14073
14074                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14075                         /* Success. */
14076                         ret = 0;
14077                         break;
14078                 }
14079         }
14080         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14081             DMA_RWCTRL_WRITE_BNDRY_16) {
14082                 static struct pci_device_id dma_wait_state_chipsets[] = {
14083                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14084                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14085                         { },
14086                 };
14087
14088                 /* DMA test passed without adjusting DMA boundary,
14089                  * now look for chipsets that are known to expose the
14090                  * DMA bug without failing the test.
14091                  */
14092                 if (pci_dev_present(dma_wait_state_chipsets)) {
14093                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14094                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14095                 } else {
14096                         /* Safe to use the calculated DMA boundary. */
14097                         tp->dma_rwctrl = saved_dma_rwctrl;
14098                 }
14099
14100                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14101         }
14102
14103 out:
14104         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14105 out_nofree:
14106         return ret;
14107 }
14108
14109 static void __devinit tg3_init_link_config(struct tg3 *tp)
14110 {
14111         tp->link_config.advertising =
14112                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14113                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14114                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14115                  ADVERTISED_Autoneg | ADVERTISED_MII);
14116         tp->link_config.speed = SPEED_INVALID;
14117         tp->link_config.duplex = DUPLEX_INVALID;
14118         tp->link_config.autoneg = AUTONEG_ENABLE;
14119         tp->link_config.active_speed = SPEED_INVALID;
14120         tp->link_config.active_duplex = DUPLEX_INVALID;
14121         tp->link_config.phy_is_low_power = 0;
14122         tp->link_config.orig_speed = SPEED_INVALID;
14123         tp->link_config.orig_duplex = DUPLEX_INVALID;
14124         tp->link_config.orig_autoneg = AUTONEG_INVALID;
14125 }
14126
14127 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14128 {
14129         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
14130                 tp->bufmgr_config.mbuf_read_dma_low_water =
14131                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14132                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14133                         DEFAULT_MB_MACRX_LOW_WATER_57765;
14134                 tp->bufmgr_config.mbuf_high_water =
14135                         DEFAULT_MB_HIGH_WATER_57765;
14136
14137                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14138                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14139                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14140                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14141                 tp->bufmgr_config.mbuf_high_water_jumbo =
14142                         DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14143         } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14144                 tp->bufmgr_config.mbuf_read_dma_low_water =
14145                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14146                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14147                         DEFAULT_MB_MACRX_LOW_WATER_5705;
14148                 tp->bufmgr_config.mbuf_high_water =
14149                         DEFAULT_MB_HIGH_WATER_5705;
14150                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14151                         tp->bufmgr_config.mbuf_mac_rx_low_water =
14152                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
14153                         tp->bufmgr_config.mbuf_high_water =
14154                                 DEFAULT_MB_HIGH_WATER_5906;
14155                 }
14156
14157                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14158                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14159                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14160                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14161                 tp->bufmgr_config.mbuf_high_water_jumbo =
14162                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14163         } else {
14164                 tp->bufmgr_config.mbuf_read_dma_low_water =
14165                         DEFAULT_MB_RDMA_LOW_WATER;
14166                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14167                         DEFAULT_MB_MACRX_LOW_WATER;
14168                 tp->bufmgr_config.mbuf_high_water =
14169                         DEFAULT_MB_HIGH_WATER;
14170
14171                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14172                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14173                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14174                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14175                 tp->bufmgr_config.mbuf_high_water_jumbo =
14176                         DEFAULT_MB_HIGH_WATER_JUMBO;
14177         }
14178
14179         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14180         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14181 }
14182
14183 static char * __devinit tg3_phy_string(struct tg3 *tp)
14184 {
14185         switch (tp->phy_id & TG3_PHY_ID_MASK) {
14186         case TG3_PHY_ID_BCM5400:        return "5400";
14187         case TG3_PHY_ID_BCM5401:        return "5401";
14188         case TG3_PHY_ID_BCM5411:        return "5411";
14189         case TG3_PHY_ID_BCM5701:        return "5701";
14190         case TG3_PHY_ID_BCM5703:        return "5703";
14191         case TG3_PHY_ID_BCM5704:        return "5704";
14192         case TG3_PHY_ID_BCM5705:        return "5705";
14193         case TG3_PHY_ID_BCM5750:        return "5750";
14194         case TG3_PHY_ID_BCM5752:        return "5752";
14195         case TG3_PHY_ID_BCM5714:        return "5714";
14196         case TG3_PHY_ID_BCM5780:        return "5780";
14197         case TG3_PHY_ID_BCM5755:        return "5755";
14198         case TG3_PHY_ID_BCM5787:        return "5787";
14199         case TG3_PHY_ID_BCM5784:        return "5784";
14200         case TG3_PHY_ID_BCM5756:        return "5722/5756";
14201         case TG3_PHY_ID_BCM5906:        return "5906";
14202         case TG3_PHY_ID_BCM5761:        return "5761";
14203         case TG3_PHY_ID_BCM5718C:       return "5718C";
14204         case TG3_PHY_ID_BCM5718S:       return "5718S";
14205         case TG3_PHY_ID_BCM57765:       return "57765";
14206         case TG3_PHY_ID_BCM5719C:       return "5719C";
14207         case TG3_PHY_ID_BCM8002:        return "8002/serdes";
14208         case 0:                 return "serdes";
14209         default:                return "unknown";
14210         }
14211 }
14212
14213 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14214 {
14215         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14216                 strcpy(str, "PCI Express");
14217                 return str;
14218         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14219                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14220
14221                 strcpy(str, "PCIX:");
14222
14223                 if ((clock_ctrl == 7) ||
14224                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14225                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14226                         strcat(str, "133MHz");
14227                 else if (clock_ctrl == 0)
14228                         strcat(str, "33MHz");
14229                 else if (clock_ctrl == 2)
14230                         strcat(str, "50MHz");
14231                 else if (clock_ctrl == 4)
14232                         strcat(str, "66MHz");
14233                 else if (clock_ctrl == 6)
14234                         strcat(str, "100MHz");
14235         } else {
14236                 strcpy(str, "PCI:");
14237                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14238                         strcat(str, "66MHz");
14239                 else
14240                         strcat(str, "33MHz");
14241         }
14242         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14243                 strcat(str, ":32-bit");
14244         else
14245                 strcat(str, ":64-bit");
14246         return str;
14247 }
14248
14249 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14250 {
14251         struct pci_dev *peer;
14252         unsigned int func, devnr = tp->pdev->devfn & ~7;
14253
14254         for (func = 0; func < 8; func++) {
14255                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14256                 if (peer && peer != tp->pdev)
14257                         break;
14258                 pci_dev_put(peer);
14259         }
14260         /* 5704 can be configured in single-port mode, set peer to
14261          * tp->pdev in that case.
14262          */
14263         if (!peer) {
14264                 peer = tp->pdev;
14265                 return peer;
14266         }
14267
14268         /*
14269          * We don't need to keep the refcount elevated; there's no way
14270          * to remove one half of this device without removing the other
14271          */
14272         pci_dev_put(peer);
14273
14274         return peer;
14275 }
14276
14277 static void __devinit tg3_init_coal(struct tg3 *tp)
14278 {
14279         struct ethtool_coalesce *ec = &tp->coal;
14280
14281         memset(ec, 0, sizeof(*ec));
14282         ec->cmd = ETHTOOL_GCOALESCE;
14283         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14284         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14285         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14286         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14287         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14288         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14289         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14290         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14291         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14292
14293         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14294                                  HOSTCC_MODE_CLRTICK_TXBD)) {
14295                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14296                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14297                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14298                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14299         }
14300
14301         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14302                 ec->rx_coalesce_usecs_irq = 0;
14303                 ec->tx_coalesce_usecs_irq = 0;
14304                 ec->stats_block_coalesce_usecs = 0;
14305         }
14306 }
14307
14308 static const struct net_device_ops tg3_netdev_ops = {
14309         .ndo_open               = tg3_open,
14310         .ndo_stop               = tg3_close,
14311         .ndo_start_xmit         = tg3_start_xmit,
14312         .ndo_get_stats64        = tg3_get_stats64,
14313         .ndo_validate_addr      = eth_validate_addr,
14314         .ndo_set_multicast_list = tg3_set_rx_mode,
14315         .ndo_set_mac_address    = tg3_set_mac_addr,
14316         .ndo_do_ioctl           = tg3_ioctl,
14317         .ndo_tx_timeout         = tg3_tx_timeout,
14318         .ndo_change_mtu         = tg3_change_mtu,
14319 #if TG3_VLAN_TAG_USED
14320         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14321 #endif
14322 #ifdef CONFIG_NET_POLL_CONTROLLER
14323         .ndo_poll_controller    = tg3_poll_controller,
14324 #endif
14325 };
14326
14327 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14328         .ndo_open               = tg3_open,
14329         .ndo_stop               = tg3_close,
14330         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
14331         .ndo_get_stats64        = tg3_get_stats64,
14332         .ndo_validate_addr      = eth_validate_addr,
14333         .ndo_set_multicast_list = tg3_set_rx_mode,
14334         .ndo_set_mac_address    = tg3_set_mac_addr,
14335         .ndo_do_ioctl           = tg3_ioctl,
14336         .ndo_tx_timeout         = tg3_tx_timeout,
14337         .ndo_change_mtu         = tg3_change_mtu,
14338 #if TG3_VLAN_TAG_USED
14339         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14340 #endif
14341 #ifdef CONFIG_NET_POLL_CONTROLLER
14342         .ndo_poll_controller    = tg3_poll_controller,
14343 #endif
14344 };
14345
14346 static int __devinit tg3_init_one(struct pci_dev *pdev,
14347                                   const struct pci_device_id *ent)
14348 {
14349         struct net_device *dev;
14350         struct tg3 *tp;
14351         int i, err, pm_cap;
14352         u32 sndmbx, rcvmbx, intmbx;
14353         char str[40];
14354         u64 dma_mask, persist_dma_mask;
14355
14356         printk_once(KERN_INFO "%s\n", version);
14357
14358         err = pci_enable_device(pdev);
14359         if (err) {
14360                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
14361                 return err;
14362         }
14363
14364         err = pci_request_regions(pdev, DRV_MODULE_NAME);
14365         if (err) {
14366                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
14367                 goto err_out_disable_pdev;
14368         }
14369
14370         pci_set_master(pdev);
14371
14372         /* Find power-management capability. */
14373         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14374         if (pm_cap == 0) {
14375                 dev_err(&pdev->dev,
14376                         "Cannot find Power Management capability, aborting\n");
14377                 err = -EIO;
14378                 goto err_out_free_res;
14379         }
14380
14381         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14382         if (!dev) {
14383                 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
14384                 err = -ENOMEM;
14385                 goto err_out_free_res;
14386         }
14387
14388         SET_NETDEV_DEV(dev, &pdev->dev);
14389
14390 #if TG3_VLAN_TAG_USED
14391         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14392 #endif
14393
14394         tp = netdev_priv(dev);
14395         tp->pdev = pdev;
14396         tp->dev = dev;
14397         tp->pm_cap = pm_cap;
14398         tp->rx_mode = TG3_DEF_RX_MODE;
14399         tp->tx_mode = TG3_DEF_TX_MODE;
14400
14401         if (tg3_debug > 0)
14402                 tp->msg_enable = tg3_debug;
14403         else
14404                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14405
14406         /* The word/byte swap controls here control register access byte
14407          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
14408          * setting below.
14409          */
14410         tp->misc_host_ctrl =
14411                 MISC_HOST_CTRL_MASK_PCI_INT |
14412                 MISC_HOST_CTRL_WORD_SWAP |
14413                 MISC_HOST_CTRL_INDIR_ACCESS |
14414                 MISC_HOST_CTRL_PCISTATE_RW;
14415
14416         /* The NONFRM (non-frame) byte/word swap controls take effect
14417          * on descriptor entries, anything which isn't packet data.
14418          *
14419          * The StrongARM chips on the board (one for tx, one for rx)
14420          * are running in big-endian mode.
14421          */
14422         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14423                         GRC_MODE_WSWAP_NONFRM_DATA);
14424 #ifdef __BIG_ENDIAN
14425         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14426 #endif
14427         spin_lock_init(&tp->lock);
14428         spin_lock_init(&tp->indirect_lock);
14429         INIT_WORK(&tp->reset_task, tg3_reset_task);
14430
14431         tp->regs = pci_ioremap_bar(pdev, BAR_0);
14432         if (!tp->regs) {
14433                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
14434                 err = -ENOMEM;
14435                 goto err_out_free_dev;
14436         }
14437
14438         tg3_init_link_config(tp);
14439
14440         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14441         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14442
14443         dev->ethtool_ops = &tg3_ethtool_ops;
14444         dev->watchdog_timeo = TG3_TX_TIMEOUT;
14445         dev->irq = pdev->irq;
14446
14447         err = tg3_get_invariants(tp);
14448         if (err) {
14449                 dev_err(&pdev->dev,
14450                         "Problem fetching invariants of chip, aborting\n");
14451                 goto err_out_iounmap;
14452         }
14453
14454         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14455             tp->pci_chip_rev_id != CHIPREV_ID_5717_A0 &&
14456             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
14457                 dev->netdev_ops = &tg3_netdev_ops;
14458         else
14459                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14460
14461
14462         /* The EPB bridge inside 5714, 5715, and 5780 and any
14463          * device behind the EPB cannot support DMA addresses > 40-bit.
14464          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14465          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14466          * do DMA address check in tg3_start_xmit().
14467          */
14468         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14469                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14470         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14471                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14472 #ifdef CONFIG_HIGHMEM
14473                 dma_mask = DMA_BIT_MASK(64);
14474 #endif
14475         } else
14476                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14477
14478         /* Configure DMA attributes. */
14479         if (dma_mask > DMA_BIT_MASK(32)) {
14480                 err = pci_set_dma_mask(pdev, dma_mask);
14481                 if (!err) {
14482                         dev->features |= NETIF_F_HIGHDMA;
14483                         err = pci_set_consistent_dma_mask(pdev,
14484                                                           persist_dma_mask);
14485                         if (err < 0) {
14486                                 dev_err(&pdev->dev, "Unable to obtain 64 bit "
14487                                         "DMA for consistent allocations\n");
14488                                 goto err_out_iounmap;
14489                         }
14490                 }
14491         }
14492         if (err || dma_mask == DMA_BIT_MASK(32)) {
14493                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14494                 if (err) {
14495                         dev_err(&pdev->dev,
14496                                 "No usable DMA configuration, aborting\n");
14497                         goto err_out_iounmap;
14498                 }
14499         }
14500
14501         tg3_init_bufmgr_config(tp);
14502
14503         /* Selectively allow TSO based on operating conditions */
14504         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14505             (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14506                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14507         else {
14508                 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14509                 tp->fw_needed = NULL;
14510         }
14511
14512         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14513                 tp->fw_needed = FIRMWARE_TG3;
14514
14515         /* TSO is on by default on chips that support hardware TSO.
14516          * Firmware TSO on older chips gives lower performance, so it
14517          * is off by default, but can be enabled using ethtool.
14518          */
14519         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14520             (dev->features & NETIF_F_IP_CSUM)) {
14521                 dev->features |= NETIF_F_TSO;
14522                 vlan_features_add(dev, NETIF_F_TSO);
14523         }
14524         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14525             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14526                 if (dev->features & NETIF_F_IPV6_CSUM) {
14527                         dev->features |= NETIF_F_TSO6;
14528                         vlan_features_add(dev, NETIF_F_TSO6);
14529                 }
14530                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14531                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14532                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14533                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14534                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14535                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
14536                         dev->features |= NETIF_F_TSO_ECN;
14537                         vlan_features_add(dev, NETIF_F_TSO_ECN);
14538                 }
14539         }
14540
14541         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14542             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14543             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14544                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14545                 tp->rx_pending = 63;
14546         }
14547
14548         err = tg3_get_device_address(tp);
14549         if (err) {
14550                 dev_err(&pdev->dev,
14551                         "Could not obtain valid ethernet address, aborting\n");
14552                 goto err_out_iounmap;
14553         }
14554
14555         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14556                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14557                 if (!tp->aperegs) {
14558                         dev_err(&pdev->dev,
14559                                 "Cannot map APE registers, aborting\n");
14560                         err = -ENOMEM;
14561                         goto err_out_iounmap;
14562                 }
14563
14564                 tg3_ape_lock_init(tp);
14565
14566                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14567                         tg3_read_dash_ver(tp);
14568         }
14569
14570         /*
14571          * Reset chip in case UNDI or EFI driver did not shutdown
14572          * DMA self test will enable WDMAC and we'll see (spurious)
14573          * pending DMA on the PCI bus at that point.
14574          */
14575         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14576             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14577                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14578                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14579         }
14580
14581         err = tg3_test_dma(tp);
14582         if (err) {
14583                 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
14584                 goto err_out_apeunmap;
14585         }
14586
14587         /* flow control autonegotiation is default behavior */
14588         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14589         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14590
14591         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14592         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14593         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14594         for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14595                 struct tg3_napi *tnapi = &tp->napi[i];
14596
14597                 tnapi->tp = tp;
14598                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14599
14600                 tnapi->int_mbox = intmbx;
14601                 if (i < 4)
14602                         intmbx += 0x8;
14603                 else
14604                         intmbx += 0x4;
14605
14606                 tnapi->consmbox = rcvmbx;
14607                 tnapi->prodmbox = sndmbx;
14608
14609                 if (i) {
14610                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14611                         netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14612                 } else {
14613                         tnapi->coal_now = HOSTCC_MODE_NOW;
14614                         netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14615                 }
14616
14617                 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14618                         break;
14619
14620                 /*
14621                  * If we support MSIX, we'll be using RSS.  If we're using
14622                  * RSS, the first vector only handles link interrupts and the
14623                  * remaining vectors handle rx and tx interrupts.  Reuse the
14624                  * mailbox values for the next iteration.  The values we setup
14625                  * above are still useful for the single vectored mode.
14626                  */
14627                 if (!i)
14628                         continue;
14629
14630                 rcvmbx += 0x8;
14631
14632                 if (sndmbx & 0x4)
14633                         sndmbx -= 0x4;
14634                 else
14635                         sndmbx += 0xc;
14636         }
14637
14638         tg3_init_coal(tp);
14639
14640         pci_set_drvdata(pdev, dev);
14641
14642         err = register_netdev(dev);
14643         if (err) {
14644                 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
14645                 goto err_out_apeunmap;
14646         }
14647
14648         netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14649                     tp->board_part_number,
14650                     tp->pci_chip_rev_id,
14651                     tg3_bus_string(tp, str),
14652                     dev->dev_addr);
14653
14654         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14655                 struct phy_device *phydev;
14656                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14657                 netdev_info(dev,
14658                             "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14659                             phydev->drv->name, dev_name(&phydev->dev));
14660         } else
14661                 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
14662                             "(WireSpeed[%d])\n", tg3_phy_string(tp),
14663                             ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14664                              ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14665                               "10/100/1000Base-T")),
14666                             (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14667
14668         netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14669                     (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14670                     (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14671                     (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14672                     (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14673                     (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14674         netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14675                     tp->dma_rwctrl,
14676                     pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
14677                     ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
14678
14679         return 0;
14680
14681 err_out_apeunmap:
14682         if (tp->aperegs) {
14683                 iounmap(tp->aperegs);
14684                 tp->aperegs = NULL;
14685         }
14686
14687 err_out_iounmap:
14688         if (tp->regs) {
14689                 iounmap(tp->regs);
14690                 tp->regs = NULL;
14691         }
14692
14693 err_out_free_dev:
14694         free_netdev(dev);
14695
14696 err_out_free_res:
14697         pci_release_regions(pdev);
14698
14699 err_out_disable_pdev:
14700         pci_disable_device(pdev);
14701         pci_set_drvdata(pdev, NULL);
14702         return err;
14703 }
14704
14705 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14706 {
14707         struct net_device *dev = pci_get_drvdata(pdev);
14708
14709         if (dev) {
14710                 struct tg3 *tp = netdev_priv(dev);
14711
14712                 if (tp->fw)
14713                         release_firmware(tp->fw);
14714
14715                 flush_scheduled_work();
14716
14717                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14718                         tg3_phy_fini(tp);
14719                         tg3_mdio_fini(tp);
14720                 }
14721
14722                 unregister_netdev(dev);
14723                 if (tp->aperegs) {
14724                         iounmap(tp->aperegs);
14725                         tp->aperegs = NULL;
14726                 }
14727                 if (tp->regs) {
14728                         iounmap(tp->regs);
14729                         tp->regs = NULL;
14730                 }
14731                 free_netdev(dev);
14732                 pci_release_regions(pdev);
14733                 pci_disable_device(pdev);
14734                 pci_set_drvdata(pdev, NULL);
14735         }
14736 }
14737
14738 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14739 {
14740         struct net_device *dev = pci_get_drvdata(pdev);
14741         struct tg3 *tp = netdev_priv(dev);
14742         pci_power_t target_state;
14743         int err;
14744
14745         /* PCI register 4 needs to be saved whether netif_running() or not.
14746          * MSI address and data need to be saved if using MSI and
14747          * netif_running().
14748          */
14749         pci_save_state(pdev);
14750
14751         if (!netif_running(dev))
14752                 return 0;
14753
14754         flush_scheduled_work();
14755         tg3_phy_stop(tp);
14756         tg3_netif_stop(tp);
14757
14758         del_timer_sync(&tp->timer);
14759
14760         tg3_full_lock(tp, 1);
14761         tg3_disable_ints(tp);
14762         tg3_full_unlock(tp);
14763
14764         netif_device_detach(dev);
14765
14766         tg3_full_lock(tp, 0);
14767         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14768         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14769         tg3_full_unlock(tp);
14770
14771         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14772
14773         err = tg3_set_power_state(tp, target_state);
14774         if (err) {
14775                 int err2;
14776
14777                 tg3_full_lock(tp, 0);
14778
14779                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14780                 err2 = tg3_restart_hw(tp, 1);
14781                 if (err2)
14782                         goto out;
14783
14784                 tp->timer.expires = jiffies + tp->timer_offset;
14785                 add_timer(&tp->timer);
14786
14787                 netif_device_attach(dev);
14788                 tg3_netif_start(tp);
14789
14790 out:
14791                 tg3_full_unlock(tp);
14792
14793                 if (!err2)
14794                         tg3_phy_start(tp);
14795         }
14796
14797         return err;
14798 }
14799
14800 static int tg3_resume(struct pci_dev *pdev)
14801 {
14802         struct net_device *dev = pci_get_drvdata(pdev);
14803         struct tg3 *tp = netdev_priv(dev);
14804         int err;
14805
14806         pci_restore_state(tp->pdev);
14807
14808         if (!netif_running(dev))
14809                 return 0;
14810
14811         err = tg3_set_power_state(tp, PCI_D0);
14812         if (err)
14813                 return err;
14814
14815         netif_device_attach(dev);
14816
14817         tg3_full_lock(tp, 0);
14818
14819         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14820         err = tg3_restart_hw(tp, 1);
14821         if (err)
14822                 goto out;
14823
14824         tp->timer.expires = jiffies + tp->timer_offset;
14825         add_timer(&tp->timer);
14826
14827         tg3_netif_start(tp);
14828
14829 out:
14830         tg3_full_unlock(tp);
14831
14832         if (!err)
14833                 tg3_phy_start(tp);
14834
14835         return err;
14836 }
14837
14838 static struct pci_driver tg3_driver = {
14839         .name           = DRV_MODULE_NAME,
14840         .id_table       = tg3_pci_tbl,
14841         .probe          = tg3_init_one,
14842         .remove         = __devexit_p(tg3_remove_one),
14843         .suspend        = tg3_suspend,
14844         .resume         = tg3_resume
14845 };
14846
14847 static int __init tg3_init(void)
14848 {
14849         return pci_register_driver(&tg3_driver);
14850 }
14851
14852 static void __exit tg3_cleanup(void)
14853 {
14854         pci_unregister_driver(&tg3_driver);
14855 }
14856
14857 module_init(tg3_init);
14858 module_exit(tg3_cleanup);