drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2010 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/phy.h>
  36 #include <linux/brcmphy.h>
  37 #include <linux/if_vlan.h>
  38 #include <linux/ip.h>
  39 #include <linux/tcp.h>
  40 #include <linux/workqueue.h>
  41 #include <linux/prefetch.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/firmware.h>
  44
  45 #include <net/checksum.h>
  46 #include <net/ip.h>
  47
  48 #include <asm/system.h>
  49 #include <asm/io.h>
  50 #include <asm/byteorder.h>
  51 #include <asm/uaccess.h>
  52
  53 #ifdef CONFIG_SPARC
  54 #include <asm/idprom.h>
  55 #include <asm/prom.h>
  56 #endif
  57
  58 #define BAR_0   0
  59 #define BAR_2   2
  60
  61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  62 #define TG3_VLAN_TAG_USED 1
  63 #else
  64 #define TG3_VLAN_TAG_USED 0
  65 #endif
  66
  67 #include "tg3.h"
  68
  69 #define DRV_MODULE_NAME         "tg3"
  70 #define DRV_MODULE_VERSION      "3.110"
  71 #define DRV_MODULE_RELDATE      "April 9, 2010"
  72
  73 #define TG3_DEF_MAC_MODE        0
  74 #define TG3_DEF_RX_MODE         0
  75 #define TG3_DEF_TX_MODE         0
  76 #define TG3_DEF_MSG_ENABLE        \
  77         (NETIF_MSG_DRV          | \
  78          NETIF_MSG_PROBE        | \
  79          NETIF_MSG_LINK         | \
  80          NETIF_MSG_TIMER        | \
  81          NETIF_MSG_IFDOWN       | \
  82          NETIF_MSG_IFUP         | \
  83          NETIF_MSG_RX_ERR       | \
  84          NETIF_MSG_TX_ERR)
  85
  86 /* length of time before we decide the hardware is borked,
  87  * and dev->tx_timeout() should be called to fix the problem
  88  */
  89 #define TG3_TX_TIMEOUT                  (5 * HZ)
  90
  91 /* hardware minimum and maximum for a single frame's data payload */
  92 #define TG3_MIN_MTU                     60
  93 #define TG3_MAX_MTU(tp) \
  94         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  95
  96 /* These numbers seem to be hard coded in the NIC firmware somehow.
  97  * You can't change the ring sizes, but you can change where you place
  98  * them in the NIC onboard memory.
  99  */
 100 #define TG3_RX_RING_SIZE                512
 101 #define TG3_DEF_RX_RING_PENDING         200
 102 #define TG3_RX_JUMBO_RING_SIZE          256
 103 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 104 #define TG3_RSS_INDIR_TBL_SIZE          128
 105
 106 /* Do not place this n-ring entries value into the tp struct itself,
 107  * we really want to expose these constants to GCC so that modulo et
 108  * al.  operations are done with shifts and masks instead of with
 109  * hw multiply/modulo instructions.  Another solution would be to
 110  * replace things like '% foo' with '& (foo - 1)'.
 111  */
 112 #define TG3_RX_RCB_RING_SIZE(tp)        \
 113         (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
 114           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
 115
 116 #define TG3_TX_RING_SIZE                512
 117 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 118
 119 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 120                                  TG3_RX_RING_SIZE)
 121 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
 122                                  TG3_RX_JUMBO_RING_SIZE)
 123 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 124                                  TG3_RX_RCB_RING_SIZE(tp))
 125 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 126                                  TG3_TX_RING_SIZE)
 127 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 128
 129 #define TG3_RX_DMA_ALIGN                16
 130 #define TG3_RX_HEADROOM                 ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
 131
 132 #define TG3_DMA_BYTE_ENAB               64
 133
 134 #define TG3_RX_STD_DMA_SZ               1536
 135 #define TG3_RX_JMB_DMA_SZ               9046
 136
 137 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 138
 139 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 140 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 141
 142 #define TG3_RX_STD_BUFF_RING_SIZE \
 143         (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
 144
 145 #define TG3_RX_JMB_BUFF_RING_SIZE \
 146         (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
 147
 148 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
 149  * that are at least dword aligned when used in PCIX mode.  The driver
 150  * works around this bug by double copying the packet.  This workaround
 151  * is built into the normal double copy length check for efficiency.
 152  *
 153  * However, the double copy is only necessary on those architectures
 154  * where unaligned memory accesses are inefficient.  For those architectures
 155  * where unaligned memory accesses incur little penalty, we can reintegrate
 156  * the 5701 in the normal rx path.  Doing so saves a device structure
 157  * dereference by hardcoding the double copy threshold in place.
 158  */
 159 #define TG3_RX_COPY_THRESHOLD           256
 160 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
 161         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
 162 #else
 163         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
 164 #endif
 165
 166 /* minimum number of free TX descriptors required to wake up TX process */
 167 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 168
 169 #define TG3_RAW_IP_ALIGN 2
 170
 171 /* number of ETHTOOL_GSTATS u64's */
 172 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 173
 174 #define TG3_NUM_TEST            6
 175
 176 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
 177
 178 #define FIRMWARE_TG3            "tigon/tg3.bin"
 179 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 180 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 181
 182 static char version[] __devinitdata =
 183         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
 184
 185 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 186 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 187 MODULE_LICENSE("GPL");
 188 MODULE_VERSION(DRV_MODULE_VERSION);
 189 MODULE_FIRMWARE(FIRMWARE_TG3);
 190 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 191 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 192
 193 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 194 module_param(tg3_debug, int, 0);
 195 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 196
 197 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 255         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 256         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 257         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 258         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 259         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 260         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 261         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 262         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 263         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 264         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
 265         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
 266         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
 267         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
 268         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
 269         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
 270         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
 271         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
 272         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
 273         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 274         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 275         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 276         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 277         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 278         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 279         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 280         {}
 281 };
 282
 283 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 284
 285 static const struct {
 286         const char string[ETH_GSTRING_LEN];
 287 } ethtool_stats_keys[TG3_NUM_STATS] = {
 288         { "rx_octets" },
 289         { "rx_fragments" },
 290         { "rx_ucast_packets" },
 291         { "rx_mcast_packets" },
 292         { "rx_bcast_packets" },
 293         { "rx_fcs_errors" },
 294         { "rx_align_errors" },
 295         { "rx_xon_pause_rcvd" },
 296         { "rx_xoff_pause_rcvd" },
 297         { "rx_mac_ctrl_rcvd" },
 298         { "rx_xoff_entered" },
 299         { "rx_frame_too_long_errors" },
 300         { "rx_jabbers" },
 301         { "rx_undersize_packets" },
 302         { "rx_in_length_errors" },
 303         { "rx_out_length_errors" },
 304         { "rx_64_or_less_octet_packets" },
 305         { "rx_65_to_127_octet_packets" },
 306         { "rx_128_to_255_octet_packets" },
 307         { "rx_256_to_511_octet_packets" },
 308         { "rx_512_to_1023_octet_packets" },
 309         { "rx_1024_to_1522_octet_packets" },
 310         { "rx_1523_to_2047_octet_packets" },
 311         { "rx_2048_to_4095_octet_packets" },
 312         { "rx_4096_to_8191_octet_packets" },
 313         { "rx_8192_to_9022_octet_packets" },
 314
 315         { "tx_octets" },
 316         { "tx_collisions" },
 317
 318         { "tx_xon_sent" },
 319         { "tx_xoff_sent" },
 320         { "tx_flow_control" },
 321         { "tx_mac_errors" },
 322         { "tx_single_collisions" },
 323         { "tx_mult_collisions" },
 324         { "tx_deferred" },
 325         { "tx_excessive_collisions" },
 326         { "tx_late_collisions" },
 327         { "tx_collide_2times" },
 328         { "tx_collide_3times" },
 329         { "tx_collide_4times" },
 330         { "tx_collide_5times" },
 331         { "tx_collide_6times" },
 332         { "tx_collide_7times" },
 333         { "tx_collide_8times" },
 334         { "tx_collide_9times" },
 335         { "tx_collide_10times" },
 336         { "tx_collide_11times" },
 337         { "tx_collide_12times" },
 338         { "tx_collide_13times" },
 339         { "tx_collide_14times" },
 340         { "tx_collide_15times" },
 341         { "tx_ucast_packets" },
 342         { "tx_mcast_packets" },
 343         { "tx_bcast_packets" },
 344         { "tx_carrier_sense_errors" },
 345         { "tx_discards" },
 346         { "tx_errors" },
 347
 348         { "dma_writeq_full" },
 349         { "dma_write_prioq_full" },
 350         { "rxbds_empty" },
 351         { "rx_discards" },
 352         { "rx_errors" },
 353         { "rx_threshold_hit" },
 354
 355         { "dma_readq_full" },
 356         { "dma_read_prioq_full" },
 357         { "tx_comp_queue_full" },
 358
 359         { "ring_set_send_prod_index" },
 360         { "ring_status_update" },
 361         { "nic_irqs" },
 362         { "nic_avoided_irqs" },
 363         { "nic_tx_threshold_hit" }
 364 };
 365
 366 static const struct {
 367         const char string[ETH_GSTRING_LEN];
 368 } ethtool_test_keys[TG3_NUM_TEST] = {
 369         { "nvram test     (online) " },
 370         { "link test      (online) " },
 371         { "register test  (offline)" },
 372         { "memory test    (offline)" },
 373         { "loopback test  (offline)" },
 374         { "interrupt test (offline)" },
 375 };
 376
 377 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 378 {
 379         writel(val, tp->regs + off);
 380 }
 381
 382 static u32 tg3_read32(struct tg3 *tp, u32 off)
 383 {
 384         return readl(tp->regs + off);
 385 }
 386
 387 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 388 {
 389         writel(val, tp->aperegs + off);
 390 }
 391
 392 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 393 {
 394         return readl(tp->aperegs + off);
 395 }
 396
 397 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 398 {
 399         unsigned long flags;
 400
 401         spin_lock_irqsave(&tp->indirect_lock, flags);
 402         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 403         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 404         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 405 }
 406
 407 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 408 {
 409         writel(val, tp->regs + off);
 410         readl(tp->regs + off);
 411 }
 412
 413 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 414 {
 415         unsigned long flags;
 416         u32 val;
 417
 418         spin_lock_irqsave(&tp->indirect_lock, flags);
 419         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 420         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 421         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 422         return val;
 423 }
 424
 425 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 426 {
 427         unsigned long flags;
 428
 429         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 430                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 431                                        TG3_64BIT_REG_LOW, val);
 432                 return;
 433         }
 434         if (off == TG3_RX_STD_PROD_IDX_REG) {
 435                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 436                                        TG3_64BIT_REG_LOW, val);
 437                 return;
 438         }
 439
 440         spin_lock_irqsave(&tp->indirect_lock, flags);
 441         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 442         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 443         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 444
 445         /* In indirect mode when disabling interrupts, we also need
 446          * to clear the interrupt bit in the GRC local ctrl register.
 447          */
 448         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 449             (val == 0x1)) {
 450                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 451                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 452         }
 453 }
 454
 455 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 456 {
 457         unsigned long flags;
 458         u32 val;
 459
 460         spin_lock_irqsave(&tp->indirect_lock, flags);
 461         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 462         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 463         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 464         return val;
 465 }
 466
 467 /* usec_wait specifies the wait time in usec when writing to certain registers
 468  * where it is unsafe to read back the register without some delay.
 469  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 470  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 471  */
 472 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 473 {
 474         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 475             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 476                 /* Non-posted methods */
 477                 tp->write32(tp, off, val);
 478         else {
 479                 /* Posted method */
 480                 tg3_write32(tp, off, val);
 481                 if (usec_wait)
 482                         udelay(usec_wait);
 483                 tp->read32(tp, off);
 484         }
 485         /* Wait again after the read for the posted method to guarantee that
 486          * the wait time is met.
 487          */
 488         if (usec_wait)
 489                 udelay(usec_wait);
 490 }
 491
 492 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 493 {
 494         tp->write32_mbox(tp, off, val);
 495         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 496             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 497                 tp->read32_mbox(tp, off);
 498 }
 499
 500 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 501 {
 502         void __iomem *mbox = tp->regs + off;
 503         writel(val, mbox);
 504         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 505                 writel(val, mbox);
 506         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 507                 readl(mbox);
 508 }
 509
 510 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 511 {
 512         return readl(tp->regs + off + GRCMBOX_BASE);
 513 }
 514
 515 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 516 {
 517         writel(val, tp->regs + off + GRCMBOX_BASE);
 518 }
 519
 520 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
 521 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 522 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
 523 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
 524 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
 525
 526 #define tw32(reg, val)                  tp->write32(tp, reg, val)
 527 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
 528 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
 529 #define tr32(reg)                       tp->read32(tp, reg)
 530
 531 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 532 {
 533         unsigned long flags;
 534
 535         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 536             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 537                 return;
 538
 539         spin_lock_irqsave(&tp->indirect_lock, flags);
 540         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 541                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 542                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 543
 544                 /* Always leave this as zero. */
 545                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 546         } else {
 547                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 548                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 549
 550                 /* Always leave this as zero. */
 551                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 552         }
 553         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 554 }
 555
 556 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 557 {
 558         unsigned long flags;
 559
 560         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 561             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 562                 *val = 0;
 563                 return;
 564         }
 565
 566         spin_lock_irqsave(&tp->indirect_lock, flags);
 567         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 568                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 569                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 570
 571                 /* Always leave this as zero. */
 572                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 573         } else {
 574                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 575                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 576
 577                 /* Always leave this as zero. */
 578                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 579         }
 580         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 581 }
 582
 583 static void tg3_ape_lock_init(struct tg3 *tp)
 584 {
 585         int i;
 586         u32 regbase;
 587
 588         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 589                 regbase = TG3_APE_LOCK_GRANT;
 590         else
 591                 regbase = TG3_APE_PER_LOCK_GRANT;
 592
 593         /* Make sure the driver hasn't any stale locks. */
 594         for (i = 0; i < 8; i++)
 595                 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
 596 }
 597
 598 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 599 {
 600         int i, off;
 601         int ret = 0;
 602         u32 status, req, gnt;
 603
 604         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 605                 return 0;
 606
 607         switch (locknum) {
 608         case TG3_APE_LOCK_GRC:
 609         case TG3_APE_LOCK_MEM:
 610                 break;
 611         default:
 612                 return -EINVAL;
 613         }
 614
 615         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
 616                 req = TG3_APE_LOCK_REQ;
 617                 gnt = TG3_APE_LOCK_GRANT;
 618         } else {
 619                 req = TG3_APE_PER_LOCK_REQ;
 620                 gnt = TG3_APE_PER_LOCK_GRANT;
 621         }
 622
 623         off = 4 * locknum;
 624
 625         tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
 626
 627         /* Wait for up to 1 millisecond to acquire lock. */
 628         for (i = 0; i < 100; i++) {
 629                 status = tg3_ape_read32(tp, gnt + off);
 630                 if (status == APE_LOCK_GRANT_DRIVER)
 631                         break;
 632                 udelay(10);
 633         }
 634
 635         if (status != APE_LOCK_GRANT_DRIVER) {
 636                 /* Revoke the lock request. */
 637                 tg3_ape_write32(tp, gnt + off,
 638                                 APE_LOCK_GRANT_DRIVER);
 639
 640                 ret = -EBUSY;
 641         }
 642
 643         return ret;
 644 }
 645
 646 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 647 {
 648         u32 gnt;
 649
 650         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 651                 return;
 652
 653         switch (locknum) {
 654         case TG3_APE_LOCK_GRC:
 655         case TG3_APE_LOCK_MEM:
 656                 break;
 657         default:
 658                 return;
 659         }
 660
 661         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 662                 gnt = TG3_APE_LOCK_GRANT;
 663         else
 664                 gnt = TG3_APE_PER_LOCK_GRANT;
 665
 666         tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
 667 }
 668
 669 static void tg3_disable_ints(struct tg3 *tp)
 670 {
 671         int i;
 672
 673         tw32(TG3PCI_MISC_HOST_CTRL,
 674              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 675         for (i = 0; i < tp->irq_max; i++)
 676                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 677 }
 678
 679 static void tg3_enable_ints(struct tg3 *tp)
 680 {
 681         int i;
 682
 683         tp->irq_sync = 0;
 684         wmb();
 685
 686         tw32(TG3PCI_MISC_HOST_CTRL,
 687              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 688
 689         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
 690         for (i = 0; i < tp->irq_cnt; i++) {
 691                 struct tg3_napi *tnapi = &tp->napi[i];
 692
 693                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 694                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 695                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 696
 697                 tp->coal_now |= tnapi->coal_now;
 698         }
 699
 700         /* Force an initial interrupt */
 701         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 702             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 703                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 704         else
 705                 tw32(HOSTCC_MODE, tp->coal_now);
 706
 707         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
 708 }
 709
 710 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 711 {
 712         struct tg3 *tp = tnapi->tp;
 713         struct tg3_hw_status *sblk = tnapi->hw_status;
 714         unsigned int work_exists = 0;
 715
 716         /* check for phy events */
 717         if (!(tp->tg3_flags &
 718               (TG3_FLAG_USE_LINKCHG_REG |
 719                TG3_FLAG_POLL_SERDES))) {
 720                 if (sblk->status & SD_STATUS_LINK_CHG)
 721                         work_exists = 1;
 722         }
 723         /* check for RX/TX work to do */
 724         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 725             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
 726                 work_exists = 1;
 727
 728         return work_exists;
 729 }
 730
 731 /* tg3_int_reenable
 732  *  similar to tg3_enable_ints, but it accurately determines whether there
 733  *  is new work pending and can return without flushing the PIO write
 734  *  which reenables interrupts
 735  */
 736 static void tg3_int_reenable(struct tg3_napi *tnapi)
 737 {
 738         struct tg3 *tp = tnapi->tp;
 739
 740         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 741         mmiowb();
 742
 743         /* When doing tagged status, this work check is unnecessary.
 744          * The last_tag we write above tells the chip which piece of
 745          * work we've completed.
 746          */
 747         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 748             tg3_has_work(tnapi))
 749                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 750                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 751 }
 752
 753 static void tg3_napi_disable(struct tg3 *tp)
 754 {
 755         int i;
 756
 757         for (i = tp->irq_cnt - 1; i >= 0; i--)
 758                 napi_disable(&tp->napi[i].napi);
 759 }
 760
 761 static void tg3_napi_enable(struct tg3 *tp)
 762 {
 763         int i;
 764
 765         for (i = 0; i < tp->irq_cnt; i++)
 766                 napi_enable(&tp->napi[i].napi);
 767 }
 768
 769 static inline void tg3_netif_stop(struct tg3 *tp)
 770 {
 771         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 772         tg3_napi_disable(tp);
 773         netif_tx_disable(tp->dev);
 774 }
 775
 776 static inline void tg3_netif_start(struct tg3 *tp)
 777 {
 778         /* NOTE: unconditional netif_tx_wake_all_queues is only
 779          * appropriate so long as all callers are assured to
 780          * have free tx slots (such as after tg3_init_hw)
 781          */
 782         netif_tx_wake_all_queues(tp->dev);
 783
 784         tg3_napi_enable(tp);
 785         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
 786         tg3_enable_ints(tp);
 787 }
 788
 789 static void tg3_switch_clocks(struct tg3 *tp)
 790 {
 791         u32 clock_ctrl;
 792         u32 orig_clock_ctrl;
 793
 794         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 795             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 796                 return;
 797
 798         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 799
 800         orig_clock_ctrl = clock_ctrl;
 801         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 802                        CLOCK_CTRL_CLKRUN_OENABLE |
 803                        0x1f);
 804         tp->pci_clock_ctrl = clock_ctrl;
 805
 806         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 807                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 808                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 809                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 810                 }
 811         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 812                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 813                             clock_ctrl |
 814                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 815                             40);
 816                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 817                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 818                             40);
 819         }
 820         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 821 }
 822
 823 #define PHY_BUSY_LOOPS  5000
 824
 825 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 826 {
 827         u32 frame_val;
 828         unsigned int loops;
 829         int ret;
 830
 831         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 832                 tw32_f(MAC_MI_MODE,
 833                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 834                 udelay(80);
 835         }
 836
 837         *val = 0x0;
 838
 839         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 840                       MI_COM_PHY_ADDR_MASK);
 841         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 842                       MI_COM_REG_ADDR_MASK);
 843         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 844
 845         tw32_f(MAC_MI_COM, frame_val);
 846
 847         loops = PHY_BUSY_LOOPS;
 848         while (loops != 0) {
 849                 udelay(10);
 850                 frame_val = tr32(MAC_MI_COM);
 851
 852                 if ((frame_val & MI_COM_BUSY) == 0) {
 853                         udelay(5);
 854                         frame_val = tr32(MAC_MI_COM);
 855                         break;
 856                 }
 857                 loops -= 1;
 858         }
 859
 860         ret = -EBUSY;
 861         if (loops != 0) {
 862                 *val = frame_val & MI_COM_DATA_MASK;
 863                 ret = 0;
 864         }
 865
 866         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 867                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 868                 udelay(80);
 869         }
 870
 871         return ret;
 872 }
 873
 874 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 875 {
 876         u32 frame_val;
 877         unsigned int loops;
 878         int ret;
 879
 880         if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
 881             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 882                 return 0;
 883
 884         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 885                 tw32_f(MAC_MI_MODE,
 886                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 887                 udelay(80);
 888         }
 889
 890         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 891                       MI_COM_PHY_ADDR_MASK);
 892         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 893                       MI_COM_REG_ADDR_MASK);
 894         frame_val |= (val & MI_COM_DATA_MASK);
 895         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 896
 897         tw32_f(MAC_MI_COM, frame_val);
 898
 899         loops = PHY_BUSY_LOOPS;
 900         while (loops != 0) {
 901                 udelay(10);
 902                 frame_val = tr32(MAC_MI_COM);
 903                 if ((frame_val & MI_COM_BUSY) == 0) {
 904                         udelay(5);
 905                         frame_val = tr32(MAC_MI_COM);
 906                         break;
 907                 }
 908                 loops -= 1;
 909         }
 910
 911         ret = -EBUSY;
 912         if (loops != 0)
 913                 ret = 0;
 914
 915         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 916                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 917                 udelay(80);
 918         }
 919
 920         return ret;
 921 }
 922
 923 static int tg3_bmcr_reset(struct tg3 *tp)
 924 {
 925         u32 phy_control;
 926         int limit, err;
 927
 928         /* OK, reset it, and poll the BMCR_RESET bit until it
 929          * clears or we time out.
 930          */
 931         phy_control = BMCR_RESET;
 932         err = tg3_writephy(tp, MII_BMCR, phy_control);
 933         if (err != 0)
 934                 return -EBUSY;
 935
 936         limit = 5000;
 937         while (limit--) {
 938                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 939                 if (err != 0)
 940                         return -EBUSY;
 941
 942                 if ((phy_control & BMCR_RESET) == 0) {
 943                         udelay(40);
 944                         break;
 945                 }
 946                 udelay(10);
 947         }
 948         if (limit < 0)
 949                 return -EBUSY;
 950
 951         return 0;
 952 }
 953
 954 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 955 {
 956         struct tg3 *tp = bp->priv;
 957         u32 val;
 958
 959         spin_lock_bh(&tp->lock);
 960
 961         if (tg3_readphy(tp, reg, &val))
 962                 val = -EIO;
 963
 964         spin_unlock_bh(&tp->lock);
 965
 966         return val;
 967 }
 968
 969 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 970 {
 971         struct tg3 *tp = bp->priv;
 972         u32 ret = 0;
 973
 974         spin_lock_bh(&tp->lock);
 975
 976         if (tg3_writephy(tp, reg, val))
 977                 ret = -EIO;
 978
 979         spin_unlock_bh(&tp->lock);
 980
 981         return ret;
 982 }
 983
 984 static int tg3_mdio_reset(struct mii_bus *bp)
 985 {
 986         return 0;
 987 }
 988
 989 static void tg3_mdio_config_5785(struct tg3 *tp)
 990 {
 991         u32 val;
 992         struct phy_device *phydev;
 993
 994         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
 995         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 996         case PHY_ID_BCM50610:
 997         case PHY_ID_BCM50610M:
 998                 val = MAC_PHYCFG2_50610_LED_MODES;
 999                 break;
1000         case PHY_ID_BCMAC131:
1001                 val = MAC_PHYCFG2_AC131_LED_MODES;
1002                 break;
1003         case PHY_ID_RTL8211C:
1004                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1005                 break;
1006         case PHY_ID_RTL8201E:
1007                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1008                 break;
1009         default:
1010                 return;
1011         }
1012
1013         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1014                 tw32(MAC_PHYCFG2, val);
1015
1016                 val = tr32(MAC_PHYCFG1);
1017                 val &= ~(MAC_PHYCFG1_RGMII_INT |
1018                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1019                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1020                 tw32(MAC_PHYCFG1, val);
1021
1022                 return;
1023         }
1024
1025         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
1026                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1027                        MAC_PHYCFG2_FMODE_MASK_MASK |
1028                        MAC_PHYCFG2_GMODE_MASK_MASK |
1029                        MAC_PHYCFG2_ACT_MASK_MASK   |
1030                        MAC_PHYCFG2_QUAL_MASK_MASK |
1031                        MAC_PHYCFG2_INBAND_ENABLE;
1032
1033         tw32(MAC_PHYCFG2, val);
1034
1035         val = tr32(MAC_PHYCFG1);
1036         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1037                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1038         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1039                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1040                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1041                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1042                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1043         }
1044         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1045                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1046         tw32(MAC_PHYCFG1, val);
1047
1048         val = tr32(MAC_EXT_RGMII_MODE);
1049         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1050                  MAC_RGMII_MODE_RX_QUALITY |
1051                  MAC_RGMII_MODE_RX_ACTIVITY |
1052                  MAC_RGMII_MODE_RX_ENG_DET |
1053                  MAC_RGMII_MODE_TX_ENABLE |
1054                  MAC_RGMII_MODE_TX_LOWPWR |
1055                  MAC_RGMII_MODE_TX_RESET);
1056         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1057                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1058                         val |= MAC_RGMII_MODE_RX_INT_B |
1059                                MAC_RGMII_MODE_RX_QUALITY |
1060                                MAC_RGMII_MODE_RX_ACTIVITY |
1061                                MAC_RGMII_MODE_RX_ENG_DET;
1062                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1063                         val |= MAC_RGMII_MODE_TX_ENABLE |
1064                                MAC_RGMII_MODE_TX_LOWPWR |
1065                                MAC_RGMII_MODE_TX_RESET;
1066         }
1067         tw32(MAC_EXT_RGMII_MODE, val);
1068 }
1069
1070 static void tg3_mdio_start(struct tg3 *tp)
1071 {
1072         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1073         tw32_f(MAC_MI_MODE, tp->mi_mode);
1074         udelay(80);
1075
1076         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1077             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1078                 tg3_mdio_config_5785(tp);
1079 }
1080
1081 static int tg3_mdio_init(struct tg3 *tp)
1082 {
1083         int i;
1084         u32 reg;
1085         struct phy_device *phydev;
1086
1087         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1088             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
1089                 u32 is_serdes;
1090
1091                 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1092
1093                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1094                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1095                 else
1096                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1097                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1098                 if (is_serdes)
1099                         tp->phy_addr += 7;
1100         } else
1101                 tp->phy_addr = TG3_PHY_MII_ADDR;
1102
1103         tg3_mdio_start(tp);
1104
1105         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1106             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1107                 return 0;
1108
1109         tp->mdio_bus = mdiobus_alloc();
1110         if (tp->mdio_bus == NULL)
1111                 return -ENOMEM;
1112
1113         tp->mdio_bus->name     = "tg3 mdio bus";
1114         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1115                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1116         tp->mdio_bus->priv     = tp;
1117         tp->mdio_bus->parent   = &tp->pdev->dev;
1118         tp->mdio_bus->read     = &tg3_mdio_read;
1119         tp->mdio_bus->write    = &tg3_mdio_write;
1120         tp->mdio_bus->reset    = &tg3_mdio_reset;
1121         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1122         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1123
1124         for (i = 0; i < PHY_MAX_ADDR; i++)
1125                 tp->mdio_bus->irq[i] = PHY_POLL;
1126
1127         /* The bus registration will look for all the PHYs on the mdio bus.
1128          * Unfortunately, it does not ensure the PHY is powered up before
1129          * accessing the PHY ID registers.  A chip reset is the
1130          * quickest way to bring the device back to an operational state..
1131          */
1132         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1133                 tg3_bmcr_reset(tp);
1134
1135         i = mdiobus_register(tp->mdio_bus);
1136         if (i) {
1137                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1138                 mdiobus_free(tp->mdio_bus);
1139                 return i;
1140         }
1141
1142         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1143
1144         if (!phydev || !phydev->drv) {
1145                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1146                 mdiobus_unregister(tp->mdio_bus);
1147                 mdiobus_free(tp->mdio_bus);
1148                 return -ENODEV;
1149         }
1150
1151         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1152         case PHY_ID_BCM57780:
1153                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1154                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1155                 break;
1156         case PHY_ID_BCM50610:
1157         case PHY_ID_BCM50610M:
1158                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1159                                      PHY_BRCM_RX_REFCLK_UNUSED |
1160                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1161                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1162                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1163                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1164                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1165                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1166                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1167                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1168                 /* fallthru */
1169         case PHY_ID_RTL8211C:
1170                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1171                 break;
1172         case PHY_ID_RTL8201E:
1173         case PHY_ID_BCMAC131:
1174                 phydev->interface = PHY_INTERFACE_MODE_MII;
1175                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1176                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1177                 break;
1178         }
1179
1180         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1181
1182         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1183                 tg3_mdio_config_5785(tp);
1184
1185         return 0;
1186 }
1187
1188 static void tg3_mdio_fini(struct tg3 *tp)
1189 {
1190         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1191                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1192                 mdiobus_unregister(tp->mdio_bus);
1193                 mdiobus_free(tp->mdio_bus);
1194         }
1195 }
1196
1197 /* tp->lock is held. */
1198 static inline void tg3_generate_fw_event(struct tg3 *tp)
1199 {
1200         u32 val;
1201
1202         val = tr32(GRC_RX_CPU_EVENT);
1203         val |= GRC_RX_CPU_DRIVER_EVENT;
1204         tw32_f(GRC_RX_CPU_EVENT, val);
1205
1206         tp->last_event_jiffies = jiffies;
1207 }
1208
1209 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1210
1211 /* tp->lock is held. */
1212 static void tg3_wait_for_event_ack(struct tg3 *tp)
1213 {
1214         int i;
1215         unsigned int delay_cnt;
1216         long time_remain;
1217
1218         /* If enough time has passed, no wait is necessary. */
1219         time_remain = (long)(tp->last_event_jiffies + 1 +
1220                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1221                       (long)jiffies;
1222         if (time_remain < 0)
1223                 return;
1224
1225         /* Check if we can shorten the wait time. */
1226         delay_cnt = jiffies_to_usecs(time_remain);
1227         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1228                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1229         delay_cnt = (delay_cnt >> 3) + 1;
1230
1231         for (i = 0; i < delay_cnt; i++) {
1232                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1233                         break;
1234                 udelay(8);
1235         }
1236 }
1237
1238 /* tp->lock is held. */
1239 static void tg3_ump_link_report(struct tg3 *tp)
1240 {
1241         u32 reg;
1242         u32 val;
1243
1244         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1245             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1246                 return;
1247
1248         tg3_wait_for_event_ack(tp);
1249
1250         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1251
1252         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1253
1254         val = 0;
1255         if (!tg3_readphy(tp, MII_BMCR, &reg))
1256                 val = reg << 16;
1257         if (!tg3_readphy(tp, MII_BMSR, &reg))
1258                 val |= (reg & 0xffff);
1259         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1260
1261         val = 0;
1262         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1263                 val = reg << 16;
1264         if (!tg3_readphy(tp, MII_LPA, &reg))
1265                 val |= (reg & 0xffff);
1266         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1267
1268         val = 0;
1269         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1270                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1271                         val = reg << 16;
1272                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1273                         val |= (reg & 0xffff);
1274         }
1275         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1276
1277         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1278                 val = reg << 16;
1279         else
1280                 val = 0;
1281         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1282
1283         tg3_generate_fw_event(tp);
1284 }
1285
1286 static void tg3_link_report(struct tg3 *tp)
1287 {
1288         if (!netif_carrier_ok(tp->dev)) {
1289                 netif_info(tp, link, tp->dev, "Link is down\n");
1290                 tg3_ump_link_report(tp);
1291         } else if (netif_msg_link(tp)) {
1292                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1293                             (tp->link_config.active_speed == SPEED_1000 ?
1294                              1000 :
1295                              (tp->link_config.active_speed == SPEED_100 ?
1296                               100 : 10)),
1297                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1298                              "full" : "half"));
1299
1300                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1301                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1302                             "on" : "off",
1303                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1304                             "on" : "off");
1305                 tg3_ump_link_report(tp);
1306         }
1307 }
1308
1309 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1310 {
1311         u16 miireg;
1312
1313         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1314                 miireg = ADVERTISE_PAUSE_CAP;
1315         else if (flow_ctrl & FLOW_CTRL_TX)
1316                 miireg = ADVERTISE_PAUSE_ASYM;
1317         else if (flow_ctrl & FLOW_CTRL_RX)
1318                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1319         else
1320                 miireg = 0;
1321
1322         return miireg;
1323 }
1324
1325 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1326 {
1327         u16 miireg;
1328
1329         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1330                 miireg = ADVERTISE_1000XPAUSE;
1331         else if (flow_ctrl & FLOW_CTRL_TX)
1332                 miireg = ADVERTISE_1000XPSE_ASYM;
1333         else if (flow_ctrl & FLOW_CTRL_RX)
1334                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1335         else
1336                 miireg = 0;
1337
1338         return miireg;
1339 }
1340
1341 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1342 {
1343         u8 cap = 0;
1344
1345         if (lcladv & ADVERTISE_1000XPAUSE) {
1346                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1347                         if (rmtadv & LPA_1000XPAUSE)
1348                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1349                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1350                                 cap = FLOW_CTRL_RX;
1351                 } else {
1352                         if (rmtadv & LPA_1000XPAUSE)
1353                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1354                 }
1355         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1356                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1357                         cap = FLOW_CTRL_TX;
1358         }
1359
1360         return cap;
1361 }
1362
1363 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1364 {
1365         u8 autoneg;
1366         u8 flowctrl = 0;
1367         u32 old_rx_mode = tp->rx_mode;
1368         u32 old_tx_mode = tp->tx_mode;
1369
1370         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1371                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1372         else
1373                 autoneg = tp->link_config.autoneg;
1374
1375         if (autoneg == AUTONEG_ENABLE &&
1376             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1377                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1378                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1379                 else
1380                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1381         } else
1382                 flowctrl = tp->link_config.flowctrl;
1383
1384         tp->link_config.active_flowctrl = flowctrl;
1385
1386         if (flowctrl & FLOW_CTRL_RX)
1387                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1388         else
1389                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1390
1391         if (old_rx_mode != tp->rx_mode)
1392                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1393
1394         if (flowctrl & FLOW_CTRL_TX)
1395                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1396         else
1397                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1398
1399         if (old_tx_mode != tp->tx_mode)
1400                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1401 }
1402
1403 static void tg3_adjust_link(struct net_device *dev)
1404 {
1405         u8 oldflowctrl, linkmesg = 0;
1406         u32 mac_mode, lcl_adv, rmt_adv;
1407         struct tg3 *tp = netdev_priv(dev);
1408         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1409
1410         spin_lock_bh(&tp->lock);
1411
1412         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1413                                     MAC_MODE_HALF_DUPLEX);
1414
1415         oldflowctrl = tp->link_config.active_flowctrl;
1416
1417         if (phydev->link) {
1418                 lcl_adv = 0;
1419                 rmt_adv = 0;
1420
1421                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1422                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1423                 else if (phydev->speed == SPEED_1000 ||
1424                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1425                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1426                 else
1427                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1428
1429                 if (phydev->duplex == DUPLEX_HALF)
1430                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1431                 else {
1432                         lcl_adv = tg3_advert_flowctrl_1000T(
1433                                   tp->link_config.flowctrl);
1434
1435                         if (phydev->pause)
1436                                 rmt_adv = LPA_PAUSE_CAP;
1437                         if (phydev->asym_pause)
1438                                 rmt_adv |= LPA_PAUSE_ASYM;
1439                 }
1440
1441                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1442         } else
1443                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1444
1445         if (mac_mode != tp->mac_mode) {
1446                 tp->mac_mode = mac_mode;
1447                 tw32_f(MAC_MODE, tp->mac_mode);
1448                 udelay(40);
1449         }
1450
1451         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1452                 if (phydev->speed == SPEED_10)
1453                         tw32(MAC_MI_STAT,
1454                              MAC_MI_STAT_10MBPS_MODE |
1455                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1456                 else
1457                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1458         }
1459
1460         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1461                 tw32(MAC_TX_LENGTHS,
1462                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1463                       (6 << TX_LENGTHS_IPG_SHIFT) |
1464                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1465         else
1466                 tw32(MAC_TX_LENGTHS,
1467                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1468                       (6 << TX_LENGTHS_IPG_SHIFT) |
1469                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1470
1471         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1472             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1473             phydev->speed != tp->link_config.active_speed ||
1474             phydev->duplex != tp->link_config.active_duplex ||
1475             oldflowctrl != tp->link_config.active_flowctrl)
1476                 linkmesg = 1;
1477
1478         tp->link_config.active_speed = phydev->speed;
1479         tp->link_config.active_duplex = phydev->duplex;
1480
1481         spin_unlock_bh(&tp->lock);
1482
1483         if (linkmesg)
1484                 tg3_link_report(tp);
1485 }
1486
1487 static int tg3_phy_init(struct tg3 *tp)
1488 {
1489         struct phy_device *phydev;
1490
1491         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1492                 return 0;
1493
1494         /* Bring the PHY back to a known state. */
1495         tg3_bmcr_reset(tp);
1496
1497         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1498
1499         /* Attach the MAC to the PHY. */
1500         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1501                              phydev->dev_flags, phydev->interface);
1502         if (IS_ERR(phydev)) {
1503                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1504                 return PTR_ERR(phydev);
1505         }
1506
1507         /* Mask with MAC supported features. */
1508         switch (phydev->interface) {
1509         case PHY_INTERFACE_MODE_GMII:
1510         case PHY_INTERFACE_MODE_RGMII:
1511                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1512                         phydev->supported &= (PHY_GBIT_FEATURES |
1513                                               SUPPORTED_Pause |
1514                                               SUPPORTED_Asym_Pause);
1515                         break;
1516                 }
1517                 /* fallthru */
1518         case PHY_INTERFACE_MODE_MII:
1519                 phydev->supported &= (PHY_BASIC_FEATURES |
1520                                       SUPPORTED_Pause |
1521                                       SUPPORTED_Asym_Pause);
1522                 break;
1523         default:
1524                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1525                 return -EINVAL;
1526         }
1527
1528         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1529
1530         phydev->advertising = phydev->supported;
1531
1532         return 0;
1533 }
1534
1535 static void tg3_phy_start(struct tg3 *tp)
1536 {
1537         struct phy_device *phydev;
1538
1539         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1540                 return;
1541
1542         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1543
1544         if (tp->link_config.phy_is_low_power) {
1545                 tp->link_config.phy_is_low_power = 0;
1546                 phydev->speed = tp->link_config.orig_speed;
1547                 phydev->duplex = tp->link_config.orig_duplex;
1548                 phydev->autoneg = tp->link_config.orig_autoneg;
1549                 phydev->advertising = tp->link_config.orig_advertising;
1550         }
1551
1552         phy_start(phydev);
1553
1554         phy_start_aneg(phydev);
1555 }
1556
1557 static void tg3_phy_stop(struct tg3 *tp)
1558 {
1559         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1560                 return;
1561
1562         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1563 }
1564
1565 static void tg3_phy_fini(struct tg3 *tp)
1566 {
1567         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1568                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1569                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1570         }
1571 }
1572
1573 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1574 {
1575         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1576         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1577 }
1578
1579 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1580 {
1581         u32 phytest;
1582
1583         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1584                 u32 phy;
1585
1586                 tg3_writephy(tp, MII_TG3_FET_TEST,
1587                              phytest | MII_TG3_FET_SHADOW_EN);
1588                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1589                         if (enable)
1590                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1591                         else
1592                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1593                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1594                 }
1595                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1596         }
1597 }
1598
1599 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1600 {
1601         u32 reg;
1602
1603         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1604             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1605               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1606              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1607                 return;
1608
1609         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1610                 tg3_phy_fet_toggle_apd(tp, enable);
1611                 return;
1612         }
1613
1614         reg = MII_TG3_MISC_SHDW_WREN |
1615               MII_TG3_MISC_SHDW_SCR5_SEL |
1616               MII_TG3_MISC_SHDW_SCR5_LPED |
1617               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1618               MII_TG3_MISC_SHDW_SCR5_SDTL |
1619               MII_TG3_MISC_SHDW_SCR5_C125OE;
1620         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1621                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1622
1623         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1624
1625
1626         reg = MII_TG3_MISC_SHDW_WREN |
1627               MII_TG3_MISC_SHDW_APD_SEL |
1628               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1629         if (enable)
1630                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1631
1632         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1633 }
1634
1635 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1636 {
1637         u32 phy;
1638
1639         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1640             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1641                 return;
1642
1643         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1644                 u32 ephy;
1645
1646                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1647                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1648
1649                         tg3_writephy(tp, MII_TG3_FET_TEST,
1650                                      ephy | MII_TG3_FET_SHADOW_EN);
1651                         if (!tg3_readphy(tp, reg, &phy)) {
1652                                 if (enable)
1653                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1654                                 else
1655                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1656                                 tg3_writephy(tp, reg, phy);
1657                         }
1658                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1659                 }
1660         } else {
1661                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1662                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1663                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1664                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1665                         if (enable)
1666                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1667                         else
1668                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1669                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1670                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1671                 }
1672         }
1673 }
1674
1675 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1676 {
1677         u32 val;
1678
1679         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1680                 return;
1681
1682         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1683             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1684                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1685                              (val | (1 << 15) | (1 << 4)));
1686 }
1687
1688 static void tg3_phy_apply_otp(struct tg3 *tp)
1689 {
1690         u32 otp, phy;
1691
1692         if (!tp->phy_otp)
1693                 return;
1694
1695         otp = tp->phy_otp;
1696
1697         /* Enable SM_DSP clock and tx 6dB coding. */
1698         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1699               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1700               MII_TG3_AUXCTL_ACTL_TX_6DB;
1701         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1702
1703         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1704         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1705         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1706
1707         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1708               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1709         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1710
1711         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1712         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1713         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1714
1715         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1716         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1717
1718         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1719         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1720
1721         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1722               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1723         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1724
1725         /* Turn off SM_DSP clock. */
1726         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1727               MII_TG3_AUXCTL_ACTL_TX_6DB;
1728         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1729 }
1730
1731 static int tg3_wait_macro_done(struct tg3 *tp)
1732 {
1733         int limit = 100;
1734
1735         while (limit--) {
1736                 u32 tmp32;
1737
1738                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1739                         if ((tmp32 & 0x1000) == 0)
1740                                 break;
1741                 }
1742         }
1743         if (limit < 0)
1744                 return -EBUSY;
1745
1746         return 0;
1747 }
1748
1749 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1750 {
1751         static const u32 test_pat[4][6] = {
1752         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1753         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1754         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1755         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1756         };
1757         int chan;
1758
1759         for (chan = 0; chan < 4; chan++) {
1760                 int i;
1761
1762                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1763                              (chan * 0x2000) | 0x0200);
1764                 tg3_writephy(tp, 0x16, 0x0002);
1765
1766                 for (i = 0; i < 6; i++)
1767                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1768                                      test_pat[chan][i]);
1769
1770                 tg3_writephy(tp, 0x16, 0x0202);
1771                 if (tg3_wait_macro_done(tp)) {
1772                         *resetp = 1;
1773                         return -EBUSY;
1774                 }
1775
1776                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1777                              (chan * 0x2000) | 0x0200);
1778                 tg3_writephy(tp, 0x16, 0x0082);
1779                 if (tg3_wait_macro_done(tp)) {
1780                         *resetp = 1;
1781                         return -EBUSY;
1782                 }
1783
1784                 tg3_writephy(tp, 0x16, 0x0802);
1785                 if (tg3_wait_macro_done(tp)) {
1786                         *resetp = 1;
1787                         return -EBUSY;
1788                 }
1789
1790                 for (i = 0; i < 6; i += 2) {
1791                         u32 low, high;
1792
1793                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1794                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1795                             tg3_wait_macro_done(tp)) {
1796                                 *resetp = 1;
1797                                 return -EBUSY;
1798                         }
1799                         low &= 0x7fff;
1800                         high &= 0x000f;
1801                         if (low != test_pat[chan][i] ||
1802                             high != test_pat[chan][i+1]) {
1803                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1804                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1805                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1806
1807                                 return -EBUSY;
1808                         }
1809                 }
1810         }
1811
1812         return 0;
1813 }
1814
1815 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1816 {
1817         int chan;
1818
1819         for (chan = 0; chan < 4; chan++) {
1820                 int i;
1821
1822                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1823                              (chan * 0x2000) | 0x0200);
1824                 tg3_writephy(tp, 0x16, 0x0002);
1825                 for (i = 0; i < 6; i++)
1826                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1827                 tg3_writephy(tp, 0x16, 0x0202);
1828                 if (tg3_wait_macro_done(tp))
1829                         return -EBUSY;
1830         }
1831
1832         return 0;
1833 }
1834
1835 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1836 {
1837         u32 reg32, phy9_orig;
1838         int retries, do_phy_reset, err;
1839
1840         retries = 10;
1841         do_phy_reset = 1;
1842         do {
1843                 if (do_phy_reset) {
1844                         err = tg3_bmcr_reset(tp);
1845                         if (err)
1846                                 return err;
1847                         do_phy_reset = 0;
1848                 }
1849
1850                 /* Disable transmitter and interrupt.  */
1851                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1852                         continue;
1853
1854                 reg32 |= 0x3000;
1855                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1856
1857                 /* Set full-duplex, 1000 mbps.  */
1858                 tg3_writephy(tp, MII_BMCR,
1859                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1860
1861                 /* Set to master mode.  */
1862                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1863                         continue;
1864
1865                 tg3_writephy(tp, MII_TG3_CTRL,
1866                              (MII_TG3_CTRL_AS_MASTER |
1867                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1868
1869                 /* Enable SM_DSP_CLOCK and 6dB.  */
1870                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1871
1872                 /* Block the PHY control access.  */
1873                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1874                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1875
1876                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1877                 if (!err)
1878                         break;
1879         } while (--retries);
1880
1881         err = tg3_phy_reset_chanpat(tp);
1882         if (err)
1883                 return err;
1884
1885         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1886         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1887
1888         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1889         tg3_writephy(tp, 0x16, 0x0000);
1890
1891         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1892             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1893                 /* Set Extended packet length bit for jumbo frames */
1894                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1895         } else {
1896                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1897         }
1898
1899         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1900
1901         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1902                 reg32 &= ~0x3000;
1903                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1904         } else if (!err)
1905                 err = -EBUSY;
1906
1907         return err;
1908 }
1909
1910 /* This will reset the tigon3 PHY if there is no valid
1911  * link unless the FORCE argument is non-zero.
1912  */
1913 static int tg3_phy_reset(struct tg3 *tp)
1914 {
1915         u32 cpmuctrl;
1916         u32 phy_status;
1917         int err;
1918
1919         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1920                 u32 val;
1921
1922                 val = tr32(GRC_MISC_CFG);
1923                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1924                 udelay(40);
1925         }
1926         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1927         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1928         if (err != 0)
1929                 return -EBUSY;
1930
1931         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1932                 netif_carrier_off(tp->dev);
1933                 tg3_link_report(tp);
1934         }
1935
1936         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1937             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1938             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1939                 err = tg3_phy_reset_5703_4_5(tp);
1940                 if (err)
1941                         return err;
1942                 goto out;
1943         }
1944
1945         cpmuctrl = 0;
1946         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1947             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1948                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1949                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1950                         tw32(TG3_CPMU_CTRL,
1951                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1952         }
1953
1954         err = tg3_bmcr_reset(tp);
1955         if (err)
1956                 return err;
1957
1958         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1959                 u32 phy;
1960
1961                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1962                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1963
1964                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1965         }
1966
1967         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1968             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1969                 u32 val;
1970
1971                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1972                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1973                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1974                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1975                         udelay(40);
1976                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1977                 }
1978         }
1979
1980         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1981              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1982             (tp->tg3_flags2 & TG3_FLG2_MII_SERDES))
1983                 return 0;
1984
1985         tg3_phy_apply_otp(tp);
1986
1987         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1988                 tg3_phy_toggle_apd(tp, true);
1989         else
1990                 tg3_phy_toggle_apd(tp, false);
1991
1992 out:
1993         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1994                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1995                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1996                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1997                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1998                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1999                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2000         }
2001         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
2002                 tg3_writephy(tp, 0x1c, 0x8d68);
2003                 tg3_writephy(tp, 0x1c, 0x8d68);
2004         }
2005         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
2006                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2007                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2008                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
2009                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2010                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
2011                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
2012                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
2013                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2014         } else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
2015                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2016                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2017                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
2018                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2019                         tg3_writephy(tp, MII_TG3_TEST1,
2020                                      MII_TG3_TEST1_TRIM_EN | 0x4);
2021                 } else
2022                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2023                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2024         }
2025         /* Set Extended packet length bit (bit 14) on all chips that */
2026         /* support jumbo frames */
2027         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2028                 /* Cannot do read-modify-write on 5401 */
2029                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2030         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2031                 u32 phy_reg;
2032
2033                 /* Set bit 14 with read-modify-write to preserve other bits */
2034                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2035                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
2036                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
2037         }
2038
2039         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2040          * jumbo frames transmission.
2041          */
2042         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2043                 u32 phy_reg;
2044
2045                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
2046                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2047                                      phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2048         }
2049
2050         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2051                 /* adjust output voltage */
2052                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2053         }
2054
2055         tg3_phy_toggle_automdix(tp, 1);
2056         tg3_phy_set_wirespeed(tp);
2057         return 0;
2058 }
2059
2060 static void tg3_frob_aux_power(struct tg3 *tp)
2061 {
2062         struct tg3 *tp_peer = tp;
2063
2064         /* The GPIOs do something completely different on 57765. */
2065         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2066             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2067             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2068                 return;
2069
2070         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2071             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2072             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2073                 struct net_device *dev_peer;
2074
2075                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2076                 /* remove_one() may have been run on the peer. */
2077                 if (!dev_peer)
2078                         tp_peer = tp;
2079                 else
2080                         tp_peer = netdev_priv(dev_peer);
2081         }
2082
2083         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2084             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2085             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2086             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2087                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2088                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2089                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2090                                     (GRC_LCLCTRL_GPIO_OE0 |
2091                                      GRC_LCLCTRL_GPIO_OE1 |
2092                                      GRC_LCLCTRL_GPIO_OE2 |
2093                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2094                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2095                                     100);
2096                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2097                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2098                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2099                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2100                                              GRC_LCLCTRL_GPIO_OE1 |
2101                                              GRC_LCLCTRL_GPIO_OE2 |
2102                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2103                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2104                                              tp->grc_local_ctrl;
2105                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2106
2107                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2108                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2109
2110                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2111                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2112                 } else {
2113                         u32 no_gpio2;
2114                         u32 grc_local_ctrl = 0;
2115
2116                         if (tp_peer != tp &&
2117                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2118                                 return;
2119
2120                         /* Workaround to prevent overdrawing Amps. */
2121                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2122                             ASIC_REV_5714) {
2123                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2124                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2125                                             grc_local_ctrl, 100);
2126                         }
2127
2128                         /* On 5753 and variants, GPIO2 cannot be used. */
2129                         no_gpio2 = tp->nic_sram_data_cfg &
2130                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2131
2132                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2133                                          GRC_LCLCTRL_GPIO_OE1 |
2134                                          GRC_LCLCTRL_GPIO_OE2 |
2135                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2136                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2137                         if (no_gpio2) {
2138                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2139                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2140                         }
2141                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2142                                                     grc_local_ctrl, 100);
2143
2144                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2145
2146                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2147                                                     grc_local_ctrl, 100);
2148
2149                         if (!no_gpio2) {
2150                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2151                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2152                                             grc_local_ctrl, 100);
2153                         }
2154                 }
2155         } else {
2156                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2157                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2158                         if (tp_peer != tp &&
2159                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2160                                 return;
2161
2162                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2163                                     (GRC_LCLCTRL_GPIO_OE1 |
2164                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2165
2166                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2167                                     GRC_LCLCTRL_GPIO_OE1, 100);
2168
2169                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2170                                     (GRC_LCLCTRL_GPIO_OE1 |
2171                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2172                 }
2173         }
2174 }
2175
2176 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2177 {
2178         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2179                 return 1;
2180         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2181                 if (speed != SPEED_10)
2182                         return 1;
2183         } else if (speed == SPEED_10)
2184                 return 1;
2185
2186         return 0;
2187 }
2188
2189 static int tg3_setup_phy(struct tg3 *, int);
2190
2191 #define RESET_KIND_SHUTDOWN     0
2192 #define RESET_KIND_INIT         1
2193 #define RESET_KIND_SUSPEND      2
2194
2195 static void tg3_write_sig_post_reset(struct tg3 *, int);
2196 static int tg3_halt_cpu(struct tg3 *, u32);
2197
2198 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2199 {
2200         u32 val;
2201
2202         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2203                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2204                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2205                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2206
2207                         sg_dig_ctrl |=
2208                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2209                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2210                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2211                 }
2212                 return;
2213         }
2214
2215         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2216                 tg3_bmcr_reset(tp);
2217                 val = tr32(GRC_MISC_CFG);
2218                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2219                 udelay(40);
2220                 return;
2221         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2222                 u32 phytest;
2223                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2224                         u32 phy;
2225
2226                         tg3_writephy(tp, MII_ADVERTISE, 0);
2227                         tg3_writephy(tp, MII_BMCR,
2228                                      BMCR_ANENABLE | BMCR_ANRESTART);
2229
2230                         tg3_writephy(tp, MII_TG3_FET_TEST,
2231                                      phytest | MII_TG3_FET_SHADOW_EN);
2232                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2233                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2234                                 tg3_writephy(tp,
2235                                              MII_TG3_FET_SHDW_AUXMODE4,
2236                                              phy);
2237                         }
2238                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2239                 }
2240                 return;
2241         } else if (do_low_power) {
2242                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2243                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2244
2245                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2246                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2247                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2248                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2249                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2250         }
2251
2252         /* The PHY should not be powered down on some chips because
2253          * of bugs.
2254          */
2255         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2256             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2257             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2258              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2259                 return;
2260
2261         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2262             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2263                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2264                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2265                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2266                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2267         }
2268
2269         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2270 }
2271
2272 /* tp->lock is held. */
2273 static int tg3_nvram_lock(struct tg3 *tp)
2274 {
2275         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2276                 int i;
2277
2278                 if (tp->nvram_lock_cnt == 0) {
2279                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2280                         for (i = 0; i < 8000; i++) {
2281                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2282                                         break;
2283                                 udelay(20);
2284                         }
2285                         if (i == 8000) {
2286                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2287                                 return -ENODEV;
2288                         }
2289                 }
2290                 tp->nvram_lock_cnt++;
2291         }
2292         return 0;
2293 }
2294
2295 /* tp->lock is held. */
2296 static void tg3_nvram_unlock(struct tg3 *tp)
2297 {
2298         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2299                 if (tp->nvram_lock_cnt > 0)
2300                         tp->nvram_lock_cnt--;
2301                 if (tp->nvram_lock_cnt == 0)
2302                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2303         }
2304 }
2305
2306 /* tp->lock is held. */
2307 static void tg3_enable_nvram_access(struct tg3 *tp)
2308 {
2309         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2310             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2311                 u32 nvaccess = tr32(NVRAM_ACCESS);
2312
2313                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2314         }
2315 }
2316
2317 /* tp->lock is held. */
2318 static void tg3_disable_nvram_access(struct tg3 *tp)
2319 {
2320         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2321             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2322                 u32 nvaccess = tr32(NVRAM_ACCESS);
2323
2324                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2325         }
2326 }
2327
2328 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2329                                         u32 offset, u32 *val)
2330 {
2331         u32 tmp;
2332         int i;
2333
2334         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2335                 return -EINVAL;
2336
2337         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2338                                         EEPROM_ADDR_DEVID_MASK |
2339                                         EEPROM_ADDR_READ);
2340         tw32(GRC_EEPROM_ADDR,
2341              tmp |
2342              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2343              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2344               EEPROM_ADDR_ADDR_MASK) |
2345              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2346
2347         for (i = 0; i < 1000; i++) {
2348                 tmp = tr32(GRC_EEPROM_ADDR);
2349
2350                 if (tmp & EEPROM_ADDR_COMPLETE)
2351                         break;
2352                 msleep(1);
2353         }
2354         if (!(tmp & EEPROM_ADDR_COMPLETE))
2355                 return -EBUSY;
2356
2357         tmp = tr32(GRC_EEPROM_DATA);
2358
2359         /*
2360          * The data will always be opposite the native endian
2361          * format.  Perform a blind byteswap to compensate.
2362          */
2363         *val = swab32(tmp);
2364
2365         return 0;
2366 }
2367
2368 #define NVRAM_CMD_TIMEOUT 10000
2369
2370 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2371 {
2372         int i;
2373
2374         tw32(NVRAM_CMD, nvram_cmd);
2375         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2376                 udelay(10);
2377                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2378                         udelay(10);
2379                         break;
2380                 }
2381         }
2382
2383         if (i == NVRAM_CMD_TIMEOUT)
2384                 return -EBUSY;
2385
2386         return 0;
2387 }
2388
2389 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2390 {
2391         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2392             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2393             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2394            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2395             (tp->nvram_jedecnum == JEDEC_ATMEL))
2396
2397                 addr = ((addr / tp->nvram_pagesize) <<
2398                         ATMEL_AT45DB0X1B_PAGE_POS) +
2399                        (addr % tp->nvram_pagesize);
2400
2401         return addr;
2402 }
2403
2404 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2405 {
2406         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2407             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2408             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2409            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2410             (tp->nvram_jedecnum == JEDEC_ATMEL))
2411
2412                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2413                         tp->nvram_pagesize) +
2414                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2415
2416         return addr;
2417 }
2418
2419 /* NOTE: Data read in from NVRAM is byteswapped according to
2420  * the byteswapping settings for all other register accesses.
2421  * tg3 devices are BE devices, so on a BE machine, the data
2422  * returned will be exactly as it is seen in NVRAM.  On a LE
2423  * machine, the 32-bit value will be byteswapped.
2424  */
2425 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2426 {
2427         int ret;
2428
2429         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2430                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2431
2432         offset = tg3_nvram_phys_addr(tp, offset);
2433
2434         if (offset > NVRAM_ADDR_MSK)
2435                 return -EINVAL;
2436
2437         ret = tg3_nvram_lock(tp);
2438         if (ret)
2439                 return ret;
2440
2441         tg3_enable_nvram_access(tp);
2442
2443         tw32(NVRAM_ADDR, offset);
2444         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2445                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2446
2447         if (ret == 0)
2448                 *val = tr32(NVRAM_RDDATA);
2449
2450         tg3_disable_nvram_access(tp);
2451
2452         tg3_nvram_unlock(tp);
2453
2454         return ret;
2455 }
2456
2457 /* Ensures NVRAM data is in bytestream format. */
2458 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2459 {
2460         u32 v;
2461         int res = tg3_nvram_read(tp, offset, &v);
2462         if (!res)
2463                 *val = cpu_to_be32(v);
2464         return res;
2465 }
2466
2467 /* tp->lock is held. */
2468 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2469 {
2470         u32 addr_high, addr_low;
2471         int i;
2472
2473         addr_high = ((tp->dev->dev_addr[0] << 8) |
2474                      tp->dev->dev_addr[1]);
2475         addr_low = ((tp->dev->dev_addr[2] << 24) |
2476                     (tp->dev->dev_addr[3] << 16) |
2477                     (tp->dev->dev_addr[4] <<  8) |
2478                     (tp->dev->dev_addr[5] <<  0));
2479         for (i = 0; i < 4; i++) {
2480                 if (i == 1 && skip_mac_1)
2481                         continue;
2482                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2483                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2484         }
2485
2486         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2487             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2488                 for (i = 0; i < 12; i++) {
2489                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2490                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2491                 }
2492         }
2493
2494         addr_high = (tp->dev->dev_addr[0] +
2495                      tp->dev->dev_addr[1] +
2496                      tp->dev->dev_addr[2] +
2497                      tp->dev->dev_addr[3] +
2498                      tp->dev->dev_addr[4] +
2499                      tp->dev->dev_addr[5]) &
2500                 TX_BACKOFF_SEED_MASK;
2501         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2502 }
2503
2504 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2505 {
2506         u32 misc_host_ctrl;
2507         bool device_should_wake, do_low_power;
2508
2509         /* Make sure register accesses (indirect or otherwise)
2510          * will function correctly.
2511          */
2512         pci_write_config_dword(tp->pdev,
2513                                TG3PCI_MISC_HOST_CTRL,
2514                                tp->misc_host_ctrl);
2515
2516         switch (state) {
2517         case PCI_D0:
2518                 pci_enable_wake(tp->pdev, state, false);
2519                 pci_set_power_state(tp->pdev, PCI_D0);
2520
2521                 /* Switch out of Vaux if it is a NIC */
2522                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2523                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2524
2525                 return 0;
2526
2527         case PCI_D1:
2528         case PCI_D2:
2529         case PCI_D3hot:
2530                 break;
2531
2532         default:
2533                 netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
2534                            state);
2535                 return -EINVAL;
2536         }
2537
2538         /* Restore the CLKREQ setting. */
2539         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2540                 u16 lnkctl;
2541
2542                 pci_read_config_word(tp->pdev,
2543                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2544                                      &lnkctl);
2545                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2546                 pci_write_config_word(tp->pdev,
2547                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2548                                       lnkctl);
2549         }
2550
2551         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2552         tw32(TG3PCI_MISC_HOST_CTRL,
2553              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2554
2555         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2556                              device_may_wakeup(&tp->pdev->dev) &&
2557                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2558
2559         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2560                 do_low_power = false;
2561                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2562                     !tp->link_config.phy_is_low_power) {
2563                         struct phy_device *phydev;
2564                         u32 phyid, advertising;
2565
2566                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2567
2568                         tp->link_config.phy_is_low_power = 1;
2569
2570                         tp->link_config.orig_speed = phydev->speed;
2571                         tp->link_config.orig_duplex = phydev->duplex;
2572                         tp->link_config.orig_autoneg = phydev->autoneg;
2573                         tp->link_config.orig_advertising = phydev->advertising;
2574
2575                         advertising = ADVERTISED_TP |
2576                                       ADVERTISED_Pause |
2577                                       ADVERTISED_Autoneg |
2578                                       ADVERTISED_10baseT_Half;
2579
2580                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2581                             device_should_wake) {
2582                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2583                                         advertising |=
2584                                                 ADVERTISED_100baseT_Half |
2585                                                 ADVERTISED_100baseT_Full |
2586                                                 ADVERTISED_10baseT_Full;
2587                                 else
2588                                         advertising |= ADVERTISED_10baseT_Full;
2589                         }
2590
2591                         phydev->advertising = advertising;
2592
2593                         phy_start_aneg(phydev);
2594
2595                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2596                         if (phyid != PHY_ID_BCMAC131) {
2597                                 phyid &= PHY_BCM_OUI_MASK;
2598                                 if (phyid == PHY_BCM_OUI_1 ||
2599                                     phyid == PHY_BCM_OUI_2 ||
2600                                     phyid == PHY_BCM_OUI_3)
2601                                         do_low_power = true;
2602                         }
2603                 }
2604         } else {
2605                 do_low_power = true;
2606
2607                 if (tp->link_config.phy_is_low_power == 0) {
2608                         tp->link_config.phy_is_low_power = 1;
2609                         tp->link_config.orig_speed = tp->link_config.speed;
2610                         tp->link_config.orig_duplex = tp->link_config.duplex;
2611                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2612                 }
2613
2614                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2615                         tp->link_config.speed = SPEED_10;
2616                         tp->link_config.duplex = DUPLEX_HALF;
2617                         tp->link_config.autoneg = AUTONEG_ENABLE;
2618                         tg3_setup_phy(tp, 0);
2619                 }
2620         }
2621
2622         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2623                 u32 val;
2624
2625                 val = tr32(GRC_VCPU_EXT_CTRL);
2626                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2627         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2628                 int i;
2629                 u32 val;
2630
2631                 for (i = 0; i < 200; i++) {
2632                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2633                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2634                                 break;
2635                         msleep(1);
2636                 }
2637         }
2638         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2639                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2640                                                      WOL_DRV_STATE_SHUTDOWN |
2641                                                      WOL_DRV_WOL |
2642                                                      WOL_SET_MAGIC_PKT);
2643
2644         if (device_should_wake) {
2645                 u32 mac_mode;
2646
2647                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2648                         if (do_low_power) {
2649                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2650                                 udelay(40);
2651                         }
2652
2653                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2654                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2655                         else
2656                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2657
2658                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2659                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2660                             ASIC_REV_5700) {
2661                                 u32 speed = (tp->tg3_flags &
2662                                              TG3_FLAG_WOL_SPEED_100MB) ?
2663                                              SPEED_100 : SPEED_10;
2664                                 if (tg3_5700_link_polarity(tp, speed))
2665                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2666                                 else
2667                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2668                         }
2669                 } else {
2670                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2671                 }
2672
2673                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2674                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2675
2676                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2677                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2678                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2679                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2680                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2681                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2682
2683                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2684                         mac_mode |= tp->mac_mode &
2685                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2686                         if (mac_mode & MAC_MODE_APE_TX_EN)
2687                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2688                 }
2689
2690                 tw32_f(MAC_MODE, mac_mode);
2691                 udelay(100);
2692
2693                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2694                 udelay(10);
2695         }
2696
2697         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2698             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2699              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2700                 u32 base_val;
2701
2702                 base_val = tp->pci_clock_ctrl;
2703                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2704                              CLOCK_CTRL_TXCLK_DISABLE);
2705
2706                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2707                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2708         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2709                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2710                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2711                 /* do nothing */
2712         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2713                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2714                 u32 newbits1, newbits2;
2715
2716                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2717                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2718                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2719                                     CLOCK_CTRL_TXCLK_DISABLE |
2720                                     CLOCK_CTRL_ALTCLK);
2721                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2722                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2723                         newbits1 = CLOCK_CTRL_625_CORE;
2724                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2725                 } else {
2726                         newbits1 = CLOCK_CTRL_ALTCLK;
2727                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2728                 }
2729
2730                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2731                             40);
2732
2733                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2734                             40);
2735
2736                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2737                         u32 newbits3;
2738
2739                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2740                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2741                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2742                                             CLOCK_CTRL_TXCLK_DISABLE |
2743                                             CLOCK_CTRL_44MHZ_CORE);
2744                         } else {
2745                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2746                         }
2747
2748                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2749                                     tp->pci_clock_ctrl | newbits3, 40);
2750                 }
2751         }
2752
2753         if (!(device_should_wake) &&
2754             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2755                 tg3_power_down_phy(tp, do_low_power);
2756
2757         tg3_frob_aux_power(tp);
2758
2759         /* Workaround for unstable PLL clock */
2760         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2761             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2762                 u32 val = tr32(0x7d00);
2763
2764                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2765                 tw32(0x7d00, val);
2766                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2767                         int err;
2768
2769                         err = tg3_nvram_lock(tp);
2770                         tg3_halt_cpu(tp, RX_CPU_BASE);
2771                         if (!err)
2772                                 tg3_nvram_unlock(tp);
2773                 }
2774         }
2775
2776         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2777
2778         if (device_should_wake)
2779                 pci_enable_wake(tp->pdev, state, true);
2780
2781         /* Finally, set the new power state. */
2782         pci_set_power_state(tp->pdev, state);
2783
2784         return 0;
2785 }
2786
2787 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2788 {
2789         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2790         case MII_TG3_AUX_STAT_10HALF:
2791                 *speed = SPEED_10;
2792                 *duplex = DUPLEX_HALF;
2793                 break;
2794
2795         case MII_TG3_AUX_STAT_10FULL:
2796                 *speed = SPEED_10;
2797                 *duplex = DUPLEX_FULL;
2798                 break;
2799
2800         case MII_TG3_AUX_STAT_100HALF:
2801                 *speed = SPEED_100;
2802                 *duplex = DUPLEX_HALF;
2803                 break;
2804
2805         case MII_TG3_AUX_STAT_100FULL:
2806                 *speed = SPEED_100;
2807                 *duplex = DUPLEX_FULL;
2808                 break;
2809
2810         case MII_TG3_AUX_STAT_1000HALF:
2811                 *speed = SPEED_1000;
2812                 *duplex = DUPLEX_HALF;
2813                 break;
2814
2815         case MII_TG3_AUX_STAT_1000FULL:
2816                 *speed = SPEED_1000;
2817                 *duplex = DUPLEX_FULL;
2818                 break;
2819
2820         default:
2821                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2822                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2823                                  SPEED_10;
2824                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2825                                   DUPLEX_HALF;
2826                         break;
2827                 }
2828                 *speed = SPEED_INVALID;
2829                 *duplex = DUPLEX_INVALID;
2830                 break;
2831         }
2832 }
2833
2834 static void tg3_phy_copper_begin(struct tg3 *tp)
2835 {
2836         u32 new_adv;
2837         int i;
2838
2839         if (tp->link_config.phy_is_low_power) {
2840                 /* Entering low power mode.  Disable gigabit and
2841                  * 100baseT advertisements.
2842                  */
2843                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2844
2845                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2846                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2847                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2848                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2849
2850                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2851         } else if (tp->link_config.speed == SPEED_INVALID) {
2852                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2853                         tp->link_config.advertising &=
2854                                 ~(ADVERTISED_1000baseT_Half |
2855                                   ADVERTISED_1000baseT_Full);
2856
2857                 new_adv = ADVERTISE_CSMA;
2858                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2859                         new_adv |= ADVERTISE_10HALF;
2860                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2861                         new_adv |= ADVERTISE_10FULL;
2862                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2863                         new_adv |= ADVERTISE_100HALF;
2864                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2865                         new_adv |= ADVERTISE_100FULL;
2866
2867                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2868
2869                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2870
2871                 if (tp->link_config.advertising &
2872                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2873                         new_adv = 0;
2874                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2875                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2876                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2877                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2878                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2879                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2880                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2881                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2882                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2883                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2884                 } else {
2885                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2886                 }
2887         } else {
2888                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2889                 new_adv |= ADVERTISE_CSMA;
2890
2891                 /* Asking for a specific link mode. */
2892                 if (tp->link_config.speed == SPEED_1000) {
2893                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2894
2895                         if (tp->link_config.duplex == DUPLEX_FULL)
2896                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2897                         else
2898                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2899                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2900                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2901                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2902                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2903                 } else {
2904                         if (tp->link_config.speed == SPEED_100) {
2905                                 if (tp->link_config.duplex == DUPLEX_FULL)
2906                                         new_adv |= ADVERTISE_100FULL;
2907                                 else
2908                                         new_adv |= ADVERTISE_100HALF;
2909                         } else {
2910                                 if (tp->link_config.duplex == DUPLEX_FULL)
2911                                         new_adv |= ADVERTISE_10FULL;
2912                                 else
2913                                         new_adv |= ADVERTISE_10HALF;
2914                         }
2915                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2916
2917                         new_adv = 0;
2918                 }
2919
2920                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2921         }
2922
2923         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2924             tp->link_config.speed != SPEED_INVALID) {
2925                 u32 bmcr, orig_bmcr;
2926
2927                 tp->link_config.active_speed = tp->link_config.speed;
2928                 tp->link_config.active_duplex = tp->link_config.duplex;
2929
2930                 bmcr = 0;
2931                 switch (tp->link_config.speed) {
2932                 default:
2933                 case SPEED_10:
2934                         break;
2935
2936                 case SPEED_100:
2937                         bmcr |= BMCR_SPEED100;
2938                         break;
2939
2940                 case SPEED_1000:
2941                         bmcr |= TG3_BMCR_SPEED1000;
2942                         break;
2943                 }
2944
2945                 if (tp->link_config.duplex == DUPLEX_FULL)
2946                         bmcr |= BMCR_FULLDPLX;
2947
2948                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2949                     (bmcr != orig_bmcr)) {
2950                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2951                         for (i = 0; i < 1500; i++) {
2952                                 u32 tmp;
2953
2954                                 udelay(10);
2955                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2956                                     tg3_readphy(tp, MII_BMSR, &tmp))
2957                                         continue;
2958                                 if (!(tmp & BMSR_LSTATUS)) {
2959                                         udelay(40);
2960                                         break;
2961                                 }
2962                         }
2963                         tg3_writephy(tp, MII_BMCR, bmcr);
2964                         udelay(40);
2965                 }
2966         } else {
2967                 tg3_writephy(tp, MII_BMCR,
2968                              BMCR_ANENABLE | BMCR_ANRESTART);
2969         }
2970 }
2971
2972 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2973 {
2974         int err;
2975
2976         /* Turn off tap power management. */
2977         /* Set Extended packet length bit */
2978         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2979
2980         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2981         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2982
2983         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2984         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2985
2986         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2987         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2988
2989         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2990         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2991
2992         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2993         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2994
2995         udelay(40);
2996
2997         return err;
2998 }
2999
3000 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
3001 {
3002         u32 adv_reg, all_mask = 0;
3003
3004         if (mask & ADVERTISED_10baseT_Half)
3005                 all_mask |= ADVERTISE_10HALF;
3006         if (mask & ADVERTISED_10baseT_Full)
3007                 all_mask |= ADVERTISE_10FULL;
3008         if (mask & ADVERTISED_100baseT_Half)
3009                 all_mask |= ADVERTISE_100HALF;
3010         if (mask & ADVERTISED_100baseT_Full)
3011                 all_mask |= ADVERTISE_100FULL;
3012
3013         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3014                 return 0;
3015
3016         if ((adv_reg & all_mask) != all_mask)
3017                 return 0;
3018         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
3019                 u32 tg3_ctrl;
3020
3021                 all_mask = 0;
3022                 if (mask & ADVERTISED_1000baseT_Half)
3023                         all_mask |= ADVERTISE_1000HALF;
3024                 if (mask & ADVERTISED_1000baseT_Full)
3025                         all_mask |= ADVERTISE_1000FULL;
3026
3027                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3028                         return 0;
3029
3030                 if ((tg3_ctrl & all_mask) != all_mask)
3031                         return 0;
3032         }
3033         return 1;
3034 }
3035
3036 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3037 {
3038         u32 curadv, reqadv;
3039
3040         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3041                 return 1;
3042
3043         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3044         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3045
3046         if (tp->link_config.active_duplex == DUPLEX_FULL) {
3047                 if (curadv != reqadv)
3048                         return 0;
3049
3050                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3051                         tg3_readphy(tp, MII_LPA, rmtadv);
3052         } else {
3053                 /* Reprogram the advertisement register, even if it
3054                  * does not affect the current link.  If the link
3055                  * gets renegotiated in the future, we can save an
3056                  * additional renegotiation cycle by advertising
3057                  * it correctly in the first place.
3058                  */
3059                 if (curadv != reqadv) {
3060                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3061                                      ADVERTISE_PAUSE_ASYM);
3062                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3063                 }
3064         }
3065
3066         return 1;
3067 }
3068
3069 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3070 {
3071         int current_link_up;
3072         u32 bmsr, dummy;
3073         u32 lcl_adv, rmt_adv;
3074         u16 current_speed;
3075         u8 current_duplex;
3076         int i, err;
3077
3078         tw32(MAC_EVENT, 0);
3079
3080         tw32_f(MAC_STATUS,
3081              (MAC_STATUS_SYNC_CHANGED |
3082               MAC_STATUS_CFG_CHANGED |
3083               MAC_STATUS_MI_COMPLETION |
3084               MAC_STATUS_LNKSTATE_CHANGED));
3085         udelay(40);
3086
3087         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3088                 tw32_f(MAC_MI_MODE,
3089                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3090                 udelay(80);
3091         }
3092
3093         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3094
3095         /* Some third-party PHYs need to be reset on link going
3096          * down.
3097          */
3098         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3099              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3100              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3101             netif_carrier_ok(tp->dev)) {
3102                 tg3_readphy(tp, MII_BMSR, &bmsr);
3103                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3104                     !(bmsr & BMSR_LSTATUS))
3105                         force_reset = 1;
3106         }
3107         if (force_reset)
3108                 tg3_phy_reset(tp);
3109
3110         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3111                 tg3_readphy(tp, MII_BMSR, &bmsr);
3112                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3113                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3114                         bmsr = 0;
3115
3116                 if (!(bmsr & BMSR_LSTATUS)) {
3117                         err = tg3_init_5401phy_dsp(tp);
3118                         if (err)
3119                                 return err;
3120
3121                         tg3_readphy(tp, MII_BMSR, &bmsr);
3122                         for (i = 0; i < 1000; i++) {
3123                                 udelay(10);
3124                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3125                                     (bmsr & BMSR_LSTATUS)) {
3126                                         udelay(40);
3127                                         break;
3128                                 }
3129                         }
3130
3131                         if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3132                             TG3_PHY_REV_BCM5401_B0 &&
3133                             !(bmsr & BMSR_LSTATUS) &&
3134                             tp->link_config.active_speed == SPEED_1000) {
3135                                 err = tg3_phy_reset(tp);
3136                                 if (!err)
3137                                         err = tg3_init_5401phy_dsp(tp);
3138                                 if (err)
3139                                         return err;
3140                         }
3141                 }
3142         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3143                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3144                 /* 5701 {A0,B0} CRC bug workaround */
3145                 tg3_writephy(tp, 0x15, 0x0a75);
3146                 tg3_writephy(tp, 0x1c, 0x8c68);
3147                 tg3_writephy(tp, 0x1c, 0x8d68);
3148                 tg3_writephy(tp, 0x1c, 0x8c68);
3149         }
3150
3151         /* Clear pending interrupts... */
3152         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3153         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3154
3155         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3156                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3157         else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3158                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3159
3160         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3161             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3162                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3163                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3164                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3165                 else
3166                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3167         }
3168
3169         current_link_up = 0;
3170         current_speed = SPEED_INVALID;
3171         current_duplex = DUPLEX_INVALID;
3172
3173         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3174                 u32 val;
3175
3176                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3177                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3178                 if (!(val & (1 << 10))) {
3179                         val |= (1 << 10);
3180                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3181                         goto relink;
3182                 }
3183         }
3184
3185         bmsr = 0;
3186         for (i = 0; i < 100; i++) {
3187                 tg3_readphy(tp, MII_BMSR, &bmsr);
3188                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3189                     (bmsr & BMSR_LSTATUS))
3190                         break;
3191                 udelay(40);
3192         }
3193
3194         if (bmsr & BMSR_LSTATUS) {
3195                 u32 aux_stat, bmcr;
3196
3197                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3198                 for (i = 0; i < 2000; i++) {
3199                         udelay(10);
3200                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3201                             aux_stat)
3202                                 break;
3203                 }
3204
3205                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3206                                              &current_speed,
3207                                              &current_duplex);
3208
3209                 bmcr = 0;
3210                 for (i = 0; i < 200; i++) {
3211                         tg3_readphy(tp, MII_BMCR, &bmcr);
3212                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3213                                 continue;
3214                         if (bmcr && bmcr != 0x7fff)
3215                                 break;
3216                         udelay(10);
3217                 }
3218
3219                 lcl_adv = 0;
3220                 rmt_adv = 0;
3221
3222                 tp->link_config.active_speed = current_speed;
3223                 tp->link_config.active_duplex = current_duplex;
3224
3225                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3226                         if ((bmcr & BMCR_ANENABLE) &&
3227                             tg3_copper_is_advertising_all(tp,
3228                                                 tp->link_config.advertising)) {
3229                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3230                                                                   &rmt_adv))
3231                                         current_link_up = 1;
3232                         }
3233                 } else {
3234                         if (!(bmcr & BMCR_ANENABLE) &&
3235                             tp->link_config.speed == current_speed &&
3236                             tp->link_config.duplex == current_duplex &&
3237                             tp->link_config.flowctrl ==
3238                             tp->link_config.active_flowctrl) {
3239                                 current_link_up = 1;
3240                         }
3241                 }
3242
3243                 if (current_link_up == 1 &&
3244                     tp->link_config.active_duplex == DUPLEX_FULL)
3245                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3246         }
3247
3248 relink:
3249         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3250                 u32 tmp;
3251
3252                 tg3_phy_copper_begin(tp);
3253
3254                 tg3_readphy(tp, MII_BMSR, &tmp);
3255                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3256                     (tmp & BMSR_LSTATUS))
3257                         current_link_up = 1;
3258         }
3259
3260         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3261         if (current_link_up == 1) {
3262                 if (tp->link_config.active_speed == SPEED_100 ||
3263                     tp->link_config.active_speed == SPEED_10)
3264                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3265                 else
3266                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3267         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3268                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3269         else
3270                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3271
3272         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3273         if (tp->link_config.active_duplex == DUPLEX_HALF)
3274                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3275
3276         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3277                 if (current_link_up == 1 &&
3278                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3279                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3280                 else
3281                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3282         }
3283
3284         /* ??? Without this setting Netgear GA302T PHY does not
3285          * ??? send/receive packets...
3286          */
3287         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3288             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3289                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3290                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3291                 udelay(80);
3292         }
3293
3294         tw32_f(MAC_MODE, tp->mac_mode);
3295         udelay(40);
3296
3297         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3298                 /* Polled via timer. */
3299                 tw32_f(MAC_EVENT, 0);
3300         } else {
3301                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3302         }
3303         udelay(40);
3304
3305         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3306             current_link_up == 1 &&
3307             tp->link_config.active_speed == SPEED_1000 &&
3308             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3309              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3310                 udelay(120);
3311                 tw32_f(MAC_STATUS,
3312                      (MAC_STATUS_SYNC_CHANGED |
3313                       MAC_STATUS_CFG_CHANGED));
3314                 udelay(40);
3315                 tg3_write_mem(tp,
3316                               NIC_SRAM_FIRMWARE_MBOX,
3317                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3318         }
3319
3320         /* Prevent send BD corruption. */
3321         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3322                 u16 oldlnkctl, newlnkctl;
3323
3324                 pci_read_config_word(tp->pdev,
3325                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3326                                      &oldlnkctl);
3327                 if (tp->link_config.active_speed == SPEED_100 ||
3328                     tp->link_config.active_speed == SPEED_10)
3329                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3330                 else
3331                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3332                 if (newlnkctl != oldlnkctl)
3333                         pci_write_config_word(tp->pdev,
3334                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3335                                               newlnkctl);
3336         }
3337
3338         if (current_link_up != netif_carrier_ok(tp->dev)) {
3339                 if (current_link_up)
3340                         netif_carrier_on(tp->dev);
3341                 else
3342                         netif_carrier_off(tp->dev);
3343                 tg3_link_report(tp);
3344         }
3345
3346         return 0;
3347 }
3348
3349 struct tg3_fiber_aneginfo {
3350         int state;
3351 #define ANEG_STATE_UNKNOWN              0
3352 #define ANEG_STATE_AN_ENABLE            1
3353 #define ANEG_STATE_RESTART_INIT         2
3354 #define ANEG_STATE_RESTART              3
3355 #define ANEG_STATE_DISABLE_LINK_OK      4
3356 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3357 #define ANEG_STATE_ABILITY_DETECT       6
3358 #define ANEG_STATE_ACK_DETECT_INIT      7
3359 #define ANEG_STATE_ACK_DETECT           8
3360 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3361 #define ANEG_STATE_COMPLETE_ACK         10
3362 #define ANEG_STATE_IDLE_DETECT_INIT     11
3363 #define ANEG_STATE_IDLE_DETECT          12
3364 #define ANEG_STATE_LINK_OK              13
3365 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3366 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3367
3368         u32 flags;
3369 #define MR_AN_ENABLE            0x00000001
3370 #define MR_RESTART_AN           0x00000002
3371 #define MR_AN_COMPLETE          0x00000004
3372 #define MR_PAGE_RX              0x00000008
3373 #define MR_NP_LOADED            0x00000010
3374 #define MR_TOGGLE_TX            0x00000020
3375 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3376 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3377 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3378 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3379 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3380 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3381 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3382 #define MR_TOGGLE_RX            0x00002000
3383 #define MR_NP_RX                0x00004000
3384
3385 #define MR_LINK_OK              0x80000000
3386
3387         unsigned long link_time, cur_time;
3388
3389         u32 ability_match_cfg;
3390         int ability_match_count;
3391
3392         char ability_match, idle_match, ack_match;
3393
3394         u32 txconfig, rxconfig;
3395 #define ANEG_CFG_NP             0x00000080
3396 #define ANEG_CFG_ACK            0x00000040
3397 #define ANEG_CFG_RF2            0x00000020
3398 #define ANEG_CFG_RF1            0x00000010
3399 #define ANEG_CFG_PS2            0x00000001
3400 #define ANEG_CFG_PS1            0x00008000
3401 #define ANEG_CFG_HD             0x00004000
3402 #define ANEG_CFG_FD             0x00002000
3403 #define ANEG_CFG_INVAL          0x00001f06
3404
3405 };
3406 #define ANEG_OK         0
3407 #define ANEG_DONE       1
3408 #define ANEG_TIMER_ENAB 2
3409 #define ANEG_FAILED     -1
3410
3411 #define ANEG_STATE_SETTLE_TIME  10000
3412
3413 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3414                                    struct tg3_fiber_aneginfo *ap)
3415 {
3416         u16 flowctrl;
3417         unsigned long delta;
3418         u32 rx_cfg_reg;
3419         int ret;
3420
3421         if (ap->state == ANEG_STATE_UNKNOWN) {
3422                 ap->rxconfig = 0;
3423                 ap->link_time = 0;
3424                 ap->cur_time = 0;
3425                 ap->ability_match_cfg = 0;
3426                 ap->ability_match_count = 0;
3427                 ap->ability_match = 0;
3428                 ap->idle_match = 0;
3429                 ap->ack_match = 0;
3430         }
3431         ap->cur_time++;
3432
3433         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3434                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3435
3436                 if (rx_cfg_reg != ap->ability_match_cfg) {
3437                         ap->ability_match_cfg = rx_cfg_reg;
3438                         ap->ability_match = 0;
3439                         ap->ability_match_count = 0;
3440                 } else {
3441                         if (++ap->ability_match_count > 1) {
3442                                 ap->ability_match = 1;
3443                                 ap->ability_match_cfg = rx_cfg_reg;
3444                         }
3445                 }
3446                 if (rx_cfg_reg & ANEG_CFG_ACK)
3447                         ap->ack_match = 1;
3448                 else
3449                         ap->ack_match = 0;
3450
3451                 ap->idle_match = 0;
3452         } else {
3453                 ap->idle_match = 1;
3454                 ap->ability_match_cfg = 0;
3455                 ap->ability_match_count = 0;
3456                 ap->ability_match = 0;
3457                 ap->ack_match = 0;
3458
3459                 rx_cfg_reg = 0;
3460         }
3461
3462         ap->rxconfig = rx_cfg_reg;
3463         ret = ANEG_OK;
3464
3465         switch (ap->state) {
3466         case ANEG_STATE_UNKNOWN:
3467                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3468                         ap->state = ANEG_STATE_AN_ENABLE;
3469
3470                 /* fallthru */
3471         case ANEG_STATE_AN_ENABLE:
3472                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3473                 if (ap->flags & MR_AN_ENABLE) {
3474                         ap->link_time = 0;
3475                         ap->cur_time = 0;
3476                         ap->ability_match_cfg = 0;
3477                         ap->ability_match_count = 0;
3478                         ap->ability_match = 0;
3479                         ap->idle_match = 0;
3480                         ap->ack_match = 0;
3481
3482                         ap->state = ANEG_STATE_RESTART_INIT;
3483                 } else {
3484                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3485                 }
3486                 break;
3487
3488         case ANEG_STATE_RESTART_INIT:
3489                 ap->link_time = ap->cur_time;
3490                 ap->flags &= ~(MR_NP_LOADED);
3491                 ap->txconfig = 0;
3492                 tw32(MAC_TX_AUTO_NEG, 0);
3493                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3494                 tw32_f(MAC_MODE, tp->mac_mode);
3495                 udelay(40);
3496
3497                 ret = ANEG_TIMER_ENAB;
3498                 ap->state = ANEG_STATE_RESTART;
3499
3500                 /* fallthru */
3501         case ANEG_STATE_RESTART:
3502                 delta = ap->cur_time - ap->link_time;
3503                 if (delta > ANEG_STATE_SETTLE_TIME)
3504                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3505                 else
3506                         ret = ANEG_TIMER_ENAB;
3507                 break;
3508
3509         case ANEG_STATE_DISABLE_LINK_OK:
3510                 ret = ANEG_DONE;
3511                 break;
3512
3513         case ANEG_STATE_ABILITY_DETECT_INIT:
3514                 ap->flags &= ~(MR_TOGGLE_TX);
3515                 ap->txconfig = ANEG_CFG_FD;
3516                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3517                 if (flowctrl & ADVERTISE_1000XPAUSE)
3518                         ap->txconfig |= ANEG_CFG_PS1;
3519                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3520                         ap->txconfig |= ANEG_CFG_PS2;
3521                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3522                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3523                 tw32_f(MAC_MODE, tp->mac_mode);
3524                 udelay(40);
3525
3526                 ap->state = ANEG_STATE_ABILITY_DETECT;
3527                 break;
3528
3529         case ANEG_STATE_ABILITY_DETECT:
3530                 if (ap->ability_match != 0 && ap->rxconfig != 0)
3531                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3532                 break;
3533
3534         case ANEG_STATE_ACK_DETECT_INIT:
3535                 ap->txconfig |= ANEG_CFG_ACK;
3536                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3537                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3538                 tw32_f(MAC_MODE, tp->mac_mode);
3539                 udelay(40);
3540
3541                 ap->state = ANEG_STATE_ACK_DETECT;
3542
3543                 /* fallthru */
3544         case ANEG_STATE_ACK_DETECT:
3545                 if (ap->ack_match != 0) {
3546                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3547                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3548                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3549                         } else {
3550                                 ap->state = ANEG_STATE_AN_ENABLE;
3551                         }
3552                 } else if (ap->ability_match != 0 &&
3553                            ap->rxconfig == 0) {
3554                         ap->state = ANEG_STATE_AN_ENABLE;
3555                 }
3556                 break;
3557
3558         case ANEG_STATE_COMPLETE_ACK_INIT:
3559                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3560                         ret = ANEG_FAILED;
3561                         break;
3562                 }
3563                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3564                                MR_LP_ADV_HALF_DUPLEX |
3565                                MR_LP_ADV_SYM_PAUSE |
3566                                MR_LP_ADV_ASYM_PAUSE |
3567                                MR_LP_ADV_REMOTE_FAULT1 |
3568                                MR_LP_ADV_REMOTE_FAULT2 |
3569                                MR_LP_ADV_NEXT_PAGE |
3570                                MR_TOGGLE_RX |
3571                                MR_NP_RX);
3572                 if (ap->rxconfig & ANEG_CFG_FD)
3573                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3574                 if (ap->rxconfig & ANEG_CFG_HD)
3575                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3576                 if (ap->rxconfig & ANEG_CFG_PS1)
3577                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3578                 if (ap->rxconfig & ANEG_CFG_PS2)
3579                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3580                 if (ap->rxconfig & ANEG_CFG_RF1)
3581                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3582                 if (ap->rxconfig & ANEG_CFG_RF2)
3583                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3584                 if (ap->rxconfig & ANEG_CFG_NP)
3585                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3586
3587                 ap->link_time = ap->cur_time;
3588
3589                 ap->flags ^= (MR_TOGGLE_TX);
3590                 if (ap->rxconfig & 0x0008)
3591                         ap->flags |= MR_TOGGLE_RX;
3592                 if (ap->rxconfig & ANEG_CFG_NP)
3593                         ap->flags |= MR_NP_RX;
3594                 ap->flags |= MR_PAGE_RX;
3595
3596                 ap->state = ANEG_STATE_COMPLETE_ACK;
3597                 ret = ANEG_TIMER_ENAB;
3598                 break;
3599
3600         case ANEG_STATE_COMPLETE_ACK:
3601                 if (ap->ability_match != 0 &&
3602                     ap->rxconfig == 0) {
3603                         ap->state = ANEG_STATE_AN_ENABLE;
3604                         break;
3605                 }
3606                 delta = ap->cur_time - ap->link_time;
3607                 if (delta > ANEG_STATE_SETTLE_TIME) {
3608                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3609                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3610                         } else {
3611                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3612                                     !(ap->flags & MR_NP_RX)) {
3613                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3614                                 } else {
3615                                         ret = ANEG_FAILED;
3616                                 }
3617                         }
3618                 }
3619                 break;
3620
3621         case ANEG_STATE_IDLE_DETECT_INIT:
3622                 ap->link_time = ap->cur_time;
3623                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3624                 tw32_f(MAC_MODE, tp->mac_mode);
3625                 udelay(40);
3626
3627                 ap->state = ANEG_STATE_IDLE_DETECT;
3628                 ret = ANEG_TIMER_ENAB;
3629                 break;
3630
3631         case ANEG_STATE_IDLE_DETECT:
3632                 if (ap->ability_match != 0 &&
3633                     ap->rxconfig == 0) {
3634                         ap->state = ANEG_STATE_AN_ENABLE;
3635                         break;
3636                 }
3637                 delta = ap->cur_time - ap->link_time;
3638                 if (delta > ANEG_STATE_SETTLE_TIME) {
3639                         /* XXX another gem from the Broadcom driver :( */
3640                         ap->state = ANEG_STATE_LINK_OK;
3641                 }
3642                 break;
3643
3644         case ANEG_STATE_LINK_OK:
3645                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3646                 ret = ANEG_DONE;
3647                 break;
3648
3649         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3650                 /* ??? unimplemented */
3651                 break;
3652
3653         case ANEG_STATE_NEXT_PAGE_WAIT:
3654                 /* ??? unimplemented */
3655                 break;
3656
3657         default:
3658                 ret = ANEG_FAILED;
3659                 break;
3660         }
3661
3662         return ret;
3663 }
3664
3665 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3666 {
3667         int res = 0;
3668         struct tg3_fiber_aneginfo aninfo;
3669         int status = ANEG_FAILED;
3670         unsigned int tick;
3671         u32 tmp;
3672
3673         tw32_f(MAC_TX_AUTO_NEG, 0);
3674
3675         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3676         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3677         udelay(40);
3678
3679         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3680         udelay(40);
3681
3682         memset(&aninfo, 0, sizeof(aninfo));
3683         aninfo.flags |= MR_AN_ENABLE;
3684         aninfo.state = ANEG_STATE_UNKNOWN;
3685         aninfo.cur_time = 0;
3686         tick = 0;
3687         while (++tick < 195000) {
3688                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3689                 if (status == ANEG_DONE || status == ANEG_FAILED)
3690                         break;
3691
3692                 udelay(1);
3693         }
3694
3695         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3696         tw32_f(MAC_MODE, tp->mac_mode);
3697         udelay(40);
3698
3699         *txflags = aninfo.txconfig;
3700         *rxflags = aninfo.flags;
3701
3702         if (status == ANEG_DONE &&
3703             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3704                              MR_LP_ADV_FULL_DUPLEX)))
3705                 res = 1;
3706
3707         return res;
3708 }
3709
3710 static void tg3_init_bcm8002(struct tg3 *tp)
3711 {
3712         u32 mac_status = tr32(MAC_STATUS);
3713         int i;
3714
3715         /* Reset when initting first time or we have a link. */
3716         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3717             !(mac_status & MAC_STATUS_PCS_SYNCED))
3718                 return;
3719
3720         /* Set PLL lock range. */
3721         tg3_writephy(tp, 0x16, 0x8007);
3722
3723         /* SW reset */
3724         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3725
3726         /* Wait for reset to complete. */
3727         /* XXX schedule_timeout() ... */
3728         for (i = 0; i < 500; i++)
3729                 udelay(10);
3730
3731         /* Config mode; select PMA/Ch 1 regs. */
3732         tg3_writephy(tp, 0x10, 0x8411);
3733
3734         /* Enable auto-lock and comdet, select txclk for tx. */
3735         tg3_writephy(tp, 0x11, 0x0a10);
3736
3737         tg3_writephy(tp, 0x18, 0x00a0);
3738         tg3_writephy(tp, 0x16, 0x41ff);
3739
3740         /* Assert and deassert POR. */
3741         tg3_writephy(tp, 0x13, 0x0400);
3742         udelay(40);
3743         tg3_writephy(tp, 0x13, 0x0000);
3744
3745         tg3_writephy(tp, 0x11, 0x0a50);
3746         udelay(40);
3747         tg3_writephy(tp, 0x11, 0x0a10);
3748
3749         /* Wait for signal to stabilize */
3750         /* XXX schedule_timeout() ... */
3751         for (i = 0; i < 15000; i++)
3752                 udelay(10);
3753
3754         /* Deselect the channel register so we can read the PHYID
3755          * later.
3756          */
3757         tg3_writephy(tp, 0x10, 0x8011);
3758 }
3759
3760 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3761 {
3762         u16 flowctrl;
3763         u32 sg_dig_ctrl, sg_dig_status;
3764         u32 serdes_cfg, expected_sg_dig_ctrl;
3765         int workaround, port_a;
3766         int current_link_up;
3767
3768         serdes_cfg = 0;
3769         expected_sg_dig_ctrl = 0;
3770         workaround = 0;
3771         port_a = 1;
3772         current_link_up = 0;
3773
3774         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3775             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3776                 workaround = 1;
3777                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3778                         port_a = 0;
3779
3780                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3781                 /* preserve bits 20-23 for voltage regulator */
3782                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3783         }
3784
3785         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3786
3787         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3788                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3789                         if (workaround) {
3790                                 u32 val = serdes_cfg;
3791
3792                                 if (port_a)
3793                                         val |= 0xc010000;
3794                                 else
3795                                         val |= 0x4010000;
3796                                 tw32_f(MAC_SERDES_CFG, val);
3797                         }
3798
3799                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3800                 }
3801                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3802                         tg3_setup_flow_control(tp, 0, 0);
3803                         current_link_up = 1;
3804                 }
3805                 goto out;
3806         }
3807
3808         /* Want auto-negotiation.  */
3809         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3810
3811         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3812         if (flowctrl & ADVERTISE_1000XPAUSE)
3813                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3814         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3815                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3816
3817         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3818                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3819                     tp->serdes_counter &&
3820                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3821                                     MAC_STATUS_RCVD_CFG)) ==
3822                      MAC_STATUS_PCS_SYNCED)) {
3823                         tp->serdes_counter--;
3824                         current_link_up = 1;
3825                         goto out;
3826                 }
3827 restart_autoneg:
3828                 if (workaround)
3829                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3830                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3831                 udelay(5);
3832                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3833
3834                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3835                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3836         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3837                                  MAC_STATUS_SIGNAL_DET)) {
3838                 sg_dig_status = tr32(SG_DIG_STATUS);
3839                 mac_status = tr32(MAC_STATUS);
3840
3841                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3842                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3843                         u32 local_adv = 0, remote_adv = 0;
3844
3845                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3846                                 local_adv |= ADVERTISE_1000XPAUSE;
3847                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3848                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3849
3850                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3851                                 remote_adv |= LPA_1000XPAUSE;
3852                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3853                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3854
3855                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3856                         current_link_up = 1;
3857                         tp->serdes_counter = 0;
3858                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3859                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3860                         if (tp->serdes_counter)
3861                                 tp->serdes_counter--;
3862                         else {
3863                                 if (workaround) {
3864                                         u32 val = serdes_cfg;
3865
3866                                         if (port_a)
3867                                                 val |= 0xc010000;
3868                                         else
3869                                                 val |= 0x4010000;
3870
3871                                         tw32_f(MAC_SERDES_CFG, val);
3872                                 }
3873
3874                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3875                                 udelay(40);
3876
3877                                 /* Link parallel detection - link is up */
3878                                 /* only if we have PCS_SYNC and not */
3879                                 /* receiving config code words */
3880                                 mac_status = tr32(MAC_STATUS);
3881                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3882                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3883                                         tg3_setup_flow_control(tp, 0, 0);
3884                                         current_link_up = 1;
3885                                         tp->tg3_flags2 |=
3886                                                 TG3_FLG2_PARALLEL_DETECT;
3887                                         tp->serdes_counter =
3888                                                 SERDES_PARALLEL_DET_TIMEOUT;
3889                                 } else
3890                                         goto restart_autoneg;
3891                         }
3892                 }
3893         } else {
3894                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3895                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3896         }
3897
3898 out:
3899         return current_link_up;
3900 }
3901
3902 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3903 {
3904         int current_link_up = 0;
3905
3906         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3907                 goto out;
3908
3909         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3910                 u32 txflags, rxflags;
3911                 int i;
3912
3913                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3914                         u32 local_adv = 0, remote_adv = 0;
3915
3916                         if (txflags & ANEG_CFG_PS1)
3917                                 local_adv |= ADVERTISE_1000XPAUSE;
3918                         if (txflags & ANEG_CFG_PS2)
3919                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3920
3921                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3922                                 remote_adv |= LPA_1000XPAUSE;
3923                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3924                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3925
3926                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3927
3928                         current_link_up = 1;
3929                 }
3930                 for (i = 0; i < 30; i++) {
3931                         udelay(20);
3932                         tw32_f(MAC_STATUS,
3933                                (MAC_STATUS_SYNC_CHANGED |
3934                                 MAC_STATUS_CFG_CHANGED));
3935                         udelay(40);
3936                         if ((tr32(MAC_STATUS) &
3937                              (MAC_STATUS_SYNC_CHANGED |
3938                               MAC_STATUS_CFG_CHANGED)) == 0)
3939                                 break;
3940                 }
3941
3942                 mac_status = tr32(MAC_STATUS);
3943                 if (current_link_up == 0 &&
3944                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3945                     !(mac_status & MAC_STATUS_RCVD_CFG))
3946                         current_link_up = 1;
3947         } else {
3948                 tg3_setup_flow_control(tp, 0, 0);
3949
3950                 /* Forcing 1000FD link up. */
3951                 current_link_up = 1;
3952
3953                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3954                 udelay(40);
3955
3956                 tw32_f(MAC_MODE, tp->mac_mode);
3957                 udelay(40);
3958         }
3959
3960 out:
3961         return current_link_up;
3962 }
3963
3964 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3965 {
3966         u32 orig_pause_cfg;
3967         u16 orig_active_speed;
3968         u8 orig_active_duplex;
3969         u32 mac_status;
3970         int current_link_up;
3971         int i;
3972
3973         orig_pause_cfg = tp->link_config.active_flowctrl;
3974         orig_active_speed = tp->link_config.active_speed;
3975         orig_active_duplex = tp->link_config.active_duplex;
3976
3977         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3978             netif_carrier_ok(tp->dev) &&
3979             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3980                 mac_status = tr32(MAC_STATUS);
3981                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3982                                MAC_STATUS_SIGNAL_DET |
3983                                MAC_STATUS_CFG_CHANGED |
3984                                MAC_STATUS_RCVD_CFG);
3985                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3986                                    MAC_STATUS_SIGNAL_DET)) {
3987                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3988                                             MAC_STATUS_CFG_CHANGED));
3989                         return 0;
3990                 }
3991         }
3992
3993         tw32_f(MAC_TX_AUTO_NEG, 0);
3994
3995         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3996         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3997         tw32_f(MAC_MODE, tp->mac_mode);
3998         udelay(40);
3999
4000         if (tp->phy_id == TG3_PHY_ID_BCM8002)
4001                 tg3_init_bcm8002(tp);
4002
4003         /* Enable link change event even when serdes polling.  */
4004         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4005         udelay(40);
4006
4007         current_link_up = 0;
4008         mac_status = tr32(MAC_STATUS);
4009
4010         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
4011                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4012         else
4013                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4014
4015         tp->napi[0].hw_status->status =
4016                 (SD_STATUS_UPDATED |
4017                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4018
4019         for (i = 0; i < 100; i++) {
4020                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4021                                     MAC_STATUS_CFG_CHANGED));
4022                 udelay(5);
4023                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4024                                          MAC_STATUS_CFG_CHANGED |
4025                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4026                         break;
4027         }
4028
4029         mac_status = tr32(MAC_STATUS);
4030         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4031                 current_link_up = 0;
4032                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4033                     tp->serdes_counter == 0) {
4034                         tw32_f(MAC_MODE, (tp->mac_mode |
4035                                           MAC_MODE_SEND_CONFIGS));
4036                         udelay(1);
4037                         tw32_f(MAC_MODE, tp->mac_mode);
4038                 }
4039         }
4040
4041         if (current_link_up == 1) {
4042                 tp->link_config.active_speed = SPEED_1000;
4043                 tp->link_config.active_duplex = DUPLEX_FULL;
4044                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4045                                     LED_CTRL_LNKLED_OVERRIDE |
4046                                     LED_CTRL_1000MBPS_ON));
4047         } else {
4048                 tp->link_config.active_speed = SPEED_INVALID;
4049                 tp->link_config.active_duplex = DUPLEX_INVALID;
4050                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4051                                     LED_CTRL_LNKLED_OVERRIDE |
4052                                     LED_CTRL_TRAFFIC_OVERRIDE));
4053         }
4054
4055         if (current_link_up != netif_carrier_ok(tp->dev)) {
4056                 if (current_link_up)
4057                         netif_carrier_on(tp->dev);
4058                 else
4059                         netif_carrier_off(tp->dev);
4060                 tg3_link_report(tp);
4061         } else {
4062                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4063                 if (orig_pause_cfg != now_pause_cfg ||
4064                     orig_active_speed != tp->link_config.active_speed ||
4065                     orig_active_duplex != tp->link_config.active_duplex)
4066                         tg3_link_report(tp);
4067         }
4068
4069         return 0;
4070 }
4071
4072 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4073 {
4074         int current_link_up, err = 0;
4075         u32 bmsr, bmcr;
4076         u16 current_speed;
4077         u8 current_duplex;
4078         u32 local_adv, remote_adv;
4079
4080         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4081         tw32_f(MAC_MODE, tp->mac_mode);
4082         udelay(40);
4083
4084         tw32(MAC_EVENT, 0);
4085
4086         tw32_f(MAC_STATUS,
4087              (MAC_STATUS_SYNC_CHANGED |
4088               MAC_STATUS_CFG_CHANGED |
4089               MAC_STATUS_MI_COMPLETION |
4090               MAC_STATUS_LNKSTATE_CHANGED));
4091         udelay(40);
4092
4093         if (force_reset)
4094                 tg3_phy_reset(tp);
4095
4096         current_link_up = 0;
4097         current_speed = SPEED_INVALID;
4098         current_duplex = DUPLEX_INVALID;
4099
4100         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4101         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4102         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4103                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4104                         bmsr |= BMSR_LSTATUS;
4105                 else
4106                         bmsr &= ~BMSR_LSTATUS;
4107         }
4108
4109         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4110
4111         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4112             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4113                 /* do nothing, just check for link up at the end */
4114         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4115                 u32 adv, new_adv;
4116
4117                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4118                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4119                                   ADVERTISE_1000XPAUSE |
4120                                   ADVERTISE_1000XPSE_ASYM |
4121                                   ADVERTISE_SLCT);
4122
4123                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4124
4125                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4126                         new_adv |= ADVERTISE_1000XHALF;
4127                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4128                         new_adv |= ADVERTISE_1000XFULL;
4129
4130                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4131                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4132                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4133                         tg3_writephy(tp, MII_BMCR, bmcr);
4134
4135                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4136                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4137                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4138
4139                         return err;
4140                 }
4141         } else {
4142                 u32 new_bmcr;
4143
4144                 bmcr &= ~BMCR_SPEED1000;
4145                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4146
4147                 if (tp->link_config.duplex == DUPLEX_FULL)
4148                         new_bmcr |= BMCR_FULLDPLX;
4149
4150                 if (new_bmcr != bmcr) {
4151                         /* BMCR_SPEED1000 is a reserved bit that needs
4152                          * to be set on write.
4153                          */
4154                         new_bmcr |= BMCR_SPEED1000;
4155
4156                         /* Force a linkdown */
4157                         if (netif_carrier_ok(tp->dev)) {
4158                                 u32 adv;
4159
4160                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4161                                 adv &= ~(ADVERTISE_1000XFULL |
4162                                          ADVERTISE_1000XHALF |
4163                                          ADVERTISE_SLCT);
4164                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4165                                 tg3_writephy(tp, MII_BMCR, bmcr |
4166                                                            BMCR_ANRESTART |
4167                                                            BMCR_ANENABLE);
4168                                 udelay(10);
4169                                 netif_carrier_off(tp->dev);
4170                         }
4171                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4172                         bmcr = new_bmcr;
4173                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4174                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4175                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4176                             ASIC_REV_5714) {
4177                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4178                                         bmsr |= BMSR_LSTATUS;
4179                                 else
4180                                         bmsr &= ~BMSR_LSTATUS;
4181                         }
4182                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4183                 }
4184         }
4185
4186         if (bmsr & BMSR_LSTATUS) {
4187                 current_speed = SPEED_1000;
4188                 current_link_up = 1;
4189                 if (bmcr & BMCR_FULLDPLX)
4190                         current_duplex = DUPLEX_FULL;
4191                 else
4192                         current_duplex = DUPLEX_HALF;
4193
4194                 local_adv = 0;
4195                 remote_adv = 0;
4196
4197                 if (bmcr & BMCR_ANENABLE) {
4198                         u32 common;
4199
4200                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4201                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4202                         common = local_adv & remote_adv;
4203                         if (common & (ADVERTISE_1000XHALF |
4204                                       ADVERTISE_1000XFULL)) {
4205                                 if (common & ADVERTISE_1000XFULL)
4206                                         current_duplex = DUPLEX_FULL;
4207                                 else
4208                                         current_duplex = DUPLEX_HALF;
4209                         } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4210                                 /* Link is up via parallel detect */
4211                         } else {
4212                                 current_link_up = 0;
4213                         }
4214                 }
4215         }
4216
4217         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4218                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4219
4220         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4221         if (tp->link_config.active_duplex == DUPLEX_HALF)
4222                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4223
4224         tw32_f(MAC_MODE, tp->mac_mode);
4225         udelay(40);
4226
4227         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4228
4229         tp->link_config.active_speed = current_speed;
4230         tp->link_config.active_duplex = current_duplex;
4231
4232         if (current_link_up != netif_carrier_ok(tp->dev)) {
4233                 if (current_link_up)
4234                         netif_carrier_on(tp->dev);
4235                 else {
4236                         netif_carrier_off(tp->dev);
4237                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4238                 }
4239                 tg3_link_report(tp);
4240         }
4241         return err;
4242 }
4243
4244 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4245 {
4246         if (tp->serdes_counter) {
4247                 /* Give autoneg time to complete. */
4248                 tp->serdes_counter--;
4249                 return;
4250         }
4251
4252         if (!netif_carrier_ok(tp->dev) &&
4253             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4254                 u32 bmcr;
4255
4256                 tg3_readphy(tp, MII_BMCR, &bmcr);
4257                 if (bmcr & BMCR_ANENABLE) {
4258                         u32 phy1, phy2;
4259
4260                         /* Select shadow register 0x1f */
4261                         tg3_writephy(tp, 0x1c, 0x7c00);
4262                         tg3_readphy(tp, 0x1c, &phy1);
4263
4264                         /* Select expansion interrupt status register */
4265                         tg3_writephy(tp, 0x17, 0x0f01);
4266                         tg3_readphy(tp, 0x15, &phy2);
4267                         tg3_readphy(tp, 0x15, &phy2);
4268
4269                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4270                                 /* We have signal detect and not receiving
4271                                  * config code words, link is up by parallel
4272                                  * detection.
4273                                  */
4274
4275                                 bmcr &= ~BMCR_ANENABLE;
4276                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4277                                 tg3_writephy(tp, MII_BMCR, bmcr);
4278                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4279                         }
4280                 }
4281         } else if (netif_carrier_ok(tp->dev) &&
4282                    (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4283                    (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4284                 u32 phy2;
4285
4286                 /* Select expansion interrupt status register */
4287                 tg3_writephy(tp, 0x17, 0x0f01);
4288                 tg3_readphy(tp, 0x15, &phy2);
4289                 if (phy2 & 0x20) {
4290                         u32 bmcr;
4291
4292                         /* Config code words received, turn on autoneg. */
4293                         tg3_readphy(tp, MII_BMCR, &bmcr);
4294                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4295
4296                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4297
4298                 }
4299         }
4300 }
4301
4302 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4303 {
4304         int err;
4305
4306         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
4307                 err = tg3_setup_fiber_phy(tp, force_reset);
4308         else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
4309                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4310         else
4311                 err = tg3_setup_copper_phy(tp, force_reset);
4312
4313         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4314                 u32 val, scale;
4315
4316                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4317                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4318                         scale = 65;
4319                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4320                         scale = 6;
4321                 else
4322                         scale = 12;
4323
4324                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4325                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4326                 tw32(GRC_MISC_CFG, val);
4327         }
4328
4329         if (tp->link_config.active_speed == SPEED_1000 &&
4330             tp->link_config.active_duplex == DUPLEX_HALF)
4331                 tw32(MAC_TX_LENGTHS,
4332                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4333                       (6 << TX_LENGTHS_IPG_SHIFT) |
4334                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4335         else
4336                 tw32(MAC_TX_LENGTHS,
4337                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4338                       (6 << TX_LENGTHS_IPG_SHIFT) |
4339                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4340
4341         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4342                 if (netif_carrier_ok(tp->dev)) {
4343                         tw32(HOSTCC_STAT_COAL_TICKS,
4344                              tp->coal.stats_block_coalesce_usecs);
4345                 } else {
4346                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4347                 }
4348         }
4349
4350         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4351                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4352                 if (!netif_carrier_ok(tp->dev))
4353                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4354                               tp->pwrmgmt_thresh;
4355                 else
4356                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4357                 tw32(PCIE_PWR_MGMT_THRESH, val);
4358         }
4359
4360         return err;
4361 }
4362
4363 /* This is called whenever we suspect that the system chipset is re-
4364  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4365  * is bogus tx completions. We try to recover by setting the
4366  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4367  * in the workqueue.
4368  */
4369 static void tg3_tx_recover(struct tg3 *tp)
4370 {
4371         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4372                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4373
4374         netdev_warn(tp->dev,
4375                     "The system may be re-ordering memory-mapped I/O "
4376                     "cycles to the network device, attempting to recover. "
4377                     "Please report the problem to the driver maintainer "
4378                     "and include system chipset information.\n");
4379
4380         spin_lock(&tp->lock);
4381         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4382         spin_unlock(&tp->lock);
4383 }
4384
4385 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4386 {
4387         smp_mb();
4388         return tnapi->tx_pending -
4389                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4390 }
4391
4392 /* Tigon3 never reports partial packet sends.  So we do not
4393  * need special logic to handle SKBs that have not had all
4394  * of their frags sent yet, like SunGEM does.
4395  */
4396 static void tg3_tx(struct tg3_napi *tnapi)
4397 {
4398         struct tg3 *tp = tnapi->tp;
4399         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4400         u32 sw_idx = tnapi->tx_cons;
4401         struct netdev_queue *txq;
4402         int index = tnapi - tp->napi;
4403
4404         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4405                 index--;
4406
4407         txq = netdev_get_tx_queue(tp->dev, index);
4408
4409         while (sw_idx != hw_idx) {
4410                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4411                 struct sk_buff *skb = ri->skb;
4412                 int i, tx_bug = 0;
4413
4414                 if (unlikely(skb == NULL)) {
4415                         tg3_tx_recover(tp);
4416                         return;
4417                 }
4418
4419                 pci_unmap_single(tp->pdev,
4420                                  dma_unmap_addr(ri, mapping),
4421                                  skb_headlen(skb),
4422                                  PCI_DMA_TODEVICE);
4423
4424                 ri->skb = NULL;
4425
4426                 sw_idx = NEXT_TX(sw_idx);
4427
4428                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4429                         ri = &tnapi->tx_buffers[sw_idx];
4430                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4431                                 tx_bug = 1;
4432
4433                         pci_unmap_page(tp->pdev,
4434                                        dma_unmap_addr(ri, mapping),
4435                                        skb_shinfo(skb)->frags[i].size,
4436                                        PCI_DMA_TODEVICE);
4437                         sw_idx = NEXT_TX(sw_idx);
4438                 }
4439
4440                 dev_kfree_skb(skb);
4441
4442                 if (unlikely(tx_bug)) {
4443                         tg3_tx_recover(tp);
4444                         return;
4445                 }
4446         }
4447
4448         tnapi->tx_cons = sw_idx;
4449
4450         /* Need to make the tx_cons update visible to tg3_start_xmit()
4451          * before checking for netif_queue_stopped().  Without the
4452          * memory barrier, there is a small possibility that tg3_start_xmit()
4453          * will miss it and cause the queue to be stopped forever.
4454          */
4455         smp_mb();
4456
4457         if (unlikely(netif_tx_queue_stopped(txq) &&
4458                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4459                 __netif_tx_lock(txq, smp_processor_id());
4460                 if (netif_tx_queue_stopped(txq) &&
4461                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4462                         netif_tx_wake_queue(txq);
4463                 __netif_tx_unlock(txq);
4464         }
4465 }
4466
4467 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4468 {
4469         if (!ri->skb)
4470                 return;
4471
4472         pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4473                          map_sz, PCI_DMA_FROMDEVICE);
4474         dev_kfree_skb_any(ri->skb);
4475         ri->skb = NULL;
4476 }
4477
4478 /* Returns size of skb allocated or < 0 on error.
4479  *
4480  * We only need to fill in the address because the other members
4481  * of the RX descriptor are invariant, see tg3_init_rings.
4482  *
4483  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4484  * posting buffers we only dirty the first cache line of the RX
4485  * descriptor (containing the address).  Whereas for the RX status
4486  * buffers the cpu only reads the last cacheline of the RX descriptor
4487  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4488  */
4489 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4490                             u32 opaque_key, u32 dest_idx_unmasked)
4491 {
4492         struct tg3_rx_buffer_desc *desc;
4493         struct ring_info *map, *src_map;
4494         struct sk_buff *skb;
4495         dma_addr_t mapping;
4496         int skb_size, dest_idx;
4497
4498         src_map = NULL;
4499         switch (opaque_key) {
4500         case RXD_OPAQUE_RING_STD:
4501                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4502                 desc = &tpr->rx_std[dest_idx];
4503                 map = &tpr->rx_std_buffers[dest_idx];
4504                 skb_size = tp->rx_pkt_map_sz;
4505                 break;
4506
4507         case RXD_OPAQUE_RING_JUMBO:
4508                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4509                 desc = &tpr->rx_jmb[dest_idx].std;
4510                 map = &tpr->rx_jmb_buffers[dest_idx];
4511                 skb_size = TG3_RX_JMB_MAP_SZ;
4512                 break;
4513
4514         default:
4515                 return -EINVAL;
4516         }
4517
4518         /* Do not overwrite any of the map or rp information
4519          * until we are sure we can commit to a new buffer.
4520          *
4521          * Callers depend upon this behavior and assume that
4522          * we leave everything unchanged if we fail.
4523          */
4524         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4525         if (skb == NULL)
4526                 return -ENOMEM;
4527
4528         skb_reserve(skb, tp->rx_offset);
4529
4530         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4531                                  PCI_DMA_FROMDEVICE);
4532         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4533                 dev_kfree_skb(skb);
4534                 return -EIO;
4535         }
4536
4537         map->skb = skb;
4538         dma_unmap_addr_set(map, mapping, mapping);
4539
4540         desc->addr_hi = ((u64)mapping >> 32);
4541         desc->addr_lo = ((u64)mapping & 0xffffffff);
4542
4543         return skb_size;
4544 }
4545
4546 /* We only need to move over in the address because the other
4547  * members of the RX descriptor are invariant.  See notes above
4548  * tg3_alloc_rx_skb for full details.
4549  */
4550 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4551                            struct tg3_rx_prodring_set *dpr,
4552                            u32 opaque_key, int src_idx,
4553                            u32 dest_idx_unmasked)
4554 {
4555         struct tg3 *tp = tnapi->tp;
4556         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4557         struct ring_info *src_map, *dest_map;
4558         struct tg3_rx_prodring_set *spr = &tp->prodring[0];
4559         int dest_idx;
4560
4561         switch (opaque_key) {
4562         case RXD_OPAQUE_RING_STD:
4563                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4564                 dest_desc = &dpr->rx_std[dest_idx];
4565                 dest_map = &dpr->rx_std_buffers[dest_idx];
4566                 src_desc = &spr->rx_std[src_idx];
4567                 src_map = &spr->rx_std_buffers[src_idx];
4568                 break;
4569
4570         case RXD_OPAQUE_RING_JUMBO:
4571                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4572                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4573                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4574                 src_desc = &spr->rx_jmb[src_idx].std;
4575                 src_map = &spr->rx_jmb_buffers[src_idx];
4576                 break;
4577
4578         default:
4579                 return;
4580         }
4581
4582         dest_map->skb = src_map->skb;
4583         dma_unmap_addr_set(dest_map, mapping,
4584                            dma_unmap_addr(src_map, mapping));
4585         dest_desc->addr_hi = src_desc->addr_hi;
4586         dest_desc->addr_lo = src_desc->addr_lo;
4587
4588         /* Ensure that the update to the skb happens after the physical
4589          * addresses have been transferred to the new BD location.
4590          */
4591         smp_wmb();
4592
4593         src_map->skb = NULL;
4594 }
4595
4596 /* The RX ring scheme is composed of multiple rings which post fresh
4597  * buffers to the chip, and one special ring the chip uses to report
4598  * status back to the host.
4599  *
4600  * The special ring reports the status of received packets to the
4601  * host.  The chip does not write into the original descriptor the
4602  * RX buffer was obtained from.  The chip simply takes the original
4603  * descriptor as provided by the host, updates the status and length
4604  * field, then writes this into the next status ring entry.
4605  *
4606  * Each ring the host uses to post buffers to the chip is described
4607  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4608  * it is first placed into the on-chip ram.  When the packet's length
4609  * is known, it walks down the TG3_BDINFO entries to select the ring.
4610  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4611  * which is within the range of the new packet's length is chosen.
4612  *
4613  * The "separate ring for rx status" scheme may sound queer, but it makes
4614  * sense from a cache coherency perspective.  If only the host writes
4615  * to the buffer post rings, and only the chip writes to the rx status
4616  * rings, then cache lines never move beyond shared-modified state.
4617  * If both the host and chip were to write into the same ring, cache line
4618  * eviction could occur since both entities want it in an exclusive state.
4619  */
4620 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4621 {
4622         struct tg3 *tp = tnapi->tp;
4623         u32 work_mask, rx_std_posted = 0;
4624         u32 std_prod_idx, jmb_prod_idx;
4625         u32 sw_idx = tnapi->rx_rcb_ptr;
4626         u16 hw_idx;
4627         int received;
4628         struct tg3_rx_prodring_set *tpr = tnapi->prodring;
4629
4630         hw_idx = *(tnapi->rx_rcb_prod_idx);
4631         /*
4632          * We need to order the read of hw_idx and the read of
4633          * the opaque cookie.
4634          */
4635         rmb();
4636         work_mask = 0;
4637         received = 0;
4638         std_prod_idx = tpr->rx_std_prod_idx;
4639         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4640         while (sw_idx != hw_idx && budget > 0) {
4641                 struct ring_info *ri;
4642                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4643                 unsigned int len;
4644                 struct sk_buff *skb;
4645                 dma_addr_t dma_addr;
4646                 u32 opaque_key, desc_idx, *post_ptr;
4647                 bool hw_vlan __maybe_unused = false;
4648                 u16 vtag __maybe_unused = 0;
4649
4650                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4651                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4652                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4653                         ri = &tp->prodring[0].rx_std_buffers[desc_idx];
4654                         dma_addr = dma_unmap_addr(ri, mapping);
4655                         skb = ri->skb;
4656                         post_ptr = &std_prod_idx;
4657                         rx_std_posted++;
4658                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4659                         ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
4660                         dma_addr = dma_unmap_addr(ri, mapping);
4661                         skb = ri->skb;
4662                         post_ptr = &jmb_prod_idx;
4663                 } else
4664                         goto next_pkt_nopost;
4665
4666                 work_mask |= opaque_key;
4667
4668                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4669                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4670                 drop_it:
4671                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4672                                        desc_idx, *post_ptr);
4673                 drop_it_no_recycle:
4674                         /* Other statistics kept track of by card. */
4675                         tp->net_stats.rx_dropped++;
4676                         goto next_pkt;
4677                 }
4678
4679                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4680                       ETH_FCS_LEN;
4681
4682                 if (len > TG3_RX_COPY_THRESH(tp)) {
4683                         int skb_size;
4684
4685                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4686                                                     *post_ptr);
4687                         if (skb_size < 0)
4688                                 goto drop_it;
4689
4690                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4691                                          PCI_DMA_FROMDEVICE);
4692
4693                         /* Ensure that the update to the skb happens
4694                          * after the usage of the old DMA mapping.
4695                          */
4696                         smp_wmb();
4697
4698                         ri->skb = NULL;
4699
4700                         skb_put(skb, len);
4701                 } else {
4702                         struct sk_buff *copy_skb;
4703
4704                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4705                                        desc_idx, *post_ptr);
4706
4707                         copy_skb = netdev_alloc_skb(tp->dev, len + VLAN_HLEN +
4708                                                     TG3_RAW_IP_ALIGN);
4709                         if (copy_skb == NULL)
4710                                 goto drop_it_no_recycle;
4711
4712                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN + VLAN_HLEN);
4713                         skb_put(copy_skb, len);
4714                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4715                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4716                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4717
4718                         /* We'll reuse the original ring buffer. */
4719                         skb = copy_skb;
4720                 }
4721
4722                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4723                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4724                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4725                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4726                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4727                 else
4728                         skb->ip_summed = CHECKSUM_NONE;
4729
4730                 skb->protocol = eth_type_trans(skb, tp->dev);
4731
4732                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4733                     skb->protocol != htons(ETH_P_8021Q)) {
4734                         dev_kfree_skb(skb);
4735                         goto next_pkt;
4736                 }
4737
4738                 if (desc->type_flags & RXD_FLAG_VLAN &&
4739                     !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) {
4740                         vtag = desc->err_vlan & RXD_VLAN_MASK;
4741 #if TG3_VLAN_TAG_USED
4742                         if (tp->vlgrp)
4743                                 hw_vlan = true;
4744                         else
4745 #endif
4746                         {
4747                                 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
4748                                                     __skb_push(skb, VLAN_HLEN);
4749
4750                                 memmove(ve, skb->data + VLAN_HLEN,
4751                                         ETH_ALEN * 2);
4752                                 ve->h_vlan_proto = htons(ETH_P_8021Q);
4753                                 ve->h_vlan_TCI = htons(vtag);
4754                         }
4755                 }
4756
4757 #if TG3_VLAN_TAG_USED
4758                 if (hw_vlan)
4759                         vlan_gro_receive(&tnapi->napi, tp->vlgrp, vtag, skb);
4760                 else
4761 #endif
4762                         napi_gro_receive(&tnapi->napi, skb);
4763
4764                 received++;
4765                 budget--;
4766
4767 next_pkt:
4768                 (*post_ptr)++;
4769
4770                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4771                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4772                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4773                                      tpr->rx_std_prod_idx);
4774                         work_mask &= ~RXD_OPAQUE_RING_STD;
4775                         rx_std_posted = 0;
4776                 }
4777 next_pkt_nopost:
4778                 sw_idx++;
4779                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4780
4781                 /* Refresh hw_idx to see if there is new work */
4782                 if (sw_idx == hw_idx) {
4783                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4784                         rmb();
4785                 }
4786         }
4787
4788         /* ACK the status ring. */
4789         tnapi->rx_rcb_ptr = sw_idx;
4790         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4791
4792         /* Refill RX ring(s). */
4793         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4794                 if (work_mask & RXD_OPAQUE_RING_STD) {
4795                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4796                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4797                                      tpr->rx_std_prod_idx);
4798                 }
4799                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4800                         tpr->rx_jmb_prod_idx = jmb_prod_idx %
4801                                                TG3_RX_JUMBO_RING_SIZE;
4802                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4803                                      tpr->rx_jmb_prod_idx);
4804                 }
4805                 mmiowb();
4806         } else if (work_mask) {
4807                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4808                  * updated before the producer indices can be updated.
4809                  */
4810                 smp_wmb();
4811
4812                 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4813                 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
4814
4815                 if (tnapi != &tp->napi[1])
4816                         napi_schedule(&tp->napi[1].napi);
4817         }
4818
4819         return received;
4820 }
4821
4822 static void tg3_poll_link(struct tg3 *tp)
4823 {
4824         /* handle link change and other phy events */
4825         if (!(tp->tg3_flags &
4826               (TG3_FLAG_USE_LINKCHG_REG |
4827                TG3_FLAG_POLL_SERDES))) {
4828                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4829
4830                 if (sblk->status & SD_STATUS_LINK_CHG) {
4831                         sblk->status = SD_STATUS_UPDATED |
4832                                        (sblk->status & ~SD_STATUS_LINK_CHG);
4833                         spin_lock(&tp->lock);
4834                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4835                                 tw32_f(MAC_STATUS,
4836                                      (MAC_STATUS_SYNC_CHANGED |
4837                                       MAC_STATUS_CFG_CHANGED |
4838                                       MAC_STATUS_MI_COMPLETION |
4839                                       MAC_STATUS_LNKSTATE_CHANGED));
4840                                 udelay(40);
4841                         } else
4842                                 tg3_setup_phy(tp, 0);
4843                         spin_unlock(&tp->lock);
4844                 }
4845         }
4846 }
4847
4848 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4849                                 struct tg3_rx_prodring_set *dpr,
4850                                 struct tg3_rx_prodring_set *spr)
4851 {
4852         u32 si, di, cpycnt, src_prod_idx;
4853         int i, err = 0;
4854
4855         while (1) {
4856                 src_prod_idx = spr->rx_std_prod_idx;
4857
4858                 /* Make sure updates to the rx_std_buffers[] entries and the
4859                  * standard producer index are seen in the correct order.
4860                  */
4861                 smp_rmb();
4862
4863                 if (spr->rx_std_cons_idx == src_prod_idx)
4864                         break;
4865
4866                 if (spr->rx_std_cons_idx < src_prod_idx)
4867                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4868                 else
4869                         cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4870
4871                 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4872
4873                 si = spr->rx_std_cons_idx;
4874                 di = dpr->rx_std_prod_idx;
4875
4876                 for (i = di; i < di + cpycnt; i++) {
4877                         if (dpr->rx_std_buffers[i].skb) {
4878                                 cpycnt = i - di;
4879                                 err = -ENOSPC;
4880                                 break;
4881                         }
4882                 }
4883
4884                 if (!cpycnt)
4885                         break;
4886
4887                 /* Ensure that updates to the rx_std_buffers ring and the
4888                  * shadowed hardware producer ring from tg3_recycle_skb() are
4889                  * ordered correctly WRT the skb check above.
4890                  */
4891                 smp_rmb();
4892
4893                 memcpy(&dpr->rx_std_buffers[di],
4894                        &spr->rx_std_buffers[si],
4895                        cpycnt * sizeof(struct ring_info));
4896
4897                 for (i = 0; i < cpycnt; i++, di++, si++) {
4898                         struct tg3_rx_buffer_desc *sbd, *dbd;
4899                         sbd = &spr->rx_std[si];
4900                         dbd = &dpr->rx_std[di];
4901                         dbd->addr_hi = sbd->addr_hi;
4902                         dbd->addr_lo = sbd->addr_lo;
4903                 }
4904
4905                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4906                                        TG3_RX_RING_SIZE;
4907                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4908                                        TG3_RX_RING_SIZE;
4909         }
4910
4911         while (1) {
4912                 src_prod_idx = spr->rx_jmb_prod_idx;
4913
4914                 /* Make sure updates to the rx_jmb_buffers[] entries and
4915                  * the jumbo producer index are seen in the correct order.
4916                  */
4917                 smp_rmb();
4918
4919                 if (spr->rx_jmb_cons_idx == src_prod_idx)
4920                         break;
4921
4922                 if (spr->rx_jmb_cons_idx < src_prod_idx)
4923                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4924                 else
4925                         cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4926
4927                 cpycnt = min(cpycnt,
4928                              TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4929
4930                 si = spr->rx_jmb_cons_idx;
4931                 di = dpr->rx_jmb_prod_idx;
4932
4933                 for (i = di; i < di + cpycnt; i++) {
4934                         if (dpr->rx_jmb_buffers[i].skb) {
4935                                 cpycnt = i - di;
4936                                 err = -ENOSPC;
4937                                 break;
4938                         }
4939                 }
4940
4941                 if (!cpycnt)
4942                         break;
4943
4944                 /* Ensure that updates to the rx_jmb_buffers ring and the
4945                  * shadowed hardware producer ring from tg3_recycle_skb() are
4946                  * ordered correctly WRT the skb check above.
4947                  */
4948                 smp_rmb();
4949
4950                 memcpy(&dpr->rx_jmb_buffers[di],
4951                        &spr->rx_jmb_buffers[si],
4952                        cpycnt * sizeof(struct ring_info));
4953
4954                 for (i = 0; i < cpycnt; i++, di++, si++) {
4955                         struct tg3_rx_buffer_desc *sbd, *dbd;
4956                         sbd = &spr->rx_jmb[si].std;
4957                         dbd = &dpr->rx_jmb[di].std;
4958                         dbd->addr_hi = sbd->addr_hi;
4959                         dbd->addr_lo = sbd->addr_lo;
4960                 }
4961
4962                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4963                                        TG3_RX_JUMBO_RING_SIZE;
4964                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4965                                        TG3_RX_JUMBO_RING_SIZE;
4966         }
4967
4968         return err;
4969 }
4970
4971 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4972 {
4973         struct tg3 *tp = tnapi->tp;
4974
4975         /* run TX completion thread */
4976         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4977                 tg3_tx(tnapi);
4978                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4979                         return work_done;
4980         }
4981
4982         /* run RX thread, within the bounds set by NAPI.
4983          * All RX "locking" is done by ensuring outside
4984          * code synchronizes with tg3->napi.poll()
4985          */
4986         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4987                 work_done += tg3_rx(tnapi, budget - work_done);
4988
4989         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4990                 struct tg3_rx_prodring_set *dpr = &tp->prodring[0];
4991                 int i, err = 0;
4992                 u32 std_prod_idx = dpr->rx_std_prod_idx;
4993                 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
4994
4995                 for (i = 1; i < tp->irq_cnt; i++)
4996                         err |= tg3_rx_prodring_xfer(tp, dpr,
4997                                                     tp->napi[i].prodring);
4998
4999                 wmb();
5000
5001                 if (std_prod_idx != dpr->rx_std_prod_idx)
5002                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5003                                      dpr->rx_std_prod_idx);
5004
5005                 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5006                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5007                                      dpr->rx_jmb_prod_idx);
5008
5009                 mmiowb();
5010
5011                 if (err)
5012                         tw32_f(HOSTCC_MODE, tp->coal_now);
5013         }
5014
5015         return work_done;
5016 }
5017
5018 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5019 {
5020         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5021         struct tg3 *tp = tnapi->tp;
5022         int work_done = 0;
5023         struct tg3_hw_status *sblk = tnapi->hw_status;
5024
5025         while (1) {
5026                 work_done = tg3_poll_work(tnapi, work_done, budget);
5027
5028                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5029                         goto tx_recovery;
5030
5031                 if (unlikely(work_done >= budget))
5032                         break;
5033
5034                 /* tp->last_tag is used in tg3_int_reenable() below
5035                  * to tell the hw how much work has been processed,
5036                  * so we must read it before checking for more work.
5037                  */
5038                 tnapi->last_tag = sblk->status_tag;
5039                 tnapi->last_irq_tag = tnapi->last_tag;
5040                 rmb();
5041
5042                 /* check for RX/TX work to do */
5043                 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5044                            *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5045                         napi_complete(napi);
5046                         /* Reenable interrupts. */
5047                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5048                         mmiowb();
5049                         break;
5050                 }
5051         }
5052
5053         return work_done;
5054
5055 tx_recovery:
5056         /* work_done is guaranteed to be less than budget. */
5057         napi_complete(napi);
5058         schedule_work(&tp->reset_task);
5059         return work_done;
5060 }
5061
5062 static int tg3_poll(struct napi_struct *napi, int budget)
5063 {
5064         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5065         struct tg3 *tp = tnapi->tp;
5066         int work_done = 0;
5067         struct tg3_hw_status *sblk = tnapi->hw_status;
5068
5069         while (1) {
5070                 tg3_poll_link(tp);
5071
5072                 work_done = tg3_poll_work(tnapi, work_done, budget);
5073
5074                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5075                         goto tx_recovery;
5076
5077                 if (unlikely(work_done >= budget))
5078                         break;
5079
5080                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5081                         /* tp->last_tag is used in tg3_int_reenable() below
5082                          * to tell the hw how much work has been processed,
5083                          * so we must read it before checking for more work.
5084                          */
5085                         tnapi->last_tag = sblk->status_tag;
5086                         tnapi->last_irq_tag = tnapi->last_tag;
5087                         rmb();
5088                 } else
5089                         sblk->status &= ~SD_STATUS_UPDATED;
5090
5091                 if (likely(!tg3_has_work(tnapi))) {
5092                         napi_complete(napi);
5093                         tg3_int_reenable(tnapi);
5094                         break;
5095                 }
5096         }
5097
5098         return work_done;
5099
5100 tx_recovery:
5101         /* work_done is guaranteed to be less than budget. */
5102         napi_complete(napi);
5103         schedule_work(&tp->reset_task);
5104         return work_done;
5105 }
5106
5107 static void tg3_irq_quiesce(struct tg3 *tp)
5108 {
5109         int i;
5110
5111         BUG_ON(tp->irq_sync);
5112
5113         tp->irq_sync = 1;
5114         smp_mb();
5115
5116         for (i = 0; i < tp->irq_cnt; i++)
5117                 synchronize_irq(tp->napi[i].irq_vec);
5118 }
5119
5120 static inline int tg3_irq_sync(struct tg3 *tp)
5121 {
5122         return tp->irq_sync;
5123 }
5124
5125 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5126  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5127  * with as well.  Most of the time, this is not necessary except when
5128  * shutting down the device.
5129  */
5130 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5131 {
5132         spin_lock_bh(&tp->lock);
5133         if (irq_sync)
5134                 tg3_irq_quiesce(tp);
5135 }
5136
5137 static inline void tg3_full_unlock(struct tg3 *tp)
5138 {
5139         spin_unlock_bh(&tp->lock);
5140 }
5141
5142 /* One-shot MSI handler - Chip automatically disables interrupt
5143  * after sending MSI so driver doesn't have to do it.
5144  */
5145 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5146 {
5147         struct tg3_napi *tnapi = dev_id;
5148         struct tg3 *tp = tnapi->tp;
5149
5150         prefetch(tnapi->hw_status);
5151         if (tnapi->rx_rcb)
5152                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5153
5154         if (likely(!tg3_irq_sync(tp)))
5155                 napi_schedule(&tnapi->napi);
5156
5157         return IRQ_HANDLED;
5158 }
5159
5160 /* MSI ISR - No need to check for interrupt sharing and no need to
5161  * flush status block and interrupt mailbox. PCI ordering rules
5162  * guarantee that MSI will arrive after the status block.
5163  */
5164 static irqreturn_t tg3_msi(int irq, void *dev_id)
5165 {
5166         struct tg3_napi *tnapi = dev_id;
5167         struct tg3 *tp = tnapi->tp;
5168
5169         prefetch(tnapi->hw_status);
5170         if (tnapi->rx_rcb)
5171                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5172         /*
5173          * Writing any value to intr-mbox-0 clears PCI INTA# and
5174          * chip-internal interrupt pending events.
5175          * Writing non-zero to intr-mbox-0 additional tells the
5176          * NIC to stop sending us irqs, engaging "in-intr-handler"
5177          * event coalescing.
5178          */
5179         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5180         if (likely(!tg3_irq_sync(tp)))
5181                 napi_schedule(&tnapi->napi);
5182
5183         return IRQ_RETVAL(1);
5184 }
5185
5186 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5187 {
5188         struct tg3_napi *tnapi = dev_id;
5189         struct tg3 *tp = tnapi->tp;
5190         struct tg3_hw_status *sblk = tnapi->hw_status;
5191         unsigned int handled = 1;
5192
5193         /* In INTx mode, it is possible for the interrupt to arrive at
5194          * the CPU before the status block posted prior to the interrupt.
5195          * Reading the PCI State register will confirm whether the
5196          * interrupt is ours and will flush the status block.
5197          */
5198         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5199                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5200                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5201                         handled = 0;
5202                         goto out;
5203                 }
5204         }
5205
5206         /*
5207          * Writing any value to intr-mbox-0 clears PCI INTA# and
5208          * chip-internal interrupt pending events.
5209          * Writing non-zero to intr-mbox-0 additional tells the
5210          * NIC to stop sending us irqs, engaging "in-intr-handler"
5211          * event coalescing.
5212          *
5213          * Flush the mailbox to de-assert the IRQ immediately to prevent
5214          * spurious interrupts.  The flush impacts performance but
5215          * excessive spurious interrupts can be worse in some cases.
5216          */
5217         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5218         if (tg3_irq_sync(tp))
5219                 goto out;
5220         sblk->status &= ~SD_STATUS_UPDATED;
5221         if (likely(tg3_has_work(tnapi))) {
5222                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5223                 napi_schedule(&tnapi->napi);
5224         } else {
5225                 /* No work, shared interrupt perhaps?  re-enable
5226                  * interrupts, and flush that PCI write
5227                  */
5228                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5229                                0x00000000);
5230         }
5231 out:
5232         return IRQ_RETVAL(handled);
5233 }
5234
5235 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5236 {
5237         struct tg3_napi *tnapi = dev_id;
5238         struct tg3 *tp = tnapi->tp;
5239         struct tg3_hw_status *sblk = tnapi->hw_status;
5240         unsigned int handled = 1;
5241
5242         /* In INTx mode, it is possible for the interrupt to arrive at
5243          * the CPU before the status block posted prior to the interrupt.
5244          * Reading the PCI State register will confirm whether the
5245          * interrupt is ours and will flush the status block.
5246          */
5247         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5248                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5249                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5250                         handled = 0;
5251                         goto out;
5252                 }
5253         }
5254
5255         /*
5256          * writing any value to intr-mbox-0 clears PCI INTA# and
5257          * chip-internal interrupt pending events.
5258          * writing non-zero to intr-mbox-0 additional tells the
5259          * NIC to stop sending us irqs, engaging "in-intr-handler"
5260          * event coalescing.
5261          *
5262          * Flush the mailbox to de-assert the IRQ immediately to prevent
5263          * spurious interrupts.  The flush impacts performance but
5264          * excessive spurious interrupts can be worse in some cases.
5265          */
5266         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5267
5268         /*
5269          * In a shared interrupt configuration, sometimes other devices'
5270          * interrupts will scream.  We record the current status tag here
5271          * so that the above check can report that the screaming interrupts
5272          * are unhandled.  Eventually they will be silenced.
5273          */
5274         tnapi->last_irq_tag = sblk->status_tag;
5275
5276         if (tg3_irq_sync(tp))
5277                 goto out;
5278
5279         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5280
5281         napi_schedule(&tnapi->napi);
5282
5283 out:
5284         return IRQ_RETVAL(handled);
5285 }
5286
5287 /* ISR for interrupt test */
5288 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5289 {
5290         struct tg3_napi *tnapi = dev_id;
5291         struct tg3 *tp = tnapi->tp;
5292         struct tg3_hw_status *sblk = tnapi->hw_status;
5293
5294         if ((sblk->status & SD_STATUS_UPDATED) ||
5295             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5296                 tg3_disable_ints(tp);
5297                 return IRQ_RETVAL(1);
5298         }
5299         return IRQ_RETVAL(0);
5300 }
5301
5302 static int tg3_init_hw(struct tg3 *, int);
5303 static int tg3_halt(struct tg3 *, int, int);
5304
5305 /* Restart hardware after configuration changes, self-test, etc.
5306  * Invoked with tp->lock held.
5307  */
5308 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5309         __releases(tp->lock)
5310         __acquires(tp->lock)
5311 {
5312         int err;
5313
5314         err = tg3_init_hw(tp, reset_phy);
5315         if (err) {
5316                 netdev_err(tp->dev,
5317                            "Failed to re-initialize device, aborting\n");
5318                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5319                 tg3_full_unlock(tp);
5320                 del_timer_sync(&tp->timer);
5321                 tp->irq_sync = 0;
5322                 tg3_napi_enable(tp);
5323                 dev_close(tp->dev);
5324                 tg3_full_lock(tp, 0);
5325         }
5326         return err;
5327 }
5328
5329 #ifdef CONFIG_NET_POLL_CONTROLLER
5330 static void tg3_poll_controller(struct net_device *dev)
5331 {
5332         int i;
5333         struct tg3 *tp = netdev_priv(dev);
5334
5335         for (i = 0; i < tp->irq_cnt; i++)
5336                 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5337 }
5338 #endif
5339
5340 static void tg3_reset_task(struct work_struct *work)
5341 {
5342         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5343         int err;
5344         unsigned int restart_timer;
5345
5346         tg3_full_lock(tp, 0);
5347
5348         if (!netif_running(tp->dev)) {
5349                 tg3_full_unlock(tp);
5350                 return;
5351         }
5352
5353         tg3_full_unlock(tp);
5354
5355         tg3_phy_stop(tp);
5356
5357         tg3_netif_stop(tp);
5358
5359         tg3_full_lock(tp, 1);
5360
5361         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5362         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5363
5364         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5365                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5366                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5367                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5368                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5369         }
5370
5371         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5372         err = tg3_init_hw(tp, 1);
5373         if (err)
5374                 goto out;
5375
5376         tg3_netif_start(tp);
5377
5378         if (restart_timer)
5379                 mod_timer(&tp->timer, jiffies + 1);
5380
5381 out:
5382         tg3_full_unlock(tp);
5383
5384         if (!err)
5385                 tg3_phy_start(tp);
5386 }
5387
5388 static void tg3_dump_short_state(struct tg3 *tp)
5389 {
5390         netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5391                    tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5392         netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5393                    tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5394 }
5395
5396 static void tg3_tx_timeout(struct net_device *dev)
5397 {
5398         struct tg3 *tp = netdev_priv(dev);
5399
5400         if (netif_msg_tx_err(tp)) {
5401                 netdev_err(dev, "transmit timed out, resetting\n");
5402                 tg3_dump_short_state(tp);
5403         }
5404
5405         schedule_work(&tp->reset_task);
5406 }
5407
5408 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5409 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5410 {
5411         u32 base = (u32) mapping & 0xffffffff;
5412
5413         return ((base > 0xffffdcc0) &&
5414                 (base + len + 8 < base));
5415 }
5416
5417 /* Test for DMA addresses > 40-bit */
5418 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5419                                           int len)
5420 {
5421 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5422         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5423                 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5424         return 0;
5425 #else
5426         return 0;
5427 #endif
5428 }
5429
5430 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5431
5432 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5433 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5434                                        struct sk_buff *skb, u32 last_plus_one,
5435                                        u32 *start, u32 base_flags, u32 mss)
5436 {
5437         struct tg3 *tp = tnapi->tp;
5438         struct sk_buff *new_skb;
5439         dma_addr_t new_addr = 0;
5440         u32 entry = *start;
5441         int i, ret = 0;
5442
5443         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5444                 new_skb = skb_copy(skb, GFP_ATOMIC);
5445         else {
5446                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5447
5448                 new_skb = skb_copy_expand(skb,
5449                                           skb_headroom(skb) + more_headroom,
5450                                           skb_tailroom(skb), GFP_ATOMIC);
5451         }
5452
5453         if (!new_skb) {
5454                 ret = -1;
5455         } else {
5456                 /* New SKB is guaranteed to be linear. */
5457                 entry = *start;
5458                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5459                                           PCI_DMA_TODEVICE);
5460                 /* Make sure the mapping succeeded */
5461                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5462                         ret = -1;
5463                         dev_kfree_skb(new_skb);
5464                         new_skb = NULL;
5465
5466                 /* Make sure new skb does not cross any 4G boundaries.
5467                  * Drop the packet if it does.
5468                  */
5469                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5470                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5471                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5472                                          PCI_DMA_TODEVICE);
5473                         ret = -1;
5474                         dev_kfree_skb(new_skb);
5475                         new_skb = NULL;
5476                 } else {
5477                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5478                                     base_flags, 1 | (mss << 1));
5479                         *start = NEXT_TX(entry);
5480                 }
5481         }
5482
5483         /* Now clean up the sw ring entries. */
5484         i = 0;
5485         while (entry != last_plus_one) {
5486                 int len;
5487
5488                 if (i == 0)
5489                         len = skb_headlen(skb);
5490                 else
5491                         len = skb_shinfo(skb)->frags[i-1].size;
5492
5493                 pci_unmap_single(tp->pdev,
5494                                  dma_unmap_addr(&tnapi->tx_buffers[entry],
5495                                                 mapping),
5496                                  len, PCI_DMA_TODEVICE);
5497                 if (i == 0) {
5498                         tnapi->tx_buffers[entry].skb = new_skb;
5499                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5500                                            new_addr);
5501                 } else {
5502                         tnapi->tx_buffers[entry].skb = NULL;
5503                 }
5504                 entry = NEXT_TX(entry);
5505                 i++;
5506         }
5507
5508         dev_kfree_skb(skb);
5509
5510         return ret;
5511 }
5512
5513 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5514                         dma_addr_t mapping, int len, u32 flags,
5515                         u32 mss_and_is_end)
5516 {
5517         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5518         int is_end = (mss_and_is_end & 0x1);
5519         u32 mss = (mss_and_is_end >> 1);
5520         u32 vlan_tag = 0;
5521
5522         if (is_end)
5523                 flags |= TXD_FLAG_END;
5524         if (flags & TXD_FLAG_VLAN) {
5525                 vlan_tag = flags >> 16;
5526                 flags &= 0xffff;
5527         }
5528         vlan_tag |= (mss << TXD_MSS_SHIFT);
5529
5530         txd->addr_hi = ((u64) mapping >> 32);
5531         txd->addr_lo = ((u64) mapping & 0xffffffff);
5532         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5533         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5534 }
5535
5536 /* hard_start_xmit for devices that don't have any bugs and
5537  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5538  */
5539 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5540                                   struct net_device *dev)
5541 {
5542         struct tg3 *tp = netdev_priv(dev);
5543         u32 len, entry, base_flags, mss;
5544         dma_addr_t mapping;
5545         struct tg3_napi *tnapi;
5546         struct netdev_queue *txq;
5547         unsigned int i, last;
5548
5549         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5550         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5551         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5552                 tnapi++;
5553
5554         /* We are running in BH disabled context with netif_tx_lock
5555          * and TX reclaim runs via tp->napi.poll inside of a software
5556          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5557          * no IRQ context deadlocks to worry about either.  Rejoice!
5558          */
5559         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5560                 if (!netif_tx_queue_stopped(txq)) {
5561                         netif_tx_stop_queue(txq);
5562
5563                         /* This is a hard error, log it. */
5564                         netdev_err(dev,
5565                                    "BUG! Tx Ring full when queue awake!\n");
5566                 }
5567                 return NETDEV_TX_BUSY;
5568         }
5569
5570         entry = tnapi->tx_prod;
5571         base_flags = 0;
5572         mss = 0;
5573         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5574                 int tcp_opt_len, ip_tcp_len;
5575                 u32 hdrlen;
5576
5577                 if (skb_header_cloned(skb) &&
5578                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5579                         dev_kfree_skb(skb);
5580                         goto out_unlock;
5581                 }
5582
5583                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5584                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5585                 else {
5586                         struct iphdr *iph = ip_hdr(skb);
5587
5588                         tcp_opt_len = tcp_optlen(skb);
5589                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5590
5591                         iph->check = 0;
5592                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5593                         hdrlen = ip_tcp_len + tcp_opt_len;
5594                 }
5595
5596                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5597                         mss |= (hdrlen & 0xc) << 12;
5598                         if (hdrlen & 0x10)
5599                                 base_flags |= 0x00000010;
5600                         base_flags |= (hdrlen & 0x3e0) << 5;
5601                 } else
5602                         mss |= hdrlen << 9;
5603
5604                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5605                                TXD_FLAG_CPU_POST_DMA);
5606
5607                 tcp_hdr(skb)->check = 0;
5608
5609         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5610                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5611         }
5612
5613 #if TG3_VLAN_TAG_USED
5614         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5615                 base_flags |= (TXD_FLAG_VLAN |
5616                                (vlan_tx_tag_get(skb) << 16));
5617 #endif
5618
5619         len = skb_headlen(skb);
5620
5621         /* Queue skb data, a.k.a. the main skb fragment. */
5622         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5623         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5624                 dev_kfree_skb(skb);
5625                 goto out_unlock;
5626         }
5627
5628         tnapi->tx_buffers[entry].skb = skb;
5629         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5630
5631         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5632             !mss && skb->len > ETH_DATA_LEN)
5633                 base_flags |= TXD_FLAG_JMB_PKT;
5634
5635         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5636                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5637
5638         entry = NEXT_TX(entry);
5639
5640         /* Now loop through additional data fragments, and queue them. */
5641         if (skb_shinfo(skb)->nr_frags > 0) {
5642                 last = skb_shinfo(skb)->nr_frags - 1;
5643                 for (i = 0; i <= last; i++) {
5644                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5645
5646                         len = frag->size;
5647                         mapping = pci_map_page(tp->pdev,
5648                                                frag->page,
5649                                                frag->page_offset,
5650                                                len, PCI_DMA_TODEVICE);
5651                         if (pci_dma_mapping_error(tp->pdev, mapping))
5652                                 goto dma_error;
5653
5654                         tnapi->tx_buffers[entry].skb = NULL;
5655                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5656                                            mapping);
5657
5658                         tg3_set_txd(tnapi, entry, mapping, len,
5659                                     base_flags, (i == last) | (mss << 1));
5660
5661                         entry = NEXT_TX(entry);
5662                 }
5663         }
5664
5665         /* Packets are ready, update Tx producer idx local and on card. */
5666         tw32_tx_mbox(tnapi->prodmbox, entry);
5667
5668         tnapi->tx_prod = entry;
5669         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5670                 netif_tx_stop_queue(txq);
5671                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5672                         netif_tx_wake_queue(txq);
5673         }
5674
5675 out_unlock:
5676         mmiowb();
5677
5678         return NETDEV_TX_OK;
5679
5680 dma_error:
5681         last = i;
5682         entry = tnapi->tx_prod;
5683         tnapi->tx_buffers[entry].skb = NULL;
5684         pci_unmap_single(tp->pdev,
5685                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5686                          skb_headlen(skb),
5687                          PCI_DMA_TODEVICE);
5688         for (i = 0; i <= last; i++) {
5689                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5690                 entry = NEXT_TX(entry);
5691
5692                 pci_unmap_page(tp->pdev,
5693                                dma_unmap_addr(&tnapi->tx_buffers[entry],
5694                                               mapping),
5695                                frag->size, PCI_DMA_TODEVICE);
5696         }
5697
5698         dev_kfree_skb(skb);
5699         return NETDEV_TX_OK;
5700 }
5701
5702 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5703                                           struct net_device *);
5704
5705 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5706  * TSO header is greater than 80 bytes.
5707  */
5708 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5709 {
5710         struct sk_buff *segs, *nskb;
5711         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5712
5713         /* Estimate the number of fragments in the worst case */
5714         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5715                 netif_stop_queue(tp->dev);
5716                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5717                         return NETDEV_TX_BUSY;
5718
5719                 netif_wake_queue(tp->dev);
5720         }
5721
5722         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5723         if (IS_ERR(segs))
5724                 goto tg3_tso_bug_end;
5725
5726         do {
5727                 nskb = segs;
5728                 segs = segs->next;
5729                 nskb->next = NULL;
5730                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5731         } while (segs);
5732
5733 tg3_tso_bug_end:
5734         dev_kfree_skb(skb);
5735
5736         return NETDEV_TX_OK;
5737 }
5738
5739 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5740  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5741  */
5742 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5743                                           struct net_device *dev)
5744 {
5745         struct tg3 *tp = netdev_priv(dev);
5746         u32 len, entry, base_flags, mss;
5747         int would_hit_hwbug;
5748         dma_addr_t mapping;
5749         struct tg3_napi *tnapi;
5750         struct netdev_queue *txq;
5751         unsigned int i, last;
5752
5753         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5754         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5755         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5756                 tnapi++;
5757
5758         /* We are running in BH disabled context with netif_tx_lock
5759          * and TX reclaim runs via tp->napi.poll inside of a software
5760          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5761          * no IRQ context deadlocks to worry about either.  Rejoice!
5762          */
5763         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5764                 if (!netif_tx_queue_stopped(txq)) {
5765                         netif_tx_stop_queue(txq);
5766
5767                         /* This is a hard error, log it. */
5768                         netdev_err(dev,
5769                                    "BUG! Tx Ring full when queue awake!\n");
5770                 }
5771                 return NETDEV_TX_BUSY;
5772         }
5773
5774         entry = tnapi->tx_prod;
5775         base_flags = 0;
5776         if (skb->ip_summed == CHECKSUM_PARTIAL)
5777                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5778
5779         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5780                 struct iphdr *iph;
5781                 u32 tcp_opt_len, ip_tcp_len, hdr_len;
5782
5783                 if (skb_header_cloned(skb) &&
5784                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5785                         dev_kfree_skb(skb);
5786                         goto out_unlock;
5787                 }
5788
5789                 tcp_opt_len = tcp_optlen(skb);
5790                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5791
5792                 hdr_len = ip_tcp_len + tcp_opt_len;
5793                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5794                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5795                         return tg3_tso_bug(tp, skb);
5796
5797                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5798                                TXD_FLAG_CPU_POST_DMA);
5799
5800                 iph = ip_hdr(skb);
5801                 iph->check = 0;
5802                 iph->tot_len = htons(mss + hdr_len);
5803                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5804                         tcp_hdr(skb)->check = 0;
5805                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5806                 } else
5807                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5808                                                                  iph->daddr, 0,
5809                                                                  IPPROTO_TCP,
5810                                                                  0);
5811
5812                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5813                         mss |= (hdr_len & 0xc) << 12;
5814                         if (hdr_len & 0x10)
5815                                 base_flags |= 0x00000010;
5816                         base_flags |= (hdr_len & 0x3e0) << 5;
5817                 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5818                         mss |= hdr_len << 9;
5819                 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5820                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5821                         if (tcp_opt_len || iph->ihl > 5) {
5822                                 int tsflags;
5823
5824                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5825                                 mss |= (tsflags << 11);
5826                         }
5827                 } else {
5828                         if (tcp_opt_len || iph->ihl > 5) {
5829                                 int tsflags;
5830
5831                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5832                                 base_flags |= tsflags << 12;
5833                         }
5834                 }
5835         }
5836 #if TG3_VLAN_TAG_USED
5837         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5838                 base_flags |= (TXD_FLAG_VLAN |
5839                                (vlan_tx_tag_get(skb) << 16));
5840 #endif
5841
5842         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5843             !mss && skb->len > ETH_DATA_LEN)
5844                 base_flags |= TXD_FLAG_JMB_PKT;
5845
5846         len = skb_headlen(skb);
5847
5848         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5849         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5850                 dev_kfree_skb(skb);
5851                 goto out_unlock;
5852         }
5853
5854         tnapi->tx_buffers[entry].skb = skb;
5855         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5856
5857         would_hit_hwbug = 0;
5858
5859         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5860                 would_hit_hwbug = 1;
5861
5862         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5863             tg3_4g_overflow_test(mapping, len))
5864                 would_hit_hwbug = 1;
5865
5866         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5867             tg3_40bit_overflow_test(tp, mapping, len))
5868                 would_hit_hwbug = 1;
5869
5870         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5871                 would_hit_hwbug = 1;
5872
5873         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5874                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5875
5876         entry = NEXT_TX(entry);
5877
5878         /* Now loop through additional data fragments, and queue them. */
5879         if (skb_shinfo(skb)->nr_frags > 0) {
5880                 last = skb_shinfo(skb)->nr_frags - 1;
5881                 for (i = 0; i <= last; i++) {
5882                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5883
5884                         len = frag->size;
5885                         mapping = pci_map_page(tp->pdev,
5886                                                frag->page,
5887                                                frag->page_offset,
5888                                                len, PCI_DMA_TODEVICE);
5889
5890                         tnapi->tx_buffers[entry].skb = NULL;
5891                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5892                                            mapping);
5893                         if (pci_dma_mapping_error(tp->pdev, mapping))
5894                                 goto dma_error;
5895
5896                         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5897                             len <= 8)
5898                                 would_hit_hwbug = 1;
5899
5900                         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5901                             tg3_4g_overflow_test(mapping, len))
5902                                 would_hit_hwbug = 1;
5903
5904                         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5905                             tg3_40bit_overflow_test(tp, mapping, len))
5906                                 would_hit_hwbug = 1;
5907
5908                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5909                                 tg3_set_txd(tnapi, entry, mapping, len,
5910                                             base_flags, (i == last)|(mss << 1));
5911                         else
5912                                 tg3_set_txd(tnapi, entry, mapping, len,
5913                                             base_flags, (i == last));
5914
5915                         entry = NEXT_TX(entry);
5916                 }
5917         }
5918
5919         if (would_hit_hwbug) {
5920                 u32 last_plus_one = entry;
5921                 u32 start;
5922
5923                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5924                 start &= (TG3_TX_RING_SIZE - 1);
5925
5926                 /* If the workaround fails due to memory/mapping
5927                  * failure, silently drop this packet.
5928                  */
5929                 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
5930                                                 &start, base_flags, mss))
5931                         goto out_unlock;
5932
5933                 entry = start;
5934         }
5935
5936         /* Packets are ready, update Tx producer idx local and on card. */
5937         tw32_tx_mbox(tnapi->prodmbox, entry);
5938
5939         tnapi->tx_prod = entry;
5940         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5941                 netif_tx_stop_queue(txq);
5942                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5943                         netif_tx_wake_queue(txq);
5944         }
5945
5946 out_unlock:
5947         mmiowb();
5948
5949         return NETDEV_TX_OK;
5950
5951 dma_error:
5952         last = i;
5953         entry = tnapi->tx_prod;
5954         tnapi->tx_buffers[entry].skb = NULL;
5955         pci_unmap_single(tp->pdev,
5956                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5957                          skb_headlen(skb),
5958                          PCI_DMA_TODEVICE);
5959         for (i = 0; i <= last; i++) {
5960                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5961                 entry = NEXT_TX(entry);
5962
5963                 pci_unmap_page(tp->pdev,
5964                                dma_unmap_addr(&tnapi->tx_buffers[entry],
5965                                               mapping),
5966                                frag->size, PCI_DMA_TODEVICE);
5967         }
5968
5969         dev_kfree_skb(skb);
5970         return NETDEV_TX_OK;
5971 }
5972
5973 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5974                                int new_mtu)
5975 {
5976         dev->mtu = new_mtu;
5977
5978         if (new_mtu > ETH_DATA_LEN) {
5979                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5980                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5981                         ethtool_op_set_tso(dev, 0);
5982                 } else {
5983                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5984                 }
5985         } else {
5986                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5987                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5988                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5989         }
5990 }
5991
5992 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5993 {
5994         struct tg3 *tp = netdev_priv(dev);
5995         int err;
5996
5997         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5998                 return -EINVAL;
5999
6000         if (!netif_running(dev)) {
6001                 /* We'll just catch it later when the
6002                  * device is up'd.
6003                  */
6004                 tg3_set_mtu(dev, tp, new_mtu);
6005                 return 0;
6006         }
6007
6008         tg3_phy_stop(tp);
6009
6010         tg3_netif_stop(tp);
6011
6012         tg3_full_lock(tp, 1);
6013
6014         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6015
6016         tg3_set_mtu(dev, tp, new_mtu);
6017
6018         err = tg3_restart_hw(tp, 0);
6019
6020         if (!err)
6021                 tg3_netif_start(tp);
6022
6023         tg3_full_unlock(tp);
6024
6025         if (!err)
6026                 tg3_phy_start(tp);
6027
6028         return err;
6029 }
6030
6031 static void tg3_rx_prodring_free(struct tg3 *tp,
6032                                  struct tg3_rx_prodring_set *tpr)
6033 {
6034         int i;
6035
6036         if (tpr != &tp->prodring[0]) {
6037                 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
6038                      i = (i + 1) % TG3_RX_RING_SIZE)
6039                         tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6040                                         tp->rx_pkt_map_sz);
6041
6042                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6043                         for (i = tpr->rx_jmb_cons_idx;
6044                              i != tpr->rx_jmb_prod_idx;
6045                              i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
6046                                 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6047                                                 TG3_RX_JMB_MAP_SZ);
6048                         }
6049                 }
6050
6051                 return;
6052         }
6053
6054         for (i = 0; i < TG3_RX_RING_SIZE; i++)
6055                 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6056                                 tp->rx_pkt_map_sz);
6057
6058         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6059                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
6060                         tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6061                                         TG3_RX_JMB_MAP_SZ);
6062         }
6063 }
6064
6065 /* Initialize rx rings for packet processing.
6066  *
6067  * The chip has been shut down and the driver detached from
6068  * the networking, so no interrupts or new tx packets will
6069  * end up in the driver.  tp->{tx,}lock are held and thus
6070  * we may not sleep.
6071  */
6072 static int tg3_rx_prodring_alloc(struct tg3 *tp,
6073                                  struct tg3_rx_prodring_set *tpr)
6074 {
6075         u32 i, rx_pkt_dma_sz;
6076
6077         tpr->rx_std_cons_idx = 0;
6078         tpr->rx_std_prod_idx = 0;
6079         tpr->rx_jmb_cons_idx = 0;
6080         tpr->rx_jmb_prod_idx = 0;
6081
6082         if (tpr != &tp->prodring[0]) {
6083                 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
6084                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
6085                         memset(&tpr->rx_jmb_buffers[0], 0,
6086                                TG3_RX_JMB_BUFF_RING_SIZE);
6087                 goto done;
6088         }
6089
6090         /* Zero out all descriptors. */
6091         memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
6092
6093         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6094         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
6095             tp->dev->mtu > ETH_DATA_LEN)
6096                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6097         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6098
6099         /* Initialize invariants of the rings, we only set this
6100          * stuff once.  This works because the card does not
6101          * write into the rx buffer posting rings.
6102          */
6103         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
6104                 struct tg3_rx_buffer_desc *rxd;
6105
6106                 rxd = &tpr->rx_std[i];
6107                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6108                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6109                 rxd->opaque = (RXD_OPAQUE_RING_STD |
6110                                (i << RXD_OPAQUE_INDEX_SHIFT));
6111         }
6112
6113         /* Now allocate fresh SKBs for each rx ring. */
6114         for (i = 0; i < tp->rx_pending; i++) {
6115                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6116                         netdev_warn(tp->dev,
6117                                     "Using a smaller RX standard ring. Only "
6118                                     "%d out of %d buffers were allocated "
6119                                     "successfully\n", i, tp->rx_pending);
6120                         if (i == 0)
6121                                 goto initfail;
6122                         tp->rx_pending = i;
6123                         break;
6124                 }
6125         }
6126
6127         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6128                 goto done;
6129
6130         memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
6131
6132         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
6133                 goto done;
6134
6135         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
6136                 struct tg3_rx_buffer_desc *rxd;
6137
6138                 rxd = &tpr->rx_jmb[i].std;
6139                 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6140                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6141                                   RXD_FLAG_JUMBO;
6142                 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6143                        (i << RXD_OPAQUE_INDEX_SHIFT));
6144         }
6145
6146         for (i = 0; i < tp->rx_jumbo_pending; i++) {
6147                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
6148                         netdev_warn(tp->dev,
6149                                     "Using a smaller RX jumbo ring. Only %d "
6150                                     "out of %d buffers were allocated "
6151                                     "successfully\n", i, tp->rx_jumbo_pending);
6152                         if (i == 0)
6153                                 goto initfail;
6154                         tp->rx_jumbo_pending = i;
6155                         break;
6156                 }
6157         }
6158
6159 done:
6160         return 0;
6161
6162 initfail:
6163         tg3_rx_prodring_free(tp, tpr);
6164         return -ENOMEM;
6165 }
6166
6167 static void tg3_rx_prodring_fini(struct tg3 *tp,
6168                                  struct tg3_rx_prodring_set *tpr)
6169 {
6170         kfree(tpr->rx_std_buffers);
6171         tpr->rx_std_buffers = NULL;
6172         kfree(tpr->rx_jmb_buffers);
6173         tpr->rx_jmb_buffers = NULL;
6174         if (tpr->rx_std) {
6175                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
6176                                     tpr->rx_std, tpr->rx_std_mapping);
6177                 tpr->rx_std = NULL;
6178         }
6179         if (tpr->rx_jmb) {
6180                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
6181                                     tpr->rx_jmb, tpr->rx_jmb_mapping);
6182                 tpr->rx_jmb = NULL;
6183         }
6184 }
6185
6186 static int tg3_rx_prodring_init(struct tg3 *tp,
6187                                 struct tg3_rx_prodring_set *tpr)
6188 {
6189         tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
6190         if (!tpr->rx_std_buffers)
6191                 return -ENOMEM;
6192
6193         tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6194                                            &tpr->rx_std_mapping);
6195         if (!tpr->rx_std)
6196                 goto err_out;
6197
6198         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6199                 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
6200                                               GFP_KERNEL);
6201                 if (!tpr->rx_jmb_buffers)
6202                         goto err_out;
6203
6204                 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6205                                                    TG3_RX_JUMBO_RING_BYTES,
6206                                                    &tpr->rx_jmb_mapping);
6207                 if (!tpr->rx_jmb)
6208                         goto err_out;
6209         }
6210
6211         return 0;
6212
6213 err_out:
6214         tg3_rx_prodring_fini(tp, tpr);
6215         return -ENOMEM;
6216 }
6217
6218 /* Free up pending packets in all rx/tx rings.
6219  *
6220  * The chip has been shut down and the driver detached from
6221  * the networking, so no interrupts or new tx packets will
6222  * end up in the driver.  tp->{tx,}lock is not held and we are not
6223  * in an interrupt context and thus may sleep.
6224  */
6225 static void tg3_free_rings(struct tg3 *tp)
6226 {
6227         int i, j;
6228
6229         for (j = 0; j < tp->irq_cnt; j++) {
6230                 struct tg3_napi *tnapi = &tp->napi[j];
6231
6232                 tg3_rx_prodring_free(tp, &tp->prodring[j]);
6233
6234                 if (!tnapi->tx_buffers)
6235                         continue;
6236
6237                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6238                         struct ring_info *txp;
6239                         struct sk_buff *skb;
6240                         unsigned int k;
6241
6242                         txp = &tnapi->tx_buffers[i];
6243                         skb = txp->skb;
6244
6245                         if (skb == NULL) {
6246                                 i++;
6247                                 continue;
6248                         }
6249
6250                         pci_unmap_single(tp->pdev,
6251                                          dma_unmap_addr(txp, mapping),
6252                                          skb_headlen(skb),
6253                                          PCI_DMA_TODEVICE);
6254                         txp->skb = NULL;
6255
6256                         i++;
6257
6258                         for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6259                                 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6260                                 pci_unmap_page(tp->pdev,
6261                                                dma_unmap_addr(txp, mapping),
6262                                                skb_shinfo(skb)->frags[k].size,
6263                                                PCI_DMA_TODEVICE);
6264                                 i++;
6265                         }
6266
6267                         dev_kfree_skb_any(skb);
6268                 }
6269         }
6270 }
6271
6272 /* Initialize tx/rx rings for packet processing.
6273  *
6274  * The chip has been shut down and the driver detached from
6275  * the networking, so no interrupts or new tx packets will
6276  * end up in the driver.  tp->{tx,}lock are held and thus
6277  * we may not sleep.
6278  */
6279 static int tg3_init_rings(struct tg3 *tp)
6280 {
6281         int i;
6282
6283         /* Free up all the SKBs. */
6284         tg3_free_rings(tp);
6285
6286         for (i = 0; i < tp->irq_cnt; i++) {
6287                 struct tg3_napi *tnapi = &tp->napi[i];
6288
6289                 tnapi->last_tag = 0;
6290                 tnapi->last_irq_tag = 0;
6291                 tnapi->hw_status->status = 0;
6292                 tnapi->hw_status->status_tag = 0;
6293                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6294
6295                 tnapi->tx_prod = 0;
6296                 tnapi->tx_cons = 0;
6297                 if (tnapi->tx_ring)
6298                         memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6299
6300                 tnapi->rx_rcb_ptr = 0;
6301                 if (tnapi->rx_rcb)
6302                         memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6303
6304                 if (tg3_rx_prodring_alloc(tp, &tp->prodring[i])) {
6305                         tg3_free_rings(tp);
6306                         return -ENOMEM;
6307                 }
6308         }
6309
6310         return 0;
6311 }
6312
6313 /*
6314  * Must not be invoked with interrupt sources disabled and
6315  * the hardware shutdown down.
6316  */
6317 static void tg3_free_consistent(struct tg3 *tp)
6318 {
6319         int i;
6320
6321         for (i = 0; i < tp->irq_cnt; i++) {
6322                 struct tg3_napi *tnapi = &tp->napi[i];
6323
6324                 if (tnapi->tx_ring) {
6325                         pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6326                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
6327                         tnapi->tx_ring = NULL;
6328                 }
6329
6330                 kfree(tnapi->tx_buffers);
6331                 tnapi->tx_buffers = NULL;
6332
6333                 if (tnapi->rx_rcb) {
6334                         pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6335                                             tnapi->rx_rcb,
6336                                             tnapi->rx_rcb_mapping);
6337                         tnapi->rx_rcb = NULL;
6338                 }
6339
6340                 if (tnapi->hw_status) {
6341                         pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6342                                             tnapi->hw_status,
6343                                             tnapi->status_mapping);
6344                         tnapi->hw_status = NULL;
6345                 }
6346         }
6347
6348         if (tp->hw_stats) {
6349                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6350                                     tp->hw_stats, tp->stats_mapping);
6351                 tp->hw_stats = NULL;
6352         }
6353
6354         for (i = 0; i < tp->irq_cnt; i++)
6355                 tg3_rx_prodring_fini(tp, &tp->prodring[i]);
6356 }
6357
6358 /*
6359  * Must not be invoked with interrupt sources disabled and
6360  * the hardware shutdown down.  Can sleep.
6361  */
6362 static int tg3_alloc_consistent(struct tg3 *tp)
6363 {
6364         int i;
6365
6366         for (i = 0; i < tp->irq_cnt; i++) {
6367                 if (tg3_rx_prodring_init(tp, &tp->prodring[i]))
6368                         goto err_out;
6369         }
6370
6371         tp->hw_stats = pci_alloc_consistent(tp->pdev,
6372                                             sizeof(struct tg3_hw_stats),
6373                                             &tp->stats_mapping);
6374         if (!tp->hw_stats)
6375                 goto err_out;
6376
6377         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6378
6379         for (i = 0; i < tp->irq_cnt; i++) {
6380                 struct tg3_napi *tnapi = &tp->napi[i];
6381                 struct tg3_hw_status *sblk;
6382
6383                 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6384                                                         TG3_HW_STATUS_SIZE,
6385                                                         &tnapi->status_mapping);
6386                 if (!tnapi->hw_status)
6387                         goto err_out;
6388
6389                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6390                 sblk = tnapi->hw_status;
6391
6392                 /* If multivector TSS is enabled, vector 0 does not handle
6393                  * tx interrupts.  Don't allocate any resources for it.
6394                  */
6395                 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6396                     (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6397                         tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6398                                                     TG3_TX_RING_SIZE,
6399                                                     GFP_KERNEL);
6400                         if (!tnapi->tx_buffers)
6401                                 goto err_out;
6402
6403                         tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6404                                                               TG3_TX_RING_BYTES,
6405                                                        &tnapi->tx_desc_mapping);
6406                         if (!tnapi->tx_ring)
6407                                 goto err_out;
6408                 }
6409
6410                 /*
6411                  * When RSS is enabled, the status block format changes
6412                  * slightly.  The "rx_jumbo_consumer", "reserved",
6413                  * and "rx_mini_consumer" members get mapped to the
6414                  * other three rx return ring producer indexes.
6415                  */
6416                 switch (i) {
6417                 default:
6418                         tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6419                         break;
6420                 case 2:
6421                         tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6422                         break;
6423                 case 3:
6424                         tnapi->rx_rcb_prod_idx = &sblk->reserved;
6425                         break;
6426                 case 4:
6427                         tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6428                         break;
6429                 }
6430
6431                 tnapi->prodring = &tp->prodring[i];
6432
6433                 /*
6434                  * If multivector RSS is enabled, vector 0 does not handle
6435                  * rx or tx interrupts.  Don't allocate any resources for it.
6436                  */
6437                 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6438                         continue;
6439
6440                 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6441                                                      TG3_RX_RCB_RING_BYTES(tp),
6442                                                      &tnapi->rx_rcb_mapping);
6443                 if (!tnapi->rx_rcb)
6444                         goto err_out;
6445
6446                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6447         }
6448
6449         return 0;
6450
6451 err_out:
6452         tg3_free_consistent(tp);
6453         return -ENOMEM;
6454 }
6455
6456 #define MAX_WAIT_CNT 1000
6457
6458 /* To stop a block, clear the enable bit and poll till it
6459  * clears.  tp->lock is held.
6460  */
6461 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6462 {
6463         unsigned int i;
6464         u32 val;
6465
6466         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6467                 switch (ofs) {
6468                 case RCVLSC_MODE:
6469                 case DMAC_MODE:
6470                 case MBFREE_MODE:
6471                 case BUFMGR_MODE:
6472                 case MEMARB_MODE:
6473                         /* We can't enable/disable these bits of the
6474                          * 5705/5750, just say success.
6475                          */
6476                         return 0;
6477
6478                 default:
6479                         break;
6480                 }
6481         }
6482
6483         val = tr32(ofs);
6484         val &= ~enable_bit;
6485         tw32_f(ofs, val);
6486
6487         for (i = 0; i < MAX_WAIT_CNT; i++) {
6488                 udelay(100);
6489                 val = tr32(ofs);
6490                 if ((val & enable_bit) == 0)
6491                         break;
6492         }
6493
6494         if (i == MAX_WAIT_CNT && !silent) {
6495                 dev_err(&tp->pdev->dev,
6496                         "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6497                         ofs, enable_bit);
6498                 return -ENODEV;
6499         }
6500
6501         return 0;
6502 }
6503
6504 /* tp->lock is held. */
6505 static int tg3_abort_hw(struct tg3 *tp, int silent)
6506 {
6507         int i, err;
6508
6509         tg3_disable_ints(tp);
6510
6511         tp->rx_mode &= ~RX_MODE_ENABLE;
6512         tw32_f(MAC_RX_MODE, tp->rx_mode);
6513         udelay(10);
6514
6515         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6516         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6517         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6518         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6519         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6520         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6521
6522         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6523         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6524         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6525         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6526         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6527         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6528         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6529
6530         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6531         tw32_f(MAC_MODE, tp->mac_mode);
6532         udelay(40);
6533
6534         tp->tx_mode &= ~TX_MODE_ENABLE;
6535         tw32_f(MAC_TX_MODE, tp->tx_mode);
6536
6537         for (i = 0; i < MAX_WAIT_CNT; i++) {
6538                 udelay(100);
6539                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6540                         break;
6541         }
6542         if (i >= MAX_WAIT_CNT) {
6543                 dev_err(&tp->pdev->dev,
6544                         "%s timed out, TX_MODE_ENABLE will not clear "
6545                         "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
6546                 err |= -ENODEV;
6547         }
6548
6549         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6550         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6551         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6552
6553         tw32(FTQ_RESET, 0xffffffff);
6554         tw32(FTQ_RESET, 0x00000000);
6555
6556         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6557         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6558
6559         for (i = 0; i < tp->irq_cnt; i++) {
6560                 struct tg3_napi *tnapi = &tp->napi[i];
6561                 if (tnapi->hw_status)
6562                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6563         }
6564         if (tp->hw_stats)
6565                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6566
6567         return err;
6568 }
6569
6570 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6571 {
6572         int i;
6573         u32 apedata;
6574
6575         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6576         if (apedata != APE_SEG_SIG_MAGIC)
6577                 return;
6578
6579         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6580         if (!(apedata & APE_FW_STATUS_READY))
6581                 return;
6582
6583         /* Wait for up to 1 millisecond for APE to service previous event. */
6584         for (i = 0; i < 10; i++) {
6585                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6586                         return;
6587
6588                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6589
6590                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6591                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6592                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6593
6594                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6595
6596                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6597                         break;
6598
6599                 udelay(100);
6600         }
6601
6602         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6603                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6604 }
6605
6606 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6607 {
6608         u32 event;
6609         u32 apedata;
6610
6611         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6612                 return;
6613
6614         switch (kind) {
6615         case RESET_KIND_INIT:
6616                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6617                                 APE_HOST_SEG_SIG_MAGIC);
6618                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6619                                 APE_HOST_SEG_LEN_MAGIC);
6620                 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6621                 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6622                 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6623                                 APE_HOST_DRIVER_ID_MAGIC);
6624                 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6625                                 APE_HOST_BEHAV_NO_PHYLOCK);
6626
6627                 event = APE_EVENT_STATUS_STATE_START;
6628                 break;
6629         case RESET_KIND_SHUTDOWN:
6630                 /* With the interface we are currently using,
6631                  * APE does not track driver state.  Wiping
6632                  * out the HOST SEGMENT SIGNATURE forces
6633                  * the APE to assume OS absent status.
6634                  */
6635                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6636
6637                 event = APE_EVENT_STATUS_STATE_UNLOAD;
6638                 break;
6639         case RESET_KIND_SUSPEND:
6640                 event = APE_EVENT_STATUS_STATE_SUSPEND;
6641                 break;
6642         default:
6643                 return;
6644         }
6645
6646         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6647
6648         tg3_ape_send_event(tp, event);
6649 }
6650
6651 /* tp->lock is held. */
6652 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6653 {
6654         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6655                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6656
6657         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6658                 switch (kind) {
6659                 case RESET_KIND_INIT:
6660                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6661                                       DRV_STATE_START);
6662                         break;
6663
6664                 case RESET_KIND_SHUTDOWN:
6665                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6666                                       DRV_STATE_UNLOAD);
6667                         break;
6668
6669                 case RESET_KIND_SUSPEND:
6670                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6671                                       DRV_STATE_SUSPEND);
6672                         break;
6673
6674                 default:
6675                         break;
6676                 }
6677         }
6678
6679         if (kind == RESET_KIND_INIT ||
6680             kind == RESET_KIND_SUSPEND)
6681                 tg3_ape_driver_state_change(tp, kind);
6682 }
6683
6684 /* tp->lock is held. */
6685 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6686 {
6687         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6688                 switch (kind) {
6689                 case RESET_KIND_INIT:
6690                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6691                                       DRV_STATE_START_DONE);
6692                         break;
6693
6694                 case RESET_KIND_SHUTDOWN:
6695                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6696                                       DRV_STATE_UNLOAD_DONE);
6697                         break;
6698
6699                 default:
6700                         break;
6701                 }
6702         }
6703
6704         if (kind == RESET_KIND_SHUTDOWN)
6705                 tg3_ape_driver_state_change(tp, kind);
6706 }
6707
6708 /* tp->lock is held. */
6709 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6710 {
6711         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6712                 switch (kind) {
6713                 case RESET_KIND_INIT:
6714                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6715                                       DRV_STATE_START);
6716                         break;
6717
6718                 case RESET_KIND_SHUTDOWN:
6719                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6720                                       DRV_STATE_UNLOAD);
6721                         break;
6722
6723                 case RESET_KIND_SUSPEND:
6724                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6725                                       DRV_STATE_SUSPEND);
6726                         break;
6727
6728                 default:
6729                         break;
6730                 }
6731         }
6732 }
6733
6734 static int tg3_poll_fw(struct tg3 *tp)
6735 {
6736         int i;
6737         u32 val;
6738
6739         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6740                 /* Wait up to 20ms for init done. */
6741                 for (i = 0; i < 200; i++) {
6742                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6743                                 return 0;
6744                         udelay(100);
6745                 }
6746                 return -ENODEV;
6747         }
6748
6749         /* Wait for firmware initialization to complete. */
6750         for (i = 0; i < 100000; i++) {
6751                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6752                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6753                         break;
6754                 udelay(10);
6755         }
6756
6757         /* Chip might not be fitted with firmware.  Some Sun onboard
6758          * parts are configured like that.  So don't signal the timeout
6759          * of the above loop as an error, but do report the lack of
6760          * running firmware once.
6761          */
6762         if (i >= 100000 &&
6763             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6764                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6765
6766                 netdev_info(tp->dev, "No firmware running\n");
6767         }
6768
6769         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6770                 /* The 57765 A0 needs a little more
6771                  * time to do some important work.
6772                  */
6773                 mdelay(10);
6774         }
6775
6776         return 0;
6777 }
6778
6779 /* Save PCI command register before chip reset */
6780 static void tg3_save_pci_state(struct tg3 *tp)
6781 {
6782         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6783 }
6784
6785 /* Restore PCI state after chip reset */
6786 static void tg3_restore_pci_state(struct tg3 *tp)
6787 {
6788         u32 val;
6789
6790         /* Re-enable indirect register accesses. */
6791         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6792                                tp->misc_host_ctrl);
6793
6794         /* Set MAX PCI retry to zero. */
6795         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6796         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6797             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6798                 val |= PCISTATE_RETRY_SAME_DMA;
6799         /* Allow reads and writes to the APE register and memory space. */
6800         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6801                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6802                        PCISTATE_ALLOW_APE_SHMEM_WR |
6803                        PCISTATE_ALLOW_APE_PSPACE_WR;
6804         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6805
6806         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6807
6808         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6809                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6810                         pcie_set_readrq(tp->pdev, 4096);
6811                 else {
6812                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6813                                               tp->pci_cacheline_sz);
6814                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6815                                               tp->pci_lat_timer);
6816                 }
6817         }
6818
6819         /* Make sure PCI-X relaxed ordering bit is clear. */
6820         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6821                 u16 pcix_cmd;
6822
6823                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6824                                      &pcix_cmd);
6825                 pcix_cmd &= ~PCI_X_CMD_ERO;
6826                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6827                                       pcix_cmd);
6828         }
6829
6830         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6831
6832                 /* Chip reset on 5780 will reset MSI enable bit,
6833                  * so need to restore it.
6834                  */
6835                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6836                         u16 ctrl;
6837
6838                         pci_read_config_word(tp->pdev,
6839                                              tp->msi_cap + PCI_MSI_FLAGS,
6840                                              &ctrl);
6841                         pci_write_config_word(tp->pdev,
6842                                               tp->msi_cap + PCI_MSI_FLAGS,
6843                                               ctrl | PCI_MSI_FLAGS_ENABLE);
6844                         val = tr32(MSGINT_MODE);
6845                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6846                 }
6847         }
6848 }
6849
6850 static void tg3_stop_fw(struct tg3 *);
6851
6852 /* tp->lock is held. */
6853 static int tg3_chip_reset(struct tg3 *tp)
6854 {
6855         u32 val;
6856         void (*write_op)(struct tg3 *, u32, u32);
6857         int i, err;
6858
6859         tg3_nvram_lock(tp);
6860
6861         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6862
6863         /* No matching tg3_nvram_unlock() after this because
6864          * chip reset below will undo the nvram lock.
6865          */
6866         tp->nvram_lock_cnt = 0;
6867
6868         /* GRC_MISC_CFG core clock reset will clear the memory
6869          * enable bit in PCI register 4 and the MSI enable bit
6870          * on some chips, so we save relevant registers here.
6871          */
6872         tg3_save_pci_state(tp);
6873
6874         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6875             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6876                 tw32(GRC_FASTBOOT_PC, 0);
6877
6878         /*
6879          * We must avoid the readl() that normally takes place.
6880          * It locks machines, causes machine checks, and other
6881          * fun things.  So, temporarily disable the 5701
6882          * hardware workaround, while we do the reset.
6883          */
6884         write_op = tp->write32;
6885         if (write_op == tg3_write_flush_reg32)
6886                 tp->write32 = tg3_write32;
6887
6888         /* Prevent the irq handler from reading or writing PCI registers
6889          * during chip reset when the memory enable bit in the PCI command
6890          * register may be cleared.  The chip does not generate interrupt
6891          * at this time, but the irq handler may still be called due to irq
6892          * sharing or irqpoll.
6893          */
6894         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6895         for (i = 0; i < tp->irq_cnt; i++) {
6896                 struct tg3_napi *tnapi = &tp->napi[i];
6897                 if (tnapi->hw_status) {
6898                         tnapi->hw_status->status = 0;
6899                         tnapi->hw_status->status_tag = 0;
6900                 }
6901                 tnapi->last_tag = 0;
6902                 tnapi->last_irq_tag = 0;
6903         }
6904         smp_mb();
6905
6906         for (i = 0; i < tp->irq_cnt; i++)
6907                 synchronize_irq(tp->napi[i].irq_vec);
6908
6909         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6910                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6911                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6912         }
6913
6914         /* do the reset */
6915         val = GRC_MISC_CFG_CORECLK_RESET;
6916
6917         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6918                 if (tr32(0x7e2c) == 0x60) {
6919                         tw32(0x7e2c, 0x20);
6920                 }
6921                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6922                         tw32(GRC_MISC_CFG, (1 << 29));
6923                         val |= (1 << 29);
6924                 }
6925         }
6926
6927         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6928                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6929                 tw32(GRC_VCPU_EXT_CTRL,
6930                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6931         }
6932
6933         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6934                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6935         tw32(GRC_MISC_CFG, val);
6936
6937         /* restore 5701 hardware bug workaround write method */
6938         tp->write32 = write_op;
6939
6940         /* Unfortunately, we have to delay before the PCI read back.
6941          * Some 575X chips even will not respond to a PCI cfg access
6942          * when the reset command is given to the chip.
6943          *
6944          * How do these hardware designers expect things to work
6945          * properly if the PCI write is posted for a long period
6946          * of time?  It is always necessary to have some method by
6947          * which a register read back can occur to push the write
6948          * out which does the reset.
6949          *
6950          * For most tg3 variants the trick below was working.
6951          * Ho hum...
6952          */
6953         udelay(120);
6954
6955         /* Flush PCI posted writes.  The normal MMIO registers
6956          * are inaccessible at this time so this is the only
6957          * way to make this reliably (actually, this is no longer
6958          * the case, see above).  I tried to use indirect
6959          * register read/write but this upset some 5701 variants.
6960          */
6961         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6962
6963         udelay(120);
6964
6965         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6966                 u16 val16;
6967
6968                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6969                         int i;
6970                         u32 cfg_val;
6971
6972                         /* Wait for link training to complete.  */
6973                         for (i = 0; i < 5000; i++)
6974                                 udelay(100);
6975
6976                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6977                         pci_write_config_dword(tp->pdev, 0xc4,
6978                                                cfg_val | (1 << 15));
6979                 }
6980
6981                 /* Clear the "no snoop" and "relaxed ordering" bits. */
6982                 pci_read_config_word(tp->pdev,
6983                                      tp->pcie_cap + PCI_EXP_DEVCTL,
6984                                      &val16);
6985                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6986                            PCI_EXP_DEVCTL_NOSNOOP_EN);
6987                 /*
6988                  * Older PCIe devices only support the 128 byte
6989                  * MPS setting.  Enforce the restriction.
6990                  */
6991                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6992                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6993                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
6994                 pci_write_config_word(tp->pdev,
6995                                       tp->pcie_cap + PCI_EXP_DEVCTL,
6996                                       val16);
6997
6998                 pcie_set_readrq(tp->pdev, 4096);
6999
7000                 /* Clear error status */
7001                 pci_write_config_word(tp->pdev,
7002                                       tp->pcie_cap + PCI_EXP_DEVSTA,
7003                                       PCI_EXP_DEVSTA_CED |
7004                                       PCI_EXP_DEVSTA_NFED |
7005                                       PCI_EXP_DEVSTA_FED |
7006                                       PCI_EXP_DEVSTA_URD);
7007         }
7008
7009         tg3_restore_pci_state(tp);
7010
7011         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
7012
7013         val = 0;
7014         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
7015                 val = tr32(MEMARB_MODE);
7016         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7017
7018         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7019                 tg3_stop_fw(tp);
7020                 tw32(0x5000, 0x400);
7021         }
7022
7023         tw32(GRC_MODE, tp->grc_mode);
7024
7025         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
7026                 val = tr32(0xc4);
7027
7028                 tw32(0xc4, val | (1 << 15));
7029         }
7030
7031         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7032             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7033                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7034                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7035                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7036                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7037         }
7038
7039         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7040                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
7041                 tw32_f(MAC_MODE, tp->mac_mode);
7042         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7043                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
7044                 tw32_f(MAC_MODE, tp->mac_mode);
7045         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7046                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
7047                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
7048                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
7049                 tw32_f(MAC_MODE, tp->mac_mode);
7050         } else
7051                 tw32_f(MAC_MODE, 0);
7052         udelay(40);
7053
7054         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7055
7056         err = tg3_poll_fw(tp);
7057         if (err)
7058                 return err;
7059
7060         tg3_mdio_start(tp);
7061
7062         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7063                 u8 phy_addr;
7064
7065                 phy_addr = tp->phy_addr;
7066                 tp->phy_addr = TG3_PHY_PCIE_ADDR;
7067
7068                 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
7069                              TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
7070                 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
7071                       TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
7072                       TG3_PCIEPHY_TX0CTRL1_NB_EN;
7073                 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
7074                 udelay(10);
7075
7076                 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
7077                              TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
7078                 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
7079                       TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
7080                 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
7081                 udelay(10);
7082
7083                 tp->phy_addr = phy_addr;
7084         }
7085
7086         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
7087             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7088             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7089             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
7090             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719 &&
7091             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
7092                 val = tr32(0x7c00);
7093
7094                 tw32(0x7c00, val | (1 << 25));
7095         }
7096
7097         /* Reprobe ASF enable state.  */
7098         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7099         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7100         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7101         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7102                 u32 nic_cfg;
7103
7104                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7105                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7106                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7107                         tp->last_event_jiffies = jiffies;
7108                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7109                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7110                 }
7111         }
7112
7113         return 0;
7114 }
7115
7116 /* tp->lock is held. */
7117 static void tg3_stop_fw(struct tg3 *tp)
7118 {
7119         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7120            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7121                 /* Wait for RX cpu to ACK the previous event. */
7122                 tg3_wait_for_event_ack(tp);
7123
7124                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7125
7126                 tg3_generate_fw_event(tp);
7127
7128                 /* Wait for RX cpu to ACK this event. */
7129                 tg3_wait_for_event_ack(tp);
7130         }
7131 }
7132
7133 /* tp->lock is held. */
7134 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7135 {
7136         int err;
7137
7138         tg3_stop_fw(tp);
7139
7140         tg3_write_sig_pre_reset(tp, kind);
7141
7142         tg3_abort_hw(tp, silent);
7143         err = tg3_chip_reset(tp);
7144
7145         __tg3_set_mac_addr(tp, 0);
7146
7147         tg3_write_sig_legacy(tp, kind);
7148         tg3_write_sig_post_reset(tp, kind);
7149
7150         if (err)
7151                 return err;
7152
7153         return 0;
7154 }
7155
7156 #define RX_CPU_SCRATCH_BASE     0x30000
7157 #define RX_CPU_SCRATCH_SIZE     0x04000
7158 #define TX_CPU_SCRATCH_BASE     0x34000
7159 #define TX_CPU_SCRATCH_SIZE     0x04000
7160
7161 /* tp->lock is held. */
7162 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7163 {
7164         int i;
7165
7166         BUG_ON(offset == TX_CPU_BASE &&
7167             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7168
7169         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7170                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7171
7172                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7173                 return 0;
7174         }
7175         if (offset == RX_CPU_BASE) {
7176                 for (i = 0; i < 10000; i++) {
7177                         tw32(offset + CPU_STATE, 0xffffffff);
7178                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7179                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7180                                 break;
7181                 }
7182
7183                 tw32(offset + CPU_STATE, 0xffffffff);
7184                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
7185                 udelay(10);
7186         } else {
7187                 for (i = 0; i < 10000; i++) {
7188                         tw32(offset + CPU_STATE, 0xffffffff);
7189                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7190                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7191                                 break;
7192                 }
7193         }
7194
7195         if (i >= 10000) {
7196                 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7197                            __func__, offset == RX_CPU_BASE ? "RX" : "TX");
7198                 return -ENODEV;
7199         }
7200
7201         /* Clear firmware's nvram arbitration. */
7202         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7203                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7204         return 0;
7205 }
7206
7207 struct fw_info {
7208         unsigned int fw_base;
7209         unsigned int fw_len;
7210         const __be32 *fw_data;
7211 };
7212
7213 /* tp->lock is held. */
7214 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7215                                  int cpu_scratch_size, struct fw_info *info)
7216 {
7217         int err, lock_err, i;
7218         void (*write_op)(struct tg3 *, u32, u32);
7219
7220         if (cpu_base == TX_CPU_BASE &&
7221             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7222                 netdev_err(tp->dev,
7223                            "%s: Trying to load TX cpu firmware which is 5705\n",
7224                            __func__);
7225                 return -EINVAL;
7226         }
7227
7228         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7229                 write_op = tg3_write_mem;
7230         else
7231                 write_op = tg3_write_indirect_reg32;
7232
7233         /* It is possible that bootcode is still loading at this point.
7234          * Get the nvram lock first before halting the cpu.
7235          */
7236         lock_err = tg3_nvram_lock(tp);
7237         err = tg3_halt_cpu(tp, cpu_base);
7238         if (!lock_err)
7239                 tg3_nvram_unlock(tp);
7240         if (err)
7241                 goto out;
7242
7243         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7244                 write_op(tp, cpu_scratch_base + i, 0);
7245         tw32(cpu_base + CPU_STATE, 0xffffffff);
7246         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7247         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7248                 write_op(tp, (cpu_scratch_base +
7249                               (info->fw_base & 0xffff) +
7250                               (i * sizeof(u32))),
7251                               be32_to_cpu(info->fw_data[i]));
7252
7253         err = 0;
7254
7255 out:
7256         return err;
7257 }
7258
7259 /* tp->lock is held. */
7260 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7261 {
7262         struct fw_info info;
7263         const __be32 *fw_data;
7264         int err, i;
7265
7266         fw_data = (void *)tp->fw->data;
7267
7268         /* Firmware blob starts with version numbers, followed by
7269            start address and length. We are setting complete length.
7270            length = end_address_of_bss - start_address_of_text.
7271            Remainder is the blob to be loaded contiguously
7272            from start address. */
7273
7274         info.fw_base = be32_to_cpu(fw_data[1]);
7275         info.fw_len = tp->fw->size - 12;
7276         info.fw_data = &fw_data[3];
7277
7278         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7279                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7280                                     &info);
7281         if (err)
7282                 return err;
7283
7284         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7285                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7286                                     &info);
7287         if (err)
7288                 return err;
7289
7290         /* Now startup only the RX cpu. */
7291         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7292         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7293
7294         for (i = 0; i < 5; i++) {
7295                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7296                         break;
7297                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7298                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
7299                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7300                 udelay(1000);
7301         }
7302         if (i >= 5) {
7303                 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7304                            "should be %08x\n", __func__,
7305                            tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
7306                 return -ENODEV;
7307         }
7308         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7309         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
7310
7311         return 0;
7312 }
7313
7314 /* 5705 needs a special version of the TSO firmware.  */
7315
7316 /* tp->lock is held. */
7317 static int tg3_load_tso_firmware(struct tg3 *tp)
7318 {
7319         struct fw_info info;
7320         const __be32 *fw_data;
7321         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7322         int err, i;
7323
7324         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7325                 return 0;
7326
7327         fw_data = (void *)tp->fw->data;
7328
7329         /* Firmware blob starts with version numbers, followed by
7330            start address and length. We are setting complete length.
7331            length = end_address_of_bss - start_address_of_text.
7332            Remainder is the blob to be loaded contiguously
7333            from start address. */
7334
7335         info.fw_base = be32_to_cpu(fw_data[1]);
7336         cpu_scratch_size = tp->fw_len;
7337         info.fw_len = tp->fw->size - 12;
7338         info.fw_data = &fw_data[3];
7339
7340         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7341                 cpu_base = RX_CPU_BASE;
7342                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7343         } else {
7344                 cpu_base = TX_CPU_BASE;
7345                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7346                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7347         }
7348
7349         err = tg3_load_firmware_cpu(tp, cpu_base,
7350                                     cpu_scratch_base, cpu_scratch_size,
7351                                     &info);
7352         if (err)
7353                 return err;
7354
7355         /* Now startup the cpu. */
7356         tw32(cpu_base + CPU_STATE, 0xffffffff);
7357         tw32_f(cpu_base + CPU_PC, info.fw_base);
7358
7359         for (i = 0; i < 5; i++) {
7360                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7361                         break;
7362                 tw32(cpu_base + CPU_STATE, 0xffffffff);
7363                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
7364                 tw32_f(cpu_base + CPU_PC, info.fw_base);
7365                 udelay(1000);
7366         }
7367         if (i >= 5) {
7368                 netdev_err(tp->dev,
7369                            "%s fails to set CPU PC, is %08x should be %08x\n",
7370                            __func__, tr32(cpu_base + CPU_PC), info.fw_base);
7371                 return -ENODEV;
7372         }
7373         tw32(cpu_base + CPU_STATE, 0xffffffff);
7374         tw32_f(cpu_base + CPU_MODE,  0x00000000);
7375         return 0;
7376 }
7377
7378
7379 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7380 {
7381         struct tg3 *tp = netdev_priv(dev);
7382         struct sockaddr *addr = p;
7383         int err = 0, skip_mac_1 = 0;
7384
7385         if (!is_valid_ether_addr(addr->sa_data))
7386                 return -EINVAL;
7387
7388         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7389
7390         if (!netif_running(dev))
7391                 return 0;
7392
7393         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7394                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7395
7396                 addr0_high = tr32(MAC_ADDR_0_HIGH);
7397                 addr0_low = tr32(MAC_ADDR_0_LOW);
7398                 addr1_high = tr32(MAC_ADDR_1_HIGH);
7399                 addr1_low = tr32(MAC_ADDR_1_LOW);
7400
7401                 /* Skip MAC addr 1 if ASF is using it. */
7402                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7403                     !(addr1_high == 0 && addr1_low == 0))
7404                         skip_mac_1 = 1;
7405         }
7406         spin_lock_bh(&tp->lock);
7407         __tg3_set_mac_addr(tp, skip_mac_1);
7408         spin_unlock_bh(&tp->lock);
7409
7410         return err;
7411 }
7412
7413 /* tp->lock is held. */
7414 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7415                            dma_addr_t mapping, u32 maxlen_flags,
7416                            u32 nic_addr)
7417 {
7418         tg3_write_mem(tp,
7419                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7420                       ((u64) mapping >> 32));
7421         tg3_write_mem(tp,
7422                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7423                       ((u64) mapping & 0xffffffff));
7424         tg3_write_mem(tp,
7425                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7426                        maxlen_flags);
7427
7428         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7429                 tg3_write_mem(tp,
7430                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7431                               nic_addr);
7432 }
7433
7434 static void __tg3_set_rx_mode(struct net_device *);
7435 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7436 {
7437         int i;
7438
7439         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7440                 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7441                 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7442                 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7443         } else {
7444                 tw32(HOSTCC_TXCOL_TICKS, 0);
7445                 tw32(HOSTCC_TXMAX_FRAMES, 0);
7446                 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7447         }
7448
7449         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7450                 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7451                 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7452                 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7453         } else {
7454                 tw32(HOSTCC_RXCOL_TICKS, 0);
7455                 tw32(HOSTCC_RXMAX_FRAMES, 0);
7456                 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7457         }
7458
7459         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7460                 u32 val = ec->stats_block_coalesce_usecs;
7461
7462                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7463                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7464
7465                 if (!netif_carrier_ok(tp->dev))
7466                         val = 0;
7467
7468                 tw32(HOSTCC_STAT_COAL_TICKS, val);
7469         }
7470
7471         for (i = 0; i < tp->irq_cnt - 1; i++) {
7472                 u32 reg;
7473
7474                 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7475                 tw32(reg, ec->rx_coalesce_usecs);
7476                 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7477                 tw32(reg, ec->rx_max_coalesced_frames);
7478                 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7479                 tw32(reg, ec->rx_max_coalesced_frames_irq);
7480
7481                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7482                         reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7483                         tw32(reg, ec->tx_coalesce_usecs);
7484                         reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7485                         tw32(reg, ec->tx_max_coalesced_frames);
7486                         reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7487                         tw32(reg, ec->tx_max_coalesced_frames_irq);
7488                 }
7489         }
7490
7491         for (; i < tp->irq_max - 1; i++) {
7492                 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7493                 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7494                 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7495
7496                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7497                         tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7498                         tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7499                         tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7500                 }
7501         }
7502 }
7503
7504 /* tp->lock is held. */
7505 static void tg3_rings_reset(struct tg3 *tp)
7506 {
7507         int i;
7508         u32 stblk, txrcb, rxrcb, limit;
7509         struct tg3_napi *tnapi = &tp->napi[0];
7510
7511         /* Disable all transmit rings but the first. */
7512         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7513                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7514         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7515                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7516         else
7517                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7518
7519         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7520              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7521                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7522                               BDINFO_FLAGS_DISABLED);
7523
7524
7525         /* Disable all receive return rings but the first. */
7526         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7527             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7528                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7529         else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7530                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7531         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7532                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7533                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7534         else
7535                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7536
7537         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7538              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7539                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7540                               BDINFO_FLAGS_DISABLED);
7541
7542         /* Disable interrupts */
7543         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7544
7545         /* Zero mailbox registers. */
7546         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7547                 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7548                         tp->napi[i].tx_prod = 0;
7549                         tp->napi[i].tx_cons = 0;
7550                         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7551                                 tw32_mailbox(tp->napi[i].prodmbox, 0);
7552                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
7553                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7554                 }
7555                 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7556                         tw32_mailbox(tp->napi[0].prodmbox, 0);
7557         } else {
7558                 tp->napi[0].tx_prod = 0;
7559                 tp->napi[0].tx_cons = 0;
7560                 tw32_mailbox(tp->napi[0].prodmbox, 0);
7561                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7562         }
7563
7564         /* Make sure the NIC-based send BD rings are disabled. */
7565         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7566                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7567                 for (i = 0; i < 16; i++)
7568                         tw32_tx_mbox(mbox + i * 8, 0);
7569         }
7570
7571         txrcb = NIC_SRAM_SEND_RCB;
7572         rxrcb = NIC_SRAM_RCV_RET_RCB;
7573
7574         /* Clear status block in ram. */
7575         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7576
7577         /* Set status block DMA address */
7578         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7579              ((u64) tnapi->status_mapping >> 32));
7580         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7581              ((u64) tnapi->status_mapping & 0xffffffff));
7582
7583         if (tnapi->tx_ring) {
7584                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7585                                (TG3_TX_RING_SIZE <<
7586                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7587                                NIC_SRAM_TX_BUFFER_DESC);
7588                 txrcb += TG3_BDINFO_SIZE;
7589         }
7590
7591         if (tnapi->rx_rcb) {
7592                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7593                                (TG3_RX_RCB_RING_SIZE(tp) <<
7594                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7595                 rxrcb += TG3_BDINFO_SIZE;
7596         }
7597
7598         stblk = HOSTCC_STATBLCK_RING1;
7599
7600         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7601                 u64 mapping = (u64)tnapi->status_mapping;
7602                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7603                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7604
7605                 /* Clear status block in ram. */
7606                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7607
7608                 if (tnapi->tx_ring) {
7609                         tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7610                                        (TG3_TX_RING_SIZE <<
7611                                         BDINFO_FLAGS_MAXLEN_SHIFT),
7612                                        NIC_SRAM_TX_BUFFER_DESC);
7613                         txrcb += TG3_BDINFO_SIZE;
7614                 }
7615
7616                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7617                                (TG3_RX_RCB_RING_SIZE(tp) <<
7618                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7619
7620                 stblk += 8;
7621                 rxrcb += TG3_BDINFO_SIZE;
7622         }
7623 }
7624
7625 /* tp->lock is held. */
7626 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7627 {
7628         u32 val, rdmac_mode;
7629         int i, err, limit;
7630         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
7631
7632         tg3_disable_ints(tp);
7633
7634         tg3_stop_fw(tp);
7635
7636         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7637
7638         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
7639                 tg3_abort_hw(tp, 1);
7640
7641         if (reset_phy)
7642                 tg3_phy_reset(tp);
7643
7644         err = tg3_chip_reset(tp);
7645         if (err)
7646                 return err;
7647
7648         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7649
7650         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7651                 val = tr32(TG3_CPMU_CTRL);
7652                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7653                 tw32(TG3_CPMU_CTRL, val);
7654
7655                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7656                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7657                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7658                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7659
7660                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7661                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7662                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7663                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7664
7665                 val = tr32(TG3_CPMU_HST_ACC);
7666                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7667                 val |= CPMU_HST_ACC_MACCLK_6_25;
7668                 tw32(TG3_CPMU_HST_ACC, val);
7669         }
7670
7671         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7672                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7673                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7674                        PCIE_PWR_MGMT_L1_THRESH_4MS;
7675                 tw32(PCIE_PWR_MGMT_THRESH, val);
7676
7677                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7678                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7679
7680                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7681
7682                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7683                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7684         }
7685
7686         if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7687                 u32 grc_mode = tr32(GRC_MODE);
7688
7689                 /* Access the lower 1K of PL PCIE block registers. */
7690                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7691                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7692
7693                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7694                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7695                      val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7696
7697                 tw32(GRC_MODE, grc_mode);
7698         }
7699
7700         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
7701                 u32 grc_mode = tr32(GRC_MODE);
7702
7703                 /* Access the lower 1K of PL PCIE block registers. */
7704                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7705                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7706
7707                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5);
7708                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
7709                      val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
7710
7711                 tw32(GRC_MODE, grc_mode);
7712
7713                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7714                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7715                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7716                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7717         }
7718
7719         /* This works around an issue with Athlon chipsets on
7720          * B3 tigon3 silicon.  This bit has no effect on any
7721          * other revision.  But do not set this on PCI Express
7722          * chips and don't even touch the clocks if the CPMU is present.
7723          */
7724         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7725                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7726                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7727                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7728         }
7729
7730         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7731             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7732                 val = tr32(TG3PCI_PCISTATE);
7733                 val |= PCISTATE_RETRY_SAME_DMA;
7734                 tw32(TG3PCI_PCISTATE, val);
7735         }
7736
7737         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7738                 /* Allow reads and writes to the
7739                  * APE register and memory space.
7740                  */
7741                 val = tr32(TG3PCI_PCISTATE);
7742                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7743                        PCISTATE_ALLOW_APE_SHMEM_WR |
7744                        PCISTATE_ALLOW_APE_PSPACE_WR;
7745                 tw32(TG3PCI_PCISTATE, val);
7746         }
7747
7748         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7749                 /* Enable some hw fixes.  */
7750                 val = tr32(TG3PCI_MSI_DATA);
7751                 val |= (1 << 26) | (1 << 28) | (1 << 29);
7752                 tw32(TG3PCI_MSI_DATA, val);
7753         }
7754
7755         /* Descriptor ring init may make accesses to the
7756          * NIC SRAM area to setup the TX descriptors, so we
7757          * can only do this after the hardware has been
7758          * successfully reset.
7759          */
7760         err = tg3_init_rings(tp);
7761         if (err)
7762                 return err;
7763
7764         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7765             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
7766             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7767                 val = tr32(TG3PCI_DMA_RW_CTRL) &
7768                       ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7769                 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
7770                         val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
7771                 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7772         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7773                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7774                 /* This value is determined during the probe time DMA
7775                  * engine test, tg3_test_dma.
7776                  */
7777                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7778         }
7779
7780         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7781                           GRC_MODE_4X_NIC_SEND_RINGS |
7782                           GRC_MODE_NO_TX_PHDR_CSUM |
7783                           GRC_MODE_NO_RX_PHDR_CSUM);
7784         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7785
7786         /* Pseudo-header checksum is done by hardware logic and not
7787          * the offload processers, so make the chip do the pseudo-
7788          * header checksums on receive.  For transmit it is more
7789          * convenient to do the pseudo-header checksum in software
7790          * as Linux does that on transmit for us in all cases.
7791          */
7792         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7793
7794         tw32(GRC_MODE,
7795              tp->grc_mode |
7796              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7797
7798         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7799         val = tr32(GRC_MISC_CFG);
7800         val &= ~0xff;
7801         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7802         tw32(GRC_MISC_CFG, val);
7803
7804         /* Initialize MBUF/DESC pool. */
7805         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7806                 /* Do nothing.  */
7807         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7808                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7809                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7810                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7811                 else
7812                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7813                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7814                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7815         } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7816                 int fw_len;
7817
7818                 fw_len = tp->fw_len;
7819                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7820                 tw32(BUFMGR_MB_POOL_ADDR,
7821                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7822                 tw32(BUFMGR_MB_POOL_SIZE,
7823                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7824         }
7825
7826         if (tp->dev->mtu <= ETH_DATA_LEN) {
7827                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7828                      tp->bufmgr_config.mbuf_read_dma_low_water);
7829                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7830                      tp->bufmgr_config.mbuf_mac_rx_low_water);
7831                 tw32(BUFMGR_MB_HIGH_WATER,
7832                      tp->bufmgr_config.mbuf_high_water);
7833         } else {
7834                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7835                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7836                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7837                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7838                 tw32(BUFMGR_MB_HIGH_WATER,
7839                      tp->bufmgr_config.mbuf_high_water_jumbo);
7840         }
7841         tw32(BUFMGR_DMA_LOW_WATER,
7842              tp->bufmgr_config.dma_low_water);
7843         tw32(BUFMGR_DMA_HIGH_WATER,
7844              tp->bufmgr_config.dma_high_water);
7845
7846         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7847         for (i = 0; i < 2000; i++) {
7848                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7849                         break;
7850                 udelay(10);
7851         }
7852         if (i >= 2000) {
7853                 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
7854                 return -ENODEV;
7855         }
7856
7857         /* Setup replenish threshold. */
7858         val = tp->rx_pending / 8;
7859         if (val == 0)
7860                 val = 1;
7861         else if (val > tp->rx_std_max_post)
7862                 val = tp->rx_std_max_post;
7863         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7864                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7865                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7866
7867                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7868                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7869         }
7870
7871         tw32(RCVBDI_STD_THRESH, val);
7872
7873         /* Initialize TG3_BDINFO's at:
7874          *  RCVDBDI_STD_BD:     standard eth size rx ring
7875          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
7876          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
7877          *
7878          * like so:
7879          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
7880          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
7881          *                              ring attribute flags
7882          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
7883          *
7884          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7885          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7886          *
7887          * The size of each ring is fixed in the firmware, but the location is
7888          * configurable.
7889          */
7890         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7891              ((u64) tpr->rx_std_mapping >> 32));
7892         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7893              ((u64) tpr->rx_std_mapping & 0xffffffff));
7894         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
7895             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
7896                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7897                      NIC_SRAM_RX_BUFFER_DESC);
7898
7899         /* Disable the mini ring */
7900         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7901                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7902                      BDINFO_FLAGS_DISABLED);
7903
7904         /* Program the jumbo buffer descriptor ring control
7905          * blocks on those devices that have them.
7906          */
7907         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7908             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7909                 /* Setup replenish threshold. */
7910                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7911
7912                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7913                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7914                              ((u64) tpr->rx_jmb_mapping >> 32));
7915                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7916                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7917                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7918                              (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7919                              BDINFO_FLAGS_USE_EXT_RECV);
7920                         if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) ||
7921                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7922                                 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7923                                      NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7924                 } else {
7925                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7926                              BDINFO_FLAGS_DISABLED);
7927                 }
7928
7929                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7930                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
7931                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7932                         val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7933                               (TG3_RX_STD_DMA_SZ << 2);
7934                 else
7935                         val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
7936         } else
7937                 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7938
7939         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7940
7941         tpr->rx_std_prod_idx = tp->rx_pending;
7942         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
7943
7944         tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7945                           tp->rx_jumbo_pending : 0;
7946         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
7947
7948         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7949             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
7950             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7951                 tw32(STD_REPLENISH_LWM, 32);
7952                 tw32(JMB_REPLENISH_LWM, 16);
7953         }
7954
7955         tg3_rings_reset(tp);
7956
7957         /* Initialize MAC address and backoff seed. */
7958         __tg3_set_mac_addr(tp, 0);
7959
7960         /* MTU + ethernet header + FCS + optional VLAN tag */
7961         tw32(MAC_RX_MTU_SIZE,
7962              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7963
7964         /* The slot time is changed by tg3_setup_phy if we
7965          * run at gigabit with half duplex.
7966          */
7967         tw32(MAC_TX_LENGTHS,
7968              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7969              (6 << TX_LENGTHS_IPG_SHIFT) |
7970              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7971
7972         /* Receive rules. */
7973         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7974         tw32(RCVLPC_CONFIG, 0x0181);
7975
7976         /* Calculate RDMAC_MODE setting early, we need it to determine
7977          * the RCVLPC_STATE_ENABLE mask.
7978          */
7979         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7980                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7981                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7982                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7983                       RDMAC_MODE_LNGREAD_ENAB);
7984
7985         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7986             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7987                 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
7988
7989         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7990             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7991             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7992                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7993                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7994                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7995
7996         /* If statement applies to 5705 and 5750 PCI devices only */
7997         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7998              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7999             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
8000                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
8001                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
8002                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
8003                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8004                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
8005                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8006                 }
8007         }
8008
8009         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
8010                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8011
8012         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8013                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8014
8015         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
8016             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8017             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8018                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
8019
8020         /* Receive/send statistics. */
8021         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
8022                 val = tr32(RCVLPC_STATS_ENABLE);
8023                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8024                 tw32(RCVLPC_STATS_ENABLE, val);
8025         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8026                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8027                 val = tr32(RCVLPC_STATS_ENABLE);
8028                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8029                 tw32(RCVLPC_STATS_ENABLE, val);
8030         } else {
8031                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8032         }
8033         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8034         tw32(SNDDATAI_STATSENAB, 0xffffff);
8035         tw32(SNDDATAI_STATSCTRL,
8036              (SNDDATAI_SCTRL_ENABLE |
8037               SNDDATAI_SCTRL_FASTUPD));
8038
8039         /* Setup host coalescing engine. */
8040         tw32(HOSTCC_MODE, 0);
8041         for (i = 0; i < 2000; i++) {
8042                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8043                         break;
8044                 udelay(10);
8045         }
8046
8047         __tg3_set_coalesce(tp, &tp->coal);
8048
8049         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8050                 /* Status/statistics block address.  See tg3_timer,
8051                  * the tg3_periodic_fetch_stats call there, and
8052                  * tg3_get_stats to see how this works for 5705/5750 chips.
8053                  */
8054                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8055                      ((u64) tp->stats_mapping >> 32));
8056                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8057                      ((u64) tp->stats_mapping & 0xffffffff));
8058                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8059
8060                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
8061
8062                 /* Clear statistics and status block memory areas */
8063                 for (i = NIC_SRAM_STATS_BLK;
8064                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8065                      i += sizeof(u32)) {
8066                         tg3_write_mem(tp, i, 0);
8067                         udelay(40);
8068                 }
8069         }
8070
8071         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8072
8073         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8074         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8075         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8076                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8077
8078         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8079                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
8080                 /* reset to prevent losing 1st rx packet intermittently */
8081                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8082                 udelay(10);
8083         }
8084
8085         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8086                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8087         else
8088                 tp->mac_mode = 0;
8089         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8090                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
8091         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8092             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8093             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8094                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8095         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8096         udelay(40);
8097
8098         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8099          * If TG3_FLG2_IS_NIC is zero, we should read the
8100          * register to preserve the GPIO settings for LOMs. The GPIOs,
8101          * whether used as inputs or outputs, are set by boot code after
8102          * reset.
8103          */
8104         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
8105                 u32 gpio_mask;
8106
8107                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8108                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8109                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8110
8111                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8112                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8113                                      GRC_LCLCTRL_GPIO_OUTPUT3;
8114
8115                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8116                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8117
8118                 tp->grc_local_ctrl &= ~gpio_mask;
8119                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8120
8121                 /* GPIO1 must be driven high for eeprom write protect */
8122                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8123                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8124                                                GRC_LCLCTRL_GPIO_OUTPUT1);
8125         }
8126         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8127         udelay(100);
8128
8129         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
8130                 val = tr32(MSGINT_MODE);
8131                 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8132                 tw32(MSGINT_MODE, val);
8133         }
8134
8135         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8136                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8137                 udelay(40);
8138         }
8139
8140         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8141                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8142                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8143                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8144                WDMAC_MODE_LNGREAD_ENAB);
8145
8146         /* If statement applies to 5705 and 5750 PCI devices only */
8147         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8148              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8149             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
8150                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8151                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8152                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8153                         /* nothing */
8154                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8155                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8156                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8157                         val |= WDMAC_MODE_RX_ACCEL;
8158                 }
8159         }
8160
8161         /* Enable host coalescing bug fix */
8162         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8163                 val |= WDMAC_MODE_STATUS_TAG_FIX;
8164
8165         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8166                 val |= WDMAC_MODE_BURST_ALL_DATA;
8167
8168         tw32_f(WDMAC_MODE, val);
8169         udelay(40);
8170
8171         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8172                 u16 pcix_cmd;
8173
8174                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8175                                      &pcix_cmd);
8176                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8177                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8178                         pcix_cmd |= PCI_X_CMD_READ_2K;
8179                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8180                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8181                         pcix_cmd |= PCI_X_CMD_READ_2K;
8182                 }
8183                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8184                                       pcix_cmd);
8185         }
8186
8187         tw32_f(RDMAC_MODE, rdmac_mode);
8188         udelay(40);
8189
8190         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8191         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8192                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8193
8194         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8195                 tw32(SNDDATAC_MODE,
8196                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8197         else
8198                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8199
8200         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8201         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8202         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8203         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8204         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8205                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8206         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8207         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8208                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8209         tw32(SNDBDI_MODE, val);
8210         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8211
8212         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8213                 err = tg3_load_5701_a0_firmware_fix(tp);
8214                 if (err)
8215                         return err;
8216         }
8217
8218         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8219                 err = tg3_load_tso_firmware(tp);
8220                 if (err)
8221                         return err;
8222         }
8223
8224         tp->tx_mode = TX_MODE_ENABLE;
8225         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
8226             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8227                 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
8228         tw32_f(MAC_TX_MODE, tp->tx_mode);
8229         udelay(100);
8230
8231         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8232                 u32 reg = MAC_RSS_INDIR_TBL_0;
8233                 u8 *ent = (u8 *)&val;
8234
8235                 /* Setup the indirection table */
8236                 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8237                         int idx = i % sizeof(val);
8238
8239                         ent[idx] = (i % (tp->irq_cnt - 1)) + 1;
8240                         if (idx == sizeof(val) - 1) {
8241                                 tw32(reg, val);
8242                                 reg += 4;
8243                         }
8244                 }
8245
8246                 /* Setup the "secret" hash key. */
8247                 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8248                 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8249                 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8250                 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8251                 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8252                 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8253                 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8254                 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8255                 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8256                 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8257         }
8258
8259         tp->rx_mode = RX_MODE_ENABLE;
8260         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8261                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8262
8263         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8264                 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8265                                RX_MODE_RSS_ITBL_HASH_BITS_7 |
8266                                RX_MODE_RSS_IPV6_HASH_EN |
8267                                RX_MODE_RSS_TCP_IPV6_HASH_EN |
8268                                RX_MODE_RSS_IPV4_HASH_EN |
8269                                RX_MODE_RSS_TCP_IPV4_HASH_EN;
8270
8271         tw32_f(MAC_RX_MODE, tp->rx_mode);
8272         udelay(10);
8273
8274         tw32(MAC_LED_CTRL, tp->led_ctrl);
8275
8276         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8277         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8278                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8279                 udelay(10);
8280         }
8281         tw32_f(MAC_RX_MODE, tp->rx_mode);
8282         udelay(10);
8283
8284         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8285                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8286                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
8287                         /* Set drive transmission level to 1.2V  */
8288                         /* only if the signal pre-emphasis bit is not set  */
8289                         val = tr32(MAC_SERDES_CFG);
8290                         val &= 0xfffff000;
8291                         val |= 0x880;
8292                         tw32(MAC_SERDES_CFG, val);
8293                 }
8294                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8295                         tw32(MAC_SERDES_CFG, 0x616000);
8296         }
8297
8298         /* Prevent chip from dropping frames when flow control
8299          * is enabled.
8300          */
8301         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8302                 val = 1;
8303         else
8304                 val = 2;
8305         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8306
8307         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8308             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8309                 /* Use hardware link auto-negotiation */
8310                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8311         }
8312
8313         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8314             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8315                 u32 tmp;
8316
8317                 tmp = tr32(SERDES_RX_CTRL);
8318                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8319                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8320                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8321                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8322         }
8323
8324         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8325                 if (tp->link_config.phy_is_low_power) {
8326                         tp->link_config.phy_is_low_power = 0;
8327                         tp->link_config.speed = tp->link_config.orig_speed;
8328                         tp->link_config.duplex = tp->link_config.orig_duplex;
8329                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
8330                 }
8331
8332                 err = tg3_setup_phy(tp, 0);
8333                 if (err)
8334                         return err;
8335
8336                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8337                     !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
8338                         u32 tmp;
8339
8340                         /* Clear CRC stats. */
8341                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8342                                 tg3_writephy(tp, MII_TG3_TEST1,
8343                                              tmp | MII_TG3_TEST1_CRC_EN);
8344                                 tg3_readphy(tp, 0x14, &tmp);
8345                         }
8346                 }
8347         }
8348
8349         __tg3_set_rx_mode(tp->dev);
8350
8351         /* Initialize receive rules. */
8352         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
8353         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8354         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
8355         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8356
8357         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8358             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8359                 limit = 8;
8360         else
8361                 limit = 16;
8362         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8363                 limit -= 4;
8364         switch (limit) {
8365         case 16:
8366                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
8367         case 15:
8368                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
8369         case 14:
8370                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
8371         case 13:
8372                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
8373         case 12:
8374                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
8375         case 11:
8376                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
8377         case 10:
8378                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
8379         case 9:
8380                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
8381         case 8:
8382                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
8383         case 7:
8384                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
8385         case 6:
8386                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
8387         case 5:
8388                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
8389         case 4:
8390                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
8391         case 3:
8392                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
8393         case 2:
8394         case 1:
8395
8396         default:
8397                 break;
8398         }
8399
8400         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8401                 /* Write our heartbeat update interval to APE. */
8402                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8403                                 APE_HOST_HEARTBEAT_INT_DISABLE);
8404
8405         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8406
8407         return 0;
8408 }
8409
8410 /* Called at device open time to get the chip ready for
8411  * packet processing.  Invoked with tp->lock held.
8412  */
8413 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8414 {
8415         tg3_switch_clocks(tp);
8416
8417         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8418
8419         return tg3_reset_hw(tp, reset_phy);
8420 }
8421
8422 #define TG3_STAT_ADD32(PSTAT, REG) \
8423 do {    u32 __val = tr32(REG); \
8424         (PSTAT)->low += __val; \
8425         if ((PSTAT)->low < __val) \
8426                 (PSTAT)->high += 1; \
8427 } while (0)
8428
8429 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8430 {
8431         struct tg3_hw_stats *sp = tp->hw_stats;
8432
8433         if (!netif_carrier_ok(tp->dev))
8434                 return;
8435
8436         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8437         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8438         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8439         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8440         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8441         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8442         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8443         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8444         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8445         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8446         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8447         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8448         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8449
8450         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8451         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8452         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8453         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8454         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8455         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8456         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8457         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8458         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8459         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8460         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8461         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8462         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8463         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8464
8465         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8466         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8467         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8468 }
8469
8470 static void tg3_timer(unsigned long __opaque)
8471 {
8472         struct tg3 *tp = (struct tg3 *) __opaque;
8473
8474         if (tp->irq_sync)
8475                 goto restart_timer;
8476
8477         spin_lock(&tp->lock);
8478
8479         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8480                 /* All of this garbage is because when using non-tagged
8481                  * IRQ status the mailbox/status_block protocol the chip
8482                  * uses with the cpu is race prone.
8483                  */
8484                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8485                         tw32(GRC_LOCAL_CTRL,
8486                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8487                 } else {
8488                         tw32(HOSTCC_MODE, tp->coalesce_mode |
8489                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8490                 }
8491
8492                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8493                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8494                         spin_unlock(&tp->lock);
8495                         schedule_work(&tp->reset_task);
8496                         return;
8497                 }
8498         }
8499
8500         /* This part only runs once per second. */
8501         if (!--tp->timer_counter) {
8502                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8503                         tg3_periodic_fetch_stats(tp);
8504
8505                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8506                         u32 mac_stat;
8507                         int phy_event;
8508
8509                         mac_stat = tr32(MAC_STATUS);
8510
8511                         phy_event = 0;
8512                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8513                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8514                                         phy_event = 1;
8515                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8516                                 phy_event = 1;
8517
8518                         if (phy_event)
8519                                 tg3_setup_phy(tp, 0);
8520                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8521                         u32 mac_stat = tr32(MAC_STATUS);
8522                         int need_setup = 0;
8523
8524                         if (netif_carrier_ok(tp->dev) &&
8525                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8526                                 need_setup = 1;
8527                         }
8528                         if (! netif_carrier_ok(tp->dev) &&
8529                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
8530                                          MAC_STATUS_SIGNAL_DET))) {
8531                                 need_setup = 1;
8532                         }
8533                         if (need_setup) {
8534                                 if (!tp->serdes_counter) {
8535                                         tw32_f(MAC_MODE,
8536                                              (tp->mac_mode &
8537                                               ~MAC_MODE_PORT_MODE_MASK));
8538                                         udelay(40);
8539                                         tw32_f(MAC_MODE, tp->mac_mode);
8540                                         udelay(40);
8541                                 }
8542                                 tg3_setup_phy(tp, 0);
8543                         }
8544                 } else if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8545                            !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8546                         tg3_serdes_parallel_detect(tp);
8547                 }
8548
8549                 tp->timer_counter = tp->timer_multiplier;
8550         }
8551
8552         /* Heartbeat is only sent once every 2 seconds.
8553          *
8554          * The heartbeat is to tell the ASF firmware that the host
8555          * driver is still alive.  In the event that the OS crashes,
8556          * ASF needs to reset the hardware to free up the FIFO space
8557          * that may be filled with rx packets destined for the host.
8558          * If the FIFO is full, ASF will no longer function properly.
8559          *
8560          * Unintended resets have been reported on real time kernels
8561          * where the timer doesn't run on time.  Netpoll will also have
8562          * same problem.
8563          *
8564          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8565          * to check the ring condition when the heartbeat is expiring
8566          * before doing the reset.  This will prevent most unintended
8567          * resets.
8568          */
8569         if (!--tp->asf_counter) {
8570                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8571                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8572                         tg3_wait_for_event_ack(tp);
8573
8574                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8575                                       FWCMD_NICDRV_ALIVE3);
8576                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8577                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
8578                                       TG3_FW_UPDATE_TIMEOUT_SEC);
8579
8580                         tg3_generate_fw_event(tp);
8581                 }
8582                 tp->asf_counter = tp->asf_multiplier;
8583         }
8584
8585         spin_unlock(&tp->lock);
8586
8587 restart_timer:
8588         tp->timer.expires = jiffies + tp->timer_offset;
8589         add_timer(&tp->timer);
8590 }
8591
8592 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8593 {
8594         irq_handler_t fn;
8595         unsigned long flags;
8596         char *name;
8597         struct tg3_napi *tnapi = &tp->napi[irq_num];
8598
8599         if (tp->irq_cnt == 1)
8600                 name = tp->dev->name;
8601         else {
8602                 name = &tnapi->irq_lbl[0];
8603                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8604                 name[IFNAMSIZ-1] = 0;
8605         }
8606
8607         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8608                 fn = tg3_msi;
8609                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8610                         fn = tg3_msi_1shot;
8611                 flags = IRQF_SAMPLE_RANDOM;
8612         } else {
8613                 fn = tg3_interrupt;
8614                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8615                         fn = tg3_interrupt_tagged;
8616                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8617         }
8618
8619         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8620 }
8621
8622 static int tg3_test_interrupt(struct tg3 *tp)
8623 {
8624         struct tg3_napi *tnapi = &tp->napi[0];
8625         struct net_device *dev = tp->dev;
8626         int err, i, intr_ok = 0;
8627         u32 val;
8628
8629         if (!netif_running(dev))
8630                 return -ENODEV;
8631
8632         tg3_disable_ints(tp);
8633
8634         free_irq(tnapi->irq_vec, tnapi);
8635
8636         /*
8637          * Turn off MSI one shot mode.  Otherwise this test has no
8638          * observable way to know whether the interrupt was delivered.
8639          */
8640         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8641              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8642              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
8643             (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8644                 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8645                 tw32(MSGINT_MODE, val);
8646         }
8647
8648         err = request_irq(tnapi->irq_vec, tg3_test_isr,
8649                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8650         if (err)
8651                 return err;
8652
8653         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8654         tg3_enable_ints(tp);
8655
8656         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8657                tnapi->coal_now);
8658
8659         for (i = 0; i < 5; i++) {
8660                 u32 int_mbox, misc_host_ctrl;
8661
8662                 int_mbox = tr32_mailbox(tnapi->int_mbox);
8663                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8664
8665                 if ((int_mbox != 0) ||
8666                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8667                         intr_ok = 1;
8668                         break;
8669                 }
8670
8671                 msleep(10);
8672         }
8673
8674         tg3_disable_ints(tp);
8675
8676         free_irq(tnapi->irq_vec, tnapi);
8677
8678         err = tg3_request_irq(tp, 0);
8679
8680         if (err)
8681                 return err;
8682
8683         if (intr_ok) {
8684                 /* Reenable MSI one shot mode. */
8685                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8686                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8687                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
8688                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8689                         val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8690                         tw32(MSGINT_MODE, val);
8691                 }
8692                 return 0;
8693         }
8694
8695         return -EIO;
8696 }
8697
8698 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8699  * successfully restored
8700  */
8701 static int tg3_test_msi(struct tg3 *tp)
8702 {
8703         int err;
8704         u16 pci_cmd;
8705
8706         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8707                 return 0;
8708
8709         /* Turn off SERR reporting in case MSI terminates with Master
8710          * Abort.
8711          */
8712         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8713         pci_write_config_word(tp->pdev, PCI_COMMAND,
8714                               pci_cmd & ~PCI_COMMAND_SERR);
8715
8716         err = tg3_test_interrupt(tp);
8717
8718         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8719
8720         if (!err)
8721                 return 0;
8722
8723         /* other failures */
8724         if (err != -EIO)
8725                 return err;
8726
8727         /* MSI test failed, go back to INTx mode */
8728         netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
8729                     "to INTx mode. Please report this failure to the PCI "
8730                     "maintainer and include system chipset information\n");
8731
8732         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8733
8734         pci_disable_msi(tp->pdev);
8735
8736         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8737         tp->napi[0].irq_vec = tp->pdev->irq;
8738
8739         err = tg3_request_irq(tp, 0);
8740         if (err)
8741                 return err;
8742
8743         /* Need to reset the chip because the MSI cycle may have terminated
8744          * with Master Abort.
8745          */
8746         tg3_full_lock(tp, 1);
8747
8748         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8749         err = tg3_init_hw(tp, 1);
8750
8751         tg3_full_unlock(tp);
8752
8753         if (err)
8754                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8755
8756         return err;
8757 }
8758
8759 static int tg3_request_firmware(struct tg3 *tp)
8760 {
8761         const __be32 *fw_data;
8762
8763         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8764                 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
8765                            tp->fw_needed);
8766                 return -ENOENT;
8767         }
8768
8769         fw_data = (void *)tp->fw->data;
8770
8771         /* Firmware blob starts with version numbers, followed by
8772          * start address and _full_ length including BSS sections
8773          * (which must be longer than the actual data, of course
8774          */
8775
8776         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
8777         if (tp->fw_len < (tp->fw->size - 12)) {
8778                 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
8779                            tp->fw_len, tp->fw_needed);
8780                 release_firmware(tp->fw);
8781                 tp->fw = NULL;
8782                 return -EINVAL;
8783         }
8784
8785         /* We no longer need firmware; we have it. */
8786         tp->fw_needed = NULL;
8787         return 0;
8788 }
8789
8790 static bool tg3_enable_msix(struct tg3 *tp)
8791 {
8792         int i, rc, cpus = num_online_cpus();
8793         struct msix_entry msix_ent[tp->irq_max];
8794
8795         if (cpus == 1)
8796                 /* Just fallback to the simpler MSI mode. */
8797                 return false;
8798
8799         /*
8800          * We want as many rx rings enabled as there are cpus.
8801          * The first MSIX vector only deals with link interrupts, etc,
8802          * so we add one to the number of vectors we are requesting.
8803          */
8804         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8805
8806         for (i = 0; i < tp->irq_max; i++) {
8807                 msix_ent[i].entry  = i;
8808                 msix_ent[i].vector = 0;
8809         }
8810
8811         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8812         if (rc < 0) {
8813                 return false;
8814         } else if (rc != 0) {
8815                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8816                         return false;
8817                 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
8818                               tp->irq_cnt, rc);
8819                 tp->irq_cnt = rc;
8820         }
8821
8822         for (i = 0; i < tp->irq_max; i++)
8823                 tp->napi[i].irq_vec = msix_ent[i].vector;
8824
8825         tp->dev->real_num_tx_queues = 1;
8826         if (tp->irq_cnt > 1) {
8827                 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8828
8829                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8830                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
8831                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
8832                         tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8833                 }
8834         }
8835
8836         return true;
8837 }
8838
8839 static void tg3_ints_init(struct tg3 *tp)
8840 {
8841         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8842             !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8843                 /* All MSI supporting chips should support tagged
8844                  * status.  Assert that this is the case.
8845                  */
8846                 netdev_warn(tp->dev,
8847                             "MSI without TAGGED_STATUS? Not using MSI\n");
8848                 goto defcfg;
8849         }
8850
8851         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8852                 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8853         else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8854                  pci_enable_msi(tp->pdev) == 0)
8855                 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8856
8857         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8858                 u32 msi_mode = tr32(MSGINT_MODE);
8859                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8860                         msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8861                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8862         }
8863 defcfg:
8864         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8865                 tp->irq_cnt = 1;
8866                 tp->napi[0].irq_vec = tp->pdev->irq;
8867                 tp->dev->real_num_tx_queues = 1;
8868         }
8869 }
8870
8871 static void tg3_ints_fini(struct tg3 *tp)
8872 {
8873         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8874                 pci_disable_msix(tp->pdev);
8875         else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8876                 pci_disable_msi(tp->pdev);
8877         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8878         tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
8879 }
8880
8881 static int tg3_open(struct net_device *dev)
8882 {
8883         struct tg3 *tp = netdev_priv(dev);
8884         int i, err;
8885
8886         if (tp->fw_needed) {
8887                 err = tg3_request_firmware(tp);
8888                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8889                         if (err)
8890                                 return err;
8891                 } else if (err) {
8892                         netdev_warn(tp->dev, "TSO capability disabled\n");
8893                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8894                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8895                         netdev_notice(tp->dev, "TSO capability restored\n");
8896                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8897                 }
8898         }
8899
8900         netif_carrier_off(tp->dev);
8901
8902         err = tg3_set_power_state(tp, PCI_D0);
8903         if (err)
8904                 return err;
8905
8906         tg3_full_lock(tp, 0);
8907
8908         tg3_disable_ints(tp);
8909         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8910
8911         tg3_full_unlock(tp);
8912
8913         /*
8914          * Setup interrupts first so we know how
8915          * many NAPI resources to allocate
8916          */
8917         tg3_ints_init(tp);
8918
8919         /* The placement of this call is tied
8920          * to the setup and use of Host TX descriptors.
8921          */
8922         err = tg3_alloc_consistent(tp);
8923         if (err)
8924                 goto err_out1;
8925
8926         tg3_napi_enable(tp);
8927
8928         for (i = 0; i < tp->irq_cnt; i++) {
8929                 struct tg3_napi *tnapi = &tp->napi[i];
8930                 err = tg3_request_irq(tp, i);
8931                 if (err) {
8932                         for (i--; i >= 0; i--)
8933                                 free_irq(tnapi->irq_vec, tnapi);
8934                         break;
8935                 }
8936         }
8937
8938         if (err)
8939                 goto err_out2;
8940
8941         tg3_full_lock(tp, 0);
8942
8943         err = tg3_init_hw(tp, 1);
8944         if (err) {
8945                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8946                 tg3_free_rings(tp);
8947         } else {
8948                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8949                         tp->timer_offset = HZ;
8950                 else
8951                         tp->timer_offset = HZ / 10;
8952
8953                 BUG_ON(tp->timer_offset > HZ);
8954                 tp->timer_counter = tp->timer_multiplier =
8955                         (HZ / tp->timer_offset);
8956                 tp->asf_counter = tp->asf_multiplier =
8957                         ((HZ / tp->timer_offset) * 2);
8958
8959                 init_timer(&tp->timer);
8960                 tp->timer.expires = jiffies + tp->timer_offset;
8961                 tp->timer.data = (unsigned long) tp;
8962                 tp->timer.function = tg3_timer;
8963         }
8964
8965         tg3_full_unlock(tp);
8966
8967         if (err)
8968                 goto err_out3;
8969
8970         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8971                 err = tg3_test_msi(tp);
8972
8973                 if (err) {
8974                         tg3_full_lock(tp, 0);
8975                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8976                         tg3_free_rings(tp);
8977                         tg3_full_unlock(tp);
8978
8979                         goto err_out2;
8980                 }
8981
8982                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8983                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719 &&
8984                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 &&
8985                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8986                     (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8987                         u32 val = tr32(PCIE_TRANSACTION_CFG);
8988
8989                         tw32(PCIE_TRANSACTION_CFG,
8990                              val | PCIE_TRANS_CFG_1SHOT_MSI);
8991                 }
8992         }
8993
8994         tg3_phy_start(tp);
8995
8996         tg3_full_lock(tp, 0);
8997
8998         add_timer(&tp->timer);
8999         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9000         tg3_enable_ints(tp);
9001
9002         tg3_full_unlock(tp);
9003
9004         netif_tx_start_all_queues(dev);
9005
9006         return 0;
9007
9008 err_out3:
9009         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9010                 struct tg3_napi *tnapi = &tp->napi[i];
9011                 free_irq(tnapi->irq_vec, tnapi);
9012         }
9013
9014 err_out2:
9015         tg3_napi_disable(tp);
9016         tg3_free_consistent(tp);
9017
9018 err_out1:
9019         tg3_ints_fini(tp);
9020         return err;
9021 }
9022
9023 static struct net_device_stats *tg3_get_stats(struct net_device *);
9024 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9025
9026 static int tg3_close(struct net_device *dev)
9027 {
9028         int i;
9029         struct tg3 *tp = netdev_priv(dev);
9030
9031         tg3_napi_disable(tp);
9032         cancel_work_sync(&tp->reset_task);
9033
9034         netif_tx_stop_all_queues(dev);
9035
9036         del_timer_sync(&tp->timer);
9037
9038         tg3_phy_stop(tp);
9039
9040         tg3_full_lock(tp, 1);
9041
9042         tg3_disable_ints(tp);
9043
9044         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9045         tg3_free_rings(tp);
9046         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9047
9048         tg3_full_unlock(tp);
9049
9050         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9051                 struct tg3_napi *tnapi = &tp->napi[i];
9052                 free_irq(tnapi->irq_vec, tnapi);
9053         }
9054
9055         tg3_ints_fini(tp);
9056
9057         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
9058                sizeof(tp->net_stats_prev));
9059         memcpy(&tp->estats_prev, tg3_get_estats(tp),
9060                sizeof(tp->estats_prev));
9061
9062         tg3_free_consistent(tp);
9063
9064         tg3_set_power_state(tp, PCI_D3hot);
9065
9066         netif_carrier_off(tp->dev);
9067
9068         return 0;
9069 }
9070
9071 static inline unsigned long get_stat64(tg3_stat64_t *val)
9072 {
9073         unsigned long ret;
9074
9075 #if (BITS_PER_LONG == 32)
9076         ret = val->low;
9077 #else
9078         ret = ((u64)val->high << 32) | ((u64)val->low);
9079 #endif
9080         return ret;
9081 }
9082
9083 static inline u64 get_estat64(tg3_stat64_t *val)
9084 {
9085        return ((u64)val->high << 32) | ((u64)val->low);
9086 }
9087
9088 static unsigned long calc_crc_errors(struct tg3 *tp)
9089 {
9090         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9091
9092         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9093             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9094              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9095                 u32 val;
9096
9097                 spin_lock_bh(&tp->lock);
9098                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9099                         tg3_writephy(tp, MII_TG3_TEST1,
9100                                      val | MII_TG3_TEST1_CRC_EN);
9101                         tg3_readphy(tp, 0x14, &val);
9102                 } else
9103                         val = 0;
9104                 spin_unlock_bh(&tp->lock);
9105
9106                 tp->phy_crc_errors += val;
9107
9108                 return tp->phy_crc_errors;
9109         }
9110
9111         return get_stat64(&hw_stats->rx_fcs_errors);
9112 }
9113
9114 #define ESTAT_ADD(member) \
9115         estats->member =        old_estats->member + \
9116                                 get_estat64(&hw_stats->member)
9117
9118 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9119 {
9120         struct tg3_ethtool_stats *estats = &tp->estats;
9121         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9122         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9123
9124         if (!hw_stats)
9125                 return old_estats;
9126
9127         ESTAT_ADD(rx_octets);
9128         ESTAT_ADD(rx_fragments);
9129         ESTAT_ADD(rx_ucast_packets);
9130         ESTAT_ADD(rx_mcast_packets);
9131         ESTAT_ADD(rx_bcast_packets);
9132         ESTAT_ADD(rx_fcs_errors);
9133         ESTAT_ADD(rx_align_errors);
9134         ESTAT_ADD(rx_xon_pause_rcvd);
9135         ESTAT_ADD(rx_xoff_pause_rcvd);
9136         ESTAT_ADD(rx_mac_ctrl_rcvd);
9137         ESTAT_ADD(rx_xoff_entered);
9138         ESTAT_ADD(rx_frame_too_long_errors);
9139         ESTAT_ADD(rx_jabbers);
9140         ESTAT_ADD(rx_undersize_packets);
9141         ESTAT_ADD(rx_in_length_errors);
9142         ESTAT_ADD(rx_out_length_errors);
9143         ESTAT_ADD(rx_64_or_less_octet_packets);
9144         ESTAT_ADD(rx_65_to_127_octet_packets);
9145         ESTAT_ADD(rx_128_to_255_octet_packets);
9146         ESTAT_ADD(rx_256_to_511_octet_packets);
9147         ESTAT_ADD(rx_512_to_1023_octet_packets);
9148         ESTAT_ADD(rx_1024_to_1522_octet_packets);
9149         ESTAT_ADD(rx_1523_to_2047_octet_packets);
9150         ESTAT_ADD(rx_2048_to_4095_octet_packets);
9151         ESTAT_ADD(rx_4096_to_8191_octet_packets);
9152         ESTAT_ADD(rx_8192_to_9022_octet_packets);
9153
9154         ESTAT_ADD(tx_octets);
9155         ESTAT_ADD(tx_collisions);
9156         ESTAT_ADD(tx_xon_sent);
9157         ESTAT_ADD(tx_xoff_sent);
9158         ESTAT_ADD(tx_flow_control);
9159         ESTAT_ADD(tx_mac_errors);
9160         ESTAT_ADD(tx_single_collisions);
9161         ESTAT_ADD(tx_mult_collisions);
9162         ESTAT_ADD(tx_deferred);
9163         ESTAT_ADD(tx_excessive_collisions);
9164         ESTAT_ADD(tx_late_collisions);
9165         ESTAT_ADD(tx_collide_2times);
9166         ESTAT_ADD(tx_collide_3times);
9167         ESTAT_ADD(tx_collide_4times);
9168         ESTAT_ADD(tx_collide_5times);
9169         ESTAT_ADD(tx_collide_6times);
9170         ESTAT_ADD(tx_collide_7times);
9171         ESTAT_ADD(tx_collide_8times);
9172         ESTAT_ADD(tx_collide_9times);
9173         ESTAT_ADD(tx_collide_10times);
9174         ESTAT_ADD(tx_collide_11times);
9175         ESTAT_ADD(tx_collide_12times);
9176         ESTAT_ADD(tx_collide_13times);
9177         ESTAT_ADD(tx_collide_14times);
9178         ESTAT_ADD(tx_collide_15times);
9179         ESTAT_ADD(tx_ucast_packets);
9180         ESTAT_ADD(tx_mcast_packets);
9181         ESTAT_ADD(tx_bcast_packets);
9182         ESTAT_ADD(tx_carrier_sense_errors);
9183         ESTAT_ADD(tx_discards);
9184         ESTAT_ADD(tx_errors);
9185
9186         ESTAT_ADD(dma_writeq_full);
9187         ESTAT_ADD(dma_write_prioq_full);
9188         ESTAT_ADD(rxbds_empty);
9189         ESTAT_ADD(rx_discards);
9190         ESTAT_ADD(rx_errors);
9191         ESTAT_ADD(rx_threshold_hit);
9192
9193         ESTAT_ADD(dma_readq_full);
9194         ESTAT_ADD(dma_read_prioq_full);
9195         ESTAT_ADD(tx_comp_queue_full);
9196
9197         ESTAT_ADD(ring_set_send_prod_index);
9198         ESTAT_ADD(ring_status_update);
9199         ESTAT_ADD(nic_irqs);
9200         ESTAT_ADD(nic_avoided_irqs);
9201         ESTAT_ADD(nic_tx_threshold_hit);
9202
9203         return estats;
9204 }
9205
9206 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
9207 {
9208         struct tg3 *tp = netdev_priv(dev);
9209         struct net_device_stats *stats = &tp->net_stats;
9210         struct net_device_stats *old_stats = &tp->net_stats_prev;
9211         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9212
9213         if (!hw_stats)
9214                 return old_stats;
9215
9216         stats->rx_packets = old_stats->rx_packets +
9217                 get_stat64(&hw_stats->rx_ucast_packets) +
9218                 get_stat64(&hw_stats->rx_mcast_packets) +
9219                 get_stat64(&hw_stats->rx_bcast_packets);
9220
9221         stats->tx_packets = old_stats->tx_packets +
9222                 get_stat64(&hw_stats->tx_ucast_packets) +
9223                 get_stat64(&hw_stats->tx_mcast_packets) +
9224                 get_stat64(&hw_stats->tx_bcast_packets);
9225
9226         stats->rx_bytes = old_stats->rx_bytes +
9227                 get_stat64(&hw_stats->rx_octets);
9228         stats->tx_bytes = old_stats->tx_bytes +
9229                 get_stat64(&hw_stats->tx_octets);
9230
9231         stats->rx_errors = old_stats->rx_errors +
9232                 get_stat64(&hw_stats->rx_errors);
9233         stats->tx_errors = old_stats->tx_errors +
9234                 get_stat64(&hw_stats->tx_errors) +
9235                 get_stat64(&hw_stats->tx_mac_errors) +
9236                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9237                 get_stat64(&hw_stats->tx_discards);
9238
9239         stats->multicast = old_stats->multicast +
9240                 get_stat64(&hw_stats->rx_mcast_packets);
9241         stats->collisions = old_stats->collisions +
9242                 get_stat64(&hw_stats->tx_collisions);
9243
9244         stats->rx_length_errors = old_stats->rx_length_errors +
9245                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9246                 get_stat64(&hw_stats->rx_undersize_packets);
9247
9248         stats->rx_over_errors = old_stats->rx_over_errors +
9249                 get_stat64(&hw_stats->rxbds_empty);
9250         stats->rx_frame_errors = old_stats->rx_frame_errors +
9251                 get_stat64(&hw_stats->rx_align_errors);
9252         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9253                 get_stat64(&hw_stats->tx_discards);
9254         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9255                 get_stat64(&hw_stats->tx_carrier_sense_errors);
9256
9257         stats->rx_crc_errors = old_stats->rx_crc_errors +
9258                 calc_crc_errors(tp);
9259
9260         stats->rx_missed_errors = old_stats->rx_missed_errors +
9261                 get_stat64(&hw_stats->rx_discards);
9262
9263         return stats;
9264 }
9265
9266 static inline u32 calc_crc(unsigned char *buf, int len)
9267 {
9268         u32 reg;
9269         u32 tmp;
9270         int j, k;
9271
9272         reg = 0xffffffff;
9273
9274         for (j = 0; j < len; j++) {
9275                 reg ^= buf[j];
9276
9277                 for (k = 0; k < 8; k++) {
9278                         tmp = reg & 0x01;
9279
9280                         reg >>= 1;
9281
9282                         if (tmp)
9283                                 reg ^= 0xedb88320;
9284                 }
9285         }
9286
9287         return ~reg;
9288 }
9289
9290 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9291 {
9292         /* accept or reject all multicast frames */
9293         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9294         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9295         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9296         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9297 }
9298
9299 static void __tg3_set_rx_mode(struct net_device *dev)
9300 {
9301         struct tg3 *tp = netdev_priv(dev);
9302         u32 rx_mode;
9303
9304         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9305                                   RX_MODE_KEEP_VLAN_TAG);
9306
9307         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9308          * flag clear.
9309          */
9310 #if TG3_VLAN_TAG_USED
9311         if (!tp->vlgrp &&
9312             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9313                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9314 #else
9315         /* By definition, VLAN is disabled always in this
9316          * case.
9317          */
9318         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9319                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9320 #endif
9321
9322         if (dev->flags & IFF_PROMISC) {
9323                 /* Promiscuous mode. */
9324                 rx_mode |= RX_MODE_PROMISC;
9325         } else if (dev->flags & IFF_ALLMULTI) {
9326                 /* Accept all multicast. */
9327                 tg3_set_multi(tp, 1);
9328         } else if (netdev_mc_empty(dev)) {
9329                 /* Reject all multicast. */
9330                 tg3_set_multi(tp, 0);
9331         } else {
9332                 /* Accept one or more multicast(s). */
9333                 struct netdev_hw_addr *ha;
9334                 u32 mc_filter[4] = { 0, };
9335                 u32 regidx;
9336                 u32 bit;
9337                 u32 crc;
9338
9339                 netdev_for_each_mc_addr(ha, dev) {
9340                         crc = calc_crc(ha->addr, ETH_ALEN);
9341                         bit = ~crc & 0x7f;
9342                         regidx = (bit & 0x60) >> 5;
9343                         bit &= 0x1f;
9344                         mc_filter[regidx] |= (1 << bit);
9345                 }
9346
9347                 tw32(MAC_HASH_REG_0, mc_filter[0]);
9348                 tw32(MAC_HASH_REG_1, mc_filter[1]);
9349                 tw32(MAC_HASH_REG_2, mc_filter[2]);
9350                 tw32(MAC_HASH_REG_3, mc_filter[3]);
9351         }
9352
9353         if (rx_mode != tp->rx_mode) {
9354                 tp->rx_mode = rx_mode;
9355                 tw32_f(MAC_RX_MODE, rx_mode);
9356                 udelay(10);
9357         }
9358 }
9359
9360 static void tg3_set_rx_mode(struct net_device *dev)
9361 {
9362         struct tg3 *tp = netdev_priv(dev);
9363
9364         if (!netif_running(dev))
9365                 return;
9366
9367         tg3_full_lock(tp, 0);
9368         __tg3_set_rx_mode(dev);
9369         tg3_full_unlock(tp);
9370 }
9371
9372 #define TG3_REGDUMP_LEN         (32 * 1024)
9373
9374 static int tg3_get_regs_len(struct net_device *dev)
9375 {
9376         return TG3_REGDUMP_LEN;
9377 }
9378
9379 static void tg3_get_regs(struct net_device *dev,
9380                 struct ethtool_regs *regs, void *_p)
9381 {
9382         u32 *p = _p;
9383         struct tg3 *tp = netdev_priv(dev);
9384         u8 *orig_p = _p;
9385         int i;
9386
9387         regs->version = 0;
9388
9389         memset(p, 0, TG3_REGDUMP_LEN);
9390
9391         if (tp->link_config.phy_is_low_power)
9392                 return;
9393
9394         tg3_full_lock(tp, 0);
9395
9396 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
9397 #define GET_REG32_LOOP(base,len)                \
9398 do {    p = (u32 *)(orig_p + (base));           \
9399         for (i = 0; i < len; i += 4)            \
9400                 __GET_REG32((base) + i);        \
9401 } while (0)
9402 #define GET_REG32_1(reg)                        \
9403 do {    p = (u32 *)(orig_p + (reg));            \
9404         __GET_REG32((reg));                     \
9405 } while (0)
9406
9407         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9408         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9409         GET_REG32_LOOP(MAC_MODE, 0x4f0);
9410         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9411         GET_REG32_1(SNDDATAC_MODE);
9412         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9413         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9414         GET_REG32_1(SNDBDC_MODE);
9415         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9416         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9417         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9418         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9419         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9420         GET_REG32_1(RCVDCC_MODE);
9421         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9422         GET_REG32_LOOP(RCVCC_MODE, 0x14);
9423         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9424         GET_REG32_1(MBFREE_MODE);
9425         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9426         GET_REG32_LOOP(MEMARB_MODE, 0x10);
9427         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9428         GET_REG32_LOOP(RDMAC_MODE, 0x08);
9429         GET_REG32_LOOP(WDMAC_MODE, 0x08);
9430         GET_REG32_1(RX_CPU_MODE);
9431         GET_REG32_1(RX_CPU_STATE);
9432         GET_REG32_1(RX_CPU_PGMCTR);
9433         GET_REG32_1(RX_CPU_HWBKPT);
9434         GET_REG32_1(TX_CPU_MODE);
9435         GET_REG32_1(TX_CPU_STATE);
9436         GET_REG32_1(TX_CPU_PGMCTR);
9437         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9438         GET_REG32_LOOP(FTQ_RESET, 0x120);
9439         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9440         GET_REG32_1(DMAC_MODE);
9441         GET_REG32_LOOP(GRC_MODE, 0x4c);
9442         if (tp->tg3_flags & TG3_FLAG_NVRAM)
9443                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9444
9445 #undef __GET_REG32
9446 #undef GET_REG32_LOOP
9447 #undef GET_REG32_1
9448
9449         tg3_full_unlock(tp);
9450 }
9451
9452 static int tg3_get_eeprom_len(struct net_device *dev)
9453 {
9454         struct tg3 *tp = netdev_priv(dev);
9455
9456         return tp->nvram_size;
9457 }
9458
9459 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9460 {
9461         struct tg3 *tp = netdev_priv(dev);
9462         int ret;
9463         u8  *pd;
9464         u32 i, offset, len, b_offset, b_count;
9465         __be32 val;
9466
9467         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9468                 return -EINVAL;
9469
9470         if (tp->link_config.phy_is_low_power)
9471                 return -EAGAIN;
9472
9473         offset = eeprom->offset;
9474         len = eeprom->len;
9475         eeprom->len = 0;
9476
9477         eeprom->magic = TG3_EEPROM_MAGIC;
9478
9479         if (offset & 3) {
9480                 /* adjustments to start on required 4 byte boundary */
9481                 b_offset = offset & 3;
9482                 b_count = 4 - b_offset;
9483                 if (b_count > len) {
9484                         /* i.e. offset=1 len=2 */
9485                         b_count = len;
9486                 }
9487                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9488                 if (ret)
9489                         return ret;
9490                 memcpy(data, ((char*)&val) + b_offset, b_count);
9491                 len -= b_count;
9492                 offset += b_count;
9493                 eeprom->len += b_count;
9494         }
9495
9496         /* read bytes upto the last 4 byte boundary */
9497         pd = &data[eeprom->len];
9498         for (i = 0; i < (len - (len & 3)); i += 4) {
9499                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9500                 if (ret) {
9501                         eeprom->len += i;
9502                         return ret;
9503                 }
9504                 memcpy(pd + i, &val, 4);
9505         }
9506         eeprom->len += i;
9507
9508         if (len & 3) {
9509                 /* read last bytes not ending on 4 byte boundary */
9510                 pd = &data[eeprom->len];
9511                 b_count = len & 3;
9512                 b_offset = offset + len - b_count;
9513                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9514                 if (ret)
9515                         return ret;
9516                 memcpy(pd, &val, b_count);
9517                 eeprom->len += b_count;
9518         }
9519         return 0;
9520 }
9521
9522 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9523
9524 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9525 {
9526         struct tg3 *tp = netdev_priv(dev);
9527         int ret;
9528         u32 offset, len, b_offset, odd_len;
9529         u8 *buf;
9530         __be32 start, end;
9531
9532         if (tp->link_config.phy_is_low_power)
9533                 return -EAGAIN;
9534
9535         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9536             eeprom->magic != TG3_EEPROM_MAGIC)
9537                 return -EINVAL;
9538
9539         offset = eeprom->offset;
9540         len = eeprom->len;
9541
9542         if ((b_offset = (offset & 3))) {
9543                 /* adjustments to start on required 4 byte boundary */
9544                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9545                 if (ret)
9546                         return ret;
9547                 len += b_offset;
9548                 offset &= ~3;
9549                 if (len < 4)
9550                         len = 4;
9551         }
9552
9553         odd_len = 0;
9554         if (len & 3) {
9555                 /* adjustments to end on required 4 byte boundary */
9556                 odd_len = 1;
9557                 len = (len + 3) & ~3;
9558                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9559                 if (ret)
9560                         return ret;
9561         }
9562
9563         buf = data;
9564         if (b_offset || odd_len) {
9565                 buf = kmalloc(len, GFP_KERNEL);
9566                 if (!buf)
9567                         return -ENOMEM;
9568                 if (b_offset)
9569                         memcpy(buf, &start, 4);
9570                 if (odd_len)
9571                         memcpy(buf+len-4, &end, 4);
9572                 memcpy(buf + b_offset, data, eeprom->len);
9573         }
9574
9575         ret = tg3_nvram_write_block(tp, offset, len, buf);
9576
9577         if (buf != data)
9578                 kfree(buf);
9579
9580         return ret;
9581 }
9582
9583 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9584 {
9585         struct tg3 *tp = netdev_priv(dev);
9586
9587         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9588                 struct phy_device *phydev;
9589                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9590                         return -EAGAIN;
9591                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9592                 return phy_ethtool_gset(phydev, cmd);
9593         }
9594
9595         cmd->supported = (SUPPORTED_Autoneg);
9596
9597         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9598                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9599                                    SUPPORTED_1000baseT_Full);
9600
9601         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
9602                 cmd->supported |= (SUPPORTED_100baseT_Half |
9603                                   SUPPORTED_100baseT_Full |
9604                                   SUPPORTED_10baseT_Half |
9605                                   SUPPORTED_10baseT_Full |
9606                                   SUPPORTED_TP);
9607                 cmd->port = PORT_TP;
9608         } else {
9609                 cmd->supported |= SUPPORTED_FIBRE;
9610                 cmd->port = PORT_FIBRE;
9611         }
9612
9613         cmd->advertising = tp->link_config.advertising;
9614         if (netif_running(dev)) {
9615                 cmd->speed = tp->link_config.active_speed;
9616                 cmd->duplex = tp->link_config.active_duplex;
9617         }
9618         cmd->phy_address = tp->phy_addr;
9619         cmd->transceiver = XCVR_INTERNAL;
9620         cmd->autoneg = tp->link_config.autoneg;
9621         cmd->maxtxpkt = 0;
9622         cmd->maxrxpkt = 0;
9623         return 0;
9624 }
9625
9626 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9627 {
9628         struct tg3 *tp = netdev_priv(dev);
9629
9630         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9631                 struct phy_device *phydev;
9632                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9633                         return -EAGAIN;
9634                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9635                 return phy_ethtool_sset(phydev, cmd);
9636         }
9637
9638         if (cmd->autoneg != AUTONEG_ENABLE &&
9639             cmd->autoneg != AUTONEG_DISABLE)
9640                 return -EINVAL;
9641
9642         if (cmd->autoneg == AUTONEG_DISABLE &&
9643             cmd->duplex != DUPLEX_FULL &&
9644             cmd->duplex != DUPLEX_HALF)
9645                 return -EINVAL;
9646
9647         if (cmd->autoneg == AUTONEG_ENABLE) {
9648                 u32 mask = ADVERTISED_Autoneg |
9649                            ADVERTISED_Pause |
9650                            ADVERTISED_Asym_Pause;
9651
9652                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9653                         mask |= ADVERTISED_1000baseT_Half |
9654                                 ADVERTISED_1000baseT_Full;
9655
9656                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9657                         mask |= ADVERTISED_100baseT_Half |
9658                                 ADVERTISED_100baseT_Full |
9659                                 ADVERTISED_10baseT_Half |
9660                                 ADVERTISED_10baseT_Full |
9661                                 ADVERTISED_TP;
9662                 else
9663                         mask |= ADVERTISED_FIBRE;
9664
9665                 if (cmd->advertising & ~mask)
9666                         return -EINVAL;
9667
9668                 mask &= (ADVERTISED_1000baseT_Half |
9669                          ADVERTISED_1000baseT_Full |
9670                          ADVERTISED_100baseT_Half |
9671                          ADVERTISED_100baseT_Full |
9672                          ADVERTISED_10baseT_Half |
9673                          ADVERTISED_10baseT_Full);
9674
9675                 cmd->advertising &= mask;
9676         } else {
9677                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9678                         if (cmd->speed != SPEED_1000)
9679                                 return -EINVAL;
9680
9681                         if (cmd->duplex != DUPLEX_FULL)
9682                                 return -EINVAL;
9683                 } else {
9684                         if (cmd->speed != SPEED_100 &&
9685                             cmd->speed != SPEED_10)
9686                                 return -EINVAL;
9687                 }
9688         }
9689
9690         tg3_full_lock(tp, 0);
9691
9692         tp->link_config.autoneg = cmd->autoneg;
9693         if (cmd->autoneg == AUTONEG_ENABLE) {
9694                 tp->link_config.advertising = (cmd->advertising |
9695                                               ADVERTISED_Autoneg);
9696                 tp->link_config.speed = SPEED_INVALID;
9697                 tp->link_config.duplex = DUPLEX_INVALID;
9698         } else {
9699                 tp->link_config.advertising = 0;
9700                 tp->link_config.speed = cmd->speed;
9701                 tp->link_config.duplex = cmd->duplex;
9702         }
9703
9704         tp->link_config.orig_speed = tp->link_config.speed;
9705         tp->link_config.orig_duplex = tp->link_config.duplex;
9706         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9707
9708         if (netif_running(dev))
9709                 tg3_setup_phy(tp, 1);
9710
9711         tg3_full_unlock(tp);
9712
9713         return 0;
9714 }
9715
9716 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9717 {
9718         struct tg3 *tp = netdev_priv(dev);
9719
9720         strcpy(info->driver, DRV_MODULE_NAME);
9721         strcpy(info->version, DRV_MODULE_VERSION);
9722         strcpy(info->fw_version, tp->fw_ver);
9723         strcpy(info->bus_info, pci_name(tp->pdev));
9724 }
9725
9726 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9727 {
9728         struct tg3 *tp = netdev_priv(dev);
9729
9730         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9731             device_can_wakeup(&tp->pdev->dev))
9732                 wol->supported = WAKE_MAGIC;
9733         else
9734                 wol->supported = 0;
9735         wol->wolopts = 0;
9736         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9737             device_can_wakeup(&tp->pdev->dev))
9738                 wol->wolopts = WAKE_MAGIC;
9739         memset(&wol->sopass, 0, sizeof(wol->sopass));
9740 }
9741
9742 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9743 {
9744         struct tg3 *tp = netdev_priv(dev);
9745         struct device *dp = &tp->pdev->dev;
9746
9747         if (wol->wolopts & ~WAKE_MAGIC)
9748                 return -EINVAL;
9749         if ((wol->wolopts & WAKE_MAGIC) &&
9750             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9751                 return -EINVAL;
9752
9753         spin_lock_bh(&tp->lock);
9754         if (wol->wolopts & WAKE_MAGIC) {
9755                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9756                 device_set_wakeup_enable(dp, true);
9757         } else {
9758                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9759                 device_set_wakeup_enable(dp, false);
9760         }
9761         spin_unlock_bh(&tp->lock);
9762
9763         return 0;
9764 }
9765
9766 static u32 tg3_get_msglevel(struct net_device *dev)
9767 {
9768         struct tg3 *tp = netdev_priv(dev);
9769         return tp->msg_enable;
9770 }
9771
9772 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9773 {
9774         struct tg3 *tp = netdev_priv(dev);
9775         tp->msg_enable = value;
9776 }
9777
9778 static int tg3_set_tso(struct net_device *dev, u32 value)
9779 {
9780         struct tg3 *tp = netdev_priv(dev);
9781
9782         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9783                 if (value)
9784                         return -EINVAL;
9785                 return 0;
9786         }
9787         if ((dev->features & NETIF_F_IPV6_CSUM) &&
9788             ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9789              (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9790                 if (value) {
9791                         dev->features |= NETIF_F_TSO6;
9792                         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9793                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9794                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9795                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9796                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9797                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9798                                 dev->features |= NETIF_F_TSO_ECN;
9799                 } else
9800                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9801         }
9802         return ethtool_op_set_tso(dev, value);
9803 }
9804
9805 static int tg3_nway_reset(struct net_device *dev)
9806 {
9807         struct tg3 *tp = netdev_priv(dev);
9808         int r;
9809
9810         if (!netif_running(dev))
9811                 return -EAGAIN;
9812
9813         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9814                 return -EINVAL;
9815
9816         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9817                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9818                         return -EAGAIN;
9819                 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9820         } else {
9821                 u32 bmcr;
9822
9823                 spin_lock_bh(&tp->lock);
9824                 r = -EINVAL;
9825                 tg3_readphy(tp, MII_BMCR, &bmcr);
9826                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9827                     ((bmcr & BMCR_ANENABLE) ||
9828                      (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9829                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9830                                                    BMCR_ANENABLE);
9831                         r = 0;
9832                 }
9833                 spin_unlock_bh(&tp->lock);
9834         }
9835
9836         return r;
9837 }
9838
9839 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9840 {
9841         struct tg3 *tp = netdev_priv(dev);
9842
9843         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9844         ering->rx_mini_max_pending = 0;
9845         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9846                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9847         else
9848                 ering->rx_jumbo_max_pending = 0;
9849
9850         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9851
9852         ering->rx_pending = tp->rx_pending;
9853         ering->rx_mini_pending = 0;
9854         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9855                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9856         else
9857                 ering->rx_jumbo_pending = 0;
9858
9859         ering->tx_pending = tp->napi[0].tx_pending;
9860 }
9861
9862 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9863 {
9864         struct tg3 *tp = netdev_priv(dev);
9865         int i, irq_sync = 0, err = 0;
9866
9867         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9868             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9869             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9870             (ering->tx_pending <= MAX_SKB_FRAGS) ||
9871             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9872              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9873                 return -EINVAL;
9874
9875         if (netif_running(dev)) {
9876                 tg3_phy_stop(tp);
9877                 tg3_netif_stop(tp);
9878                 irq_sync = 1;
9879         }
9880
9881         tg3_full_lock(tp, irq_sync);
9882
9883         tp->rx_pending = ering->rx_pending;
9884
9885         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9886             tp->rx_pending > 63)
9887                 tp->rx_pending = 63;
9888         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9889
9890         for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9891                 tp->napi[i].tx_pending = ering->tx_pending;
9892
9893         if (netif_running(dev)) {
9894                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9895                 err = tg3_restart_hw(tp, 1);
9896                 if (!err)
9897                         tg3_netif_start(tp);
9898         }
9899
9900         tg3_full_unlock(tp);
9901
9902         if (irq_sync && !err)
9903                 tg3_phy_start(tp);
9904
9905         return err;
9906 }
9907
9908 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9909 {
9910         struct tg3 *tp = netdev_priv(dev);
9911
9912         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9913
9914         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9915                 epause->rx_pause = 1;
9916         else
9917                 epause->rx_pause = 0;
9918
9919         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9920                 epause->tx_pause = 1;
9921         else
9922                 epause->tx_pause = 0;
9923 }
9924
9925 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9926 {
9927         struct tg3 *tp = netdev_priv(dev);
9928         int err = 0;
9929
9930         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9931                 u32 newadv;
9932                 struct phy_device *phydev;
9933
9934                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9935
9936                 if (!(phydev->supported & SUPPORTED_Pause) ||
9937                     (!(phydev->supported & SUPPORTED_Asym_Pause) &&
9938                      ((epause->rx_pause && !epause->tx_pause) ||
9939                       (!epause->rx_pause && epause->tx_pause))))
9940                         return -EINVAL;
9941
9942                 tp->link_config.flowctrl = 0;
9943                 if (epause->rx_pause) {
9944                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
9945
9946                         if (epause->tx_pause) {
9947                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9948                                 newadv = ADVERTISED_Pause;
9949                         } else
9950                                 newadv = ADVERTISED_Pause |
9951                                          ADVERTISED_Asym_Pause;
9952                 } else if (epause->tx_pause) {
9953                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
9954                         newadv = ADVERTISED_Asym_Pause;
9955                 } else
9956                         newadv = 0;
9957
9958                 if (epause->autoneg)
9959                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9960                 else
9961                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9962
9963                 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9964                         u32 oldadv = phydev->advertising &
9965                                      (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
9966                         if (oldadv != newadv) {
9967                                 phydev->advertising &=
9968                                         ~(ADVERTISED_Pause |
9969                                           ADVERTISED_Asym_Pause);
9970                                 phydev->advertising |= newadv;
9971                                 if (phydev->autoneg) {
9972                                         /*
9973                                          * Always renegotiate the link to
9974                                          * inform our link partner of our
9975                                          * flow control settings, even if the
9976                                          * flow control is forced.  Let
9977                                          * tg3_adjust_link() do the final
9978                                          * flow control setup.
9979                                          */
9980                                         return phy_start_aneg(phydev);
9981                                 }
9982                         }
9983
9984                         if (!epause->autoneg)
9985                                 tg3_setup_flow_control(tp, 0, 0);
9986                 } else {
9987                         tp->link_config.orig_advertising &=
9988                                         ~(ADVERTISED_Pause |
9989                                           ADVERTISED_Asym_Pause);
9990                         tp->link_config.orig_advertising |= newadv;
9991                 }
9992         } else {
9993                 int irq_sync = 0;
9994
9995                 if (netif_running(dev)) {
9996                         tg3_netif_stop(tp);
9997                         irq_sync = 1;
9998                 }
9999
10000                 tg3_full_lock(tp, irq_sync);
10001
10002                 if (epause->autoneg)
10003                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10004                 else
10005                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10006                 if (epause->rx_pause)
10007                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
10008                 else
10009                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10010                 if (epause->tx_pause)
10011                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
10012                 else
10013                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10014
10015                 if (netif_running(dev)) {
10016                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10017                         err = tg3_restart_hw(tp, 1);
10018                         if (!err)
10019                                 tg3_netif_start(tp);
10020                 }
10021
10022                 tg3_full_unlock(tp);
10023         }
10024
10025         return err;
10026 }
10027
10028 static u32 tg3_get_rx_csum(struct net_device *dev)
10029 {
10030         struct tg3 *tp = netdev_priv(dev);
10031         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10032 }
10033
10034 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10035 {
10036         struct tg3 *tp = netdev_priv(dev);
10037
10038         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10039                 if (data != 0)
10040                         return -EINVAL;
10041                 return 0;
10042         }
10043
10044         spin_lock_bh(&tp->lock);
10045         if (data)
10046                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10047         else
10048                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10049         spin_unlock_bh(&tp->lock);
10050
10051         return 0;
10052 }
10053
10054 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10055 {
10056         struct tg3 *tp = netdev_priv(dev);
10057
10058         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10059                 if (data != 0)
10060                         return -EINVAL;
10061                 return 0;
10062         }
10063
10064         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10065                 ethtool_op_set_tx_ipv6_csum(dev, data);
10066         else
10067                 ethtool_op_set_tx_csum(dev, data);
10068
10069         return 0;
10070 }
10071
10072 static int tg3_get_sset_count(struct net_device *dev, int sset)
10073 {
10074         switch (sset) {
10075         case ETH_SS_TEST:
10076                 return TG3_NUM_TEST;
10077         case ETH_SS_STATS:
10078                 return TG3_NUM_STATS;
10079         default:
10080                 return -EOPNOTSUPP;
10081         }
10082 }
10083
10084 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
10085 {
10086         switch (stringset) {
10087         case ETH_SS_STATS:
10088                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10089                 break;
10090         case ETH_SS_TEST:
10091                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10092                 break;
10093         default:
10094                 WARN_ON(1);     /* we need a WARN() */
10095                 break;
10096         }
10097 }
10098
10099 static int tg3_phys_id(struct net_device *dev, u32 data)
10100 {
10101         struct tg3 *tp = netdev_priv(dev);
10102         int i;
10103
10104         if (!netif_running(tp->dev))
10105                 return -EAGAIN;
10106
10107         if (data == 0)
10108                 data = UINT_MAX / 2;
10109
10110         for (i = 0; i < (data * 2); i++) {
10111                 if ((i % 2) == 0)
10112                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10113                                            LED_CTRL_1000MBPS_ON |
10114                                            LED_CTRL_100MBPS_ON |
10115                                            LED_CTRL_10MBPS_ON |
10116                                            LED_CTRL_TRAFFIC_OVERRIDE |
10117                                            LED_CTRL_TRAFFIC_BLINK |
10118                                            LED_CTRL_TRAFFIC_LED);
10119
10120                 else
10121                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10122                                            LED_CTRL_TRAFFIC_OVERRIDE);
10123
10124                 if (msleep_interruptible(500))
10125                         break;
10126         }
10127         tw32(MAC_LED_CTRL, tp->led_ctrl);
10128         return 0;
10129 }
10130
10131 static void tg3_get_ethtool_stats(struct net_device *dev,
10132                                    struct ethtool_stats *estats, u64 *tmp_stats)
10133 {
10134         struct tg3 *tp = netdev_priv(dev);
10135         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10136 }
10137
10138 #define NVRAM_TEST_SIZE 0x100
10139 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
10140 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
10141 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
10142 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10143 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10144
10145 static int tg3_test_nvram(struct tg3 *tp)
10146 {
10147         u32 csum, magic;
10148         __be32 *buf;
10149         int i, j, k, err = 0, size;
10150
10151         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10152                 return 0;
10153
10154         if (tg3_nvram_read(tp, 0, &magic) != 0)
10155                 return -EIO;
10156
10157         if (magic == TG3_EEPROM_MAGIC)
10158                 size = NVRAM_TEST_SIZE;
10159         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10160                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10161                     TG3_EEPROM_SB_FORMAT_1) {
10162                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10163                         case TG3_EEPROM_SB_REVISION_0:
10164                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10165                                 break;
10166                         case TG3_EEPROM_SB_REVISION_2:
10167                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10168                                 break;
10169                         case TG3_EEPROM_SB_REVISION_3:
10170                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10171                                 break;
10172                         default:
10173                                 return 0;
10174                         }
10175                 } else
10176                         return 0;
10177         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10178                 size = NVRAM_SELFBOOT_HW_SIZE;
10179         else
10180                 return -EIO;
10181
10182         buf = kmalloc(size, GFP_KERNEL);
10183         if (buf == NULL)
10184                 return -ENOMEM;
10185
10186         err = -EIO;
10187         for (i = 0, j = 0; i < size; i += 4, j++) {
10188                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10189                 if (err)
10190                         break;
10191         }
10192         if (i < size)
10193                 goto out;
10194
10195         /* Selfboot format */
10196         magic = be32_to_cpu(buf[0]);
10197         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10198             TG3_EEPROM_MAGIC_FW) {
10199                 u8 *buf8 = (u8 *) buf, csum8 = 0;
10200
10201                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10202                     TG3_EEPROM_SB_REVISION_2) {
10203                         /* For rev 2, the csum doesn't include the MBA. */
10204                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10205                                 csum8 += buf8[i];
10206                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10207                                 csum8 += buf8[i];
10208                 } else {
10209                         for (i = 0; i < size; i++)
10210                                 csum8 += buf8[i];
10211                 }
10212
10213                 if (csum8 == 0) {
10214                         err = 0;
10215                         goto out;
10216                 }
10217
10218                 err = -EIO;
10219                 goto out;
10220         }
10221
10222         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10223             TG3_EEPROM_MAGIC_HW) {
10224                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10225                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10226                 u8 *buf8 = (u8 *) buf;
10227
10228                 /* Separate the parity bits and the data bytes.  */
10229                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10230                         if ((i == 0) || (i == 8)) {
10231                                 int l;
10232                                 u8 msk;
10233
10234                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10235                                         parity[k++] = buf8[i] & msk;
10236                                 i++;
10237                         } else if (i == 16) {
10238                                 int l;
10239                                 u8 msk;
10240
10241                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10242                                         parity[k++] = buf8[i] & msk;
10243                                 i++;
10244
10245                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10246                                         parity[k++] = buf8[i] & msk;
10247                                 i++;
10248                         }
10249                         data[j++] = buf8[i];
10250                 }
10251
10252                 err = -EIO;
10253                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10254                         u8 hw8 = hweight8(data[i]);
10255
10256                         if ((hw8 & 0x1) && parity[i])
10257                                 goto out;
10258                         else if (!(hw8 & 0x1) && !parity[i])
10259                                 goto out;
10260                 }
10261                 err = 0;
10262                 goto out;
10263         }
10264
10265         /* Bootstrap checksum at offset 0x10 */
10266         csum = calc_crc((unsigned char *) buf, 0x10);
10267         if (csum != be32_to_cpu(buf[0x10/4]))
10268                 goto out;
10269
10270         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10271         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10272         if (csum != be32_to_cpu(buf[0xfc/4]))
10273                 goto out;
10274
10275         err = 0;
10276
10277 out:
10278         kfree(buf);
10279         return err;
10280 }
10281
10282 #define TG3_SERDES_TIMEOUT_SEC  2
10283 #define TG3_COPPER_TIMEOUT_SEC  6
10284
10285 static int tg3_test_link(struct tg3 *tp)
10286 {
10287         int i, max;
10288
10289         if (!netif_running(tp->dev))
10290                 return -ENODEV;
10291
10292         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10293                 max = TG3_SERDES_TIMEOUT_SEC;
10294         else
10295                 max = TG3_COPPER_TIMEOUT_SEC;
10296
10297         for (i = 0; i < max; i++) {
10298                 if (netif_carrier_ok(tp->dev))
10299                         return 0;
10300
10301                 if (msleep_interruptible(1000))
10302                         break;
10303         }
10304
10305         return -EIO;
10306 }
10307
10308 /* Only test the commonly used registers */
10309 static int tg3_test_registers(struct tg3 *tp)
10310 {
10311         int i, is_5705, is_5750;
10312         u32 offset, read_mask, write_mask, val, save_val, read_val;
10313         static struct {
10314                 u16 offset;
10315                 u16 flags;
10316 #define TG3_FL_5705     0x1
10317 #define TG3_FL_NOT_5705 0x2
10318 #define TG3_FL_NOT_5788 0x4
10319 #define TG3_FL_NOT_5750 0x8
10320                 u32 read_mask;
10321                 u32 write_mask;
10322         } reg_tbl[] = {
10323                 /* MAC Control Registers */
10324                 { MAC_MODE, TG3_FL_NOT_5705,
10325                         0x00000000, 0x00ef6f8c },
10326                 { MAC_MODE, TG3_FL_5705,
10327                         0x00000000, 0x01ef6b8c },
10328                 { MAC_STATUS, TG3_FL_NOT_5705,
10329                         0x03800107, 0x00000000 },
10330                 { MAC_STATUS, TG3_FL_5705,
10331                         0x03800100, 0x00000000 },
10332                 { MAC_ADDR_0_HIGH, 0x0000,
10333                         0x00000000, 0x0000ffff },
10334                 { MAC_ADDR_0_LOW, 0x0000,
10335                         0x00000000, 0xffffffff },
10336                 { MAC_RX_MTU_SIZE, 0x0000,
10337                         0x00000000, 0x0000ffff },
10338                 { MAC_TX_MODE, 0x0000,
10339                         0x00000000, 0x00000070 },
10340                 { MAC_TX_LENGTHS, 0x0000,
10341                         0x00000000, 0x00003fff },
10342                 { MAC_RX_MODE, TG3_FL_NOT_5705,
10343                         0x00000000, 0x000007fc },
10344                 { MAC_RX_MODE, TG3_FL_5705,
10345                         0x00000000, 0x000007dc },
10346                 { MAC_HASH_REG_0, 0x0000,
10347                         0x00000000, 0xffffffff },
10348                 { MAC_HASH_REG_1, 0x0000,
10349                         0x00000000, 0xffffffff },
10350                 { MAC_HASH_REG_2, 0x0000,
10351                         0x00000000, 0xffffffff },
10352                 { MAC_HASH_REG_3, 0x0000,
10353                         0x00000000, 0xffffffff },
10354
10355                 /* Receive Data and Receive BD Initiator Control Registers. */
10356                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10357                         0x00000000, 0xffffffff },
10358                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10359                         0x00000000, 0xffffffff },
10360                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10361                         0x00000000, 0x00000003 },
10362                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10363                         0x00000000, 0xffffffff },
10364                 { RCVDBDI_STD_BD+0, 0x0000,
10365                         0x00000000, 0xffffffff },
10366                 { RCVDBDI_STD_BD+4, 0x0000,
10367                         0x00000000, 0xffffffff },
10368                 { RCVDBDI_STD_BD+8, 0x0000,
10369                         0x00000000, 0xffff0002 },
10370                 { RCVDBDI_STD_BD+0xc, 0x0000,
10371                         0x00000000, 0xffffffff },
10372
10373                 /* Receive BD Initiator Control Registers. */
10374                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10375                         0x00000000, 0xffffffff },
10376                 { RCVBDI_STD_THRESH, TG3_FL_5705,
10377                         0x00000000, 0x000003ff },
10378                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10379                         0x00000000, 0xffffffff },
10380
10381                 /* Host Coalescing Control Registers. */
10382                 { HOSTCC_MODE, TG3_FL_NOT_5705,
10383                         0x00000000, 0x00000004 },
10384                 { HOSTCC_MODE, TG3_FL_5705,
10385                         0x00000000, 0x000000f6 },
10386                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10387                         0x00000000, 0xffffffff },
10388                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10389                         0x00000000, 0x000003ff },
10390                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10391                         0x00000000, 0xffffffff },
10392                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10393                         0x00000000, 0x000003ff },
10394                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10395                         0x00000000, 0xffffffff },
10396                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10397                         0x00000000, 0x000000ff },
10398                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10399                         0x00000000, 0xffffffff },
10400                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10401                         0x00000000, 0x000000ff },
10402                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10403                         0x00000000, 0xffffffff },
10404                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10405                         0x00000000, 0xffffffff },
10406                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10407                         0x00000000, 0xffffffff },
10408                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10409                         0x00000000, 0x000000ff },
10410                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10411                         0x00000000, 0xffffffff },
10412                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10413                         0x00000000, 0x000000ff },
10414                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10415                         0x00000000, 0xffffffff },
10416                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10417                         0x00000000, 0xffffffff },
10418                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10419                         0x00000000, 0xffffffff },
10420                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10421                         0x00000000, 0xffffffff },
10422                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10423                         0x00000000, 0xffffffff },
10424                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10425                         0xffffffff, 0x00000000 },
10426                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10427                         0xffffffff, 0x00000000 },
10428
10429                 /* Buffer Manager Control Registers. */
10430                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10431                         0x00000000, 0x007fff80 },
10432                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10433                         0x00000000, 0x007fffff },
10434                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10435                         0x00000000, 0x0000003f },
10436                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10437                         0x00000000, 0x000001ff },
10438                 { BUFMGR_MB_HIGH_WATER, 0x0000,
10439                         0x00000000, 0x000001ff },
10440                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10441                         0xffffffff, 0x00000000 },
10442                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10443                         0xffffffff, 0x00000000 },
10444
10445                 /* Mailbox Registers */
10446                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10447                         0x00000000, 0x000001ff },
10448                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10449                         0x00000000, 0x000001ff },
10450                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10451                         0x00000000, 0x000007ff },
10452                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10453                         0x00000000, 0x000001ff },
10454
10455                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10456         };
10457
10458         is_5705 = is_5750 = 0;
10459         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10460                 is_5705 = 1;
10461                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10462                         is_5750 = 1;
10463         }
10464
10465         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10466                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10467                         continue;
10468
10469                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10470                         continue;
10471
10472                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10473                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
10474                         continue;
10475
10476                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10477                         continue;
10478
10479                 offset = (u32) reg_tbl[i].offset;
10480                 read_mask = reg_tbl[i].read_mask;
10481                 write_mask = reg_tbl[i].write_mask;
10482
10483                 /* Save the original register content */
10484                 save_val = tr32(offset);
10485
10486                 /* Determine the read-only value. */
10487                 read_val = save_val & read_mask;
10488
10489                 /* Write zero to the register, then make sure the read-only bits
10490                  * are not changed and the read/write bits are all zeros.
10491                  */
10492                 tw32(offset, 0);
10493
10494                 val = tr32(offset);
10495
10496                 /* Test the read-only and read/write bits. */
10497                 if (((val & read_mask) != read_val) || (val & write_mask))
10498                         goto out;
10499
10500                 /* Write ones to all the bits defined by RdMask and WrMask, then
10501                  * make sure the read-only bits are not changed and the
10502                  * read/write bits are all ones.
10503                  */
10504                 tw32(offset, read_mask | write_mask);
10505
10506                 val = tr32(offset);
10507
10508                 /* Test the read-only bits. */
10509                 if ((val & read_mask) != read_val)
10510                         goto out;
10511
10512                 /* Test the read/write bits. */
10513                 if ((val & write_mask) != write_mask)
10514                         goto out;
10515
10516                 tw32(offset, save_val);
10517         }
10518
10519         return 0;
10520
10521 out:
10522         if (netif_msg_hw(tp))
10523                 netdev_err(tp->dev,
10524                            "Register test failed at offset %x\n", offset);
10525         tw32(offset, save_val);
10526         return -EIO;
10527 }
10528
10529 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10530 {
10531         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10532         int i;
10533         u32 j;
10534
10535         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10536                 for (j = 0; j < len; j += 4) {
10537                         u32 val;
10538
10539                         tg3_write_mem(tp, offset + j, test_pattern[i]);
10540                         tg3_read_mem(tp, offset + j, &val);
10541                         if (val != test_pattern[i])
10542                                 return -EIO;
10543                 }
10544         }
10545         return 0;
10546 }
10547
10548 static int tg3_test_memory(struct tg3 *tp)
10549 {
10550         static struct mem_entry {
10551                 u32 offset;
10552                 u32 len;
10553         } mem_tbl_570x[] = {
10554                 { 0x00000000, 0x00b50},
10555                 { 0x00002000, 0x1c000},
10556                 { 0xffffffff, 0x00000}
10557         }, mem_tbl_5705[] = {
10558                 { 0x00000100, 0x0000c},
10559                 { 0x00000200, 0x00008},
10560                 { 0x00004000, 0x00800},
10561                 { 0x00006000, 0x01000},
10562                 { 0x00008000, 0x02000},
10563                 { 0x00010000, 0x0e000},
10564                 { 0xffffffff, 0x00000}
10565         }, mem_tbl_5755[] = {
10566                 { 0x00000200, 0x00008},
10567                 { 0x00004000, 0x00800},
10568                 { 0x00006000, 0x00800},
10569                 { 0x00008000, 0x02000},
10570                 { 0x00010000, 0x0c000},
10571                 { 0xffffffff, 0x00000}
10572         }, mem_tbl_5906[] = {
10573                 { 0x00000200, 0x00008},
10574                 { 0x00004000, 0x00400},
10575                 { 0x00006000, 0x00400},
10576                 { 0x00008000, 0x01000},
10577                 { 0x00010000, 0x01000},
10578                 { 0xffffffff, 0x00000}
10579         }, mem_tbl_5717[] = {
10580                 { 0x00000200, 0x00008},
10581                 { 0x00010000, 0x0a000},
10582                 { 0x00020000, 0x13c00},
10583                 { 0xffffffff, 0x00000}
10584         }, mem_tbl_57765[] = {
10585                 { 0x00000200, 0x00008},
10586                 { 0x00004000, 0x00800},
10587                 { 0x00006000, 0x09800},
10588                 { 0x00010000, 0x0a000},
10589                 { 0xffffffff, 0x00000}
10590         };
10591         struct mem_entry *mem_tbl;
10592         int err = 0;
10593         int i;
10594
10595         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
10596             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
10597                 mem_tbl = mem_tbl_5717;
10598         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10599                 mem_tbl = mem_tbl_57765;
10600         else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10601                 mem_tbl = mem_tbl_5755;
10602         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10603                 mem_tbl = mem_tbl_5906;
10604         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10605                 mem_tbl = mem_tbl_5705;
10606         else
10607                 mem_tbl = mem_tbl_570x;
10608
10609         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10610                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10611                     mem_tbl[i].len)) != 0)
10612                         break;
10613         }
10614
10615         return err;
10616 }
10617
10618 #define TG3_MAC_LOOPBACK        0
10619 #define TG3_PHY_LOOPBACK        1
10620
10621 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10622 {
10623         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10624         u32 desc_idx, coal_now;
10625         struct sk_buff *skb, *rx_skb;
10626         u8 *tx_data;
10627         dma_addr_t map;
10628         int num_pkts, tx_len, rx_len, i, err;
10629         struct tg3_rx_buffer_desc *desc;
10630         struct tg3_napi *tnapi, *rnapi;
10631         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
10632
10633         tnapi = &tp->napi[0];
10634         rnapi = &tp->napi[0];
10635         if (tp->irq_cnt > 1) {
10636                 rnapi = &tp->napi[1];
10637                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
10638                         tnapi = &tp->napi[1];
10639         }
10640         coal_now = tnapi->coal_now | rnapi->coal_now;
10641
10642         if (loopback_mode == TG3_MAC_LOOPBACK) {
10643                 /* HW errata - mac loopback fails in some cases on 5780.
10644                  * Normal traffic and PHY loopback are not affected by
10645                  * errata.
10646                  */
10647                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10648                         return 0;
10649
10650                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10651                            MAC_MODE_PORT_INT_LPBACK;
10652                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10653                         mac_mode |= MAC_MODE_LINK_POLARITY;
10654                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10655                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10656                 else
10657                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10658                 tw32(MAC_MODE, mac_mode);
10659         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10660                 u32 val;
10661
10662                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10663                         tg3_phy_fet_toggle_apd(tp, false);
10664                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10665                 } else
10666                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10667
10668                 tg3_phy_toggle_automdix(tp, 0);
10669
10670                 tg3_writephy(tp, MII_BMCR, val);
10671                 udelay(40);
10672
10673                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10674                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10675                         tg3_writephy(tp, MII_TG3_FET_PTEST,
10676                                      MII_TG3_FET_PTEST_FRC_TX_LINK |
10677                                      MII_TG3_FET_PTEST_FRC_TX_LOCK);
10678                         /* The write needs to be flushed for the AC131 */
10679                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10680                                 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
10681                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10682                 } else
10683                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10684
10685                 /* reset to prevent losing 1st rx packet intermittently */
10686                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10687                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10688                         udelay(10);
10689                         tw32_f(MAC_RX_MODE, tp->rx_mode);
10690                 }
10691                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10692                         u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
10693                         if (masked_phy_id == TG3_PHY_ID_BCM5401)
10694                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10695                         else if (masked_phy_id == TG3_PHY_ID_BCM5411)
10696                                 mac_mode |= MAC_MODE_LINK_POLARITY;
10697                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
10698                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10699                 }
10700                 tw32(MAC_MODE, mac_mode);
10701         } else {
10702                 return -EINVAL;
10703         }
10704
10705         err = -EIO;
10706
10707         tx_len = 1514;
10708         skb = netdev_alloc_skb(tp->dev, tx_len);
10709         if (!skb)
10710                 return -ENOMEM;
10711
10712         tx_data = skb_put(skb, tx_len);
10713         memcpy(tx_data, tp->dev->dev_addr, 6);
10714         memset(tx_data + 6, 0x0, 8);
10715
10716         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10717
10718         for (i = 14; i < tx_len; i++)
10719                 tx_data[i] = (u8) (i & 0xff);
10720
10721         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10722         if (pci_dma_mapping_error(tp->pdev, map)) {
10723                 dev_kfree_skb(skb);
10724                 return -EIO;
10725         }
10726
10727         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10728                rnapi->coal_now);
10729
10730         udelay(10);
10731
10732         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10733
10734         num_pkts = 0;
10735
10736         tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10737
10738         tnapi->tx_prod++;
10739         num_pkts++;
10740
10741         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10742         tr32_mailbox(tnapi->prodmbox);
10743
10744         udelay(10);
10745
10746         /* 350 usec to allow enough time on some 10/100 Mbps devices.  */
10747         for (i = 0; i < 35; i++) {
10748                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10749                        coal_now);
10750
10751                 udelay(10);
10752
10753                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10754                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10755                 if ((tx_idx == tnapi->tx_prod) &&
10756                     (rx_idx == (rx_start_idx + num_pkts)))
10757                         break;
10758         }
10759
10760         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10761         dev_kfree_skb(skb);
10762
10763         if (tx_idx != tnapi->tx_prod)
10764                 goto out;
10765
10766         if (rx_idx != rx_start_idx + num_pkts)
10767                 goto out;
10768
10769         desc = &rnapi->rx_rcb[rx_start_idx];
10770         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10771         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10772         if (opaque_key != RXD_OPAQUE_RING_STD)
10773                 goto out;
10774
10775         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10776             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10777                 goto out;
10778
10779         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10780         if (rx_len != tx_len)
10781                 goto out;
10782
10783         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10784
10785         map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10786         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10787
10788         for (i = 14; i < tx_len; i++) {
10789                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10790                         goto out;
10791         }
10792         err = 0;
10793
10794         /* tg3_free_rings will unmap and free the rx_skb */
10795 out:
10796         return err;
10797 }
10798
10799 #define TG3_MAC_LOOPBACK_FAILED         1
10800 #define TG3_PHY_LOOPBACK_FAILED         2
10801 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
10802                                          TG3_PHY_LOOPBACK_FAILED)
10803
10804 static int tg3_test_loopback(struct tg3 *tp)
10805 {
10806         int err = 0;
10807         u32 cpmuctrl = 0;
10808
10809         if (!netif_running(tp->dev))
10810                 return TG3_LOOPBACK_FAILED;
10811
10812         err = tg3_reset_hw(tp, 1);
10813         if (err)
10814                 return TG3_LOOPBACK_FAILED;
10815
10816         /* Turn off gphy autopowerdown. */
10817         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10818                 tg3_phy_toggle_apd(tp, false);
10819
10820         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10821                 int i;
10822                 u32 status;
10823
10824                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10825
10826                 /* Wait for up to 40 microseconds to acquire lock. */
10827                 for (i = 0; i < 4; i++) {
10828                         status = tr32(TG3_CPMU_MUTEX_GNT);
10829                         if (status == CPMU_MUTEX_GNT_DRIVER)
10830                                 break;
10831                         udelay(10);
10832                 }
10833
10834                 if (status != CPMU_MUTEX_GNT_DRIVER)
10835                         return TG3_LOOPBACK_FAILED;
10836
10837                 /* Turn off link-based power management. */
10838                 cpmuctrl = tr32(TG3_CPMU_CTRL);
10839                 tw32(TG3_CPMU_CTRL,
10840                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10841                                   CPMU_CTRL_LINK_AWARE_MODE));
10842         }
10843
10844         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10845                 err |= TG3_MAC_LOOPBACK_FAILED;
10846
10847         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10848                 tw32(TG3_CPMU_CTRL, cpmuctrl);
10849
10850                 /* Release the mutex */
10851                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10852         }
10853
10854         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10855             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10856                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10857                         err |= TG3_PHY_LOOPBACK_FAILED;
10858         }
10859
10860         /* Re-enable gphy autopowerdown. */
10861         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10862                 tg3_phy_toggle_apd(tp, true);
10863
10864         return err;
10865 }
10866
10867 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10868                           u64 *data)
10869 {
10870         struct tg3 *tp = netdev_priv(dev);
10871
10872         if (tp->link_config.phy_is_low_power)
10873                 tg3_set_power_state(tp, PCI_D0);
10874
10875         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10876
10877         if (tg3_test_nvram(tp) != 0) {
10878                 etest->flags |= ETH_TEST_FL_FAILED;
10879                 data[0] = 1;
10880         }
10881         if (tg3_test_link(tp) != 0) {
10882                 etest->flags |= ETH_TEST_FL_FAILED;
10883                 data[1] = 1;
10884         }
10885         if (etest->flags & ETH_TEST_FL_OFFLINE) {
10886                 int err, err2 = 0, irq_sync = 0;
10887
10888                 if (netif_running(dev)) {
10889                         tg3_phy_stop(tp);
10890                         tg3_netif_stop(tp);
10891                         irq_sync = 1;
10892                 }
10893
10894                 tg3_full_lock(tp, irq_sync);
10895
10896                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10897                 err = tg3_nvram_lock(tp);
10898                 tg3_halt_cpu(tp, RX_CPU_BASE);
10899                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10900                         tg3_halt_cpu(tp, TX_CPU_BASE);
10901                 if (!err)
10902                         tg3_nvram_unlock(tp);
10903
10904                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10905                         tg3_phy_reset(tp);
10906
10907                 if (tg3_test_registers(tp) != 0) {
10908                         etest->flags |= ETH_TEST_FL_FAILED;
10909                         data[2] = 1;
10910                 }
10911                 if (tg3_test_memory(tp) != 0) {
10912                         etest->flags |= ETH_TEST_FL_FAILED;
10913                         data[3] = 1;
10914                 }
10915                 if ((data[4] = tg3_test_loopback(tp)) != 0)
10916                         etest->flags |= ETH_TEST_FL_FAILED;
10917
10918                 tg3_full_unlock(tp);
10919
10920                 if (tg3_test_interrupt(tp) != 0) {
10921                         etest->flags |= ETH_TEST_FL_FAILED;
10922                         data[5] = 1;
10923                 }
10924
10925                 tg3_full_lock(tp, 0);
10926
10927                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10928                 if (netif_running(dev)) {
10929                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10930                         err2 = tg3_restart_hw(tp, 1);
10931                         if (!err2)
10932                                 tg3_netif_start(tp);
10933                 }
10934
10935                 tg3_full_unlock(tp);
10936
10937                 if (irq_sync && !err2)
10938                         tg3_phy_start(tp);
10939         }
10940         if (tp->link_config.phy_is_low_power)
10941                 tg3_set_power_state(tp, PCI_D3hot);
10942
10943 }
10944
10945 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10946 {
10947         struct mii_ioctl_data *data = if_mii(ifr);
10948         struct tg3 *tp = netdev_priv(dev);
10949         int err;
10950
10951         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10952                 struct phy_device *phydev;
10953                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10954                         return -EAGAIN;
10955                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10956                 return phy_mii_ioctl(phydev, data, cmd);
10957         }
10958
10959         switch (cmd) {
10960         case SIOCGMIIPHY:
10961                 data->phy_id = tp->phy_addr;
10962
10963                 /* fallthru */
10964         case SIOCGMIIREG: {
10965                 u32 mii_regval;
10966
10967                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10968                         break;                  /* We have no PHY */
10969
10970                 if (tp->link_config.phy_is_low_power)
10971                         return -EAGAIN;
10972
10973                 spin_lock_bh(&tp->lock);
10974                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10975                 spin_unlock_bh(&tp->lock);
10976
10977                 data->val_out = mii_regval;
10978
10979                 return err;
10980         }
10981
10982         case SIOCSMIIREG:
10983                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10984                         break;                  /* We have no PHY */
10985
10986                 if (tp->link_config.phy_is_low_power)
10987                         return -EAGAIN;
10988
10989                 spin_lock_bh(&tp->lock);
10990                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10991                 spin_unlock_bh(&tp->lock);
10992
10993                 return err;
10994
10995         default:
10996                 /* do nothing */
10997                 break;
10998         }
10999         return -EOPNOTSUPP;
11000 }
11001
11002 #if TG3_VLAN_TAG_USED
11003 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
11004 {
11005         struct tg3 *tp = netdev_priv(dev);
11006
11007         if (!netif_running(dev)) {
11008                 tp->vlgrp = grp;
11009                 return;
11010         }
11011
11012         tg3_netif_stop(tp);
11013
11014         tg3_full_lock(tp, 0);
11015
11016         tp->vlgrp = grp;
11017
11018         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11019         __tg3_set_rx_mode(dev);
11020
11021         tg3_netif_start(tp);
11022
11023         tg3_full_unlock(tp);
11024 }
11025 #endif
11026
11027 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11028 {
11029         struct tg3 *tp = netdev_priv(dev);
11030
11031         memcpy(ec, &tp->coal, sizeof(*ec));
11032         return 0;
11033 }
11034
11035 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11036 {
11037         struct tg3 *tp = netdev_priv(dev);
11038         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11039         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11040
11041         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11042                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11043                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11044                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11045                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11046         }
11047
11048         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11049             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11050             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11051             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11052             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11053             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11054             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11055             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11056             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11057             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11058                 return -EINVAL;
11059
11060         /* No rx interrupts will be generated if both are zero */
11061         if ((ec->rx_coalesce_usecs == 0) &&
11062             (ec->rx_max_coalesced_frames == 0))
11063                 return -EINVAL;
11064
11065         /* No tx interrupts will be generated if both are zero */
11066         if ((ec->tx_coalesce_usecs == 0) &&
11067             (ec->tx_max_coalesced_frames == 0))
11068                 return -EINVAL;
11069
11070         /* Only copy relevant parameters, ignore all others. */
11071         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11072         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11073         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11074         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11075         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11076         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11077         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11078         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11079         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11080
11081         if (netif_running(dev)) {
11082                 tg3_full_lock(tp, 0);
11083                 __tg3_set_coalesce(tp, &tp->coal);
11084                 tg3_full_unlock(tp);
11085         }
11086         return 0;
11087 }
11088
11089 static const struct ethtool_ops tg3_ethtool_ops = {
11090         .get_settings           = tg3_get_settings,
11091         .set_settings           = tg3_set_settings,
11092         .get_drvinfo            = tg3_get_drvinfo,
11093         .get_regs_len           = tg3_get_regs_len,
11094         .get_regs               = tg3_get_regs,
11095         .get_wol                = tg3_get_wol,
11096         .set_wol                = tg3_set_wol,
11097         .get_msglevel           = tg3_get_msglevel,
11098         .set_msglevel           = tg3_set_msglevel,
11099         .nway_reset             = tg3_nway_reset,
11100         .get_link               = ethtool_op_get_link,
11101         .get_eeprom_len         = tg3_get_eeprom_len,
11102         .get_eeprom             = tg3_get_eeprom,
11103         .set_eeprom             = tg3_set_eeprom,
11104         .get_ringparam          = tg3_get_ringparam,
11105         .set_ringparam          = tg3_set_ringparam,
11106         .get_pauseparam         = tg3_get_pauseparam,
11107         .set_pauseparam         = tg3_set_pauseparam,
11108         .get_rx_csum            = tg3_get_rx_csum,
11109         .set_rx_csum            = tg3_set_rx_csum,
11110         .set_tx_csum            = tg3_set_tx_csum,
11111         .set_sg                 = ethtool_op_set_sg,
11112         .set_tso                = tg3_set_tso,
11113         .self_test              = tg3_self_test,
11114         .get_strings            = tg3_get_strings,
11115         .phys_id                = tg3_phys_id,
11116         .get_ethtool_stats      = tg3_get_ethtool_stats,
11117         .get_coalesce           = tg3_get_coalesce,
11118         .set_coalesce           = tg3_set_coalesce,
11119         .get_sset_count         = tg3_get_sset_count,
11120 };
11121
11122 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11123 {
11124         u32 cursize, val, magic;
11125
11126         tp->nvram_size = EEPROM_CHIP_SIZE;
11127
11128         if (tg3_nvram_read(tp, 0, &magic) != 0)
11129                 return;
11130
11131         if ((magic != TG3_EEPROM_MAGIC) &&
11132             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11133             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11134                 return;
11135
11136         /*
11137          * Size the chip by reading offsets at increasing powers of two.
11138          * When we encounter our validation signature, we know the addressing
11139          * has wrapped around, and thus have our chip size.
11140          */
11141         cursize = 0x10;
11142
11143         while (cursize < tp->nvram_size) {
11144                 if (tg3_nvram_read(tp, cursize, &val) != 0)
11145                         return;
11146
11147                 if (val == magic)
11148                         break;
11149
11150                 cursize <<= 1;
11151         }
11152
11153         tp->nvram_size = cursize;
11154 }
11155
11156 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11157 {
11158         u32 val;
11159
11160         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11161             tg3_nvram_read(tp, 0, &val) != 0)
11162                 return;
11163
11164         /* Selfboot format */
11165         if (val != TG3_EEPROM_MAGIC) {
11166                 tg3_get_eeprom_size(tp);
11167                 return;
11168         }
11169
11170         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11171                 if (val != 0) {
11172                         /* This is confusing.  We want to operate on the
11173                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
11174                          * call will read from NVRAM and byteswap the data
11175                          * according to the byteswapping settings for all
11176                          * other register accesses.  This ensures the data we
11177                          * want will always reside in the lower 16-bits.
11178                          * However, the data in NVRAM is in LE format, which
11179                          * means the data from the NVRAM read will always be
11180                          * opposite the endianness of the CPU.  The 16-bit
11181                          * byteswap then brings the data to CPU endianness.
11182                          */
11183                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11184                         return;
11185                 }
11186         }
11187         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11188 }
11189
11190 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11191 {
11192         u32 nvcfg1;
11193
11194         nvcfg1 = tr32(NVRAM_CFG1);
11195         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11196                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11197         } else {
11198                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11199                 tw32(NVRAM_CFG1, nvcfg1);
11200         }
11201
11202         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11203             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11204                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11205                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11206                         tp->nvram_jedecnum = JEDEC_ATMEL;
11207                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11208                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11209                         break;
11210                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11211                         tp->nvram_jedecnum = JEDEC_ATMEL;
11212                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11213                         break;
11214                 case FLASH_VENDOR_ATMEL_EEPROM:
11215                         tp->nvram_jedecnum = JEDEC_ATMEL;
11216                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11217                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11218                         break;
11219                 case FLASH_VENDOR_ST:
11220                         tp->nvram_jedecnum = JEDEC_ST;
11221                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11222                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11223                         break;
11224                 case FLASH_VENDOR_SAIFUN:
11225                         tp->nvram_jedecnum = JEDEC_SAIFUN;
11226                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11227                         break;
11228                 case FLASH_VENDOR_SST_SMALL:
11229                 case FLASH_VENDOR_SST_LARGE:
11230                         tp->nvram_jedecnum = JEDEC_SST;
11231                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11232                         break;
11233                 }
11234         } else {
11235                 tp->nvram_jedecnum = JEDEC_ATMEL;
11236                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11237                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11238         }
11239 }
11240
11241 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11242 {
11243         switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11244         case FLASH_5752PAGE_SIZE_256:
11245                 tp->nvram_pagesize = 256;
11246                 break;
11247         case FLASH_5752PAGE_SIZE_512:
11248                 tp->nvram_pagesize = 512;
11249                 break;
11250         case FLASH_5752PAGE_SIZE_1K:
11251                 tp->nvram_pagesize = 1024;
11252                 break;
11253         case FLASH_5752PAGE_SIZE_2K:
11254                 tp->nvram_pagesize = 2048;
11255                 break;
11256         case FLASH_5752PAGE_SIZE_4K:
11257                 tp->nvram_pagesize = 4096;
11258                 break;
11259         case FLASH_5752PAGE_SIZE_264:
11260                 tp->nvram_pagesize = 264;
11261                 break;
11262         case FLASH_5752PAGE_SIZE_528:
11263                 tp->nvram_pagesize = 528;
11264                 break;
11265         }
11266 }
11267
11268 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11269 {
11270         u32 nvcfg1;
11271
11272         nvcfg1 = tr32(NVRAM_CFG1);
11273
11274         /* NVRAM protection for TPM */
11275         if (nvcfg1 & (1 << 27))
11276                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11277
11278         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11279         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11280         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11281                 tp->nvram_jedecnum = JEDEC_ATMEL;
11282                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11283                 break;
11284         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11285                 tp->nvram_jedecnum = JEDEC_ATMEL;
11286                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11287                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11288                 break;
11289         case FLASH_5752VENDOR_ST_M45PE10:
11290         case FLASH_5752VENDOR_ST_M45PE20:
11291         case FLASH_5752VENDOR_ST_M45PE40:
11292                 tp->nvram_jedecnum = JEDEC_ST;
11293                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11294                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11295                 break;
11296         }
11297
11298         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11299                 tg3_nvram_get_pagesize(tp, nvcfg1);
11300         } else {
11301                 /* For eeprom, set pagesize to maximum eeprom size */
11302                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11303
11304                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11305                 tw32(NVRAM_CFG1, nvcfg1);
11306         }
11307 }
11308
11309 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11310 {
11311         u32 nvcfg1, protect = 0;
11312
11313         nvcfg1 = tr32(NVRAM_CFG1);
11314
11315         /* NVRAM protection for TPM */
11316         if (nvcfg1 & (1 << 27)) {
11317                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11318                 protect = 1;
11319         }
11320
11321         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11322         switch (nvcfg1) {
11323         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11324         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11325         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11326         case FLASH_5755VENDOR_ATMEL_FLASH_5:
11327                 tp->nvram_jedecnum = JEDEC_ATMEL;
11328                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11329                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11330                 tp->nvram_pagesize = 264;
11331                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11332                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11333                         tp->nvram_size = (protect ? 0x3e200 :
11334                                           TG3_NVRAM_SIZE_512KB);
11335                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11336                         tp->nvram_size = (protect ? 0x1f200 :
11337                                           TG3_NVRAM_SIZE_256KB);
11338                 else
11339                         tp->nvram_size = (protect ? 0x1f200 :
11340                                           TG3_NVRAM_SIZE_128KB);
11341                 break;
11342         case FLASH_5752VENDOR_ST_M45PE10:
11343         case FLASH_5752VENDOR_ST_M45PE20:
11344         case FLASH_5752VENDOR_ST_M45PE40:
11345                 tp->nvram_jedecnum = JEDEC_ST;
11346                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11347                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11348                 tp->nvram_pagesize = 256;
11349                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11350                         tp->nvram_size = (protect ?
11351                                           TG3_NVRAM_SIZE_64KB :
11352                                           TG3_NVRAM_SIZE_128KB);
11353                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11354                         tp->nvram_size = (protect ?
11355                                           TG3_NVRAM_SIZE_64KB :
11356                                           TG3_NVRAM_SIZE_256KB);
11357                 else
11358                         tp->nvram_size = (protect ?
11359                                           TG3_NVRAM_SIZE_128KB :
11360                                           TG3_NVRAM_SIZE_512KB);
11361                 break;
11362         }
11363 }
11364
11365 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11366 {
11367         u32 nvcfg1;
11368
11369         nvcfg1 = tr32(NVRAM_CFG1);
11370
11371         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11372         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11373         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11374         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11375         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11376                 tp->nvram_jedecnum = JEDEC_ATMEL;
11377                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11378                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11379
11380                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11381                 tw32(NVRAM_CFG1, nvcfg1);
11382                 break;
11383         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11384         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11385         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11386         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11387                 tp->nvram_jedecnum = JEDEC_ATMEL;
11388                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11389                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11390                 tp->nvram_pagesize = 264;
11391                 break;
11392         case FLASH_5752VENDOR_ST_M45PE10:
11393         case FLASH_5752VENDOR_ST_M45PE20:
11394         case FLASH_5752VENDOR_ST_M45PE40:
11395                 tp->nvram_jedecnum = JEDEC_ST;
11396                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11397                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11398                 tp->nvram_pagesize = 256;
11399                 break;
11400         }
11401 }
11402
11403 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11404 {
11405         u32 nvcfg1, protect = 0;
11406
11407         nvcfg1 = tr32(NVRAM_CFG1);
11408
11409         /* NVRAM protection for TPM */
11410         if (nvcfg1 & (1 << 27)) {
11411                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11412                 protect = 1;
11413         }
11414
11415         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11416         switch (nvcfg1) {
11417         case FLASH_5761VENDOR_ATMEL_ADB021D:
11418         case FLASH_5761VENDOR_ATMEL_ADB041D:
11419         case FLASH_5761VENDOR_ATMEL_ADB081D:
11420         case FLASH_5761VENDOR_ATMEL_ADB161D:
11421         case FLASH_5761VENDOR_ATMEL_MDB021D:
11422         case FLASH_5761VENDOR_ATMEL_MDB041D:
11423         case FLASH_5761VENDOR_ATMEL_MDB081D:
11424         case FLASH_5761VENDOR_ATMEL_MDB161D:
11425                 tp->nvram_jedecnum = JEDEC_ATMEL;
11426                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11427                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11428                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11429                 tp->nvram_pagesize = 256;
11430                 break;
11431         case FLASH_5761VENDOR_ST_A_M45PE20:
11432         case FLASH_5761VENDOR_ST_A_M45PE40:
11433         case FLASH_5761VENDOR_ST_A_M45PE80:
11434         case FLASH_5761VENDOR_ST_A_M45PE16:
11435         case FLASH_5761VENDOR_ST_M_M45PE20:
11436         case FLASH_5761VENDOR_ST_M_M45PE40:
11437         case FLASH_5761VENDOR_ST_M_M45PE80:
11438         case FLASH_5761VENDOR_ST_M_M45PE16:
11439                 tp->nvram_jedecnum = JEDEC_ST;
11440                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11441                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11442                 tp->nvram_pagesize = 256;
11443                 break;
11444         }
11445
11446         if (protect) {
11447                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11448         } else {
11449                 switch (nvcfg1) {
11450                 case FLASH_5761VENDOR_ATMEL_ADB161D:
11451                 case FLASH_5761VENDOR_ATMEL_MDB161D:
11452                 case FLASH_5761VENDOR_ST_A_M45PE16:
11453                 case FLASH_5761VENDOR_ST_M_M45PE16:
11454                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11455                         break;
11456                 case FLASH_5761VENDOR_ATMEL_ADB081D:
11457                 case FLASH_5761VENDOR_ATMEL_MDB081D:
11458                 case FLASH_5761VENDOR_ST_A_M45PE80:
11459                 case FLASH_5761VENDOR_ST_M_M45PE80:
11460                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11461                         break;
11462                 case FLASH_5761VENDOR_ATMEL_ADB041D:
11463                 case FLASH_5761VENDOR_ATMEL_MDB041D:
11464                 case FLASH_5761VENDOR_ST_A_M45PE40:
11465                 case FLASH_5761VENDOR_ST_M_M45PE40:
11466                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11467                         break;
11468                 case FLASH_5761VENDOR_ATMEL_ADB021D:
11469                 case FLASH_5761VENDOR_ATMEL_MDB021D:
11470                 case FLASH_5761VENDOR_ST_A_M45PE20:
11471                 case FLASH_5761VENDOR_ST_M_M45PE20:
11472                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11473                         break;
11474                 }
11475         }
11476 }
11477
11478 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11479 {
11480         tp->nvram_jedecnum = JEDEC_ATMEL;
11481         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11482         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11483 }
11484
11485 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11486 {
11487         u32 nvcfg1;
11488
11489         nvcfg1 = tr32(NVRAM_CFG1);
11490
11491         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11492         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11493         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11494                 tp->nvram_jedecnum = JEDEC_ATMEL;
11495                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11496                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11497
11498                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11499                 tw32(NVRAM_CFG1, nvcfg1);
11500                 return;
11501         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11502         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11503         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11504         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11505         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11506         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11507         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11508                 tp->nvram_jedecnum = JEDEC_ATMEL;
11509                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11510                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11511
11512                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11513                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11514                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11515                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11516                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11517                         break;
11518                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11519                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11520                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11521                         break;
11522                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11523                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11524                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11525                         break;
11526                 }
11527                 break;
11528         case FLASH_5752VENDOR_ST_M45PE10:
11529         case FLASH_5752VENDOR_ST_M45PE20:
11530         case FLASH_5752VENDOR_ST_M45PE40:
11531                 tp->nvram_jedecnum = JEDEC_ST;
11532                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11533                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11534
11535                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11536                 case FLASH_5752VENDOR_ST_M45PE10:
11537                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11538                         break;
11539                 case FLASH_5752VENDOR_ST_M45PE20:
11540                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11541                         break;
11542                 case FLASH_5752VENDOR_ST_M45PE40:
11543                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11544                         break;
11545                 }
11546                 break;
11547         default:
11548                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11549                 return;
11550         }
11551
11552         tg3_nvram_get_pagesize(tp, nvcfg1);
11553         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11554                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11555 }
11556
11557
11558 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11559 {
11560         u32 nvcfg1;
11561
11562         nvcfg1 = tr32(NVRAM_CFG1);
11563
11564         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11565         case FLASH_5717VENDOR_ATMEL_EEPROM:
11566         case FLASH_5717VENDOR_MICRO_EEPROM:
11567                 tp->nvram_jedecnum = JEDEC_ATMEL;
11568                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11569                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11570
11571                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11572                 tw32(NVRAM_CFG1, nvcfg1);
11573                 return;
11574         case FLASH_5717VENDOR_ATMEL_MDB011D:
11575         case FLASH_5717VENDOR_ATMEL_ADB011B:
11576         case FLASH_5717VENDOR_ATMEL_ADB011D:
11577         case FLASH_5717VENDOR_ATMEL_MDB021D:
11578         case FLASH_5717VENDOR_ATMEL_ADB021B:
11579         case FLASH_5717VENDOR_ATMEL_ADB021D:
11580         case FLASH_5717VENDOR_ATMEL_45USPT:
11581                 tp->nvram_jedecnum = JEDEC_ATMEL;
11582                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11583                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11584
11585                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11586                 case FLASH_5717VENDOR_ATMEL_MDB021D:
11587                 case FLASH_5717VENDOR_ATMEL_ADB021B:
11588                 case FLASH_5717VENDOR_ATMEL_ADB021D:
11589                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11590                         break;
11591                 default:
11592                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11593                         break;
11594                 }
11595                 break;
11596         case FLASH_5717VENDOR_ST_M_M25PE10:
11597         case FLASH_5717VENDOR_ST_A_M25PE10:
11598         case FLASH_5717VENDOR_ST_M_M45PE10:
11599         case FLASH_5717VENDOR_ST_A_M45PE10:
11600         case FLASH_5717VENDOR_ST_M_M25PE20:
11601         case FLASH_5717VENDOR_ST_A_M25PE20:
11602         case FLASH_5717VENDOR_ST_M_M45PE20:
11603         case FLASH_5717VENDOR_ST_A_M45PE20:
11604         case FLASH_5717VENDOR_ST_25USPT:
11605         case FLASH_5717VENDOR_ST_45USPT:
11606                 tp->nvram_jedecnum = JEDEC_ST;
11607                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11608                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11609
11610                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11611                 case FLASH_5717VENDOR_ST_M_M25PE20:
11612                 case FLASH_5717VENDOR_ST_A_M25PE20:
11613                 case FLASH_5717VENDOR_ST_M_M45PE20:
11614                 case FLASH_5717VENDOR_ST_A_M45PE20:
11615                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11616                         break;
11617                 default:
11618                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11619                         break;
11620                 }
11621                 break;
11622         default:
11623                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11624                 return;
11625         }
11626
11627         tg3_nvram_get_pagesize(tp, nvcfg1);
11628         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11629                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11630 }
11631
11632 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11633 static void __devinit tg3_nvram_init(struct tg3 *tp)
11634 {
11635         tw32_f(GRC_EEPROM_ADDR,
11636              (EEPROM_ADDR_FSM_RESET |
11637               (EEPROM_DEFAULT_CLOCK_PERIOD <<
11638                EEPROM_ADDR_CLKPERD_SHIFT)));
11639
11640         msleep(1);
11641
11642         /* Enable seeprom accesses. */
11643         tw32_f(GRC_LOCAL_CTRL,
11644              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11645         udelay(100);
11646
11647         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11648             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11649                 tp->tg3_flags |= TG3_FLAG_NVRAM;
11650
11651                 if (tg3_nvram_lock(tp)) {
11652                         netdev_warn(tp->dev,
11653                                     "Cannot get nvram lock, %s failed\n",
11654                                     __func__);
11655                         return;
11656                 }
11657                 tg3_enable_nvram_access(tp);
11658
11659                 tp->nvram_size = 0;
11660
11661                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11662                         tg3_get_5752_nvram_info(tp);
11663                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11664                         tg3_get_5755_nvram_info(tp);
11665                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11666                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11667                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11668                         tg3_get_5787_nvram_info(tp);
11669                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11670                         tg3_get_5761_nvram_info(tp);
11671                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11672                         tg3_get_5906_nvram_info(tp);
11673                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11674                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11675                         tg3_get_57780_nvram_info(tp);
11676                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
11677                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
11678                         tg3_get_5717_nvram_info(tp);
11679                 else
11680                         tg3_get_nvram_info(tp);
11681
11682                 if (tp->nvram_size == 0)
11683                         tg3_get_nvram_size(tp);
11684
11685                 tg3_disable_nvram_access(tp);
11686                 tg3_nvram_unlock(tp);
11687
11688         } else {
11689                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11690
11691                 tg3_get_eeprom_size(tp);
11692         }
11693 }
11694
11695 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11696                                     u32 offset, u32 len, u8 *buf)
11697 {
11698         int i, j, rc = 0;
11699         u32 val;
11700
11701         for (i = 0; i < len; i += 4) {
11702                 u32 addr;
11703                 __be32 data;
11704
11705                 addr = offset + i;
11706
11707                 memcpy(&data, buf + i, 4);
11708
11709                 /*
11710                  * The SEEPROM interface expects the data to always be opposite
11711                  * the native endian format.  We accomplish this by reversing
11712                  * all the operations that would have been performed on the
11713                  * data from a call to tg3_nvram_read_be32().
11714                  */
11715                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11716
11717                 val = tr32(GRC_EEPROM_ADDR);
11718                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11719
11720                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11721                         EEPROM_ADDR_READ);
11722                 tw32(GRC_EEPROM_ADDR, val |
11723                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
11724                         (addr & EEPROM_ADDR_ADDR_MASK) |
11725                         EEPROM_ADDR_START |
11726                         EEPROM_ADDR_WRITE);
11727
11728                 for (j = 0; j < 1000; j++) {
11729                         val = tr32(GRC_EEPROM_ADDR);
11730
11731                         if (val & EEPROM_ADDR_COMPLETE)
11732                                 break;
11733                         msleep(1);
11734                 }
11735                 if (!(val & EEPROM_ADDR_COMPLETE)) {
11736                         rc = -EBUSY;
11737                         break;
11738                 }
11739         }
11740
11741         return rc;
11742 }
11743
11744 /* offset and length are dword aligned */
11745 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11746                 u8 *buf)
11747 {
11748         int ret = 0;
11749         u32 pagesize = tp->nvram_pagesize;
11750         u32 pagemask = pagesize - 1;
11751         u32 nvram_cmd;
11752         u8 *tmp;
11753
11754         tmp = kmalloc(pagesize, GFP_KERNEL);
11755         if (tmp == NULL)
11756                 return -ENOMEM;
11757
11758         while (len) {
11759                 int j;
11760                 u32 phy_addr, page_off, size;
11761
11762                 phy_addr = offset & ~pagemask;
11763
11764                 for (j = 0; j < pagesize; j += 4) {
11765                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
11766                                                   (__be32 *) (tmp + j));
11767                         if (ret)
11768                                 break;
11769                 }
11770                 if (ret)
11771                         break;
11772
11773                 page_off = offset & pagemask;
11774                 size = pagesize;
11775                 if (len < size)
11776                         size = len;
11777
11778                 len -= size;
11779
11780                 memcpy(tmp + page_off, buf, size);
11781
11782                 offset = offset + (pagesize - page_off);
11783
11784                 tg3_enable_nvram_access(tp);
11785
11786                 /*
11787                  * Before we can erase the flash page, we need
11788                  * to issue a special "write enable" command.
11789                  */
11790                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11791
11792                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11793                         break;
11794
11795                 /* Erase the target page */
11796                 tw32(NVRAM_ADDR, phy_addr);
11797
11798                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11799                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11800
11801                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11802                         break;
11803
11804                 /* Issue another write enable to start the write. */
11805                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11806
11807                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11808                         break;
11809
11810                 for (j = 0; j < pagesize; j += 4) {
11811                         __be32 data;
11812
11813                         data = *((__be32 *) (tmp + j));
11814
11815                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
11816
11817                         tw32(NVRAM_ADDR, phy_addr + j);
11818
11819                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11820                                 NVRAM_CMD_WR;
11821
11822                         if (j == 0)
11823                                 nvram_cmd |= NVRAM_CMD_FIRST;
11824                         else if (j == (pagesize - 4))
11825                                 nvram_cmd |= NVRAM_CMD_LAST;
11826
11827                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11828                                 break;
11829                 }
11830                 if (ret)
11831                         break;
11832         }
11833
11834         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11835         tg3_nvram_exec_cmd(tp, nvram_cmd);
11836
11837         kfree(tmp);
11838
11839         return ret;
11840 }
11841
11842 /* offset and length are dword aligned */
11843 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11844                 u8 *buf)
11845 {
11846         int i, ret = 0;
11847
11848         for (i = 0; i < len; i += 4, offset += 4) {
11849                 u32 page_off, phy_addr, nvram_cmd;
11850                 __be32 data;
11851
11852                 memcpy(&data, buf + i, 4);
11853                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11854
11855                 page_off = offset % tp->nvram_pagesize;
11856
11857                 phy_addr = tg3_nvram_phys_addr(tp, offset);
11858
11859                 tw32(NVRAM_ADDR, phy_addr);
11860
11861                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11862
11863                 if (page_off == 0 || i == 0)
11864                         nvram_cmd |= NVRAM_CMD_FIRST;
11865                 if (page_off == (tp->nvram_pagesize - 4))
11866                         nvram_cmd |= NVRAM_CMD_LAST;
11867
11868                 if (i == (len - 4))
11869                         nvram_cmd |= NVRAM_CMD_LAST;
11870
11871                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11872                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11873                     (tp->nvram_jedecnum == JEDEC_ST) &&
11874                     (nvram_cmd & NVRAM_CMD_FIRST)) {
11875
11876                         if ((ret = tg3_nvram_exec_cmd(tp,
11877                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11878                                 NVRAM_CMD_DONE)))
11879
11880                                 break;
11881                 }
11882                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11883                         /* We always do complete word writes to eeprom. */
11884                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11885                 }
11886
11887                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11888                         break;
11889         }
11890         return ret;
11891 }
11892
11893 /* offset and length are dword aligned */
11894 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11895 {
11896         int ret;
11897
11898         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11899                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11900                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
11901                 udelay(40);
11902         }
11903
11904         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11905                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11906         } else {
11907                 u32 grc_mode;
11908
11909                 ret = tg3_nvram_lock(tp);
11910                 if (ret)
11911                         return ret;
11912
11913                 tg3_enable_nvram_access(tp);
11914                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11915                     !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
11916                         tw32(NVRAM_WRITE1, 0x406);
11917
11918                 grc_mode = tr32(GRC_MODE);
11919                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11920
11921                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11922                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11923
11924                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
11925                                 buf);
11926                 } else {
11927                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11928                                 buf);
11929                 }
11930
11931                 grc_mode = tr32(GRC_MODE);
11932                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11933
11934                 tg3_disable_nvram_access(tp);
11935                 tg3_nvram_unlock(tp);
11936         }
11937
11938         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11939                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11940                 udelay(40);
11941         }
11942
11943         return ret;
11944 }
11945
11946 struct subsys_tbl_ent {
11947         u16 subsys_vendor, subsys_devid;
11948         u32 phy_id;
11949 };
11950
11951 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
11952         /* Broadcom boards. */
11953         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11954           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
11955         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11956           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
11957         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11958           TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
11959         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11960           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
11961         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11962           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
11963         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11964           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
11965         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11966           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
11967         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11968           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
11969         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11970           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
11971         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11972           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
11973         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11974           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
11975
11976         /* 3com boards. */
11977         { TG3PCI_SUBVENDOR_ID_3COM,
11978           TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
11979         { TG3PCI_SUBVENDOR_ID_3COM,
11980           TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
11981         { TG3PCI_SUBVENDOR_ID_3COM,
11982           TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
11983         { TG3PCI_SUBVENDOR_ID_3COM,
11984           TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
11985         { TG3PCI_SUBVENDOR_ID_3COM,
11986           TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
11987
11988         /* DELL boards. */
11989         { TG3PCI_SUBVENDOR_ID_DELL,
11990           TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
11991         { TG3PCI_SUBVENDOR_ID_DELL,
11992           TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
11993         { TG3PCI_SUBVENDOR_ID_DELL,
11994           TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
11995         { TG3PCI_SUBVENDOR_ID_DELL,
11996           TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
11997
11998         /* Compaq boards. */
11999         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12000           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
12001         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12002           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
12003         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12004           TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
12005         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12006           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
12007         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12008           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
12009
12010         /* IBM boards. */
12011         { TG3PCI_SUBVENDOR_ID_IBM,
12012           TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
12013 };
12014
12015 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
12016 {
12017         int i;
12018
12019         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12020                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12021                      tp->pdev->subsystem_vendor) &&
12022                     (subsys_id_to_phy_id[i].subsys_devid ==
12023                      tp->pdev->subsystem_device))
12024                         return &subsys_id_to_phy_id[i];
12025         }
12026         return NULL;
12027 }
12028
12029 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12030 {
12031         u32 val;
12032         u16 pmcsr;
12033
12034         /* On some early chips the SRAM cannot be accessed in D3hot state,
12035          * so need make sure we're in D0.
12036          */
12037         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12038         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12039         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12040         msleep(1);
12041
12042         /* Make sure register accesses (indirect or otherwise)
12043          * will function correctly.
12044          */
12045         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12046                                tp->misc_host_ctrl);
12047
12048         /* The memory arbiter has to be enabled in order for SRAM accesses
12049          * to succeed.  Normally on powerup the tg3 chip firmware will make
12050          * sure it is enabled, but other entities such as system netboot
12051          * code might disable it.
12052          */
12053         val = tr32(MEMARB_MODE);
12054         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12055
12056         tp->phy_id = TG3_PHY_ID_INVALID;
12057         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12058
12059         /* Assume an onboard device and WOL capable by default.  */
12060         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12061
12062         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12063                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12064                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12065                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12066                 }
12067                 val = tr32(VCPU_CFGSHDW);
12068                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12069                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12070                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12071                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
12072                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12073                 goto done;
12074         }
12075
12076         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12077         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12078                 u32 nic_cfg, led_cfg;
12079                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12080                 int eeprom_phy_serdes = 0;
12081
12082                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12083                 tp->nic_sram_data_cfg = nic_cfg;
12084
12085                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12086                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12087                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12088                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12089                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12090                     (ver > 0) && (ver < 0x100))
12091                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12092
12093                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12094                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12095
12096                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12097                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12098                         eeprom_phy_serdes = 1;
12099
12100                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12101                 if (nic_phy_id != 0) {
12102                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12103                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12104
12105                         eeprom_phy_id  = (id1 >> 16) << 10;
12106                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
12107                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
12108                 } else
12109                         eeprom_phy_id = 0;
12110
12111                 tp->phy_id = eeprom_phy_id;
12112                 if (eeprom_phy_serdes) {
12113                         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12114                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12115                         else
12116                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
12117                 }
12118
12119                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12120                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12121                                     SHASTA_EXT_LED_MODE_MASK);
12122                 else
12123                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12124
12125                 switch (led_cfg) {
12126                 default:
12127                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12128                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12129                         break;
12130
12131                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12132                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12133                         break;
12134
12135                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12136                         tp->led_ctrl = LED_CTRL_MODE_MAC;
12137
12138                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12139                          * read on some older 5700/5701 bootcode.
12140                          */
12141                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12142                             ASIC_REV_5700 ||
12143                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
12144                             ASIC_REV_5701)
12145                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12146
12147                         break;
12148
12149                 case SHASTA_EXT_LED_SHARED:
12150                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
12151                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12152                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12153                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12154                                                  LED_CTRL_MODE_PHY_2);
12155                         break;
12156
12157                 case SHASTA_EXT_LED_MAC:
12158                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12159                         break;
12160
12161                 case SHASTA_EXT_LED_COMBO:
12162                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
12163                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12164                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12165                                                  LED_CTRL_MODE_PHY_2);
12166                         break;
12167
12168                 }
12169
12170                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12171                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12172                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12173                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12174
12175                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12176                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12177
12178                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12179                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12180                         if ((tp->pdev->subsystem_vendor ==
12181                              PCI_VENDOR_ID_ARIMA) &&
12182                             (tp->pdev->subsystem_device == 0x205a ||
12183                              tp->pdev->subsystem_device == 0x2063))
12184                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12185                 } else {
12186                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12187                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12188                 }
12189
12190                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12191                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12192                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12193                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12194                 }
12195
12196                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12197                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12198                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12199
12200                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
12201                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12202                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12203
12204                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12205                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12206                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12207
12208                 if (cfg2 & (1 << 17))
12209                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
12210
12211                 /* serdes signal pre-emphasis in register 0x590 set by */
12212                 /* bootcode if bit 18 is set */
12213                 if (cfg2 & (1 << 18))
12214                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
12215
12216                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12217                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
12218                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12219                         tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
12220
12221                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12222                         u32 cfg3;
12223
12224                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12225                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12226                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12227                 }
12228
12229                 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12230                         tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
12231                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12232                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12233                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12234                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12235         }
12236 done:
12237         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12238         device_set_wakeup_enable(&tp->pdev->dev,
12239                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12240 }
12241
12242 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12243 {
12244         int i;
12245         u32 val;
12246
12247         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12248         tw32(OTP_CTRL, cmd);
12249
12250         /* Wait for up to 1 ms for command to execute. */
12251         for (i = 0; i < 100; i++) {
12252                 val = tr32(OTP_STATUS);
12253                 if (val & OTP_STATUS_CMD_DONE)
12254                         break;
12255                 udelay(10);
12256         }
12257
12258         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12259 }
12260
12261 /* Read the gphy configuration from the OTP region of the chip.  The gphy
12262  * configuration is a 32-bit value that straddles the alignment boundary.
12263  * We do two 32-bit reads and then shift and merge the results.
12264  */
12265 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12266 {
12267         u32 bhalf_otp, thalf_otp;
12268
12269         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12270
12271         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12272                 return 0;
12273
12274         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12275
12276         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12277                 return 0;
12278
12279         thalf_otp = tr32(OTP_READ_DATA);
12280
12281         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12282
12283         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12284                 return 0;
12285
12286         bhalf_otp = tr32(OTP_READ_DATA);
12287
12288         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12289 }
12290
12291 static int __devinit tg3_phy_probe(struct tg3 *tp)
12292 {
12293         u32 hw_phy_id_1, hw_phy_id_2;
12294         u32 hw_phy_id, hw_phy_id_masked;
12295         int err;
12296
12297         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12298                 return tg3_phy_init(tp);
12299
12300         /* Reading the PHY ID register can conflict with ASF
12301          * firmware access to the PHY hardware.
12302          */
12303         err = 0;
12304         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12305             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12306                 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
12307         } else {
12308                 /* Now read the physical PHY_ID from the chip and verify
12309                  * that it is sane.  If it doesn't look good, we fall back
12310                  * to either the hard-coded table based PHY_ID and failing
12311                  * that the value found in the eeprom area.
12312                  */
12313                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12314                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12315
12316                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
12317                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12318                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
12319
12320                 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
12321         }
12322
12323         if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
12324                 tp->phy_id = hw_phy_id;
12325                 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
12326                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12327                 else
12328                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
12329         } else {
12330                 if (tp->phy_id != TG3_PHY_ID_INVALID) {
12331                         /* Do nothing, phy ID already set up in
12332                          * tg3_get_eeprom_hw_cfg().
12333                          */
12334                 } else {
12335                         struct subsys_tbl_ent *p;
12336
12337                         /* No eeprom signature?  Try the hardcoded
12338                          * subsys device table.
12339                          */
12340                         p = tg3_lookup_by_subsys(tp);
12341                         if (!p)
12342                                 return -ENODEV;
12343
12344                         tp->phy_id = p->phy_id;
12345                         if (!tp->phy_id ||
12346                             tp->phy_id == TG3_PHY_ID_BCM8002)
12347                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12348                 }
12349         }
12350
12351         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
12352             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12353             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12354                 u32 bmsr, adv_reg, tg3_ctrl, mask;
12355
12356                 tg3_readphy(tp, MII_BMSR, &bmsr);
12357                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12358                     (bmsr & BMSR_LSTATUS))
12359                         goto skip_phy_reset;
12360
12361                 err = tg3_phy_reset(tp);
12362                 if (err)
12363                         return err;
12364
12365                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12366                            ADVERTISE_100HALF | ADVERTISE_100FULL |
12367                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12368                 tg3_ctrl = 0;
12369                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12370                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12371                                     MII_TG3_CTRL_ADV_1000_FULL);
12372                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12373                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12374                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12375                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
12376                 }
12377
12378                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12379                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12380                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12381                 if (!tg3_copper_is_advertising_all(tp, mask)) {
12382                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12383
12384                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12385                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12386
12387                         tg3_writephy(tp, MII_BMCR,
12388                                      BMCR_ANENABLE | BMCR_ANRESTART);
12389                 }
12390                 tg3_phy_set_wirespeed(tp);
12391
12392                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12393                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12394                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12395         }
12396
12397 skip_phy_reset:
12398         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
12399                 err = tg3_init_5401phy_dsp(tp);
12400                 if (err)
12401                         return err;
12402
12403                 err = tg3_init_5401phy_dsp(tp);
12404         }
12405
12406         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
12407                 tp->link_config.advertising =
12408                         (ADVERTISED_1000baseT_Half |
12409                          ADVERTISED_1000baseT_Full |
12410                          ADVERTISED_Autoneg |
12411                          ADVERTISED_FIBRE);
12412         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12413                 tp->link_config.advertising &=
12414                         ~(ADVERTISED_1000baseT_Half |
12415                           ADVERTISED_1000baseT_Full);
12416
12417         return err;
12418 }
12419
12420 static void __devinit tg3_read_vpd(struct tg3 *tp)
12421 {
12422         u8 vpd_data[TG3_NVM_VPD_LEN];
12423         unsigned int block_end, rosize, len;
12424         int j, i = 0;
12425         u32 magic;
12426
12427         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12428             tg3_nvram_read(tp, 0x0, &magic))
12429                 goto out_not_found;
12430
12431         if (magic == TG3_EEPROM_MAGIC) {
12432                 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12433                         u32 tmp;
12434
12435                         /* The data is in little-endian format in NVRAM.
12436                          * Use the big-endian read routines to preserve
12437                          * the byte order as it exists in NVRAM.
12438                          */
12439                         if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12440                                 goto out_not_found;
12441
12442                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12443                 }
12444         } else {
12445                 ssize_t cnt;
12446                 unsigned int pos = 0;
12447
12448                 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12449                         cnt = pci_read_vpd(tp->pdev, pos,
12450                                            TG3_NVM_VPD_LEN - pos,
12451                                            &vpd_data[pos]);
12452                         if (cnt == -ETIMEDOUT || -EINTR)
12453                                 cnt = 0;
12454                         else if (cnt < 0)
12455                                 goto out_not_found;
12456                 }
12457                 if (pos != TG3_NVM_VPD_LEN)
12458                         goto out_not_found;
12459         }
12460
12461         i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
12462                              PCI_VPD_LRDT_RO_DATA);
12463         if (i < 0)
12464                 goto out_not_found;
12465
12466         rosize = pci_vpd_lrdt_size(&vpd_data[i]);
12467         block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
12468         i += PCI_VPD_LRDT_TAG_SIZE;
12469
12470         if (block_end > TG3_NVM_VPD_LEN)
12471                 goto out_not_found;
12472
12473         j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12474                                       PCI_VPD_RO_KEYWORD_MFR_ID);
12475         if (j > 0) {
12476                 len = pci_vpd_info_field_size(&vpd_data[j]);
12477
12478                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12479                 if (j + len > block_end || len != 4 ||
12480                     memcmp(&vpd_data[j], "1028", 4))
12481                         goto partno;
12482
12483                 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12484                                               PCI_VPD_RO_KEYWORD_VENDOR0);
12485                 if (j < 0)
12486                         goto partno;
12487
12488                 len = pci_vpd_info_field_size(&vpd_data[j]);
12489
12490                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12491                 if (j + len > block_end)
12492                         goto partno;
12493
12494                 memcpy(tp->fw_ver, &vpd_data[j], len);
12495                 strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
12496         }
12497
12498 partno:
12499         i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12500                                       PCI_VPD_RO_KEYWORD_PARTNO);
12501         if (i < 0)
12502                 goto out_not_found;
12503
12504         len = pci_vpd_info_field_size(&vpd_data[i]);
12505
12506         i += PCI_VPD_INFO_FLD_HDR_SIZE;
12507         if (len > TG3_BPN_SIZE ||
12508             (len + i) > TG3_NVM_VPD_LEN)
12509                 goto out_not_found;
12510
12511         memcpy(tp->board_part_number, &vpd_data[i], len);
12512
12513         return;
12514
12515 out_not_found:
12516         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12517                 strcpy(tp->board_part_number, "BCM95906");
12518         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12519                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12520                 strcpy(tp->board_part_number, "BCM57780");
12521         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12522                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12523                 strcpy(tp->board_part_number, "BCM57760");
12524         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12525                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12526                 strcpy(tp->board_part_number, "BCM57790");
12527         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12528                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12529                 strcpy(tp->board_part_number, "BCM57788");
12530         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12531                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
12532                 strcpy(tp->board_part_number, "BCM57761");
12533         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12534                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
12535                 strcpy(tp->board_part_number, "BCM57765");
12536         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12537                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
12538                 strcpy(tp->board_part_number, "BCM57781");
12539         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12540                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
12541                 strcpy(tp->board_part_number, "BCM57785");
12542         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12543                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
12544                 strcpy(tp->board_part_number, "BCM57791");
12545         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12546                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12547                 strcpy(tp->board_part_number, "BCM57795");
12548         else
12549                 strcpy(tp->board_part_number, "none");
12550 }
12551
12552 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12553 {
12554         u32 val;
12555
12556         if (tg3_nvram_read(tp, offset, &val) ||
12557             (val & 0xfc000000) != 0x0c000000 ||
12558             tg3_nvram_read(tp, offset + 4, &val) ||
12559             val != 0)
12560                 return 0;
12561
12562         return 1;
12563 }
12564
12565 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12566 {
12567         u32 val, offset, start, ver_offset;
12568         int i, dst_off;
12569         bool newver = false;
12570
12571         if (tg3_nvram_read(tp, 0xc, &offset) ||
12572             tg3_nvram_read(tp, 0x4, &start))
12573                 return;
12574
12575         offset = tg3_nvram_logical_addr(tp, offset);
12576
12577         if (tg3_nvram_read(tp, offset, &val))
12578                 return;
12579
12580         if ((val & 0xfc000000) == 0x0c000000) {
12581                 if (tg3_nvram_read(tp, offset + 4, &val))
12582                         return;
12583
12584                 if (val == 0)
12585                         newver = true;
12586         }
12587
12588         dst_off = strlen(tp->fw_ver);
12589
12590         if (newver) {
12591                 if (TG3_VER_SIZE - dst_off < 16 ||
12592                     tg3_nvram_read(tp, offset + 8, &ver_offset))
12593                         return;
12594
12595                 offset = offset + ver_offset - start;
12596                 for (i = 0; i < 16; i += 4) {
12597                         __be32 v;
12598                         if (tg3_nvram_read_be32(tp, offset + i, &v))
12599                                 return;
12600
12601                         memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
12602                 }
12603         } else {
12604                 u32 major, minor;
12605
12606                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12607                         return;
12608
12609                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12610                         TG3_NVM_BCVER_MAJSFT;
12611                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12612                 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
12613                          "v%d.%02d", major, minor);
12614         }
12615 }
12616
12617 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12618 {
12619         u32 val, major, minor;
12620
12621         /* Use native endian representation */
12622         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12623                 return;
12624
12625         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12626                 TG3_NVM_HWSB_CFG1_MAJSFT;
12627         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12628                 TG3_NVM_HWSB_CFG1_MINSFT;
12629
12630         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12631 }
12632
12633 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12634 {
12635         u32 offset, major, minor, build;
12636
12637         strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
12638
12639         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12640                 return;
12641
12642         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12643         case TG3_EEPROM_SB_REVISION_0:
12644                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12645                 break;
12646         case TG3_EEPROM_SB_REVISION_2:
12647                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12648                 break;
12649         case TG3_EEPROM_SB_REVISION_3:
12650                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12651                 break;
12652         case TG3_EEPROM_SB_REVISION_4:
12653                 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
12654                 break;
12655         case TG3_EEPROM_SB_REVISION_5:
12656                 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
12657                 break;
12658         default:
12659                 return;
12660         }
12661
12662         if (tg3_nvram_read(tp, offset, &val))
12663                 return;
12664
12665         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12666                 TG3_EEPROM_SB_EDH_BLD_SHFT;
12667         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12668                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12669         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
12670
12671         if (minor > 99 || build > 26)
12672                 return;
12673
12674         offset = strlen(tp->fw_ver);
12675         snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
12676                  " v%d.%02d", major, minor);
12677
12678         if (build > 0) {
12679                 offset = strlen(tp->fw_ver);
12680                 if (offset < TG3_VER_SIZE - 1)
12681                         tp->fw_ver[offset] = 'a' + build - 1;
12682         }
12683 }
12684
12685 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12686 {
12687         u32 val, offset, start;
12688         int i, vlen;
12689
12690         for (offset = TG3_NVM_DIR_START;
12691              offset < TG3_NVM_DIR_END;
12692              offset += TG3_NVM_DIRENT_SIZE) {
12693                 if (tg3_nvram_read(tp, offset, &val))
12694                         return;
12695
12696                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12697                         break;
12698         }
12699
12700         if (offset == TG3_NVM_DIR_END)
12701                 return;
12702
12703         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12704                 start = 0x08000000;
12705         else if (tg3_nvram_read(tp, offset - 4, &start))
12706                 return;
12707
12708         if (tg3_nvram_read(tp, offset + 4, &offset) ||
12709             !tg3_fw_img_is_valid(tp, offset) ||
12710             tg3_nvram_read(tp, offset + 8, &val))
12711                 return;
12712
12713         offset += val - start;
12714
12715         vlen = strlen(tp->fw_ver);
12716
12717         tp->fw_ver[vlen++] = ',';
12718         tp->fw_ver[vlen++] = ' ';
12719
12720         for (i = 0; i < 4; i++) {
12721                 __be32 v;
12722                 if (tg3_nvram_read_be32(tp, offset, &v))
12723                         return;
12724
12725                 offset += sizeof(v);
12726
12727                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12728                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12729                         break;
12730                 }
12731
12732                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12733                 vlen += sizeof(v);
12734         }
12735 }
12736
12737 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12738 {
12739         int vlen;
12740         u32 apedata;
12741
12742         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12743             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
12744                 return;
12745
12746         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12747         if (apedata != APE_SEG_SIG_MAGIC)
12748                 return;
12749
12750         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12751         if (!(apedata & APE_FW_STATUS_READY))
12752                 return;
12753
12754         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12755
12756         vlen = strlen(tp->fw_ver);
12757
12758         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12759                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12760                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12761                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12762                  (apedata & APE_FW_VERSION_BLDMSK));
12763 }
12764
12765 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12766 {
12767         u32 val;
12768         bool vpd_vers = false;
12769
12770         if (tp->fw_ver[0] != 0)
12771                 vpd_vers = true;
12772
12773         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12774                 strcat(tp->fw_ver, "sb");
12775                 return;
12776         }
12777
12778         if (tg3_nvram_read(tp, 0, &val))
12779                 return;
12780
12781         if (val == TG3_EEPROM_MAGIC)
12782                 tg3_read_bc_ver(tp);
12783         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12784                 tg3_read_sb_ver(tp, val);
12785         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12786                 tg3_read_hwsb_ver(tp);
12787         else
12788                 return;
12789
12790         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12791              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
12792                 goto done;
12793
12794         tg3_read_mgmtfw_ver(tp);
12795
12796 done:
12797         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12798 }
12799
12800 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12801
12802 static int __devinit tg3_get_invariants(struct tg3 *tp)
12803 {
12804         static struct pci_device_id write_reorder_chipsets[] = {
12805                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12806                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12807                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12808                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12809                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12810                              PCI_DEVICE_ID_VIA_8385_0) },
12811                 { },
12812         };
12813         u32 misc_ctrl_reg;
12814         u32 pci_state_reg, grc_misc_cfg;
12815         u32 val;
12816         u16 pci_cmd;
12817         int err;
12818
12819         /* Force memory write invalidate off.  If we leave it on,
12820          * then on 5700_BX chips we have to enable a workaround.
12821          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12822          * to match the cacheline size.  The Broadcom driver have this
12823          * workaround but turns MWI off all the times so never uses
12824          * it.  This seems to suggest that the workaround is insufficient.
12825          */
12826         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12827         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12828         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12829
12830         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12831          * has the register indirect write enable bit set before
12832          * we try to access any of the MMIO registers.  It is also
12833          * critical that the PCI-X hw workaround situation is decided
12834          * before that as well.
12835          */
12836         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12837                               &misc_ctrl_reg);
12838
12839         tp->pci_chip_rev_id = (misc_ctrl_reg >>
12840                                MISC_HOST_CTRL_CHIPREV_SHIFT);
12841         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12842                 u32 prod_id_asic_rev;
12843
12844                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12845                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12846                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724 ||
12847                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719)
12848                         pci_read_config_dword(tp->pdev,
12849                                               TG3PCI_GEN2_PRODID_ASICREV,
12850                                               &prod_id_asic_rev);
12851                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
12852                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
12853                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
12854                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
12855                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
12856                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12857                         pci_read_config_dword(tp->pdev,
12858                                               TG3PCI_GEN15_PRODID_ASICREV,
12859                                               &prod_id_asic_rev);
12860                 else
12861                         pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12862                                               &prod_id_asic_rev);
12863
12864                 tp->pci_chip_rev_id = prod_id_asic_rev;
12865         }
12866
12867         /* Wrong chip ID in 5752 A0. This code can be removed later
12868          * as A0 is not in production.
12869          */
12870         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12871                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12872
12873         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12874          * we need to disable memory and use config. cycles
12875          * only to access all registers. The 5702/03 chips
12876          * can mistakenly decode the special cycles from the
12877          * ICH chipsets as memory write cycles, causing corruption
12878          * of register and memory space. Only certain ICH bridges
12879          * will drive special cycles with non-zero data during the
12880          * address phase which can fall within the 5703's address
12881          * range. This is not an ICH bug as the PCI spec allows
12882          * non-zero address during special cycles. However, only
12883          * these ICH bridges are known to drive non-zero addresses
12884          * during special cycles.
12885          *
12886          * Since special cycles do not cross PCI bridges, we only
12887          * enable this workaround if the 5703 is on the secondary
12888          * bus of these ICH bridges.
12889          */
12890         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12891             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12892                 static struct tg3_dev_id {
12893                         u32     vendor;
12894                         u32     device;
12895                         u32     rev;
12896                 } ich_chipsets[] = {
12897                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12898                           PCI_ANY_ID },
12899                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12900                           PCI_ANY_ID },
12901                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12902                           0xa },
12903                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12904                           PCI_ANY_ID },
12905                         { },
12906                 };
12907                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12908                 struct pci_dev *bridge = NULL;
12909
12910                 while (pci_id->vendor != 0) {
12911                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
12912                                                 bridge);
12913                         if (!bridge) {
12914                                 pci_id++;
12915                                 continue;
12916                         }
12917                         if (pci_id->rev != PCI_ANY_ID) {
12918                                 if (bridge->revision > pci_id->rev)
12919                                         continue;
12920                         }
12921                         if (bridge->subordinate &&
12922                             (bridge->subordinate->number ==
12923                              tp->pdev->bus->number)) {
12924
12925                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12926                                 pci_dev_put(bridge);
12927                                 break;
12928                         }
12929                 }
12930         }
12931
12932         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12933                 static struct tg3_dev_id {
12934                         u32     vendor;
12935                         u32     device;
12936                 } bridge_chipsets[] = {
12937                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12938                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12939                         { },
12940                 };
12941                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12942                 struct pci_dev *bridge = NULL;
12943
12944                 while (pci_id->vendor != 0) {
12945                         bridge = pci_get_device(pci_id->vendor,
12946                                                 pci_id->device,
12947                                                 bridge);
12948                         if (!bridge) {
12949                                 pci_id++;
12950                                 continue;
12951                         }
12952                         if (bridge->subordinate &&
12953                             (bridge->subordinate->number <=
12954                              tp->pdev->bus->number) &&
12955                             (bridge->subordinate->subordinate >=
12956                              tp->pdev->bus->number)) {
12957                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12958                                 pci_dev_put(bridge);
12959                                 break;
12960                         }
12961                 }
12962         }
12963
12964         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12965          * DMA addresses > 40-bit. This bridge may have other additional
12966          * 57xx devices behind it in some 4-port NIC designs for example.
12967          * Any tg3 device found behind the bridge will also need the 40-bit
12968          * DMA workaround.
12969          */
12970         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12971             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12972                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
12973                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12974                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
12975         } else {
12976                 struct pci_dev *bridge = NULL;
12977
12978                 do {
12979                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12980                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
12981                                                 bridge);
12982                         if (bridge && bridge->subordinate &&
12983                             (bridge->subordinate->number <=
12984                              tp->pdev->bus->number) &&
12985                             (bridge->subordinate->subordinate >=
12986                              tp->pdev->bus->number)) {
12987                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12988                                 pci_dev_put(bridge);
12989                                 break;
12990                         }
12991                 } while (bridge);
12992         }
12993
12994         /* Initialize misc host control in PCI block. */
12995         tp->misc_host_ctrl |= (misc_ctrl_reg &
12996                                MISC_HOST_CTRL_CHIPREV);
12997         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12998                                tp->misc_host_ctrl);
12999
13000         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13001             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13002             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13003                 tp->pdev_peer = tg3_find_peer(tp);
13004
13005         /* Intentionally exclude ASIC_REV_5906 */
13006         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13007             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13008             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13009             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13010             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13011             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13012             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13013             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13014             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13015                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13016
13017         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13018             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13019             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13020             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13021             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13022                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13023
13024         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13025             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13026                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13027
13028         /* 5700 B0 chips do not support checksumming correctly due
13029          * to hardware bugs.
13030          */
13031         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13032                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13033         else {
13034                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13035                 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
13036                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13037                         tp->dev->features |= NETIF_F_IPV6_CSUM;
13038                 tp->dev->features |= NETIF_F_GRO;
13039         }
13040
13041         /* Determine TSO capabilities */
13042         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13043             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13044             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13045                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13046         else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13047                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13048                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13049         else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13050                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13051                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13052                     tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13053                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13054         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13055                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13056                    tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13057                 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13058                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13059                         tp->fw_needed = FIRMWARE_TG3TSO5;
13060                 else
13061                         tp->fw_needed = FIRMWARE_TG3TSO;
13062         }
13063
13064         tp->irq_max = 1;
13065
13066         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13067                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13068                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13069                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13070                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13071                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13072                      tp->pdev_peer == tp->pdev))
13073                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13074
13075                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13076                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13077                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13078                 }
13079
13080                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13081                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13082                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13083                         tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13084                         tp->irq_max = TG3_IRQ_MAX_VECS;
13085                 }
13086         }
13087
13088         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13089             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13090             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13091                 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13092         else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13093                 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13094                 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13095         }
13096
13097         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13098             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13099             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13100                 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13101
13102         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13103             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13104             (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13105                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13106
13107         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13108                               &pci_state_reg);
13109
13110         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13111         if (tp->pcie_cap != 0) {
13112                 u16 lnkctl;
13113
13114                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13115
13116                 pcie_set_readrq(tp->pdev, 4096);
13117
13118                 pci_read_config_word(tp->pdev,
13119                                      tp->pcie_cap + PCI_EXP_LNKCTL,
13120                                      &lnkctl);
13121                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13122                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13123                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13124                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13125                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13126                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13127                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13128                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13129                 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13130                         tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13131                 }
13132         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13133                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13134         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13135                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13136                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13137                 if (!tp->pcix_cap) {
13138                         dev_err(&tp->pdev->dev,
13139                                 "Cannot find PCI-X capability, aborting\n");
13140                         return -EIO;
13141                 }
13142
13143                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13144                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13145         }
13146
13147         /* If we have an AMD 762 or VIA K8T800 chipset, write
13148          * reordering to the mailbox registers done by the host
13149          * controller can cause major troubles.  We read back from
13150          * every mailbox register write to force the writes to be
13151          * posted to the chip in order.
13152          */
13153         if (pci_dev_present(write_reorder_chipsets) &&
13154             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13155                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13156
13157         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13158                              &tp->pci_cacheline_sz);
13159         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13160                              &tp->pci_lat_timer);
13161         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13162             tp->pci_lat_timer < 64) {
13163                 tp->pci_lat_timer = 64;
13164                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13165                                       tp->pci_lat_timer);
13166         }
13167
13168         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13169                 /* 5700 BX chips need to have their TX producer index
13170                  * mailboxes written twice to workaround a bug.
13171                  */
13172                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13173
13174                 /* If we are in PCI-X mode, enable register write workaround.
13175                  *
13176                  * The workaround is to use indirect register accesses
13177                  * for all chip writes not to mailbox registers.
13178                  */
13179                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13180                         u32 pm_reg;
13181
13182                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13183
13184                         /* The chip can have it's power management PCI config
13185                          * space registers clobbered due to this bug.
13186                          * So explicitly force the chip into D0 here.
13187                          */
13188                         pci_read_config_dword(tp->pdev,
13189                                               tp->pm_cap + PCI_PM_CTRL,
13190                                               &pm_reg);
13191                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13192                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13193                         pci_write_config_dword(tp->pdev,
13194                                                tp->pm_cap + PCI_PM_CTRL,
13195                                                pm_reg);
13196
13197                         /* Also, force SERR#/PERR# in PCI command. */
13198                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13199                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13200                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13201                 }
13202         }
13203
13204         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13205                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13206         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13207                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13208
13209         /* Chip-specific fixup from Broadcom driver */
13210         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13211             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13212                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13213                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13214         }
13215
13216         /* Default fast path register access methods */
13217         tp->read32 = tg3_read32;
13218         tp->write32 = tg3_write32;
13219         tp->read32_mbox = tg3_read32;
13220         tp->write32_mbox = tg3_write32;
13221         tp->write32_tx_mbox = tg3_write32;
13222         tp->write32_rx_mbox = tg3_write32;
13223
13224         /* Various workaround register access methods */
13225         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13226                 tp->write32 = tg3_write_indirect_reg32;
13227         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13228                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13229                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13230                 /*
13231                  * Back to back register writes can cause problems on these
13232                  * chips, the workaround is to read back all reg writes
13233                  * except those to mailbox regs.
13234                  *
13235                  * See tg3_write_indirect_reg32().
13236                  */
13237                 tp->write32 = tg3_write_flush_reg32;
13238         }
13239
13240         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13241             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13242                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13243                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13244                         tp->write32_rx_mbox = tg3_write_flush_reg32;
13245         }
13246
13247         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13248                 tp->read32 = tg3_read_indirect_reg32;
13249                 tp->write32 = tg3_write_indirect_reg32;
13250                 tp->read32_mbox = tg3_read_indirect_mbox;
13251                 tp->write32_mbox = tg3_write_indirect_mbox;
13252                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13253                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13254
13255                 iounmap(tp->regs);
13256                 tp->regs = NULL;
13257
13258                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13259                 pci_cmd &= ~PCI_COMMAND_MEMORY;
13260                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13261         }
13262         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13263                 tp->read32_mbox = tg3_read32_mbox_5906;
13264                 tp->write32_mbox = tg3_write32_mbox_5906;
13265                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13266                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13267         }
13268
13269         if (tp->write32 == tg3_write_indirect_reg32 ||
13270             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13271              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13272               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13273                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13274
13275         /* Get eeprom hw config before calling tg3_set_power_state().
13276          * In particular, the TG3_FLG2_IS_NIC flag must be
13277          * determined before calling tg3_set_power_state() so that
13278          * we know whether or not to switch out of Vaux power.
13279          * When the flag is set, it means that GPIO1 is used for eeprom
13280          * write protect and also implies that it is a LOM where GPIOs
13281          * are not used to switch power.
13282          */
13283         tg3_get_eeprom_hw_cfg(tp);
13284
13285         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13286                 /* Allow reads and writes to the
13287                  * APE register and memory space.
13288                  */
13289                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13290                                  PCISTATE_ALLOW_APE_SHMEM_WR |
13291                                  PCISTATE_ALLOW_APE_PSPACE_WR;
13292                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13293                                        pci_state_reg);
13294         }
13295
13296         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13297             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13298             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13299             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13300             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13301             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13302             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13303                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13304
13305         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13306          * GPIO1 driven high will bring 5700's external PHY out of reset.
13307          * It is also used as eeprom write protect on LOMs.
13308          */
13309         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13310         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13311             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13312                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13313                                        GRC_LCLCTRL_GPIO_OUTPUT1);
13314         /* Unused GPIO3 must be driven as output on 5752 because there
13315          * are no pull-up resistors on unused GPIO pins.
13316          */
13317         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13318                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13319
13320         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13321             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13322             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13323                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13324
13325         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13326             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13327                 /* Turn off the debug UART. */
13328                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13329                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13330                         /* Keep VMain power. */
13331                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13332                                               GRC_LCLCTRL_GPIO_OUTPUT0;
13333         }
13334
13335         /* Force the chip into D0. */
13336         err = tg3_set_power_state(tp, PCI_D0);
13337         if (err) {
13338                 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
13339                 return err;
13340         }
13341
13342         /* Derive initial jumbo mode from MTU assigned in
13343          * ether_setup() via the alloc_etherdev() call
13344          */
13345         if (tp->dev->mtu > ETH_DATA_LEN &&
13346             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13347                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13348
13349         /* Determine WakeOnLan speed to use. */
13350         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13351             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13352             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13353             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13354                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13355         } else {
13356                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13357         }
13358
13359         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13360                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
13361
13362         /* A few boards don't want Ethernet@WireSpeed phy feature */
13363         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13364             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13365              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13366              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13367             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
13368             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
13369                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
13370
13371         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13372             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13373                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
13374         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13375                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
13376
13377         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13378             !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
13379             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13380             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13381             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
13382             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719 &&
13383             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
13384                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13385                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13386                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13387                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13388                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13389                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13390                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
13391                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13392                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
13393                 } else
13394                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
13395         }
13396
13397         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13398             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13399                 tp->phy_otp = tg3_read_otp_phycfg(tp);
13400                 if (tp->phy_otp == 0)
13401                         tp->phy_otp = TG3_OTP_DEFAULT;
13402         }
13403
13404         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13405                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13406         else
13407                 tp->mi_mode = MAC_MI_MODE_BASE;
13408
13409         tp->coalesce_mode = 0;
13410         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13411             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13412                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13413
13414         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13415             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13416                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13417
13418         err = tg3_mdio_init(tp);
13419         if (err)
13420                 return err;
13421
13422         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
13423             (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0 ||
13424                  (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
13425                 return -ENOTSUPP;
13426
13427         /* Initialize data/descriptor byte/word swapping. */
13428         val = tr32(GRC_MODE);
13429         val &= GRC_MODE_HOST_STACKUP;
13430         tw32(GRC_MODE, val | tp->grc_mode);
13431
13432         tg3_switch_clocks(tp);
13433
13434         /* Clear this out for sanity. */
13435         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13436
13437         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13438                               &pci_state_reg);
13439         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13440             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13441                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13442
13443                 if (chiprevid == CHIPREV_ID_5701_A0 ||
13444                     chiprevid == CHIPREV_ID_5701_B0 ||
13445                     chiprevid == CHIPREV_ID_5701_B2 ||
13446                     chiprevid == CHIPREV_ID_5701_B5) {
13447                         void __iomem *sram_base;
13448
13449                         /* Write some dummy words into the SRAM status block
13450                          * area, see if it reads back correctly.  If the return
13451                          * value is bad, force enable the PCIX workaround.
13452                          */
13453                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13454
13455                         writel(0x00000000, sram_base);
13456                         writel(0x00000000, sram_base + 4);
13457                         writel(0xffffffff, sram_base + 4);
13458                         if (readl(sram_base) != 0x00000000)
13459                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13460                 }
13461         }
13462
13463         udelay(50);
13464         tg3_nvram_init(tp);
13465
13466         grc_misc_cfg = tr32(GRC_MISC_CFG);
13467         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13468
13469         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13470             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13471              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13472                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13473
13474         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13475             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13476                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13477         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13478                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13479                                       HOSTCC_MODE_CLRTICK_TXBD);
13480
13481                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13482                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13483                                        tp->misc_host_ctrl);
13484         }
13485
13486         /* Preserve the APE MAC_MODE bits */
13487         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13488                 tp->mac_mode = tr32(MAC_MODE) |
13489                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13490         else
13491                 tp->mac_mode = TG3_DEF_MAC_MODE;
13492
13493         /* these are limited to 10/100 only */
13494         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13495              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13496             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13497              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13498              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13499               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13500               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13501             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13502              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13503               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13504               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13505             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13506             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13507             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
13508             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
13509                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13510
13511         err = tg3_phy_probe(tp);
13512         if (err) {
13513                 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
13514                 /* ... but do not return immediately ... */
13515                 tg3_mdio_fini(tp);
13516         }
13517
13518         tg3_read_vpd(tp);
13519         tg3_read_fw_ver(tp);
13520
13521         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13522                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13523         } else {
13524                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13525                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13526                 else
13527                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13528         }
13529
13530         /* 5700 {AX,BX} chips have a broken status block link
13531          * change bit implementation, so we must use the
13532          * status register in those cases.
13533          */
13534         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13535                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13536         else
13537                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13538
13539         /* The led_ctrl is set during tg3_phy_probe, here we might
13540          * have to force the link status polling mechanism based
13541          * upon subsystem IDs.
13542          */
13543         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13544             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13545             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13546                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13547                                   TG3_FLAG_USE_LINKCHG_REG);
13548         }
13549
13550         /* For all SERDES we poll the MAC status register. */
13551         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13552                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13553         else
13554                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13555
13556         tp->rx_offset = NET_IP_ALIGN + TG3_RX_HEADROOM;
13557         tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
13558         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13559             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
13560                 tp->rx_offset -= NET_IP_ALIGN;
13561 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
13562                 tp->rx_copy_thresh = ~(u16)0;
13563 #endif
13564         }
13565
13566         tp->rx_std_max_post = TG3_RX_RING_SIZE;
13567
13568         /* Increment the rx prod index on the rx std ring by at most
13569          * 8 for these chips to workaround hw errata.
13570          */
13571         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13572             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13573             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13574                 tp->rx_std_max_post = 8;
13575
13576         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13577                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13578                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
13579
13580         return err;
13581 }
13582
13583 #ifdef CONFIG_SPARC
13584 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13585 {
13586         struct net_device *dev = tp->dev;
13587         struct pci_dev *pdev = tp->pdev;
13588         struct device_node *dp = pci_device_to_OF_node(pdev);
13589         const unsigned char *addr;
13590         int len;
13591
13592         addr = of_get_property(dp, "local-mac-address", &len);
13593         if (addr && len == 6) {
13594                 memcpy(dev->dev_addr, addr, 6);
13595                 memcpy(dev->perm_addr, dev->dev_addr, 6);
13596                 return 0;
13597         }
13598         return -ENODEV;
13599 }
13600
13601 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13602 {
13603         struct net_device *dev = tp->dev;
13604
13605         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13606         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13607         return 0;
13608 }
13609 #endif
13610
13611 static int __devinit tg3_get_device_address(struct tg3 *tp)
13612 {
13613         struct net_device *dev = tp->dev;
13614         u32 hi, lo, mac_offset;
13615         int addr_ok = 0;
13616
13617 #ifdef CONFIG_SPARC
13618         if (!tg3_get_macaddr_sparc(tp))
13619                 return 0;
13620 #endif
13621
13622         mac_offset = 0x7c;
13623         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13624             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13625                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13626                         mac_offset = 0xcc;
13627                 if (tg3_nvram_lock(tp))
13628                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13629                 else
13630                         tg3_nvram_unlock(tp);
13631         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13632                    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
13633                 if (PCI_FUNC(tp->pdev->devfn) & 1)
13634                         mac_offset = 0xcc;
13635                 if (PCI_FUNC(tp->pdev->devfn) > 1)
13636                         mac_offset += 0x18c;
13637         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13638                 mac_offset = 0x10;
13639
13640         /* First try to get it from MAC address mailbox. */
13641         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13642         if ((hi >> 16) == 0x484b) {
13643                 dev->dev_addr[0] = (hi >>  8) & 0xff;
13644                 dev->dev_addr[1] = (hi >>  0) & 0xff;
13645
13646                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13647                 dev->dev_addr[2] = (lo >> 24) & 0xff;
13648                 dev->dev_addr[3] = (lo >> 16) & 0xff;
13649                 dev->dev_addr[4] = (lo >>  8) & 0xff;
13650                 dev->dev_addr[5] = (lo >>  0) & 0xff;
13651
13652                 /* Some old bootcode may report a 0 MAC address in SRAM */
13653                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13654         }
13655         if (!addr_ok) {
13656                 /* Next, try NVRAM. */
13657                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13658                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13659                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13660                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13661                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13662                 }
13663                 /* Finally just fetch it out of the MAC control regs. */
13664                 else {
13665                         hi = tr32(MAC_ADDR_0_HIGH);
13666                         lo = tr32(MAC_ADDR_0_LOW);
13667
13668                         dev->dev_addr[5] = lo & 0xff;
13669                         dev->dev_addr[4] = (lo >> 8) & 0xff;
13670                         dev->dev_addr[3] = (lo >> 16) & 0xff;
13671                         dev->dev_addr[2] = (lo >> 24) & 0xff;
13672                         dev->dev_addr[1] = hi & 0xff;
13673                         dev->dev_addr[0] = (hi >> 8) & 0xff;
13674                 }
13675         }
13676
13677         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13678 #ifdef CONFIG_SPARC
13679                 if (!tg3_get_default_macaddr_sparc(tp))
13680                         return 0;
13681 #endif
13682                 return -EINVAL;
13683         }
13684         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13685         return 0;
13686 }
13687
13688 #define BOUNDARY_SINGLE_CACHELINE       1
13689 #define BOUNDARY_MULTI_CACHELINE        2
13690
13691 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13692 {
13693         int cacheline_size;
13694         u8 byte;
13695         int goal;
13696
13697         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13698         if (byte == 0)
13699                 cacheline_size = 1024;
13700         else
13701                 cacheline_size = (int) byte * 4;
13702
13703         /* On 5703 and later chips, the boundary bits have no
13704          * effect.
13705          */
13706         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13707             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13708             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13709                 goto out;
13710
13711 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13712         goal = BOUNDARY_MULTI_CACHELINE;
13713 #else
13714 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13715         goal = BOUNDARY_SINGLE_CACHELINE;
13716 #else
13717         goal = 0;
13718 #endif
13719 #endif
13720
13721         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13722             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13723             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13724                 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13725                 goto out;
13726         }
13727
13728         if (!goal)
13729                 goto out;
13730
13731         /* PCI controllers on most RISC systems tend to disconnect
13732          * when a device tries to burst across a cache-line boundary.
13733          * Therefore, letting tg3 do so just wastes PCI bandwidth.
13734          *
13735          * Unfortunately, for PCI-E there are only limited
13736          * write-side controls for this, and thus for reads
13737          * we will still get the disconnects.  We'll also waste
13738          * these PCI cycles for both read and write for chips
13739          * other than 5700 and 5701 which do not implement the
13740          * boundary bits.
13741          */
13742         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13743             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13744                 switch (cacheline_size) {
13745                 case 16:
13746                 case 32:
13747                 case 64:
13748                 case 128:
13749                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13750                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13751                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13752                         } else {
13753                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13754                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13755                         }
13756                         break;
13757
13758                 case 256:
13759                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13760                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13761                         break;
13762
13763                 default:
13764                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13765                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13766                         break;
13767                 }
13768         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13769                 switch (cacheline_size) {
13770                 case 16:
13771                 case 32:
13772                 case 64:
13773                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13774                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13775                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13776                                 break;
13777                         }
13778                         /* fallthrough */
13779                 case 128:
13780                 default:
13781                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13782                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13783                         break;
13784                 }
13785         } else {
13786                 switch (cacheline_size) {
13787                 case 16:
13788                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13789                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13790                                         DMA_RWCTRL_WRITE_BNDRY_16);
13791                                 break;
13792                         }
13793                         /* fallthrough */
13794                 case 32:
13795                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13796                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13797                                         DMA_RWCTRL_WRITE_BNDRY_32);
13798                                 break;
13799                         }
13800                         /* fallthrough */
13801                 case 64:
13802                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13803                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13804                                         DMA_RWCTRL_WRITE_BNDRY_64);
13805                                 break;
13806                         }
13807                         /* fallthrough */
13808                 case 128:
13809                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13810                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13811                                         DMA_RWCTRL_WRITE_BNDRY_128);
13812                                 break;
13813                         }
13814                         /* fallthrough */
13815                 case 256:
13816                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
13817                                 DMA_RWCTRL_WRITE_BNDRY_256);
13818                         break;
13819                 case 512:
13820                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
13821                                 DMA_RWCTRL_WRITE_BNDRY_512);
13822                         break;
13823                 case 1024:
13824                 default:
13825                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13826                                 DMA_RWCTRL_WRITE_BNDRY_1024);
13827                         break;
13828                 }
13829         }
13830
13831 out:
13832         return val;
13833 }
13834
13835 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13836 {
13837         struct tg3_internal_buffer_desc test_desc;
13838         u32 sram_dma_descs;
13839         int i, ret;
13840
13841         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13842
13843         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13844         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13845         tw32(RDMAC_STATUS, 0);
13846         tw32(WDMAC_STATUS, 0);
13847
13848         tw32(BUFMGR_MODE, 0);
13849         tw32(FTQ_RESET, 0);
13850
13851         test_desc.addr_hi = ((u64) buf_dma) >> 32;
13852         test_desc.addr_lo = buf_dma & 0xffffffff;
13853         test_desc.nic_mbuf = 0x00002100;
13854         test_desc.len = size;
13855
13856         /*
13857          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13858          * the *second* time the tg3 driver was getting loaded after an
13859          * initial scan.
13860          *
13861          * Broadcom tells me:
13862          *   ...the DMA engine is connected to the GRC block and a DMA
13863          *   reset may affect the GRC block in some unpredictable way...
13864          *   The behavior of resets to individual blocks has not been tested.
13865          *
13866          * Broadcom noted the GRC reset will also reset all sub-components.
13867          */
13868         if (to_device) {
13869                 test_desc.cqid_sqid = (13 << 8) | 2;
13870
13871                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13872                 udelay(40);
13873         } else {
13874                 test_desc.cqid_sqid = (16 << 8) | 7;
13875
13876                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13877                 udelay(40);
13878         }
13879         test_desc.flags = 0x00000005;
13880
13881         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13882                 u32 val;
13883
13884                 val = *(((u32 *)&test_desc) + i);
13885                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13886                                        sram_dma_descs + (i * sizeof(u32)));
13887                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13888         }
13889         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13890
13891         if (to_device)
13892                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13893         else
13894                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13895
13896         ret = -ENODEV;
13897         for (i = 0; i < 40; i++) {
13898                 u32 val;
13899
13900                 if (to_device)
13901                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13902                 else
13903                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13904                 if ((val & 0xffff) == sram_dma_descs) {
13905                         ret = 0;
13906                         break;
13907                 }
13908
13909                 udelay(100);
13910         }
13911
13912         return ret;
13913 }
13914
13915 #define TEST_BUFFER_SIZE        0x2000
13916
13917 static int __devinit tg3_test_dma(struct tg3 *tp)
13918 {
13919         dma_addr_t buf_dma;
13920         u32 *buf, saved_dma_rwctrl;
13921         int ret = 0;
13922
13923         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13924         if (!buf) {
13925                 ret = -ENOMEM;
13926                 goto out_nofree;
13927         }
13928
13929         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13930                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13931
13932         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13933
13934         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13935             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13936             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13937                 goto out;
13938
13939         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13940                 /* DMA read watermark not used on PCIE */
13941                 tp->dma_rwctrl |= 0x00180000;
13942         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
13943                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13944                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
13945                         tp->dma_rwctrl |= 0x003f0000;
13946                 else
13947                         tp->dma_rwctrl |= 0x003f000f;
13948         } else {
13949                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13950                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13951                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
13952                         u32 read_water = 0x7;
13953
13954                         /* If the 5704 is behind the EPB bridge, we can
13955                          * do the less restrictive ONE_DMA workaround for
13956                          * better performance.
13957                          */
13958                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13959                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13960                                 tp->dma_rwctrl |= 0x8000;
13961                         else if (ccval == 0x6 || ccval == 0x7)
13962                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13963
13964                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13965                                 read_water = 4;
13966                         /* Set bit 23 to enable PCIX hw bug fix */
13967                         tp->dma_rwctrl |=
13968                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13969                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13970                                 (1 << 23);
13971                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13972                         /* 5780 always in PCIX mode */
13973                         tp->dma_rwctrl |= 0x00144000;
13974                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13975                         /* 5714 always in PCIX mode */
13976                         tp->dma_rwctrl |= 0x00148000;
13977                 } else {
13978                         tp->dma_rwctrl |= 0x001b000f;
13979                 }
13980         }
13981
13982         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13983             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13984                 tp->dma_rwctrl &= 0xfffffff0;
13985
13986         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13987             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13988                 /* Remove this if it causes problems for some boards. */
13989                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13990
13991                 /* On 5700/5701 chips, we need to set this bit.
13992                  * Otherwise the chip will issue cacheline transactions
13993                  * to streamable DMA memory with not all the byte
13994                  * enables turned on.  This is an error on several
13995                  * RISC PCI controllers, in particular sparc64.
13996                  *
13997                  * On 5703/5704 chips, this bit has been reassigned
13998                  * a different meaning.  In particular, it is used
13999                  * on those chips to enable a PCI-X workaround.
14000                  */
14001                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
14002         }
14003
14004         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14005
14006 #if 0
14007         /* Unneeded, already done by tg3_get_invariants.  */
14008         tg3_switch_clocks(tp);
14009 #endif
14010
14011         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14012             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14013                 goto out;
14014
14015         /* It is best to perform DMA test with maximum write burst size
14016          * to expose the 5700/5701 write DMA bug.
14017          */
14018         saved_dma_rwctrl = tp->dma_rwctrl;
14019         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14020         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14021
14022         while (1) {
14023                 u32 *p = buf, i;
14024
14025                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14026                         p[i] = i;
14027
14028                 /* Send the buffer to the chip. */
14029                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14030                 if (ret) {
14031                         dev_err(&tp->pdev->dev,
14032                                 "%s: Buffer write failed. err = %d\n",
14033                                 __func__, ret);
14034                         break;
14035                 }
14036
14037 #if 0
14038                 /* validate data reached card RAM correctly. */
14039                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14040                         u32 val;
14041                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
14042                         if (le32_to_cpu(val) != p[i]) {
14043                                 dev_err(&tp->pdev->dev,
14044                                         "%s: Buffer corrupted on device! "
14045                                         "(%d != %d)\n", __func__, val, i);
14046                                 /* ret = -ENODEV here? */
14047                         }
14048                         p[i] = 0;
14049                 }
14050 #endif
14051                 /* Now read it back. */
14052                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14053                 if (ret) {
14054                         dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
14055                                 "err = %d\n", __func__, ret);
14056                         break;
14057                 }
14058
14059                 /* Verify it. */
14060                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14061                         if (p[i] == i)
14062                                 continue;
14063
14064                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14065                             DMA_RWCTRL_WRITE_BNDRY_16) {
14066                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14067                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14068                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14069                                 break;
14070                         } else {
14071                                 dev_err(&tp->pdev->dev,
14072                                         "%s: Buffer corrupted on read back! "
14073                                         "(%d != %d)\n", __func__, p[i], i);
14074                                 ret = -ENODEV;
14075                                 goto out;
14076                         }
14077                 }
14078
14079                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14080                         /* Success. */
14081                         ret = 0;
14082                         break;
14083                 }
14084         }
14085         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14086             DMA_RWCTRL_WRITE_BNDRY_16) {
14087                 static struct pci_device_id dma_wait_state_chipsets[] = {
14088                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14089                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14090                         { },
14091                 };
14092
14093                 /* DMA test passed without adjusting DMA boundary,
14094                  * now look for chipsets that are known to expose the
14095                  * DMA bug without failing the test.
14096                  */
14097                 if (pci_dev_present(dma_wait_state_chipsets)) {
14098                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14099                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14100                 } else {
14101                         /* Safe to use the calculated DMA boundary. */
14102                         tp->dma_rwctrl = saved_dma_rwctrl;
14103                 }
14104
14105                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14106         }
14107
14108 out:
14109         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14110 out_nofree:
14111         return ret;
14112 }
14113
14114 static void __devinit tg3_init_link_config(struct tg3 *tp)
14115 {
14116         tp->link_config.advertising =
14117                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14118                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14119                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14120                  ADVERTISED_Autoneg | ADVERTISED_MII);
14121         tp->link_config.speed = SPEED_INVALID;
14122         tp->link_config.duplex = DUPLEX_INVALID;
14123         tp->link_config.autoneg = AUTONEG_ENABLE;
14124         tp->link_config.active_speed = SPEED_INVALID;
14125         tp->link_config.active_duplex = DUPLEX_INVALID;
14126         tp->link_config.phy_is_low_power = 0;
14127         tp->link_config.orig_speed = SPEED_INVALID;
14128         tp->link_config.orig_duplex = DUPLEX_INVALID;
14129         tp->link_config.orig_autoneg = AUTONEG_INVALID;
14130 }
14131
14132 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14133 {
14134         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14135             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
14136             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
14137                 tp->bufmgr_config.mbuf_read_dma_low_water =
14138                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14139                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14140                         DEFAULT_MB_MACRX_LOW_WATER_57765;
14141                 tp->bufmgr_config.mbuf_high_water =
14142                         DEFAULT_MB_HIGH_WATER_57765;
14143
14144                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14145                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14146                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14147                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14148                 tp->bufmgr_config.mbuf_high_water_jumbo =
14149                         DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14150         } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14151                 tp->bufmgr_config.mbuf_read_dma_low_water =
14152                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14153                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14154                         DEFAULT_MB_MACRX_LOW_WATER_5705;
14155                 tp->bufmgr_config.mbuf_high_water =
14156                         DEFAULT_MB_HIGH_WATER_5705;
14157                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14158                         tp->bufmgr_config.mbuf_mac_rx_low_water =
14159                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
14160                         tp->bufmgr_config.mbuf_high_water =
14161                                 DEFAULT_MB_HIGH_WATER_5906;
14162                 }
14163
14164                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14165                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14166                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14167                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14168                 tp->bufmgr_config.mbuf_high_water_jumbo =
14169                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14170         } else {
14171                 tp->bufmgr_config.mbuf_read_dma_low_water =
14172                         DEFAULT_MB_RDMA_LOW_WATER;
14173                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14174                         DEFAULT_MB_MACRX_LOW_WATER;
14175                 tp->bufmgr_config.mbuf_high_water =
14176                         DEFAULT_MB_HIGH_WATER;
14177
14178                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14179                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14180                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14181                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14182                 tp->bufmgr_config.mbuf_high_water_jumbo =
14183                         DEFAULT_MB_HIGH_WATER_JUMBO;
14184         }
14185
14186         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14187         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14188 }
14189
14190 static char * __devinit tg3_phy_string(struct tg3 *tp)
14191 {
14192         switch (tp->phy_id & TG3_PHY_ID_MASK) {
14193         case TG3_PHY_ID_BCM5400:        return "5400";
14194         case TG3_PHY_ID_BCM5401:        return "5401";
14195         case TG3_PHY_ID_BCM5411:        return "5411";
14196         case TG3_PHY_ID_BCM5701:        return "5701";
14197         case TG3_PHY_ID_BCM5703:        return "5703";
14198         case TG3_PHY_ID_BCM5704:        return "5704";
14199         case TG3_PHY_ID_BCM5705:        return "5705";
14200         case TG3_PHY_ID_BCM5750:        return "5750";
14201         case TG3_PHY_ID_BCM5752:        return "5752";
14202         case TG3_PHY_ID_BCM5714:        return "5714";
14203         case TG3_PHY_ID_BCM5780:        return "5780";
14204         case TG3_PHY_ID_BCM5755:        return "5755";
14205         case TG3_PHY_ID_BCM5787:        return "5787";
14206         case TG3_PHY_ID_BCM5784:        return "5784";
14207         case TG3_PHY_ID_BCM5756:        return "5722/5756";
14208         case TG3_PHY_ID_BCM5906:        return "5906";
14209         case TG3_PHY_ID_BCM5761:        return "5761";
14210         case TG3_PHY_ID_BCM5718C:       return "5718C";
14211         case TG3_PHY_ID_BCM5718S:       return "5718S";
14212         case TG3_PHY_ID_BCM57765:       return "57765";
14213         case TG3_PHY_ID_BCM8002:        return "8002/serdes";
14214         case 0:                 return "serdes";
14215         default:                return "unknown";
14216         }
14217 }
14218
14219 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14220 {
14221         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14222                 strcpy(str, "PCI Express");
14223                 return str;
14224         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14225                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14226
14227                 strcpy(str, "PCIX:");
14228
14229                 if ((clock_ctrl == 7) ||
14230                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14231                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14232                         strcat(str, "133MHz");
14233                 else if (clock_ctrl == 0)
14234                         strcat(str, "33MHz");
14235                 else if (clock_ctrl == 2)
14236                         strcat(str, "50MHz");
14237                 else if (clock_ctrl == 4)
14238                         strcat(str, "66MHz");
14239                 else if (clock_ctrl == 6)
14240                         strcat(str, "100MHz");
14241         } else {
14242                 strcpy(str, "PCI:");
14243                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14244                         strcat(str, "66MHz");
14245                 else
14246                         strcat(str, "33MHz");
14247         }
14248         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14249                 strcat(str, ":32-bit");
14250         else
14251                 strcat(str, ":64-bit");
14252         return str;
14253 }
14254
14255 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14256 {
14257         struct pci_dev *peer;
14258         unsigned int func, devnr = tp->pdev->devfn & ~7;
14259
14260         for (func = 0; func < 8; func++) {
14261                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14262                 if (peer && peer != tp->pdev)
14263                         break;
14264                 pci_dev_put(peer);
14265         }
14266         /* 5704 can be configured in single-port mode, set peer to
14267          * tp->pdev in that case.
14268          */
14269         if (!peer) {
14270                 peer = tp->pdev;
14271                 return peer;
14272         }
14273
14274         /*
14275          * We don't need to keep the refcount elevated; there's no way
14276          * to remove one half of this device without removing the other
14277          */
14278         pci_dev_put(peer);
14279
14280         return peer;
14281 }
14282
14283 static void __devinit tg3_init_coal(struct tg3 *tp)
14284 {
14285         struct ethtool_coalesce *ec = &tp->coal;
14286
14287         memset(ec, 0, sizeof(*ec));
14288         ec->cmd = ETHTOOL_GCOALESCE;
14289         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14290         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14291         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14292         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14293         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14294         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14295         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14296         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14297         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14298
14299         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14300                                  HOSTCC_MODE_CLRTICK_TXBD)) {
14301                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14302                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14303                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14304                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14305         }
14306
14307         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14308                 ec->rx_coalesce_usecs_irq = 0;
14309                 ec->tx_coalesce_usecs_irq = 0;
14310                 ec->stats_block_coalesce_usecs = 0;
14311         }
14312 }
14313
14314 static const struct net_device_ops tg3_netdev_ops = {
14315         .ndo_open               = tg3_open,
14316         .ndo_stop               = tg3_close,
14317         .ndo_start_xmit         = tg3_start_xmit,
14318         .ndo_get_stats          = tg3_get_stats,
14319         .ndo_validate_addr      = eth_validate_addr,
14320         .ndo_set_multicast_list = tg3_set_rx_mode,
14321         .ndo_set_mac_address    = tg3_set_mac_addr,
14322         .ndo_do_ioctl           = tg3_ioctl,
14323         .ndo_tx_timeout         = tg3_tx_timeout,
14324         .ndo_change_mtu         = tg3_change_mtu,
14325 #if TG3_VLAN_TAG_USED
14326         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14327 #endif
14328 #ifdef CONFIG_NET_POLL_CONTROLLER
14329         .ndo_poll_controller    = tg3_poll_controller,
14330 #endif
14331 };
14332
14333 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14334         .ndo_open               = tg3_open,
14335         .ndo_stop               = tg3_close,
14336         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
14337         .ndo_get_stats          = tg3_get_stats,
14338         .ndo_validate_addr      = eth_validate_addr,
14339         .ndo_set_multicast_list = tg3_set_rx_mode,
14340         .ndo_set_mac_address    = tg3_set_mac_addr,
14341         .ndo_do_ioctl           = tg3_ioctl,
14342         .ndo_tx_timeout         = tg3_tx_timeout,
14343         .ndo_change_mtu         = tg3_change_mtu,
14344 #if TG3_VLAN_TAG_USED
14345         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14346 #endif
14347 #ifdef CONFIG_NET_POLL_CONTROLLER
14348         .ndo_poll_controller    = tg3_poll_controller,
14349 #endif
14350 };
14351
14352 static int __devinit tg3_init_one(struct pci_dev *pdev,
14353                                   const struct pci_device_id *ent)
14354 {
14355         struct net_device *dev;
14356         struct tg3 *tp;
14357         int i, err, pm_cap;
14358         u32 sndmbx, rcvmbx, intmbx;
14359         char str[40];
14360         u64 dma_mask, persist_dma_mask;
14361
14362         printk_once(KERN_INFO "%s\n", version);
14363
14364         err = pci_enable_device(pdev);
14365         if (err) {
14366                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
14367                 return err;
14368         }
14369
14370         err = pci_request_regions(pdev, DRV_MODULE_NAME);
14371         if (err) {
14372                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
14373                 goto err_out_disable_pdev;
14374         }
14375
14376         pci_set_master(pdev);
14377
14378         /* Find power-management capability. */
14379         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14380         if (pm_cap == 0) {
14381                 dev_err(&pdev->dev,
14382                         "Cannot find Power Management capability, aborting\n");
14383                 err = -EIO;
14384                 goto err_out_free_res;
14385         }
14386
14387         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14388         if (!dev) {
14389                 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
14390                 err = -ENOMEM;
14391                 goto err_out_free_res;
14392         }
14393
14394         SET_NETDEV_DEV(dev, &pdev->dev);
14395
14396 #if TG3_VLAN_TAG_USED
14397         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14398 #endif
14399
14400         tp = netdev_priv(dev);
14401         tp->pdev = pdev;
14402         tp->dev = dev;
14403         tp->pm_cap = pm_cap;
14404         tp->rx_mode = TG3_DEF_RX_MODE;
14405         tp->tx_mode = TG3_DEF_TX_MODE;
14406
14407         if (tg3_debug > 0)
14408                 tp->msg_enable = tg3_debug;
14409         else
14410                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14411
14412         /* The word/byte swap controls here control register access byte
14413          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
14414          * setting below.
14415          */
14416         tp->misc_host_ctrl =
14417                 MISC_HOST_CTRL_MASK_PCI_INT |
14418                 MISC_HOST_CTRL_WORD_SWAP |
14419                 MISC_HOST_CTRL_INDIR_ACCESS |
14420                 MISC_HOST_CTRL_PCISTATE_RW;
14421
14422         /* The NONFRM (non-frame) byte/word swap controls take effect
14423          * on descriptor entries, anything which isn't packet data.
14424          *
14425          * The StrongARM chips on the board (one for tx, one for rx)
14426          * are running in big-endian mode.
14427          */
14428         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14429                         GRC_MODE_WSWAP_NONFRM_DATA);
14430 #ifdef __BIG_ENDIAN
14431         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14432 #endif
14433         spin_lock_init(&tp->lock);
14434         spin_lock_init(&tp->indirect_lock);
14435         INIT_WORK(&tp->reset_task, tg3_reset_task);
14436
14437         tp->regs = pci_ioremap_bar(pdev, BAR_0);
14438         if (!tp->regs) {
14439                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
14440                 err = -ENOMEM;
14441                 goto err_out_free_dev;
14442         }
14443
14444         tg3_init_link_config(tp);
14445
14446         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14447         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14448
14449         dev->ethtool_ops = &tg3_ethtool_ops;
14450         dev->watchdog_timeo = TG3_TX_TIMEOUT;
14451         dev->irq = pdev->irq;
14452
14453         err = tg3_get_invariants(tp);
14454         if (err) {
14455                 dev_err(&pdev->dev,
14456                         "Problem fetching invariants of chip, aborting\n");
14457                 goto err_out_iounmap;
14458         }
14459
14460         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14461             tp->pci_chip_rev_id != CHIPREV_ID_5717_A0 &&
14462             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
14463                 dev->netdev_ops = &tg3_netdev_ops;
14464         else
14465                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14466
14467
14468         /* The EPB bridge inside 5714, 5715, and 5780 and any
14469          * device behind the EPB cannot support DMA addresses > 40-bit.
14470          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14471          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14472          * do DMA address check in tg3_start_xmit().
14473          */
14474         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14475                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14476         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14477                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14478 #ifdef CONFIG_HIGHMEM
14479                 dma_mask = DMA_BIT_MASK(64);
14480 #endif
14481         } else
14482                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14483
14484         /* Configure DMA attributes. */
14485         if (dma_mask > DMA_BIT_MASK(32)) {
14486                 err = pci_set_dma_mask(pdev, dma_mask);
14487                 if (!err) {
14488                         dev->features |= NETIF_F_HIGHDMA;
14489                         err = pci_set_consistent_dma_mask(pdev,
14490                                                           persist_dma_mask);
14491                         if (err < 0) {
14492                                 dev_err(&pdev->dev, "Unable to obtain 64 bit "
14493                                         "DMA for consistent allocations\n");
14494                                 goto err_out_iounmap;
14495                         }
14496                 }
14497         }
14498         if (err || dma_mask == DMA_BIT_MASK(32)) {
14499                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14500                 if (err) {
14501                         dev_err(&pdev->dev,
14502                                 "No usable DMA configuration, aborting\n");
14503                         goto err_out_iounmap;
14504                 }
14505         }
14506
14507         tg3_init_bufmgr_config(tp);
14508
14509         /* Selectively allow TSO based on operating conditions */
14510         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14511             (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14512                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14513         else {
14514                 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14515                 tp->fw_needed = NULL;
14516         }
14517
14518         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14519                 tp->fw_needed = FIRMWARE_TG3;
14520
14521         /* TSO is on by default on chips that support hardware TSO.
14522          * Firmware TSO on older chips gives lower performance, so it
14523          * is off by default, but can be enabled using ethtool.
14524          */
14525         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14526             (dev->features & NETIF_F_IP_CSUM))
14527                 dev->features |= NETIF_F_TSO;
14528
14529         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14530             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14531                 if (dev->features & NETIF_F_IPV6_CSUM)
14532                         dev->features |= NETIF_F_TSO6;
14533                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14534                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14535                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14536                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14537                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14538                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
14539                         dev->features |= NETIF_F_TSO_ECN;
14540         }
14541
14542         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14543             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14544             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14545                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14546                 tp->rx_pending = 63;
14547         }
14548
14549         err = tg3_get_device_address(tp);
14550         if (err) {
14551                 dev_err(&pdev->dev,
14552                         "Could not obtain valid ethernet address, aborting\n");
14553                 goto err_out_iounmap;
14554         }
14555
14556         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14557                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14558                 if (!tp->aperegs) {
14559                         dev_err(&pdev->dev,
14560                                 "Cannot map APE registers, aborting\n");
14561                         err = -ENOMEM;
14562                         goto err_out_iounmap;
14563                 }
14564
14565                 tg3_ape_lock_init(tp);
14566
14567                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14568                         tg3_read_dash_ver(tp);
14569         }
14570
14571         /*
14572          * Reset chip in case UNDI or EFI driver did not shutdown
14573          * DMA self test will enable WDMAC and we'll see (spurious)
14574          * pending DMA on the PCI bus at that point.
14575          */
14576         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14577             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14578                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14579                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14580         }
14581
14582         err = tg3_test_dma(tp);
14583         if (err) {
14584                 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
14585                 goto err_out_apeunmap;
14586         }
14587
14588         /* flow control autonegotiation is default behavior */
14589         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14590         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14591
14592         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14593         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14594         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14595         for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14596                 struct tg3_napi *tnapi = &tp->napi[i];
14597
14598                 tnapi->tp = tp;
14599                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14600
14601                 tnapi->int_mbox = intmbx;
14602                 if (i < 4)
14603                         intmbx += 0x8;
14604                 else
14605                         intmbx += 0x4;
14606
14607                 tnapi->consmbox = rcvmbx;
14608                 tnapi->prodmbox = sndmbx;
14609
14610                 if (i) {
14611                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14612                         netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14613                 } else {
14614                         tnapi->coal_now = HOSTCC_MODE_NOW;
14615                         netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14616                 }
14617
14618                 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14619                         break;
14620
14621                 /*
14622                  * If we support MSIX, we'll be using RSS.  If we're using
14623                  * RSS, the first vector only handles link interrupts and the
14624                  * remaining vectors handle rx and tx interrupts.  Reuse the
14625                  * mailbox values for the next iteration.  The values we setup
14626                  * above are still useful for the single vectored mode.
14627                  */
14628                 if (!i)
14629                         continue;
14630
14631                 rcvmbx += 0x8;
14632
14633                 if (sndmbx & 0x4)
14634                         sndmbx -= 0x4;
14635                 else
14636                         sndmbx += 0xc;
14637         }
14638
14639         tg3_init_coal(tp);
14640
14641         pci_set_drvdata(pdev, dev);
14642
14643         err = register_netdev(dev);
14644         if (err) {
14645                 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
14646                 goto err_out_apeunmap;
14647         }
14648
14649         netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14650                     tp->board_part_number,
14651                     tp->pci_chip_rev_id,
14652                     tg3_bus_string(tp, str),
14653                     dev->dev_addr);
14654
14655         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14656                 struct phy_device *phydev;
14657                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14658                 netdev_info(dev,
14659                             "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14660                             phydev->drv->name, dev_name(&phydev->dev));
14661         } else
14662                 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
14663                             "(WireSpeed[%d])\n", tg3_phy_string(tp),
14664                             ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14665                              ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14666                               "10/100/1000Base-T")),
14667                             (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14668
14669         netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14670                     (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14671                     (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14672                     (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14673                     (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14674                     (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14675         netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14676                     tp->dma_rwctrl,
14677                     pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
14678                     ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
14679
14680         return 0;
14681
14682 err_out_apeunmap:
14683         if (tp->aperegs) {
14684                 iounmap(tp->aperegs);
14685                 tp->aperegs = NULL;
14686         }
14687
14688 err_out_iounmap:
14689         if (tp->regs) {
14690                 iounmap(tp->regs);
14691                 tp->regs = NULL;
14692         }
14693
14694 err_out_free_dev:
14695         free_netdev(dev);
14696
14697 err_out_free_res:
14698         pci_release_regions(pdev);
14699
14700 err_out_disable_pdev:
14701         pci_disable_device(pdev);
14702         pci_set_drvdata(pdev, NULL);
14703         return err;
14704 }
14705
14706 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14707 {
14708         struct net_device *dev = pci_get_drvdata(pdev);
14709
14710         if (dev) {
14711                 struct tg3 *tp = netdev_priv(dev);
14712
14713                 if (tp->fw)
14714                         release_firmware(tp->fw);
14715
14716                 flush_scheduled_work();
14717
14718                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14719                         tg3_phy_fini(tp);
14720                         tg3_mdio_fini(tp);
14721                 }
14722
14723                 unregister_netdev(dev);
14724                 if (tp->aperegs) {
14725                         iounmap(tp->aperegs);
14726                         tp->aperegs = NULL;
14727                 }
14728                 if (tp->regs) {
14729                         iounmap(tp->regs);
14730                         tp->regs = NULL;
14731                 }
14732                 free_netdev(dev);
14733                 pci_release_regions(pdev);
14734                 pci_disable_device(pdev);
14735                 pci_set_drvdata(pdev, NULL);
14736         }
14737 }
14738
14739 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14740 {
14741         struct net_device *dev = pci_get_drvdata(pdev);
14742         struct tg3 *tp = netdev_priv(dev);
14743         pci_power_t target_state;
14744         int err;
14745
14746         /* PCI register 4 needs to be saved whether netif_running() or not.
14747          * MSI address and data need to be saved if using MSI and
14748          * netif_running().
14749          */
14750         pci_save_state(pdev);
14751
14752         if (!netif_running(dev))
14753                 return 0;
14754
14755         flush_scheduled_work();
14756         tg3_phy_stop(tp);
14757         tg3_netif_stop(tp);
14758
14759         del_timer_sync(&tp->timer);
14760
14761         tg3_full_lock(tp, 1);
14762         tg3_disable_ints(tp);
14763         tg3_full_unlock(tp);
14764
14765         netif_device_detach(dev);
14766
14767         tg3_full_lock(tp, 0);
14768         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14769         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14770         tg3_full_unlock(tp);
14771
14772         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14773
14774         err = tg3_set_power_state(tp, target_state);
14775         if (err) {
14776                 int err2;
14777
14778                 tg3_full_lock(tp, 0);
14779
14780                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14781                 err2 = tg3_restart_hw(tp, 1);
14782                 if (err2)
14783                         goto out;
14784
14785                 tp->timer.expires = jiffies + tp->timer_offset;
14786                 add_timer(&tp->timer);
14787
14788                 netif_device_attach(dev);
14789                 tg3_netif_start(tp);
14790
14791 out:
14792                 tg3_full_unlock(tp);
14793
14794                 if (!err2)
14795                         tg3_phy_start(tp);
14796         }
14797
14798         return err;
14799 }
14800
14801 static int tg3_resume(struct pci_dev *pdev)
14802 {
14803         struct net_device *dev = pci_get_drvdata(pdev);
14804         struct tg3 *tp = netdev_priv(dev);
14805         int err;
14806
14807         pci_restore_state(tp->pdev);
14808
14809         if (!netif_running(dev))
14810                 return 0;
14811
14812         err = tg3_set_power_state(tp, PCI_D0);
14813         if (err)
14814                 return err;
14815
14816         netif_device_attach(dev);
14817
14818         tg3_full_lock(tp, 0);
14819
14820         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14821         err = tg3_restart_hw(tp, 1);
14822         if (err)
14823                 goto out;
14824
14825         tp->timer.expires = jiffies + tp->timer_offset;
14826         add_timer(&tp->timer);
14827
14828         tg3_netif_start(tp);
14829
14830 out:
14831         tg3_full_unlock(tp);
14832
14833         if (!err)
14834                 tg3_phy_start(tp);
14835
14836         return err;
14837 }
14838
14839 static struct pci_driver tg3_driver = {
14840         .name           = DRV_MODULE_NAME,
14841         .id_table       = tg3_pci_tbl,
14842         .probe          = tg3_init_one,
14843         .remove         = __devexit_p(tg3_remove_one),
14844         .suspend        = tg3_suspend,
14845         .resume         = tg3_resume
14846 };
14847
14848 static int __init tg3_init(void)
14849 {
14850         return pci_register_driver(&tg3_driver);
14851 }
14852
14853 static void __exit tg3_cleanup(void)
14854 {
14855         pci_unregister_driver(&tg3_driver);
14856 }
14857
14858 module_init(tg3_init);
14859 module_exit(tg3_cleanup);