2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2010 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/phy.h>
36 #include <linux/brcmphy.h>
37 #include <linux/if_vlan.h>
39 #include <linux/tcp.h>
40 #include <linux/workqueue.h>
41 #include <linux/prefetch.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/firmware.h>
45 #include <net/checksum.h>
48 #include <asm/system.h>
50 #include <asm/byteorder.h>
51 #include <asm/uaccess.h>
54 #include <asm/idprom.h>
61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62 #define TG3_VLAN_TAG_USED 1
64 #define TG3_VLAN_TAG_USED 0
69 #define DRV_MODULE_NAME "tg3"
70 #define DRV_MODULE_VERSION "3.109"
71 #define DRV_MODULE_RELDATE "April 2, 2010"
73 #define TG3_DEF_MAC_MODE 0
74 #define TG3_DEF_RX_MODE 0
75 #define TG3_DEF_TX_MODE 0
76 #define TG3_DEF_MSG_ENABLE \
86 /* length of time before we decide the hardware is borked,
87 * and dev->tx_timeout() should be called to fix the problem
89 #define TG3_TX_TIMEOUT (5 * HZ)
91 /* hardware minimum and maximum for a single frame's data payload */
92 #define TG3_MIN_MTU 60
93 #define TG3_MAX_MTU(tp) \
94 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
96 /* These numbers seem to be hard coded in the NIC firmware somehow.
97 * You can't change the ring sizes, but you can change where you place
98 * them in the NIC onboard memory.
100 #define TG3_RX_RING_SIZE 512
101 #define TG3_DEF_RX_RING_PENDING 200
102 #define TG3_RX_JUMBO_RING_SIZE 256
103 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
104 #define TG3_RSS_INDIR_TBL_SIZE 128
106 /* Do not place this n-ring entries value into the tp struct itself,
107 * we really want to expose these constants to GCC so that modulo et
108 * al. operations are done with shifts and masks instead of with
109 * hw multiply/modulo instructions. Another solution would be to
110 * replace things like '% foo' with '& (foo - 1)'.
112 #define TG3_RX_RCB_RING_SIZE(tp) \
113 (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
114 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
116 #define TG3_TX_RING_SIZE 512
117 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
119 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
122 TG3_RX_JUMBO_RING_SIZE)
123 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
124 TG3_RX_RCB_RING_SIZE(tp))
125 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
127 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
129 #define TG3_DMA_BYTE_ENAB 64
131 #define TG3_RX_STD_DMA_SZ 1536
132 #define TG3_RX_JMB_DMA_SZ 9046
134 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
136 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
137 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
139 #define TG3_RX_STD_BUFF_RING_SIZE \
140 (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
142 #define TG3_RX_JMB_BUFF_RING_SIZE \
143 (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
145 #define TG3_RSS_MIN_NUM_MSIX_VECS 2
147 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
148 * that are at least dword aligned when used in PCIX mode. The driver
149 * works around this bug by double copying the packet. This workaround
150 * is built into the normal double copy length check for efficiency.
152 * However, the double copy is only necessary on those architectures
153 * where unaligned memory accesses are inefficient. For those architectures
154 * where unaligned memory accesses incur little penalty, we can reintegrate
155 * the 5701 in the normal rx path. Doing so saves a device structure
156 * dereference by hardcoding the double copy threshold in place.
158 #define TG3_RX_COPY_THRESHOLD 256
159 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
160 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
162 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
165 /* minimum number of free TX descriptors required to wake up TX process */
166 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
168 #define TG3_RAW_IP_ALIGN 2
170 /* number of ETHTOOL_GSTATS u64's */
171 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
173 #define TG3_NUM_TEST 6
175 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
177 #define FIRMWARE_TG3 "tigon/tg3.bin"
178 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
179 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
181 static char version[] __devinitdata =
182 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
184 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
185 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
186 MODULE_LICENSE("GPL");
187 MODULE_VERSION(DRV_MODULE_VERSION);
188 MODULE_FIRMWARE(FIRMWARE_TG3);
189 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
190 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
192 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
193 module_param(tg3_debug, int, 0);
194 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
196 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
260 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
261 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
264 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
267 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
268 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
272 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
273 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
274 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
275 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
276 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
277 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
278 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
282 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
284 static const struct {
285 const char string[ETH_GSTRING_LEN];
286 } ethtool_stats_keys[TG3_NUM_STATS] = {
289 { "rx_ucast_packets" },
290 { "rx_mcast_packets" },
291 { "rx_bcast_packets" },
293 { "rx_align_errors" },
294 { "rx_xon_pause_rcvd" },
295 { "rx_xoff_pause_rcvd" },
296 { "rx_mac_ctrl_rcvd" },
297 { "rx_xoff_entered" },
298 { "rx_frame_too_long_errors" },
300 { "rx_undersize_packets" },
301 { "rx_in_length_errors" },
302 { "rx_out_length_errors" },
303 { "rx_64_or_less_octet_packets" },
304 { "rx_65_to_127_octet_packets" },
305 { "rx_128_to_255_octet_packets" },
306 { "rx_256_to_511_octet_packets" },
307 { "rx_512_to_1023_octet_packets" },
308 { "rx_1024_to_1522_octet_packets" },
309 { "rx_1523_to_2047_octet_packets" },
310 { "rx_2048_to_4095_octet_packets" },
311 { "rx_4096_to_8191_octet_packets" },
312 { "rx_8192_to_9022_octet_packets" },
319 { "tx_flow_control" },
321 { "tx_single_collisions" },
322 { "tx_mult_collisions" },
324 { "tx_excessive_collisions" },
325 { "tx_late_collisions" },
326 { "tx_collide_2times" },
327 { "tx_collide_3times" },
328 { "tx_collide_4times" },
329 { "tx_collide_5times" },
330 { "tx_collide_6times" },
331 { "tx_collide_7times" },
332 { "tx_collide_8times" },
333 { "tx_collide_9times" },
334 { "tx_collide_10times" },
335 { "tx_collide_11times" },
336 { "tx_collide_12times" },
337 { "tx_collide_13times" },
338 { "tx_collide_14times" },
339 { "tx_collide_15times" },
340 { "tx_ucast_packets" },
341 { "tx_mcast_packets" },
342 { "tx_bcast_packets" },
343 { "tx_carrier_sense_errors" },
347 { "dma_writeq_full" },
348 { "dma_write_prioq_full" },
352 { "rx_threshold_hit" },
354 { "dma_readq_full" },
355 { "dma_read_prioq_full" },
356 { "tx_comp_queue_full" },
358 { "ring_set_send_prod_index" },
359 { "ring_status_update" },
361 { "nic_avoided_irqs" },
362 { "nic_tx_threshold_hit" }
365 static const struct {
366 const char string[ETH_GSTRING_LEN];
367 } ethtool_test_keys[TG3_NUM_TEST] = {
368 { "nvram test (online) " },
369 { "link test (online) " },
370 { "register test (offline)" },
371 { "memory test (offline)" },
372 { "loopback test (offline)" },
373 { "interrupt test (offline)" },
376 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
378 writel(val, tp->regs + off);
381 static u32 tg3_read32(struct tg3 *tp, u32 off)
383 return (readl(tp->regs + off));
386 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
388 writel(val, tp->aperegs + off);
391 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
393 return (readl(tp->aperegs + off));
396 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
400 spin_lock_irqsave(&tp->indirect_lock, flags);
401 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
402 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
403 spin_unlock_irqrestore(&tp->indirect_lock, flags);
406 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
408 writel(val, tp->regs + off);
409 readl(tp->regs + off);
412 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
417 spin_lock_irqsave(&tp->indirect_lock, flags);
418 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
419 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
420 spin_unlock_irqrestore(&tp->indirect_lock, flags);
424 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
428 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
429 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
430 TG3_64BIT_REG_LOW, val);
433 if (off == TG3_RX_STD_PROD_IDX_REG) {
434 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
435 TG3_64BIT_REG_LOW, val);
439 spin_lock_irqsave(&tp->indirect_lock, flags);
440 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
441 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
442 spin_unlock_irqrestore(&tp->indirect_lock, flags);
444 /* In indirect mode when disabling interrupts, we also need
445 * to clear the interrupt bit in the GRC local ctrl register.
447 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
449 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
450 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
454 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
459 spin_lock_irqsave(&tp->indirect_lock, flags);
460 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
461 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
462 spin_unlock_irqrestore(&tp->indirect_lock, flags);
466 /* usec_wait specifies the wait time in usec when writing to certain registers
467 * where it is unsafe to read back the register without some delay.
468 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
469 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
471 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
473 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
474 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
475 /* Non-posted methods */
476 tp->write32(tp, off, val);
479 tg3_write32(tp, off, val);
484 /* Wait again after the read for the posted method to guarantee that
485 * the wait time is met.
491 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
493 tp->write32_mbox(tp, off, val);
494 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
495 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
496 tp->read32_mbox(tp, off);
499 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
501 void __iomem *mbox = tp->regs + off;
503 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
505 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
509 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
511 return (readl(tp->regs + off + GRCMBOX_BASE));
514 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
516 writel(val, tp->regs + off + GRCMBOX_BASE);
519 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
520 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
521 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
522 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
523 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
525 #define tw32(reg, val) tp->write32(tp, reg, val)
526 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
527 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
528 #define tr32(reg) tp->read32(tp, reg)
530 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
534 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
535 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
538 spin_lock_irqsave(&tp->indirect_lock, flags);
539 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
540 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
541 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
543 /* Always leave this as zero. */
544 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
546 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
547 tw32_f(TG3PCI_MEM_WIN_DATA, val);
549 /* Always leave this as zero. */
550 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
552 spin_unlock_irqrestore(&tp->indirect_lock, flags);
555 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
559 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
560 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
565 spin_lock_irqsave(&tp->indirect_lock, flags);
566 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
567 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
568 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
570 /* Always leave this as zero. */
571 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
573 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
574 *val = tr32(TG3PCI_MEM_WIN_DATA);
576 /* Always leave this as zero. */
577 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
579 spin_unlock_irqrestore(&tp->indirect_lock, flags);
582 static void tg3_ape_lock_init(struct tg3 *tp)
586 /* Make sure the driver hasn't any stale locks. */
587 for (i = 0; i < 8; i++)
588 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
589 APE_LOCK_GRANT_DRIVER);
592 static int tg3_ape_lock(struct tg3 *tp, int locknum)
598 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
602 case TG3_APE_LOCK_GRC:
603 case TG3_APE_LOCK_MEM:
611 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
613 /* Wait for up to 1 millisecond to acquire lock. */
614 for (i = 0; i < 100; i++) {
615 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
616 if (status == APE_LOCK_GRANT_DRIVER)
621 if (status != APE_LOCK_GRANT_DRIVER) {
622 /* Revoke the lock request. */
623 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
624 APE_LOCK_GRANT_DRIVER);
632 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
636 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
640 case TG3_APE_LOCK_GRC:
641 case TG3_APE_LOCK_MEM:
648 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
651 static void tg3_disable_ints(struct tg3 *tp)
655 tw32(TG3PCI_MISC_HOST_CTRL,
656 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
657 for (i = 0; i < tp->irq_max; i++)
658 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
661 static void tg3_enable_ints(struct tg3 *tp)
668 tw32(TG3PCI_MISC_HOST_CTRL,
669 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
671 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
672 for (i = 0; i < tp->irq_cnt; i++) {
673 struct tg3_napi *tnapi = &tp->napi[i];
675 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
676 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
677 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
679 tp->coal_now |= tnapi->coal_now;
682 /* Force an initial interrupt */
683 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
684 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
685 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
687 tw32(HOSTCC_MODE, tp->coal_now);
689 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
692 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
694 struct tg3 *tp = tnapi->tp;
695 struct tg3_hw_status *sblk = tnapi->hw_status;
696 unsigned int work_exists = 0;
698 /* check for phy events */
699 if (!(tp->tg3_flags &
700 (TG3_FLAG_USE_LINKCHG_REG |
701 TG3_FLAG_POLL_SERDES))) {
702 if (sblk->status & SD_STATUS_LINK_CHG)
705 /* check for RX/TX work to do */
706 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
707 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
714 * similar to tg3_enable_ints, but it accurately determines whether there
715 * is new work pending and can return without flushing the PIO write
716 * which reenables interrupts
718 static void tg3_int_reenable(struct tg3_napi *tnapi)
720 struct tg3 *tp = tnapi->tp;
722 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
725 /* When doing tagged status, this work check is unnecessary.
726 * The last_tag we write above tells the chip which piece of
727 * work we've completed.
729 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
731 tw32(HOSTCC_MODE, tp->coalesce_mode |
732 HOSTCC_MODE_ENABLE | tnapi->coal_now);
735 static void tg3_napi_disable(struct tg3 *tp)
739 for (i = tp->irq_cnt - 1; i >= 0; i--)
740 napi_disable(&tp->napi[i].napi);
743 static void tg3_napi_enable(struct tg3 *tp)
747 for (i = 0; i < tp->irq_cnt; i++)
748 napi_enable(&tp->napi[i].napi);
751 static inline void tg3_netif_stop(struct tg3 *tp)
753 tp->dev->trans_start = jiffies; /* prevent tx timeout */
754 tg3_napi_disable(tp);
755 netif_tx_disable(tp->dev);
758 static inline void tg3_netif_start(struct tg3 *tp)
760 /* NOTE: unconditional netif_tx_wake_all_queues is only
761 * appropriate so long as all callers are assured to
762 * have free tx slots (such as after tg3_init_hw)
764 netif_tx_wake_all_queues(tp->dev);
767 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
771 static void tg3_switch_clocks(struct tg3 *tp)
776 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
777 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
780 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
782 orig_clock_ctrl = clock_ctrl;
783 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
784 CLOCK_CTRL_CLKRUN_OENABLE |
786 tp->pci_clock_ctrl = clock_ctrl;
788 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
789 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
790 tw32_wait_f(TG3PCI_CLOCK_CTRL,
791 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
793 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
794 tw32_wait_f(TG3PCI_CLOCK_CTRL,
796 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
798 tw32_wait_f(TG3PCI_CLOCK_CTRL,
799 clock_ctrl | (CLOCK_CTRL_ALTCLK),
802 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
805 #define PHY_BUSY_LOOPS 5000
807 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
813 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
815 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
821 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
822 MI_COM_PHY_ADDR_MASK);
823 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
824 MI_COM_REG_ADDR_MASK);
825 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
827 tw32_f(MAC_MI_COM, frame_val);
829 loops = PHY_BUSY_LOOPS;
832 frame_val = tr32(MAC_MI_COM);
834 if ((frame_val & MI_COM_BUSY) == 0) {
836 frame_val = tr32(MAC_MI_COM);
844 *val = frame_val & MI_COM_DATA_MASK;
848 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
849 tw32_f(MAC_MI_MODE, tp->mi_mode);
856 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
862 if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
863 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
866 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
868 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
872 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
873 MI_COM_PHY_ADDR_MASK);
874 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
875 MI_COM_REG_ADDR_MASK);
876 frame_val |= (val & MI_COM_DATA_MASK);
877 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
879 tw32_f(MAC_MI_COM, frame_val);
881 loops = PHY_BUSY_LOOPS;
884 frame_val = tr32(MAC_MI_COM);
885 if ((frame_val & MI_COM_BUSY) == 0) {
887 frame_val = tr32(MAC_MI_COM);
897 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
898 tw32_f(MAC_MI_MODE, tp->mi_mode);
905 static int tg3_bmcr_reset(struct tg3 *tp)
910 /* OK, reset it, and poll the BMCR_RESET bit until it
911 * clears or we time out.
913 phy_control = BMCR_RESET;
914 err = tg3_writephy(tp, MII_BMCR, phy_control);
920 err = tg3_readphy(tp, MII_BMCR, &phy_control);
924 if ((phy_control & BMCR_RESET) == 0) {
936 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
938 struct tg3 *tp = bp->priv;
941 spin_lock_bh(&tp->lock);
943 if (tg3_readphy(tp, reg, &val))
946 spin_unlock_bh(&tp->lock);
951 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
953 struct tg3 *tp = bp->priv;
956 spin_lock_bh(&tp->lock);
958 if (tg3_writephy(tp, reg, val))
961 spin_unlock_bh(&tp->lock);
966 static int tg3_mdio_reset(struct mii_bus *bp)
971 static void tg3_mdio_config_5785(struct tg3 *tp)
974 struct phy_device *phydev;
976 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
977 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
978 case PHY_ID_BCM50610:
979 case PHY_ID_BCM50610M:
980 val = MAC_PHYCFG2_50610_LED_MODES;
982 case PHY_ID_BCMAC131:
983 val = MAC_PHYCFG2_AC131_LED_MODES;
985 case PHY_ID_RTL8211C:
986 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
988 case PHY_ID_RTL8201E:
989 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
995 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
996 tw32(MAC_PHYCFG2, val);
998 val = tr32(MAC_PHYCFG1);
999 val &= ~(MAC_PHYCFG1_RGMII_INT |
1000 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1001 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1002 tw32(MAC_PHYCFG1, val);
1007 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
1008 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1009 MAC_PHYCFG2_FMODE_MASK_MASK |
1010 MAC_PHYCFG2_GMODE_MASK_MASK |
1011 MAC_PHYCFG2_ACT_MASK_MASK |
1012 MAC_PHYCFG2_QUAL_MASK_MASK |
1013 MAC_PHYCFG2_INBAND_ENABLE;
1015 tw32(MAC_PHYCFG2, val);
1017 val = tr32(MAC_PHYCFG1);
1018 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1019 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1020 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1021 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1022 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1023 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1024 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1026 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1027 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1028 tw32(MAC_PHYCFG1, val);
1030 val = tr32(MAC_EXT_RGMII_MODE);
1031 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1032 MAC_RGMII_MODE_RX_QUALITY |
1033 MAC_RGMII_MODE_RX_ACTIVITY |
1034 MAC_RGMII_MODE_RX_ENG_DET |
1035 MAC_RGMII_MODE_TX_ENABLE |
1036 MAC_RGMII_MODE_TX_LOWPWR |
1037 MAC_RGMII_MODE_TX_RESET);
1038 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1039 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1040 val |= MAC_RGMII_MODE_RX_INT_B |
1041 MAC_RGMII_MODE_RX_QUALITY |
1042 MAC_RGMII_MODE_RX_ACTIVITY |
1043 MAC_RGMII_MODE_RX_ENG_DET;
1044 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1045 val |= MAC_RGMII_MODE_TX_ENABLE |
1046 MAC_RGMII_MODE_TX_LOWPWR |
1047 MAC_RGMII_MODE_TX_RESET;
1049 tw32(MAC_EXT_RGMII_MODE, val);
1052 static void tg3_mdio_start(struct tg3 *tp)
1054 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1055 tw32_f(MAC_MI_MODE, tp->mi_mode);
1058 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1059 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1060 tg3_mdio_config_5785(tp);
1063 static int tg3_mdio_init(struct tg3 *tp)
1067 struct phy_device *phydev;
1069 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1070 u32 funcnum, is_serdes;
1072 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1078 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1079 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1081 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1082 TG3_CPMU_PHY_STRAP_IS_SERDES;
1086 tp->phy_addr = TG3_PHY_MII_ADDR;
1090 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1091 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1094 tp->mdio_bus = mdiobus_alloc();
1095 if (tp->mdio_bus == NULL)
1098 tp->mdio_bus->name = "tg3 mdio bus";
1099 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1100 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1101 tp->mdio_bus->priv = tp;
1102 tp->mdio_bus->parent = &tp->pdev->dev;
1103 tp->mdio_bus->read = &tg3_mdio_read;
1104 tp->mdio_bus->write = &tg3_mdio_write;
1105 tp->mdio_bus->reset = &tg3_mdio_reset;
1106 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1107 tp->mdio_bus->irq = &tp->mdio_irq[0];
1109 for (i = 0; i < PHY_MAX_ADDR; i++)
1110 tp->mdio_bus->irq[i] = PHY_POLL;
1112 /* The bus registration will look for all the PHYs on the mdio bus.
1113 * Unfortunately, it does not ensure the PHY is powered up before
1114 * accessing the PHY ID registers. A chip reset is the
1115 * quickest way to bring the device back to an operational state..
1117 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN))
1120 i = mdiobus_register(tp->mdio_bus);
1122 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1123 mdiobus_free(tp->mdio_bus);
1127 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1129 if (!phydev || !phydev->drv) {
1130 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1131 mdiobus_unregister(tp->mdio_bus);
1132 mdiobus_free(tp->mdio_bus);
1136 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1137 case PHY_ID_BCM57780:
1138 phydev->interface = PHY_INTERFACE_MODE_GMII;
1139 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1141 case PHY_ID_BCM50610:
1142 case PHY_ID_BCM50610M:
1143 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1144 PHY_BRCM_RX_REFCLK_UNUSED |
1145 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1146 PHY_BRCM_AUTO_PWRDWN_ENABLE;
1147 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1148 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1149 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1150 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1151 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1152 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1154 case PHY_ID_RTL8211C:
1155 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1157 case PHY_ID_RTL8201E:
1158 case PHY_ID_BCMAC131:
1159 phydev->interface = PHY_INTERFACE_MODE_MII;
1160 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1161 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1165 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1167 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1168 tg3_mdio_config_5785(tp);
1173 static void tg3_mdio_fini(struct tg3 *tp)
1175 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1176 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1177 mdiobus_unregister(tp->mdio_bus);
1178 mdiobus_free(tp->mdio_bus);
1182 /* tp->lock is held. */
1183 static inline void tg3_generate_fw_event(struct tg3 *tp)
1187 val = tr32(GRC_RX_CPU_EVENT);
1188 val |= GRC_RX_CPU_DRIVER_EVENT;
1189 tw32_f(GRC_RX_CPU_EVENT, val);
1191 tp->last_event_jiffies = jiffies;
1194 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1196 /* tp->lock is held. */
1197 static void tg3_wait_for_event_ack(struct tg3 *tp)
1200 unsigned int delay_cnt;
1203 /* If enough time has passed, no wait is necessary. */
1204 time_remain = (long)(tp->last_event_jiffies + 1 +
1205 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1207 if (time_remain < 0)
1210 /* Check if we can shorten the wait time. */
1211 delay_cnt = jiffies_to_usecs(time_remain);
1212 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1213 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1214 delay_cnt = (delay_cnt >> 3) + 1;
1216 for (i = 0; i < delay_cnt; i++) {
1217 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1223 /* tp->lock is held. */
1224 static void tg3_ump_link_report(struct tg3 *tp)
1229 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1230 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1233 tg3_wait_for_event_ack(tp);
1235 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1237 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1240 if (!tg3_readphy(tp, MII_BMCR, ®))
1242 if (!tg3_readphy(tp, MII_BMSR, ®))
1243 val |= (reg & 0xffff);
1244 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1247 if (!tg3_readphy(tp, MII_ADVERTISE, ®))
1249 if (!tg3_readphy(tp, MII_LPA, ®))
1250 val |= (reg & 0xffff);
1251 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1254 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1255 if (!tg3_readphy(tp, MII_CTRL1000, ®))
1257 if (!tg3_readphy(tp, MII_STAT1000, ®))
1258 val |= (reg & 0xffff);
1260 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1262 if (!tg3_readphy(tp, MII_PHYADDR, ®))
1266 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1268 tg3_generate_fw_event(tp);
1271 static void tg3_link_report(struct tg3 *tp)
1273 if (!netif_carrier_ok(tp->dev)) {
1274 netif_info(tp, link, tp->dev, "Link is down\n");
1275 tg3_ump_link_report(tp);
1276 } else if (netif_msg_link(tp)) {
1277 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1278 (tp->link_config.active_speed == SPEED_1000 ?
1280 (tp->link_config.active_speed == SPEED_100 ?
1282 (tp->link_config.active_duplex == DUPLEX_FULL ?
1285 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1286 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1288 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1290 tg3_ump_link_report(tp);
1294 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1298 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1299 miireg = ADVERTISE_PAUSE_CAP;
1300 else if (flow_ctrl & FLOW_CTRL_TX)
1301 miireg = ADVERTISE_PAUSE_ASYM;
1302 else if (flow_ctrl & FLOW_CTRL_RX)
1303 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1310 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1314 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1315 miireg = ADVERTISE_1000XPAUSE;
1316 else if (flow_ctrl & FLOW_CTRL_TX)
1317 miireg = ADVERTISE_1000XPSE_ASYM;
1318 else if (flow_ctrl & FLOW_CTRL_RX)
1319 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1326 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1330 if (lcladv & ADVERTISE_1000XPAUSE) {
1331 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1332 if (rmtadv & LPA_1000XPAUSE)
1333 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1334 else if (rmtadv & LPA_1000XPAUSE_ASYM)
1337 if (rmtadv & LPA_1000XPAUSE)
1338 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1340 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1341 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1348 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1352 u32 old_rx_mode = tp->rx_mode;
1353 u32 old_tx_mode = tp->tx_mode;
1355 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1356 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1358 autoneg = tp->link_config.autoneg;
1360 if (autoneg == AUTONEG_ENABLE &&
1361 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1362 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1363 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1365 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1367 flowctrl = tp->link_config.flowctrl;
1369 tp->link_config.active_flowctrl = flowctrl;
1371 if (flowctrl & FLOW_CTRL_RX)
1372 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1374 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1376 if (old_rx_mode != tp->rx_mode)
1377 tw32_f(MAC_RX_MODE, tp->rx_mode);
1379 if (flowctrl & FLOW_CTRL_TX)
1380 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1382 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1384 if (old_tx_mode != tp->tx_mode)
1385 tw32_f(MAC_TX_MODE, tp->tx_mode);
1388 static void tg3_adjust_link(struct net_device *dev)
1390 u8 oldflowctrl, linkmesg = 0;
1391 u32 mac_mode, lcl_adv, rmt_adv;
1392 struct tg3 *tp = netdev_priv(dev);
1393 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1395 spin_lock_bh(&tp->lock);
1397 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1398 MAC_MODE_HALF_DUPLEX);
1400 oldflowctrl = tp->link_config.active_flowctrl;
1406 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1407 mac_mode |= MAC_MODE_PORT_MODE_MII;
1408 else if (phydev->speed == SPEED_1000 ||
1409 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1410 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1412 mac_mode |= MAC_MODE_PORT_MODE_MII;
1414 if (phydev->duplex == DUPLEX_HALF)
1415 mac_mode |= MAC_MODE_HALF_DUPLEX;
1417 lcl_adv = tg3_advert_flowctrl_1000T(
1418 tp->link_config.flowctrl);
1421 rmt_adv = LPA_PAUSE_CAP;
1422 if (phydev->asym_pause)
1423 rmt_adv |= LPA_PAUSE_ASYM;
1426 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1428 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1430 if (mac_mode != tp->mac_mode) {
1431 tp->mac_mode = mac_mode;
1432 tw32_f(MAC_MODE, tp->mac_mode);
1436 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1437 if (phydev->speed == SPEED_10)
1439 MAC_MI_STAT_10MBPS_MODE |
1440 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1442 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1445 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1446 tw32(MAC_TX_LENGTHS,
1447 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1448 (6 << TX_LENGTHS_IPG_SHIFT) |
1449 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1451 tw32(MAC_TX_LENGTHS,
1452 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1453 (6 << TX_LENGTHS_IPG_SHIFT) |
1454 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1456 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1457 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1458 phydev->speed != tp->link_config.active_speed ||
1459 phydev->duplex != tp->link_config.active_duplex ||
1460 oldflowctrl != tp->link_config.active_flowctrl)
1463 tp->link_config.active_speed = phydev->speed;
1464 tp->link_config.active_duplex = phydev->duplex;
1466 spin_unlock_bh(&tp->lock);
1469 tg3_link_report(tp);
1472 static int tg3_phy_init(struct tg3 *tp)
1474 struct phy_device *phydev;
1476 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1479 /* Bring the PHY back to a known state. */
1482 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1484 /* Attach the MAC to the PHY. */
1485 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1486 phydev->dev_flags, phydev->interface);
1487 if (IS_ERR(phydev)) {
1488 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1489 return PTR_ERR(phydev);
1492 /* Mask with MAC supported features. */
1493 switch (phydev->interface) {
1494 case PHY_INTERFACE_MODE_GMII:
1495 case PHY_INTERFACE_MODE_RGMII:
1496 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1497 phydev->supported &= (PHY_GBIT_FEATURES |
1499 SUPPORTED_Asym_Pause);
1503 case PHY_INTERFACE_MODE_MII:
1504 phydev->supported &= (PHY_BASIC_FEATURES |
1506 SUPPORTED_Asym_Pause);
1509 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1513 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1515 phydev->advertising = phydev->supported;
1520 static void tg3_phy_start(struct tg3 *tp)
1522 struct phy_device *phydev;
1524 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1527 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1529 if (tp->link_config.phy_is_low_power) {
1530 tp->link_config.phy_is_low_power = 0;
1531 phydev->speed = tp->link_config.orig_speed;
1532 phydev->duplex = tp->link_config.orig_duplex;
1533 phydev->autoneg = tp->link_config.orig_autoneg;
1534 phydev->advertising = tp->link_config.orig_advertising;
1539 phy_start_aneg(phydev);
1542 static void tg3_phy_stop(struct tg3 *tp)
1544 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1547 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1550 static void tg3_phy_fini(struct tg3 *tp)
1552 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1553 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1554 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1558 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1560 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1561 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1564 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1568 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1571 tg3_writephy(tp, MII_TG3_FET_TEST,
1572 phytest | MII_TG3_FET_SHADOW_EN);
1573 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1575 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1577 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1578 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1580 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1584 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1588 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1589 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1590 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1593 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1594 tg3_phy_fet_toggle_apd(tp, enable);
1598 reg = MII_TG3_MISC_SHDW_WREN |
1599 MII_TG3_MISC_SHDW_SCR5_SEL |
1600 MII_TG3_MISC_SHDW_SCR5_LPED |
1601 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1602 MII_TG3_MISC_SHDW_SCR5_SDTL |
1603 MII_TG3_MISC_SHDW_SCR5_C125OE;
1604 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1605 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1607 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1610 reg = MII_TG3_MISC_SHDW_WREN |
1611 MII_TG3_MISC_SHDW_APD_SEL |
1612 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1614 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1616 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1619 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1623 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1624 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1627 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1630 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1631 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1633 tg3_writephy(tp, MII_TG3_FET_TEST,
1634 ephy | MII_TG3_FET_SHADOW_EN);
1635 if (!tg3_readphy(tp, reg, &phy)) {
1637 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1639 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1640 tg3_writephy(tp, reg, phy);
1642 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1645 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1646 MII_TG3_AUXCTL_SHDWSEL_MISC;
1647 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1648 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1650 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1652 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1653 phy |= MII_TG3_AUXCTL_MISC_WREN;
1654 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1659 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1663 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1666 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1667 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1668 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1669 (val | (1 << 15) | (1 << 4)));
1672 static void tg3_phy_apply_otp(struct tg3 *tp)
1681 /* Enable SM_DSP clock and tx 6dB coding. */
1682 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1683 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1684 MII_TG3_AUXCTL_ACTL_TX_6DB;
1685 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1687 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1688 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1689 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1691 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1692 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1693 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1695 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1696 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1697 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1699 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1700 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1702 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1703 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1705 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1706 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1707 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1709 /* Turn off SM_DSP clock. */
1710 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1711 MII_TG3_AUXCTL_ACTL_TX_6DB;
1712 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1715 static int tg3_wait_macro_done(struct tg3 *tp)
1722 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1723 if ((tmp32 & 0x1000) == 0)
1733 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1735 static const u32 test_pat[4][6] = {
1736 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1737 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1738 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1739 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1743 for (chan = 0; chan < 4; chan++) {
1746 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1747 (chan * 0x2000) | 0x0200);
1748 tg3_writephy(tp, 0x16, 0x0002);
1750 for (i = 0; i < 6; i++)
1751 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1754 tg3_writephy(tp, 0x16, 0x0202);
1755 if (tg3_wait_macro_done(tp)) {
1760 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1761 (chan * 0x2000) | 0x0200);
1762 tg3_writephy(tp, 0x16, 0x0082);
1763 if (tg3_wait_macro_done(tp)) {
1768 tg3_writephy(tp, 0x16, 0x0802);
1769 if (tg3_wait_macro_done(tp)) {
1774 for (i = 0; i < 6; i += 2) {
1777 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1778 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1779 tg3_wait_macro_done(tp)) {
1785 if (low != test_pat[chan][i] ||
1786 high != test_pat[chan][i+1]) {
1787 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1788 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1789 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1799 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1803 for (chan = 0; chan < 4; chan++) {
1806 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1807 (chan * 0x2000) | 0x0200);
1808 tg3_writephy(tp, 0x16, 0x0002);
1809 for (i = 0; i < 6; i++)
1810 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1811 tg3_writephy(tp, 0x16, 0x0202);
1812 if (tg3_wait_macro_done(tp))
1819 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1821 u32 reg32, phy9_orig;
1822 int retries, do_phy_reset, err;
1828 err = tg3_bmcr_reset(tp);
1834 /* Disable transmitter and interrupt. */
1835 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
1839 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1841 /* Set full-duplex, 1000 mbps. */
1842 tg3_writephy(tp, MII_BMCR,
1843 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1845 /* Set to master mode. */
1846 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1849 tg3_writephy(tp, MII_TG3_CTRL,
1850 (MII_TG3_CTRL_AS_MASTER |
1851 MII_TG3_CTRL_ENABLE_AS_MASTER));
1853 /* Enable SM_DSP_CLOCK and 6dB. */
1854 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1856 /* Block the PHY control access. */
1857 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1858 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1860 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1863 } while (--retries);
1865 err = tg3_phy_reset_chanpat(tp);
1869 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1870 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1872 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1873 tg3_writephy(tp, 0x16, 0x0000);
1875 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1876 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1877 /* Set Extended packet length bit for jumbo frames */
1878 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1880 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1883 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1885 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) {
1887 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1894 /* This will reset the tigon3 PHY if there is no valid
1895 * link unless the FORCE argument is non-zero.
1897 static int tg3_phy_reset(struct tg3 *tp)
1903 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1906 val = tr32(GRC_MISC_CFG);
1907 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1910 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1911 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1915 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1916 netif_carrier_off(tp->dev);
1917 tg3_link_report(tp);
1920 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1921 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1922 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1923 err = tg3_phy_reset_5703_4_5(tp);
1930 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1931 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1932 cpmuctrl = tr32(TG3_CPMU_CTRL);
1933 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1935 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1938 err = tg3_bmcr_reset(tp);
1942 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1945 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1946 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1948 tw32(TG3_CPMU_CTRL, cpmuctrl);
1951 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1952 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1955 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1956 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1957 CPMU_LSPD_1000MB_MACCLK_12_5) {
1958 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1960 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1964 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1965 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES))
1968 tg3_phy_apply_otp(tp);
1970 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1971 tg3_phy_toggle_apd(tp, true);
1973 tg3_phy_toggle_apd(tp, false);
1976 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1977 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1978 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1979 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1980 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1981 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1982 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1984 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1985 tg3_writephy(tp, 0x1c, 0x8d68);
1986 tg3_writephy(tp, 0x1c, 0x8d68);
1988 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1989 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1990 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1991 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1992 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1993 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1994 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1995 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1996 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1997 } else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1998 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1999 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2000 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
2001 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2002 tg3_writephy(tp, MII_TG3_TEST1,
2003 MII_TG3_TEST1_TRIM_EN | 0x4);
2005 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2006 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2008 /* Set Extended packet length bit (bit 14) on all chips that */
2009 /* support jumbo frames */
2010 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2011 /* Cannot do read-modify-write on 5401 */
2012 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2013 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2016 /* Set bit 14 with read-modify-write to preserve other bits */
2017 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2018 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
2019 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
2022 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2023 * jumbo frames transmission.
2025 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2028 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
2029 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2030 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2033 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2034 /* adjust output voltage */
2035 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2038 tg3_phy_toggle_automdix(tp, 1);
2039 tg3_phy_set_wirespeed(tp);
2043 static void tg3_frob_aux_power(struct tg3 *tp)
2045 struct tg3 *tp_peer = tp;
2047 /* The GPIOs do something completely different on 57765. */
2048 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2049 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2052 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2053 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2054 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2055 struct net_device *dev_peer;
2057 dev_peer = pci_get_drvdata(tp->pdev_peer);
2058 /* remove_one() may have been run on the peer. */
2062 tp_peer = netdev_priv(dev_peer);
2065 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2066 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2067 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2068 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2069 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2070 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2071 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2072 (GRC_LCLCTRL_GPIO_OE0 |
2073 GRC_LCLCTRL_GPIO_OE1 |
2074 GRC_LCLCTRL_GPIO_OE2 |
2075 GRC_LCLCTRL_GPIO_OUTPUT0 |
2076 GRC_LCLCTRL_GPIO_OUTPUT1),
2078 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2079 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2080 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2081 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2082 GRC_LCLCTRL_GPIO_OE1 |
2083 GRC_LCLCTRL_GPIO_OE2 |
2084 GRC_LCLCTRL_GPIO_OUTPUT0 |
2085 GRC_LCLCTRL_GPIO_OUTPUT1 |
2087 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2089 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2090 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2092 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2093 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2096 u32 grc_local_ctrl = 0;
2098 if (tp_peer != tp &&
2099 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2102 /* Workaround to prevent overdrawing Amps. */
2103 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2105 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2106 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2107 grc_local_ctrl, 100);
2110 /* On 5753 and variants, GPIO2 cannot be used. */
2111 no_gpio2 = tp->nic_sram_data_cfg &
2112 NIC_SRAM_DATA_CFG_NO_GPIO2;
2114 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2115 GRC_LCLCTRL_GPIO_OE1 |
2116 GRC_LCLCTRL_GPIO_OE2 |
2117 GRC_LCLCTRL_GPIO_OUTPUT1 |
2118 GRC_LCLCTRL_GPIO_OUTPUT2;
2120 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2121 GRC_LCLCTRL_GPIO_OUTPUT2);
2123 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2124 grc_local_ctrl, 100);
2126 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2128 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2129 grc_local_ctrl, 100);
2132 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2133 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2134 grc_local_ctrl, 100);
2138 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2139 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2140 if (tp_peer != tp &&
2141 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2144 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2145 (GRC_LCLCTRL_GPIO_OE1 |
2146 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2148 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2149 GRC_LCLCTRL_GPIO_OE1, 100);
2151 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2152 (GRC_LCLCTRL_GPIO_OE1 |
2153 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2158 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2160 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2162 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2163 if (speed != SPEED_10)
2165 } else if (speed == SPEED_10)
2171 static int tg3_setup_phy(struct tg3 *, int);
2173 #define RESET_KIND_SHUTDOWN 0
2174 #define RESET_KIND_INIT 1
2175 #define RESET_KIND_SUSPEND 2
2177 static void tg3_write_sig_post_reset(struct tg3 *, int);
2178 static int tg3_halt_cpu(struct tg3 *, u32);
2180 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2184 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2185 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2186 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2187 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2190 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2191 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2192 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2197 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2199 val = tr32(GRC_MISC_CFG);
2200 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2203 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2205 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2208 tg3_writephy(tp, MII_ADVERTISE, 0);
2209 tg3_writephy(tp, MII_BMCR,
2210 BMCR_ANENABLE | BMCR_ANRESTART);
2212 tg3_writephy(tp, MII_TG3_FET_TEST,
2213 phytest | MII_TG3_FET_SHADOW_EN);
2214 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2215 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2217 MII_TG3_FET_SHDW_AUXMODE4,
2220 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2223 } else if (do_low_power) {
2224 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2225 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2227 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2228 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2229 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2230 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2231 MII_TG3_AUXCTL_PCTL_VREG_11V);
2234 /* The PHY should not be powered down on some chips because
2237 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2238 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2239 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2240 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2243 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2244 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2245 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2246 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2247 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2248 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2251 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2254 /* tp->lock is held. */
2255 static int tg3_nvram_lock(struct tg3 *tp)
2257 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2260 if (tp->nvram_lock_cnt == 0) {
2261 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2262 for (i = 0; i < 8000; i++) {
2263 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2268 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2272 tp->nvram_lock_cnt++;
2277 /* tp->lock is held. */
2278 static void tg3_nvram_unlock(struct tg3 *tp)
2280 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2281 if (tp->nvram_lock_cnt > 0)
2282 tp->nvram_lock_cnt--;
2283 if (tp->nvram_lock_cnt == 0)
2284 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2288 /* tp->lock is held. */
2289 static void tg3_enable_nvram_access(struct tg3 *tp)
2291 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2292 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2293 u32 nvaccess = tr32(NVRAM_ACCESS);
2295 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2299 /* tp->lock is held. */
2300 static void tg3_disable_nvram_access(struct tg3 *tp)
2302 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2303 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2304 u32 nvaccess = tr32(NVRAM_ACCESS);
2306 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2310 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2311 u32 offset, u32 *val)
2316 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2319 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2320 EEPROM_ADDR_DEVID_MASK |
2322 tw32(GRC_EEPROM_ADDR,
2324 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2325 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2326 EEPROM_ADDR_ADDR_MASK) |
2327 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2329 for (i = 0; i < 1000; i++) {
2330 tmp = tr32(GRC_EEPROM_ADDR);
2332 if (tmp & EEPROM_ADDR_COMPLETE)
2336 if (!(tmp & EEPROM_ADDR_COMPLETE))
2339 tmp = tr32(GRC_EEPROM_DATA);
2342 * The data will always be opposite the native endian
2343 * format. Perform a blind byteswap to compensate.
2350 #define NVRAM_CMD_TIMEOUT 10000
2352 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2356 tw32(NVRAM_CMD, nvram_cmd);
2357 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2359 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2365 if (i == NVRAM_CMD_TIMEOUT)
2371 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2373 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2374 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2375 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2376 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2377 (tp->nvram_jedecnum == JEDEC_ATMEL))
2379 addr = ((addr / tp->nvram_pagesize) <<
2380 ATMEL_AT45DB0X1B_PAGE_POS) +
2381 (addr % tp->nvram_pagesize);
2386 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2388 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2389 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2390 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2391 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2392 (tp->nvram_jedecnum == JEDEC_ATMEL))
2394 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2395 tp->nvram_pagesize) +
2396 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2401 /* NOTE: Data read in from NVRAM is byteswapped according to
2402 * the byteswapping settings for all other register accesses.
2403 * tg3 devices are BE devices, so on a BE machine, the data
2404 * returned will be exactly as it is seen in NVRAM. On a LE
2405 * machine, the 32-bit value will be byteswapped.
2407 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2411 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2412 return tg3_nvram_read_using_eeprom(tp, offset, val);
2414 offset = tg3_nvram_phys_addr(tp, offset);
2416 if (offset > NVRAM_ADDR_MSK)
2419 ret = tg3_nvram_lock(tp);
2423 tg3_enable_nvram_access(tp);
2425 tw32(NVRAM_ADDR, offset);
2426 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2427 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2430 *val = tr32(NVRAM_RDDATA);
2432 tg3_disable_nvram_access(tp);
2434 tg3_nvram_unlock(tp);
2439 /* Ensures NVRAM data is in bytestream format. */
2440 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2443 int res = tg3_nvram_read(tp, offset, &v);
2445 *val = cpu_to_be32(v);
2449 /* tp->lock is held. */
2450 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2452 u32 addr_high, addr_low;
2455 addr_high = ((tp->dev->dev_addr[0] << 8) |
2456 tp->dev->dev_addr[1]);
2457 addr_low = ((tp->dev->dev_addr[2] << 24) |
2458 (tp->dev->dev_addr[3] << 16) |
2459 (tp->dev->dev_addr[4] << 8) |
2460 (tp->dev->dev_addr[5] << 0));
2461 for (i = 0; i < 4; i++) {
2462 if (i == 1 && skip_mac_1)
2464 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2465 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2468 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2469 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2470 for (i = 0; i < 12; i++) {
2471 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2472 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2476 addr_high = (tp->dev->dev_addr[0] +
2477 tp->dev->dev_addr[1] +
2478 tp->dev->dev_addr[2] +
2479 tp->dev->dev_addr[3] +
2480 tp->dev->dev_addr[4] +
2481 tp->dev->dev_addr[5]) &
2482 TX_BACKOFF_SEED_MASK;
2483 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2486 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2489 bool device_should_wake, do_low_power;
2491 /* Make sure register accesses (indirect or otherwise)
2492 * will function correctly.
2494 pci_write_config_dword(tp->pdev,
2495 TG3PCI_MISC_HOST_CTRL,
2496 tp->misc_host_ctrl);
2500 pci_enable_wake(tp->pdev, state, false);
2501 pci_set_power_state(tp->pdev, PCI_D0);
2503 /* Switch out of Vaux if it is a NIC */
2504 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2505 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2515 netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
2520 /* Restore the CLKREQ setting. */
2521 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2524 pci_read_config_word(tp->pdev,
2525 tp->pcie_cap + PCI_EXP_LNKCTL,
2527 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2528 pci_write_config_word(tp->pdev,
2529 tp->pcie_cap + PCI_EXP_LNKCTL,
2533 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2534 tw32(TG3PCI_MISC_HOST_CTRL,
2535 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2537 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2538 device_may_wakeup(&tp->pdev->dev) &&
2539 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2541 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2542 do_low_power = false;
2543 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2544 !tp->link_config.phy_is_low_power) {
2545 struct phy_device *phydev;
2546 u32 phyid, advertising;
2548 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2550 tp->link_config.phy_is_low_power = 1;
2552 tp->link_config.orig_speed = phydev->speed;
2553 tp->link_config.orig_duplex = phydev->duplex;
2554 tp->link_config.orig_autoneg = phydev->autoneg;
2555 tp->link_config.orig_advertising = phydev->advertising;
2557 advertising = ADVERTISED_TP |
2559 ADVERTISED_Autoneg |
2560 ADVERTISED_10baseT_Half;
2562 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2563 device_should_wake) {
2564 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2566 ADVERTISED_100baseT_Half |
2567 ADVERTISED_100baseT_Full |
2568 ADVERTISED_10baseT_Full;
2570 advertising |= ADVERTISED_10baseT_Full;
2573 phydev->advertising = advertising;
2575 phy_start_aneg(phydev);
2577 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2578 if (phyid != PHY_ID_BCMAC131) {
2579 phyid &= PHY_BCM_OUI_MASK;
2580 if (phyid == PHY_BCM_OUI_1 ||
2581 phyid == PHY_BCM_OUI_2 ||
2582 phyid == PHY_BCM_OUI_3)
2583 do_low_power = true;
2587 do_low_power = true;
2589 if (tp->link_config.phy_is_low_power == 0) {
2590 tp->link_config.phy_is_low_power = 1;
2591 tp->link_config.orig_speed = tp->link_config.speed;
2592 tp->link_config.orig_duplex = tp->link_config.duplex;
2593 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2596 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2597 tp->link_config.speed = SPEED_10;
2598 tp->link_config.duplex = DUPLEX_HALF;
2599 tp->link_config.autoneg = AUTONEG_ENABLE;
2600 tg3_setup_phy(tp, 0);
2604 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2607 val = tr32(GRC_VCPU_EXT_CTRL);
2608 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2609 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2613 for (i = 0; i < 200; i++) {
2614 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2615 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2620 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2621 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2622 WOL_DRV_STATE_SHUTDOWN |
2626 if (device_should_wake) {
2629 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2631 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2635 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2636 mac_mode = MAC_MODE_PORT_MODE_GMII;
2638 mac_mode = MAC_MODE_PORT_MODE_MII;
2640 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2641 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2643 u32 speed = (tp->tg3_flags &
2644 TG3_FLAG_WOL_SPEED_100MB) ?
2645 SPEED_100 : SPEED_10;
2646 if (tg3_5700_link_polarity(tp, speed))
2647 mac_mode |= MAC_MODE_LINK_POLARITY;
2649 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2652 mac_mode = MAC_MODE_PORT_MODE_TBI;
2655 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2656 tw32(MAC_LED_CTRL, tp->led_ctrl);
2658 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2659 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2660 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2661 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2662 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2663 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2665 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2666 mac_mode |= tp->mac_mode &
2667 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2668 if (mac_mode & MAC_MODE_APE_TX_EN)
2669 mac_mode |= MAC_MODE_TDE_ENABLE;
2672 tw32_f(MAC_MODE, mac_mode);
2675 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2679 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2680 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2681 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2684 base_val = tp->pci_clock_ctrl;
2685 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2686 CLOCK_CTRL_TXCLK_DISABLE);
2688 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2689 CLOCK_CTRL_PWRDOWN_PLL133, 40);
2690 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2691 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2692 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2694 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2695 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2696 u32 newbits1, newbits2;
2698 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2699 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2700 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2701 CLOCK_CTRL_TXCLK_DISABLE |
2703 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2704 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2705 newbits1 = CLOCK_CTRL_625_CORE;
2706 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2708 newbits1 = CLOCK_CTRL_ALTCLK;
2709 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2712 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2715 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2718 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2721 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2722 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2723 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2724 CLOCK_CTRL_TXCLK_DISABLE |
2725 CLOCK_CTRL_44MHZ_CORE);
2727 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2730 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2731 tp->pci_clock_ctrl | newbits3, 40);
2735 if (!(device_should_wake) &&
2736 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2737 tg3_power_down_phy(tp, do_low_power);
2739 tg3_frob_aux_power(tp);
2741 /* Workaround for unstable PLL clock */
2742 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2743 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2744 u32 val = tr32(0x7d00);
2746 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2748 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2751 err = tg3_nvram_lock(tp);
2752 tg3_halt_cpu(tp, RX_CPU_BASE);
2754 tg3_nvram_unlock(tp);
2758 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2760 if (device_should_wake)
2761 pci_enable_wake(tp->pdev, state, true);
2763 /* Finally, set the new power state. */
2764 pci_set_power_state(tp->pdev, state);
2769 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2771 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2772 case MII_TG3_AUX_STAT_10HALF:
2774 *duplex = DUPLEX_HALF;
2777 case MII_TG3_AUX_STAT_10FULL:
2779 *duplex = DUPLEX_FULL;
2782 case MII_TG3_AUX_STAT_100HALF:
2784 *duplex = DUPLEX_HALF;
2787 case MII_TG3_AUX_STAT_100FULL:
2789 *duplex = DUPLEX_FULL;
2792 case MII_TG3_AUX_STAT_1000HALF:
2793 *speed = SPEED_1000;
2794 *duplex = DUPLEX_HALF;
2797 case MII_TG3_AUX_STAT_1000FULL:
2798 *speed = SPEED_1000;
2799 *duplex = DUPLEX_FULL;
2803 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2804 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2806 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2810 *speed = SPEED_INVALID;
2811 *duplex = DUPLEX_INVALID;
2816 static void tg3_phy_copper_begin(struct tg3 *tp)
2821 if (tp->link_config.phy_is_low_power) {
2822 /* Entering low power mode. Disable gigabit and
2823 * 100baseT advertisements.
2825 tg3_writephy(tp, MII_TG3_CTRL, 0);
2827 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2828 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2829 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2830 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2832 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2833 } else if (tp->link_config.speed == SPEED_INVALID) {
2834 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2835 tp->link_config.advertising &=
2836 ~(ADVERTISED_1000baseT_Half |
2837 ADVERTISED_1000baseT_Full);
2839 new_adv = ADVERTISE_CSMA;
2840 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2841 new_adv |= ADVERTISE_10HALF;
2842 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2843 new_adv |= ADVERTISE_10FULL;
2844 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2845 new_adv |= ADVERTISE_100HALF;
2846 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2847 new_adv |= ADVERTISE_100FULL;
2849 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2851 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2853 if (tp->link_config.advertising &
2854 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2856 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2857 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2858 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2859 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2860 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2861 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2862 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2863 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2864 MII_TG3_CTRL_ENABLE_AS_MASTER);
2865 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2867 tg3_writephy(tp, MII_TG3_CTRL, 0);
2870 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2871 new_adv |= ADVERTISE_CSMA;
2873 /* Asking for a specific link mode. */
2874 if (tp->link_config.speed == SPEED_1000) {
2875 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2877 if (tp->link_config.duplex == DUPLEX_FULL)
2878 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2880 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2881 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2882 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2883 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2884 MII_TG3_CTRL_ENABLE_AS_MASTER);
2886 if (tp->link_config.speed == SPEED_100) {
2887 if (tp->link_config.duplex == DUPLEX_FULL)
2888 new_adv |= ADVERTISE_100FULL;
2890 new_adv |= ADVERTISE_100HALF;
2892 if (tp->link_config.duplex == DUPLEX_FULL)
2893 new_adv |= ADVERTISE_10FULL;
2895 new_adv |= ADVERTISE_10HALF;
2897 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2902 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2905 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2906 tp->link_config.speed != SPEED_INVALID) {
2907 u32 bmcr, orig_bmcr;
2909 tp->link_config.active_speed = tp->link_config.speed;
2910 tp->link_config.active_duplex = tp->link_config.duplex;
2913 switch (tp->link_config.speed) {
2919 bmcr |= BMCR_SPEED100;
2923 bmcr |= TG3_BMCR_SPEED1000;
2927 if (tp->link_config.duplex == DUPLEX_FULL)
2928 bmcr |= BMCR_FULLDPLX;
2930 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2931 (bmcr != orig_bmcr)) {
2932 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2933 for (i = 0; i < 1500; i++) {
2937 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2938 tg3_readphy(tp, MII_BMSR, &tmp))
2940 if (!(tmp & BMSR_LSTATUS)) {
2945 tg3_writephy(tp, MII_BMCR, bmcr);
2949 tg3_writephy(tp, MII_BMCR,
2950 BMCR_ANENABLE | BMCR_ANRESTART);
2954 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2958 /* Turn off tap power management. */
2959 /* Set Extended packet length bit */
2960 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2962 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2963 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2965 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2966 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2968 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2969 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2971 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2972 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2974 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2975 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2982 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2984 u32 adv_reg, all_mask = 0;
2986 if (mask & ADVERTISED_10baseT_Half)
2987 all_mask |= ADVERTISE_10HALF;
2988 if (mask & ADVERTISED_10baseT_Full)
2989 all_mask |= ADVERTISE_10FULL;
2990 if (mask & ADVERTISED_100baseT_Half)
2991 all_mask |= ADVERTISE_100HALF;
2992 if (mask & ADVERTISED_100baseT_Full)
2993 all_mask |= ADVERTISE_100FULL;
2995 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2998 if ((adv_reg & all_mask) != all_mask)
3000 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
3004 if (mask & ADVERTISED_1000baseT_Half)
3005 all_mask |= ADVERTISE_1000HALF;
3006 if (mask & ADVERTISED_1000baseT_Full)
3007 all_mask |= ADVERTISE_1000FULL;
3009 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3012 if ((tg3_ctrl & all_mask) != all_mask)
3018 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3022 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3025 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3026 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3028 if (tp->link_config.active_duplex == DUPLEX_FULL) {
3029 if (curadv != reqadv)
3032 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3033 tg3_readphy(tp, MII_LPA, rmtadv);
3035 /* Reprogram the advertisement register, even if it
3036 * does not affect the current link. If the link
3037 * gets renegotiated in the future, we can save an
3038 * additional renegotiation cycle by advertising
3039 * it correctly in the first place.
3041 if (curadv != reqadv) {
3042 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3043 ADVERTISE_PAUSE_ASYM);
3044 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3051 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3053 int current_link_up;
3055 u32 lcl_adv, rmt_adv;
3063 (MAC_STATUS_SYNC_CHANGED |
3064 MAC_STATUS_CFG_CHANGED |
3065 MAC_STATUS_MI_COMPLETION |
3066 MAC_STATUS_LNKSTATE_CHANGED));
3069 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3071 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3075 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3077 /* Some third-party PHYs need to be reset on link going
3080 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3081 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3082 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3083 netif_carrier_ok(tp->dev)) {
3084 tg3_readphy(tp, MII_BMSR, &bmsr);
3085 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3086 !(bmsr & BMSR_LSTATUS))
3092 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3093 tg3_readphy(tp, MII_BMSR, &bmsr);
3094 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3095 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3098 if (!(bmsr & BMSR_LSTATUS)) {
3099 err = tg3_init_5401phy_dsp(tp);
3103 tg3_readphy(tp, MII_BMSR, &bmsr);
3104 for (i = 0; i < 1000; i++) {
3106 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3107 (bmsr & BMSR_LSTATUS)) {
3113 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3114 TG3_PHY_REV_BCM5401_B0 &&
3115 !(bmsr & BMSR_LSTATUS) &&
3116 tp->link_config.active_speed == SPEED_1000) {
3117 err = tg3_phy_reset(tp);
3119 err = tg3_init_5401phy_dsp(tp);
3124 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3125 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3126 /* 5701 {A0,B0} CRC bug workaround */
3127 tg3_writephy(tp, 0x15, 0x0a75);
3128 tg3_writephy(tp, 0x1c, 0x8c68);
3129 tg3_writephy(tp, 0x1c, 0x8d68);
3130 tg3_writephy(tp, 0x1c, 0x8c68);
3133 /* Clear pending interrupts... */
3134 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3135 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3137 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3138 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3139 else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3140 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3142 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3143 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3144 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3145 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3146 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3148 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3151 current_link_up = 0;
3152 current_speed = SPEED_INVALID;
3153 current_duplex = DUPLEX_INVALID;
3155 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3158 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3159 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3160 if (!(val & (1 << 10))) {
3162 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3168 for (i = 0; i < 100; i++) {
3169 tg3_readphy(tp, MII_BMSR, &bmsr);
3170 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3171 (bmsr & BMSR_LSTATUS))
3176 if (bmsr & BMSR_LSTATUS) {
3179 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3180 for (i = 0; i < 2000; i++) {
3182 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3187 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3192 for (i = 0; i < 200; i++) {
3193 tg3_readphy(tp, MII_BMCR, &bmcr);
3194 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3196 if (bmcr && bmcr != 0x7fff)
3204 tp->link_config.active_speed = current_speed;
3205 tp->link_config.active_duplex = current_duplex;
3207 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3208 if ((bmcr & BMCR_ANENABLE) &&
3209 tg3_copper_is_advertising_all(tp,
3210 tp->link_config.advertising)) {
3211 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3213 current_link_up = 1;
3216 if (!(bmcr & BMCR_ANENABLE) &&
3217 tp->link_config.speed == current_speed &&
3218 tp->link_config.duplex == current_duplex &&
3219 tp->link_config.flowctrl ==
3220 tp->link_config.active_flowctrl) {
3221 current_link_up = 1;
3225 if (current_link_up == 1 &&
3226 tp->link_config.active_duplex == DUPLEX_FULL)
3227 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3231 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3234 tg3_phy_copper_begin(tp);
3236 tg3_readphy(tp, MII_BMSR, &tmp);
3237 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3238 (tmp & BMSR_LSTATUS))
3239 current_link_up = 1;
3242 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3243 if (current_link_up == 1) {
3244 if (tp->link_config.active_speed == SPEED_100 ||
3245 tp->link_config.active_speed == SPEED_10)
3246 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3248 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3249 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3250 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3252 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3254 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3255 if (tp->link_config.active_duplex == DUPLEX_HALF)
3256 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3258 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3259 if (current_link_up == 1 &&
3260 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3261 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3263 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3266 /* ??? Without this setting Netgear GA302T PHY does not
3267 * ??? send/receive packets...
3269 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3270 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3271 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3272 tw32_f(MAC_MI_MODE, tp->mi_mode);
3276 tw32_f(MAC_MODE, tp->mac_mode);
3279 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3280 /* Polled via timer. */
3281 tw32_f(MAC_EVENT, 0);
3283 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3287 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3288 current_link_up == 1 &&
3289 tp->link_config.active_speed == SPEED_1000 &&
3290 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3291 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3294 (MAC_STATUS_SYNC_CHANGED |
3295 MAC_STATUS_CFG_CHANGED));
3298 NIC_SRAM_FIRMWARE_MBOX,
3299 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3302 /* Prevent send BD corruption. */
3303 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3304 u16 oldlnkctl, newlnkctl;
3306 pci_read_config_word(tp->pdev,
3307 tp->pcie_cap + PCI_EXP_LNKCTL,
3309 if (tp->link_config.active_speed == SPEED_100 ||
3310 tp->link_config.active_speed == SPEED_10)
3311 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3313 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3314 if (newlnkctl != oldlnkctl)
3315 pci_write_config_word(tp->pdev,
3316 tp->pcie_cap + PCI_EXP_LNKCTL,
3320 if (current_link_up != netif_carrier_ok(tp->dev)) {
3321 if (current_link_up)
3322 netif_carrier_on(tp->dev);
3324 netif_carrier_off(tp->dev);
3325 tg3_link_report(tp);
3331 struct tg3_fiber_aneginfo {
3333 #define ANEG_STATE_UNKNOWN 0
3334 #define ANEG_STATE_AN_ENABLE 1
3335 #define ANEG_STATE_RESTART_INIT 2
3336 #define ANEG_STATE_RESTART 3
3337 #define ANEG_STATE_DISABLE_LINK_OK 4
3338 #define ANEG_STATE_ABILITY_DETECT_INIT 5
3339 #define ANEG_STATE_ABILITY_DETECT 6
3340 #define ANEG_STATE_ACK_DETECT_INIT 7
3341 #define ANEG_STATE_ACK_DETECT 8
3342 #define ANEG_STATE_COMPLETE_ACK_INIT 9
3343 #define ANEG_STATE_COMPLETE_ACK 10
3344 #define ANEG_STATE_IDLE_DETECT_INIT 11
3345 #define ANEG_STATE_IDLE_DETECT 12
3346 #define ANEG_STATE_LINK_OK 13
3347 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3348 #define ANEG_STATE_NEXT_PAGE_WAIT 15
3351 #define MR_AN_ENABLE 0x00000001
3352 #define MR_RESTART_AN 0x00000002
3353 #define MR_AN_COMPLETE 0x00000004
3354 #define MR_PAGE_RX 0x00000008
3355 #define MR_NP_LOADED 0x00000010
3356 #define MR_TOGGLE_TX 0x00000020
3357 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
3358 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
3359 #define MR_LP_ADV_SYM_PAUSE 0x00000100
3360 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
3361 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3362 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3363 #define MR_LP_ADV_NEXT_PAGE 0x00001000
3364 #define MR_TOGGLE_RX 0x00002000
3365 #define MR_NP_RX 0x00004000
3367 #define MR_LINK_OK 0x80000000
3369 unsigned long link_time, cur_time;
3371 u32 ability_match_cfg;
3372 int ability_match_count;
3374 char ability_match, idle_match, ack_match;
3376 u32 txconfig, rxconfig;
3377 #define ANEG_CFG_NP 0x00000080
3378 #define ANEG_CFG_ACK 0x00000040
3379 #define ANEG_CFG_RF2 0x00000020
3380 #define ANEG_CFG_RF1 0x00000010
3381 #define ANEG_CFG_PS2 0x00000001
3382 #define ANEG_CFG_PS1 0x00008000
3383 #define ANEG_CFG_HD 0x00004000
3384 #define ANEG_CFG_FD 0x00002000
3385 #define ANEG_CFG_INVAL 0x00001f06
3390 #define ANEG_TIMER_ENAB 2
3391 #define ANEG_FAILED -1
3393 #define ANEG_STATE_SETTLE_TIME 10000
3395 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3396 struct tg3_fiber_aneginfo *ap)
3399 unsigned long delta;
3403 if (ap->state == ANEG_STATE_UNKNOWN) {
3407 ap->ability_match_cfg = 0;
3408 ap->ability_match_count = 0;
3409 ap->ability_match = 0;
3415 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3416 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3418 if (rx_cfg_reg != ap->ability_match_cfg) {
3419 ap->ability_match_cfg = rx_cfg_reg;
3420 ap->ability_match = 0;
3421 ap->ability_match_count = 0;
3423 if (++ap->ability_match_count > 1) {
3424 ap->ability_match = 1;
3425 ap->ability_match_cfg = rx_cfg_reg;
3428 if (rx_cfg_reg & ANEG_CFG_ACK)
3436 ap->ability_match_cfg = 0;
3437 ap->ability_match_count = 0;
3438 ap->ability_match = 0;
3444 ap->rxconfig = rx_cfg_reg;
3447 switch (ap->state) {
3448 case ANEG_STATE_UNKNOWN:
3449 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3450 ap->state = ANEG_STATE_AN_ENABLE;
3453 case ANEG_STATE_AN_ENABLE:
3454 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3455 if (ap->flags & MR_AN_ENABLE) {
3458 ap->ability_match_cfg = 0;
3459 ap->ability_match_count = 0;
3460 ap->ability_match = 0;
3464 ap->state = ANEG_STATE_RESTART_INIT;
3466 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3470 case ANEG_STATE_RESTART_INIT:
3471 ap->link_time = ap->cur_time;
3472 ap->flags &= ~(MR_NP_LOADED);
3474 tw32(MAC_TX_AUTO_NEG, 0);
3475 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3476 tw32_f(MAC_MODE, tp->mac_mode);
3479 ret = ANEG_TIMER_ENAB;
3480 ap->state = ANEG_STATE_RESTART;
3483 case ANEG_STATE_RESTART:
3484 delta = ap->cur_time - ap->link_time;
3485 if (delta > ANEG_STATE_SETTLE_TIME)
3486 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3488 ret = ANEG_TIMER_ENAB;
3491 case ANEG_STATE_DISABLE_LINK_OK:
3495 case ANEG_STATE_ABILITY_DETECT_INIT:
3496 ap->flags &= ~(MR_TOGGLE_TX);
3497 ap->txconfig = ANEG_CFG_FD;
3498 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3499 if (flowctrl & ADVERTISE_1000XPAUSE)
3500 ap->txconfig |= ANEG_CFG_PS1;
3501 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3502 ap->txconfig |= ANEG_CFG_PS2;
3503 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3504 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3505 tw32_f(MAC_MODE, tp->mac_mode);
3508 ap->state = ANEG_STATE_ABILITY_DETECT;
3511 case ANEG_STATE_ABILITY_DETECT:
3512 if (ap->ability_match != 0 && ap->rxconfig != 0)
3513 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3516 case ANEG_STATE_ACK_DETECT_INIT:
3517 ap->txconfig |= ANEG_CFG_ACK;
3518 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3519 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3520 tw32_f(MAC_MODE, tp->mac_mode);
3523 ap->state = ANEG_STATE_ACK_DETECT;
3526 case ANEG_STATE_ACK_DETECT:
3527 if (ap->ack_match != 0) {
3528 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3529 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3530 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3532 ap->state = ANEG_STATE_AN_ENABLE;
3534 } else if (ap->ability_match != 0 &&
3535 ap->rxconfig == 0) {
3536 ap->state = ANEG_STATE_AN_ENABLE;
3540 case ANEG_STATE_COMPLETE_ACK_INIT:
3541 if (ap->rxconfig & ANEG_CFG_INVAL) {
3545 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3546 MR_LP_ADV_HALF_DUPLEX |
3547 MR_LP_ADV_SYM_PAUSE |
3548 MR_LP_ADV_ASYM_PAUSE |
3549 MR_LP_ADV_REMOTE_FAULT1 |
3550 MR_LP_ADV_REMOTE_FAULT2 |
3551 MR_LP_ADV_NEXT_PAGE |
3554 if (ap->rxconfig & ANEG_CFG_FD)
3555 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3556 if (ap->rxconfig & ANEG_CFG_HD)
3557 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3558 if (ap->rxconfig & ANEG_CFG_PS1)
3559 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3560 if (ap->rxconfig & ANEG_CFG_PS2)
3561 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3562 if (ap->rxconfig & ANEG_CFG_RF1)
3563 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3564 if (ap->rxconfig & ANEG_CFG_RF2)
3565 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3566 if (ap->rxconfig & ANEG_CFG_NP)
3567 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3569 ap->link_time = ap->cur_time;
3571 ap->flags ^= (MR_TOGGLE_TX);
3572 if (ap->rxconfig & 0x0008)
3573 ap->flags |= MR_TOGGLE_RX;
3574 if (ap->rxconfig & ANEG_CFG_NP)
3575 ap->flags |= MR_NP_RX;
3576 ap->flags |= MR_PAGE_RX;
3578 ap->state = ANEG_STATE_COMPLETE_ACK;
3579 ret = ANEG_TIMER_ENAB;
3582 case ANEG_STATE_COMPLETE_ACK:
3583 if (ap->ability_match != 0 &&
3584 ap->rxconfig == 0) {
3585 ap->state = ANEG_STATE_AN_ENABLE;
3588 delta = ap->cur_time - ap->link_time;
3589 if (delta > ANEG_STATE_SETTLE_TIME) {
3590 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3591 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3593 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3594 !(ap->flags & MR_NP_RX)) {
3595 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3603 case ANEG_STATE_IDLE_DETECT_INIT:
3604 ap->link_time = ap->cur_time;
3605 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3606 tw32_f(MAC_MODE, tp->mac_mode);
3609 ap->state = ANEG_STATE_IDLE_DETECT;
3610 ret = ANEG_TIMER_ENAB;
3613 case ANEG_STATE_IDLE_DETECT:
3614 if (ap->ability_match != 0 &&
3615 ap->rxconfig == 0) {
3616 ap->state = ANEG_STATE_AN_ENABLE;
3619 delta = ap->cur_time - ap->link_time;
3620 if (delta > ANEG_STATE_SETTLE_TIME) {
3621 /* XXX another gem from the Broadcom driver :( */
3622 ap->state = ANEG_STATE_LINK_OK;
3626 case ANEG_STATE_LINK_OK:
3627 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3631 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3632 /* ??? unimplemented */
3635 case ANEG_STATE_NEXT_PAGE_WAIT:
3636 /* ??? unimplemented */
3647 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3650 struct tg3_fiber_aneginfo aninfo;
3651 int status = ANEG_FAILED;
3655 tw32_f(MAC_TX_AUTO_NEG, 0);
3657 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3658 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3661 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3664 memset(&aninfo, 0, sizeof(aninfo));
3665 aninfo.flags |= MR_AN_ENABLE;
3666 aninfo.state = ANEG_STATE_UNKNOWN;
3667 aninfo.cur_time = 0;
3669 while (++tick < 195000) {
3670 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3671 if (status == ANEG_DONE || status == ANEG_FAILED)
3677 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3678 tw32_f(MAC_MODE, tp->mac_mode);
3681 *txflags = aninfo.txconfig;
3682 *rxflags = aninfo.flags;
3684 if (status == ANEG_DONE &&
3685 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3686 MR_LP_ADV_FULL_DUPLEX)))
3692 static void tg3_init_bcm8002(struct tg3 *tp)
3694 u32 mac_status = tr32(MAC_STATUS);
3697 /* Reset when initting first time or we have a link. */
3698 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3699 !(mac_status & MAC_STATUS_PCS_SYNCED))
3702 /* Set PLL lock range. */
3703 tg3_writephy(tp, 0x16, 0x8007);
3706 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3708 /* Wait for reset to complete. */
3709 /* XXX schedule_timeout() ... */
3710 for (i = 0; i < 500; i++)
3713 /* Config mode; select PMA/Ch 1 regs. */
3714 tg3_writephy(tp, 0x10, 0x8411);
3716 /* Enable auto-lock and comdet, select txclk for tx. */
3717 tg3_writephy(tp, 0x11, 0x0a10);
3719 tg3_writephy(tp, 0x18, 0x00a0);
3720 tg3_writephy(tp, 0x16, 0x41ff);
3722 /* Assert and deassert POR. */
3723 tg3_writephy(tp, 0x13, 0x0400);
3725 tg3_writephy(tp, 0x13, 0x0000);
3727 tg3_writephy(tp, 0x11, 0x0a50);
3729 tg3_writephy(tp, 0x11, 0x0a10);
3731 /* Wait for signal to stabilize */
3732 /* XXX schedule_timeout() ... */
3733 for (i = 0; i < 15000; i++)
3736 /* Deselect the channel register so we can read the PHYID
3739 tg3_writephy(tp, 0x10, 0x8011);
3742 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3745 u32 sg_dig_ctrl, sg_dig_status;
3746 u32 serdes_cfg, expected_sg_dig_ctrl;
3747 int workaround, port_a;
3748 int current_link_up;
3751 expected_sg_dig_ctrl = 0;
3754 current_link_up = 0;
3756 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3757 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3759 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3762 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3763 /* preserve bits 20-23 for voltage regulator */
3764 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3767 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3769 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3770 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3772 u32 val = serdes_cfg;
3778 tw32_f(MAC_SERDES_CFG, val);
3781 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3783 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3784 tg3_setup_flow_control(tp, 0, 0);
3785 current_link_up = 1;
3790 /* Want auto-negotiation. */
3791 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3793 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3794 if (flowctrl & ADVERTISE_1000XPAUSE)
3795 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3796 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3797 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3799 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3800 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3801 tp->serdes_counter &&
3802 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3803 MAC_STATUS_RCVD_CFG)) ==
3804 MAC_STATUS_PCS_SYNCED)) {
3805 tp->serdes_counter--;
3806 current_link_up = 1;
3811 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3812 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3814 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3816 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3817 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3818 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3819 MAC_STATUS_SIGNAL_DET)) {
3820 sg_dig_status = tr32(SG_DIG_STATUS);
3821 mac_status = tr32(MAC_STATUS);
3823 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3824 (mac_status & MAC_STATUS_PCS_SYNCED)) {
3825 u32 local_adv = 0, remote_adv = 0;
3827 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3828 local_adv |= ADVERTISE_1000XPAUSE;
3829 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3830 local_adv |= ADVERTISE_1000XPSE_ASYM;
3832 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3833 remote_adv |= LPA_1000XPAUSE;
3834 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3835 remote_adv |= LPA_1000XPAUSE_ASYM;
3837 tg3_setup_flow_control(tp, local_adv, remote_adv);
3838 current_link_up = 1;
3839 tp->serdes_counter = 0;
3840 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3841 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3842 if (tp->serdes_counter)
3843 tp->serdes_counter--;
3846 u32 val = serdes_cfg;
3853 tw32_f(MAC_SERDES_CFG, val);
3856 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3859 /* Link parallel detection - link is up */
3860 /* only if we have PCS_SYNC and not */
3861 /* receiving config code words */
3862 mac_status = tr32(MAC_STATUS);
3863 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3864 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3865 tg3_setup_flow_control(tp, 0, 0);
3866 current_link_up = 1;
3868 TG3_FLG2_PARALLEL_DETECT;
3869 tp->serdes_counter =
3870 SERDES_PARALLEL_DET_TIMEOUT;
3872 goto restart_autoneg;
3876 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3877 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3881 return current_link_up;
3884 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3886 int current_link_up = 0;
3888 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3891 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3892 u32 txflags, rxflags;
3895 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3896 u32 local_adv = 0, remote_adv = 0;
3898 if (txflags & ANEG_CFG_PS1)
3899 local_adv |= ADVERTISE_1000XPAUSE;
3900 if (txflags & ANEG_CFG_PS2)
3901 local_adv |= ADVERTISE_1000XPSE_ASYM;
3903 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3904 remote_adv |= LPA_1000XPAUSE;
3905 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3906 remote_adv |= LPA_1000XPAUSE_ASYM;
3908 tg3_setup_flow_control(tp, local_adv, remote_adv);
3910 current_link_up = 1;
3912 for (i = 0; i < 30; i++) {
3915 (MAC_STATUS_SYNC_CHANGED |
3916 MAC_STATUS_CFG_CHANGED));
3918 if ((tr32(MAC_STATUS) &
3919 (MAC_STATUS_SYNC_CHANGED |
3920 MAC_STATUS_CFG_CHANGED)) == 0)
3924 mac_status = tr32(MAC_STATUS);
3925 if (current_link_up == 0 &&
3926 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3927 !(mac_status & MAC_STATUS_RCVD_CFG))
3928 current_link_up = 1;
3930 tg3_setup_flow_control(tp, 0, 0);
3932 /* Forcing 1000FD link up. */
3933 current_link_up = 1;
3935 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3938 tw32_f(MAC_MODE, tp->mac_mode);
3943 return current_link_up;
3946 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3949 u16 orig_active_speed;
3950 u8 orig_active_duplex;
3952 int current_link_up;
3955 orig_pause_cfg = tp->link_config.active_flowctrl;
3956 orig_active_speed = tp->link_config.active_speed;
3957 orig_active_duplex = tp->link_config.active_duplex;
3959 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3960 netif_carrier_ok(tp->dev) &&
3961 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3962 mac_status = tr32(MAC_STATUS);
3963 mac_status &= (MAC_STATUS_PCS_SYNCED |
3964 MAC_STATUS_SIGNAL_DET |
3965 MAC_STATUS_CFG_CHANGED |
3966 MAC_STATUS_RCVD_CFG);
3967 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3968 MAC_STATUS_SIGNAL_DET)) {
3969 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3970 MAC_STATUS_CFG_CHANGED));
3975 tw32_f(MAC_TX_AUTO_NEG, 0);
3977 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3978 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3979 tw32_f(MAC_MODE, tp->mac_mode);
3982 if (tp->phy_id == TG3_PHY_ID_BCM8002)
3983 tg3_init_bcm8002(tp);
3985 /* Enable link change event even when serdes polling. */
3986 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3989 current_link_up = 0;
3990 mac_status = tr32(MAC_STATUS);
3992 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3993 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3995 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3997 tp->napi[0].hw_status->status =
3998 (SD_STATUS_UPDATED |
3999 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4001 for (i = 0; i < 100; i++) {
4002 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4003 MAC_STATUS_CFG_CHANGED));
4005 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4006 MAC_STATUS_CFG_CHANGED |
4007 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4011 mac_status = tr32(MAC_STATUS);
4012 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4013 current_link_up = 0;
4014 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4015 tp->serdes_counter == 0) {
4016 tw32_f(MAC_MODE, (tp->mac_mode |
4017 MAC_MODE_SEND_CONFIGS));
4019 tw32_f(MAC_MODE, tp->mac_mode);
4023 if (current_link_up == 1) {
4024 tp->link_config.active_speed = SPEED_1000;
4025 tp->link_config.active_duplex = DUPLEX_FULL;
4026 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4027 LED_CTRL_LNKLED_OVERRIDE |
4028 LED_CTRL_1000MBPS_ON));
4030 tp->link_config.active_speed = SPEED_INVALID;
4031 tp->link_config.active_duplex = DUPLEX_INVALID;
4032 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4033 LED_CTRL_LNKLED_OVERRIDE |
4034 LED_CTRL_TRAFFIC_OVERRIDE));
4037 if (current_link_up != netif_carrier_ok(tp->dev)) {
4038 if (current_link_up)
4039 netif_carrier_on(tp->dev);
4041 netif_carrier_off(tp->dev);
4042 tg3_link_report(tp);
4044 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4045 if (orig_pause_cfg != now_pause_cfg ||
4046 orig_active_speed != tp->link_config.active_speed ||
4047 orig_active_duplex != tp->link_config.active_duplex)
4048 tg3_link_report(tp);
4054 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4056 int current_link_up, err = 0;
4060 u32 local_adv, remote_adv;
4062 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4063 tw32_f(MAC_MODE, tp->mac_mode);
4069 (MAC_STATUS_SYNC_CHANGED |
4070 MAC_STATUS_CFG_CHANGED |
4071 MAC_STATUS_MI_COMPLETION |
4072 MAC_STATUS_LNKSTATE_CHANGED));
4078 current_link_up = 0;
4079 current_speed = SPEED_INVALID;
4080 current_duplex = DUPLEX_INVALID;
4082 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4083 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4084 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4085 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4086 bmsr |= BMSR_LSTATUS;
4088 bmsr &= ~BMSR_LSTATUS;
4091 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4093 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4094 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4095 /* do nothing, just check for link up at the end */
4096 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4099 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4100 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4101 ADVERTISE_1000XPAUSE |
4102 ADVERTISE_1000XPSE_ASYM |
4105 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4107 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4108 new_adv |= ADVERTISE_1000XHALF;
4109 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4110 new_adv |= ADVERTISE_1000XFULL;
4112 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4113 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4114 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4115 tg3_writephy(tp, MII_BMCR, bmcr);
4117 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4118 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4119 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4126 bmcr &= ~BMCR_SPEED1000;
4127 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4129 if (tp->link_config.duplex == DUPLEX_FULL)
4130 new_bmcr |= BMCR_FULLDPLX;
4132 if (new_bmcr != bmcr) {
4133 /* BMCR_SPEED1000 is a reserved bit that needs
4134 * to be set on write.
4136 new_bmcr |= BMCR_SPEED1000;
4138 /* Force a linkdown */
4139 if (netif_carrier_ok(tp->dev)) {
4142 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4143 adv &= ~(ADVERTISE_1000XFULL |
4144 ADVERTISE_1000XHALF |
4146 tg3_writephy(tp, MII_ADVERTISE, adv);
4147 tg3_writephy(tp, MII_BMCR, bmcr |
4151 netif_carrier_off(tp->dev);
4153 tg3_writephy(tp, MII_BMCR, new_bmcr);
4155 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4156 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4157 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4159 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4160 bmsr |= BMSR_LSTATUS;
4162 bmsr &= ~BMSR_LSTATUS;
4164 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4168 if (bmsr & BMSR_LSTATUS) {
4169 current_speed = SPEED_1000;
4170 current_link_up = 1;
4171 if (bmcr & BMCR_FULLDPLX)
4172 current_duplex = DUPLEX_FULL;
4174 current_duplex = DUPLEX_HALF;
4179 if (bmcr & BMCR_ANENABLE) {
4182 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4183 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4184 common = local_adv & remote_adv;
4185 if (common & (ADVERTISE_1000XHALF |
4186 ADVERTISE_1000XFULL)) {
4187 if (common & ADVERTISE_1000XFULL)
4188 current_duplex = DUPLEX_FULL;
4190 current_duplex = DUPLEX_HALF;
4192 current_link_up = 0;
4197 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4198 tg3_setup_flow_control(tp, local_adv, remote_adv);
4200 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4201 if (tp->link_config.active_duplex == DUPLEX_HALF)
4202 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4204 tw32_f(MAC_MODE, tp->mac_mode);
4207 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4209 tp->link_config.active_speed = current_speed;
4210 tp->link_config.active_duplex = current_duplex;
4212 if (current_link_up != netif_carrier_ok(tp->dev)) {
4213 if (current_link_up)
4214 netif_carrier_on(tp->dev);
4216 netif_carrier_off(tp->dev);
4217 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4219 tg3_link_report(tp);
4224 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4226 if (tp->serdes_counter) {
4227 /* Give autoneg time to complete. */
4228 tp->serdes_counter--;
4232 if (!netif_carrier_ok(tp->dev) &&
4233 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4236 tg3_readphy(tp, MII_BMCR, &bmcr);
4237 if (bmcr & BMCR_ANENABLE) {
4240 /* Select shadow register 0x1f */
4241 tg3_writephy(tp, 0x1c, 0x7c00);
4242 tg3_readphy(tp, 0x1c, &phy1);
4244 /* Select expansion interrupt status register */
4245 tg3_writephy(tp, 0x17, 0x0f01);
4246 tg3_readphy(tp, 0x15, &phy2);
4247 tg3_readphy(tp, 0x15, &phy2);
4249 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4250 /* We have signal detect and not receiving
4251 * config code words, link is up by parallel
4255 bmcr &= ~BMCR_ANENABLE;
4256 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4257 tg3_writephy(tp, MII_BMCR, bmcr);
4258 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4261 } else if (netif_carrier_ok(tp->dev) &&
4262 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4263 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4266 /* Select expansion interrupt status register */
4267 tg3_writephy(tp, 0x17, 0x0f01);
4268 tg3_readphy(tp, 0x15, &phy2);
4272 /* Config code words received, turn on autoneg. */
4273 tg3_readphy(tp, MII_BMCR, &bmcr);
4274 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4276 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4282 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4286 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
4287 err = tg3_setup_fiber_phy(tp, force_reset);
4288 else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
4289 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4291 err = tg3_setup_copper_phy(tp, force_reset);
4293 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4296 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4297 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4299 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4304 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4305 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4306 tw32(GRC_MISC_CFG, val);
4309 if (tp->link_config.active_speed == SPEED_1000 &&
4310 tp->link_config.active_duplex == DUPLEX_HALF)
4311 tw32(MAC_TX_LENGTHS,
4312 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4313 (6 << TX_LENGTHS_IPG_SHIFT) |
4314 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4316 tw32(MAC_TX_LENGTHS,
4317 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4318 (6 << TX_LENGTHS_IPG_SHIFT) |
4319 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4321 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4322 if (netif_carrier_ok(tp->dev)) {
4323 tw32(HOSTCC_STAT_COAL_TICKS,
4324 tp->coal.stats_block_coalesce_usecs);
4326 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4330 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4331 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4332 if (!netif_carrier_ok(tp->dev))
4333 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4336 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4337 tw32(PCIE_PWR_MGMT_THRESH, val);
4343 /* This is called whenever we suspect that the system chipset is re-
4344 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4345 * is bogus tx completions. We try to recover by setting the
4346 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4349 static void tg3_tx_recover(struct tg3 *tp)
4351 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4352 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4354 netdev_warn(tp->dev,
4355 "The system may be re-ordering memory-mapped I/O "
4356 "cycles to the network device, attempting to recover. "
4357 "Please report the problem to the driver maintainer "
4358 "and include system chipset information.\n");
4360 spin_lock(&tp->lock);
4361 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4362 spin_unlock(&tp->lock);
4365 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4368 return tnapi->tx_pending -
4369 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4372 /* Tigon3 never reports partial packet sends. So we do not
4373 * need special logic to handle SKBs that have not had all
4374 * of their frags sent yet, like SunGEM does.
4376 static void tg3_tx(struct tg3_napi *tnapi)
4378 struct tg3 *tp = tnapi->tp;
4379 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4380 u32 sw_idx = tnapi->tx_cons;
4381 struct netdev_queue *txq;
4382 int index = tnapi - tp->napi;
4384 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4387 txq = netdev_get_tx_queue(tp->dev, index);
4389 while (sw_idx != hw_idx) {
4390 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4391 struct sk_buff *skb = ri->skb;
4394 if (unlikely(skb == NULL)) {
4399 pci_unmap_single(tp->pdev,
4400 pci_unmap_addr(ri, mapping),
4406 sw_idx = NEXT_TX(sw_idx);
4408 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4409 ri = &tnapi->tx_buffers[sw_idx];
4410 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4413 pci_unmap_page(tp->pdev,
4414 pci_unmap_addr(ri, mapping),
4415 skb_shinfo(skb)->frags[i].size,
4417 sw_idx = NEXT_TX(sw_idx);
4422 if (unlikely(tx_bug)) {
4428 tnapi->tx_cons = sw_idx;
4430 /* Need to make the tx_cons update visible to tg3_start_xmit()
4431 * before checking for netif_queue_stopped(). Without the
4432 * memory barrier, there is a small possibility that tg3_start_xmit()
4433 * will miss it and cause the queue to be stopped forever.
4437 if (unlikely(netif_tx_queue_stopped(txq) &&
4438 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4439 __netif_tx_lock(txq, smp_processor_id());
4440 if (netif_tx_queue_stopped(txq) &&
4441 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4442 netif_tx_wake_queue(txq);
4443 __netif_tx_unlock(txq);
4447 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4452 pci_unmap_single(tp->pdev, pci_unmap_addr(ri, mapping),
4453 map_sz, PCI_DMA_FROMDEVICE);
4454 dev_kfree_skb_any(ri->skb);
4458 /* Returns size of skb allocated or < 0 on error.
4460 * We only need to fill in the address because the other members
4461 * of the RX descriptor are invariant, see tg3_init_rings.
4463 * Note the purposeful assymetry of cpu vs. chip accesses. For
4464 * posting buffers we only dirty the first cache line of the RX
4465 * descriptor (containing the address). Whereas for the RX status
4466 * buffers the cpu only reads the last cacheline of the RX descriptor
4467 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4469 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4470 u32 opaque_key, u32 dest_idx_unmasked)
4472 struct tg3_rx_buffer_desc *desc;
4473 struct ring_info *map, *src_map;
4474 struct sk_buff *skb;
4476 int skb_size, dest_idx;
4479 switch (opaque_key) {
4480 case RXD_OPAQUE_RING_STD:
4481 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4482 desc = &tpr->rx_std[dest_idx];
4483 map = &tpr->rx_std_buffers[dest_idx];
4484 skb_size = tp->rx_pkt_map_sz;
4487 case RXD_OPAQUE_RING_JUMBO:
4488 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4489 desc = &tpr->rx_jmb[dest_idx].std;
4490 map = &tpr->rx_jmb_buffers[dest_idx];
4491 skb_size = TG3_RX_JMB_MAP_SZ;
4498 /* Do not overwrite any of the map or rp information
4499 * until we are sure we can commit to a new buffer.
4501 * Callers depend upon this behavior and assume that
4502 * we leave everything unchanged if we fail.
4504 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4508 skb_reserve(skb, tp->rx_offset);
4510 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4511 PCI_DMA_FROMDEVICE);
4512 if (pci_dma_mapping_error(tp->pdev, mapping)) {
4518 pci_unmap_addr_set(map, mapping, mapping);
4520 desc->addr_hi = ((u64)mapping >> 32);
4521 desc->addr_lo = ((u64)mapping & 0xffffffff);
4526 /* We only need to move over in the address because the other
4527 * members of the RX descriptor are invariant. See notes above
4528 * tg3_alloc_rx_skb for full details.
4530 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4531 struct tg3_rx_prodring_set *dpr,
4532 u32 opaque_key, int src_idx,
4533 u32 dest_idx_unmasked)
4535 struct tg3 *tp = tnapi->tp;
4536 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4537 struct ring_info *src_map, *dest_map;
4538 struct tg3_rx_prodring_set *spr = &tp->prodring[0];
4541 switch (opaque_key) {
4542 case RXD_OPAQUE_RING_STD:
4543 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4544 dest_desc = &dpr->rx_std[dest_idx];
4545 dest_map = &dpr->rx_std_buffers[dest_idx];
4546 src_desc = &spr->rx_std[src_idx];
4547 src_map = &spr->rx_std_buffers[src_idx];
4550 case RXD_OPAQUE_RING_JUMBO:
4551 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4552 dest_desc = &dpr->rx_jmb[dest_idx].std;
4553 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4554 src_desc = &spr->rx_jmb[src_idx].std;
4555 src_map = &spr->rx_jmb_buffers[src_idx];
4562 dest_map->skb = src_map->skb;
4563 pci_unmap_addr_set(dest_map, mapping,
4564 pci_unmap_addr(src_map, mapping));
4565 dest_desc->addr_hi = src_desc->addr_hi;
4566 dest_desc->addr_lo = src_desc->addr_lo;
4568 /* Ensure that the update to the skb happens after the physical
4569 * addresses have been transferred to the new BD location.
4573 src_map->skb = NULL;
4576 /* The RX ring scheme is composed of multiple rings which post fresh
4577 * buffers to the chip, and one special ring the chip uses to report
4578 * status back to the host.
4580 * The special ring reports the status of received packets to the
4581 * host. The chip does not write into the original descriptor the
4582 * RX buffer was obtained from. The chip simply takes the original
4583 * descriptor as provided by the host, updates the status and length
4584 * field, then writes this into the next status ring entry.
4586 * Each ring the host uses to post buffers to the chip is described
4587 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4588 * it is first placed into the on-chip ram. When the packet's length
4589 * is known, it walks down the TG3_BDINFO entries to select the ring.
4590 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4591 * which is within the range of the new packet's length is chosen.
4593 * The "separate ring for rx status" scheme may sound queer, but it makes
4594 * sense from a cache coherency perspective. If only the host writes
4595 * to the buffer post rings, and only the chip writes to the rx status
4596 * rings, then cache lines never move beyond shared-modified state.
4597 * If both the host and chip were to write into the same ring, cache line
4598 * eviction could occur since both entities want it in an exclusive state.
4600 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4602 struct tg3 *tp = tnapi->tp;
4603 u32 work_mask, rx_std_posted = 0;
4604 u32 std_prod_idx, jmb_prod_idx;
4605 u32 sw_idx = tnapi->rx_rcb_ptr;
4608 struct tg3_rx_prodring_set *tpr = tnapi->prodring;
4610 hw_idx = *(tnapi->rx_rcb_prod_idx);
4612 * We need to order the read of hw_idx and the read of
4613 * the opaque cookie.
4618 std_prod_idx = tpr->rx_std_prod_idx;
4619 jmb_prod_idx = tpr->rx_jmb_prod_idx;
4620 while (sw_idx != hw_idx && budget > 0) {
4621 struct ring_info *ri;
4622 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4624 struct sk_buff *skb;
4625 dma_addr_t dma_addr;
4626 u32 opaque_key, desc_idx, *post_ptr;
4628 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4629 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4630 if (opaque_key == RXD_OPAQUE_RING_STD) {
4631 ri = &tp->prodring[0].rx_std_buffers[desc_idx];
4632 dma_addr = pci_unmap_addr(ri, mapping);
4634 post_ptr = &std_prod_idx;
4636 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4637 ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
4638 dma_addr = pci_unmap_addr(ri, mapping);
4640 post_ptr = &jmb_prod_idx;
4642 goto next_pkt_nopost;
4644 work_mask |= opaque_key;
4646 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4647 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4649 tg3_recycle_rx(tnapi, tpr, opaque_key,
4650 desc_idx, *post_ptr);
4652 /* Other statistics kept track of by card. */
4653 tp->net_stats.rx_dropped++;
4657 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4660 if (len > TG3_RX_COPY_THRESH(tp)) {
4663 skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4668 pci_unmap_single(tp->pdev, dma_addr, skb_size,
4669 PCI_DMA_FROMDEVICE);
4671 /* Ensure that the update to the skb happens
4672 * after the usage of the old DMA mapping.
4680 struct sk_buff *copy_skb;
4682 tg3_recycle_rx(tnapi, tpr, opaque_key,
4683 desc_idx, *post_ptr);
4685 copy_skb = netdev_alloc_skb(tp->dev,
4686 len + TG3_RAW_IP_ALIGN);
4687 if (copy_skb == NULL)
4688 goto drop_it_no_recycle;
4690 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4691 skb_put(copy_skb, len);
4692 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4693 skb_copy_from_linear_data(skb, copy_skb->data, len);
4694 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4696 /* We'll reuse the original ring buffer. */
4700 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4701 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4702 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4703 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4704 skb->ip_summed = CHECKSUM_UNNECESSARY;
4706 skb->ip_summed = CHECKSUM_NONE;
4708 skb->protocol = eth_type_trans(skb, tp->dev);
4710 if (len > (tp->dev->mtu + ETH_HLEN) &&
4711 skb->protocol != htons(ETH_P_8021Q)) {
4716 #if TG3_VLAN_TAG_USED
4717 if (tp->vlgrp != NULL &&
4718 desc->type_flags & RXD_FLAG_VLAN) {
4719 vlan_gro_receive(&tnapi->napi, tp->vlgrp,
4720 desc->err_vlan & RXD_VLAN_MASK, skb);
4723 napi_gro_receive(&tnapi->napi, skb);
4731 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4732 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4733 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4734 tpr->rx_std_prod_idx);
4735 work_mask &= ~RXD_OPAQUE_RING_STD;
4740 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4742 /* Refresh hw_idx to see if there is new work */
4743 if (sw_idx == hw_idx) {
4744 hw_idx = *(tnapi->rx_rcb_prod_idx);
4749 /* ACK the status ring. */
4750 tnapi->rx_rcb_ptr = sw_idx;
4751 tw32_rx_mbox(tnapi->consmbox, sw_idx);
4753 /* Refill RX ring(s). */
4754 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4755 if (work_mask & RXD_OPAQUE_RING_STD) {
4756 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4757 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4758 tpr->rx_std_prod_idx);
4760 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4761 tpr->rx_jmb_prod_idx = jmb_prod_idx %
4762 TG3_RX_JUMBO_RING_SIZE;
4763 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4764 tpr->rx_jmb_prod_idx);
4767 } else if (work_mask) {
4768 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4769 * updated before the producer indices can be updated.
4773 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4774 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
4776 if (tnapi != &tp->napi[1])
4777 napi_schedule(&tp->napi[1].napi);
4783 static void tg3_poll_link(struct tg3 *tp)
4785 /* handle link change and other phy events */
4786 if (!(tp->tg3_flags &
4787 (TG3_FLAG_USE_LINKCHG_REG |
4788 TG3_FLAG_POLL_SERDES))) {
4789 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4791 if (sblk->status & SD_STATUS_LINK_CHG) {
4792 sblk->status = SD_STATUS_UPDATED |
4793 (sblk->status & ~SD_STATUS_LINK_CHG);
4794 spin_lock(&tp->lock);
4795 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4797 (MAC_STATUS_SYNC_CHANGED |
4798 MAC_STATUS_CFG_CHANGED |
4799 MAC_STATUS_MI_COMPLETION |
4800 MAC_STATUS_LNKSTATE_CHANGED));
4803 tg3_setup_phy(tp, 0);
4804 spin_unlock(&tp->lock);
4809 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4810 struct tg3_rx_prodring_set *dpr,
4811 struct tg3_rx_prodring_set *spr)
4813 u32 si, di, cpycnt, src_prod_idx;
4817 src_prod_idx = spr->rx_std_prod_idx;
4819 /* Make sure updates to the rx_std_buffers[] entries and the
4820 * standard producer index are seen in the correct order.
4824 if (spr->rx_std_cons_idx == src_prod_idx)
4827 if (spr->rx_std_cons_idx < src_prod_idx)
4828 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4830 cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4832 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4834 si = spr->rx_std_cons_idx;
4835 di = dpr->rx_std_prod_idx;
4837 for (i = di; i < di + cpycnt; i++) {
4838 if (dpr->rx_std_buffers[i].skb) {
4848 /* Ensure that updates to the rx_std_buffers ring and the
4849 * shadowed hardware producer ring from tg3_recycle_skb() are
4850 * ordered correctly WRT the skb check above.
4854 memcpy(&dpr->rx_std_buffers[di],
4855 &spr->rx_std_buffers[si],
4856 cpycnt * sizeof(struct ring_info));
4858 for (i = 0; i < cpycnt; i++, di++, si++) {
4859 struct tg3_rx_buffer_desc *sbd, *dbd;
4860 sbd = &spr->rx_std[si];
4861 dbd = &dpr->rx_std[di];
4862 dbd->addr_hi = sbd->addr_hi;
4863 dbd->addr_lo = sbd->addr_lo;
4866 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4868 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4873 src_prod_idx = spr->rx_jmb_prod_idx;
4875 /* Make sure updates to the rx_jmb_buffers[] entries and
4876 * the jumbo producer index are seen in the correct order.
4880 if (spr->rx_jmb_cons_idx == src_prod_idx)
4883 if (spr->rx_jmb_cons_idx < src_prod_idx)
4884 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4886 cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4888 cpycnt = min(cpycnt,
4889 TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4891 si = spr->rx_jmb_cons_idx;
4892 di = dpr->rx_jmb_prod_idx;
4894 for (i = di; i < di + cpycnt; i++) {
4895 if (dpr->rx_jmb_buffers[i].skb) {
4905 /* Ensure that updates to the rx_jmb_buffers ring and the
4906 * shadowed hardware producer ring from tg3_recycle_skb() are
4907 * ordered correctly WRT the skb check above.
4911 memcpy(&dpr->rx_jmb_buffers[di],
4912 &spr->rx_jmb_buffers[si],
4913 cpycnt * sizeof(struct ring_info));
4915 for (i = 0; i < cpycnt; i++, di++, si++) {
4916 struct tg3_rx_buffer_desc *sbd, *dbd;
4917 sbd = &spr->rx_jmb[si].std;
4918 dbd = &dpr->rx_jmb[di].std;
4919 dbd->addr_hi = sbd->addr_hi;
4920 dbd->addr_lo = sbd->addr_lo;
4923 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4924 TG3_RX_JUMBO_RING_SIZE;
4925 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4926 TG3_RX_JUMBO_RING_SIZE;
4932 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4934 struct tg3 *tp = tnapi->tp;
4936 /* run TX completion thread */
4937 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4939 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4943 /* run RX thread, within the bounds set by NAPI.
4944 * All RX "locking" is done by ensuring outside
4945 * code synchronizes with tg3->napi.poll()
4947 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4948 work_done += tg3_rx(tnapi, budget - work_done);
4950 if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4951 struct tg3_rx_prodring_set *dpr = &tp->prodring[0];
4953 u32 std_prod_idx = dpr->rx_std_prod_idx;
4954 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
4956 for (i = 1; i < tp->irq_cnt; i++)
4957 err |= tg3_rx_prodring_xfer(tp, dpr,
4958 tp->napi[i].prodring);
4962 if (std_prod_idx != dpr->rx_std_prod_idx)
4963 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4964 dpr->rx_std_prod_idx);
4966 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
4967 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4968 dpr->rx_jmb_prod_idx);
4973 tw32_f(HOSTCC_MODE, tp->coal_now);
4979 static int tg3_poll_msix(struct napi_struct *napi, int budget)
4981 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4982 struct tg3 *tp = tnapi->tp;
4984 struct tg3_hw_status *sblk = tnapi->hw_status;
4987 work_done = tg3_poll_work(tnapi, work_done, budget);
4989 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4992 if (unlikely(work_done >= budget))
4995 /* tp->last_tag is used in tg3_int_reenable() below
4996 * to tell the hw how much work has been processed,
4997 * so we must read it before checking for more work.
4999 tnapi->last_tag = sblk->status_tag;
5000 tnapi->last_irq_tag = tnapi->last_tag;
5003 /* check for RX/TX work to do */
5004 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5005 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5006 napi_complete(napi);
5007 /* Reenable interrupts. */
5008 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5017 /* work_done is guaranteed to be less than budget. */
5018 napi_complete(napi);
5019 schedule_work(&tp->reset_task);
5023 static int tg3_poll(struct napi_struct *napi, int budget)
5025 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5026 struct tg3 *tp = tnapi->tp;
5028 struct tg3_hw_status *sblk = tnapi->hw_status;
5033 work_done = tg3_poll_work(tnapi, work_done, budget);
5035 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5038 if (unlikely(work_done >= budget))
5041 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5042 /* tp->last_tag is used in tg3_int_reenable() below
5043 * to tell the hw how much work has been processed,
5044 * so we must read it before checking for more work.
5046 tnapi->last_tag = sblk->status_tag;
5047 tnapi->last_irq_tag = tnapi->last_tag;
5050 sblk->status &= ~SD_STATUS_UPDATED;
5052 if (likely(!tg3_has_work(tnapi))) {
5053 napi_complete(napi);
5054 tg3_int_reenable(tnapi);
5062 /* work_done is guaranteed to be less than budget. */
5063 napi_complete(napi);
5064 schedule_work(&tp->reset_task);
5068 static void tg3_irq_quiesce(struct tg3 *tp)
5072 BUG_ON(tp->irq_sync);
5077 for (i = 0; i < tp->irq_cnt; i++)
5078 synchronize_irq(tp->napi[i].irq_vec);
5081 static inline int tg3_irq_sync(struct tg3 *tp)
5083 return tp->irq_sync;
5086 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5087 * If irq_sync is non-zero, then the IRQ handler must be synchronized
5088 * with as well. Most of the time, this is not necessary except when
5089 * shutting down the device.
5091 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5093 spin_lock_bh(&tp->lock);
5095 tg3_irq_quiesce(tp);
5098 static inline void tg3_full_unlock(struct tg3 *tp)
5100 spin_unlock_bh(&tp->lock);
5103 /* One-shot MSI handler - Chip automatically disables interrupt
5104 * after sending MSI so driver doesn't have to do it.
5106 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5108 struct tg3_napi *tnapi = dev_id;
5109 struct tg3 *tp = tnapi->tp;
5111 prefetch(tnapi->hw_status);
5113 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5115 if (likely(!tg3_irq_sync(tp)))
5116 napi_schedule(&tnapi->napi);
5121 /* MSI ISR - No need to check for interrupt sharing and no need to
5122 * flush status block and interrupt mailbox. PCI ordering rules
5123 * guarantee that MSI will arrive after the status block.
5125 static irqreturn_t tg3_msi(int irq, void *dev_id)
5127 struct tg3_napi *tnapi = dev_id;
5128 struct tg3 *tp = tnapi->tp;
5130 prefetch(tnapi->hw_status);
5132 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5134 * Writing any value to intr-mbox-0 clears PCI INTA# and
5135 * chip-internal interrupt pending events.
5136 * Writing non-zero to intr-mbox-0 additional tells the
5137 * NIC to stop sending us irqs, engaging "in-intr-handler"
5140 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5141 if (likely(!tg3_irq_sync(tp)))
5142 napi_schedule(&tnapi->napi);
5144 return IRQ_RETVAL(1);
5147 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5149 struct tg3_napi *tnapi = dev_id;
5150 struct tg3 *tp = tnapi->tp;
5151 struct tg3_hw_status *sblk = tnapi->hw_status;
5152 unsigned int handled = 1;
5154 /* In INTx mode, it is possible for the interrupt to arrive at
5155 * the CPU before the status block posted prior to the interrupt.
5156 * Reading the PCI State register will confirm whether the
5157 * interrupt is ours and will flush the status block.
5159 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5160 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5161 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5168 * Writing any value to intr-mbox-0 clears PCI INTA# and
5169 * chip-internal interrupt pending events.
5170 * Writing non-zero to intr-mbox-0 additional tells the
5171 * NIC to stop sending us irqs, engaging "in-intr-handler"
5174 * Flush the mailbox to de-assert the IRQ immediately to prevent
5175 * spurious interrupts. The flush impacts performance but
5176 * excessive spurious interrupts can be worse in some cases.
5178 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5179 if (tg3_irq_sync(tp))
5181 sblk->status &= ~SD_STATUS_UPDATED;
5182 if (likely(tg3_has_work(tnapi))) {
5183 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5184 napi_schedule(&tnapi->napi);
5186 /* No work, shared interrupt perhaps? re-enable
5187 * interrupts, and flush that PCI write
5189 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5193 return IRQ_RETVAL(handled);
5196 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5198 struct tg3_napi *tnapi = dev_id;
5199 struct tg3 *tp = tnapi->tp;
5200 struct tg3_hw_status *sblk = tnapi->hw_status;
5201 unsigned int handled = 1;
5203 /* In INTx mode, it is possible for the interrupt to arrive at
5204 * the CPU before the status block posted prior to the interrupt.
5205 * Reading the PCI State register will confirm whether the
5206 * interrupt is ours and will flush the status block.
5208 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5209 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5210 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5217 * writing any value to intr-mbox-0 clears PCI INTA# and
5218 * chip-internal interrupt pending events.
5219 * writing non-zero to intr-mbox-0 additional tells the
5220 * NIC to stop sending us irqs, engaging "in-intr-handler"
5223 * Flush the mailbox to de-assert the IRQ immediately to prevent
5224 * spurious interrupts. The flush impacts performance but
5225 * excessive spurious interrupts can be worse in some cases.
5227 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5230 * In a shared interrupt configuration, sometimes other devices'
5231 * interrupts will scream. We record the current status tag here
5232 * so that the above check can report that the screaming interrupts
5233 * are unhandled. Eventually they will be silenced.
5235 tnapi->last_irq_tag = sblk->status_tag;
5237 if (tg3_irq_sync(tp))
5240 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5242 napi_schedule(&tnapi->napi);
5245 return IRQ_RETVAL(handled);
5248 /* ISR for interrupt test */
5249 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5251 struct tg3_napi *tnapi = dev_id;
5252 struct tg3 *tp = tnapi->tp;
5253 struct tg3_hw_status *sblk = tnapi->hw_status;
5255 if ((sblk->status & SD_STATUS_UPDATED) ||
5256 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5257 tg3_disable_ints(tp);
5258 return IRQ_RETVAL(1);
5260 return IRQ_RETVAL(0);
5263 static int tg3_init_hw(struct tg3 *, int);
5264 static int tg3_halt(struct tg3 *, int, int);
5266 /* Restart hardware after configuration changes, self-test, etc.
5267 * Invoked with tp->lock held.
5269 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5270 __releases(tp->lock)
5271 __acquires(tp->lock)
5275 err = tg3_init_hw(tp, reset_phy);
5278 "Failed to re-initialize device, aborting\n");
5279 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5280 tg3_full_unlock(tp);
5281 del_timer_sync(&tp->timer);
5283 tg3_napi_enable(tp);
5285 tg3_full_lock(tp, 0);
5290 #ifdef CONFIG_NET_POLL_CONTROLLER
5291 static void tg3_poll_controller(struct net_device *dev)
5294 struct tg3 *tp = netdev_priv(dev);
5296 for (i = 0; i < tp->irq_cnt; i++)
5297 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5301 static void tg3_reset_task(struct work_struct *work)
5303 struct tg3 *tp = container_of(work, struct tg3, reset_task);
5305 unsigned int restart_timer;
5307 tg3_full_lock(tp, 0);
5309 if (!netif_running(tp->dev)) {
5310 tg3_full_unlock(tp);
5314 tg3_full_unlock(tp);
5320 tg3_full_lock(tp, 1);
5322 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5323 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5325 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5326 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5327 tp->write32_rx_mbox = tg3_write_flush_reg32;
5328 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5329 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5332 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5333 err = tg3_init_hw(tp, 1);
5337 tg3_netif_start(tp);
5340 mod_timer(&tp->timer, jiffies + 1);
5343 tg3_full_unlock(tp);
5349 static void tg3_dump_short_state(struct tg3 *tp)
5351 netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5352 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5353 netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5354 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5357 static void tg3_tx_timeout(struct net_device *dev)
5359 struct tg3 *tp = netdev_priv(dev);
5361 if (netif_msg_tx_err(tp)) {
5362 netdev_err(dev, "transmit timed out, resetting\n");
5363 tg3_dump_short_state(tp);
5366 schedule_work(&tp->reset_task);
5369 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5370 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5372 u32 base = (u32) mapping & 0xffffffff;
5374 return ((base > 0xffffdcc0) &&
5375 (base + len + 8 < base));
5378 /* Test for DMA addresses > 40-bit */
5379 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5382 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5383 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5384 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5391 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5393 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5394 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5395 struct sk_buff *skb, u32 last_plus_one,
5396 u32 *start, u32 base_flags, u32 mss)
5398 struct tg3 *tp = tnapi->tp;
5399 struct sk_buff *new_skb;
5400 dma_addr_t new_addr = 0;
5404 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5405 new_skb = skb_copy(skb, GFP_ATOMIC);
5407 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5409 new_skb = skb_copy_expand(skb,
5410 skb_headroom(skb) + more_headroom,
5411 skb_tailroom(skb), GFP_ATOMIC);
5417 /* New SKB is guaranteed to be linear. */
5419 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5421 /* Make sure the mapping succeeded */
5422 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5424 dev_kfree_skb(new_skb);
5427 /* Make sure new skb does not cross any 4G boundaries.
5428 * Drop the packet if it does.
5430 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5431 tg3_4g_overflow_test(new_addr, new_skb->len)) {
5432 pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5435 dev_kfree_skb(new_skb);
5438 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5439 base_flags, 1 | (mss << 1));
5440 *start = NEXT_TX(entry);
5444 /* Now clean up the sw ring entries. */
5446 while (entry != last_plus_one) {
5450 len = skb_headlen(skb);
5452 len = skb_shinfo(skb)->frags[i-1].size;
5454 pci_unmap_single(tp->pdev,
5455 pci_unmap_addr(&tnapi->tx_buffers[entry],
5457 len, PCI_DMA_TODEVICE);
5459 tnapi->tx_buffers[entry].skb = new_skb;
5460 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5463 tnapi->tx_buffers[entry].skb = NULL;
5465 entry = NEXT_TX(entry);
5474 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5475 dma_addr_t mapping, int len, u32 flags,
5478 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5479 int is_end = (mss_and_is_end & 0x1);
5480 u32 mss = (mss_and_is_end >> 1);
5484 flags |= TXD_FLAG_END;
5485 if (flags & TXD_FLAG_VLAN) {
5486 vlan_tag = flags >> 16;
5489 vlan_tag |= (mss << TXD_MSS_SHIFT);
5491 txd->addr_hi = ((u64) mapping >> 32);
5492 txd->addr_lo = ((u64) mapping & 0xffffffff);
5493 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5494 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5497 /* hard_start_xmit for devices that don't have any bugs and
5498 * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5500 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5501 struct net_device *dev)
5503 struct tg3 *tp = netdev_priv(dev);
5504 u32 len, entry, base_flags, mss;
5506 struct tg3_napi *tnapi;
5507 struct netdev_queue *txq;
5508 unsigned int i, last;
5510 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5511 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5512 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5515 /* We are running in BH disabled context with netif_tx_lock
5516 * and TX reclaim runs via tp->napi.poll inside of a software
5517 * interrupt. Furthermore, IRQ processing runs lockless so we have
5518 * no IRQ context deadlocks to worry about either. Rejoice!
5520 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5521 if (!netif_tx_queue_stopped(txq)) {
5522 netif_tx_stop_queue(txq);
5524 /* This is a hard error, log it. */
5526 "BUG! Tx Ring full when queue awake!\n");
5528 return NETDEV_TX_BUSY;
5531 entry = tnapi->tx_prod;
5534 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5535 int tcp_opt_len, ip_tcp_len;
5538 if (skb_header_cloned(skb) &&
5539 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5544 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5545 hdrlen = skb_headlen(skb) - ETH_HLEN;
5547 struct iphdr *iph = ip_hdr(skb);
5549 tcp_opt_len = tcp_optlen(skb);
5550 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5553 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5554 hdrlen = ip_tcp_len + tcp_opt_len;
5557 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5558 mss |= (hdrlen & 0xc) << 12;
5560 base_flags |= 0x00000010;
5561 base_flags |= (hdrlen & 0x3e0) << 5;
5565 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5566 TXD_FLAG_CPU_POST_DMA);
5568 tcp_hdr(skb)->check = 0;
5570 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5571 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5574 #if TG3_VLAN_TAG_USED
5575 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5576 base_flags |= (TXD_FLAG_VLAN |
5577 (vlan_tx_tag_get(skb) << 16));
5580 len = skb_headlen(skb);
5582 /* Queue skb data, a.k.a. the main skb fragment. */
5583 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5584 if (pci_dma_mapping_error(tp->pdev, mapping)) {
5589 tnapi->tx_buffers[entry].skb = skb;
5590 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5592 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5593 !mss && skb->len > ETH_DATA_LEN)
5594 base_flags |= TXD_FLAG_JMB_PKT;
5596 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5597 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5599 entry = NEXT_TX(entry);
5601 /* Now loop through additional data fragments, and queue them. */
5602 if (skb_shinfo(skb)->nr_frags > 0) {
5603 last = skb_shinfo(skb)->nr_frags - 1;
5604 for (i = 0; i <= last; i++) {
5605 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5608 mapping = pci_map_page(tp->pdev,
5611 len, PCI_DMA_TODEVICE);
5612 if (pci_dma_mapping_error(tp->pdev, mapping))
5615 tnapi->tx_buffers[entry].skb = NULL;
5616 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5619 tg3_set_txd(tnapi, entry, mapping, len,
5620 base_flags, (i == last) | (mss << 1));
5622 entry = NEXT_TX(entry);
5626 /* Packets are ready, update Tx producer idx local and on card. */
5627 tw32_tx_mbox(tnapi->prodmbox, entry);
5629 tnapi->tx_prod = entry;
5630 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5631 netif_tx_stop_queue(txq);
5632 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5633 netif_tx_wake_queue(txq);
5639 return NETDEV_TX_OK;
5643 entry = tnapi->tx_prod;
5644 tnapi->tx_buffers[entry].skb = NULL;
5645 pci_unmap_single(tp->pdev,
5646 pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5649 for (i = 0; i <= last; i++) {
5650 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5651 entry = NEXT_TX(entry);
5653 pci_unmap_page(tp->pdev,
5654 pci_unmap_addr(&tnapi->tx_buffers[entry],
5656 frag->size, PCI_DMA_TODEVICE);
5660 return NETDEV_TX_OK;
5663 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5664 struct net_device *);
5666 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5667 * TSO header is greater than 80 bytes.
5669 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5671 struct sk_buff *segs, *nskb;
5672 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5674 /* Estimate the number of fragments in the worst case */
5675 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5676 netif_stop_queue(tp->dev);
5677 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5678 return NETDEV_TX_BUSY;
5680 netif_wake_queue(tp->dev);
5683 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5685 goto tg3_tso_bug_end;
5691 tg3_start_xmit_dma_bug(nskb, tp->dev);
5697 return NETDEV_TX_OK;
5700 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5701 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5703 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5704 struct net_device *dev)
5706 struct tg3 *tp = netdev_priv(dev);
5707 u32 len, entry, base_flags, mss;
5708 int would_hit_hwbug;
5710 struct tg3_napi *tnapi;
5711 struct netdev_queue *txq;
5712 unsigned int i, last;
5714 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5715 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5716 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5719 /* We are running in BH disabled context with netif_tx_lock
5720 * and TX reclaim runs via tp->napi.poll inside of a software
5721 * interrupt. Furthermore, IRQ processing runs lockless so we have
5722 * no IRQ context deadlocks to worry about either. Rejoice!
5724 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5725 if (!netif_tx_queue_stopped(txq)) {
5726 netif_tx_stop_queue(txq);
5728 /* This is a hard error, log it. */
5730 "BUG! Tx Ring full when queue awake!\n");
5732 return NETDEV_TX_BUSY;
5735 entry = tnapi->tx_prod;
5737 if (skb->ip_summed == CHECKSUM_PARTIAL)
5738 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5740 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5742 u32 tcp_opt_len, ip_tcp_len, hdr_len;
5744 if (skb_header_cloned(skb) &&
5745 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5750 tcp_opt_len = tcp_optlen(skb);
5751 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5753 hdr_len = ip_tcp_len + tcp_opt_len;
5754 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5755 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5756 return (tg3_tso_bug(tp, skb));
5758 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5759 TXD_FLAG_CPU_POST_DMA);
5763 iph->tot_len = htons(mss + hdr_len);
5764 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5765 tcp_hdr(skb)->check = 0;
5766 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5768 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5773 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5774 mss |= (hdr_len & 0xc) << 12;
5776 base_flags |= 0x00000010;
5777 base_flags |= (hdr_len & 0x3e0) << 5;
5778 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5779 mss |= hdr_len << 9;
5780 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5781 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5782 if (tcp_opt_len || iph->ihl > 5) {
5785 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5786 mss |= (tsflags << 11);
5789 if (tcp_opt_len || iph->ihl > 5) {
5792 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5793 base_flags |= tsflags << 12;
5797 #if TG3_VLAN_TAG_USED
5798 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5799 base_flags |= (TXD_FLAG_VLAN |
5800 (vlan_tx_tag_get(skb) << 16));
5803 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5804 !mss && skb->len > ETH_DATA_LEN)
5805 base_flags |= TXD_FLAG_JMB_PKT;
5807 len = skb_headlen(skb);
5809 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5810 if (pci_dma_mapping_error(tp->pdev, mapping)) {
5815 tnapi->tx_buffers[entry].skb = skb;
5816 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5818 would_hit_hwbug = 0;
5820 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5821 would_hit_hwbug = 1;
5823 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5824 tg3_4g_overflow_test(mapping, len))
5825 would_hit_hwbug = 1;
5827 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5828 tg3_40bit_overflow_test(tp, mapping, len))
5829 would_hit_hwbug = 1;
5831 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5832 would_hit_hwbug = 1;
5834 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5835 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5837 entry = NEXT_TX(entry);
5839 /* Now loop through additional data fragments, and queue them. */
5840 if (skb_shinfo(skb)->nr_frags > 0) {
5841 last = skb_shinfo(skb)->nr_frags - 1;
5842 for (i = 0; i <= last; i++) {
5843 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5846 mapping = pci_map_page(tp->pdev,
5849 len, PCI_DMA_TODEVICE);
5851 tnapi->tx_buffers[entry].skb = NULL;
5852 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5854 if (pci_dma_mapping_error(tp->pdev, mapping))
5857 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5859 would_hit_hwbug = 1;
5861 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5862 tg3_4g_overflow_test(mapping, len))
5863 would_hit_hwbug = 1;
5865 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5866 tg3_40bit_overflow_test(tp, mapping, len))
5867 would_hit_hwbug = 1;
5869 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5870 tg3_set_txd(tnapi, entry, mapping, len,
5871 base_flags, (i == last)|(mss << 1));
5873 tg3_set_txd(tnapi, entry, mapping, len,
5874 base_flags, (i == last));
5876 entry = NEXT_TX(entry);
5880 if (would_hit_hwbug) {
5881 u32 last_plus_one = entry;
5884 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5885 start &= (TG3_TX_RING_SIZE - 1);
5887 /* If the workaround fails due to memory/mapping
5888 * failure, silently drop this packet.
5890 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
5891 &start, base_flags, mss))
5897 /* Packets are ready, update Tx producer idx local and on card. */
5898 tw32_tx_mbox(tnapi->prodmbox, entry);
5900 tnapi->tx_prod = entry;
5901 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5902 netif_tx_stop_queue(txq);
5903 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5904 netif_tx_wake_queue(txq);
5910 return NETDEV_TX_OK;
5914 entry = tnapi->tx_prod;
5915 tnapi->tx_buffers[entry].skb = NULL;
5916 pci_unmap_single(tp->pdev,
5917 pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5920 for (i = 0; i <= last; i++) {
5921 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5922 entry = NEXT_TX(entry);
5924 pci_unmap_page(tp->pdev,
5925 pci_unmap_addr(&tnapi->tx_buffers[entry],
5927 frag->size, PCI_DMA_TODEVICE);
5931 return NETDEV_TX_OK;
5934 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5939 if (new_mtu > ETH_DATA_LEN) {
5940 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5941 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5942 ethtool_op_set_tso(dev, 0);
5944 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5947 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5948 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5949 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5953 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5955 struct tg3 *tp = netdev_priv(dev);
5958 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5961 if (!netif_running(dev)) {
5962 /* We'll just catch it later when the
5965 tg3_set_mtu(dev, tp, new_mtu);
5973 tg3_full_lock(tp, 1);
5975 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5977 tg3_set_mtu(dev, tp, new_mtu);
5979 err = tg3_restart_hw(tp, 0);
5982 tg3_netif_start(tp);
5984 tg3_full_unlock(tp);
5992 static void tg3_rx_prodring_free(struct tg3 *tp,
5993 struct tg3_rx_prodring_set *tpr)
5997 if (tpr != &tp->prodring[0]) {
5998 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
5999 i = (i + 1) % TG3_RX_RING_SIZE)
6000 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6003 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6004 for (i = tpr->rx_jmb_cons_idx;
6005 i != tpr->rx_jmb_prod_idx;
6006 i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
6007 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6015 for (i = 0; i < TG3_RX_RING_SIZE; i++)
6016 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6019 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6020 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
6021 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6026 /* Initialize rx rings for packet processing.
6028 * The chip has been shut down and the driver detached from
6029 * the networking, so no interrupts or new tx packets will
6030 * end up in the driver. tp->{tx,}lock are held and thus
6033 static int tg3_rx_prodring_alloc(struct tg3 *tp,
6034 struct tg3_rx_prodring_set *tpr)
6036 u32 i, rx_pkt_dma_sz;
6038 tpr->rx_std_cons_idx = 0;
6039 tpr->rx_std_prod_idx = 0;
6040 tpr->rx_jmb_cons_idx = 0;
6041 tpr->rx_jmb_prod_idx = 0;
6043 if (tpr != &tp->prodring[0]) {
6044 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
6045 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
6046 memset(&tpr->rx_jmb_buffers[0], 0,
6047 TG3_RX_JMB_BUFF_RING_SIZE);
6051 /* Zero out all descriptors. */
6052 memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
6054 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6055 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
6056 tp->dev->mtu > ETH_DATA_LEN)
6057 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6058 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6060 /* Initialize invariants of the rings, we only set this
6061 * stuff once. This works because the card does not
6062 * write into the rx buffer posting rings.
6064 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
6065 struct tg3_rx_buffer_desc *rxd;
6067 rxd = &tpr->rx_std[i];
6068 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6069 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6070 rxd->opaque = (RXD_OPAQUE_RING_STD |
6071 (i << RXD_OPAQUE_INDEX_SHIFT));
6074 /* Now allocate fresh SKBs for each rx ring. */
6075 for (i = 0; i < tp->rx_pending; i++) {
6076 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6077 netdev_warn(tp->dev,
6078 "Using a smaller RX standard ring. Only "
6079 "%d out of %d buffers were allocated "
6080 "successfully\n", i, tp->rx_pending);
6088 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6091 memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
6093 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
6096 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
6097 struct tg3_rx_buffer_desc *rxd;
6099 rxd = &tpr->rx_jmb[i].std;
6100 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6101 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6103 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6104 (i << RXD_OPAQUE_INDEX_SHIFT));
6107 for (i = 0; i < tp->rx_jumbo_pending; i++) {
6108 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
6109 netdev_warn(tp->dev,
6110 "Using a smaller RX jumbo ring. Only %d "
6111 "out of %d buffers were allocated "
6112 "successfully\n", i, tp->rx_jumbo_pending);
6115 tp->rx_jumbo_pending = i;
6124 tg3_rx_prodring_free(tp, tpr);
6128 static void tg3_rx_prodring_fini(struct tg3 *tp,
6129 struct tg3_rx_prodring_set *tpr)
6131 kfree(tpr->rx_std_buffers);
6132 tpr->rx_std_buffers = NULL;
6133 kfree(tpr->rx_jmb_buffers);
6134 tpr->rx_jmb_buffers = NULL;
6136 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
6137 tpr->rx_std, tpr->rx_std_mapping);
6141 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
6142 tpr->rx_jmb, tpr->rx_jmb_mapping);
6147 static int tg3_rx_prodring_init(struct tg3 *tp,
6148 struct tg3_rx_prodring_set *tpr)
6150 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
6151 if (!tpr->rx_std_buffers)
6154 tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6155 &tpr->rx_std_mapping);
6159 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6160 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
6162 if (!tpr->rx_jmb_buffers)
6165 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6166 TG3_RX_JUMBO_RING_BYTES,
6167 &tpr->rx_jmb_mapping);
6175 tg3_rx_prodring_fini(tp, tpr);
6179 /* Free up pending packets in all rx/tx rings.
6181 * The chip has been shut down and the driver detached from
6182 * the networking, so no interrupts or new tx packets will
6183 * end up in the driver. tp->{tx,}lock is not held and we are not
6184 * in an interrupt context and thus may sleep.
6186 static void tg3_free_rings(struct tg3 *tp)
6190 for (j = 0; j < tp->irq_cnt; j++) {
6191 struct tg3_napi *tnapi = &tp->napi[j];
6193 if (!tnapi->tx_buffers)
6196 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6197 struct ring_info *txp;
6198 struct sk_buff *skb;
6201 txp = &tnapi->tx_buffers[i];
6209 pci_unmap_single(tp->pdev,
6210 pci_unmap_addr(txp, mapping),
6217 for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6218 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6219 pci_unmap_page(tp->pdev,
6220 pci_unmap_addr(txp, mapping),
6221 skb_shinfo(skb)->frags[k].size,
6226 dev_kfree_skb_any(skb);
6229 tg3_rx_prodring_free(tp, &tp->prodring[j]);
6233 /* Initialize tx/rx rings for packet processing.
6235 * The chip has been shut down and the driver detached from
6236 * the networking, so no interrupts or new tx packets will
6237 * end up in the driver. tp->{tx,}lock are held and thus
6240 static int tg3_init_rings(struct tg3 *tp)
6244 /* Free up all the SKBs. */
6247 for (i = 0; i < tp->irq_cnt; i++) {
6248 struct tg3_napi *tnapi = &tp->napi[i];
6250 tnapi->last_tag = 0;
6251 tnapi->last_irq_tag = 0;
6252 tnapi->hw_status->status = 0;
6253 tnapi->hw_status->status_tag = 0;
6254 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6259 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6261 tnapi->rx_rcb_ptr = 0;
6263 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6265 if (tg3_rx_prodring_alloc(tp, &tp->prodring[i])) {
6275 * Must not be invoked with interrupt sources disabled and
6276 * the hardware shutdown down.
6278 static void tg3_free_consistent(struct tg3 *tp)
6282 for (i = 0; i < tp->irq_cnt; i++) {
6283 struct tg3_napi *tnapi = &tp->napi[i];
6285 if (tnapi->tx_ring) {
6286 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6287 tnapi->tx_ring, tnapi->tx_desc_mapping);
6288 tnapi->tx_ring = NULL;
6291 kfree(tnapi->tx_buffers);
6292 tnapi->tx_buffers = NULL;
6294 if (tnapi->rx_rcb) {
6295 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6297 tnapi->rx_rcb_mapping);
6298 tnapi->rx_rcb = NULL;
6301 if (tnapi->hw_status) {
6302 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6304 tnapi->status_mapping);
6305 tnapi->hw_status = NULL;
6310 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6311 tp->hw_stats, tp->stats_mapping);
6312 tp->hw_stats = NULL;
6315 for (i = 0; i < tp->irq_cnt; i++)
6316 tg3_rx_prodring_fini(tp, &tp->prodring[i]);
6320 * Must not be invoked with interrupt sources disabled and
6321 * the hardware shutdown down. Can sleep.
6323 static int tg3_alloc_consistent(struct tg3 *tp)
6327 for (i = 0; i < tp->irq_cnt; i++) {
6328 if (tg3_rx_prodring_init(tp, &tp->prodring[i]))
6332 tp->hw_stats = pci_alloc_consistent(tp->pdev,
6333 sizeof(struct tg3_hw_stats),
6334 &tp->stats_mapping);
6338 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6340 for (i = 0; i < tp->irq_cnt; i++) {
6341 struct tg3_napi *tnapi = &tp->napi[i];
6342 struct tg3_hw_status *sblk;
6344 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6346 &tnapi->status_mapping);
6347 if (!tnapi->hw_status)
6350 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6351 sblk = tnapi->hw_status;
6353 /* If multivector TSS is enabled, vector 0 does not handle
6354 * tx interrupts. Don't allocate any resources for it.
6356 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6357 (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6358 tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6361 if (!tnapi->tx_buffers)
6364 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6366 &tnapi->tx_desc_mapping);
6367 if (!tnapi->tx_ring)
6372 * When RSS is enabled, the status block format changes
6373 * slightly. The "rx_jumbo_consumer", "reserved",
6374 * and "rx_mini_consumer" members get mapped to the
6375 * other three rx return ring producer indexes.
6379 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6382 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6385 tnapi->rx_rcb_prod_idx = &sblk->reserved;
6388 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6392 tnapi->prodring = &tp->prodring[i];
6395 * If multivector RSS is enabled, vector 0 does not handle
6396 * rx or tx interrupts. Don't allocate any resources for it.
6398 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6401 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6402 TG3_RX_RCB_RING_BYTES(tp),
6403 &tnapi->rx_rcb_mapping);
6407 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6413 tg3_free_consistent(tp);
6417 #define MAX_WAIT_CNT 1000
6419 /* To stop a block, clear the enable bit and poll till it
6420 * clears. tp->lock is held.
6422 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6427 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6434 /* We can't enable/disable these bits of the
6435 * 5705/5750, just say success.
6448 for (i = 0; i < MAX_WAIT_CNT; i++) {
6451 if ((val & enable_bit) == 0)
6455 if (i == MAX_WAIT_CNT && !silent) {
6456 dev_err(&tp->pdev->dev,
6457 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6465 /* tp->lock is held. */
6466 static int tg3_abort_hw(struct tg3 *tp, int silent)
6470 tg3_disable_ints(tp);
6472 tp->rx_mode &= ~RX_MODE_ENABLE;
6473 tw32_f(MAC_RX_MODE, tp->rx_mode);
6476 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6477 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6478 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6479 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6480 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6481 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6483 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6484 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6485 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6486 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6487 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6488 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6489 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6491 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6492 tw32_f(MAC_MODE, tp->mac_mode);
6495 tp->tx_mode &= ~TX_MODE_ENABLE;
6496 tw32_f(MAC_TX_MODE, tp->tx_mode);
6498 for (i = 0; i < MAX_WAIT_CNT; i++) {
6500 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6503 if (i >= MAX_WAIT_CNT) {
6504 dev_err(&tp->pdev->dev,
6505 "%s timed out, TX_MODE_ENABLE will not clear "
6506 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
6510 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6511 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6512 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6514 tw32(FTQ_RESET, 0xffffffff);
6515 tw32(FTQ_RESET, 0x00000000);
6517 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6518 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6520 for (i = 0; i < tp->irq_cnt; i++) {
6521 struct tg3_napi *tnapi = &tp->napi[i];
6522 if (tnapi->hw_status)
6523 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6526 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6531 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6536 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6537 if (apedata != APE_SEG_SIG_MAGIC)
6540 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6541 if (!(apedata & APE_FW_STATUS_READY))
6544 /* Wait for up to 1 millisecond for APE to service previous event. */
6545 for (i = 0; i < 10; i++) {
6546 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6549 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6551 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6552 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6553 event | APE_EVENT_STATUS_EVENT_PENDING);
6555 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6557 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6563 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6564 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6567 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6572 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6576 case RESET_KIND_INIT:
6577 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6578 APE_HOST_SEG_SIG_MAGIC);
6579 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6580 APE_HOST_SEG_LEN_MAGIC);
6581 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6582 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6583 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6584 APE_HOST_DRIVER_ID_MAGIC);
6585 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6586 APE_HOST_BEHAV_NO_PHYLOCK);
6588 event = APE_EVENT_STATUS_STATE_START;
6590 case RESET_KIND_SHUTDOWN:
6591 /* With the interface we are currently using,
6592 * APE does not track driver state. Wiping
6593 * out the HOST SEGMENT SIGNATURE forces
6594 * the APE to assume OS absent status.
6596 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6598 event = APE_EVENT_STATUS_STATE_UNLOAD;
6600 case RESET_KIND_SUSPEND:
6601 event = APE_EVENT_STATUS_STATE_SUSPEND;
6607 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6609 tg3_ape_send_event(tp, event);
6612 /* tp->lock is held. */
6613 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6615 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6616 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6618 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6620 case RESET_KIND_INIT:
6621 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6625 case RESET_KIND_SHUTDOWN:
6626 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6630 case RESET_KIND_SUSPEND:
6631 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6640 if (kind == RESET_KIND_INIT ||
6641 kind == RESET_KIND_SUSPEND)
6642 tg3_ape_driver_state_change(tp, kind);
6645 /* tp->lock is held. */
6646 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6648 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6650 case RESET_KIND_INIT:
6651 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6652 DRV_STATE_START_DONE);
6655 case RESET_KIND_SHUTDOWN:
6656 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6657 DRV_STATE_UNLOAD_DONE);
6665 if (kind == RESET_KIND_SHUTDOWN)
6666 tg3_ape_driver_state_change(tp, kind);
6669 /* tp->lock is held. */
6670 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6672 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6674 case RESET_KIND_INIT:
6675 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6679 case RESET_KIND_SHUTDOWN:
6680 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6684 case RESET_KIND_SUSPEND:
6685 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6695 static int tg3_poll_fw(struct tg3 *tp)
6700 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6701 /* Wait up to 20ms for init done. */
6702 for (i = 0; i < 200; i++) {
6703 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6710 /* Wait for firmware initialization to complete. */
6711 for (i = 0; i < 100000; i++) {
6712 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6713 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6718 /* Chip might not be fitted with firmware. Some Sun onboard
6719 * parts are configured like that. So don't signal the timeout
6720 * of the above loop as an error, but do report the lack of
6721 * running firmware once.
6724 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6725 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6727 netdev_info(tp->dev, "No firmware running\n");
6730 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6731 /* The 57765 A0 needs a little more
6732 * time to do some important work.
6740 /* Save PCI command register before chip reset */
6741 static void tg3_save_pci_state(struct tg3 *tp)
6743 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6746 /* Restore PCI state after chip reset */
6747 static void tg3_restore_pci_state(struct tg3 *tp)
6751 /* Re-enable indirect register accesses. */
6752 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6753 tp->misc_host_ctrl);
6755 /* Set MAX PCI retry to zero. */
6756 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6757 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6758 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6759 val |= PCISTATE_RETRY_SAME_DMA;
6760 /* Allow reads and writes to the APE register and memory space. */
6761 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6762 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6763 PCISTATE_ALLOW_APE_SHMEM_WR;
6764 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6766 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6768 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6769 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6770 pcie_set_readrq(tp->pdev, 4096);
6772 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6773 tp->pci_cacheline_sz);
6774 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6779 /* Make sure PCI-X relaxed ordering bit is clear. */
6780 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6783 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6785 pcix_cmd &= ~PCI_X_CMD_ERO;
6786 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6790 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6792 /* Chip reset on 5780 will reset MSI enable bit,
6793 * so need to restore it.
6795 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6798 pci_read_config_word(tp->pdev,
6799 tp->msi_cap + PCI_MSI_FLAGS,
6801 pci_write_config_word(tp->pdev,
6802 tp->msi_cap + PCI_MSI_FLAGS,
6803 ctrl | PCI_MSI_FLAGS_ENABLE);
6804 val = tr32(MSGINT_MODE);
6805 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6810 static void tg3_stop_fw(struct tg3 *);
6812 /* tp->lock is held. */
6813 static int tg3_chip_reset(struct tg3 *tp)
6816 void (*write_op)(struct tg3 *, u32, u32);
6821 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6823 /* No matching tg3_nvram_unlock() after this because
6824 * chip reset below will undo the nvram lock.
6826 tp->nvram_lock_cnt = 0;
6828 /* GRC_MISC_CFG core clock reset will clear the memory
6829 * enable bit in PCI register 4 and the MSI enable bit
6830 * on some chips, so we save relevant registers here.
6832 tg3_save_pci_state(tp);
6834 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6835 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6836 tw32(GRC_FASTBOOT_PC, 0);
6839 * We must avoid the readl() that normally takes place.
6840 * It locks machines, causes machine checks, and other
6841 * fun things. So, temporarily disable the 5701
6842 * hardware workaround, while we do the reset.
6844 write_op = tp->write32;
6845 if (write_op == tg3_write_flush_reg32)
6846 tp->write32 = tg3_write32;
6848 /* Prevent the irq handler from reading or writing PCI registers
6849 * during chip reset when the memory enable bit in the PCI command
6850 * register may be cleared. The chip does not generate interrupt
6851 * at this time, but the irq handler may still be called due to irq
6852 * sharing or irqpoll.
6854 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6855 for (i = 0; i < tp->irq_cnt; i++) {
6856 struct tg3_napi *tnapi = &tp->napi[i];
6857 if (tnapi->hw_status) {
6858 tnapi->hw_status->status = 0;
6859 tnapi->hw_status->status_tag = 0;
6861 tnapi->last_tag = 0;
6862 tnapi->last_irq_tag = 0;
6866 for (i = 0; i < tp->irq_cnt; i++)
6867 synchronize_irq(tp->napi[i].irq_vec);
6869 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6870 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6871 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6875 val = GRC_MISC_CFG_CORECLK_RESET;
6877 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6878 if (tr32(0x7e2c) == 0x60) {
6881 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6882 tw32(GRC_MISC_CFG, (1 << 29));
6887 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6888 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6889 tw32(GRC_VCPU_EXT_CTRL,
6890 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6893 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6894 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6895 tw32(GRC_MISC_CFG, val);
6897 /* restore 5701 hardware bug workaround write method */
6898 tp->write32 = write_op;
6900 /* Unfortunately, we have to delay before the PCI read back.
6901 * Some 575X chips even will not respond to a PCI cfg access
6902 * when the reset command is given to the chip.
6904 * How do these hardware designers expect things to work
6905 * properly if the PCI write is posted for a long period
6906 * of time? It is always necessary to have some method by
6907 * which a register read back can occur to push the write
6908 * out which does the reset.
6910 * For most tg3 variants the trick below was working.
6915 /* Flush PCI posted writes. The normal MMIO registers
6916 * are inaccessible at this time so this is the only
6917 * way to make this reliably (actually, this is no longer
6918 * the case, see above). I tried to use indirect
6919 * register read/write but this upset some 5701 variants.
6921 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6925 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6928 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6932 /* Wait for link training to complete. */
6933 for (i = 0; i < 5000; i++)
6936 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6937 pci_write_config_dword(tp->pdev, 0xc4,
6938 cfg_val | (1 << 15));
6941 /* Clear the "no snoop" and "relaxed ordering" bits. */
6942 pci_read_config_word(tp->pdev,
6943 tp->pcie_cap + PCI_EXP_DEVCTL,
6945 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6946 PCI_EXP_DEVCTL_NOSNOOP_EN);
6948 * Older PCIe devices only support the 128 byte
6949 * MPS setting. Enforce the restriction.
6951 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6952 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6953 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
6954 pci_write_config_word(tp->pdev,
6955 tp->pcie_cap + PCI_EXP_DEVCTL,
6958 pcie_set_readrq(tp->pdev, 4096);
6960 /* Clear error status */
6961 pci_write_config_word(tp->pdev,
6962 tp->pcie_cap + PCI_EXP_DEVSTA,
6963 PCI_EXP_DEVSTA_CED |
6964 PCI_EXP_DEVSTA_NFED |
6965 PCI_EXP_DEVSTA_FED |
6966 PCI_EXP_DEVSTA_URD);
6969 tg3_restore_pci_state(tp);
6971 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6974 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6975 val = tr32(MEMARB_MODE);
6976 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6978 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6980 tw32(0x5000, 0x400);
6983 tw32(GRC_MODE, tp->grc_mode);
6985 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6988 tw32(0xc4, val | (1 << 15));
6991 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6992 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6993 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6994 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6995 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6996 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6999 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7000 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
7001 tw32_f(MAC_MODE, tp->mac_mode);
7002 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7003 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
7004 tw32_f(MAC_MODE, tp->mac_mode);
7005 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7006 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
7007 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
7008 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
7009 tw32_f(MAC_MODE, tp->mac_mode);
7011 tw32_f(MAC_MODE, 0);
7014 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7016 err = tg3_poll_fw(tp);
7022 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7025 phy_addr = tp->phy_addr;
7026 tp->phy_addr = TG3_PHY_PCIE_ADDR;
7028 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
7029 TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
7030 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
7031 TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
7032 TG3_PCIEPHY_TX0CTRL1_NB_EN;
7033 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
7036 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
7037 TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
7038 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
7039 TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
7040 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
7043 tp->phy_addr = phy_addr;
7046 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
7047 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7048 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7049 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
7050 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
7053 tw32(0x7c00, val | (1 << 25));
7056 /* Reprobe ASF enable state. */
7057 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7058 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7059 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7060 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7063 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7064 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7065 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7066 tp->last_event_jiffies = jiffies;
7067 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7068 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7075 /* tp->lock is held. */
7076 static void tg3_stop_fw(struct tg3 *tp)
7078 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7079 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7080 /* Wait for RX cpu to ACK the previous event. */
7081 tg3_wait_for_event_ack(tp);
7083 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7085 tg3_generate_fw_event(tp);
7087 /* Wait for RX cpu to ACK this event. */
7088 tg3_wait_for_event_ack(tp);
7092 /* tp->lock is held. */
7093 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7099 tg3_write_sig_pre_reset(tp, kind);
7101 tg3_abort_hw(tp, silent);
7102 err = tg3_chip_reset(tp);
7104 __tg3_set_mac_addr(tp, 0);
7106 tg3_write_sig_legacy(tp, kind);
7107 tg3_write_sig_post_reset(tp, kind);
7115 #define RX_CPU_SCRATCH_BASE 0x30000
7116 #define RX_CPU_SCRATCH_SIZE 0x04000
7117 #define TX_CPU_SCRATCH_BASE 0x34000
7118 #define TX_CPU_SCRATCH_SIZE 0x04000
7120 /* tp->lock is held. */
7121 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7125 BUG_ON(offset == TX_CPU_BASE &&
7126 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7128 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7129 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7131 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7134 if (offset == RX_CPU_BASE) {
7135 for (i = 0; i < 10000; i++) {
7136 tw32(offset + CPU_STATE, 0xffffffff);
7137 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7138 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7142 tw32(offset + CPU_STATE, 0xffffffff);
7143 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
7146 for (i = 0; i < 10000; i++) {
7147 tw32(offset + CPU_STATE, 0xffffffff);
7148 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7149 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7155 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7156 __func__, offset == RX_CPU_BASE ? "RX" : "TX");
7160 /* Clear firmware's nvram arbitration. */
7161 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7162 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7167 unsigned int fw_base;
7168 unsigned int fw_len;
7169 const __be32 *fw_data;
7172 /* tp->lock is held. */
7173 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7174 int cpu_scratch_size, struct fw_info *info)
7176 int err, lock_err, i;
7177 void (*write_op)(struct tg3 *, u32, u32);
7179 if (cpu_base == TX_CPU_BASE &&
7180 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7182 "%s: Trying to load TX cpu firmware which is 5705\n",
7187 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7188 write_op = tg3_write_mem;
7190 write_op = tg3_write_indirect_reg32;
7192 /* It is possible that bootcode is still loading at this point.
7193 * Get the nvram lock first before halting the cpu.
7195 lock_err = tg3_nvram_lock(tp);
7196 err = tg3_halt_cpu(tp, cpu_base);
7198 tg3_nvram_unlock(tp);
7202 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7203 write_op(tp, cpu_scratch_base + i, 0);
7204 tw32(cpu_base + CPU_STATE, 0xffffffff);
7205 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7206 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7207 write_op(tp, (cpu_scratch_base +
7208 (info->fw_base & 0xffff) +
7210 be32_to_cpu(info->fw_data[i]));
7218 /* tp->lock is held. */
7219 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7221 struct fw_info info;
7222 const __be32 *fw_data;
7225 fw_data = (void *)tp->fw->data;
7227 /* Firmware blob starts with version numbers, followed by
7228 start address and length. We are setting complete length.
7229 length = end_address_of_bss - start_address_of_text.
7230 Remainder is the blob to be loaded contiguously
7231 from start address. */
7233 info.fw_base = be32_to_cpu(fw_data[1]);
7234 info.fw_len = tp->fw->size - 12;
7235 info.fw_data = &fw_data[3];
7237 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7238 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7243 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7244 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7249 /* Now startup only the RX cpu. */
7250 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7251 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7253 for (i = 0; i < 5; i++) {
7254 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7256 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7257 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
7258 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7262 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7263 "should be %08x\n", __func__,
7264 tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
7267 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7268 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
7273 /* 5705 needs a special version of the TSO firmware. */
7275 /* tp->lock is held. */
7276 static int tg3_load_tso_firmware(struct tg3 *tp)
7278 struct fw_info info;
7279 const __be32 *fw_data;
7280 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7283 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7286 fw_data = (void *)tp->fw->data;
7288 /* Firmware blob starts with version numbers, followed by
7289 start address and length. We are setting complete length.
7290 length = end_address_of_bss - start_address_of_text.
7291 Remainder is the blob to be loaded contiguously
7292 from start address. */
7294 info.fw_base = be32_to_cpu(fw_data[1]);
7295 cpu_scratch_size = tp->fw_len;
7296 info.fw_len = tp->fw->size - 12;
7297 info.fw_data = &fw_data[3];
7299 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7300 cpu_base = RX_CPU_BASE;
7301 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7303 cpu_base = TX_CPU_BASE;
7304 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7305 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7308 err = tg3_load_firmware_cpu(tp, cpu_base,
7309 cpu_scratch_base, cpu_scratch_size,
7314 /* Now startup the cpu. */
7315 tw32(cpu_base + CPU_STATE, 0xffffffff);
7316 tw32_f(cpu_base + CPU_PC, info.fw_base);
7318 for (i = 0; i < 5; i++) {
7319 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7321 tw32(cpu_base + CPU_STATE, 0xffffffff);
7322 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
7323 tw32_f(cpu_base + CPU_PC, info.fw_base);
7328 "%s fails to set CPU PC, is %08x should be %08x\n",
7329 __func__, tr32(cpu_base + CPU_PC), info.fw_base);
7332 tw32(cpu_base + CPU_STATE, 0xffffffff);
7333 tw32_f(cpu_base + CPU_MODE, 0x00000000);
7338 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7340 struct tg3 *tp = netdev_priv(dev);
7341 struct sockaddr *addr = p;
7342 int err = 0, skip_mac_1 = 0;
7344 if (!is_valid_ether_addr(addr->sa_data))
7347 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7349 if (!netif_running(dev))
7352 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7353 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7355 addr0_high = tr32(MAC_ADDR_0_HIGH);
7356 addr0_low = tr32(MAC_ADDR_0_LOW);
7357 addr1_high = tr32(MAC_ADDR_1_HIGH);
7358 addr1_low = tr32(MAC_ADDR_1_LOW);
7360 /* Skip MAC addr 1 if ASF is using it. */
7361 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7362 !(addr1_high == 0 && addr1_low == 0))
7365 spin_lock_bh(&tp->lock);
7366 __tg3_set_mac_addr(tp, skip_mac_1);
7367 spin_unlock_bh(&tp->lock);
7372 /* tp->lock is held. */
7373 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7374 dma_addr_t mapping, u32 maxlen_flags,
7378 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7379 ((u64) mapping >> 32));
7381 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7382 ((u64) mapping & 0xffffffff));
7384 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7387 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7389 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7393 static void __tg3_set_rx_mode(struct net_device *);
7394 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7398 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7399 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7400 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7401 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7403 tw32(HOSTCC_TXCOL_TICKS, 0);
7404 tw32(HOSTCC_TXMAX_FRAMES, 0);
7405 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7408 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7409 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7410 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7411 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7413 tw32(HOSTCC_RXCOL_TICKS, 0);
7414 tw32(HOSTCC_RXMAX_FRAMES, 0);
7415 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7418 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7419 u32 val = ec->stats_block_coalesce_usecs;
7421 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7422 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7424 if (!netif_carrier_ok(tp->dev))
7427 tw32(HOSTCC_STAT_COAL_TICKS, val);
7430 for (i = 0; i < tp->irq_cnt - 1; i++) {
7433 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7434 tw32(reg, ec->rx_coalesce_usecs);
7435 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7436 tw32(reg, ec->rx_max_coalesced_frames);
7437 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7438 tw32(reg, ec->rx_max_coalesced_frames_irq);
7440 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7441 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7442 tw32(reg, ec->tx_coalesce_usecs);
7443 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7444 tw32(reg, ec->tx_max_coalesced_frames);
7445 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7446 tw32(reg, ec->tx_max_coalesced_frames_irq);
7450 for (; i < tp->irq_max - 1; i++) {
7451 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7452 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7453 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7455 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7456 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7457 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7458 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7463 /* tp->lock is held. */
7464 static void tg3_rings_reset(struct tg3 *tp)
7467 u32 stblk, txrcb, rxrcb, limit;
7468 struct tg3_napi *tnapi = &tp->napi[0];
7470 /* Disable all transmit rings but the first. */
7471 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7472 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7473 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7474 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7476 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7478 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7479 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7480 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7481 BDINFO_FLAGS_DISABLED);
7484 /* Disable all receive return rings but the first. */
7485 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7486 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7487 else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7488 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7489 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7490 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7491 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7493 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7495 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7496 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7497 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7498 BDINFO_FLAGS_DISABLED);
7500 /* Disable interrupts */
7501 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7503 /* Zero mailbox registers. */
7504 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7505 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7506 tp->napi[i].tx_prod = 0;
7507 tp->napi[i].tx_cons = 0;
7508 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7509 tw32_mailbox(tp->napi[i].prodmbox, 0);
7510 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7511 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7513 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7514 tw32_mailbox(tp->napi[0].prodmbox, 0);
7516 tp->napi[0].tx_prod = 0;
7517 tp->napi[0].tx_cons = 0;
7518 tw32_mailbox(tp->napi[0].prodmbox, 0);
7519 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7522 /* Make sure the NIC-based send BD rings are disabled. */
7523 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7524 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7525 for (i = 0; i < 16; i++)
7526 tw32_tx_mbox(mbox + i * 8, 0);
7529 txrcb = NIC_SRAM_SEND_RCB;
7530 rxrcb = NIC_SRAM_RCV_RET_RCB;
7532 /* Clear status block in ram. */
7533 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7535 /* Set status block DMA address */
7536 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7537 ((u64) tnapi->status_mapping >> 32));
7538 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7539 ((u64) tnapi->status_mapping & 0xffffffff));
7541 if (tnapi->tx_ring) {
7542 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7543 (TG3_TX_RING_SIZE <<
7544 BDINFO_FLAGS_MAXLEN_SHIFT),
7545 NIC_SRAM_TX_BUFFER_DESC);
7546 txrcb += TG3_BDINFO_SIZE;
7549 if (tnapi->rx_rcb) {
7550 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7551 (TG3_RX_RCB_RING_SIZE(tp) <<
7552 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7553 rxrcb += TG3_BDINFO_SIZE;
7556 stblk = HOSTCC_STATBLCK_RING1;
7558 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7559 u64 mapping = (u64)tnapi->status_mapping;
7560 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7561 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7563 /* Clear status block in ram. */
7564 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7566 if (tnapi->tx_ring) {
7567 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7568 (TG3_TX_RING_SIZE <<
7569 BDINFO_FLAGS_MAXLEN_SHIFT),
7570 NIC_SRAM_TX_BUFFER_DESC);
7571 txrcb += TG3_BDINFO_SIZE;
7574 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7575 (TG3_RX_RCB_RING_SIZE(tp) <<
7576 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7579 rxrcb += TG3_BDINFO_SIZE;
7583 /* tp->lock is held. */
7584 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7586 u32 val, rdmac_mode;
7588 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
7590 tg3_disable_ints(tp);
7594 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7596 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
7597 tg3_abort_hw(tp, 1);
7602 err = tg3_chip_reset(tp);
7606 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7608 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7609 val = tr32(TG3_CPMU_CTRL);
7610 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7611 tw32(TG3_CPMU_CTRL, val);
7613 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7614 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7615 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7616 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7618 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7619 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7620 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7621 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7623 val = tr32(TG3_CPMU_HST_ACC);
7624 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7625 val |= CPMU_HST_ACC_MACCLK_6_25;
7626 tw32(TG3_CPMU_HST_ACC, val);
7629 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7630 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7631 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7632 PCIE_PWR_MGMT_L1_THRESH_4MS;
7633 tw32(PCIE_PWR_MGMT_THRESH, val);
7635 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7636 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7638 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7640 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7641 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7644 if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7645 u32 grc_mode = tr32(GRC_MODE);
7647 /* Access the lower 1K of PL PCIE block registers. */
7648 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7649 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7651 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7652 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7653 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7655 tw32(GRC_MODE, grc_mode);
7658 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
7659 u32 grc_mode = tr32(GRC_MODE);
7661 /* Access the lower 1K of PL PCIE block registers. */
7662 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7663 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7665 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5);
7666 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
7667 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
7669 tw32(GRC_MODE, grc_mode);
7671 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7672 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7673 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7674 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7677 /* This works around an issue with Athlon chipsets on
7678 * B3 tigon3 silicon. This bit has no effect on any
7679 * other revision. But do not set this on PCI Express
7680 * chips and don't even touch the clocks if the CPMU is present.
7682 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7683 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7684 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7685 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7688 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7689 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7690 val = tr32(TG3PCI_PCISTATE);
7691 val |= PCISTATE_RETRY_SAME_DMA;
7692 tw32(TG3PCI_PCISTATE, val);
7695 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7696 /* Allow reads and writes to the
7697 * APE register and memory space.
7699 val = tr32(TG3PCI_PCISTATE);
7700 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7701 PCISTATE_ALLOW_APE_SHMEM_WR;
7702 tw32(TG3PCI_PCISTATE, val);
7705 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7706 /* Enable some hw fixes. */
7707 val = tr32(TG3PCI_MSI_DATA);
7708 val |= (1 << 26) | (1 << 28) | (1 << 29);
7709 tw32(TG3PCI_MSI_DATA, val);
7712 /* Descriptor ring init may make accesses to the
7713 * NIC SRAM area to setup the TX descriptors, so we
7714 * can only do this after the hardware has been
7715 * successfully reset.
7717 err = tg3_init_rings(tp);
7721 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7722 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7723 val = tr32(TG3PCI_DMA_RW_CTRL) &
7724 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7725 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
7726 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
7727 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7728 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7729 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7730 /* This value is determined during the probe time DMA
7731 * engine test, tg3_test_dma.
7733 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7736 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7737 GRC_MODE_4X_NIC_SEND_RINGS |
7738 GRC_MODE_NO_TX_PHDR_CSUM |
7739 GRC_MODE_NO_RX_PHDR_CSUM);
7740 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7742 /* Pseudo-header checksum is done by hardware logic and not
7743 * the offload processers, so make the chip do the pseudo-
7744 * header checksums on receive. For transmit it is more
7745 * convenient to do the pseudo-header checksum in software
7746 * as Linux does that on transmit for us in all cases.
7748 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7752 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7754 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7755 val = tr32(GRC_MISC_CFG);
7757 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7758 tw32(GRC_MISC_CFG, val);
7760 /* Initialize MBUF/DESC pool. */
7761 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7763 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7764 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7765 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7766 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7768 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7769 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7770 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7771 } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7774 fw_len = tp->fw_len;
7775 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7776 tw32(BUFMGR_MB_POOL_ADDR,
7777 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7778 tw32(BUFMGR_MB_POOL_SIZE,
7779 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7782 if (tp->dev->mtu <= ETH_DATA_LEN) {
7783 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7784 tp->bufmgr_config.mbuf_read_dma_low_water);
7785 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7786 tp->bufmgr_config.mbuf_mac_rx_low_water);
7787 tw32(BUFMGR_MB_HIGH_WATER,
7788 tp->bufmgr_config.mbuf_high_water);
7790 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7791 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7792 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7793 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7794 tw32(BUFMGR_MB_HIGH_WATER,
7795 tp->bufmgr_config.mbuf_high_water_jumbo);
7797 tw32(BUFMGR_DMA_LOW_WATER,
7798 tp->bufmgr_config.dma_low_water);
7799 tw32(BUFMGR_DMA_HIGH_WATER,
7800 tp->bufmgr_config.dma_high_water);
7802 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7803 for (i = 0; i < 2000; i++) {
7804 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7809 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
7813 /* Setup replenish threshold. */
7814 val = tp->rx_pending / 8;
7817 else if (val > tp->rx_std_max_post)
7818 val = tp->rx_std_max_post;
7819 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7820 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7821 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7823 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7824 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7827 tw32(RCVBDI_STD_THRESH, val);
7829 /* Initialize TG3_BDINFO's at:
7830 * RCVDBDI_STD_BD: standard eth size rx ring
7831 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7832 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7835 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7836 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7837 * ring attribute flags
7838 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7840 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7841 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7843 * The size of each ring is fixed in the firmware, but the location is
7846 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7847 ((u64) tpr->rx_std_mapping >> 32));
7848 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7849 ((u64) tpr->rx_std_mapping & 0xffffffff));
7850 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
7851 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7852 NIC_SRAM_RX_BUFFER_DESC);
7854 /* Disable the mini ring */
7855 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7856 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7857 BDINFO_FLAGS_DISABLED);
7859 /* Program the jumbo buffer descriptor ring control
7860 * blocks on those devices that have them.
7862 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7863 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7864 /* Setup replenish threshold. */
7865 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7867 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7868 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7869 ((u64) tpr->rx_jmb_mapping >> 32));
7870 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7871 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7872 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7873 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7874 BDINFO_FLAGS_USE_EXT_RECV);
7875 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
7876 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7877 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7879 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7880 BDINFO_FLAGS_DISABLED);
7883 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7884 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7885 val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7886 (RX_STD_MAX_SIZE << 2);
7888 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
7890 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7892 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7894 tpr->rx_std_prod_idx = tp->rx_pending;
7895 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
7897 tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7898 tp->rx_jumbo_pending : 0;
7899 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
7901 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7902 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7903 tw32(STD_REPLENISH_LWM, 32);
7904 tw32(JMB_REPLENISH_LWM, 16);
7907 tg3_rings_reset(tp);
7909 /* Initialize MAC address and backoff seed. */
7910 __tg3_set_mac_addr(tp, 0);
7912 /* MTU + ethernet header + FCS + optional VLAN tag */
7913 tw32(MAC_RX_MTU_SIZE,
7914 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7916 /* The slot time is changed by tg3_setup_phy if we
7917 * run at gigabit with half duplex.
7919 tw32(MAC_TX_LENGTHS,
7920 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7921 (6 << TX_LENGTHS_IPG_SHIFT) |
7922 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7924 /* Receive rules. */
7925 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7926 tw32(RCVLPC_CONFIG, 0x0181);
7928 /* Calculate RDMAC_MODE setting early, we need it to determine
7929 * the RCVLPC_STATE_ENABLE mask.
7931 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7932 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7933 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7934 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7935 RDMAC_MODE_LNGREAD_ENAB);
7937 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7938 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
7940 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7941 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7942 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7943 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7944 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7945 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7947 /* If statement applies to 5705 and 5750 PCI devices only */
7948 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7949 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7950 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7951 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7952 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7953 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7954 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7955 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7956 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7960 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7961 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7963 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7964 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7966 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
7967 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7968 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7969 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7971 /* Receive/send statistics. */
7972 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7973 val = tr32(RCVLPC_STATS_ENABLE);
7974 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7975 tw32(RCVLPC_STATS_ENABLE, val);
7976 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7977 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7978 val = tr32(RCVLPC_STATS_ENABLE);
7979 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7980 tw32(RCVLPC_STATS_ENABLE, val);
7982 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7984 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7985 tw32(SNDDATAI_STATSENAB, 0xffffff);
7986 tw32(SNDDATAI_STATSCTRL,
7987 (SNDDATAI_SCTRL_ENABLE |
7988 SNDDATAI_SCTRL_FASTUPD));
7990 /* Setup host coalescing engine. */
7991 tw32(HOSTCC_MODE, 0);
7992 for (i = 0; i < 2000; i++) {
7993 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7998 __tg3_set_coalesce(tp, &tp->coal);
8000 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8001 /* Status/statistics block address. See tg3_timer,
8002 * the tg3_periodic_fetch_stats call there, and
8003 * tg3_get_stats to see how this works for 5705/5750 chips.
8005 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8006 ((u64) tp->stats_mapping >> 32));
8007 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8008 ((u64) tp->stats_mapping & 0xffffffff));
8009 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8011 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
8013 /* Clear statistics and status block memory areas */
8014 for (i = NIC_SRAM_STATS_BLK;
8015 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8017 tg3_write_mem(tp, i, 0);
8022 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8024 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8025 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8026 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8027 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8029 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8030 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
8031 /* reset to prevent losing 1st rx packet intermittently */
8032 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8036 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8037 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8040 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8041 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
8042 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8043 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8044 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8045 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8046 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8049 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8050 * If TG3_FLG2_IS_NIC is zero, we should read the
8051 * register to preserve the GPIO settings for LOMs. The GPIOs,
8052 * whether used as inputs or outputs, are set by boot code after
8055 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
8058 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8059 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8060 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8062 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8063 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8064 GRC_LCLCTRL_GPIO_OUTPUT3;
8066 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8067 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8069 tp->grc_local_ctrl &= ~gpio_mask;
8070 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8072 /* GPIO1 must be driven high for eeprom write protect */
8073 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8074 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8075 GRC_LCLCTRL_GPIO_OUTPUT1);
8077 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8080 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
8081 val = tr32(MSGINT_MODE);
8082 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8083 tw32(MSGINT_MODE, val);
8086 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8087 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8091 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8092 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8093 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8094 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8095 WDMAC_MODE_LNGREAD_ENAB);
8097 /* If statement applies to 5705 and 5750 PCI devices only */
8098 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8099 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8100 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
8101 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8102 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8103 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8105 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8106 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8107 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8108 val |= WDMAC_MODE_RX_ACCEL;
8112 /* Enable host coalescing bug fix */
8113 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8114 val |= WDMAC_MODE_STATUS_TAG_FIX;
8116 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8117 val |= WDMAC_MODE_BURST_ALL_DATA;
8119 tw32_f(WDMAC_MODE, val);
8122 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8125 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8127 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8128 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8129 pcix_cmd |= PCI_X_CMD_READ_2K;
8130 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8131 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8132 pcix_cmd |= PCI_X_CMD_READ_2K;
8134 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8138 tw32_f(RDMAC_MODE, rdmac_mode);
8141 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8142 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8143 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8145 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8147 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8149 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8151 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8152 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8153 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8154 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8155 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8156 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8157 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8158 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8159 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8160 tw32(SNDBDI_MODE, val);
8161 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8163 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8164 err = tg3_load_5701_a0_firmware_fix(tp);
8169 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8170 err = tg3_load_tso_firmware(tp);
8175 tp->tx_mode = TX_MODE_ENABLE;
8176 tw32_f(MAC_TX_MODE, tp->tx_mode);
8179 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8180 u32 reg = MAC_RSS_INDIR_TBL_0;
8181 u8 *ent = (u8 *)&val;
8183 /* Setup the indirection table */
8184 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8185 int idx = i % sizeof(val);
8187 ent[idx] = i % (tp->irq_cnt - 1);
8188 if (idx == sizeof(val) - 1) {
8194 /* Setup the "secret" hash key. */
8195 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8196 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8197 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8198 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8199 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8200 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8201 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8202 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8203 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8204 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8207 tp->rx_mode = RX_MODE_ENABLE;
8208 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8209 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8211 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8212 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8213 RX_MODE_RSS_ITBL_HASH_BITS_7 |
8214 RX_MODE_RSS_IPV6_HASH_EN |
8215 RX_MODE_RSS_TCP_IPV6_HASH_EN |
8216 RX_MODE_RSS_IPV4_HASH_EN |
8217 RX_MODE_RSS_TCP_IPV4_HASH_EN;
8219 tw32_f(MAC_RX_MODE, tp->rx_mode);
8222 tw32(MAC_LED_CTRL, tp->led_ctrl);
8224 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8225 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8226 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8229 tw32_f(MAC_RX_MODE, tp->rx_mode);
8232 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8233 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8234 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
8235 /* Set drive transmission level to 1.2V */
8236 /* only if the signal pre-emphasis bit is not set */
8237 val = tr32(MAC_SERDES_CFG);
8240 tw32(MAC_SERDES_CFG, val);
8242 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8243 tw32(MAC_SERDES_CFG, 0x616000);
8246 /* Prevent chip from dropping frames when flow control
8249 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8253 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8255 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8256 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8257 /* Use hardware link auto-negotiation */
8258 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8261 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8262 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8265 tmp = tr32(SERDES_RX_CTRL);
8266 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8267 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8268 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8269 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8272 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8273 if (tp->link_config.phy_is_low_power) {
8274 tp->link_config.phy_is_low_power = 0;
8275 tp->link_config.speed = tp->link_config.orig_speed;
8276 tp->link_config.duplex = tp->link_config.orig_duplex;
8277 tp->link_config.autoneg = tp->link_config.orig_autoneg;
8280 err = tg3_setup_phy(tp, 0);
8284 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8285 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
8288 /* Clear CRC stats. */
8289 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8290 tg3_writephy(tp, MII_TG3_TEST1,
8291 tmp | MII_TG3_TEST1_CRC_EN);
8292 tg3_readphy(tp, 0x14, &tmp);
8297 __tg3_set_rx_mode(tp->dev);
8299 /* Initialize receive rules. */
8300 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
8301 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8302 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
8303 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8305 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8306 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8310 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8314 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
8316 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
8318 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
8320 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
8322 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
8324 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
8326 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
8328 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
8330 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
8332 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
8334 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
8336 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
8338 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
8340 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
8348 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8349 /* Write our heartbeat update interval to APE. */
8350 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8351 APE_HOST_HEARTBEAT_INT_DISABLE);
8353 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8358 /* Called at device open time to get the chip ready for
8359 * packet processing. Invoked with tp->lock held.
8361 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8363 tg3_switch_clocks(tp);
8365 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8367 return tg3_reset_hw(tp, reset_phy);
8370 #define TG3_STAT_ADD32(PSTAT, REG) \
8371 do { u32 __val = tr32(REG); \
8372 (PSTAT)->low += __val; \
8373 if ((PSTAT)->low < __val) \
8374 (PSTAT)->high += 1; \
8377 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8379 struct tg3_hw_stats *sp = tp->hw_stats;
8381 if (!netif_carrier_ok(tp->dev))
8384 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8385 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8386 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8387 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8388 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8389 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8390 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8391 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8392 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8393 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8394 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8395 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8396 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8398 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8399 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8400 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8401 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8402 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8403 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8404 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8405 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8406 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8407 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8408 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8409 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8410 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8411 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8413 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8414 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8415 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8418 static void tg3_timer(unsigned long __opaque)
8420 struct tg3 *tp = (struct tg3 *) __opaque;
8425 spin_lock(&tp->lock);
8427 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8428 /* All of this garbage is because when using non-tagged
8429 * IRQ status the mailbox/status_block protocol the chip
8430 * uses with the cpu is race prone.
8432 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8433 tw32(GRC_LOCAL_CTRL,
8434 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8436 tw32(HOSTCC_MODE, tp->coalesce_mode |
8437 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8440 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8441 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8442 spin_unlock(&tp->lock);
8443 schedule_work(&tp->reset_task);
8448 /* This part only runs once per second. */
8449 if (!--tp->timer_counter) {
8450 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8451 tg3_periodic_fetch_stats(tp);
8453 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8457 mac_stat = tr32(MAC_STATUS);
8460 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8461 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8463 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8467 tg3_setup_phy(tp, 0);
8468 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8469 u32 mac_stat = tr32(MAC_STATUS);
8472 if (netif_carrier_ok(tp->dev) &&
8473 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8476 if (! netif_carrier_ok(tp->dev) &&
8477 (mac_stat & (MAC_STATUS_PCS_SYNCED |
8478 MAC_STATUS_SIGNAL_DET))) {
8482 if (!tp->serdes_counter) {
8485 ~MAC_MODE_PORT_MODE_MASK));
8487 tw32_f(MAC_MODE, tp->mac_mode);
8490 tg3_setup_phy(tp, 0);
8492 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8493 tg3_serdes_parallel_detect(tp);
8495 tp->timer_counter = tp->timer_multiplier;
8498 /* Heartbeat is only sent once every 2 seconds.
8500 * The heartbeat is to tell the ASF firmware that the host
8501 * driver is still alive. In the event that the OS crashes,
8502 * ASF needs to reset the hardware to free up the FIFO space
8503 * that may be filled with rx packets destined for the host.
8504 * If the FIFO is full, ASF will no longer function properly.
8506 * Unintended resets have been reported on real time kernels
8507 * where the timer doesn't run on time. Netpoll will also have
8510 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8511 * to check the ring condition when the heartbeat is expiring
8512 * before doing the reset. This will prevent most unintended
8515 if (!--tp->asf_counter) {
8516 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8517 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8518 tg3_wait_for_event_ack(tp);
8520 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8521 FWCMD_NICDRV_ALIVE3);
8522 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8523 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
8524 TG3_FW_UPDATE_TIMEOUT_SEC);
8526 tg3_generate_fw_event(tp);
8528 tp->asf_counter = tp->asf_multiplier;
8531 spin_unlock(&tp->lock);
8534 tp->timer.expires = jiffies + tp->timer_offset;
8535 add_timer(&tp->timer);
8538 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8541 unsigned long flags;
8543 struct tg3_napi *tnapi = &tp->napi[irq_num];
8545 if (tp->irq_cnt == 1)
8546 name = tp->dev->name;
8548 name = &tnapi->irq_lbl[0];
8549 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8550 name[IFNAMSIZ-1] = 0;
8553 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8555 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8557 flags = IRQF_SAMPLE_RANDOM;
8560 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8561 fn = tg3_interrupt_tagged;
8562 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8565 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8568 static int tg3_test_interrupt(struct tg3 *tp)
8570 struct tg3_napi *tnapi = &tp->napi[0];
8571 struct net_device *dev = tp->dev;
8572 int err, i, intr_ok = 0;
8575 if (!netif_running(dev))
8578 tg3_disable_ints(tp);
8580 free_irq(tnapi->irq_vec, tnapi);
8583 * Turn off MSI one shot mode. Otherwise this test has no
8584 * observable way to know whether the interrupt was delivered.
8586 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8587 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
8588 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8589 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8590 tw32(MSGINT_MODE, val);
8593 err = request_irq(tnapi->irq_vec, tg3_test_isr,
8594 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8598 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8599 tg3_enable_ints(tp);
8601 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8604 for (i = 0; i < 5; i++) {
8605 u32 int_mbox, misc_host_ctrl;
8607 int_mbox = tr32_mailbox(tnapi->int_mbox);
8608 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8610 if ((int_mbox != 0) ||
8611 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8619 tg3_disable_ints(tp);
8621 free_irq(tnapi->irq_vec, tnapi);
8623 err = tg3_request_irq(tp, 0);
8629 /* Reenable MSI one shot mode. */
8630 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8631 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
8632 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8633 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8634 tw32(MSGINT_MODE, val);
8642 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8643 * successfully restored
8645 static int tg3_test_msi(struct tg3 *tp)
8650 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8653 /* Turn off SERR reporting in case MSI terminates with Master
8656 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8657 pci_write_config_word(tp->pdev, PCI_COMMAND,
8658 pci_cmd & ~PCI_COMMAND_SERR);
8660 err = tg3_test_interrupt(tp);
8662 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8667 /* other failures */
8671 /* MSI test failed, go back to INTx mode */
8672 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
8673 "to INTx mode. Please report this failure to the PCI "
8674 "maintainer and include system chipset information\n");
8676 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8678 pci_disable_msi(tp->pdev);
8680 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8682 err = tg3_request_irq(tp, 0);
8686 /* Need to reset the chip because the MSI cycle may have terminated
8687 * with Master Abort.
8689 tg3_full_lock(tp, 1);
8691 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8692 err = tg3_init_hw(tp, 1);
8694 tg3_full_unlock(tp);
8697 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8702 static int tg3_request_firmware(struct tg3 *tp)
8704 const __be32 *fw_data;
8706 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8707 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
8712 fw_data = (void *)tp->fw->data;
8714 /* Firmware blob starts with version numbers, followed by
8715 * start address and _full_ length including BSS sections
8716 * (which must be longer than the actual data, of course
8719 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
8720 if (tp->fw_len < (tp->fw->size - 12)) {
8721 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
8722 tp->fw_len, tp->fw_needed);
8723 release_firmware(tp->fw);
8728 /* We no longer need firmware; we have it. */
8729 tp->fw_needed = NULL;
8733 static bool tg3_enable_msix(struct tg3 *tp)
8735 int i, rc, cpus = num_online_cpus();
8736 struct msix_entry msix_ent[tp->irq_max];
8739 /* Just fallback to the simpler MSI mode. */
8743 * We want as many rx rings enabled as there are cpus.
8744 * The first MSIX vector only deals with link interrupts, etc,
8745 * so we add one to the number of vectors we are requesting.
8747 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8749 for (i = 0; i < tp->irq_max; i++) {
8750 msix_ent[i].entry = i;
8751 msix_ent[i].vector = 0;
8754 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8756 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8758 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8760 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
8765 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8767 for (i = 0; i < tp->irq_max; i++)
8768 tp->napi[i].irq_vec = msix_ent[i].vector;
8770 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8771 tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
8772 tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8774 tp->dev->real_num_tx_queues = 1;
8779 static void tg3_ints_init(struct tg3 *tp)
8781 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8782 !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8783 /* All MSI supporting chips should support tagged
8784 * status. Assert that this is the case.
8786 netdev_warn(tp->dev,
8787 "MSI without TAGGED_STATUS? Not using MSI\n");
8791 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8792 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8793 else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8794 pci_enable_msi(tp->pdev) == 0)
8795 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8797 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8798 u32 msi_mode = tr32(MSGINT_MODE);
8799 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8800 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8801 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8804 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8806 tp->napi[0].irq_vec = tp->pdev->irq;
8807 tp->dev->real_num_tx_queues = 1;
8811 static void tg3_ints_fini(struct tg3 *tp)
8813 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8814 pci_disable_msix(tp->pdev);
8815 else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8816 pci_disable_msi(tp->pdev);
8817 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8818 tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
8821 static int tg3_open(struct net_device *dev)
8823 struct tg3 *tp = netdev_priv(dev);
8826 if (tp->fw_needed) {
8827 err = tg3_request_firmware(tp);
8828 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8832 netdev_warn(tp->dev, "TSO capability disabled\n");
8833 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8834 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8835 netdev_notice(tp->dev, "TSO capability restored\n");
8836 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8840 netif_carrier_off(tp->dev);
8842 err = tg3_set_power_state(tp, PCI_D0);
8846 tg3_full_lock(tp, 0);
8848 tg3_disable_ints(tp);
8849 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8851 tg3_full_unlock(tp);
8854 * Setup interrupts first so we know how
8855 * many NAPI resources to allocate
8859 /* The placement of this call is tied
8860 * to the setup and use of Host TX descriptors.
8862 err = tg3_alloc_consistent(tp);
8866 tg3_napi_enable(tp);
8868 for (i = 0; i < tp->irq_cnt; i++) {
8869 struct tg3_napi *tnapi = &tp->napi[i];
8870 err = tg3_request_irq(tp, i);
8872 for (i--; i >= 0; i--)
8873 free_irq(tnapi->irq_vec, tnapi);
8881 tg3_full_lock(tp, 0);
8883 err = tg3_init_hw(tp, 1);
8885 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8888 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8889 tp->timer_offset = HZ;
8891 tp->timer_offset = HZ / 10;
8893 BUG_ON(tp->timer_offset > HZ);
8894 tp->timer_counter = tp->timer_multiplier =
8895 (HZ / tp->timer_offset);
8896 tp->asf_counter = tp->asf_multiplier =
8897 ((HZ / tp->timer_offset) * 2);
8899 init_timer(&tp->timer);
8900 tp->timer.expires = jiffies + tp->timer_offset;
8901 tp->timer.data = (unsigned long) tp;
8902 tp->timer.function = tg3_timer;
8905 tg3_full_unlock(tp);
8910 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8911 err = tg3_test_msi(tp);
8914 tg3_full_lock(tp, 0);
8915 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8917 tg3_full_unlock(tp);
8922 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8923 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 &&
8924 (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8925 (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8926 u32 val = tr32(PCIE_TRANSACTION_CFG);
8928 tw32(PCIE_TRANSACTION_CFG,
8929 val | PCIE_TRANS_CFG_1SHOT_MSI);
8935 tg3_full_lock(tp, 0);
8937 add_timer(&tp->timer);
8938 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8939 tg3_enable_ints(tp);
8941 tg3_full_unlock(tp);
8943 netif_tx_start_all_queues(dev);
8948 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8949 struct tg3_napi *tnapi = &tp->napi[i];
8950 free_irq(tnapi->irq_vec, tnapi);
8954 tg3_napi_disable(tp);
8955 tg3_free_consistent(tp);
8962 static struct net_device_stats *tg3_get_stats(struct net_device *);
8963 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8965 static int tg3_close(struct net_device *dev)
8968 struct tg3 *tp = netdev_priv(dev);
8970 tg3_napi_disable(tp);
8971 cancel_work_sync(&tp->reset_task);
8973 netif_tx_stop_all_queues(dev);
8975 del_timer_sync(&tp->timer);
8979 tg3_full_lock(tp, 1);
8981 tg3_disable_ints(tp);
8983 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8985 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8987 tg3_full_unlock(tp);
8989 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8990 struct tg3_napi *tnapi = &tp->napi[i];
8991 free_irq(tnapi->irq_vec, tnapi);
8996 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8997 sizeof(tp->net_stats_prev));
8998 memcpy(&tp->estats_prev, tg3_get_estats(tp),
8999 sizeof(tp->estats_prev));
9001 tg3_free_consistent(tp);
9003 tg3_set_power_state(tp, PCI_D3hot);
9005 netif_carrier_off(tp->dev);
9010 static inline unsigned long get_stat64(tg3_stat64_t *val)
9014 #if (BITS_PER_LONG == 32)
9017 ret = ((u64)val->high << 32) | ((u64)val->low);
9022 static inline u64 get_estat64(tg3_stat64_t *val)
9024 return ((u64)val->high << 32) | ((u64)val->low);
9027 static unsigned long calc_crc_errors(struct tg3 *tp)
9029 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9031 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9032 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9033 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9036 spin_lock_bh(&tp->lock);
9037 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9038 tg3_writephy(tp, MII_TG3_TEST1,
9039 val | MII_TG3_TEST1_CRC_EN);
9040 tg3_readphy(tp, 0x14, &val);
9043 spin_unlock_bh(&tp->lock);
9045 tp->phy_crc_errors += val;
9047 return tp->phy_crc_errors;
9050 return get_stat64(&hw_stats->rx_fcs_errors);
9053 #define ESTAT_ADD(member) \
9054 estats->member = old_estats->member + \
9055 get_estat64(&hw_stats->member)
9057 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9059 struct tg3_ethtool_stats *estats = &tp->estats;
9060 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9061 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9066 ESTAT_ADD(rx_octets);
9067 ESTAT_ADD(rx_fragments);
9068 ESTAT_ADD(rx_ucast_packets);
9069 ESTAT_ADD(rx_mcast_packets);
9070 ESTAT_ADD(rx_bcast_packets);
9071 ESTAT_ADD(rx_fcs_errors);
9072 ESTAT_ADD(rx_align_errors);
9073 ESTAT_ADD(rx_xon_pause_rcvd);
9074 ESTAT_ADD(rx_xoff_pause_rcvd);
9075 ESTAT_ADD(rx_mac_ctrl_rcvd);
9076 ESTAT_ADD(rx_xoff_entered);
9077 ESTAT_ADD(rx_frame_too_long_errors);
9078 ESTAT_ADD(rx_jabbers);
9079 ESTAT_ADD(rx_undersize_packets);
9080 ESTAT_ADD(rx_in_length_errors);
9081 ESTAT_ADD(rx_out_length_errors);
9082 ESTAT_ADD(rx_64_or_less_octet_packets);
9083 ESTAT_ADD(rx_65_to_127_octet_packets);
9084 ESTAT_ADD(rx_128_to_255_octet_packets);
9085 ESTAT_ADD(rx_256_to_511_octet_packets);
9086 ESTAT_ADD(rx_512_to_1023_octet_packets);
9087 ESTAT_ADD(rx_1024_to_1522_octet_packets);
9088 ESTAT_ADD(rx_1523_to_2047_octet_packets);
9089 ESTAT_ADD(rx_2048_to_4095_octet_packets);
9090 ESTAT_ADD(rx_4096_to_8191_octet_packets);
9091 ESTAT_ADD(rx_8192_to_9022_octet_packets);
9093 ESTAT_ADD(tx_octets);
9094 ESTAT_ADD(tx_collisions);
9095 ESTAT_ADD(tx_xon_sent);
9096 ESTAT_ADD(tx_xoff_sent);
9097 ESTAT_ADD(tx_flow_control);
9098 ESTAT_ADD(tx_mac_errors);
9099 ESTAT_ADD(tx_single_collisions);
9100 ESTAT_ADD(tx_mult_collisions);
9101 ESTAT_ADD(tx_deferred);
9102 ESTAT_ADD(tx_excessive_collisions);
9103 ESTAT_ADD(tx_late_collisions);
9104 ESTAT_ADD(tx_collide_2times);
9105 ESTAT_ADD(tx_collide_3times);
9106 ESTAT_ADD(tx_collide_4times);
9107 ESTAT_ADD(tx_collide_5times);
9108 ESTAT_ADD(tx_collide_6times);
9109 ESTAT_ADD(tx_collide_7times);
9110 ESTAT_ADD(tx_collide_8times);
9111 ESTAT_ADD(tx_collide_9times);
9112 ESTAT_ADD(tx_collide_10times);
9113 ESTAT_ADD(tx_collide_11times);
9114 ESTAT_ADD(tx_collide_12times);
9115 ESTAT_ADD(tx_collide_13times);
9116 ESTAT_ADD(tx_collide_14times);
9117 ESTAT_ADD(tx_collide_15times);
9118 ESTAT_ADD(tx_ucast_packets);
9119 ESTAT_ADD(tx_mcast_packets);
9120 ESTAT_ADD(tx_bcast_packets);
9121 ESTAT_ADD(tx_carrier_sense_errors);
9122 ESTAT_ADD(tx_discards);
9123 ESTAT_ADD(tx_errors);
9125 ESTAT_ADD(dma_writeq_full);
9126 ESTAT_ADD(dma_write_prioq_full);
9127 ESTAT_ADD(rxbds_empty);
9128 ESTAT_ADD(rx_discards);
9129 ESTAT_ADD(rx_errors);
9130 ESTAT_ADD(rx_threshold_hit);
9132 ESTAT_ADD(dma_readq_full);
9133 ESTAT_ADD(dma_read_prioq_full);
9134 ESTAT_ADD(tx_comp_queue_full);
9136 ESTAT_ADD(ring_set_send_prod_index);
9137 ESTAT_ADD(ring_status_update);
9138 ESTAT_ADD(nic_irqs);
9139 ESTAT_ADD(nic_avoided_irqs);
9140 ESTAT_ADD(nic_tx_threshold_hit);
9145 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
9147 struct tg3 *tp = netdev_priv(dev);
9148 struct net_device_stats *stats = &tp->net_stats;
9149 struct net_device_stats *old_stats = &tp->net_stats_prev;
9150 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9155 stats->rx_packets = old_stats->rx_packets +
9156 get_stat64(&hw_stats->rx_ucast_packets) +
9157 get_stat64(&hw_stats->rx_mcast_packets) +
9158 get_stat64(&hw_stats->rx_bcast_packets);
9160 stats->tx_packets = old_stats->tx_packets +
9161 get_stat64(&hw_stats->tx_ucast_packets) +
9162 get_stat64(&hw_stats->tx_mcast_packets) +
9163 get_stat64(&hw_stats->tx_bcast_packets);
9165 stats->rx_bytes = old_stats->rx_bytes +
9166 get_stat64(&hw_stats->rx_octets);
9167 stats->tx_bytes = old_stats->tx_bytes +
9168 get_stat64(&hw_stats->tx_octets);
9170 stats->rx_errors = old_stats->rx_errors +
9171 get_stat64(&hw_stats->rx_errors);
9172 stats->tx_errors = old_stats->tx_errors +
9173 get_stat64(&hw_stats->tx_errors) +
9174 get_stat64(&hw_stats->tx_mac_errors) +
9175 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9176 get_stat64(&hw_stats->tx_discards);
9178 stats->multicast = old_stats->multicast +
9179 get_stat64(&hw_stats->rx_mcast_packets);
9180 stats->collisions = old_stats->collisions +
9181 get_stat64(&hw_stats->tx_collisions);
9183 stats->rx_length_errors = old_stats->rx_length_errors +
9184 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9185 get_stat64(&hw_stats->rx_undersize_packets);
9187 stats->rx_over_errors = old_stats->rx_over_errors +
9188 get_stat64(&hw_stats->rxbds_empty);
9189 stats->rx_frame_errors = old_stats->rx_frame_errors +
9190 get_stat64(&hw_stats->rx_align_errors);
9191 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9192 get_stat64(&hw_stats->tx_discards);
9193 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9194 get_stat64(&hw_stats->tx_carrier_sense_errors);
9196 stats->rx_crc_errors = old_stats->rx_crc_errors +
9197 calc_crc_errors(tp);
9199 stats->rx_missed_errors = old_stats->rx_missed_errors +
9200 get_stat64(&hw_stats->rx_discards);
9205 static inline u32 calc_crc(unsigned char *buf, int len)
9213 for (j = 0; j < len; j++) {
9216 for (k = 0; k < 8; k++) {
9229 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9231 /* accept or reject all multicast frames */
9232 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9233 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9234 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9235 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9238 static void __tg3_set_rx_mode(struct net_device *dev)
9240 struct tg3 *tp = netdev_priv(dev);
9243 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9244 RX_MODE_KEEP_VLAN_TAG);
9246 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9249 #if TG3_VLAN_TAG_USED
9251 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9252 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9254 /* By definition, VLAN is disabled always in this
9257 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9258 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9261 if (dev->flags & IFF_PROMISC) {
9262 /* Promiscuous mode. */
9263 rx_mode |= RX_MODE_PROMISC;
9264 } else if (dev->flags & IFF_ALLMULTI) {
9265 /* Accept all multicast. */
9266 tg3_set_multi (tp, 1);
9267 } else if (netdev_mc_empty(dev)) {
9268 /* Reject all multicast. */
9269 tg3_set_multi (tp, 0);
9271 /* Accept one or more multicast(s). */
9272 struct netdev_hw_addr *ha;
9273 u32 mc_filter[4] = { 0, };
9278 netdev_for_each_mc_addr(ha, dev) {
9279 crc = calc_crc(ha->addr, ETH_ALEN);
9281 regidx = (bit & 0x60) >> 5;
9283 mc_filter[regidx] |= (1 << bit);
9286 tw32(MAC_HASH_REG_0, mc_filter[0]);
9287 tw32(MAC_HASH_REG_1, mc_filter[1]);
9288 tw32(MAC_HASH_REG_2, mc_filter[2]);
9289 tw32(MAC_HASH_REG_3, mc_filter[3]);
9292 if (rx_mode != tp->rx_mode) {
9293 tp->rx_mode = rx_mode;
9294 tw32_f(MAC_RX_MODE, rx_mode);
9299 static void tg3_set_rx_mode(struct net_device *dev)
9301 struct tg3 *tp = netdev_priv(dev);
9303 if (!netif_running(dev))
9306 tg3_full_lock(tp, 0);
9307 __tg3_set_rx_mode(dev);
9308 tg3_full_unlock(tp);
9311 #define TG3_REGDUMP_LEN (32 * 1024)
9313 static int tg3_get_regs_len(struct net_device *dev)
9315 return TG3_REGDUMP_LEN;
9318 static void tg3_get_regs(struct net_device *dev,
9319 struct ethtool_regs *regs, void *_p)
9322 struct tg3 *tp = netdev_priv(dev);
9328 memset(p, 0, TG3_REGDUMP_LEN);
9330 if (tp->link_config.phy_is_low_power)
9333 tg3_full_lock(tp, 0);
9335 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
9336 #define GET_REG32_LOOP(base,len) \
9337 do { p = (u32 *)(orig_p + (base)); \
9338 for (i = 0; i < len; i += 4) \
9339 __GET_REG32((base) + i); \
9341 #define GET_REG32_1(reg) \
9342 do { p = (u32 *)(orig_p + (reg)); \
9343 __GET_REG32((reg)); \
9346 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9347 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9348 GET_REG32_LOOP(MAC_MODE, 0x4f0);
9349 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9350 GET_REG32_1(SNDDATAC_MODE);
9351 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9352 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9353 GET_REG32_1(SNDBDC_MODE);
9354 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9355 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9356 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9357 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9358 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9359 GET_REG32_1(RCVDCC_MODE);
9360 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9361 GET_REG32_LOOP(RCVCC_MODE, 0x14);
9362 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9363 GET_REG32_1(MBFREE_MODE);
9364 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9365 GET_REG32_LOOP(MEMARB_MODE, 0x10);
9366 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9367 GET_REG32_LOOP(RDMAC_MODE, 0x08);
9368 GET_REG32_LOOP(WDMAC_MODE, 0x08);
9369 GET_REG32_1(RX_CPU_MODE);
9370 GET_REG32_1(RX_CPU_STATE);
9371 GET_REG32_1(RX_CPU_PGMCTR);
9372 GET_REG32_1(RX_CPU_HWBKPT);
9373 GET_REG32_1(TX_CPU_MODE);
9374 GET_REG32_1(TX_CPU_STATE);
9375 GET_REG32_1(TX_CPU_PGMCTR);
9376 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9377 GET_REG32_LOOP(FTQ_RESET, 0x120);
9378 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9379 GET_REG32_1(DMAC_MODE);
9380 GET_REG32_LOOP(GRC_MODE, 0x4c);
9381 if (tp->tg3_flags & TG3_FLAG_NVRAM)
9382 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9385 #undef GET_REG32_LOOP
9388 tg3_full_unlock(tp);
9391 static int tg3_get_eeprom_len(struct net_device *dev)
9393 struct tg3 *tp = netdev_priv(dev);
9395 return tp->nvram_size;
9398 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9400 struct tg3 *tp = netdev_priv(dev);
9403 u32 i, offset, len, b_offset, b_count;
9406 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9409 if (tp->link_config.phy_is_low_power)
9412 offset = eeprom->offset;
9416 eeprom->magic = TG3_EEPROM_MAGIC;
9419 /* adjustments to start on required 4 byte boundary */
9420 b_offset = offset & 3;
9421 b_count = 4 - b_offset;
9422 if (b_count > len) {
9423 /* i.e. offset=1 len=2 */
9426 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9429 memcpy(data, ((char*)&val) + b_offset, b_count);
9432 eeprom->len += b_count;
9435 /* read bytes upto the last 4 byte boundary */
9436 pd = &data[eeprom->len];
9437 for (i = 0; i < (len - (len & 3)); i += 4) {
9438 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9443 memcpy(pd + i, &val, 4);
9448 /* read last bytes not ending on 4 byte boundary */
9449 pd = &data[eeprom->len];
9451 b_offset = offset + len - b_count;
9452 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9455 memcpy(pd, &val, b_count);
9456 eeprom->len += b_count;
9461 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9463 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9465 struct tg3 *tp = netdev_priv(dev);
9467 u32 offset, len, b_offset, odd_len;
9471 if (tp->link_config.phy_is_low_power)
9474 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9475 eeprom->magic != TG3_EEPROM_MAGIC)
9478 offset = eeprom->offset;
9481 if ((b_offset = (offset & 3))) {
9482 /* adjustments to start on required 4 byte boundary */
9483 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9494 /* adjustments to end on required 4 byte boundary */
9496 len = (len + 3) & ~3;
9497 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9503 if (b_offset || odd_len) {
9504 buf = kmalloc(len, GFP_KERNEL);
9508 memcpy(buf, &start, 4);
9510 memcpy(buf+len-4, &end, 4);
9511 memcpy(buf + b_offset, data, eeprom->len);
9514 ret = tg3_nvram_write_block(tp, offset, len, buf);
9522 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9524 struct tg3 *tp = netdev_priv(dev);
9526 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9527 struct phy_device *phydev;
9528 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9530 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9531 return phy_ethtool_gset(phydev, cmd);
9534 cmd->supported = (SUPPORTED_Autoneg);
9536 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9537 cmd->supported |= (SUPPORTED_1000baseT_Half |
9538 SUPPORTED_1000baseT_Full);
9540 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
9541 cmd->supported |= (SUPPORTED_100baseT_Half |
9542 SUPPORTED_100baseT_Full |
9543 SUPPORTED_10baseT_Half |
9544 SUPPORTED_10baseT_Full |
9546 cmd->port = PORT_TP;
9548 cmd->supported |= SUPPORTED_FIBRE;
9549 cmd->port = PORT_FIBRE;
9552 cmd->advertising = tp->link_config.advertising;
9553 if (netif_running(dev)) {
9554 cmd->speed = tp->link_config.active_speed;
9555 cmd->duplex = tp->link_config.active_duplex;
9557 cmd->phy_address = tp->phy_addr;
9558 cmd->transceiver = XCVR_INTERNAL;
9559 cmd->autoneg = tp->link_config.autoneg;
9565 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9567 struct tg3 *tp = netdev_priv(dev);
9569 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9570 struct phy_device *phydev;
9571 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9573 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9574 return phy_ethtool_sset(phydev, cmd);
9577 if (cmd->autoneg != AUTONEG_ENABLE &&
9578 cmd->autoneg != AUTONEG_DISABLE)
9581 if (cmd->autoneg == AUTONEG_DISABLE &&
9582 cmd->duplex != DUPLEX_FULL &&
9583 cmd->duplex != DUPLEX_HALF)
9586 if (cmd->autoneg == AUTONEG_ENABLE) {
9587 u32 mask = ADVERTISED_Autoneg |
9589 ADVERTISED_Asym_Pause;
9591 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9592 mask |= ADVERTISED_1000baseT_Half |
9593 ADVERTISED_1000baseT_Full;
9595 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9596 mask |= ADVERTISED_100baseT_Half |
9597 ADVERTISED_100baseT_Full |
9598 ADVERTISED_10baseT_Half |
9599 ADVERTISED_10baseT_Full |
9602 mask |= ADVERTISED_FIBRE;
9604 if (cmd->advertising & ~mask)
9607 mask &= (ADVERTISED_1000baseT_Half |
9608 ADVERTISED_1000baseT_Full |
9609 ADVERTISED_100baseT_Half |
9610 ADVERTISED_100baseT_Full |
9611 ADVERTISED_10baseT_Half |
9612 ADVERTISED_10baseT_Full);
9614 cmd->advertising &= mask;
9616 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9617 if (cmd->speed != SPEED_1000)
9620 if (cmd->duplex != DUPLEX_FULL)
9623 if (cmd->speed != SPEED_100 &&
9624 cmd->speed != SPEED_10)
9629 tg3_full_lock(tp, 0);
9631 tp->link_config.autoneg = cmd->autoneg;
9632 if (cmd->autoneg == AUTONEG_ENABLE) {
9633 tp->link_config.advertising = (cmd->advertising |
9634 ADVERTISED_Autoneg);
9635 tp->link_config.speed = SPEED_INVALID;
9636 tp->link_config.duplex = DUPLEX_INVALID;
9638 tp->link_config.advertising = 0;
9639 tp->link_config.speed = cmd->speed;
9640 tp->link_config.duplex = cmd->duplex;
9643 tp->link_config.orig_speed = tp->link_config.speed;
9644 tp->link_config.orig_duplex = tp->link_config.duplex;
9645 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9647 if (netif_running(dev))
9648 tg3_setup_phy(tp, 1);
9650 tg3_full_unlock(tp);
9655 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9657 struct tg3 *tp = netdev_priv(dev);
9659 strcpy(info->driver, DRV_MODULE_NAME);
9660 strcpy(info->version, DRV_MODULE_VERSION);
9661 strcpy(info->fw_version, tp->fw_ver);
9662 strcpy(info->bus_info, pci_name(tp->pdev));
9665 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9667 struct tg3 *tp = netdev_priv(dev);
9669 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9670 device_can_wakeup(&tp->pdev->dev))
9671 wol->supported = WAKE_MAGIC;
9675 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9676 device_can_wakeup(&tp->pdev->dev))
9677 wol->wolopts = WAKE_MAGIC;
9678 memset(&wol->sopass, 0, sizeof(wol->sopass));
9681 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9683 struct tg3 *tp = netdev_priv(dev);
9684 struct device *dp = &tp->pdev->dev;
9686 if (wol->wolopts & ~WAKE_MAGIC)
9688 if ((wol->wolopts & WAKE_MAGIC) &&
9689 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9692 spin_lock_bh(&tp->lock);
9693 if (wol->wolopts & WAKE_MAGIC) {
9694 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9695 device_set_wakeup_enable(dp, true);
9697 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9698 device_set_wakeup_enable(dp, false);
9700 spin_unlock_bh(&tp->lock);
9705 static u32 tg3_get_msglevel(struct net_device *dev)
9707 struct tg3 *tp = netdev_priv(dev);
9708 return tp->msg_enable;
9711 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9713 struct tg3 *tp = netdev_priv(dev);
9714 tp->msg_enable = value;
9717 static int tg3_set_tso(struct net_device *dev, u32 value)
9719 struct tg3 *tp = netdev_priv(dev);
9721 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9726 if ((dev->features & NETIF_F_IPV6_CSUM) &&
9727 ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9728 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9730 dev->features |= NETIF_F_TSO6;
9731 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9732 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9733 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9734 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9735 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9736 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9737 dev->features |= NETIF_F_TSO_ECN;
9739 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9741 return ethtool_op_set_tso(dev, value);
9744 static int tg3_nway_reset(struct net_device *dev)
9746 struct tg3 *tp = netdev_priv(dev);
9749 if (!netif_running(dev))
9752 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9755 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9756 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9758 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9762 spin_lock_bh(&tp->lock);
9764 tg3_readphy(tp, MII_BMCR, &bmcr);
9765 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9766 ((bmcr & BMCR_ANENABLE) ||
9767 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9768 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9772 spin_unlock_bh(&tp->lock);
9778 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9780 struct tg3 *tp = netdev_priv(dev);
9782 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9783 ering->rx_mini_max_pending = 0;
9784 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9785 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9787 ering->rx_jumbo_max_pending = 0;
9789 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9791 ering->rx_pending = tp->rx_pending;
9792 ering->rx_mini_pending = 0;
9793 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9794 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9796 ering->rx_jumbo_pending = 0;
9798 ering->tx_pending = tp->napi[0].tx_pending;
9801 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9803 struct tg3 *tp = netdev_priv(dev);
9804 int i, irq_sync = 0, err = 0;
9806 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9807 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9808 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9809 (ering->tx_pending <= MAX_SKB_FRAGS) ||
9810 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9811 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9814 if (netif_running(dev)) {
9820 tg3_full_lock(tp, irq_sync);
9822 tp->rx_pending = ering->rx_pending;
9824 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9825 tp->rx_pending > 63)
9826 tp->rx_pending = 63;
9827 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9829 for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9830 tp->napi[i].tx_pending = ering->tx_pending;
9832 if (netif_running(dev)) {
9833 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9834 err = tg3_restart_hw(tp, 1);
9836 tg3_netif_start(tp);
9839 tg3_full_unlock(tp);
9841 if (irq_sync && !err)
9847 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9849 struct tg3 *tp = netdev_priv(dev);
9851 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9853 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9854 epause->rx_pause = 1;
9856 epause->rx_pause = 0;
9858 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9859 epause->tx_pause = 1;
9861 epause->tx_pause = 0;
9864 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9866 struct tg3 *tp = netdev_priv(dev);
9869 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9871 struct phy_device *phydev;
9873 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9875 if (!(phydev->supported & SUPPORTED_Pause) ||
9876 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
9877 ((epause->rx_pause && !epause->tx_pause) ||
9878 (!epause->rx_pause && epause->tx_pause))))
9881 tp->link_config.flowctrl = 0;
9882 if (epause->rx_pause) {
9883 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9885 if (epause->tx_pause) {
9886 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9887 newadv = ADVERTISED_Pause;
9889 newadv = ADVERTISED_Pause |
9890 ADVERTISED_Asym_Pause;
9891 } else if (epause->tx_pause) {
9892 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9893 newadv = ADVERTISED_Asym_Pause;
9897 if (epause->autoneg)
9898 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9900 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9902 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9903 u32 oldadv = phydev->advertising &
9904 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
9905 if (oldadv != newadv) {
9906 phydev->advertising &=
9907 ~(ADVERTISED_Pause |
9908 ADVERTISED_Asym_Pause);
9909 phydev->advertising |= newadv;
9910 if (phydev->autoneg) {
9912 * Always renegotiate the link to
9913 * inform our link partner of our
9914 * flow control settings, even if the
9915 * flow control is forced. Let
9916 * tg3_adjust_link() do the final
9917 * flow control setup.
9919 return phy_start_aneg(phydev);
9923 if (!epause->autoneg)
9924 tg3_setup_flow_control(tp, 0, 0);
9926 tp->link_config.orig_advertising &=
9927 ~(ADVERTISED_Pause |
9928 ADVERTISED_Asym_Pause);
9929 tp->link_config.orig_advertising |= newadv;
9934 if (netif_running(dev)) {
9939 tg3_full_lock(tp, irq_sync);
9941 if (epause->autoneg)
9942 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9944 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9945 if (epause->rx_pause)
9946 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9948 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9949 if (epause->tx_pause)
9950 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9952 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9954 if (netif_running(dev)) {
9955 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9956 err = tg3_restart_hw(tp, 1);
9958 tg3_netif_start(tp);
9961 tg3_full_unlock(tp);
9967 static u32 tg3_get_rx_csum(struct net_device *dev)
9969 struct tg3 *tp = netdev_priv(dev);
9970 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9973 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9975 struct tg3 *tp = netdev_priv(dev);
9977 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9983 spin_lock_bh(&tp->lock);
9985 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9987 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
9988 spin_unlock_bh(&tp->lock);
9993 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9995 struct tg3 *tp = netdev_priv(dev);
9997 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10003 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10004 ethtool_op_set_tx_ipv6_csum(dev, data);
10006 ethtool_op_set_tx_csum(dev, data);
10011 static int tg3_get_sset_count (struct net_device *dev, int sset)
10015 return TG3_NUM_TEST;
10017 return TG3_NUM_STATS;
10019 return -EOPNOTSUPP;
10023 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
10025 switch (stringset) {
10027 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
10030 memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys));
10033 WARN_ON(1); /* we need a WARN() */
10038 static int tg3_phys_id(struct net_device *dev, u32 data)
10040 struct tg3 *tp = netdev_priv(dev);
10043 if (!netif_running(tp->dev))
10047 data = UINT_MAX / 2;
10049 for (i = 0; i < (data * 2); i++) {
10051 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10052 LED_CTRL_1000MBPS_ON |
10053 LED_CTRL_100MBPS_ON |
10054 LED_CTRL_10MBPS_ON |
10055 LED_CTRL_TRAFFIC_OVERRIDE |
10056 LED_CTRL_TRAFFIC_BLINK |
10057 LED_CTRL_TRAFFIC_LED);
10060 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10061 LED_CTRL_TRAFFIC_OVERRIDE);
10063 if (msleep_interruptible(500))
10066 tw32(MAC_LED_CTRL, tp->led_ctrl);
10070 static void tg3_get_ethtool_stats (struct net_device *dev,
10071 struct ethtool_stats *estats, u64 *tmp_stats)
10073 struct tg3 *tp = netdev_priv(dev);
10074 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10077 #define NVRAM_TEST_SIZE 0x100
10078 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10079 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10080 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
10081 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10082 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10084 static int tg3_test_nvram(struct tg3 *tp)
10088 int i, j, k, err = 0, size;
10090 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10093 if (tg3_nvram_read(tp, 0, &magic) != 0)
10096 if (magic == TG3_EEPROM_MAGIC)
10097 size = NVRAM_TEST_SIZE;
10098 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10099 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10100 TG3_EEPROM_SB_FORMAT_1) {
10101 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10102 case TG3_EEPROM_SB_REVISION_0:
10103 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10105 case TG3_EEPROM_SB_REVISION_2:
10106 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10108 case TG3_EEPROM_SB_REVISION_3:
10109 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10116 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10117 size = NVRAM_SELFBOOT_HW_SIZE;
10121 buf = kmalloc(size, GFP_KERNEL);
10126 for (i = 0, j = 0; i < size; i += 4, j++) {
10127 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10134 /* Selfboot format */
10135 magic = be32_to_cpu(buf[0]);
10136 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10137 TG3_EEPROM_MAGIC_FW) {
10138 u8 *buf8 = (u8 *) buf, csum8 = 0;
10140 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10141 TG3_EEPROM_SB_REVISION_2) {
10142 /* For rev 2, the csum doesn't include the MBA. */
10143 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10145 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10148 for (i = 0; i < size; i++)
10161 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10162 TG3_EEPROM_MAGIC_HW) {
10163 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10164 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10165 u8 *buf8 = (u8 *) buf;
10167 /* Separate the parity bits and the data bytes. */
10168 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10169 if ((i == 0) || (i == 8)) {
10173 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10174 parity[k++] = buf8[i] & msk;
10176 } else if (i == 16) {
10180 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10181 parity[k++] = buf8[i] & msk;
10184 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10185 parity[k++] = buf8[i] & msk;
10188 data[j++] = buf8[i];
10192 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10193 u8 hw8 = hweight8(data[i]);
10195 if ((hw8 & 0x1) && parity[i])
10197 else if (!(hw8 & 0x1) && !parity[i])
10204 /* Bootstrap checksum at offset 0x10 */
10205 csum = calc_crc((unsigned char *) buf, 0x10);
10206 if (csum != be32_to_cpu(buf[0x10/4]))
10209 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10210 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10211 if (csum != be32_to_cpu(buf[0xfc/4]))
10221 #define TG3_SERDES_TIMEOUT_SEC 2
10222 #define TG3_COPPER_TIMEOUT_SEC 6
10224 static int tg3_test_link(struct tg3 *tp)
10228 if (!netif_running(tp->dev))
10231 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10232 max = TG3_SERDES_TIMEOUT_SEC;
10234 max = TG3_COPPER_TIMEOUT_SEC;
10236 for (i = 0; i < max; i++) {
10237 if (netif_carrier_ok(tp->dev))
10240 if (msleep_interruptible(1000))
10247 /* Only test the commonly used registers */
10248 static int tg3_test_registers(struct tg3 *tp)
10250 int i, is_5705, is_5750;
10251 u32 offset, read_mask, write_mask, val, save_val, read_val;
10255 #define TG3_FL_5705 0x1
10256 #define TG3_FL_NOT_5705 0x2
10257 #define TG3_FL_NOT_5788 0x4
10258 #define TG3_FL_NOT_5750 0x8
10262 /* MAC Control Registers */
10263 { MAC_MODE, TG3_FL_NOT_5705,
10264 0x00000000, 0x00ef6f8c },
10265 { MAC_MODE, TG3_FL_5705,
10266 0x00000000, 0x01ef6b8c },
10267 { MAC_STATUS, TG3_FL_NOT_5705,
10268 0x03800107, 0x00000000 },
10269 { MAC_STATUS, TG3_FL_5705,
10270 0x03800100, 0x00000000 },
10271 { MAC_ADDR_0_HIGH, 0x0000,
10272 0x00000000, 0x0000ffff },
10273 { MAC_ADDR_0_LOW, 0x0000,
10274 0x00000000, 0xffffffff },
10275 { MAC_RX_MTU_SIZE, 0x0000,
10276 0x00000000, 0x0000ffff },
10277 { MAC_TX_MODE, 0x0000,
10278 0x00000000, 0x00000070 },
10279 { MAC_TX_LENGTHS, 0x0000,
10280 0x00000000, 0x00003fff },
10281 { MAC_RX_MODE, TG3_FL_NOT_5705,
10282 0x00000000, 0x000007fc },
10283 { MAC_RX_MODE, TG3_FL_5705,
10284 0x00000000, 0x000007dc },
10285 { MAC_HASH_REG_0, 0x0000,
10286 0x00000000, 0xffffffff },
10287 { MAC_HASH_REG_1, 0x0000,
10288 0x00000000, 0xffffffff },
10289 { MAC_HASH_REG_2, 0x0000,
10290 0x00000000, 0xffffffff },
10291 { MAC_HASH_REG_3, 0x0000,
10292 0x00000000, 0xffffffff },
10294 /* Receive Data and Receive BD Initiator Control Registers. */
10295 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10296 0x00000000, 0xffffffff },
10297 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10298 0x00000000, 0xffffffff },
10299 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10300 0x00000000, 0x00000003 },
10301 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10302 0x00000000, 0xffffffff },
10303 { RCVDBDI_STD_BD+0, 0x0000,
10304 0x00000000, 0xffffffff },
10305 { RCVDBDI_STD_BD+4, 0x0000,
10306 0x00000000, 0xffffffff },
10307 { RCVDBDI_STD_BD+8, 0x0000,
10308 0x00000000, 0xffff0002 },
10309 { RCVDBDI_STD_BD+0xc, 0x0000,
10310 0x00000000, 0xffffffff },
10312 /* Receive BD Initiator Control Registers. */
10313 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10314 0x00000000, 0xffffffff },
10315 { RCVBDI_STD_THRESH, TG3_FL_5705,
10316 0x00000000, 0x000003ff },
10317 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10318 0x00000000, 0xffffffff },
10320 /* Host Coalescing Control Registers. */
10321 { HOSTCC_MODE, TG3_FL_NOT_5705,
10322 0x00000000, 0x00000004 },
10323 { HOSTCC_MODE, TG3_FL_5705,
10324 0x00000000, 0x000000f6 },
10325 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10326 0x00000000, 0xffffffff },
10327 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10328 0x00000000, 0x000003ff },
10329 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10330 0x00000000, 0xffffffff },
10331 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10332 0x00000000, 0x000003ff },
10333 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10334 0x00000000, 0xffffffff },
10335 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10336 0x00000000, 0x000000ff },
10337 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10338 0x00000000, 0xffffffff },
10339 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10340 0x00000000, 0x000000ff },
10341 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10342 0x00000000, 0xffffffff },
10343 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10344 0x00000000, 0xffffffff },
10345 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10346 0x00000000, 0xffffffff },
10347 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10348 0x00000000, 0x000000ff },
10349 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10350 0x00000000, 0xffffffff },
10351 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10352 0x00000000, 0x000000ff },
10353 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10354 0x00000000, 0xffffffff },
10355 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10356 0x00000000, 0xffffffff },
10357 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10358 0x00000000, 0xffffffff },
10359 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10360 0x00000000, 0xffffffff },
10361 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10362 0x00000000, 0xffffffff },
10363 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10364 0xffffffff, 0x00000000 },
10365 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10366 0xffffffff, 0x00000000 },
10368 /* Buffer Manager Control Registers. */
10369 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10370 0x00000000, 0x007fff80 },
10371 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10372 0x00000000, 0x007fffff },
10373 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10374 0x00000000, 0x0000003f },
10375 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10376 0x00000000, 0x000001ff },
10377 { BUFMGR_MB_HIGH_WATER, 0x0000,
10378 0x00000000, 0x000001ff },
10379 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10380 0xffffffff, 0x00000000 },
10381 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10382 0xffffffff, 0x00000000 },
10384 /* Mailbox Registers */
10385 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10386 0x00000000, 0x000001ff },
10387 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10388 0x00000000, 0x000001ff },
10389 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10390 0x00000000, 0x000007ff },
10391 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10392 0x00000000, 0x000001ff },
10394 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10397 is_5705 = is_5750 = 0;
10398 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10400 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10404 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10405 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10408 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10411 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10412 (reg_tbl[i].flags & TG3_FL_NOT_5788))
10415 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10418 offset = (u32) reg_tbl[i].offset;
10419 read_mask = reg_tbl[i].read_mask;
10420 write_mask = reg_tbl[i].write_mask;
10422 /* Save the original register content */
10423 save_val = tr32(offset);
10425 /* Determine the read-only value. */
10426 read_val = save_val & read_mask;
10428 /* Write zero to the register, then make sure the read-only bits
10429 * are not changed and the read/write bits are all zeros.
10433 val = tr32(offset);
10435 /* Test the read-only and read/write bits. */
10436 if (((val & read_mask) != read_val) || (val & write_mask))
10439 /* Write ones to all the bits defined by RdMask and WrMask, then
10440 * make sure the read-only bits are not changed and the
10441 * read/write bits are all ones.
10443 tw32(offset, read_mask | write_mask);
10445 val = tr32(offset);
10447 /* Test the read-only bits. */
10448 if ((val & read_mask) != read_val)
10451 /* Test the read/write bits. */
10452 if ((val & write_mask) != write_mask)
10455 tw32(offset, save_val);
10461 if (netif_msg_hw(tp))
10462 netdev_err(tp->dev,
10463 "Register test failed at offset %x\n", offset);
10464 tw32(offset, save_val);
10468 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10470 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10474 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10475 for (j = 0; j < len; j += 4) {
10478 tg3_write_mem(tp, offset + j, test_pattern[i]);
10479 tg3_read_mem(tp, offset + j, &val);
10480 if (val != test_pattern[i])
10487 static int tg3_test_memory(struct tg3 *tp)
10489 static struct mem_entry {
10492 } mem_tbl_570x[] = {
10493 { 0x00000000, 0x00b50},
10494 { 0x00002000, 0x1c000},
10495 { 0xffffffff, 0x00000}
10496 }, mem_tbl_5705[] = {
10497 { 0x00000100, 0x0000c},
10498 { 0x00000200, 0x00008},
10499 { 0x00004000, 0x00800},
10500 { 0x00006000, 0x01000},
10501 { 0x00008000, 0x02000},
10502 { 0x00010000, 0x0e000},
10503 { 0xffffffff, 0x00000}
10504 }, mem_tbl_5755[] = {
10505 { 0x00000200, 0x00008},
10506 { 0x00004000, 0x00800},
10507 { 0x00006000, 0x00800},
10508 { 0x00008000, 0x02000},
10509 { 0x00010000, 0x0c000},
10510 { 0xffffffff, 0x00000}
10511 }, mem_tbl_5906[] = {
10512 { 0x00000200, 0x00008},
10513 { 0x00004000, 0x00400},
10514 { 0x00006000, 0x00400},
10515 { 0x00008000, 0x01000},
10516 { 0x00010000, 0x01000},
10517 { 0xffffffff, 0x00000}
10518 }, mem_tbl_5717[] = {
10519 { 0x00000200, 0x00008},
10520 { 0x00010000, 0x0a000},
10521 { 0x00020000, 0x13c00},
10522 { 0xffffffff, 0x00000}
10523 }, mem_tbl_57765[] = {
10524 { 0x00000200, 0x00008},
10525 { 0x00004000, 0x00800},
10526 { 0x00006000, 0x09800},
10527 { 0x00010000, 0x0a000},
10528 { 0xffffffff, 0x00000}
10530 struct mem_entry *mem_tbl;
10534 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
10535 mem_tbl = mem_tbl_5717;
10536 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10537 mem_tbl = mem_tbl_57765;
10538 else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10539 mem_tbl = mem_tbl_5755;
10540 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10541 mem_tbl = mem_tbl_5906;
10542 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10543 mem_tbl = mem_tbl_5705;
10545 mem_tbl = mem_tbl_570x;
10547 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10548 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10549 mem_tbl[i].len)) != 0)
10556 #define TG3_MAC_LOOPBACK 0
10557 #define TG3_PHY_LOOPBACK 1
10559 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10561 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10562 u32 desc_idx, coal_now;
10563 struct sk_buff *skb, *rx_skb;
10566 int num_pkts, tx_len, rx_len, i, err;
10567 struct tg3_rx_buffer_desc *desc;
10568 struct tg3_napi *tnapi, *rnapi;
10569 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
10571 tnapi = &tp->napi[0];
10572 rnapi = &tp->napi[0];
10573 if (tp->irq_cnt > 1) {
10574 rnapi = &tp->napi[1];
10575 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
10576 tnapi = &tp->napi[1];
10578 coal_now = tnapi->coal_now | rnapi->coal_now;
10580 if (loopback_mode == TG3_MAC_LOOPBACK) {
10581 /* HW errata - mac loopback fails in some cases on 5780.
10582 * Normal traffic and PHY loopback are not affected by
10585 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10588 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10589 MAC_MODE_PORT_INT_LPBACK;
10590 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10591 mac_mode |= MAC_MODE_LINK_POLARITY;
10592 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10593 mac_mode |= MAC_MODE_PORT_MODE_MII;
10595 mac_mode |= MAC_MODE_PORT_MODE_GMII;
10596 tw32(MAC_MODE, mac_mode);
10597 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10600 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10601 tg3_phy_fet_toggle_apd(tp, false);
10602 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10604 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10606 tg3_phy_toggle_automdix(tp, 0);
10608 tg3_writephy(tp, MII_BMCR, val);
10611 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10612 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10613 tg3_writephy(tp, MII_TG3_FET_PTEST,
10614 MII_TG3_FET_PTEST_FRC_TX_LINK |
10615 MII_TG3_FET_PTEST_FRC_TX_LOCK);
10616 /* The write needs to be flushed for the AC131 */
10617 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10618 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
10619 mac_mode |= MAC_MODE_PORT_MODE_MII;
10621 mac_mode |= MAC_MODE_PORT_MODE_GMII;
10623 /* reset to prevent losing 1st rx packet intermittently */
10624 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10625 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10627 tw32_f(MAC_RX_MODE, tp->rx_mode);
10629 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10630 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
10631 if (masked_phy_id == TG3_PHY_ID_BCM5401)
10632 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10633 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
10634 mac_mode |= MAC_MODE_LINK_POLARITY;
10635 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10636 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10638 tw32(MAC_MODE, mac_mode);
10646 skb = netdev_alloc_skb(tp->dev, tx_len);
10650 tx_data = skb_put(skb, tx_len);
10651 memcpy(tx_data, tp->dev->dev_addr, 6);
10652 memset(tx_data + 6, 0x0, 8);
10654 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10656 for (i = 14; i < tx_len; i++)
10657 tx_data[i] = (u8) (i & 0xff);
10659 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10660 if (pci_dma_mapping_error(tp->pdev, map)) {
10661 dev_kfree_skb(skb);
10665 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10670 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10674 tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10679 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10680 tr32_mailbox(tnapi->prodmbox);
10684 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
10685 for (i = 0; i < 35; i++) {
10686 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10691 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10692 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10693 if ((tx_idx == tnapi->tx_prod) &&
10694 (rx_idx == (rx_start_idx + num_pkts)))
10698 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10699 dev_kfree_skb(skb);
10701 if (tx_idx != tnapi->tx_prod)
10704 if (rx_idx != rx_start_idx + num_pkts)
10707 desc = &rnapi->rx_rcb[rx_start_idx];
10708 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10709 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10710 if (opaque_key != RXD_OPAQUE_RING_STD)
10713 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10714 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10717 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10718 if (rx_len != tx_len)
10721 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10723 map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10724 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10726 for (i = 14; i < tx_len; i++) {
10727 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10732 /* tg3_free_rings will unmap and free the rx_skb */
10737 #define TG3_MAC_LOOPBACK_FAILED 1
10738 #define TG3_PHY_LOOPBACK_FAILED 2
10739 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10740 TG3_PHY_LOOPBACK_FAILED)
10742 static int tg3_test_loopback(struct tg3 *tp)
10747 if (!netif_running(tp->dev))
10748 return TG3_LOOPBACK_FAILED;
10750 err = tg3_reset_hw(tp, 1);
10752 return TG3_LOOPBACK_FAILED;
10754 /* Turn off gphy autopowerdown. */
10755 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10756 tg3_phy_toggle_apd(tp, false);
10758 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10762 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10764 /* Wait for up to 40 microseconds to acquire lock. */
10765 for (i = 0; i < 4; i++) {
10766 status = tr32(TG3_CPMU_MUTEX_GNT);
10767 if (status == CPMU_MUTEX_GNT_DRIVER)
10772 if (status != CPMU_MUTEX_GNT_DRIVER)
10773 return TG3_LOOPBACK_FAILED;
10775 /* Turn off link-based power management. */
10776 cpmuctrl = tr32(TG3_CPMU_CTRL);
10777 tw32(TG3_CPMU_CTRL,
10778 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10779 CPMU_CTRL_LINK_AWARE_MODE));
10782 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10783 err |= TG3_MAC_LOOPBACK_FAILED;
10785 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10786 tw32(TG3_CPMU_CTRL, cpmuctrl);
10788 /* Release the mutex */
10789 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10792 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10793 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10794 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10795 err |= TG3_PHY_LOOPBACK_FAILED;
10798 /* Re-enable gphy autopowerdown. */
10799 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10800 tg3_phy_toggle_apd(tp, true);
10805 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10808 struct tg3 *tp = netdev_priv(dev);
10810 if (tp->link_config.phy_is_low_power)
10811 tg3_set_power_state(tp, PCI_D0);
10813 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10815 if (tg3_test_nvram(tp) != 0) {
10816 etest->flags |= ETH_TEST_FL_FAILED;
10819 if (tg3_test_link(tp) != 0) {
10820 etest->flags |= ETH_TEST_FL_FAILED;
10823 if (etest->flags & ETH_TEST_FL_OFFLINE) {
10824 int err, err2 = 0, irq_sync = 0;
10826 if (netif_running(dev)) {
10828 tg3_netif_stop(tp);
10832 tg3_full_lock(tp, irq_sync);
10834 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10835 err = tg3_nvram_lock(tp);
10836 tg3_halt_cpu(tp, RX_CPU_BASE);
10837 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10838 tg3_halt_cpu(tp, TX_CPU_BASE);
10840 tg3_nvram_unlock(tp);
10842 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10845 if (tg3_test_registers(tp) != 0) {
10846 etest->flags |= ETH_TEST_FL_FAILED;
10849 if (tg3_test_memory(tp) != 0) {
10850 etest->flags |= ETH_TEST_FL_FAILED;
10853 if ((data[4] = tg3_test_loopback(tp)) != 0)
10854 etest->flags |= ETH_TEST_FL_FAILED;
10856 tg3_full_unlock(tp);
10858 if (tg3_test_interrupt(tp) != 0) {
10859 etest->flags |= ETH_TEST_FL_FAILED;
10863 tg3_full_lock(tp, 0);
10865 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10866 if (netif_running(dev)) {
10867 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10868 err2 = tg3_restart_hw(tp, 1);
10870 tg3_netif_start(tp);
10873 tg3_full_unlock(tp);
10875 if (irq_sync && !err2)
10878 if (tp->link_config.phy_is_low_power)
10879 tg3_set_power_state(tp, PCI_D3hot);
10883 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10885 struct mii_ioctl_data *data = if_mii(ifr);
10886 struct tg3 *tp = netdev_priv(dev);
10889 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10890 struct phy_device *phydev;
10891 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10893 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10894 return phy_mii_ioctl(phydev, data, cmd);
10899 data->phy_id = tp->phy_addr;
10902 case SIOCGMIIREG: {
10905 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10906 break; /* We have no PHY */
10908 if (tp->link_config.phy_is_low_power)
10911 spin_lock_bh(&tp->lock);
10912 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10913 spin_unlock_bh(&tp->lock);
10915 data->val_out = mii_regval;
10921 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10922 break; /* We have no PHY */
10924 if (tp->link_config.phy_is_low_power)
10927 spin_lock_bh(&tp->lock);
10928 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10929 spin_unlock_bh(&tp->lock);
10937 return -EOPNOTSUPP;
10940 #if TG3_VLAN_TAG_USED
10941 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10943 struct tg3 *tp = netdev_priv(dev);
10945 if (!netif_running(dev)) {
10950 tg3_netif_stop(tp);
10952 tg3_full_lock(tp, 0);
10956 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10957 __tg3_set_rx_mode(dev);
10959 tg3_netif_start(tp);
10961 tg3_full_unlock(tp);
10965 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10967 struct tg3 *tp = netdev_priv(dev);
10969 memcpy(ec, &tp->coal, sizeof(*ec));
10973 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10975 struct tg3 *tp = netdev_priv(dev);
10976 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10977 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10979 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10980 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10981 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10982 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10983 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10986 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10987 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10988 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10989 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10990 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10991 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10992 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10993 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10994 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10995 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10998 /* No rx interrupts will be generated if both are zero */
10999 if ((ec->rx_coalesce_usecs == 0) &&
11000 (ec->rx_max_coalesced_frames == 0))
11003 /* No tx interrupts will be generated if both are zero */
11004 if ((ec->tx_coalesce_usecs == 0) &&
11005 (ec->tx_max_coalesced_frames == 0))
11008 /* Only copy relevant parameters, ignore all others. */
11009 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11010 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11011 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11012 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11013 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11014 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11015 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11016 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11017 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11019 if (netif_running(dev)) {
11020 tg3_full_lock(tp, 0);
11021 __tg3_set_coalesce(tp, &tp->coal);
11022 tg3_full_unlock(tp);
11027 static const struct ethtool_ops tg3_ethtool_ops = {
11028 .get_settings = tg3_get_settings,
11029 .set_settings = tg3_set_settings,
11030 .get_drvinfo = tg3_get_drvinfo,
11031 .get_regs_len = tg3_get_regs_len,
11032 .get_regs = tg3_get_regs,
11033 .get_wol = tg3_get_wol,
11034 .set_wol = tg3_set_wol,
11035 .get_msglevel = tg3_get_msglevel,
11036 .set_msglevel = tg3_set_msglevel,
11037 .nway_reset = tg3_nway_reset,
11038 .get_link = ethtool_op_get_link,
11039 .get_eeprom_len = tg3_get_eeprom_len,
11040 .get_eeprom = tg3_get_eeprom,
11041 .set_eeprom = tg3_set_eeprom,
11042 .get_ringparam = tg3_get_ringparam,
11043 .set_ringparam = tg3_set_ringparam,
11044 .get_pauseparam = tg3_get_pauseparam,
11045 .set_pauseparam = tg3_set_pauseparam,
11046 .get_rx_csum = tg3_get_rx_csum,
11047 .set_rx_csum = tg3_set_rx_csum,
11048 .set_tx_csum = tg3_set_tx_csum,
11049 .set_sg = ethtool_op_set_sg,
11050 .set_tso = tg3_set_tso,
11051 .self_test = tg3_self_test,
11052 .get_strings = tg3_get_strings,
11053 .phys_id = tg3_phys_id,
11054 .get_ethtool_stats = tg3_get_ethtool_stats,
11055 .get_coalesce = tg3_get_coalesce,
11056 .set_coalesce = tg3_set_coalesce,
11057 .get_sset_count = tg3_get_sset_count,
11060 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11062 u32 cursize, val, magic;
11064 tp->nvram_size = EEPROM_CHIP_SIZE;
11066 if (tg3_nvram_read(tp, 0, &magic) != 0)
11069 if ((magic != TG3_EEPROM_MAGIC) &&
11070 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11071 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11075 * Size the chip by reading offsets at increasing powers of two.
11076 * When we encounter our validation signature, we know the addressing
11077 * has wrapped around, and thus have our chip size.
11081 while (cursize < tp->nvram_size) {
11082 if (tg3_nvram_read(tp, cursize, &val) != 0)
11091 tp->nvram_size = cursize;
11094 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11098 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11099 tg3_nvram_read(tp, 0, &val) != 0)
11102 /* Selfboot format */
11103 if (val != TG3_EEPROM_MAGIC) {
11104 tg3_get_eeprom_size(tp);
11108 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11110 /* This is confusing. We want to operate on the
11111 * 16-bit value at offset 0xf2. The tg3_nvram_read()
11112 * call will read from NVRAM and byteswap the data
11113 * according to the byteswapping settings for all
11114 * other register accesses. This ensures the data we
11115 * want will always reside in the lower 16-bits.
11116 * However, the data in NVRAM is in LE format, which
11117 * means the data from the NVRAM read will always be
11118 * opposite the endianness of the CPU. The 16-bit
11119 * byteswap then brings the data to CPU endianness.
11121 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11125 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11128 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11132 nvcfg1 = tr32(NVRAM_CFG1);
11133 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11134 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11136 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11137 tw32(NVRAM_CFG1, nvcfg1);
11140 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11141 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11142 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11143 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11144 tp->nvram_jedecnum = JEDEC_ATMEL;
11145 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11146 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11148 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11149 tp->nvram_jedecnum = JEDEC_ATMEL;
11150 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11152 case FLASH_VENDOR_ATMEL_EEPROM:
11153 tp->nvram_jedecnum = JEDEC_ATMEL;
11154 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11155 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11157 case FLASH_VENDOR_ST:
11158 tp->nvram_jedecnum = JEDEC_ST;
11159 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11160 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11162 case FLASH_VENDOR_SAIFUN:
11163 tp->nvram_jedecnum = JEDEC_SAIFUN;
11164 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11166 case FLASH_VENDOR_SST_SMALL:
11167 case FLASH_VENDOR_SST_LARGE:
11168 tp->nvram_jedecnum = JEDEC_SST;
11169 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11173 tp->nvram_jedecnum = JEDEC_ATMEL;
11174 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11175 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11179 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11181 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11182 case FLASH_5752PAGE_SIZE_256:
11183 tp->nvram_pagesize = 256;
11185 case FLASH_5752PAGE_SIZE_512:
11186 tp->nvram_pagesize = 512;
11188 case FLASH_5752PAGE_SIZE_1K:
11189 tp->nvram_pagesize = 1024;
11191 case FLASH_5752PAGE_SIZE_2K:
11192 tp->nvram_pagesize = 2048;
11194 case FLASH_5752PAGE_SIZE_4K:
11195 tp->nvram_pagesize = 4096;
11197 case FLASH_5752PAGE_SIZE_264:
11198 tp->nvram_pagesize = 264;
11200 case FLASH_5752PAGE_SIZE_528:
11201 tp->nvram_pagesize = 528;
11206 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11210 nvcfg1 = tr32(NVRAM_CFG1);
11212 /* NVRAM protection for TPM */
11213 if (nvcfg1 & (1 << 27))
11214 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11216 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11217 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11218 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11219 tp->nvram_jedecnum = JEDEC_ATMEL;
11220 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11222 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11223 tp->nvram_jedecnum = JEDEC_ATMEL;
11224 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11225 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11227 case FLASH_5752VENDOR_ST_M45PE10:
11228 case FLASH_5752VENDOR_ST_M45PE20:
11229 case FLASH_5752VENDOR_ST_M45PE40:
11230 tp->nvram_jedecnum = JEDEC_ST;
11231 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11232 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11236 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11237 tg3_nvram_get_pagesize(tp, nvcfg1);
11239 /* For eeprom, set pagesize to maximum eeprom size */
11240 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11242 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11243 tw32(NVRAM_CFG1, nvcfg1);
11247 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11249 u32 nvcfg1, protect = 0;
11251 nvcfg1 = tr32(NVRAM_CFG1);
11253 /* NVRAM protection for TPM */
11254 if (nvcfg1 & (1 << 27)) {
11255 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11259 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11261 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11262 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11263 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11264 case FLASH_5755VENDOR_ATMEL_FLASH_5:
11265 tp->nvram_jedecnum = JEDEC_ATMEL;
11266 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11267 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11268 tp->nvram_pagesize = 264;
11269 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11270 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11271 tp->nvram_size = (protect ? 0x3e200 :
11272 TG3_NVRAM_SIZE_512KB);
11273 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11274 tp->nvram_size = (protect ? 0x1f200 :
11275 TG3_NVRAM_SIZE_256KB);
11277 tp->nvram_size = (protect ? 0x1f200 :
11278 TG3_NVRAM_SIZE_128KB);
11280 case FLASH_5752VENDOR_ST_M45PE10:
11281 case FLASH_5752VENDOR_ST_M45PE20:
11282 case FLASH_5752VENDOR_ST_M45PE40:
11283 tp->nvram_jedecnum = JEDEC_ST;
11284 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11285 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11286 tp->nvram_pagesize = 256;
11287 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11288 tp->nvram_size = (protect ?
11289 TG3_NVRAM_SIZE_64KB :
11290 TG3_NVRAM_SIZE_128KB);
11291 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11292 tp->nvram_size = (protect ?
11293 TG3_NVRAM_SIZE_64KB :
11294 TG3_NVRAM_SIZE_256KB);
11296 tp->nvram_size = (protect ?
11297 TG3_NVRAM_SIZE_128KB :
11298 TG3_NVRAM_SIZE_512KB);
11303 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11307 nvcfg1 = tr32(NVRAM_CFG1);
11309 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11310 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11311 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11312 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11313 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11314 tp->nvram_jedecnum = JEDEC_ATMEL;
11315 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11316 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11318 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11319 tw32(NVRAM_CFG1, nvcfg1);
11321 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11322 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11323 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11324 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11325 tp->nvram_jedecnum = JEDEC_ATMEL;
11326 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11327 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11328 tp->nvram_pagesize = 264;
11330 case FLASH_5752VENDOR_ST_M45PE10:
11331 case FLASH_5752VENDOR_ST_M45PE20:
11332 case FLASH_5752VENDOR_ST_M45PE40:
11333 tp->nvram_jedecnum = JEDEC_ST;
11334 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11335 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11336 tp->nvram_pagesize = 256;
11341 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11343 u32 nvcfg1, protect = 0;
11345 nvcfg1 = tr32(NVRAM_CFG1);
11347 /* NVRAM protection for TPM */
11348 if (nvcfg1 & (1 << 27)) {
11349 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11353 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11355 case FLASH_5761VENDOR_ATMEL_ADB021D:
11356 case FLASH_5761VENDOR_ATMEL_ADB041D:
11357 case FLASH_5761VENDOR_ATMEL_ADB081D:
11358 case FLASH_5761VENDOR_ATMEL_ADB161D:
11359 case FLASH_5761VENDOR_ATMEL_MDB021D:
11360 case FLASH_5761VENDOR_ATMEL_MDB041D:
11361 case FLASH_5761VENDOR_ATMEL_MDB081D:
11362 case FLASH_5761VENDOR_ATMEL_MDB161D:
11363 tp->nvram_jedecnum = JEDEC_ATMEL;
11364 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11365 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11366 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11367 tp->nvram_pagesize = 256;
11369 case FLASH_5761VENDOR_ST_A_M45PE20:
11370 case FLASH_5761VENDOR_ST_A_M45PE40:
11371 case FLASH_5761VENDOR_ST_A_M45PE80:
11372 case FLASH_5761VENDOR_ST_A_M45PE16:
11373 case FLASH_5761VENDOR_ST_M_M45PE20:
11374 case FLASH_5761VENDOR_ST_M_M45PE40:
11375 case FLASH_5761VENDOR_ST_M_M45PE80:
11376 case FLASH_5761VENDOR_ST_M_M45PE16:
11377 tp->nvram_jedecnum = JEDEC_ST;
11378 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11379 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11380 tp->nvram_pagesize = 256;
11385 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11388 case FLASH_5761VENDOR_ATMEL_ADB161D:
11389 case FLASH_5761VENDOR_ATMEL_MDB161D:
11390 case FLASH_5761VENDOR_ST_A_M45PE16:
11391 case FLASH_5761VENDOR_ST_M_M45PE16:
11392 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11394 case FLASH_5761VENDOR_ATMEL_ADB081D:
11395 case FLASH_5761VENDOR_ATMEL_MDB081D:
11396 case FLASH_5761VENDOR_ST_A_M45PE80:
11397 case FLASH_5761VENDOR_ST_M_M45PE80:
11398 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11400 case FLASH_5761VENDOR_ATMEL_ADB041D:
11401 case FLASH_5761VENDOR_ATMEL_MDB041D:
11402 case FLASH_5761VENDOR_ST_A_M45PE40:
11403 case FLASH_5761VENDOR_ST_M_M45PE40:
11404 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11406 case FLASH_5761VENDOR_ATMEL_ADB021D:
11407 case FLASH_5761VENDOR_ATMEL_MDB021D:
11408 case FLASH_5761VENDOR_ST_A_M45PE20:
11409 case FLASH_5761VENDOR_ST_M_M45PE20:
11410 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11416 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11418 tp->nvram_jedecnum = JEDEC_ATMEL;
11419 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11420 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11423 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11427 nvcfg1 = tr32(NVRAM_CFG1);
11429 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11430 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11431 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11432 tp->nvram_jedecnum = JEDEC_ATMEL;
11433 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11434 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11436 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11437 tw32(NVRAM_CFG1, nvcfg1);
11439 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11440 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11441 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11442 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11443 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11444 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11445 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11446 tp->nvram_jedecnum = JEDEC_ATMEL;
11447 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11448 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11450 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11451 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11452 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11453 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11454 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11456 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11457 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11458 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11460 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11461 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11462 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11466 case FLASH_5752VENDOR_ST_M45PE10:
11467 case FLASH_5752VENDOR_ST_M45PE20:
11468 case FLASH_5752VENDOR_ST_M45PE40:
11469 tp->nvram_jedecnum = JEDEC_ST;
11470 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11471 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11473 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11474 case FLASH_5752VENDOR_ST_M45PE10:
11475 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11477 case FLASH_5752VENDOR_ST_M45PE20:
11478 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11480 case FLASH_5752VENDOR_ST_M45PE40:
11481 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11486 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11490 tg3_nvram_get_pagesize(tp, nvcfg1);
11491 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11492 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11496 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11500 nvcfg1 = tr32(NVRAM_CFG1);
11502 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11503 case FLASH_5717VENDOR_ATMEL_EEPROM:
11504 case FLASH_5717VENDOR_MICRO_EEPROM:
11505 tp->nvram_jedecnum = JEDEC_ATMEL;
11506 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11507 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11509 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11510 tw32(NVRAM_CFG1, nvcfg1);
11512 case FLASH_5717VENDOR_ATMEL_MDB011D:
11513 case FLASH_5717VENDOR_ATMEL_ADB011B:
11514 case FLASH_5717VENDOR_ATMEL_ADB011D:
11515 case FLASH_5717VENDOR_ATMEL_MDB021D:
11516 case FLASH_5717VENDOR_ATMEL_ADB021B:
11517 case FLASH_5717VENDOR_ATMEL_ADB021D:
11518 case FLASH_5717VENDOR_ATMEL_45USPT:
11519 tp->nvram_jedecnum = JEDEC_ATMEL;
11520 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11521 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11523 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11524 case FLASH_5717VENDOR_ATMEL_MDB021D:
11525 case FLASH_5717VENDOR_ATMEL_ADB021B:
11526 case FLASH_5717VENDOR_ATMEL_ADB021D:
11527 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11530 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11534 case FLASH_5717VENDOR_ST_M_M25PE10:
11535 case FLASH_5717VENDOR_ST_A_M25PE10:
11536 case FLASH_5717VENDOR_ST_M_M45PE10:
11537 case FLASH_5717VENDOR_ST_A_M45PE10:
11538 case FLASH_5717VENDOR_ST_M_M25PE20:
11539 case FLASH_5717VENDOR_ST_A_M25PE20:
11540 case FLASH_5717VENDOR_ST_M_M45PE20:
11541 case FLASH_5717VENDOR_ST_A_M45PE20:
11542 case FLASH_5717VENDOR_ST_25USPT:
11543 case FLASH_5717VENDOR_ST_45USPT:
11544 tp->nvram_jedecnum = JEDEC_ST;
11545 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11546 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11548 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11549 case FLASH_5717VENDOR_ST_M_M25PE20:
11550 case FLASH_5717VENDOR_ST_A_M25PE20:
11551 case FLASH_5717VENDOR_ST_M_M45PE20:
11552 case FLASH_5717VENDOR_ST_A_M45PE20:
11553 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11556 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11561 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11565 tg3_nvram_get_pagesize(tp, nvcfg1);
11566 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11567 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11570 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11571 static void __devinit tg3_nvram_init(struct tg3 *tp)
11573 tw32_f(GRC_EEPROM_ADDR,
11574 (EEPROM_ADDR_FSM_RESET |
11575 (EEPROM_DEFAULT_CLOCK_PERIOD <<
11576 EEPROM_ADDR_CLKPERD_SHIFT)));
11580 /* Enable seeprom accesses. */
11581 tw32_f(GRC_LOCAL_CTRL,
11582 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11585 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11586 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11587 tp->tg3_flags |= TG3_FLAG_NVRAM;
11589 if (tg3_nvram_lock(tp)) {
11590 netdev_warn(tp->dev,
11591 "Cannot get nvram lock, %s failed\n",
11595 tg3_enable_nvram_access(tp);
11597 tp->nvram_size = 0;
11599 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11600 tg3_get_5752_nvram_info(tp);
11601 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11602 tg3_get_5755_nvram_info(tp);
11603 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11604 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11605 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11606 tg3_get_5787_nvram_info(tp);
11607 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11608 tg3_get_5761_nvram_info(tp);
11609 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11610 tg3_get_5906_nvram_info(tp);
11611 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11612 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11613 tg3_get_57780_nvram_info(tp);
11614 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11615 tg3_get_5717_nvram_info(tp);
11617 tg3_get_nvram_info(tp);
11619 if (tp->nvram_size == 0)
11620 tg3_get_nvram_size(tp);
11622 tg3_disable_nvram_access(tp);
11623 tg3_nvram_unlock(tp);
11626 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11628 tg3_get_eeprom_size(tp);
11632 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11633 u32 offset, u32 len, u8 *buf)
11638 for (i = 0; i < len; i += 4) {
11644 memcpy(&data, buf + i, 4);
11647 * The SEEPROM interface expects the data to always be opposite
11648 * the native endian format. We accomplish this by reversing
11649 * all the operations that would have been performed on the
11650 * data from a call to tg3_nvram_read_be32().
11652 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11654 val = tr32(GRC_EEPROM_ADDR);
11655 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11657 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11659 tw32(GRC_EEPROM_ADDR, val |
11660 (0 << EEPROM_ADDR_DEVID_SHIFT) |
11661 (addr & EEPROM_ADDR_ADDR_MASK) |
11662 EEPROM_ADDR_START |
11663 EEPROM_ADDR_WRITE);
11665 for (j = 0; j < 1000; j++) {
11666 val = tr32(GRC_EEPROM_ADDR);
11668 if (val & EEPROM_ADDR_COMPLETE)
11672 if (!(val & EEPROM_ADDR_COMPLETE)) {
11681 /* offset and length are dword aligned */
11682 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11686 u32 pagesize = tp->nvram_pagesize;
11687 u32 pagemask = pagesize - 1;
11691 tmp = kmalloc(pagesize, GFP_KERNEL);
11697 u32 phy_addr, page_off, size;
11699 phy_addr = offset & ~pagemask;
11701 for (j = 0; j < pagesize; j += 4) {
11702 ret = tg3_nvram_read_be32(tp, phy_addr + j,
11703 (__be32 *) (tmp + j));
11710 page_off = offset & pagemask;
11717 memcpy(tmp + page_off, buf, size);
11719 offset = offset + (pagesize - page_off);
11721 tg3_enable_nvram_access(tp);
11724 * Before we can erase the flash page, we need
11725 * to issue a special "write enable" command.
11727 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11729 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11732 /* Erase the target page */
11733 tw32(NVRAM_ADDR, phy_addr);
11735 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11736 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11738 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11741 /* Issue another write enable to start the write. */
11742 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11744 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11747 for (j = 0; j < pagesize; j += 4) {
11750 data = *((__be32 *) (tmp + j));
11752 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11754 tw32(NVRAM_ADDR, phy_addr + j);
11756 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11760 nvram_cmd |= NVRAM_CMD_FIRST;
11761 else if (j == (pagesize - 4))
11762 nvram_cmd |= NVRAM_CMD_LAST;
11764 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11771 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11772 tg3_nvram_exec_cmd(tp, nvram_cmd);
11779 /* offset and length are dword aligned */
11780 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11785 for (i = 0; i < len; i += 4, offset += 4) {
11786 u32 page_off, phy_addr, nvram_cmd;
11789 memcpy(&data, buf + i, 4);
11790 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11792 page_off = offset % tp->nvram_pagesize;
11794 phy_addr = tg3_nvram_phys_addr(tp, offset);
11796 tw32(NVRAM_ADDR, phy_addr);
11798 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11800 if (page_off == 0 || i == 0)
11801 nvram_cmd |= NVRAM_CMD_FIRST;
11802 if (page_off == (tp->nvram_pagesize - 4))
11803 nvram_cmd |= NVRAM_CMD_LAST;
11805 if (i == (len - 4))
11806 nvram_cmd |= NVRAM_CMD_LAST;
11808 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11809 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11810 (tp->nvram_jedecnum == JEDEC_ST) &&
11811 (nvram_cmd & NVRAM_CMD_FIRST)) {
11813 if ((ret = tg3_nvram_exec_cmd(tp,
11814 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11819 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11820 /* We always do complete word writes to eeprom. */
11821 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11824 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11830 /* offset and length are dword aligned */
11831 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11835 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11836 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11837 ~GRC_LCLCTRL_GPIO_OUTPUT1);
11841 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11842 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11846 ret = tg3_nvram_lock(tp);
11850 tg3_enable_nvram_access(tp);
11851 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11852 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
11853 tw32(NVRAM_WRITE1, 0x406);
11855 grc_mode = tr32(GRC_MODE);
11856 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11858 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11859 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11861 ret = tg3_nvram_write_block_buffered(tp, offset, len,
11864 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11868 grc_mode = tr32(GRC_MODE);
11869 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11871 tg3_disable_nvram_access(tp);
11872 tg3_nvram_unlock(tp);
11875 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11876 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11883 struct subsys_tbl_ent {
11884 u16 subsys_vendor, subsys_devid;
11888 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
11889 /* Broadcom boards. */
11890 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11891 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
11892 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11893 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
11894 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11895 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
11896 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11897 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
11898 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11899 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
11900 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11901 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
11902 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11903 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
11904 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11905 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
11906 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11907 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
11908 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11909 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
11910 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11911 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
11914 { TG3PCI_SUBVENDOR_ID_3COM,
11915 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
11916 { TG3PCI_SUBVENDOR_ID_3COM,
11917 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
11918 { TG3PCI_SUBVENDOR_ID_3COM,
11919 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
11920 { TG3PCI_SUBVENDOR_ID_3COM,
11921 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
11922 { TG3PCI_SUBVENDOR_ID_3COM,
11923 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
11926 { TG3PCI_SUBVENDOR_ID_DELL,
11927 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
11928 { TG3PCI_SUBVENDOR_ID_DELL,
11929 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
11930 { TG3PCI_SUBVENDOR_ID_DELL,
11931 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
11932 { TG3PCI_SUBVENDOR_ID_DELL,
11933 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
11935 /* Compaq boards. */
11936 { TG3PCI_SUBVENDOR_ID_COMPAQ,
11937 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
11938 { TG3PCI_SUBVENDOR_ID_COMPAQ,
11939 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
11940 { TG3PCI_SUBVENDOR_ID_COMPAQ,
11941 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
11942 { TG3PCI_SUBVENDOR_ID_COMPAQ,
11943 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
11944 { TG3PCI_SUBVENDOR_ID_COMPAQ,
11945 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
11948 { TG3PCI_SUBVENDOR_ID_IBM,
11949 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
11952 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
11956 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11957 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11958 tp->pdev->subsystem_vendor) &&
11959 (subsys_id_to_phy_id[i].subsys_devid ==
11960 tp->pdev->subsystem_device))
11961 return &subsys_id_to_phy_id[i];
11966 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
11971 /* On some early chips the SRAM cannot be accessed in D3hot state,
11972 * so need make sure we're in D0.
11974 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11975 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11976 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11979 /* Make sure register accesses (indirect or otherwise)
11980 * will function correctly.
11982 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11983 tp->misc_host_ctrl);
11985 /* The memory arbiter has to be enabled in order for SRAM accesses
11986 * to succeed. Normally on powerup the tg3 chip firmware will make
11987 * sure it is enabled, but other entities such as system netboot
11988 * code might disable it.
11990 val = tr32(MEMARB_MODE);
11991 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11993 tp->phy_id = TG3_PHY_ID_INVALID;
11994 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11996 /* Assume an onboard device and WOL capable by default. */
11997 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
11999 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12000 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12001 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12002 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12004 val = tr32(VCPU_CFGSHDW);
12005 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12006 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12007 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12008 (val & VCPU_CFGSHDW_WOL_MAGPKT))
12009 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12013 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12014 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12015 u32 nic_cfg, led_cfg;
12016 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12017 int eeprom_phy_serdes = 0;
12019 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12020 tp->nic_sram_data_cfg = nic_cfg;
12022 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12023 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12024 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12025 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12026 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12027 (ver > 0) && (ver < 0x100))
12028 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12030 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12031 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12033 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12034 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12035 eeprom_phy_serdes = 1;
12037 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12038 if (nic_phy_id != 0) {
12039 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12040 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12042 eeprom_phy_id = (id1 >> 16) << 10;
12043 eeprom_phy_id |= (id2 & 0xfc00) << 16;
12044 eeprom_phy_id |= (id2 & 0x03ff) << 0;
12048 tp->phy_id = eeprom_phy_id;
12049 if (eeprom_phy_serdes) {
12050 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
12051 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12052 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
12054 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12057 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12058 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12059 SHASTA_EXT_LED_MODE_MASK);
12061 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12065 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12066 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12069 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12070 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12073 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12074 tp->led_ctrl = LED_CTRL_MODE_MAC;
12076 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12077 * read on some older 5700/5701 bootcode.
12079 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12081 GET_ASIC_REV(tp->pci_chip_rev_id) ==
12083 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12087 case SHASTA_EXT_LED_SHARED:
12088 tp->led_ctrl = LED_CTRL_MODE_SHARED;
12089 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12090 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12091 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12092 LED_CTRL_MODE_PHY_2);
12095 case SHASTA_EXT_LED_MAC:
12096 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12099 case SHASTA_EXT_LED_COMBO:
12100 tp->led_ctrl = LED_CTRL_MODE_COMBO;
12101 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12102 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12103 LED_CTRL_MODE_PHY_2);
12108 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12109 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12110 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12111 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12113 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12114 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12116 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12117 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12118 if ((tp->pdev->subsystem_vendor ==
12119 PCI_VENDOR_ID_ARIMA) &&
12120 (tp->pdev->subsystem_device == 0x205a ||
12121 tp->pdev->subsystem_device == 0x2063))
12122 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12124 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12125 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12128 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12129 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12130 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12131 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12134 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12135 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12136 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12138 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
12139 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12140 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12142 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12143 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12144 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12146 if (cfg2 & (1 << 17))
12147 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
12149 /* serdes signal pre-emphasis in register 0x590 set by */
12150 /* bootcode if bit 18 is set */
12151 if (cfg2 & (1 << 18))
12152 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
12154 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12155 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
12156 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12157 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
12159 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12162 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12163 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12164 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12167 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12168 tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
12169 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12170 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12171 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12172 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12175 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12176 device_set_wakeup_enable(&tp->pdev->dev,
12177 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12180 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12185 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12186 tw32(OTP_CTRL, cmd);
12188 /* Wait for up to 1 ms for command to execute. */
12189 for (i = 0; i < 100; i++) {
12190 val = tr32(OTP_STATUS);
12191 if (val & OTP_STATUS_CMD_DONE)
12196 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12199 /* Read the gphy configuration from the OTP region of the chip. The gphy
12200 * configuration is a 32-bit value that straddles the alignment boundary.
12201 * We do two 32-bit reads and then shift and merge the results.
12203 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12205 u32 bhalf_otp, thalf_otp;
12207 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12209 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12212 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12214 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12217 thalf_otp = tr32(OTP_READ_DATA);
12219 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12221 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12224 bhalf_otp = tr32(OTP_READ_DATA);
12226 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12229 static int __devinit tg3_phy_probe(struct tg3 *tp)
12231 u32 hw_phy_id_1, hw_phy_id_2;
12232 u32 hw_phy_id, hw_phy_id_masked;
12235 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12236 return tg3_phy_init(tp);
12238 /* Reading the PHY ID register can conflict with ASF
12239 * firmware access to the PHY hardware.
12242 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12243 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12244 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
12246 /* Now read the physical PHY_ID from the chip and verify
12247 * that it is sane. If it doesn't look good, we fall back
12248 * to either the hard-coded table based PHY_ID and failing
12249 * that the value found in the eeprom area.
12251 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12252 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12254 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
12255 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12256 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
12258 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
12261 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
12262 tp->phy_id = hw_phy_id;
12263 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
12264 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12266 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
12268 if (tp->phy_id != TG3_PHY_ID_INVALID) {
12269 /* Do nothing, phy ID already set up in
12270 * tg3_get_eeprom_hw_cfg().
12273 struct subsys_tbl_ent *p;
12275 /* No eeprom signature? Try the hardcoded
12276 * subsys device table.
12278 p = tg3_lookup_by_subsys(tp);
12282 tp->phy_id = p->phy_id;
12284 tp->phy_id == TG3_PHY_ID_BCM8002)
12285 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12289 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
12290 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12291 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12292 u32 bmsr, adv_reg, tg3_ctrl, mask;
12294 tg3_readphy(tp, MII_BMSR, &bmsr);
12295 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12296 (bmsr & BMSR_LSTATUS))
12297 goto skip_phy_reset;
12299 err = tg3_phy_reset(tp);
12303 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12304 ADVERTISE_100HALF | ADVERTISE_100FULL |
12305 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12307 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12308 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12309 MII_TG3_CTRL_ADV_1000_FULL);
12310 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12311 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12312 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12313 MII_TG3_CTRL_ENABLE_AS_MASTER);
12316 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12317 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12318 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12319 if (!tg3_copper_is_advertising_all(tp, mask)) {
12320 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12322 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12323 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12325 tg3_writephy(tp, MII_BMCR,
12326 BMCR_ANENABLE | BMCR_ANRESTART);
12328 tg3_phy_set_wirespeed(tp);
12330 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12331 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12332 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12336 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
12337 err = tg3_init_5401phy_dsp(tp);
12341 err = tg3_init_5401phy_dsp(tp);
12344 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
12345 tp->link_config.advertising =
12346 (ADVERTISED_1000baseT_Half |
12347 ADVERTISED_1000baseT_Full |
12348 ADVERTISED_Autoneg |
12350 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12351 tp->link_config.advertising &=
12352 ~(ADVERTISED_1000baseT_Half |
12353 ADVERTISED_1000baseT_Full);
12358 static void __devinit tg3_read_vpd(struct tg3 *tp)
12360 u8 vpd_data[TG3_NVM_VPD_LEN];
12361 unsigned int block_end, rosize, len;
12365 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12366 tg3_nvram_read(tp, 0x0, &magic))
12367 goto out_not_found;
12369 if (magic == TG3_EEPROM_MAGIC) {
12370 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12373 /* The data is in little-endian format in NVRAM.
12374 * Use the big-endian read routines to preserve
12375 * the byte order as it exists in NVRAM.
12377 if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12378 goto out_not_found;
12380 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12384 unsigned int pos = 0;
12386 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12387 cnt = pci_read_vpd(tp->pdev, pos,
12388 TG3_NVM_VPD_LEN - pos,
12390 if (cnt == -ETIMEDOUT || -EINTR)
12393 goto out_not_found;
12395 if (pos != TG3_NVM_VPD_LEN)
12396 goto out_not_found;
12399 i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
12400 PCI_VPD_LRDT_RO_DATA);
12402 goto out_not_found;
12404 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
12405 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
12406 i += PCI_VPD_LRDT_TAG_SIZE;
12408 if (block_end > TG3_NVM_VPD_LEN)
12409 goto out_not_found;
12411 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12412 PCI_VPD_RO_KEYWORD_MFR_ID);
12414 len = pci_vpd_info_field_size(&vpd_data[j]);
12416 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12417 if (j + len > block_end || len != 4 ||
12418 memcmp(&vpd_data[j], "1028", 4))
12421 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12422 PCI_VPD_RO_KEYWORD_VENDOR0);
12426 len = pci_vpd_info_field_size(&vpd_data[j]);
12428 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12429 if (j + len > block_end)
12432 memcpy(tp->fw_ver, &vpd_data[j], len);
12433 strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
12437 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12438 PCI_VPD_RO_KEYWORD_PARTNO);
12440 goto out_not_found;
12442 len = pci_vpd_info_field_size(&vpd_data[i]);
12444 i += PCI_VPD_INFO_FLD_HDR_SIZE;
12445 if (len > TG3_BPN_SIZE ||
12446 (len + i) > TG3_NVM_VPD_LEN)
12447 goto out_not_found;
12449 memcpy(tp->board_part_number, &vpd_data[i], len);
12454 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12455 strcpy(tp->board_part_number, "BCM95906");
12456 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12457 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12458 strcpy(tp->board_part_number, "BCM57780");
12459 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12460 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12461 strcpy(tp->board_part_number, "BCM57760");
12462 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12463 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12464 strcpy(tp->board_part_number, "BCM57790");
12465 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12466 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12467 strcpy(tp->board_part_number, "BCM57788");
12468 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12469 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
12470 strcpy(tp->board_part_number, "BCM57761");
12471 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12472 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
12473 strcpy(tp->board_part_number, "BCM57765");
12474 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12475 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
12476 strcpy(tp->board_part_number, "BCM57781");
12477 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12478 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
12479 strcpy(tp->board_part_number, "BCM57785");
12480 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12481 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
12482 strcpy(tp->board_part_number, "BCM57791");
12483 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12484 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12485 strcpy(tp->board_part_number, "BCM57795");
12487 strcpy(tp->board_part_number, "none");
12490 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12494 if (tg3_nvram_read(tp, offset, &val) ||
12495 (val & 0xfc000000) != 0x0c000000 ||
12496 tg3_nvram_read(tp, offset + 4, &val) ||
12503 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12505 u32 val, offset, start, ver_offset;
12507 bool newver = false;
12509 if (tg3_nvram_read(tp, 0xc, &offset) ||
12510 tg3_nvram_read(tp, 0x4, &start))
12513 offset = tg3_nvram_logical_addr(tp, offset);
12515 if (tg3_nvram_read(tp, offset, &val))
12518 if ((val & 0xfc000000) == 0x0c000000) {
12519 if (tg3_nvram_read(tp, offset + 4, &val))
12526 dst_off = strlen(tp->fw_ver);
12529 if (TG3_VER_SIZE - dst_off < 16 ||
12530 tg3_nvram_read(tp, offset + 8, &ver_offset))
12533 offset = offset + ver_offset - start;
12534 for (i = 0; i < 16; i += 4) {
12536 if (tg3_nvram_read_be32(tp, offset + i, &v))
12539 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
12544 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12547 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12548 TG3_NVM_BCVER_MAJSFT;
12549 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12550 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
12551 "v%d.%02d", major, minor);
12555 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12557 u32 val, major, minor;
12559 /* Use native endian representation */
12560 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12563 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12564 TG3_NVM_HWSB_CFG1_MAJSFT;
12565 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12566 TG3_NVM_HWSB_CFG1_MINSFT;
12568 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12571 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12573 u32 offset, major, minor, build;
12575 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
12577 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12580 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12581 case TG3_EEPROM_SB_REVISION_0:
12582 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12584 case TG3_EEPROM_SB_REVISION_2:
12585 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12587 case TG3_EEPROM_SB_REVISION_3:
12588 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12590 case TG3_EEPROM_SB_REVISION_4:
12591 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
12593 case TG3_EEPROM_SB_REVISION_5:
12594 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
12600 if (tg3_nvram_read(tp, offset, &val))
12603 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12604 TG3_EEPROM_SB_EDH_BLD_SHFT;
12605 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12606 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12607 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
12609 if (minor > 99 || build > 26)
12612 offset = strlen(tp->fw_ver);
12613 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
12614 " v%d.%02d", major, minor);
12617 offset = strlen(tp->fw_ver);
12618 if (offset < TG3_VER_SIZE - 1)
12619 tp->fw_ver[offset] = 'a' + build - 1;
12623 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12625 u32 val, offset, start;
12628 for (offset = TG3_NVM_DIR_START;
12629 offset < TG3_NVM_DIR_END;
12630 offset += TG3_NVM_DIRENT_SIZE) {
12631 if (tg3_nvram_read(tp, offset, &val))
12634 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12638 if (offset == TG3_NVM_DIR_END)
12641 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12642 start = 0x08000000;
12643 else if (tg3_nvram_read(tp, offset - 4, &start))
12646 if (tg3_nvram_read(tp, offset + 4, &offset) ||
12647 !tg3_fw_img_is_valid(tp, offset) ||
12648 tg3_nvram_read(tp, offset + 8, &val))
12651 offset += val - start;
12653 vlen = strlen(tp->fw_ver);
12655 tp->fw_ver[vlen++] = ',';
12656 tp->fw_ver[vlen++] = ' ';
12658 for (i = 0; i < 4; i++) {
12660 if (tg3_nvram_read_be32(tp, offset, &v))
12663 offset += sizeof(v);
12665 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12666 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12670 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12675 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12680 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12681 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
12684 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12685 if (apedata != APE_SEG_SIG_MAGIC)
12688 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12689 if (!(apedata & APE_FW_STATUS_READY))
12692 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12694 vlen = strlen(tp->fw_ver);
12696 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12697 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12698 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12699 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12700 (apedata & APE_FW_VERSION_BLDMSK));
12703 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12706 bool vpd_vers = false;
12708 if (tp->fw_ver[0] != 0)
12711 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12712 strcat(tp->fw_ver, "sb");
12716 if (tg3_nvram_read(tp, 0, &val))
12719 if (val == TG3_EEPROM_MAGIC)
12720 tg3_read_bc_ver(tp);
12721 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12722 tg3_read_sb_ver(tp, val);
12723 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12724 tg3_read_hwsb_ver(tp);
12728 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12729 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
12732 tg3_read_mgmtfw_ver(tp);
12735 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12738 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12740 static int __devinit tg3_get_invariants(struct tg3 *tp)
12742 static struct pci_device_id write_reorder_chipsets[] = {
12743 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12744 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12745 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12746 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12747 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12748 PCI_DEVICE_ID_VIA_8385_0) },
12752 u32 pci_state_reg, grc_misc_cfg;
12757 /* Force memory write invalidate off. If we leave it on,
12758 * then on 5700_BX chips we have to enable a workaround.
12759 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12760 * to match the cacheline size. The Broadcom driver have this
12761 * workaround but turns MWI off all the times so never uses
12762 * it. This seems to suggest that the workaround is insufficient.
12764 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12765 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12766 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12768 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12769 * has the register indirect write enable bit set before
12770 * we try to access any of the MMIO registers. It is also
12771 * critical that the PCI-X hw workaround situation is decided
12772 * before that as well.
12774 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12777 tp->pci_chip_rev_id = (misc_ctrl_reg >>
12778 MISC_HOST_CTRL_CHIPREV_SHIFT);
12779 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12780 u32 prod_id_asic_rev;
12782 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12783 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12784 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724)
12785 pci_read_config_dword(tp->pdev,
12786 TG3PCI_GEN2_PRODID_ASICREV,
12787 &prod_id_asic_rev);
12788 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
12789 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
12790 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
12791 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
12792 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
12793 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12794 pci_read_config_dword(tp->pdev,
12795 TG3PCI_GEN15_PRODID_ASICREV,
12796 &prod_id_asic_rev);
12798 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12799 &prod_id_asic_rev);
12801 tp->pci_chip_rev_id = prod_id_asic_rev;
12804 /* Wrong chip ID in 5752 A0. This code can be removed later
12805 * as A0 is not in production.
12807 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12808 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12810 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12811 * we need to disable memory and use config. cycles
12812 * only to access all registers. The 5702/03 chips
12813 * can mistakenly decode the special cycles from the
12814 * ICH chipsets as memory write cycles, causing corruption
12815 * of register and memory space. Only certain ICH bridges
12816 * will drive special cycles with non-zero data during the
12817 * address phase which can fall within the 5703's address
12818 * range. This is not an ICH bug as the PCI spec allows
12819 * non-zero address during special cycles. However, only
12820 * these ICH bridges are known to drive non-zero addresses
12821 * during special cycles.
12823 * Since special cycles do not cross PCI bridges, we only
12824 * enable this workaround if the 5703 is on the secondary
12825 * bus of these ICH bridges.
12827 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12828 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12829 static struct tg3_dev_id {
12833 } ich_chipsets[] = {
12834 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12836 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12838 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12840 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12844 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12845 struct pci_dev *bridge = NULL;
12847 while (pci_id->vendor != 0) {
12848 bridge = pci_get_device(pci_id->vendor, pci_id->device,
12854 if (pci_id->rev != PCI_ANY_ID) {
12855 if (bridge->revision > pci_id->rev)
12858 if (bridge->subordinate &&
12859 (bridge->subordinate->number ==
12860 tp->pdev->bus->number)) {
12862 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12863 pci_dev_put(bridge);
12869 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12870 static struct tg3_dev_id {
12873 } bridge_chipsets[] = {
12874 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12875 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12878 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12879 struct pci_dev *bridge = NULL;
12881 while (pci_id->vendor != 0) {
12882 bridge = pci_get_device(pci_id->vendor,
12889 if (bridge->subordinate &&
12890 (bridge->subordinate->number <=
12891 tp->pdev->bus->number) &&
12892 (bridge->subordinate->subordinate >=
12893 tp->pdev->bus->number)) {
12894 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12895 pci_dev_put(bridge);
12901 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12902 * DMA addresses > 40-bit. This bridge may have other additional
12903 * 57xx devices behind it in some 4-port NIC designs for example.
12904 * Any tg3 device found behind the bridge will also need the 40-bit
12907 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12908 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12909 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
12910 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12911 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
12913 struct pci_dev *bridge = NULL;
12916 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12917 PCI_DEVICE_ID_SERVERWORKS_EPB,
12919 if (bridge && bridge->subordinate &&
12920 (bridge->subordinate->number <=
12921 tp->pdev->bus->number) &&
12922 (bridge->subordinate->subordinate >=
12923 tp->pdev->bus->number)) {
12924 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12925 pci_dev_put(bridge);
12931 /* Initialize misc host control in PCI block. */
12932 tp->misc_host_ctrl |= (misc_ctrl_reg &
12933 MISC_HOST_CTRL_CHIPREV);
12934 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12935 tp->misc_host_ctrl);
12937 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
12938 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
12939 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12940 tp->pdev_peer = tg3_find_peer(tp);
12942 /* Intentionally exclude ASIC_REV_5906 */
12943 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12944 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12945 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12946 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12947 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12948 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12949 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
12950 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
12951 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12953 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12954 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12955 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
12956 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12957 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12958 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12960 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12961 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12962 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12964 /* 5700 B0 chips do not support checksumming correctly due
12965 * to hardware bugs.
12967 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12968 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12970 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12971 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12972 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
12973 tp->dev->features |= NETIF_F_IPV6_CSUM;
12976 /* Determine TSO capabilities */
12977 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
12978 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
12979 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
12980 else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
12981 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12982 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
12983 else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
12984 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
12985 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
12986 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
12987 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
12988 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12989 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12990 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
12991 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
12992 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
12993 tp->fw_needed = FIRMWARE_TG3TSO5;
12995 tp->fw_needed = FIRMWARE_TG3TSO;
13000 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13001 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13002 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13003 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13004 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13005 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13006 tp->pdev_peer == tp->pdev))
13007 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13009 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13010 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13011 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13014 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13015 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13016 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13017 tp->irq_max = TG3_IRQ_MAX_VECS;
13021 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13022 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13023 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13024 else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13025 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13026 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13029 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13030 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13031 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13033 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13034 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13035 (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13036 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13038 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13041 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13042 if (tp->pcie_cap != 0) {
13045 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13047 pcie_set_readrq(tp->pdev, 4096);
13049 pci_read_config_word(tp->pdev,
13050 tp->pcie_cap + PCI_EXP_LNKCTL,
13052 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13053 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13054 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13055 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13056 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13057 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13058 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13059 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13060 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13061 tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13063 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13064 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13065 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13066 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13067 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13068 if (!tp->pcix_cap) {
13069 dev_err(&tp->pdev->dev,
13070 "Cannot find PCI-X capability, aborting\n");
13074 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13075 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13078 /* If we have an AMD 762 or VIA K8T800 chipset, write
13079 * reordering to the mailbox registers done by the host
13080 * controller can cause major troubles. We read back from
13081 * every mailbox register write to force the writes to be
13082 * posted to the chip in order.
13084 if (pci_dev_present(write_reorder_chipsets) &&
13085 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13086 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13088 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13089 &tp->pci_cacheline_sz);
13090 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13091 &tp->pci_lat_timer);
13092 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13093 tp->pci_lat_timer < 64) {
13094 tp->pci_lat_timer = 64;
13095 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13096 tp->pci_lat_timer);
13099 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13100 /* 5700 BX chips need to have their TX producer index
13101 * mailboxes written twice to workaround a bug.
13103 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13105 /* If we are in PCI-X mode, enable register write workaround.
13107 * The workaround is to use indirect register accesses
13108 * for all chip writes not to mailbox registers.
13110 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13113 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13115 /* The chip can have it's power management PCI config
13116 * space registers clobbered due to this bug.
13117 * So explicitly force the chip into D0 here.
13119 pci_read_config_dword(tp->pdev,
13120 tp->pm_cap + PCI_PM_CTRL,
13122 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13123 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13124 pci_write_config_dword(tp->pdev,
13125 tp->pm_cap + PCI_PM_CTRL,
13128 /* Also, force SERR#/PERR# in PCI command. */
13129 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13130 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13131 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13135 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13136 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13137 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13138 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13140 /* Chip-specific fixup from Broadcom driver */
13141 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13142 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13143 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13144 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13147 /* Default fast path register access methods */
13148 tp->read32 = tg3_read32;
13149 tp->write32 = tg3_write32;
13150 tp->read32_mbox = tg3_read32;
13151 tp->write32_mbox = tg3_write32;
13152 tp->write32_tx_mbox = tg3_write32;
13153 tp->write32_rx_mbox = tg3_write32;
13155 /* Various workaround register access methods */
13156 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13157 tp->write32 = tg3_write_indirect_reg32;
13158 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13159 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13160 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13162 * Back to back register writes can cause problems on these
13163 * chips, the workaround is to read back all reg writes
13164 * except those to mailbox regs.
13166 * See tg3_write_indirect_reg32().
13168 tp->write32 = tg3_write_flush_reg32;
13171 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13172 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13173 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13174 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13175 tp->write32_rx_mbox = tg3_write_flush_reg32;
13178 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13179 tp->read32 = tg3_read_indirect_reg32;
13180 tp->write32 = tg3_write_indirect_reg32;
13181 tp->read32_mbox = tg3_read_indirect_mbox;
13182 tp->write32_mbox = tg3_write_indirect_mbox;
13183 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13184 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13189 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13190 pci_cmd &= ~PCI_COMMAND_MEMORY;
13191 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13193 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13194 tp->read32_mbox = tg3_read32_mbox_5906;
13195 tp->write32_mbox = tg3_write32_mbox_5906;
13196 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13197 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13200 if (tp->write32 == tg3_write_indirect_reg32 ||
13201 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13202 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13203 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13204 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13206 /* Get eeprom hw config before calling tg3_set_power_state().
13207 * In particular, the TG3_FLG2_IS_NIC flag must be
13208 * determined before calling tg3_set_power_state() so that
13209 * we know whether or not to switch out of Vaux power.
13210 * When the flag is set, it means that GPIO1 is used for eeprom
13211 * write protect and also implies that it is a LOM where GPIOs
13212 * are not used to switch power.
13214 tg3_get_eeprom_hw_cfg(tp);
13216 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13217 /* Allow reads and writes to the
13218 * APE register and memory space.
13220 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13221 PCISTATE_ALLOW_APE_SHMEM_WR;
13222 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13226 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13227 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13228 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13229 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13230 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13231 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13232 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13234 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13235 * GPIO1 driven high will bring 5700's external PHY out of reset.
13236 * It is also used as eeprom write protect on LOMs.
13238 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13239 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13240 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13241 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13242 GRC_LCLCTRL_GPIO_OUTPUT1);
13243 /* Unused GPIO3 must be driven as output on 5752 because there
13244 * are no pull-up resistors on unused GPIO pins.
13246 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13247 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13249 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13250 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13251 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13252 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13254 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13255 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13256 /* Turn off the debug UART. */
13257 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13258 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13259 /* Keep VMain power. */
13260 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13261 GRC_LCLCTRL_GPIO_OUTPUT0;
13264 /* Force the chip into D0. */
13265 err = tg3_set_power_state(tp, PCI_D0);
13267 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
13271 /* Derive initial jumbo mode from MTU assigned in
13272 * ether_setup() via the alloc_etherdev() call
13274 if (tp->dev->mtu > ETH_DATA_LEN &&
13275 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13276 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13278 /* Determine WakeOnLan speed to use. */
13279 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13280 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13281 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13282 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13283 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13285 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13288 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13289 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
13291 /* A few boards don't want Ethernet@WireSpeed phy feature */
13292 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13293 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13294 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13295 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13296 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
13297 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
13298 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
13300 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13301 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13302 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
13303 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13304 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
13306 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13307 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
13308 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13309 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13310 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
13311 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
13312 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13313 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13314 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13315 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13316 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13317 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13318 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
13319 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13320 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
13322 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
13325 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13326 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13327 tp->phy_otp = tg3_read_otp_phycfg(tp);
13328 if (tp->phy_otp == 0)
13329 tp->phy_otp = TG3_OTP_DEFAULT;
13332 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13333 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13335 tp->mi_mode = MAC_MI_MODE_BASE;
13337 tp->coalesce_mode = 0;
13338 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13339 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13340 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13342 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13343 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13344 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13346 err = tg3_mdio_init(tp);
13350 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
13351 (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0 ||
13352 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
13355 /* Initialize data/descriptor byte/word swapping. */
13356 val = tr32(GRC_MODE);
13357 val &= GRC_MODE_HOST_STACKUP;
13358 tw32(GRC_MODE, val | tp->grc_mode);
13360 tg3_switch_clocks(tp);
13362 /* Clear this out for sanity. */
13363 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13365 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13367 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13368 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13369 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13371 if (chiprevid == CHIPREV_ID_5701_A0 ||
13372 chiprevid == CHIPREV_ID_5701_B0 ||
13373 chiprevid == CHIPREV_ID_5701_B2 ||
13374 chiprevid == CHIPREV_ID_5701_B5) {
13375 void __iomem *sram_base;
13377 /* Write some dummy words into the SRAM status block
13378 * area, see if it reads back correctly. If the return
13379 * value is bad, force enable the PCIX workaround.
13381 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13383 writel(0x00000000, sram_base);
13384 writel(0x00000000, sram_base + 4);
13385 writel(0xffffffff, sram_base + 4);
13386 if (readl(sram_base) != 0x00000000)
13387 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13392 tg3_nvram_init(tp);
13394 grc_misc_cfg = tr32(GRC_MISC_CFG);
13395 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13397 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13398 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13399 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13400 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13402 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13403 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13404 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13405 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13406 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13407 HOSTCC_MODE_CLRTICK_TXBD);
13409 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13410 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13411 tp->misc_host_ctrl);
13414 /* Preserve the APE MAC_MODE bits */
13415 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13416 tp->mac_mode = tr32(MAC_MODE) |
13417 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13419 tp->mac_mode = TG3_DEF_MAC_MODE;
13421 /* these are limited to 10/100 only */
13422 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13423 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13424 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13425 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13426 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13427 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13428 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13429 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13430 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13431 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13432 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13433 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13434 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13435 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
13436 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
13437 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13439 err = tg3_phy_probe(tp);
13441 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
13442 /* ... but do not return immediately ... */
13447 tg3_read_fw_ver(tp);
13449 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13450 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13452 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13453 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13455 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13458 /* 5700 {AX,BX} chips have a broken status block link
13459 * change bit implementation, so we must use the
13460 * status register in those cases.
13462 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13463 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13465 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13467 /* The led_ctrl is set during tg3_phy_probe, here we might
13468 * have to force the link status polling mechanism based
13469 * upon subsystem IDs.
13471 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13472 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13473 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13474 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13475 TG3_FLAG_USE_LINKCHG_REG);
13478 /* For all SERDES we poll the MAC status register. */
13479 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13480 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13482 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13484 tp->rx_offset = NET_IP_ALIGN;
13485 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
13486 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13487 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
13489 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
13490 tp->rx_copy_thresh = ~0;
13494 tp->rx_std_max_post = TG3_RX_RING_SIZE;
13496 /* Increment the rx prod index on the rx std ring by at most
13497 * 8 for these chips to workaround hw errata.
13499 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13500 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13501 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13502 tp->rx_std_max_post = 8;
13504 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13505 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13506 PCIE_PWR_MGMT_L1_THRESH_MSK;
13511 #ifdef CONFIG_SPARC
13512 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13514 struct net_device *dev = tp->dev;
13515 struct pci_dev *pdev = tp->pdev;
13516 struct device_node *dp = pci_device_to_OF_node(pdev);
13517 const unsigned char *addr;
13520 addr = of_get_property(dp, "local-mac-address", &len);
13521 if (addr && len == 6) {
13522 memcpy(dev->dev_addr, addr, 6);
13523 memcpy(dev->perm_addr, dev->dev_addr, 6);
13529 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13531 struct net_device *dev = tp->dev;
13533 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13534 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13539 static int __devinit tg3_get_device_address(struct tg3 *tp)
13541 struct net_device *dev = tp->dev;
13542 u32 hi, lo, mac_offset;
13545 #ifdef CONFIG_SPARC
13546 if (!tg3_get_macaddr_sparc(tp))
13551 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13552 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13553 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13555 if (tg3_nvram_lock(tp))
13556 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13558 tg3_nvram_unlock(tp);
13559 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13560 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13562 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13565 /* First try to get it from MAC address mailbox. */
13566 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13567 if ((hi >> 16) == 0x484b) {
13568 dev->dev_addr[0] = (hi >> 8) & 0xff;
13569 dev->dev_addr[1] = (hi >> 0) & 0xff;
13571 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13572 dev->dev_addr[2] = (lo >> 24) & 0xff;
13573 dev->dev_addr[3] = (lo >> 16) & 0xff;
13574 dev->dev_addr[4] = (lo >> 8) & 0xff;
13575 dev->dev_addr[5] = (lo >> 0) & 0xff;
13577 /* Some old bootcode may report a 0 MAC address in SRAM */
13578 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13581 /* Next, try NVRAM. */
13582 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13583 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13584 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13585 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13586 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13588 /* Finally just fetch it out of the MAC control regs. */
13590 hi = tr32(MAC_ADDR_0_HIGH);
13591 lo = tr32(MAC_ADDR_0_LOW);
13593 dev->dev_addr[5] = lo & 0xff;
13594 dev->dev_addr[4] = (lo >> 8) & 0xff;
13595 dev->dev_addr[3] = (lo >> 16) & 0xff;
13596 dev->dev_addr[2] = (lo >> 24) & 0xff;
13597 dev->dev_addr[1] = hi & 0xff;
13598 dev->dev_addr[0] = (hi >> 8) & 0xff;
13602 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13603 #ifdef CONFIG_SPARC
13604 if (!tg3_get_default_macaddr_sparc(tp))
13609 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13613 #define BOUNDARY_SINGLE_CACHELINE 1
13614 #define BOUNDARY_MULTI_CACHELINE 2
13616 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13618 int cacheline_size;
13622 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13624 cacheline_size = 1024;
13626 cacheline_size = (int) byte * 4;
13628 /* On 5703 and later chips, the boundary bits have no
13631 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13632 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13633 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13636 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13637 goal = BOUNDARY_MULTI_CACHELINE;
13639 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13640 goal = BOUNDARY_SINGLE_CACHELINE;
13646 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13647 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13648 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13655 /* PCI controllers on most RISC systems tend to disconnect
13656 * when a device tries to burst across a cache-line boundary.
13657 * Therefore, letting tg3 do so just wastes PCI bandwidth.
13659 * Unfortunately, for PCI-E there are only limited
13660 * write-side controls for this, and thus for reads
13661 * we will still get the disconnects. We'll also waste
13662 * these PCI cycles for both read and write for chips
13663 * other than 5700 and 5701 which do not implement the
13666 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13667 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13668 switch (cacheline_size) {
13673 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13674 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13675 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13677 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13678 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13683 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13684 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13688 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13689 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13692 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13693 switch (cacheline_size) {
13697 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13698 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13699 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13705 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13706 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13710 switch (cacheline_size) {
13712 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13713 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13714 DMA_RWCTRL_WRITE_BNDRY_16);
13719 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13720 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13721 DMA_RWCTRL_WRITE_BNDRY_32);
13726 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13727 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13728 DMA_RWCTRL_WRITE_BNDRY_64);
13733 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13734 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13735 DMA_RWCTRL_WRITE_BNDRY_128);
13740 val |= (DMA_RWCTRL_READ_BNDRY_256 |
13741 DMA_RWCTRL_WRITE_BNDRY_256);
13744 val |= (DMA_RWCTRL_READ_BNDRY_512 |
13745 DMA_RWCTRL_WRITE_BNDRY_512);
13749 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13750 DMA_RWCTRL_WRITE_BNDRY_1024);
13759 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13761 struct tg3_internal_buffer_desc test_desc;
13762 u32 sram_dma_descs;
13765 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13767 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13768 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13769 tw32(RDMAC_STATUS, 0);
13770 tw32(WDMAC_STATUS, 0);
13772 tw32(BUFMGR_MODE, 0);
13773 tw32(FTQ_RESET, 0);
13775 test_desc.addr_hi = ((u64) buf_dma) >> 32;
13776 test_desc.addr_lo = buf_dma & 0xffffffff;
13777 test_desc.nic_mbuf = 0x00002100;
13778 test_desc.len = size;
13781 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13782 * the *second* time the tg3 driver was getting loaded after an
13785 * Broadcom tells me:
13786 * ...the DMA engine is connected to the GRC block and a DMA
13787 * reset may affect the GRC block in some unpredictable way...
13788 * The behavior of resets to individual blocks has not been tested.
13790 * Broadcom noted the GRC reset will also reset all sub-components.
13793 test_desc.cqid_sqid = (13 << 8) | 2;
13795 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13798 test_desc.cqid_sqid = (16 << 8) | 7;
13800 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13803 test_desc.flags = 0x00000005;
13805 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13808 val = *(((u32 *)&test_desc) + i);
13809 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13810 sram_dma_descs + (i * sizeof(u32)));
13811 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13813 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13816 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13818 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13821 for (i = 0; i < 40; i++) {
13825 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13827 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13828 if ((val & 0xffff) == sram_dma_descs) {
13839 #define TEST_BUFFER_SIZE 0x2000
13841 static int __devinit tg3_test_dma(struct tg3 *tp)
13843 dma_addr_t buf_dma;
13844 u32 *buf, saved_dma_rwctrl;
13847 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13853 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13854 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13856 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13858 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13859 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13862 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13863 /* DMA read watermark not used on PCIE */
13864 tp->dma_rwctrl |= 0x00180000;
13865 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
13866 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13867 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
13868 tp->dma_rwctrl |= 0x003f0000;
13870 tp->dma_rwctrl |= 0x003f000f;
13872 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13873 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13874 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
13875 u32 read_water = 0x7;
13877 /* If the 5704 is behind the EPB bridge, we can
13878 * do the less restrictive ONE_DMA workaround for
13879 * better performance.
13881 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13882 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13883 tp->dma_rwctrl |= 0x8000;
13884 else if (ccval == 0x6 || ccval == 0x7)
13885 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13887 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13889 /* Set bit 23 to enable PCIX hw bug fix */
13891 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13892 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13894 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13895 /* 5780 always in PCIX mode */
13896 tp->dma_rwctrl |= 0x00144000;
13897 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13898 /* 5714 always in PCIX mode */
13899 tp->dma_rwctrl |= 0x00148000;
13901 tp->dma_rwctrl |= 0x001b000f;
13905 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13906 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13907 tp->dma_rwctrl &= 0xfffffff0;
13909 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13910 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13911 /* Remove this if it causes problems for some boards. */
13912 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13914 /* On 5700/5701 chips, we need to set this bit.
13915 * Otherwise the chip will issue cacheline transactions
13916 * to streamable DMA memory with not all the byte
13917 * enables turned on. This is an error on several
13918 * RISC PCI controllers, in particular sparc64.
13920 * On 5703/5704 chips, this bit has been reassigned
13921 * a different meaning. In particular, it is used
13922 * on those chips to enable a PCI-X workaround.
13924 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13927 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13930 /* Unneeded, already done by tg3_get_invariants. */
13931 tg3_switch_clocks(tp);
13934 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13935 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13938 /* It is best to perform DMA test with maximum write burst size
13939 * to expose the 5700/5701 write DMA bug.
13941 saved_dma_rwctrl = tp->dma_rwctrl;
13942 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13943 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13948 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13951 /* Send the buffer to the chip. */
13952 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
13954 dev_err(&tp->pdev->dev,
13955 "%s: Buffer write failed. err = %d\n",
13961 /* validate data reached card RAM correctly. */
13962 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13964 tg3_read_mem(tp, 0x2100 + (i*4), &val);
13965 if (le32_to_cpu(val) != p[i]) {
13966 dev_err(&tp->pdev->dev,
13967 "%s: Buffer corrupted on device! "
13968 "(%d != %d)\n", __func__, val, i);
13969 /* ret = -ENODEV here? */
13974 /* Now read it back. */
13975 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
13977 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
13978 "err = %d\n", __func__, ret);
13983 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13987 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13988 DMA_RWCTRL_WRITE_BNDRY_16) {
13989 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13990 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13991 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13994 dev_err(&tp->pdev->dev,
13995 "%s: Buffer corrupted on read back! "
13996 "(%d != %d)\n", __func__, p[i], i);
14002 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14008 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14009 DMA_RWCTRL_WRITE_BNDRY_16) {
14010 static struct pci_device_id dma_wait_state_chipsets[] = {
14011 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14012 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14016 /* DMA test passed without adjusting DMA boundary,
14017 * now look for chipsets that are known to expose the
14018 * DMA bug without failing the test.
14020 if (pci_dev_present(dma_wait_state_chipsets)) {
14021 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14022 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14024 /* Safe to use the calculated DMA boundary. */
14025 tp->dma_rwctrl = saved_dma_rwctrl;
14028 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14032 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14037 static void __devinit tg3_init_link_config(struct tg3 *tp)
14039 tp->link_config.advertising =
14040 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14041 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14042 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14043 ADVERTISED_Autoneg | ADVERTISED_MII);
14044 tp->link_config.speed = SPEED_INVALID;
14045 tp->link_config.duplex = DUPLEX_INVALID;
14046 tp->link_config.autoneg = AUTONEG_ENABLE;
14047 tp->link_config.active_speed = SPEED_INVALID;
14048 tp->link_config.active_duplex = DUPLEX_INVALID;
14049 tp->link_config.phy_is_low_power = 0;
14050 tp->link_config.orig_speed = SPEED_INVALID;
14051 tp->link_config.orig_duplex = DUPLEX_INVALID;
14052 tp->link_config.orig_autoneg = AUTONEG_INVALID;
14055 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14057 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14058 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
14059 tp->bufmgr_config.mbuf_read_dma_low_water =
14060 DEFAULT_MB_RDMA_LOW_WATER_5705;
14061 tp->bufmgr_config.mbuf_mac_rx_low_water =
14062 DEFAULT_MB_MACRX_LOW_WATER_57765;
14063 tp->bufmgr_config.mbuf_high_water =
14064 DEFAULT_MB_HIGH_WATER_57765;
14066 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14067 DEFAULT_MB_RDMA_LOW_WATER_5705;
14068 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14069 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14070 tp->bufmgr_config.mbuf_high_water_jumbo =
14071 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14072 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14073 tp->bufmgr_config.mbuf_read_dma_low_water =
14074 DEFAULT_MB_RDMA_LOW_WATER_5705;
14075 tp->bufmgr_config.mbuf_mac_rx_low_water =
14076 DEFAULT_MB_MACRX_LOW_WATER_5705;
14077 tp->bufmgr_config.mbuf_high_water =
14078 DEFAULT_MB_HIGH_WATER_5705;
14079 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14080 tp->bufmgr_config.mbuf_mac_rx_low_water =
14081 DEFAULT_MB_MACRX_LOW_WATER_5906;
14082 tp->bufmgr_config.mbuf_high_water =
14083 DEFAULT_MB_HIGH_WATER_5906;
14086 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14087 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14088 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14089 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14090 tp->bufmgr_config.mbuf_high_water_jumbo =
14091 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14093 tp->bufmgr_config.mbuf_read_dma_low_water =
14094 DEFAULT_MB_RDMA_LOW_WATER;
14095 tp->bufmgr_config.mbuf_mac_rx_low_water =
14096 DEFAULT_MB_MACRX_LOW_WATER;
14097 tp->bufmgr_config.mbuf_high_water =
14098 DEFAULT_MB_HIGH_WATER;
14100 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14101 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14102 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14103 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14104 tp->bufmgr_config.mbuf_high_water_jumbo =
14105 DEFAULT_MB_HIGH_WATER_JUMBO;
14108 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14109 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14112 static char * __devinit tg3_phy_string(struct tg3 *tp)
14114 switch (tp->phy_id & TG3_PHY_ID_MASK) {
14115 case TG3_PHY_ID_BCM5400: return "5400";
14116 case TG3_PHY_ID_BCM5401: return "5401";
14117 case TG3_PHY_ID_BCM5411: return "5411";
14118 case TG3_PHY_ID_BCM5701: return "5701";
14119 case TG3_PHY_ID_BCM5703: return "5703";
14120 case TG3_PHY_ID_BCM5704: return "5704";
14121 case TG3_PHY_ID_BCM5705: return "5705";
14122 case TG3_PHY_ID_BCM5750: return "5750";
14123 case TG3_PHY_ID_BCM5752: return "5752";
14124 case TG3_PHY_ID_BCM5714: return "5714";
14125 case TG3_PHY_ID_BCM5780: return "5780";
14126 case TG3_PHY_ID_BCM5755: return "5755";
14127 case TG3_PHY_ID_BCM5787: return "5787";
14128 case TG3_PHY_ID_BCM5784: return "5784";
14129 case TG3_PHY_ID_BCM5756: return "5722/5756";
14130 case TG3_PHY_ID_BCM5906: return "5906";
14131 case TG3_PHY_ID_BCM5761: return "5761";
14132 case TG3_PHY_ID_BCM5718C: return "5718C";
14133 case TG3_PHY_ID_BCM5718S: return "5718S";
14134 case TG3_PHY_ID_BCM57765: return "57765";
14135 case TG3_PHY_ID_BCM8002: return "8002/serdes";
14136 case 0: return "serdes";
14137 default: return "unknown";
14141 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14143 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14144 strcpy(str, "PCI Express");
14146 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14147 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14149 strcpy(str, "PCIX:");
14151 if ((clock_ctrl == 7) ||
14152 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14153 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14154 strcat(str, "133MHz");
14155 else if (clock_ctrl == 0)
14156 strcat(str, "33MHz");
14157 else if (clock_ctrl == 2)
14158 strcat(str, "50MHz");
14159 else if (clock_ctrl == 4)
14160 strcat(str, "66MHz");
14161 else if (clock_ctrl == 6)
14162 strcat(str, "100MHz");
14164 strcpy(str, "PCI:");
14165 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14166 strcat(str, "66MHz");
14168 strcat(str, "33MHz");
14170 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14171 strcat(str, ":32-bit");
14173 strcat(str, ":64-bit");
14177 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14179 struct pci_dev *peer;
14180 unsigned int func, devnr = tp->pdev->devfn & ~7;
14182 for (func = 0; func < 8; func++) {
14183 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14184 if (peer && peer != tp->pdev)
14188 /* 5704 can be configured in single-port mode, set peer to
14189 * tp->pdev in that case.
14197 * We don't need to keep the refcount elevated; there's no way
14198 * to remove one half of this device without removing the other
14205 static void __devinit tg3_init_coal(struct tg3 *tp)
14207 struct ethtool_coalesce *ec = &tp->coal;
14209 memset(ec, 0, sizeof(*ec));
14210 ec->cmd = ETHTOOL_GCOALESCE;
14211 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14212 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14213 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14214 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14215 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14216 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14217 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14218 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14219 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14221 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14222 HOSTCC_MODE_CLRTICK_TXBD)) {
14223 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14224 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14225 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14226 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14229 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14230 ec->rx_coalesce_usecs_irq = 0;
14231 ec->tx_coalesce_usecs_irq = 0;
14232 ec->stats_block_coalesce_usecs = 0;
14236 static const struct net_device_ops tg3_netdev_ops = {
14237 .ndo_open = tg3_open,
14238 .ndo_stop = tg3_close,
14239 .ndo_start_xmit = tg3_start_xmit,
14240 .ndo_get_stats = tg3_get_stats,
14241 .ndo_validate_addr = eth_validate_addr,
14242 .ndo_set_multicast_list = tg3_set_rx_mode,
14243 .ndo_set_mac_address = tg3_set_mac_addr,
14244 .ndo_do_ioctl = tg3_ioctl,
14245 .ndo_tx_timeout = tg3_tx_timeout,
14246 .ndo_change_mtu = tg3_change_mtu,
14247 #if TG3_VLAN_TAG_USED
14248 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14250 #ifdef CONFIG_NET_POLL_CONTROLLER
14251 .ndo_poll_controller = tg3_poll_controller,
14255 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14256 .ndo_open = tg3_open,
14257 .ndo_stop = tg3_close,
14258 .ndo_start_xmit = tg3_start_xmit_dma_bug,
14259 .ndo_get_stats = tg3_get_stats,
14260 .ndo_validate_addr = eth_validate_addr,
14261 .ndo_set_multicast_list = tg3_set_rx_mode,
14262 .ndo_set_mac_address = tg3_set_mac_addr,
14263 .ndo_do_ioctl = tg3_ioctl,
14264 .ndo_tx_timeout = tg3_tx_timeout,
14265 .ndo_change_mtu = tg3_change_mtu,
14266 #if TG3_VLAN_TAG_USED
14267 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14269 #ifdef CONFIG_NET_POLL_CONTROLLER
14270 .ndo_poll_controller = tg3_poll_controller,
14274 static int __devinit tg3_init_one(struct pci_dev *pdev,
14275 const struct pci_device_id *ent)
14277 struct net_device *dev;
14279 int i, err, pm_cap;
14280 u32 sndmbx, rcvmbx, intmbx;
14282 u64 dma_mask, persist_dma_mask;
14284 printk_once(KERN_INFO "%s\n", version);
14286 err = pci_enable_device(pdev);
14288 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
14292 err = pci_request_regions(pdev, DRV_MODULE_NAME);
14294 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
14295 goto err_out_disable_pdev;
14298 pci_set_master(pdev);
14300 /* Find power-management capability. */
14301 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14303 dev_err(&pdev->dev,
14304 "Cannot find Power Management capability, aborting\n");
14306 goto err_out_free_res;
14309 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14311 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
14313 goto err_out_free_res;
14316 SET_NETDEV_DEV(dev, &pdev->dev);
14318 #if TG3_VLAN_TAG_USED
14319 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14322 tp = netdev_priv(dev);
14325 tp->pm_cap = pm_cap;
14326 tp->rx_mode = TG3_DEF_RX_MODE;
14327 tp->tx_mode = TG3_DEF_TX_MODE;
14330 tp->msg_enable = tg3_debug;
14332 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14334 /* The word/byte swap controls here control register access byte
14335 * swapping. DMA data byte swapping is controlled in the GRC_MODE
14338 tp->misc_host_ctrl =
14339 MISC_HOST_CTRL_MASK_PCI_INT |
14340 MISC_HOST_CTRL_WORD_SWAP |
14341 MISC_HOST_CTRL_INDIR_ACCESS |
14342 MISC_HOST_CTRL_PCISTATE_RW;
14344 /* The NONFRM (non-frame) byte/word swap controls take effect
14345 * on descriptor entries, anything which isn't packet data.
14347 * The StrongARM chips on the board (one for tx, one for rx)
14348 * are running in big-endian mode.
14350 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14351 GRC_MODE_WSWAP_NONFRM_DATA);
14352 #ifdef __BIG_ENDIAN
14353 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14355 spin_lock_init(&tp->lock);
14356 spin_lock_init(&tp->indirect_lock);
14357 INIT_WORK(&tp->reset_task, tg3_reset_task);
14359 tp->regs = pci_ioremap_bar(pdev, BAR_0);
14361 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
14363 goto err_out_free_dev;
14366 tg3_init_link_config(tp);
14368 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14369 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14371 dev->ethtool_ops = &tg3_ethtool_ops;
14372 dev->watchdog_timeo = TG3_TX_TIMEOUT;
14373 dev->irq = pdev->irq;
14375 err = tg3_get_invariants(tp);
14377 dev_err(&pdev->dev,
14378 "Problem fetching invariants of chip, aborting\n");
14379 goto err_out_iounmap;
14382 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14383 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
14384 dev->netdev_ops = &tg3_netdev_ops;
14386 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14389 /* The EPB bridge inside 5714, 5715, and 5780 and any
14390 * device behind the EPB cannot support DMA addresses > 40-bit.
14391 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14392 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14393 * do DMA address check in tg3_start_xmit().
14395 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14396 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14397 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14398 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14399 #ifdef CONFIG_HIGHMEM
14400 dma_mask = DMA_BIT_MASK(64);
14403 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14405 /* Configure DMA attributes. */
14406 if (dma_mask > DMA_BIT_MASK(32)) {
14407 err = pci_set_dma_mask(pdev, dma_mask);
14409 dev->features |= NETIF_F_HIGHDMA;
14410 err = pci_set_consistent_dma_mask(pdev,
14413 dev_err(&pdev->dev, "Unable to obtain 64 bit "
14414 "DMA for consistent allocations\n");
14415 goto err_out_iounmap;
14419 if (err || dma_mask == DMA_BIT_MASK(32)) {
14420 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14422 dev_err(&pdev->dev,
14423 "No usable DMA configuration, aborting\n");
14424 goto err_out_iounmap;
14428 tg3_init_bufmgr_config(tp);
14430 /* Selectively allow TSO based on operating conditions */
14431 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14432 (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14433 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14435 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14436 tp->fw_needed = NULL;
14439 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14440 tp->fw_needed = FIRMWARE_TG3;
14442 /* TSO is on by default on chips that support hardware TSO.
14443 * Firmware TSO on older chips gives lower performance, so it
14444 * is off by default, but can be enabled using ethtool.
14446 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14447 (dev->features & NETIF_F_IP_CSUM))
14448 dev->features |= NETIF_F_TSO;
14450 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14451 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14452 if (dev->features & NETIF_F_IPV6_CSUM)
14453 dev->features |= NETIF_F_TSO6;
14454 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14455 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14456 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14457 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14458 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14459 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
14460 dev->features |= NETIF_F_TSO_ECN;
14463 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14464 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14465 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14466 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14467 tp->rx_pending = 63;
14470 err = tg3_get_device_address(tp);
14472 dev_err(&pdev->dev,
14473 "Could not obtain valid ethernet address, aborting\n");
14474 goto err_out_iounmap;
14477 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14478 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14479 if (!tp->aperegs) {
14480 dev_err(&pdev->dev,
14481 "Cannot map APE registers, aborting\n");
14483 goto err_out_iounmap;
14486 tg3_ape_lock_init(tp);
14488 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14489 tg3_read_dash_ver(tp);
14493 * Reset chip in case UNDI or EFI driver did not shutdown
14494 * DMA self test will enable WDMAC and we'll see (spurious)
14495 * pending DMA on the PCI bus at that point.
14497 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14498 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14499 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14500 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14503 err = tg3_test_dma(tp);
14505 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
14506 goto err_out_apeunmap;
14509 /* flow control autonegotiation is default behavior */
14510 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14511 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14513 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14514 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14515 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14516 for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14517 struct tg3_napi *tnapi = &tp->napi[i];
14520 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14522 tnapi->int_mbox = intmbx;
14528 tnapi->consmbox = rcvmbx;
14529 tnapi->prodmbox = sndmbx;
14532 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14533 netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14535 tnapi->coal_now = HOSTCC_MODE_NOW;
14536 netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14539 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14543 * If we support MSIX, we'll be using RSS. If we're using
14544 * RSS, the first vector only handles link interrupts and the
14545 * remaining vectors handle rx and tx interrupts. Reuse the
14546 * mailbox values for the next iteration. The values we setup
14547 * above are still useful for the single vectored mode.
14562 pci_set_drvdata(pdev, dev);
14564 err = register_netdev(dev);
14566 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
14567 goto err_out_apeunmap;
14570 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14571 tp->board_part_number,
14572 tp->pci_chip_rev_id,
14573 tg3_bus_string(tp, str),
14576 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14577 struct phy_device *phydev;
14578 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14580 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14581 phydev->drv->name, dev_name(&phydev->dev));
14583 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
14584 "(WireSpeed[%d])\n", tg3_phy_string(tp),
14585 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14586 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14587 "10/100/1000Base-T")),
14588 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14590 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14591 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14592 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14593 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14594 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14595 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14596 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14598 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
14599 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
14605 iounmap(tp->aperegs);
14606 tp->aperegs = NULL;
14619 pci_release_regions(pdev);
14621 err_out_disable_pdev:
14622 pci_disable_device(pdev);
14623 pci_set_drvdata(pdev, NULL);
14627 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14629 struct net_device *dev = pci_get_drvdata(pdev);
14632 struct tg3 *tp = netdev_priv(dev);
14635 release_firmware(tp->fw);
14637 flush_scheduled_work();
14639 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14644 unregister_netdev(dev);
14646 iounmap(tp->aperegs);
14647 tp->aperegs = NULL;
14654 pci_release_regions(pdev);
14655 pci_disable_device(pdev);
14656 pci_set_drvdata(pdev, NULL);
14660 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14662 struct net_device *dev = pci_get_drvdata(pdev);
14663 struct tg3 *tp = netdev_priv(dev);
14664 pci_power_t target_state;
14667 /* PCI register 4 needs to be saved whether netif_running() or not.
14668 * MSI address and data need to be saved if using MSI and
14671 pci_save_state(pdev);
14673 if (!netif_running(dev))
14676 flush_scheduled_work();
14678 tg3_netif_stop(tp);
14680 del_timer_sync(&tp->timer);
14682 tg3_full_lock(tp, 1);
14683 tg3_disable_ints(tp);
14684 tg3_full_unlock(tp);
14686 netif_device_detach(dev);
14688 tg3_full_lock(tp, 0);
14689 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14690 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14691 tg3_full_unlock(tp);
14693 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14695 err = tg3_set_power_state(tp, target_state);
14699 tg3_full_lock(tp, 0);
14701 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14702 err2 = tg3_restart_hw(tp, 1);
14706 tp->timer.expires = jiffies + tp->timer_offset;
14707 add_timer(&tp->timer);
14709 netif_device_attach(dev);
14710 tg3_netif_start(tp);
14713 tg3_full_unlock(tp);
14722 static int tg3_resume(struct pci_dev *pdev)
14724 struct net_device *dev = pci_get_drvdata(pdev);
14725 struct tg3 *tp = netdev_priv(dev);
14728 pci_restore_state(tp->pdev);
14730 if (!netif_running(dev))
14733 err = tg3_set_power_state(tp, PCI_D0);
14737 netif_device_attach(dev);
14739 tg3_full_lock(tp, 0);
14741 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14742 err = tg3_restart_hw(tp, 1);
14746 tp->timer.expires = jiffies + tp->timer_offset;
14747 add_timer(&tp->timer);
14749 tg3_netif_start(tp);
14752 tg3_full_unlock(tp);
14760 static struct pci_driver tg3_driver = {
14761 .name = DRV_MODULE_NAME,
14762 .id_table = tg3_pci_tbl,
14763 .probe = tg3_init_one,
14764 .remove = __devexit_p(tg3_remove_one),
14765 .suspend = tg3_suspend,
14766 .resume = tg3_resume
14769 static int __init tg3_init(void)
14771 return pci_register_driver(&tg3_driver);
14774 static void __exit tg3_cleanup(void)
14776 pci_unregister_driver(&tg3_driver);
14779 module_init(tg3_init);
14780 module_exit(tg3_cleanup);