drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2010 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/phy.h>
  36 #include <linux/brcmphy.h>
  37 #include <linux/if_vlan.h>
  38 #include <linux/ip.h>
  39 #include <linux/tcp.h>
  40 #include <linux/workqueue.h>
  41 #include <linux/prefetch.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/firmware.h>
  44
  45 #include <net/checksum.h>
  46 #include <net/ip.h>
  47
  48 #include <asm/system.h>
  49 #include <asm/io.h>
  50 #include <asm/byteorder.h>
  51 #include <asm/uaccess.h>
  52
  53 #ifdef CONFIG_SPARC
  54 #include <asm/idprom.h>
  55 #include <asm/prom.h>
  56 #endif
  57
  58 #define BAR_0   0
  59 #define BAR_2   2
  60
  61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  62 #define TG3_VLAN_TAG_USED 1
  63 #else
  64 #define TG3_VLAN_TAG_USED 0
  65 #endif
  66
  67 #include "tg3.h"
  68
  69 #define DRV_MODULE_NAME         "tg3"
  70 #define DRV_MODULE_VERSION      "3.108"
  71 #define DRV_MODULE_RELDATE      "February 17, 2010"
  72
  73 #define TG3_DEF_MAC_MODE        0
  74 #define TG3_DEF_RX_MODE         0
  75 #define TG3_DEF_TX_MODE         0
  76 #define TG3_DEF_MSG_ENABLE        \
  77         (NETIF_MSG_DRV          | \
  78          NETIF_MSG_PROBE        | \
  79          NETIF_MSG_LINK         | \
  80          NETIF_MSG_TIMER        | \
  81          NETIF_MSG_IFDOWN       | \
  82          NETIF_MSG_IFUP         | \
  83          NETIF_MSG_RX_ERR       | \
  84          NETIF_MSG_TX_ERR)
  85
  86 /* length of time before we decide the hardware is borked,
  87  * and dev->tx_timeout() should be called to fix the problem
  88  */
  89 #define TG3_TX_TIMEOUT                  (5 * HZ)
  90
  91 /* hardware minimum and maximum for a single frame's data payload */
  92 #define TG3_MIN_MTU                     60
  93 #define TG3_MAX_MTU(tp) \
  94         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  95
  96 /* These numbers seem to be hard coded in the NIC firmware somehow.
  97  * You can't change the ring sizes, but you can change where you place
  98  * them in the NIC onboard memory.
  99  */
 100 #define TG3_RX_RING_SIZE                512
 101 #define TG3_DEF_RX_RING_PENDING         200
 102 #define TG3_RX_JUMBO_RING_SIZE          256
 103 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 104 #define TG3_RSS_INDIR_TBL_SIZE 128
 105
 106 /* Do not place this n-ring entries value into the tp struct itself,
 107  * we really want to expose these constants to GCC so that modulo et
 108  * al.  operations are done with shifts and masks instead of with
 109  * hw multiply/modulo instructions.  Another solution would be to
 110  * replace things like '% foo' with '& (foo - 1)'.
 111  */
 112 #define TG3_RX_RCB_RING_SIZE(tp)        \
 113         (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
 114           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
 115
 116 #define TG3_TX_RING_SIZE                512
 117 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 118
 119 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 120                                  TG3_RX_RING_SIZE)
 121 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
 122                                  TG3_RX_JUMBO_RING_SIZE)
 123 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 124                                  TG3_RX_RCB_RING_SIZE(tp))
 125 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 126                                  TG3_TX_RING_SIZE)
 127 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 128
 129 #define TG3_DMA_BYTE_ENAB               64
 130
 131 #define TG3_RX_STD_DMA_SZ               1536
 132 #define TG3_RX_JMB_DMA_SZ               9046
 133
 134 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 135
 136 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 137 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 138
 139 #define TG3_RX_STD_BUFF_RING_SIZE \
 140         (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
 141
 142 #define TG3_RX_JMB_BUFF_RING_SIZE \
 143         (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
 144
 145 /* minimum number of free TX descriptors required to wake up TX process */
 146 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 147
 148 #define TG3_RAW_IP_ALIGN 2
 149
 150 /* number of ETHTOOL_GSTATS u64's */
 151 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 152
 153 #define TG3_NUM_TEST            6
 154
 155 #define FIRMWARE_TG3            "tigon/tg3.bin"
 156 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 157 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 158
 159 static char version[] __devinitdata =
 160         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
 161
 162 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 163 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 164 MODULE_LICENSE("GPL");
 165 MODULE_VERSION(DRV_MODULE_VERSION);
 166 MODULE_FIRMWARE(FIRMWARE_TG3);
 167 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 168 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 169
 170 #define TG3_RSS_MIN_NUM_MSIX_VECS       2
 171
 172 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 173 module_param(tg3_debug, int, 0);
 174 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 175
 176 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
 177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
 244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
 245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
 246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
 247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
 248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
 249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
 250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
 251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
 252         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 253         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 254         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 255         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 256         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 257         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 258         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 259         {}
 260 };
 261
 262 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 263
 264 static const struct {
 265         const char string[ETH_GSTRING_LEN];
 266 } ethtool_stats_keys[TG3_NUM_STATS] = {
 267         { "rx_octets" },
 268         { "rx_fragments" },
 269         { "rx_ucast_packets" },
 270         { "rx_mcast_packets" },
 271         { "rx_bcast_packets" },
 272         { "rx_fcs_errors" },
 273         { "rx_align_errors" },
 274         { "rx_xon_pause_rcvd" },
 275         { "rx_xoff_pause_rcvd" },
 276         { "rx_mac_ctrl_rcvd" },
 277         { "rx_xoff_entered" },
 278         { "rx_frame_too_long_errors" },
 279         { "rx_jabbers" },
 280         { "rx_undersize_packets" },
 281         { "rx_in_length_errors" },
 282         { "rx_out_length_errors" },
 283         { "rx_64_or_less_octet_packets" },
 284         { "rx_65_to_127_octet_packets" },
 285         { "rx_128_to_255_octet_packets" },
 286         { "rx_256_to_511_octet_packets" },
 287         { "rx_512_to_1023_octet_packets" },
 288         { "rx_1024_to_1522_octet_packets" },
 289         { "rx_1523_to_2047_octet_packets" },
 290         { "rx_2048_to_4095_octet_packets" },
 291         { "rx_4096_to_8191_octet_packets" },
 292         { "rx_8192_to_9022_octet_packets" },
 293
 294         { "tx_octets" },
 295         { "tx_collisions" },
 296
 297         { "tx_xon_sent" },
 298         { "tx_xoff_sent" },
 299         { "tx_flow_control" },
 300         { "tx_mac_errors" },
 301         { "tx_single_collisions" },
 302         { "tx_mult_collisions" },
 303         { "tx_deferred" },
 304         { "tx_excessive_collisions" },
 305         { "tx_late_collisions" },
 306         { "tx_collide_2times" },
 307         { "tx_collide_3times" },
 308         { "tx_collide_4times" },
 309         { "tx_collide_5times" },
 310         { "tx_collide_6times" },
 311         { "tx_collide_7times" },
 312         { "tx_collide_8times" },
 313         { "tx_collide_9times" },
 314         { "tx_collide_10times" },
 315         { "tx_collide_11times" },
 316         { "tx_collide_12times" },
 317         { "tx_collide_13times" },
 318         { "tx_collide_14times" },
 319         { "tx_collide_15times" },
 320         { "tx_ucast_packets" },
 321         { "tx_mcast_packets" },
 322         { "tx_bcast_packets" },
 323         { "tx_carrier_sense_errors" },
 324         { "tx_discards" },
 325         { "tx_errors" },
 326
 327         { "dma_writeq_full" },
 328         { "dma_write_prioq_full" },
 329         { "rxbds_empty" },
 330         { "rx_discards" },
 331         { "rx_errors" },
 332         { "rx_threshold_hit" },
 333
 334         { "dma_readq_full" },
 335         { "dma_read_prioq_full" },
 336         { "tx_comp_queue_full" },
 337
 338         { "ring_set_send_prod_index" },
 339         { "ring_status_update" },
 340         { "nic_irqs" },
 341         { "nic_avoided_irqs" },
 342         { "nic_tx_threshold_hit" }
 343 };
 344
 345 static const struct {
 346         const char string[ETH_GSTRING_LEN];
 347 } ethtool_test_keys[TG3_NUM_TEST] = {
 348         { "nvram test     (online) " },
 349         { "link test      (online) " },
 350         { "register test  (offline)" },
 351         { "memory test    (offline)" },
 352         { "loopback test  (offline)" },
 353         { "interrupt test (offline)" },
 354 };
 355
 356 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 357 {
 358         writel(val, tp->regs + off);
 359 }
 360
 361 static u32 tg3_read32(struct tg3 *tp, u32 off)
 362 {
 363         return (readl(tp->regs + off));
 364 }
 365
 366 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 367 {
 368         writel(val, tp->aperegs + off);
 369 }
 370
 371 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 372 {
 373         return (readl(tp->aperegs + off));
 374 }
 375
 376 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 377 {
 378         unsigned long flags;
 379
 380         spin_lock_irqsave(&tp->indirect_lock, flags);
 381         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 382         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 383         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 384 }
 385
 386 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 387 {
 388         writel(val, tp->regs + off);
 389         readl(tp->regs + off);
 390 }
 391
 392 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 393 {
 394         unsigned long flags;
 395         u32 val;
 396
 397         spin_lock_irqsave(&tp->indirect_lock, flags);
 398         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 399         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 400         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 401         return val;
 402 }
 403
 404 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 405 {
 406         unsigned long flags;
 407
 408         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 409                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 410                                        TG3_64BIT_REG_LOW, val);
 411                 return;
 412         }
 413         if (off == TG3_RX_STD_PROD_IDX_REG) {
 414                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 415                                        TG3_64BIT_REG_LOW, val);
 416                 return;
 417         }
 418
 419         spin_lock_irqsave(&tp->indirect_lock, flags);
 420         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 421         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 422         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 423
 424         /* In indirect mode when disabling interrupts, we also need
 425          * to clear the interrupt bit in the GRC local ctrl register.
 426          */
 427         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 428             (val == 0x1)) {
 429                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 430                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 431         }
 432 }
 433
 434 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 435 {
 436         unsigned long flags;
 437         u32 val;
 438
 439         spin_lock_irqsave(&tp->indirect_lock, flags);
 440         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 441         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 442         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 443         return val;
 444 }
 445
 446 /* usec_wait specifies the wait time in usec when writing to certain registers
 447  * where it is unsafe to read back the register without some delay.
 448  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 449  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 450  */
 451 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 452 {
 453         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 454             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 455                 /* Non-posted methods */
 456                 tp->write32(tp, off, val);
 457         else {
 458                 /* Posted method */
 459                 tg3_write32(tp, off, val);
 460                 if (usec_wait)
 461                         udelay(usec_wait);
 462                 tp->read32(tp, off);
 463         }
 464         /* Wait again after the read for the posted method to guarantee that
 465          * the wait time is met.
 466          */
 467         if (usec_wait)
 468                 udelay(usec_wait);
 469 }
 470
 471 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 472 {
 473         tp->write32_mbox(tp, off, val);
 474         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 475             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 476                 tp->read32_mbox(tp, off);
 477 }
 478
 479 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 480 {
 481         void __iomem *mbox = tp->regs + off;
 482         writel(val, mbox);
 483         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 484                 writel(val, mbox);
 485         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 486                 readl(mbox);
 487 }
 488
 489 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 490 {
 491         return (readl(tp->regs + off + GRCMBOX_BASE));
 492 }
 493
 494 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 495 {
 496         writel(val, tp->regs + off + GRCMBOX_BASE);
 497 }
 498
 499 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 500 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 501 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 502 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 503 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 504
 505 #define tw32(reg,val)           tp->write32(tp, reg, val)
 506 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 507 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 508 #define tr32(reg)               tp->read32(tp, reg)
 509
 510 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 511 {
 512         unsigned long flags;
 513
 514         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 515             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 516                 return;
 517
 518         spin_lock_irqsave(&tp->indirect_lock, flags);
 519         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 520                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 521                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 522
 523                 /* Always leave this as zero. */
 524                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 525         } else {
 526                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 527                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 528
 529                 /* Always leave this as zero. */
 530                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 531         }
 532         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 533 }
 534
 535 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 536 {
 537         unsigned long flags;
 538
 539         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 540             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 541                 *val = 0;
 542                 return;
 543         }
 544
 545         spin_lock_irqsave(&tp->indirect_lock, flags);
 546         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 547                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 548                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 549
 550                 /* Always leave this as zero. */
 551                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 552         } else {
 553                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 554                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 555
 556                 /* Always leave this as zero. */
 557                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 558         }
 559         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 560 }
 561
 562 static void tg3_ape_lock_init(struct tg3 *tp)
 563 {
 564         int i;
 565
 566         /* Make sure the driver hasn't any stale locks. */
 567         for (i = 0; i < 8; i++)
 568                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
 569                                 APE_LOCK_GRANT_DRIVER);
 570 }
 571
 572 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 573 {
 574         int i, off;
 575         int ret = 0;
 576         u32 status;
 577
 578         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 579                 return 0;
 580
 581         switch (locknum) {
 582                 case TG3_APE_LOCK_GRC:
 583                 case TG3_APE_LOCK_MEM:
 584                         break;
 585                 default:
 586                         return -EINVAL;
 587         }
 588
 589         off = 4 * locknum;
 590
 591         tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
 592
 593         /* Wait for up to 1 millisecond to acquire lock. */
 594         for (i = 0; i < 100; i++) {
 595                 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
 596                 if (status == APE_LOCK_GRANT_DRIVER)
 597                         break;
 598                 udelay(10);
 599         }
 600
 601         if (status != APE_LOCK_GRANT_DRIVER) {
 602                 /* Revoke the lock request. */
 603                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
 604                                 APE_LOCK_GRANT_DRIVER);
 605
 606                 ret = -EBUSY;
 607         }
 608
 609         return ret;
 610 }
 611
 612 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 613 {
 614         int off;
 615
 616         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 617                 return;
 618
 619         switch (locknum) {
 620                 case TG3_APE_LOCK_GRC:
 621                 case TG3_APE_LOCK_MEM:
 622                         break;
 623                 default:
 624                         return;
 625         }
 626
 627         off = 4 * locknum;
 628         tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
 629 }
 630
 631 static void tg3_disable_ints(struct tg3 *tp)
 632 {
 633         int i;
 634
 635         tw32(TG3PCI_MISC_HOST_CTRL,
 636              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 637         for (i = 0; i < tp->irq_max; i++)
 638                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 639 }
 640
 641 static void tg3_enable_ints(struct tg3 *tp)
 642 {
 643         int i;
 644
 645         tp->irq_sync = 0;
 646         wmb();
 647
 648         tw32(TG3PCI_MISC_HOST_CTRL,
 649              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 650
 651         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
 652         for (i = 0; i < tp->irq_cnt; i++) {
 653                 struct tg3_napi *tnapi = &tp->napi[i];
 654                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 655                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 656                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 657
 658                 tp->coal_now |= tnapi->coal_now;
 659         }
 660
 661         /* Force an initial interrupt */
 662         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 663             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 664                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 665         else
 666                 tw32(HOSTCC_MODE, tp->coal_now);
 667
 668         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
 669 }
 670
 671 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 672 {
 673         struct tg3 *tp = tnapi->tp;
 674         struct tg3_hw_status *sblk = tnapi->hw_status;
 675         unsigned int work_exists = 0;
 676
 677         /* check for phy events */
 678         if (!(tp->tg3_flags &
 679               (TG3_FLAG_USE_LINKCHG_REG |
 680                TG3_FLAG_POLL_SERDES))) {
 681                 if (sblk->status & SD_STATUS_LINK_CHG)
 682                         work_exists = 1;
 683         }
 684         /* check for RX/TX work to do */
 685         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 686             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
 687                 work_exists = 1;
 688
 689         return work_exists;
 690 }
 691
 692 /* tg3_int_reenable
 693  *  similar to tg3_enable_ints, but it accurately determines whether there
 694  *  is new work pending and can return without flushing the PIO write
 695  *  which reenables interrupts
 696  */
 697 static void tg3_int_reenable(struct tg3_napi *tnapi)
 698 {
 699         struct tg3 *tp = tnapi->tp;
 700
 701         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 702         mmiowb();
 703
 704         /* When doing tagged status, this work check is unnecessary.
 705          * The last_tag we write above tells the chip which piece of
 706          * work we've completed.
 707          */
 708         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 709             tg3_has_work(tnapi))
 710                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 711                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 712 }
 713
 714 static void tg3_napi_disable(struct tg3 *tp)
 715 {
 716         int i;
 717
 718         for (i = tp->irq_cnt - 1; i >= 0; i--)
 719                 napi_disable(&tp->napi[i].napi);
 720 }
 721
 722 static void tg3_napi_enable(struct tg3 *tp)
 723 {
 724         int i;
 725
 726         for (i = 0; i < tp->irq_cnt; i++)
 727                 napi_enable(&tp->napi[i].napi);
 728 }
 729
 730 static inline void tg3_netif_stop(struct tg3 *tp)
 731 {
 732         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 733         tg3_napi_disable(tp);
 734         netif_tx_disable(tp->dev);
 735 }
 736
 737 static inline void tg3_netif_start(struct tg3 *tp)
 738 {
 739         /* NOTE: unconditional netif_tx_wake_all_queues is only
 740          * appropriate so long as all callers are assured to
 741          * have free tx slots (such as after tg3_init_hw)
 742          */
 743         netif_tx_wake_all_queues(tp->dev);
 744
 745         tg3_napi_enable(tp);
 746         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
 747         tg3_enable_ints(tp);
 748 }
 749
 750 static void tg3_switch_clocks(struct tg3 *tp)
 751 {
 752         u32 clock_ctrl;
 753         u32 orig_clock_ctrl;
 754
 755         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 756             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 757                 return;
 758
 759         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 760
 761         orig_clock_ctrl = clock_ctrl;
 762         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 763                        CLOCK_CTRL_CLKRUN_OENABLE |
 764                        0x1f);
 765         tp->pci_clock_ctrl = clock_ctrl;
 766
 767         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 768                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 769                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 770                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 771                 }
 772         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 773                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 774                             clock_ctrl |
 775                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 776                             40);
 777                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 778                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 779                             40);
 780         }
 781         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 782 }
 783
 784 #define PHY_BUSY_LOOPS  5000
 785
 786 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 787 {
 788         u32 frame_val;
 789         unsigned int loops;
 790         int ret;
 791
 792         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 793                 tw32_f(MAC_MI_MODE,
 794                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 795                 udelay(80);
 796         }
 797
 798         *val = 0x0;
 799
 800         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 801                       MI_COM_PHY_ADDR_MASK);
 802         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 803                       MI_COM_REG_ADDR_MASK);
 804         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 805
 806         tw32_f(MAC_MI_COM, frame_val);
 807
 808         loops = PHY_BUSY_LOOPS;
 809         while (loops != 0) {
 810                 udelay(10);
 811                 frame_val = tr32(MAC_MI_COM);
 812
 813                 if ((frame_val & MI_COM_BUSY) == 0) {
 814                         udelay(5);
 815                         frame_val = tr32(MAC_MI_COM);
 816                         break;
 817                 }
 818                 loops -= 1;
 819         }
 820
 821         ret = -EBUSY;
 822         if (loops != 0) {
 823                 *val = frame_val & MI_COM_DATA_MASK;
 824                 ret = 0;
 825         }
 826
 827         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 828                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 829                 udelay(80);
 830         }
 831
 832         return ret;
 833 }
 834
 835 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 836 {
 837         u32 frame_val;
 838         unsigned int loops;
 839         int ret;
 840
 841         if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
 842             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 843                 return 0;
 844
 845         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 846                 tw32_f(MAC_MI_MODE,
 847                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 848                 udelay(80);
 849         }
 850
 851         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 852                       MI_COM_PHY_ADDR_MASK);
 853         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 854                       MI_COM_REG_ADDR_MASK);
 855         frame_val |= (val & MI_COM_DATA_MASK);
 856         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 857
 858         tw32_f(MAC_MI_COM, frame_val);
 859
 860         loops = PHY_BUSY_LOOPS;
 861         while (loops != 0) {
 862                 udelay(10);
 863                 frame_val = tr32(MAC_MI_COM);
 864                 if ((frame_val & MI_COM_BUSY) == 0) {
 865                         udelay(5);
 866                         frame_val = tr32(MAC_MI_COM);
 867                         break;
 868                 }
 869                 loops -= 1;
 870         }
 871
 872         ret = -EBUSY;
 873         if (loops != 0)
 874                 ret = 0;
 875
 876         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 877                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 878                 udelay(80);
 879         }
 880
 881         return ret;
 882 }
 883
 884 static int tg3_bmcr_reset(struct tg3 *tp)
 885 {
 886         u32 phy_control;
 887         int limit, err;
 888
 889         /* OK, reset it, and poll the BMCR_RESET bit until it
 890          * clears or we time out.
 891          */
 892         phy_control = BMCR_RESET;
 893         err = tg3_writephy(tp, MII_BMCR, phy_control);
 894         if (err != 0)
 895                 return -EBUSY;
 896
 897         limit = 5000;
 898         while (limit--) {
 899                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 900                 if (err != 0)
 901                         return -EBUSY;
 902
 903                 if ((phy_control & BMCR_RESET) == 0) {
 904                         udelay(40);
 905                         break;
 906                 }
 907                 udelay(10);
 908         }
 909         if (limit < 0)
 910                 return -EBUSY;
 911
 912         return 0;
 913 }
 914
 915 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 916 {
 917         struct tg3 *tp = bp->priv;
 918         u32 val;
 919
 920         spin_lock_bh(&tp->lock);
 921
 922         if (tg3_readphy(tp, reg, &val))
 923                 val = -EIO;
 924
 925         spin_unlock_bh(&tp->lock);
 926
 927         return val;
 928 }
 929
 930 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 931 {
 932         struct tg3 *tp = bp->priv;
 933         u32 ret = 0;
 934
 935         spin_lock_bh(&tp->lock);
 936
 937         if (tg3_writephy(tp, reg, val))
 938                 ret = -EIO;
 939
 940         spin_unlock_bh(&tp->lock);
 941
 942         return ret;
 943 }
 944
 945 static int tg3_mdio_reset(struct mii_bus *bp)
 946 {
 947         return 0;
 948 }
 949
 950 static void tg3_mdio_config_5785(struct tg3 *tp)
 951 {
 952         u32 val;
 953         struct phy_device *phydev;
 954
 955         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
 956         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 957         case PHY_ID_BCM50610:
 958         case PHY_ID_BCM50610M:
 959                 val = MAC_PHYCFG2_50610_LED_MODES;
 960                 break;
 961         case PHY_ID_BCMAC131:
 962                 val = MAC_PHYCFG2_AC131_LED_MODES;
 963                 break;
 964         case PHY_ID_RTL8211C:
 965                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
 966                 break;
 967         case PHY_ID_RTL8201E:
 968                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
 969                 break;
 970         default:
 971                 return;
 972         }
 973
 974         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
 975                 tw32(MAC_PHYCFG2, val);
 976
 977                 val = tr32(MAC_PHYCFG1);
 978                 val &= ~(MAC_PHYCFG1_RGMII_INT |
 979                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
 980                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
 981                 tw32(MAC_PHYCFG1, val);
 982
 983                 return;
 984         }
 985
 986         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
 987                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
 988                        MAC_PHYCFG2_FMODE_MASK_MASK |
 989                        MAC_PHYCFG2_GMODE_MASK_MASK |
 990                        MAC_PHYCFG2_ACT_MASK_MASK   |
 991                        MAC_PHYCFG2_QUAL_MASK_MASK |
 992                        MAC_PHYCFG2_INBAND_ENABLE;
 993
 994         tw32(MAC_PHYCFG2, val);
 995
 996         val = tr32(MAC_PHYCFG1);
 997         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
 998                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
 999         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1000                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1001                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1002                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1003                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1004         }
1005         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1006                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1007         tw32(MAC_PHYCFG1, val);
1008
1009         val = tr32(MAC_EXT_RGMII_MODE);
1010         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1011                  MAC_RGMII_MODE_RX_QUALITY |
1012                  MAC_RGMII_MODE_RX_ACTIVITY |
1013                  MAC_RGMII_MODE_RX_ENG_DET |
1014                  MAC_RGMII_MODE_TX_ENABLE |
1015                  MAC_RGMII_MODE_TX_LOWPWR |
1016                  MAC_RGMII_MODE_TX_RESET);
1017         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1018                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1019                         val |= MAC_RGMII_MODE_RX_INT_B |
1020                                MAC_RGMII_MODE_RX_QUALITY |
1021                                MAC_RGMII_MODE_RX_ACTIVITY |
1022                                MAC_RGMII_MODE_RX_ENG_DET;
1023                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1024                         val |= MAC_RGMII_MODE_TX_ENABLE |
1025                                MAC_RGMII_MODE_TX_LOWPWR |
1026                                MAC_RGMII_MODE_TX_RESET;
1027         }
1028         tw32(MAC_EXT_RGMII_MODE, val);
1029 }
1030
1031 static void tg3_mdio_start(struct tg3 *tp)
1032 {
1033         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1034         tw32_f(MAC_MI_MODE, tp->mi_mode);
1035         udelay(80);
1036
1037         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1038             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1039                 tg3_mdio_config_5785(tp);
1040 }
1041
1042 static int tg3_mdio_init(struct tg3 *tp)
1043 {
1044         int i;
1045         u32 reg;
1046         struct phy_device *phydev;
1047
1048         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1049                 u32 funcnum, is_serdes;
1050
1051                 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1052                 if (funcnum)
1053                         tp->phy_addr = 2;
1054                 else
1055                         tp->phy_addr = 1;
1056
1057                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1058                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1059                 else
1060                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1061                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1062                 if (is_serdes)
1063                         tp->phy_addr += 7;
1064         } else
1065                 tp->phy_addr = TG3_PHY_MII_ADDR;
1066
1067         tg3_mdio_start(tp);
1068
1069         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1070             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1071                 return 0;
1072
1073         tp->mdio_bus = mdiobus_alloc();
1074         if (tp->mdio_bus == NULL)
1075                 return -ENOMEM;
1076
1077         tp->mdio_bus->name     = "tg3 mdio bus";
1078         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1079                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1080         tp->mdio_bus->priv     = tp;
1081         tp->mdio_bus->parent   = &tp->pdev->dev;
1082         tp->mdio_bus->read     = &tg3_mdio_read;
1083         tp->mdio_bus->write    = &tg3_mdio_write;
1084         tp->mdio_bus->reset    = &tg3_mdio_reset;
1085         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1086         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1087
1088         for (i = 0; i < PHY_MAX_ADDR; i++)
1089                 tp->mdio_bus->irq[i] = PHY_POLL;
1090
1091         /* The bus registration will look for all the PHYs on the mdio bus.
1092          * Unfortunately, it does not ensure the PHY is powered up before
1093          * accessing the PHY ID registers.  A chip reset is the
1094          * quickest way to bring the device back to an operational state..
1095          */
1096         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1097                 tg3_bmcr_reset(tp);
1098
1099         i = mdiobus_register(tp->mdio_bus);
1100         if (i) {
1101                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1102                 mdiobus_free(tp->mdio_bus);
1103                 return i;
1104         }
1105
1106         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1107
1108         if (!phydev || !phydev->drv) {
1109                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1110                 mdiobus_unregister(tp->mdio_bus);
1111                 mdiobus_free(tp->mdio_bus);
1112                 return -ENODEV;
1113         }
1114
1115         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1116         case PHY_ID_BCM57780:
1117                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1118                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1119                 break;
1120         case PHY_ID_BCM50610:
1121         case PHY_ID_BCM50610M:
1122                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1123                                      PHY_BRCM_RX_REFCLK_UNUSED |
1124                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1125                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1126                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1127                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1128                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1129                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1130                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1131                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1132                 /* fallthru */
1133         case PHY_ID_RTL8211C:
1134                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1135                 break;
1136         case PHY_ID_RTL8201E:
1137         case PHY_ID_BCMAC131:
1138                 phydev->interface = PHY_INTERFACE_MODE_MII;
1139                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1140                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1141                 break;
1142         }
1143
1144         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1145
1146         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1147                 tg3_mdio_config_5785(tp);
1148
1149         return 0;
1150 }
1151
1152 static void tg3_mdio_fini(struct tg3 *tp)
1153 {
1154         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1155                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1156                 mdiobus_unregister(tp->mdio_bus);
1157                 mdiobus_free(tp->mdio_bus);
1158         }
1159 }
1160
1161 /* tp->lock is held. */
1162 static inline void tg3_generate_fw_event(struct tg3 *tp)
1163 {
1164         u32 val;
1165
1166         val = tr32(GRC_RX_CPU_EVENT);
1167         val |= GRC_RX_CPU_DRIVER_EVENT;
1168         tw32_f(GRC_RX_CPU_EVENT, val);
1169
1170         tp->last_event_jiffies = jiffies;
1171 }
1172
1173 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1174
1175 /* tp->lock is held. */
1176 static void tg3_wait_for_event_ack(struct tg3 *tp)
1177 {
1178         int i;
1179         unsigned int delay_cnt;
1180         long time_remain;
1181
1182         /* If enough time has passed, no wait is necessary. */
1183         time_remain = (long)(tp->last_event_jiffies + 1 +
1184                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1185                       (long)jiffies;
1186         if (time_remain < 0)
1187                 return;
1188
1189         /* Check if we can shorten the wait time. */
1190         delay_cnt = jiffies_to_usecs(time_remain);
1191         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1192                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1193         delay_cnt = (delay_cnt >> 3) + 1;
1194
1195         for (i = 0; i < delay_cnt; i++) {
1196                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1197                         break;
1198                 udelay(8);
1199         }
1200 }
1201
1202 /* tp->lock is held. */
1203 static void tg3_ump_link_report(struct tg3 *tp)
1204 {
1205         u32 reg;
1206         u32 val;
1207
1208         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1209             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1210                 return;
1211
1212         tg3_wait_for_event_ack(tp);
1213
1214         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1215
1216         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1217
1218         val = 0;
1219         if (!tg3_readphy(tp, MII_BMCR, &reg))
1220                 val = reg << 16;
1221         if (!tg3_readphy(tp, MII_BMSR, &reg))
1222                 val |= (reg & 0xffff);
1223         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1224
1225         val = 0;
1226         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1227                 val = reg << 16;
1228         if (!tg3_readphy(tp, MII_LPA, &reg))
1229                 val |= (reg & 0xffff);
1230         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1231
1232         val = 0;
1233         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1234                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1235                         val = reg << 16;
1236                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1237                         val |= (reg & 0xffff);
1238         }
1239         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1240
1241         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1242                 val = reg << 16;
1243         else
1244                 val = 0;
1245         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1246
1247         tg3_generate_fw_event(tp);
1248 }
1249
1250 static void tg3_link_report(struct tg3 *tp)
1251 {
1252         if (!netif_carrier_ok(tp->dev)) {
1253                 netif_info(tp, link, tp->dev, "Link is down\n");
1254                 tg3_ump_link_report(tp);
1255         } else if (netif_msg_link(tp)) {
1256                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1257                             (tp->link_config.active_speed == SPEED_1000 ?
1258                              1000 :
1259                              (tp->link_config.active_speed == SPEED_100 ?
1260                               100 : 10)),
1261                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1262                              "full" : "half"));
1263
1264                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1265                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1266                             "on" : "off",
1267                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1268                             "on" : "off");
1269                 tg3_ump_link_report(tp);
1270         }
1271 }
1272
1273 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1274 {
1275         u16 miireg;
1276
1277         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1278                 miireg = ADVERTISE_PAUSE_CAP;
1279         else if (flow_ctrl & FLOW_CTRL_TX)
1280                 miireg = ADVERTISE_PAUSE_ASYM;
1281         else if (flow_ctrl & FLOW_CTRL_RX)
1282                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1283         else
1284                 miireg = 0;
1285
1286         return miireg;
1287 }
1288
1289 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1290 {
1291         u16 miireg;
1292
1293         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1294                 miireg = ADVERTISE_1000XPAUSE;
1295         else if (flow_ctrl & FLOW_CTRL_TX)
1296                 miireg = ADVERTISE_1000XPSE_ASYM;
1297         else if (flow_ctrl & FLOW_CTRL_RX)
1298                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1299         else
1300                 miireg = 0;
1301
1302         return miireg;
1303 }
1304
1305 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1306 {
1307         u8 cap = 0;
1308
1309         if (lcladv & ADVERTISE_1000XPAUSE) {
1310                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1311                         if (rmtadv & LPA_1000XPAUSE)
1312                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1313                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1314                                 cap = FLOW_CTRL_RX;
1315                 } else {
1316                         if (rmtadv & LPA_1000XPAUSE)
1317                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1318                 }
1319         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1320                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1321                         cap = FLOW_CTRL_TX;
1322         }
1323
1324         return cap;
1325 }
1326
1327 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1328 {
1329         u8 autoneg;
1330         u8 flowctrl = 0;
1331         u32 old_rx_mode = tp->rx_mode;
1332         u32 old_tx_mode = tp->tx_mode;
1333
1334         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1335                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1336         else
1337                 autoneg = tp->link_config.autoneg;
1338
1339         if (autoneg == AUTONEG_ENABLE &&
1340             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1341                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1342                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1343                 else
1344                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1345         } else
1346                 flowctrl = tp->link_config.flowctrl;
1347
1348         tp->link_config.active_flowctrl = flowctrl;
1349
1350         if (flowctrl & FLOW_CTRL_RX)
1351                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1352         else
1353                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1354
1355         if (old_rx_mode != tp->rx_mode)
1356                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1357
1358         if (flowctrl & FLOW_CTRL_TX)
1359                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1360         else
1361                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1362
1363         if (old_tx_mode != tp->tx_mode)
1364                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1365 }
1366
1367 static void tg3_adjust_link(struct net_device *dev)
1368 {
1369         u8 oldflowctrl, linkmesg = 0;
1370         u32 mac_mode, lcl_adv, rmt_adv;
1371         struct tg3 *tp = netdev_priv(dev);
1372         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1373
1374         spin_lock_bh(&tp->lock);
1375
1376         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1377                                     MAC_MODE_HALF_DUPLEX);
1378
1379         oldflowctrl = tp->link_config.active_flowctrl;
1380
1381         if (phydev->link) {
1382                 lcl_adv = 0;
1383                 rmt_adv = 0;
1384
1385                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1386                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1387                 else if (phydev->speed == SPEED_1000 ||
1388                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1389                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1390                 else
1391                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1392
1393                 if (phydev->duplex == DUPLEX_HALF)
1394                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1395                 else {
1396                         lcl_adv = tg3_advert_flowctrl_1000T(
1397                                   tp->link_config.flowctrl);
1398
1399                         if (phydev->pause)
1400                                 rmt_adv = LPA_PAUSE_CAP;
1401                         if (phydev->asym_pause)
1402                                 rmt_adv |= LPA_PAUSE_ASYM;
1403                 }
1404
1405                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1406         } else
1407                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1408
1409         if (mac_mode != tp->mac_mode) {
1410                 tp->mac_mode = mac_mode;
1411                 tw32_f(MAC_MODE, tp->mac_mode);
1412                 udelay(40);
1413         }
1414
1415         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1416                 if (phydev->speed == SPEED_10)
1417                         tw32(MAC_MI_STAT,
1418                              MAC_MI_STAT_10MBPS_MODE |
1419                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1420                 else
1421                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1422         }
1423
1424         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1425                 tw32(MAC_TX_LENGTHS,
1426                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1427                       (6 << TX_LENGTHS_IPG_SHIFT) |
1428                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1429         else
1430                 tw32(MAC_TX_LENGTHS,
1431                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1432                       (6 << TX_LENGTHS_IPG_SHIFT) |
1433                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1434
1435         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1436             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1437             phydev->speed != tp->link_config.active_speed ||
1438             phydev->duplex != tp->link_config.active_duplex ||
1439             oldflowctrl != tp->link_config.active_flowctrl)
1440             linkmesg = 1;
1441
1442         tp->link_config.active_speed = phydev->speed;
1443         tp->link_config.active_duplex = phydev->duplex;
1444
1445         spin_unlock_bh(&tp->lock);
1446
1447         if (linkmesg)
1448                 tg3_link_report(tp);
1449 }
1450
1451 static int tg3_phy_init(struct tg3 *tp)
1452 {
1453         struct phy_device *phydev;
1454
1455         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1456                 return 0;
1457
1458         /* Bring the PHY back to a known state. */
1459         tg3_bmcr_reset(tp);
1460
1461         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1462
1463         /* Attach the MAC to the PHY. */
1464         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1465                              phydev->dev_flags, phydev->interface);
1466         if (IS_ERR(phydev)) {
1467                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1468                 return PTR_ERR(phydev);
1469         }
1470
1471         /* Mask with MAC supported features. */
1472         switch (phydev->interface) {
1473         case PHY_INTERFACE_MODE_GMII:
1474         case PHY_INTERFACE_MODE_RGMII:
1475                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1476                         phydev->supported &= (PHY_GBIT_FEATURES |
1477                                               SUPPORTED_Pause |
1478                                               SUPPORTED_Asym_Pause);
1479                         break;
1480                 }
1481                 /* fallthru */
1482         case PHY_INTERFACE_MODE_MII:
1483                 phydev->supported &= (PHY_BASIC_FEATURES |
1484                                       SUPPORTED_Pause |
1485                                       SUPPORTED_Asym_Pause);
1486                 break;
1487         default:
1488                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1489                 return -EINVAL;
1490         }
1491
1492         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1493
1494         phydev->advertising = phydev->supported;
1495
1496         return 0;
1497 }
1498
1499 static void tg3_phy_start(struct tg3 *tp)
1500 {
1501         struct phy_device *phydev;
1502
1503         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1504                 return;
1505
1506         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1507
1508         if (tp->link_config.phy_is_low_power) {
1509                 tp->link_config.phy_is_low_power = 0;
1510                 phydev->speed = tp->link_config.orig_speed;
1511                 phydev->duplex = tp->link_config.orig_duplex;
1512                 phydev->autoneg = tp->link_config.orig_autoneg;
1513                 phydev->advertising = tp->link_config.orig_advertising;
1514         }
1515
1516         phy_start(phydev);
1517
1518         phy_start_aneg(phydev);
1519 }
1520
1521 static void tg3_phy_stop(struct tg3 *tp)
1522 {
1523         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1524                 return;
1525
1526         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1527 }
1528
1529 static void tg3_phy_fini(struct tg3 *tp)
1530 {
1531         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1532                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1533                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1534         }
1535 }
1536
1537 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1538 {
1539         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1540         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1541 }
1542
1543 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1544 {
1545         u32 phytest;
1546
1547         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1548                 u32 phy;
1549
1550                 tg3_writephy(tp, MII_TG3_FET_TEST,
1551                              phytest | MII_TG3_FET_SHADOW_EN);
1552                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1553                         if (enable)
1554                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1555                         else
1556                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1557                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1558                 }
1559                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1560         }
1561 }
1562
1563 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1564 {
1565         u32 reg;
1566
1567         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1568                 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1569              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1570                 return;
1571
1572         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1573                 tg3_phy_fet_toggle_apd(tp, enable);
1574                 return;
1575         }
1576
1577         reg = MII_TG3_MISC_SHDW_WREN |
1578               MII_TG3_MISC_SHDW_SCR5_SEL |
1579               MII_TG3_MISC_SHDW_SCR5_LPED |
1580               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1581               MII_TG3_MISC_SHDW_SCR5_SDTL |
1582               MII_TG3_MISC_SHDW_SCR5_C125OE;
1583         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1584                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1585
1586         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1587
1588
1589         reg = MII_TG3_MISC_SHDW_WREN |
1590               MII_TG3_MISC_SHDW_APD_SEL |
1591               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1592         if (enable)
1593                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1594
1595         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1596 }
1597
1598 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1599 {
1600         u32 phy;
1601
1602         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1603             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1604                 return;
1605
1606         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1607                 u32 ephy;
1608
1609                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1610                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1611
1612                         tg3_writephy(tp, MII_TG3_FET_TEST,
1613                                      ephy | MII_TG3_FET_SHADOW_EN);
1614                         if (!tg3_readphy(tp, reg, &phy)) {
1615                                 if (enable)
1616                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1617                                 else
1618                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1619                                 tg3_writephy(tp, reg, phy);
1620                         }
1621                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1622                 }
1623         } else {
1624                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1625                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1626                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1627                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1628                         if (enable)
1629                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1630                         else
1631                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1632                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1633                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1634                 }
1635         }
1636 }
1637
1638 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1639 {
1640         u32 val;
1641
1642         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1643                 return;
1644
1645         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1646             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1647                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1648                              (val | (1 << 15) | (1 << 4)));
1649 }
1650
1651 static void tg3_phy_apply_otp(struct tg3 *tp)
1652 {
1653         u32 otp, phy;
1654
1655         if (!tp->phy_otp)
1656                 return;
1657
1658         otp = tp->phy_otp;
1659
1660         /* Enable SM_DSP clock and tx 6dB coding. */
1661         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1662               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1663               MII_TG3_AUXCTL_ACTL_TX_6DB;
1664         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1665
1666         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1667         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1668         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1669
1670         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1671               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1672         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1673
1674         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1675         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1676         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1677
1678         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1679         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1680
1681         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1682         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1683
1684         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1685               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1686         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1687
1688         /* Turn off SM_DSP clock. */
1689         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1690               MII_TG3_AUXCTL_ACTL_TX_6DB;
1691         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1692 }
1693
1694 static int tg3_wait_macro_done(struct tg3 *tp)
1695 {
1696         int limit = 100;
1697
1698         while (limit--) {
1699                 u32 tmp32;
1700
1701                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1702                         if ((tmp32 & 0x1000) == 0)
1703                                 break;
1704                 }
1705         }
1706         if (limit < 0)
1707                 return -EBUSY;
1708
1709         return 0;
1710 }
1711
1712 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1713 {
1714         static const u32 test_pat[4][6] = {
1715         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1716         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1717         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1718         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1719         };
1720         int chan;
1721
1722         for (chan = 0; chan < 4; chan++) {
1723                 int i;
1724
1725                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1726                              (chan * 0x2000) | 0x0200);
1727                 tg3_writephy(tp, 0x16, 0x0002);
1728
1729                 for (i = 0; i < 6; i++)
1730                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1731                                      test_pat[chan][i]);
1732
1733                 tg3_writephy(tp, 0x16, 0x0202);
1734                 if (tg3_wait_macro_done(tp)) {
1735                         *resetp = 1;
1736                         return -EBUSY;
1737                 }
1738
1739                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1740                              (chan * 0x2000) | 0x0200);
1741                 tg3_writephy(tp, 0x16, 0x0082);
1742                 if (tg3_wait_macro_done(tp)) {
1743                         *resetp = 1;
1744                         return -EBUSY;
1745                 }
1746
1747                 tg3_writephy(tp, 0x16, 0x0802);
1748                 if (tg3_wait_macro_done(tp)) {
1749                         *resetp = 1;
1750                         return -EBUSY;
1751                 }
1752
1753                 for (i = 0; i < 6; i += 2) {
1754                         u32 low, high;
1755
1756                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1757                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1758                             tg3_wait_macro_done(tp)) {
1759                                 *resetp = 1;
1760                                 return -EBUSY;
1761                         }
1762                         low &= 0x7fff;
1763                         high &= 0x000f;
1764                         if (low != test_pat[chan][i] ||
1765                             high != test_pat[chan][i+1]) {
1766                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1767                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1768                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1769
1770                                 return -EBUSY;
1771                         }
1772                 }
1773         }
1774
1775         return 0;
1776 }
1777
1778 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1779 {
1780         int chan;
1781
1782         for (chan = 0; chan < 4; chan++) {
1783                 int i;
1784
1785                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1786                              (chan * 0x2000) | 0x0200);
1787                 tg3_writephy(tp, 0x16, 0x0002);
1788                 for (i = 0; i < 6; i++)
1789                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1790                 tg3_writephy(tp, 0x16, 0x0202);
1791                 if (tg3_wait_macro_done(tp))
1792                         return -EBUSY;
1793         }
1794
1795         return 0;
1796 }
1797
1798 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1799 {
1800         u32 reg32, phy9_orig;
1801         int retries, do_phy_reset, err;
1802
1803         retries = 10;
1804         do_phy_reset = 1;
1805         do {
1806                 if (do_phy_reset) {
1807                         err = tg3_bmcr_reset(tp);
1808                         if (err)
1809                                 return err;
1810                         do_phy_reset = 0;
1811                 }
1812
1813                 /* Disable transmitter and interrupt.  */
1814                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1815                         continue;
1816
1817                 reg32 |= 0x3000;
1818                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1819
1820                 /* Set full-duplex, 1000 mbps.  */
1821                 tg3_writephy(tp, MII_BMCR,
1822                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1823
1824                 /* Set to master mode.  */
1825                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1826                         continue;
1827
1828                 tg3_writephy(tp, MII_TG3_CTRL,
1829                              (MII_TG3_CTRL_AS_MASTER |
1830                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1831
1832                 /* Enable SM_DSP_CLOCK and 6dB.  */
1833                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1834
1835                 /* Block the PHY control access.  */
1836                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1837                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1838
1839                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1840                 if (!err)
1841                         break;
1842         } while (--retries);
1843
1844         err = tg3_phy_reset_chanpat(tp);
1845         if (err)
1846                 return err;
1847
1848         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1849         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1850
1851         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1852         tg3_writephy(tp, 0x16, 0x0000);
1853
1854         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1855             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1856                 /* Set Extended packet length bit for jumbo frames */
1857                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1858         }
1859         else {
1860                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1861         }
1862
1863         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1864
1865         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1866                 reg32 &= ~0x3000;
1867                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1868         } else if (!err)
1869                 err = -EBUSY;
1870
1871         return err;
1872 }
1873
1874 /* This will reset the tigon3 PHY if there is no valid
1875  * link unless the FORCE argument is non-zero.
1876  */
1877 static int tg3_phy_reset(struct tg3 *tp)
1878 {
1879         u32 cpmuctrl;
1880         u32 phy_status;
1881         int err;
1882
1883         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1884                 u32 val;
1885
1886                 val = tr32(GRC_MISC_CFG);
1887                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1888                 udelay(40);
1889         }
1890         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1891         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1892         if (err != 0)
1893                 return -EBUSY;
1894
1895         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1896                 netif_carrier_off(tp->dev);
1897                 tg3_link_report(tp);
1898         }
1899
1900         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1901             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1902             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1903                 err = tg3_phy_reset_5703_4_5(tp);
1904                 if (err)
1905                         return err;
1906                 goto out;
1907         }
1908
1909         cpmuctrl = 0;
1910         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1911             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1912                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1913                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1914                         tw32(TG3_CPMU_CTRL,
1915                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1916         }
1917
1918         err = tg3_bmcr_reset(tp);
1919         if (err)
1920                 return err;
1921
1922         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1923                 u32 phy;
1924
1925                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1926                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1927
1928                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1929         }
1930
1931         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1932             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1933                 u32 val;
1934
1935                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1936                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1937                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1938                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1939                         udelay(40);
1940                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1941                 }
1942         }
1943
1944         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1945             (tp->tg3_flags2 & TG3_FLG2_MII_SERDES))
1946                 return 0;
1947
1948         tg3_phy_apply_otp(tp);
1949
1950         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1951                 tg3_phy_toggle_apd(tp, true);
1952         else
1953                 tg3_phy_toggle_apd(tp, false);
1954
1955 out:
1956         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1957                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1958                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1959                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1960                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1961                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1962                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1963         }
1964         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1965                 tg3_writephy(tp, 0x1c, 0x8d68);
1966                 tg3_writephy(tp, 0x1c, 0x8d68);
1967         }
1968         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1969                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1970                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1971                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1972                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1973                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1974                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1975                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1976                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1977         }
1978         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1979                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1980                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1981                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1982                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1983                         tg3_writephy(tp, MII_TG3_TEST1,
1984                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1985                 } else
1986                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1987                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1988         }
1989         /* Set Extended packet length bit (bit 14) on all chips that */
1990         /* support jumbo frames */
1991         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1992                 /* Cannot do read-modify-write on 5401 */
1993                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1994         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1995                 u32 phy_reg;
1996
1997                 /* Set bit 14 with read-modify-write to preserve other bits */
1998                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1999                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
2000                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
2001         }
2002
2003         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2004          * jumbo frames transmission.
2005          */
2006         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2007                 u32 phy_reg;
2008
2009                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
2010                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
2011                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2012         }
2013
2014         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2015                 /* adjust output voltage */
2016                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2017         }
2018
2019         tg3_phy_toggle_automdix(tp, 1);
2020         tg3_phy_set_wirespeed(tp);
2021         return 0;
2022 }
2023
2024 static void tg3_frob_aux_power(struct tg3 *tp)
2025 {
2026         struct tg3 *tp_peer = tp;
2027
2028         /* The GPIOs do something completely different on 57765. */
2029         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2030             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2031                 return;
2032
2033         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2034             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2035             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2036                 struct net_device *dev_peer;
2037
2038                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2039                 /* remove_one() may have been run on the peer. */
2040                 if (!dev_peer)
2041                         tp_peer = tp;
2042                 else
2043                         tp_peer = netdev_priv(dev_peer);
2044         }
2045
2046         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2047             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2048             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2049             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2050                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2051                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2052                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2053                                     (GRC_LCLCTRL_GPIO_OE0 |
2054                                      GRC_LCLCTRL_GPIO_OE1 |
2055                                      GRC_LCLCTRL_GPIO_OE2 |
2056                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2057                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2058                                     100);
2059                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2060                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2061                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2062                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2063                                              GRC_LCLCTRL_GPIO_OE1 |
2064                                              GRC_LCLCTRL_GPIO_OE2 |
2065                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2066                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2067                                              tp->grc_local_ctrl;
2068                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2069
2070                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2071                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2072
2073                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2074                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2075                 } else {
2076                         u32 no_gpio2;
2077                         u32 grc_local_ctrl = 0;
2078
2079                         if (tp_peer != tp &&
2080                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2081                                 return;
2082
2083                         /* Workaround to prevent overdrawing Amps. */
2084                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2085                             ASIC_REV_5714) {
2086                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2087                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2088                                             grc_local_ctrl, 100);
2089                         }
2090
2091                         /* On 5753 and variants, GPIO2 cannot be used. */
2092                         no_gpio2 = tp->nic_sram_data_cfg &
2093                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2094
2095                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2096                                          GRC_LCLCTRL_GPIO_OE1 |
2097                                          GRC_LCLCTRL_GPIO_OE2 |
2098                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2099                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2100                         if (no_gpio2) {
2101                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2102                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2103                         }
2104                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2105                                                     grc_local_ctrl, 100);
2106
2107                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2108
2109                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2110                                                     grc_local_ctrl, 100);
2111
2112                         if (!no_gpio2) {
2113                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2114                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2115                                             grc_local_ctrl, 100);
2116                         }
2117                 }
2118         } else {
2119                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2120                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2121                         if (tp_peer != tp &&
2122                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2123                                 return;
2124
2125                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2126                                     (GRC_LCLCTRL_GPIO_OE1 |
2127                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2128
2129                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2130                                     GRC_LCLCTRL_GPIO_OE1, 100);
2131
2132                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2133                                     (GRC_LCLCTRL_GPIO_OE1 |
2134                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2135                 }
2136         }
2137 }
2138
2139 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2140 {
2141         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2142                 return 1;
2143         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2144                 if (speed != SPEED_10)
2145                         return 1;
2146         } else if (speed == SPEED_10)
2147                 return 1;
2148
2149         return 0;
2150 }
2151
2152 static int tg3_setup_phy(struct tg3 *, int);
2153
2154 #define RESET_KIND_SHUTDOWN     0
2155 #define RESET_KIND_INIT         1
2156 #define RESET_KIND_SUSPEND      2
2157
2158 static void tg3_write_sig_post_reset(struct tg3 *, int);
2159 static int tg3_halt_cpu(struct tg3 *, u32);
2160
2161 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2162 {
2163         u32 val;
2164
2165         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2166                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2167                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2168                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2169
2170                         sg_dig_ctrl |=
2171                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2172                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2173                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2174                 }
2175                 return;
2176         }
2177
2178         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2179                 tg3_bmcr_reset(tp);
2180                 val = tr32(GRC_MISC_CFG);
2181                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2182                 udelay(40);
2183                 return;
2184         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2185                 u32 phytest;
2186                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2187                         u32 phy;
2188
2189                         tg3_writephy(tp, MII_ADVERTISE, 0);
2190                         tg3_writephy(tp, MII_BMCR,
2191                                      BMCR_ANENABLE | BMCR_ANRESTART);
2192
2193                         tg3_writephy(tp, MII_TG3_FET_TEST,
2194                                      phytest | MII_TG3_FET_SHADOW_EN);
2195                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2196                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2197                                 tg3_writephy(tp,
2198                                              MII_TG3_FET_SHDW_AUXMODE4,
2199                                              phy);
2200                         }
2201                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2202                 }
2203                 return;
2204         } else if (do_low_power) {
2205                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2206                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2207
2208                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2209                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2210                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2211                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2212                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2213         }
2214
2215         /* The PHY should not be powered down on some chips because
2216          * of bugs.
2217          */
2218         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2219             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2220             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2221              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2222                 return;
2223
2224         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2225             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2226                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2227                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2228                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2229                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2230         }
2231
2232         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2233 }
2234
2235 /* tp->lock is held. */
2236 static int tg3_nvram_lock(struct tg3 *tp)
2237 {
2238         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2239                 int i;
2240
2241                 if (tp->nvram_lock_cnt == 0) {
2242                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2243                         for (i = 0; i < 8000; i++) {
2244                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2245                                         break;
2246                                 udelay(20);
2247                         }
2248                         if (i == 8000) {
2249                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2250                                 return -ENODEV;
2251                         }
2252                 }
2253                 tp->nvram_lock_cnt++;
2254         }
2255         return 0;
2256 }
2257
2258 /* tp->lock is held. */
2259 static void tg3_nvram_unlock(struct tg3 *tp)
2260 {
2261         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2262                 if (tp->nvram_lock_cnt > 0)
2263                         tp->nvram_lock_cnt--;
2264                 if (tp->nvram_lock_cnt == 0)
2265                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2266         }
2267 }
2268
2269 /* tp->lock is held. */
2270 static void tg3_enable_nvram_access(struct tg3 *tp)
2271 {
2272         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2273             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2274                 u32 nvaccess = tr32(NVRAM_ACCESS);
2275
2276                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2277         }
2278 }
2279
2280 /* tp->lock is held. */
2281 static void tg3_disable_nvram_access(struct tg3 *tp)
2282 {
2283         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2284             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2285                 u32 nvaccess = tr32(NVRAM_ACCESS);
2286
2287                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2288         }
2289 }
2290
2291 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2292                                         u32 offset, u32 *val)
2293 {
2294         u32 tmp;
2295         int i;
2296
2297         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2298                 return -EINVAL;
2299
2300         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2301                                         EEPROM_ADDR_DEVID_MASK |
2302                                         EEPROM_ADDR_READ);
2303         tw32(GRC_EEPROM_ADDR,
2304              tmp |
2305              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2306              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2307               EEPROM_ADDR_ADDR_MASK) |
2308              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2309
2310         for (i = 0; i < 1000; i++) {
2311                 tmp = tr32(GRC_EEPROM_ADDR);
2312
2313                 if (tmp & EEPROM_ADDR_COMPLETE)
2314                         break;
2315                 msleep(1);
2316         }
2317         if (!(tmp & EEPROM_ADDR_COMPLETE))
2318                 return -EBUSY;
2319
2320         tmp = tr32(GRC_EEPROM_DATA);
2321
2322         /*
2323          * The data will always be opposite the native endian
2324          * format.  Perform a blind byteswap to compensate.
2325          */
2326         *val = swab32(tmp);
2327
2328         return 0;
2329 }
2330
2331 #define NVRAM_CMD_TIMEOUT 10000
2332
2333 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2334 {
2335         int i;
2336
2337         tw32(NVRAM_CMD, nvram_cmd);
2338         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2339                 udelay(10);
2340                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2341                         udelay(10);
2342                         break;
2343                 }
2344         }
2345
2346         if (i == NVRAM_CMD_TIMEOUT)
2347                 return -EBUSY;
2348
2349         return 0;
2350 }
2351
2352 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2353 {
2354         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2355             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2356             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2357            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2358             (tp->nvram_jedecnum == JEDEC_ATMEL))
2359
2360                 addr = ((addr / tp->nvram_pagesize) <<
2361                         ATMEL_AT45DB0X1B_PAGE_POS) +
2362                        (addr % tp->nvram_pagesize);
2363
2364         return addr;
2365 }
2366
2367 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2368 {
2369         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2370             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2371             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2372            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2373             (tp->nvram_jedecnum == JEDEC_ATMEL))
2374
2375                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2376                         tp->nvram_pagesize) +
2377                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2378
2379         return addr;
2380 }
2381
2382 /* NOTE: Data read in from NVRAM is byteswapped according to
2383  * the byteswapping settings for all other register accesses.
2384  * tg3 devices are BE devices, so on a BE machine, the data
2385  * returned will be exactly as it is seen in NVRAM.  On a LE
2386  * machine, the 32-bit value will be byteswapped.
2387  */
2388 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2389 {
2390         int ret;
2391
2392         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2393                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2394
2395         offset = tg3_nvram_phys_addr(tp, offset);
2396
2397         if (offset > NVRAM_ADDR_MSK)
2398                 return -EINVAL;
2399
2400         ret = tg3_nvram_lock(tp);
2401         if (ret)
2402                 return ret;
2403
2404         tg3_enable_nvram_access(tp);
2405
2406         tw32(NVRAM_ADDR, offset);
2407         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2408                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2409
2410         if (ret == 0)
2411                 *val = tr32(NVRAM_RDDATA);
2412
2413         tg3_disable_nvram_access(tp);
2414
2415         tg3_nvram_unlock(tp);
2416
2417         return ret;
2418 }
2419
2420 /* Ensures NVRAM data is in bytestream format. */
2421 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2422 {
2423         u32 v;
2424         int res = tg3_nvram_read(tp, offset, &v);
2425         if (!res)
2426                 *val = cpu_to_be32(v);
2427         return res;
2428 }
2429
2430 /* tp->lock is held. */
2431 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2432 {
2433         u32 addr_high, addr_low;
2434         int i;
2435
2436         addr_high = ((tp->dev->dev_addr[0] << 8) |
2437                      tp->dev->dev_addr[1]);
2438         addr_low = ((tp->dev->dev_addr[2] << 24) |
2439                     (tp->dev->dev_addr[3] << 16) |
2440                     (tp->dev->dev_addr[4] <<  8) |
2441                     (tp->dev->dev_addr[5] <<  0));
2442         for (i = 0; i < 4; i++) {
2443                 if (i == 1 && skip_mac_1)
2444                         continue;
2445                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2446                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2447         }
2448
2449         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2450             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2451                 for (i = 0; i < 12; i++) {
2452                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2453                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2454                 }
2455         }
2456
2457         addr_high = (tp->dev->dev_addr[0] +
2458                      tp->dev->dev_addr[1] +
2459                      tp->dev->dev_addr[2] +
2460                      tp->dev->dev_addr[3] +
2461                      tp->dev->dev_addr[4] +
2462                      tp->dev->dev_addr[5]) &
2463                 TX_BACKOFF_SEED_MASK;
2464         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2465 }
2466
2467 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2468 {
2469         u32 misc_host_ctrl;
2470         bool device_should_wake, do_low_power;
2471
2472         /* Make sure register accesses (indirect or otherwise)
2473          * will function correctly.
2474          */
2475         pci_write_config_dword(tp->pdev,
2476                                TG3PCI_MISC_HOST_CTRL,
2477                                tp->misc_host_ctrl);
2478
2479         switch (state) {
2480         case PCI_D0:
2481                 pci_enable_wake(tp->pdev, state, false);
2482                 pci_set_power_state(tp->pdev, PCI_D0);
2483
2484                 /* Switch out of Vaux if it is a NIC */
2485                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2486                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2487
2488                 return 0;
2489
2490         case PCI_D1:
2491         case PCI_D2:
2492         case PCI_D3hot:
2493                 break;
2494
2495         default:
2496                 netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
2497                            state);
2498                 return -EINVAL;
2499         }
2500
2501         /* Restore the CLKREQ setting. */
2502         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2503                 u16 lnkctl;
2504
2505                 pci_read_config_word(tp->pdev,
2506                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2507                                      &lnkctl);
2508                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2509                 pci_write_config_word(tp->pdev,
2510                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2511                                       lnkctl);
2512         }
2513
2514         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2515         tw32(TG3PCI_MISC_HOST_CTRL,
2516              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2517
2518         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2519                              device_may_wakeup(&tp->pdev->dev) &&
2520                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2521
2522         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2523                 do_low_power = false;
2524                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2525                     !tp->link_config.phy_is_low_power) {
2526                         struct phy_device *phydev;
2527                         u32 phyid, advertising;
2528
2529                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2530
2531                         tp->link_config.phy_is_low_power = 1;
2532
2533                         tp->link_config.orig_speed = phydev->speed;
2534                         tp->link_config.orig_duplex = phydev->duplex;
2535                         tp->link_config.orig_autoneg = phydev->autoneg;
2536                         tp->link_config.orig_advertising = phydev->advertising;
2537
2538                         advertising = ADVERTISED_TP |
2539                                       ADVERTISED_Pause |
2540                                       ADVERTISED_Autoneg |
2541                                       ADVERTISED_10baseT_Half;
2542
2543                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2544                             device_should_wake) {
2545                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2546                                         advertising |=
2547                                                 ADVERTISED_100baseT_Half |
2548                                                 ADVERTISED_100baseT_Full |
2549                                                 ADVERTISED_10baseT_Full;
2550                                 else
2551                                         advertising |= ADVERTISED_10baseT_Full;
2552                         }
2553
2554                         phydev->advertising = advertising;
2555
2556                         phy_start_aneg(phydev);
2557
2558                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2559                         if (phyid != PHY_ID_BCMAC131) {
2560                                 phyid &= PHY_BCM_OUI_MASK;
2561                                 if (phyid == PHY_BCM_OUI_1 ||
2562                                     phyid == PHY_BCM_OUI_2 ||
2563                                     phyid == PHY_BCM_OUI_3)
2564                                         do_low_power = true;
2565                         }
2566                 }
2567         } else {
2568                 do_low_power = true;
2569
2570                 if (tp->link_config.phy_is_low_power == 0) {
2571                         tp->link_config.phy_is_low_power = 1;
2572                         tp->link_config.orig_speed = tp->link_config.speed;
2573                         tp->link_config.orig_duplex = tp->link_config.duplex;
2574                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2575                 }
2576
2577                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2578                         tp->link_config.speed = SPEED_10;
2579                         tp->link_config.duplex = DUPLEX_HALF;
2580                         tp->link_config.autoneg = AUTONEG_ENABLE;
2581                         tg3_setup_phy(tp, 0);
2582                 }
2583         }
2584
2585         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2586                 u32 val;
2587
2588                 val = tr32(GRC_VCPU_EXT_CTRL);
2589                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2590         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2591                 int i;
2592                 u32 val;
2593
2594                 for (i = 0; i < 200; i++) {
2595                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2596                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2597                                 break;
2598                         msleep(1);
2599                 }
2600         }
2601         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2602                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2603                                                      WOL_DRV_STATE_SHUTDOWN |
2604                                                      WOL_DRV_WOL |
2605                                                      WOL_SET_MAGIC_PKT);
2606
2607         if (device_should_wake) {
2608                 u32 mac_mode;
2609
2610                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2611                         if (do_low_power) {
2612                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2613                                 udelay(40);
2614                         }
2615
2616                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2617                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2618                         else
2619                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2620
2621                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2622                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2623                             ASIC_REV_5700) {
2624                                 u32 speed = (tp->tg3_flags &
2625                                              TG3_FLAG_WOL_SPEED_100MB) ?
2626                                              SPEED_100 : SPEED_10;
2627                                 if (tg3_5700_link_polarity(tp, speed))
2628                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2629                                 else
2630                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2631                         }
2632                 } else {
2633                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2634                 }
2635
2636                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2637                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2638
2639                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2640                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2641                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2642                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2643                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2644                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2645
2646                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2647                         mac_mode |= tp->mac_mode &
2648                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2649                         if (mac_mode & MAC_MODE_APE_TX_EN)
2650                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2651                 }
2652
2653                 tw32_f(MAC_MODE, mac_mode);
2654                 udelay(100);
2655
2656                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2657                 udelay(10);
2658         }
2659
2660         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2661             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2662              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2663                 u32 base_val;
2664
2665                 base_val = tp->pci_clock_ctrl;
2666                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2667                              CLOCK_CTRL_TXCLK_DISABLE);
2668
2669                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2670                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2671         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2672                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2673                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2674                 /* do nothing */
2675         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2676                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2677                 u32 newbits1, newbits2;
2678
2679                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2680                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2681                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2682                                     CLOCK_CTRL_TXCLK_DISABLE |
2683                                     CLOCK_CTRL_ALTCLK);
2684                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2685                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2686                         newbits1 = CLOCK_CTRL_625_CORE;
2687                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2688                 } else {
2689                         newbits1 = CLOCK_CTRL_ALTCLK;
2690                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2691                 }
2692
2693                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2694                             40);
2695
2696                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2697                             40);
2698
2699                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2700                         u32 newbits3;
2701
2702                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2703                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2704                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2705                                             CLOCK_CTRL_TXCLK_DISABLE |
2706                                             CLOCK_CTRL_44MHZ_CORE);
2707                         } else {
2708                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2709                         }
2710
2711                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2712                                     tp->pci_clock_ctrl | newbits3, 40);
2713                 }
2714         }
2715
2716         if (!(device_should_wake) &&
2717             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2718                 tg3_power_down_phy(tp, do_low_power);
2719
2720         tg3_frob_aux_power(tp);
2721
2722         /* Workaround for unstable PLL clock */
2723         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2724             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2725                 u32 val = tr32(0x7d00);
2726
2727                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2728                 tw32(0x7d00, val);
2729                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2730                         int err;
2731
2732                         err = tg3_nvram_lock(tp);
2733                         tg3_halt_cpu(tp, RX_CPU_BASE);
2734                         if (!err)
2735                                 tg3_nvram_unlock(tp);
2736                 }
2737         }
2738
2739         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2740
2741         if (device_should_wake)
2742                 pci_enable_wake(tp->pdev, state, true);
2743
2744         /* Finally, set the new power state. */
2745         pci_set_power_state(tp->pdev, state);
2746
2747         return 0;
2748 }
2749
2750 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2751 {
2752         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2753         case MII_TG3_AUX_STAT_10HALF:
2754                 *speed = SPEED_10;
2755                 *duplex = DUPLEX_HALF;
2756                 break;
2757
2758         case MII_TG3_AUX_STAT_10FULL:
2759                 *speed = SPEED_10;
2760                 *duplex = DUPLEX_FULL;
2761                 break;
2762
2763         case MII_TG3_AUX_STAT_100HALF:
2764                 *speed = SPEED_100;
2765                 *duplex = DUPLEX_HALF;
2766                 break;
2767
2768         case MII_TG3_AUX_STAT_100FULL:
2769                 *speed = SPEED_100;
2770                 *duplex = DUPLEX_FULL;
2771                 break;
2772
2773         case MII_TG3_AUX_STAT_1000HALF:
2774                 *speed = SPEED_1000;
2775                 *duplex = DUPLEX_HALF;
2776                 break;
2777
2778         case MII_TG3_AUX_STAT_1000FULL:
2779                 *speed = SPEED_1000;
2780                 *duplex = DUPLEX_FULL;
2781                 break;
2782
2783         default:
2784                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2785                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2786                                  SPEED_10;
2787                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2788                                   DUPLEX_HALF;
2789                         break;
2790                 }
2791                 *speed = SPEED_INVALID;
2792                 *duplex = DUPLEX_INVALID;
2793                 break;
2794         }
2795 }
2796
2797 static void tg3_phy_copper_begin(struct tg3 *tp)
2798 {
2799         u32 new_adv;
2800         int i;
2801
2802         if (tp->link_config.phy_is_low_power) {
2803                 /* Entering low power mode.  Disable gigabit and
2804                  * 100baseT advertisements.
2805                  */
2806                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2807
2808                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2809                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2810                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2811                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2812
2813                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2814         } else if (tp->link_config.speed == SPEED_INVALID) {
2815                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2816                         tp->link_config.advertising &=
2817                                 ~(ADVERTISED_1000baseT_Half |
2818                                   ADVERTISED_1000baseT_Full);
2819
2820                 new_adv = ADVERTISE_CSMA;
2821                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2822                         new_adv |= ADVERTISE_10HALF;
2823                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2824                         new_adv |= ADVERTISE_10FULL;
2825                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2826                         new_adv |= ADVERTISE_100HALF;
2827                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2828                         new_adv |= ADVERTISE_100FULL;
2829
2830                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2831
2832                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2833
2834                 if (tp->link_config.advertising &
2835                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2836                         new_adv = 0;
2837                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2838                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2839                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2840                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2841                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2842                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2843                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2844                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2845                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2846                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2847                 } else {
2848                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2849                 }
2850         } else {
2851                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2852                 new_adv |= ADVERTISE_CSMA;
2853
2854                 /* Asking for a specific link mode. */
2855                 if (tp->link_config.speed == SPEED_1000) {
2856                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2857
2858                         if (tp->link_config.duplex == DUPLEX_FULL)
2859                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2860                         else
2861                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2862                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2863                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2864                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2865                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2866                 } else {
2867                         if (tp->link_config.speed == SPEED_100) {
2868                                 if (tp->link_config.duplex == DUPLEX_FULL)
2869                                         new_adv |= ADVERTISE_100FULL;
2870                                 else
2871                                         new_adv |= ADVERTISE_100HALF;
2872                         } else {
2873                                 if (tp->link_config.duplex == DUPLEX_FULL)
2874                                         new_adv |= ADVERTISE_10FULL;
2875                                 else
2876                                         new_adv |= ADVERTISE_10HALF;
2877                         }
2878                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2879
2880                         new_adv = 0;
2881                 }
2882
2883                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2884         }
2885
2886         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2887             tp->link_config.speed != SPEED_INVALID) {
2888                 u32 bmcr, orig_bmcr;
2889
2890                 tp->link_config.active_speed = tp->link_config.speed;
2891                 tp->link_config.active_duplex = tp->link_config.duplex;
2892
2893                 bmcr = 0;
2894                 switch (tp->link_config.speed) {
2895                 default:
2896                 case SPEED_10:
2897                         break;
2898
2899                 case SPEED_100:
2900                         bmcr |= BMCR_SPEED100;
2901                         break;
2902
2903                 case SPEED_1000:
2904                         bmcr |= TG3_BMCR_SPEED1000;
2905                         break;
2906                 }
2907
2908                 if (tp->link_config.duplex == DUPLEX_FULL)
2909                         bmcr |= BMCR_FULLDPLX;
2910
2911                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2912                     (bmcr != orig_bmcr)) {
2913                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2914                         for (i = 0; i < 1500; i++) {
2915                                 u32 tmp;
2916
2917                                 udelay(10);
2918                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2919                                     tg3_readphy(tp, MII_BMSR, &tmp))
2920                                         continue;
2921                                 if (!(tmp & BMSR_LSTATUS)) {
2922                                         udelay(40);
2923                                         break;
2924                                 }
2925                         }
2926                         tg3_writephy(tp, MII_BMCR, bmcr);
2927                         udelay(40);
2928                 }
2929         } else {
2930                 tg3_writephy(tp, MII_BMCR,
2931                              BMCR_ANENABLE | BMCR_ANRESTART);
2932         }
2933 }
2934
2935 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2936 {
2937         int err;
2938
2939         /* Turn off tap power management. */
2940         /* Set Extended packet length bit */
2941         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2942
2943         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2944         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2945
2946         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2947         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2948
2949         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2950         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2951
2952         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2953         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2954
2955         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2956         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2957
2958         udelay(40);
2959
2960         return err;
2961 }
2962
2963 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2964 {
2965         u32 adv_reg, all_mask = 0;
2966
2967         if (mask & ADVERTISED_10baseT_Half)
2968                 all_mask |= ADVERTISE_10HALF;
2969         if (mask & ADVERTISED_10baseT_Full)
2970                 all_mask |= ADVERTISE_10FULL;
2971         if (mask & ADVERTISED_100baseT_Half)
2972                 all_mask |= ADVERTISE_100HALF;
2973         if (mask & ADVERTISED_100baseT_Full)
2974                 all_mask |= ADVERTISE_100FULL;
2975
2976         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2977                 return 0;
2978
2979         if ((adv_reg & all_mask) != all_mask)
2980                 return 0;
2981         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2982                 u32 tg3_ctrl;
2983
2984                 all_mask = 0;
2985                 if (mask & ADVERTISED_1000baseT_Half)
2986                         all_mask |= ADVERTISE_1000HALF;
2987                 if (mask & ADVERTISED_1000baseT_Full)
2988                         all_mask |= ADVERTISE_1000FULL;
2989
2990                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2991                         return 0;
2992
2993                 if ((tg3_ctrl & all_mask) != all_mask)
2994                         return 0;
2995         }
2996         return 1;
2997 }
2998
2999 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3000 {
3001         u32 curadv, reqadv;
3002
3003         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3004                 return 1;
3005
3006         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3007         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3008
3009         if (tp->link_config.active_duplex == DUPLEX_FULL) {
3010                 if (curadv != reqadv)
3011                         return 0;
3012
3013                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3014                         tg3_readphy(tp, MII_LPA, rmtadv);
3015         } else {
3016                 /* Reprogram the advertisement register, even if it
3017                  * does not affect the current link.  If the link
3018                  * gets renegotiated in the future, we can save an
3019                  * additional renegotiation cycle by advertising
3020                  * it correctly in the first place.
3021                  */
3022                 if (curadv != reqadv) {
3023                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3024                                      ADVERTISE_PAUSE_ASYM);
3025                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3026                 }
3027         }
3028
3029         return 1;
3030 }
3031
3032 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3033 {
3034         int current_link_up;
3035         u32 bmsr, dummy;
3036         u32 lcl_adv, rmt_adv;
3037         u16 current_speed;
3038         u8 current_duplex;
3039         int i, err;
3040
3041         tw32(MAC_EVENT, 0);
3042
3043         tw32_f(MAC_STATUS,
3044              (MAC_STATUS_SYNC_CHANGED |
3045               MAC_STATUS_CFG_CHANGED |
3046               MAC_STATUS_MI_COMPLETION |
3047               MAC_STATUS_LNKSTATE_CHANGED));
3048         udelay(40);
3049
3050         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3051                 tw32_f(MAC_MI_MODE,
3052                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3053                 udelay(80);
3054         }
3055
3056         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3057
3058         /* Some third-party PHYs need to be reset on link going
3059          * down.
3060          */
3061         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3062              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3063              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3064             netif_carrier_ok(tp->dev)) {
3065                 tg3_readphy(tp, MII_BMSR, &bmsr);
3066                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3067                     !(bmsr & BMSR_LSTATUS))
3068                         force_reset = 1;
3069         }
3070         if (force_reset)
3071                 tg3_phy_reset(tp);
3072
3073         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3074                 tg3_readphy(tp, MII_BMSR, &bmsr);
3075                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3076                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3077                         bmsr = 0;
3078
3079                 if (!(bmsr & BMSR_LSTATUS)) {
3080                         err = tg3_init_5401phy_dsp(tp);
3081                         if (err)
3082                                 return err;
3083
3084                         tg3_readphy(tp, MII_BMSR, &bmsr);
3085                         for (i = 0; i < 1000; i++) {
3086                                 udelay(10);
3087                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3088                                     (bmsr & BMSR_LSTATUS)) {
3089                                         udelay(40);
3090                                         break;
3091                                 }
3092                         }
3093
3094                         if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3095                             TG3_PHY_REV_BCM5401_B0 &&
3096                             !(bmsr & BMSR_LSTATUS) &&
3097                             tp->link_config.active_speed == SPEED_1000) {
3098                                 err = tg3_phy_reset(tp);
3099                                 if (!err)
3100                                         err = tg3_init_5401phy_dsp(tp);
3101                                 if (err)
3102                                         return err;
3103                         }
3104                 }
3105         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3106                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3107                 /* 5701 {A0,B0} CRC bug workaround */
3108                 tg3_writephy(tp, 0x15, 0x0a75);
3109                 tg3_writephy(tp, 0x1c, 0x8c68);
3110                 tg3_writephy(tp, 0x1c, 0x8d68);
3111                 tg3_writephy(tp, 0x1c, 0x8c68);
3112         }
3113
3114         /* Clear pending interrupts... */
3115         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3116         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3117
3118         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3119                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3120         else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3121                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3122
3123         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3124             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3125                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3126                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3127                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3128                 else
3129                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3130         }
3131
3132         current_link_up = 0;
3133         current_speed = SPEED_INVALID;
3134         current_duplex = DUPLEX_INVALID;
3135
3136         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3137                 u32 val;
3138
3139                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3140                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3141                 if (!(val & (1 << 10))) {
3142                         val |= (1 << 10);
3143                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3144                         goto relink;
3145                 }
3146         }
3147
3148         bmsr = 0;
3149         for (i = 0; i < 100; i++) {
3150                 tg3_readphy(tp, MII_BMSR, &bmsr);
3151                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3152                     (bmsr & BMSR_LSTATUS))
3153                         break;
3154                 udelay(40);
3155         }
3156
3157         if (bmsr & BMSR_LSTATUS) {
3158                 u32 aux_stat, bmcr;
3159
3160                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3161                 for (i = 0; i < 2000; i++) {
3162                         udelay(10);
3163                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3164                             aux_stat)
3165                                 break;
3166                 }
3167
3168                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3169                                              &current_speed,
3170                                              &current_duplex);
3171
3172                 bmcr = 0;
3173                 for (i = 0; i < 200; i++) {
3174                         tg3_readphy(tp, MII_BMCR, &bmcr);
3175                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3176                                 continue;
3177                         if (bmcr && bmcr != 0x7fff)
3178                                 break;
3179                         udelay(10);
3180                 }
3181
3182                 lcl_adv = 0;
3183                 rmt_adv = 0;
3184
3185                 tp->link_config.active_speed = current_speed;
3186                 tp->link_config.active_duplex = current_duplex;
3187
3188                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3189                         if ((bmcr & BMCR_ANENABLE) &&
3190                             tg3_copper_is_advertising_all(tp,
3191                                                 tp->link_config.advertising)) {
3192                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3193                                                                   &rmt_adv))
3194                                         current_link_up = 1;
3195                         }
3196                 } else {
3197                         if (!(bmcr & BMCR_ANENABLE) &&
3198                             tp->link_config.speed == current_speed &&
3199                             tp->link_config.duplex == current_duplex &&
3200                             tp->link_config.flowctrl ==
3201                             tp->link_config.active_flowctrl) {
3202                                 current_link_up = 1;
3203                         }
3204                 }
3205
3206                 if (current_link_up == 1 &&
3207                     tp->link_config.active_duplex == DUPLEX_FULL)
3208                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3209         }
3210
3211 relink:
3212         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3213                 u32 tmp;
3214
3215                 tg3_phy_copper_begin(tp);
3216
3217                 tg3_readphy(tp, MII_BMSR, &tmp);
3218                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3219                     (tmp & BMSR_LSTATUS))
3220                         current_link_up = 1;
3221         }
3222
3223         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3224         if (current_link_up == 1) {
3225                 if (tp->link_config.active_speed == SPEED_100 ||
3226                     tp->link_config.active_speed == SPEED_10)
3227                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3228                 else
3229                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3230         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3231                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3232         else
3233                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3234
3235         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3236         if (tp->link_config.active_duplex == DUPLEX_HALF)
3237                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3238
3239         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3240                 if (current_link_up == 1 &&
3241                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3242                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3243                 else
3244                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3245         }
3246
3247         /* ??? Without this setting Netgear GA302T PHY does not
3248          * ??? send/receive packets...
3249          */
3250         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3251             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3252                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3253                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3254                 udelay(80);
3255         }
3256
3257         tw32_f(MAC_MODE, tp->mac_mode);
3258         udelay(40);
3259
3260         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3261                 /* Polled via timer. */
3262                 tw32_f(MAC_EVENT, 0);
3263         } else {
3264                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3265         }
3266         udelay(40);
3267
3268         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3269             current_link_up == 1 &&
3270             tp->link_config.active_speed == SPEED_1000 &&
3271             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3272              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3273                 udelay(120);
3274                 tw32_f(MAC_STATUS,
3275                      (MAC_STATUS_SYNC_CHANGED |
3276                       MAC_STATUS_CFG_CHANGED));
3277                 udelay(40);
3278                 tg3_write_mem(tp,
3279                               NIC_SRAM_FIRMWARE_MBOX,
3280                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3281         }
3282
3283         /* Prevent send BD corruption. */
3284         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3285                 u16 oldlnkctl, newlnkctl;
3286
3287                 pci_read_config_word(tp->pdev,
3288                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3289                                      &oldlnkctl);
3290                 if (tp->link_config.active_speed == SPEED_100 ||
3291                     tp->link_config.active_speed == SPEED_10)
3292                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3293                 else
3294                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3295                 if (newlnkctl != oldlnkctl)
3296                         pci_write_config_word(tp->pdev,
3297                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3298                                               newlnkctl);
3299         }
3300
3301         if (current_link_up != netif_carrier_ok(tp->dev)) {
3302                 if (current_link_up)
3303                         netif_carrier_on(tp->dev);
3304                 else
3305                         netif_carrier_off(tp->dev);
3306                 tg3_link_report(tp);
3307         }
3308
3309         return 0;
3310 }
3311
3312 struct tg3_fiber_aneginfo {
3313         int state;
3314 #define ANEG_STATE_UNKNOWN              0
3315 #define ANEG_STATE_AN_ENABLE            1
3316 #define ANEG_STATE_RESTART_INIT         2
3317 #define ANEG_STATE_RESTART              3
3318 #define ANEG_STATE_DISABLE_LINK_OK      4
3319 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3320 #define ANEG_STATE_ABILITY_DETECT       6
3321 #define ANEG_STATE_ACK_DETECT_INIT      7
3322 #define ANEG_STATE_ACK_DETECT           8
3323 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3324 #define ANEG_STATE_COMPLETE_ACK         10
3325 #define ANEG_STATE_IDLE_DETECT_INIT     11
3326 #define ANEG_STATE_IDLE_DETECT          12
3327 #define ANEG_STATE_LINK_OK              13
3328 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3329 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3330
3331         u32 flags;
3332 #define MR_AN_ENABLE            0x00000001
3333 #define MR_RESTART_AN           0x00000002
3334 #define MR_AN_COMPLETE          0x00000004
3335 #define MR_PAGE_RX              0x00000008
3336 #define MR_NP_LOADED            0x00000010
3337 #define MR_TOGGLE_TX            0x00000020
3338 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3339 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3340 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3341 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3342 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3343 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3344 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3345 #define MR_TOGGLE_RX            0x00002000
3346 #define MR_NP_RX                0x00004000
3347
3348 #define MR_LINK_OK              0x80000000
3349
3350         unsigned long link_time, cur_time;
3351
3352         u32 ability_match_cfg;
3353         int ability_match_count;
3354
3355         char ability_match, idle_match, ack_match;
3356
3357         u32 txconfig, rxconfig;
3358 #define ANEG_CFG_NP             0x00000080
3359 #define ANEG_CFG_ACK            0x00000040
3360 #define ANEG_CFG_RF2            0x00000020
3361 #define ANEG_CFG_RF1            0x00000010
3362 #define ANEG_CFG_PS2            0x00000001
3363 #define ANEG_CFG_PS1            0x00008000
3364 #define ANEG_CFG_HD             0x00004000
3365 #define ANEG_CFG_FD             0x00002000
3366 #define ANEG_CFG_INVAL          0x00001f06
3367
3368 };
3369 #define ANEG_OK         0
3370 #define ANEG_DONE       1
3371 #define ANEG_TIMER_ENAB 2
3372 #define ANEG_FAILED     -1
3373
3374 #define ANEG_STATE_SETTLE_TIME  10000
3375
3376 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3377                                    struct tg3_fiber_aneginfo *ap)
3378 {
3379         u16 flowctrl;
3380         unsigned long delta;
3381         u32 rx_cfg_reg;
3382         int ret;
3383
3384         if (ap->state == ANEG_STATE_UNKNOWN) {
3385                 ap->rxconfig = 0;
3386                 ap->link_time = 0;
3387                 ap->cur_time = 0;
3388                 ap->ability_match_cfg = 0;
3389                 ap->ability_match_count = 0;
3390                 ap->ability_match = 0;
3391                 ap->idle_match = 0;
3392                 ap->ack_match = 0;
3393         }
3394         ap->cur_time++;
3395
3396         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3397                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3398
3399                 if (rx_cfg_reg != ap->ability_match_cfg) {
3400                         ap->ability_match_cfg = rx_cfg_reg;
3401                         ap->ability_match = 0;
3402                         ap->ability_match_count = 0;
3403                 } else {
3404                         if (++ap->ability_match_count > 1) {
3405                                 ap->ability_match = 1;
3406                                 ap->ability_match_cfg = rx_cfg_reg;
3407                         }
3408                 }
3409                 if (rx_cfg_reg & ANEG_CFG_ACK)
3410                         ap->ack_match = 1;
3411                 else
3412                         ap->ack_match = 0;
3413
3414                 ap->idle_match = 0;
3415         } else {
3416                 ap->idle_match = 1;
3417                 ap->ability_match_cfg = 0;
3418                 ap->ability_match_count = 0;
3419                 ap->ability_match = 0;
3420                 ap->ack_match = 0;
3421
3422                 rx_cfg_reg = 0;
3423         }
3424
3425         ap->rxconfig = rx_cfg_reg;
3426         ret = ANEG_OK;
3427
3428         switch(ap->state) {
3429         case ANEG_STATE_UNKNOWN:
3430                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3431                         ap->state = ANEG_STATE_AN_ENABLE;
3432
3433                 /* fallthru */
3434         case ANEG_STATE_AN_ENABLE:
3435                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3436                 if (ap->flags & MR_AN_ENABLE) {
3437                         ap->link_time = 0;
3438                         ap->cur_time = 0;
3439                         ap->ability_match_cfg = 0;
3440                         ap->ability_match_count = 0;
3441                         ap->ability_match = 0;
3442                         ap->idle_match = 0;
3443                         ap->ack_match = 0;
3444
3445                         ap->state = ANEG_STATE_RESTART_INIT;
3446                 } else {
3447                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3448                 }
3449                 break;
3450
3451         case ANEG_STATE_RESTART_INIT:
3452                 ap->link_time = ap->cur_time;
3453                 ap->flags &= ~(MR_NP_LOADED);
3454                 ap->txconfig = 0;
3455                 tw32(MAC_TX_AUTO_NEG, 0);
3456                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3457                 tw32_f(MAC_MODE, tp->mac_mode);
3458                 udelay(40);
3459
3460                 ret = ANEG_TIMER_ENAB;
3461                 ap->state = ANEG_STATE_RESTART;
3462
3463                 /* fallthru */
3464         case ANEG_STATE_RESTART:
3465                 delta = ap->cur_time - ap->link_time;
3466                 if (delta > ANEG_STATE_SETTLE_TIME) {
3467                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3468                 } else {
3469                         ret = ANEG_TIMER_ENAB;
3470                 }
3471                 break;
3472
3473         case ANEG_STATE_DISABLE_LINK_OK:
3474                 ret = ANEG_DONE;
3475                 break;
3476
3477         case ANEG_STATE_ABILITY_DETECT_INIT:
3478                 ap->flags &= ~(MR_TOGGLE_TX);
3479                 ap->txconfig = ANEG_CFG_FD;
3480                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3481                 if (flowctrl & ADVERTISE_1000XPAUSE)
3482                         ap->txconfig |= ANEG_CFG_PS1;
3483                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3484                         ap->txconfig |= ANEG_CFG_PS2;
3485                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3486                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3487                 tw32_f(MAC_MODE, tp->mac_mode);
3488                 udelay(40);
3489
3490                 ap->state = ANEG_STATE_ABILITY_DETECT;
3491                 break;
3492
3493         case ANEG_STATE_ABILITY_DETECT:
3494                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3495                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3496                 }
3497                 break;
3498
3499         case ANEG_STATE_ACK_DETECT_INIT:
3500                 ap->txconfig |= ANEG_CFG_ACK;
3501                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3502                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3503                 tw32_f(MAC_MODE, tp->mac_mode);
3504                 udelay(40);
3505
3506                 ap->state = ANEG_STATE_ACK_DETECT;
3507
3508                 /* fallthru */
3509         case ANEG_STATE_ACK_DETECT:
3510                 if (ap->ack_match != 0) {
3511                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3512                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3513                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3514                         } else {
3515                                 ap->state = ANEG_STATE_AN_ENABLE;
3516                         }
3517                 } else if (ap->ability_match != 0 &&
3518                            ap->rxconfig == 0) {
3519                         ap->state = ANEG_STATE_AN_ENABLE;
3520                 }
3521                 break;
3522
3523         case ANEG_STATE_COMPLETE_ACK_INIT:
3524                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3525                         ret = ANEG_FAILED;
3526                         break;
3527                 }
3528                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3529                                MR_LP_ADV_HALF_DUPLEX |
3530                                MR_LP_ADV_SYM_PAUSE |
3531                                MR_LP_ADV_ASYM_PAUSE |
3532                                MR_LP_ADV_REMOTE_FAULT1 |
3533                                MR_LP_ADV_REMOTE_FAULT2 |
3534                                MR_LP_ADV_NEXT_PAGE |
3535                                MR_TOGGLE_RX |
3536                                MR_NP_RX);
3537                 if (ap->rxconfig & ANEG_CFG_FD)
3538                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3539                 if (ap->rxconfig & ANEG_CFG_HD)
3540                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3541                 if (ap->rxconfig & ANEG_CFG_PS1)
3542                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3543                 if (ap->rxconfig & ANEG_CFG_PS2)
3544                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3545                 if (ap->rxconfig & ANEG_CFG_RF1)
3546                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3547                 if (ap->rxconfig & ANEG_CFG_RF2)
3548                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3549                 if (ap->rxconfig & ANEG_CFG_NP)
3550                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3551
3552                 ap->link_time = ap->cur_time;
3553
3554                 ap->flags ^= (MR_TOGGLE_TX);
3555                 if (ap->rxconfig & 0x0008)
3556                         ap->flags |= MR_TOGGLE_RX;
3557                 if (ap->rxconfig & ANEG_CFG_NP)
3558                         ap->flags |= MR_NP_RX;
3559                 ap->flags |= MR_PAGE_RX;
3560
3561                 ap->state = ANEG_STATE_COMPLETE_ACK;
3562                 ret = ANEG_TIMER_ENAB;
3563                 break;
3564
3565         case ANEG_STATE_COMPLETE_ACK:
3566                 if (ap->ability_match != 0 &&
3567                     ap->rxconfig == 0) {
3568                         ap->state = ANEG_STATE_AN_ENABLE;
3569                         break;
3570                 }
3571                 delta = ap->cur_time - ap->link_time;
3572                 if (delta > ANEG_STATE_SETTLE_TIME) {
3573                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3574                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3575                         } else {
3576                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3577                                     !(ap->flags & MR_NP_RX)) {
3578                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3579                                 } else {
3580                                         ret = ANEG_FAILED;
3581                                 }
3582                         }
3583                 }
3584                 break;
3585
3586         case ANEG_STATE_IDLE_DETECT_INIT:
3587                 ap->link_time = ap->cur_time;
3588                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3589                 tw32_f(MAC_MODE, tp->mac_mode);
3590                 udelay(40);
3591
3592                 ap->state = ANEG_STATE_IDLE_DETECT;
3593                 ret = ANEG_TIMER_ENAB;
3594                 break;
3595
3596         case ANEG_STATE_IDLE_DETECT:
3597                 if (ap->ability_match != 0 &&
3598                     ap->rxconfig == 0) {
3599                         ap->state = ANEG_STATE_AN_ENABLE;
3600                         break;
3601                 }
3602                 delta = ap->cur_time - ap->link_time;
3603                 if (delta > ANEG_STATE_SETTLE_TIME) {
3604                         /* XXX another gem from the Broadcom driver :( */
3605                         ap->state = ANEG_STATE_LINK_OK;
3606                 }
3607                 break;
3608
3609         case ANEG_STATE_LINK_OK:
3610                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3611                 ret = ANEG_DONE;
3612                 break;
3613
3614         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3615                 /* ??? unimplemented */
3616                 break;
3617
3618         case ANEG_STATE_NEXT_PAGE_WAIT:
3619                 /* ??? unimplemented */
3620                 break;
3621
3622         default:
3623                 ret = ANEG_FAILED;
3624                 break;
3625         }
3626
3627         return ret;
3628 }
3629
3630 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3631 {
3632         int res = 0;
3633         struct tg3_fiber_aneginfo aninfo;
3634         int status = ANEG_FAILED;
3635         unsigned int tick;
3636         u32 tmp;
3637
3638         tw32_f(MAC_TX_AUTO_NEG, 0);
3639
3640         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3641         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3642         udelay(40);
3643
3644         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3645         udelay(40);
3646
3647         memset(&aninfo, 0, sizeof(aninfo));
3648         aninfo.flags |= MR_AN_ENABLE;
3649         aninfo.state = ANEG_STATE_UNKNOWN;
3650         aninfo.cur_time = 0;
3651         tick = 0;
3652         while (++tick < 195000) {
3653                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3654                 if (status == ANEG_DONE || status == ANEG_FAILED)
3655                         break;
3656
3657                 udelay(1);
3658         }
3659
3660         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3661         tw32_f(MAC_MODE, tp->mac_mode);
3662         udelay(40);
3663
3664         *txflags = aninfo.txconfig;
3665         *rxflags = aninfo.flags;
3666
3667         if (status == ANEG_DONE &&
3668             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3669                              MR_LP_ADV_FULL_DUPLEX)))
3670                 res = 1;
3671
3672         return res;
3673 }
3674
3675 static void tg3_init_bcm8002(struct tg3 *tp)
3676 {
3677         u32 mac_status = tr32(MAC_STATUS);
3678         int i;
3679
3680         /* Reset when initting first time or we have a link. */
3681         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3682             !(mac_status & MAC_STATUS_PCS_SYNCED))
3683                 return;
3684
3685         /* Set PLL lock range. */
3686         tg3_writephy(tp, 0x16, 0x8007);
3687
3688         /* SW reset */
3689         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3690
3691         /* Wait for reset to complete. */
3692         /* XXX schedule_timeout() ... */
3693         for (i = 0; i < 500; i++)
3694                 udelay(10);
3695
3696         /* Config mode; select PMA/Ch 1 regs. */
3697         tg3_writephy(tp, 0x10, 0x8411);
3698
3699         /* Enable auto-lock and comdet, select txclk for tx. */
3700         tg3_writephy(tp, 0x11, 0x0a10);
3701
3702         tg3_writephy(tp, 0x18, 0x00a0);
3703         tg3_writephy(tp, 0x16, 0x41ff);
3704
3705         /* Assert and deassert POR. */
3706         tg3_writephy(tp, 0x13, 0x0400);
3707         udelay(40);
3708         tg3_writephy(tp, 0x13, 0x0000);
3709
3710         tg3_writephy(tp, 0x11, 0x0a50);
3711         udelay(40);
3712         tg3_writephy(tp, 0x11, 0x0a10);
3713
3714         /* Wait for signal to stabilize */
3715         /* XXX schedule_timeout() ... */
3716         for (i = 0; i < 15000; i++)
3717                 udelay(10);
3718
3719         /* Deselect the channel register so we can read the PHYID
3720          * later.
3721          */
3722         tg3_writephy(tp, 0x10, 0x8011);
3723 }
3724
3725 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3726 {
3727         u16 flowctrl;
3728         u32 sg_dig_ctrl, sg_dig_status;
3729         u32 serdes_cfg, expected_sg_dig_ctrl;
3730         int workaround, port_a;
3731         int current_link_up;
3732
3733         serdes_cfg = 0;
3734         expected_sg_dig_ctrl = 0;
3735         workaround = 0;
3736         port_a = 1;
3737         current_link_up = 0;
3738
3739         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3740             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3741                 workaround = 1;
3742                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3743                         port_a = 0;
3744
3745                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3746                 /* preserve bits 20-23 for voltage regulator */
3747                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3748         }
3749
3750         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3751
3752         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3753                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3754                         if (workaround) {
3755                                 u32 val = serdes_cfg;
3756
3757                                 if (port_a)
3758                                         val |= 0xc010000;
3759                                 else
3760                                         val |= 0x4010000;
3761                                 tw32_f(MAC_SERDES_CFG, val);
3762                         }
3763
3764                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3765                 }
3766                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3767                         tg3_setup_flow_control(tp, 0, 0);
3768                         current_link_up = 1;
3769                 }
3770                 goto out;
3771         }
3772
3773         /* Want auto-negotiation.  */
3774         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3775
3776         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3777         if (flowctrl & ADVERTISE_1000XPAUSE)
3778                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3779         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3780                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3781
3782         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3783                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3784                     tp->serdes_counter &&
3785                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3786                                     MAC_STATUS_RCVD_CFG)) ==
3787                      MAC_STATUS_PCS_SYNCED)) {
3788                         tp->serdes_counter--;
3789                         current_link_up = 1;
3790                         goto out;
3791                 }
3792 restart_autoneg:
3793                 if (workaround)
3794                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3795                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3796                 udelay(5);
3797                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3798
3799                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3800                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3801         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3802                                  MAC_STATUS_SIGNAL_DET)) {
3803                 sg_dig_status = tr32(SG_DIG_STATUS);
3804                 mac_status = tr32(MAC_STATUS);
3805
3806                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3807                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3808                         u32 local_adv = 0, remote_adv = 0;
3809
3810                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3811                                 local_adv |= ADVERTISE_1000XPAUSE;
3812                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3813                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3814
3815                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3816                                 remote_adv |= LPA_1000XPAUSE;
3817                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3818                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3819
3820                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3821                         current_link_up = 1;
3822                         tp->serdes_counter = 0;
3823                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3824                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3825                         if (tp->serdes_counter)
3826                                 tp->serdes_counter--;
3827                         else {
3828                                 if (workaround) {
3829                                         u32 val = serdes_cfg;
3830
3831                                         if (port_a)
3832                                                 val |= 0xc010000;
3833                                         else
3834                                                 val |= 0x4010000;
3835
3836                                         tw32_f(MAC_SERDES_CFG, val);
3837                                 }
3838
3839                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3840                                 udelay(40);
3841
3842                                 /* Link parallel detection - link is up */
3843                                 /* only if we have PCS_SYNC and not */
3844                                 /* receiving config code words */
3845                                 mac_status = tr32(MAC_STATUS);
3846                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3847                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3848                                         tg3_setup_flow_control(tp, 0, 0);
3849                                         current_link_up = 1;
3850                                         tp->tg3_flags2 |=
3851                                                 TG3_FLG2_PARALLEL_DETECT;
3852                                         tp->serdes_counter =
3853                                                 SERDES_PARALLEL_DET_TIMEOUT;
3854                                 } else
3855                                         goto restart_autoneg;
3856                         }
3857                 }
3858         } else {
3859                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3860                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3861         }
3862
3863 out:
3864         return current_link_up;
3865 }
3866
3867 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3868 {
3869         int current_link_up = 0;
3870
3871         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3872                 goto out;
3873
3874         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3875                 u32 txflags, rxflags;
3876                 int i;
3877
3878                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3879                         u32 local_adv = 0, remote_adv = 0;
3880
3881                         if (txflags & ANEG_CFG_PS1)
3882                                 local_adv |= ADVERTISE_1000XPAUSE;
3883                         if (txflags & ANEG_CFG_PS2)
3884                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3885
3886                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3887                                 remote_adv |= LPA_1000XPAUSE;
3888                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3889                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3890
3891                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3892
3893                         current_link_up = 1;
3894                 }
3895                 for (i = 0; i < 30; i++) {
3896                         udelay(20);
3897                         tw32_f(MAC_STATUS,
3898                                (MAC_STATUS_SYNC_CHANGED |
3899                                 MAC_STATUS_CFG_CHANGED));
3900                         udelay(40);
3901                         if ((tr32(MAC_STATUS) &
3902                              (MAC_STATUS_SYNC_CHANGED |
3903                               MAC_STATUS_CFG_CHANGED)) == 0)
3904                                 break;
3905                 }
3906
3907                 mac_status = tr32(MAC_STATUS);
3908                 if (current_link_up == 0 &&
3909                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3910                     !(mac_status & MAC_STATUS_RCVD_CFG))
3911                         current_link_up = 1;
3912         } else {
3913                 tg3_setup_flow_control(tp, 0, 0);
3914
3915                 /* Forcing 1000FD link up. */
3916                 current_link_up = 1;
3917
3918                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3919                 udelay(40);
3920
3921                 tw32_f(MAC_MODE, tp->mac_mode);
3922                 udelay(40);
3923         }
3924
3925 out:
3926         return current_link_up;
3927 }
3928
3929 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3930 {
3931         u32 orig_pause_cfg;
3932         u16 orig_active_speed;
3933         u8 orig_active_duplex;
3934         u32 mac_status;
3935         int current_link_up;
3936         int i;
3937
3938         orig_pause_cfg = tp->link_config.active_flowctrl;
3939         orig_active_speed = tp->link_config.active_speed;
3940         orig_active_duplex = tp->link_config.active_duplex;
3941
3942         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3943             netif_carrier_ok(tp->dev) &&
3944             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3945                 mac_status = tr32(MAC_STATUS);
3946                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3947                                MAC_STATUS_SIGNAL_DET |
3948                                MAC_STATUS_CFG_CHANGED |
3949                                MAC_STATUS_RCVD_CFG);
3950                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3951                                    MAC_STATUS_SIGNAL_DET)) {
3952                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3953                                             MAC_STATUS_CFG_CHANGED));
3954                         return 0;
3955                 }
3956         }
3957
3958         tw32_f(MAC_TX_AUTO_NEG, 0);
3959
3960         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3961         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3962         tw32_f(MAC_MODE, tp->mac_mode);
3963         udelay(40);
3964
3965         if (tp->phy_id == TG3_PHY_ID_BCM8002)
3966                 tg3_init_bcm8002(tp);
3967
3968         /* Enable link change event even when serdes polling.  */
3969         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3970         udelay(40);
3971
3972         current_link_up = 0;
3973         mac_status = tr32(MAC_STATUS);
3974
3975         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3976                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3977         else
3978                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3979
3980         tp->napi[0].hw_status->status =
3981                 (SD_STATUS_UPDATED |
3982                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3983
3984         for (i = 0; i < 100; i++) {
3985                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3986                                     MAC_STATUS_CFG_CHANGED));
3987                 udelay(5);
3988                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3989                                          MAC_STATUS_CFG_CHANGED |
3990                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3991                         break;
3992         }
3993
3994         mac_status = tr32(MAC_STATUS);
3995         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3996                 current_link_up = 0;
3997                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3998                     tp->serdes_counter == 0) {
3999                         tw32_f(MAC_MODE, (tp->mac_mode |
4000                                           MAC_MODE_SEND_CONFIGS));
4001                         udelay(1);
4002                         tw32_f(MAC_MODE, tp->mac_mode);
4003                 }
4004         }
4005
4006         if (current_link_up == 1) {
4007                 tp->link_config.active_speed = SPEED_1000;
4008                 tp->link_config.active_duplex = DUPLEX_FULL;
4009                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4010                                     LED_CTRL_LNKLED_OVERRIDE |
4011                                     LED_CTRL_1000MBPS_ON));
4012         } else {
4013                 tp->link_config.active_speed = SPEED_INVALID;
4014                 tp->link_config.active_duplex = DUPLEX_INVALID;
4015                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4016                                     LED_CTRL_LNKLED_OVERRIDE |
4017                                     LED_CTRL_TRAFFIC_OVERRIDE));
4018         }
4019
4020         if (current_link_up != netif_carrier_ok(tp->dev)) {
4021                 if (current_link_up)
4022                         netif_carrier_on(tp->dev);
4023                 else
4024                         netif_carrier_off(tp->dev);
4025                 tg3_link_report(tp);
4026         } else {
4027                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4028                 if (orig_pause_cfg != now_pause_cfg ||
4029                     orig_active_speed != tp->link_config.active_speed ||
4030                     orig_active_duplex != tp->link_config.active_duplex)
4031                         tg3_link_report(tp);
4032         }
4033
4034         return 0;
4035 }
4036
4037 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4038 {
4039         int current_link_up, err = 0;
4040         u32 bmsr, bmcr;
4041         u16 current_speed;
4042         u8 current_duplex;
4043         u32 local_adv, remote_adv;
4044
4045         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4046         tw32_f(MAC_MODE, tp->mac_mode);
4047         udelay(40);
4048
4049         tw32(MAC_EVENT, 0);
4050
4051         tw32_f(MAC_STATUS,
4052              (MAC_STATUS_SYNC_CHANGED |
4053               MAC_STATUS_CFG_CHANGED |
4054               MAC_STATUS_MI_COMPLETION |
4055               MAC_STATUS_LNKSTATE_CHANGED));
4056         udelay(40);
4057
4058         if (force_reset)
4059                 tg3_phy_reset(tp);
4060
4061         current_link_up = 0;
4062         current_speed = SPEED_INVALID;
4063         current_duplex = DUPLEX_INVALID;
4064
4065         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4066         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4067         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4068                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4069                         bmsr |= BMSR_LSTATUS;
4070                 else
4071                         bmsr &= ~BMSR_LSTATUS;
4072         }
4073
4074         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4075
4076         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4077             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4078                 /* do nothing, just check for link up at the end */
4079         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4080                 u32 adv, new_adv;
4081
4082                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4083                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4084                                   ADVERTISE_1000XPAUSE |
4085                                   ADVERTISE_1000XPSE_ASYM |
4086                                   ADVERTISE_SLCT);
4087
4088                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4089
4090                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4091                         new_adv |= ADVERTISE_1000XHALF;
4092                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4093                         new_adv |= ADVERTISE_1000XFULL;
4094
4095                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4096                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4097                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4098                         tg3_writephy(tp, MII_BMCR, bmcr);
4099
4100                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4101                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4102                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4103
4104                         return err;
4105                 }
4106         } else {
4107                 u32 new_bmcr;
4108
4109                 bmcr &= ~BMCR_SPEED1000;
4110                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4111
4112                 if (tp->link_config.duplex == DUPLEX_FULL)
4113                         new_bmcr |= BMCR_FULLDPLX;
4114
4115                 if (new_bmcr != bmcr) {
4116                         /* BMCR_SPEED1000 is a reserved bit that needs
4117                          * to be set on write.
4118                          */
4119                         new_bmcr |= BMCR_SPEED1000;
4120
4121                         /* Force a linkdown */
4122                         if (netif_carrier_ok(tp->dev)) {
4123                                 u32 adv;
4124
4125                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4126                                 adv &= ~(ADVERTISE_1000XFULL |
4127                                          ADVERTISE_1000XHALF |
4128                                          ADVERTISE_SLCT);
4129                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4130                                 tg3_writephy(tp, MII_BMCR, bmcr |
4131                                                            BMCR_ANRESTART |
4132                                                            BMCR_ANENABLE);
4133                                 udelay(10);
4134                                 netif_carrier_off(tp->dev);
4135                         }
4136                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4137                         bmcr = new_bmcr;
4138                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4139                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4140                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4141                             ASIC_REV_5714) {
4142                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4143                                         bmsr |= BMSR_LSTATUS;
4144                                 else
4145                                         bmsr &= ~BMSR_LSTATUS;
4146                         }
4147                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4148                 }
4149         }
4150
4151         if (bmsr & BMSR_LSTATUS) {
4152                 current_speed = SPEED_1000;
4153                 current_link_up = 1;
4154                 if (bmcr & BMCR_FULLDPLX)
4155                         current_duplex = DUPLEX_FULL;
4156                 else
4157                         current_duplex = DUPLEX_HALF;
4158
4159                 local_adv = 0;
4160                 remote_adv = 0;
4161
4162                 if (bmcr & BMCR_ANENABLE) {
4163                         u32 common;
4164
4165                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4166                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4167                         common = local_adv & remote_adv;
4168                         if (common & (ADVERTISE_1000XHALF |
4169                                       ADVERTISE_1000XFULL)) {
4170                                 if (common & ADVERTISE_1000XFULL)
4171                                         current_duplex = DUPLEX_FULL;
4172                                 else
4173                                         current_duplex = DUPLEX_HALF;
4174                         }
4175                         else
4176                                 current_link_up = 0;
4177                 }
4178         }
4179
4180         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4181                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4182
4183         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4184         if (tp->link_config.active_duplex == DUPLEX_HALF)
4185                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4186
4187         tw32_f(MAC_MODE, tp->mac_mode);
4188         udelay(40);
4189
4190         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4191
4192         tp->link_config.active_speed = current_speed;
4193         tp->link_config.active_duplex = current_duplex;
4194
4195         if (current_link_up != netif_carrier_ok(tp->dev)) {
4196                 if (current_link_up)
4197                         netif_carrier_on(tp->dev);
4198                 else {
4199                         netif_carrier_off(tp->dev);
4200                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4201                 }
4202                 tg3_link_report(tp);
4203         }
4204         return err;
4205 }
4206
4207 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4208 {
4209         if (tp->serdes_counter) {
4210                 /* Give autoneg time to complete. */
4211                 tp->serdes_counter--;
4212                 return;
4213         }
4214         if (!netif_carrier_ok(tp->dev) &&
4215             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4216                 u32 bmcr;
4217
4218                 tg3_readphy(tp, MII_BMCR, &bmcr);
4219                 if (bmcr & BMCR_ANENABLE) {
4220                         u32 phy1, phy2;
4221
4222                         /* Select shadow register 0x1f */
4223                         tg3_writephy(tp, 0x1c, 0x7c00);
4224                         tg3_readphy(tp, 0x1c, &phy1);
4225
4226                         /* Select expansion interrupt status register */
4227                         tg3_writephy(tp, 0x17, 0x0f01);
4228                         tg3_readphy(tp, 0x15, &phy2);
4229                         tg3_readphy(tp, 0x15, &phy2);
4230
4231                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4232                                 /* We have signal detect and not receiving
4233                                  * config code words, link is up by parallel
4234                                  * detection.
4235                                  */
4236
4237                                 bmcr &= ~BMCR_ANENABLE;
4238                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4239                                 tg3_writephy(tp, MII_BMCR, bmcr);
4240                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4241                         }
4242                 }
4243         }
4244         else if (netif_carrier_ok(tp->dev) &&
4245                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4246                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4247                 u32 phy2;
4248
4249                 /* Select expansion interrupt status register */
4250                 tg3_writephy(tp, 0x17, 0x0f01);
4251                 tg3_readphy(tp, 0x15, &phy2);
4252                 if (phy2 & 0x20) {
4253                         u32 bmcr;
4254
4255                         /* Config code words received, turn on autoneg. */
4256                         tg3_readphy(tp, MII_BMCR, &bmcr);
4257                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4258
4259                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4260
4261                 }
4262         }
4263 }
4264
4265 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4266 {
4267         int err;
4268
4269         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4270                 err = tg3_setup_fiber_phy(tp, force_reset);
4271         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4272                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4273         } else {
4274                 err = tg3_setup_copper_phy(tp, force_reset);
4275         }
4276
4277         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4278                 u32 val, scale;
4279
4280                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4281                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4282                         scale = 65;
4283                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4284                         scale = 6;
4285                 else
4286                         scale = 12;
4287
4288                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4289                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4290                 tw32(GRC_MISC_CFG, val);
4291         }
4292
4293         if (tp->link_config.active_speed == SPEED_1000 &&
4294             tp->link_config.active_duplex == DUPLEX_HALF)
4295                 tw32(MAC_TX_LENGTHS,
4296                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4297                       (6 << TX_LENGTHS_IPG_SHIFT) |
4298                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4299         else
4300                 tw32(MAC_TX_LENGTHS,
4301                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4302                       (6 << TX_LENGTHS_IPG_SHIFT) |
4303                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4304
4305         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4306                 if (netif_carrier_ok(tp->dev)) {
4307                         tw32(HOSTCC_STAT_COAL_TICKS,
4308                              tp->coal.stats_block_coalesce_usecs);
4309                 } else {
4310                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4311                 }
4312         }
4313
4314         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4315                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4316                 if (!netif_carrier_ok(tp->dev))
4317                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4318                               tp->pwrmgmt_thresh;
4319                 else
4320                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4321                 tw32(PCIE_PWR_MGMT_THRESH, val);
4322         }
4323
4324         return err;
4325 }
4326
4327 /* This is called whenever we suspect that the system chipset is re-
4328  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4329  * is bogus tx completions. We try to recover by setting the
4330  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4331  * in the workqueue.
4332  */
4333 static void tg3_tx_recover(struct tg3 *tp)
4334 {
4335         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4336                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4337
4338         netdev_warn(tp->dev,
4339                     "The system may be re-ordering memory-mapped I/O "
4340                     "cycles to the network device, attempting to recover. "
4341                     "Please report the problem to the driver maintainer "
4342                     "and include system chipset information.\n");
4343
4344         spin_lock(&tp->lock);
4345         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4346         spin_unlock(&tp->lock);
4347 }
4348
4349 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4350 {
4351         smp_mb();
4352         return tnapi->tx_pending -
4353                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4354 }
4355
4356 /* Tigon3 never reports partial packet sends.  So we do not
4357  * need special logic to handle SKBs that have not had all
4358  * of their frags sent yet, like SunGEM does.
4359  */
4360 static void tg3_tx(struct tg3_napi *tnapi)
4361 {
4362         struct tg3 *tp = tnapi->tp;
4363         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4364         u32 sw_idx = tnapi->tx_cons;
4365         struct netdev_queue *txq;
4366         int index = tnapi - tp->napi;
4367
4368         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4369                 index--;
4370
4371         txq = netdev_get_tx_queue(tp->dev, index);
4372
4373         while (sw_idx != hw_idx) {
4374                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4375                 struct sk_buff *skb = ri->skb;
4376                 int i, tx_bug = 0;
4377
4378                 if (unlikely(skb == NULL)) {
4379                         tg3_tx_recover(tp);
4380                         return;
4381                 }
4382
4383                 pci_unmap_single(tp->pdev,
4384                                  pci_unmap_addr(ri, mapping),
4385                                  skb_headlen(skb),
4386                                  PCI_DMA_TODEVICE);
4387
4388                 ri->skb = NULL;
4389
4390                 sw_idx = NEXT_TX(sw_idx);
4391
4392                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4393                         ri = &tnapi->tx_buffers[sw_idx];
4394                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4395                                 tx_bug = 1;
4396
4397                         pci_unmap_page(tp->pdev,
4398                                        pci_unmap_addr(ri, mapping),
4399                                        skb_shinfo(skb)->frags[i].size,
4400                                        PCI_DMA_TODEVICE);
4401                         sw_idx = NEXT_TX(sw_idx);
4402                 }
4403
4404                 dev_kfree_skb(skb);
4405
4406                 if (unlikely(tx_bug)) {
4407                         tg3_tx_recover(tp);
4408                         return;
4409                 }
4410         }
4411
4412         tnapi->tx_cons = sw_idx;
4413
4414         /* Need to make the tx_cons update visible to tg3_start_xmit()
4415          * before checking for netif_queue_stopped().  Without the
4416          * memory barrier, there is a small possibility that tg3_start_xmit()
4417          * will miss it and cause the queue to be stopped forever.
4418          */
4419         smp_mb();
4420
4421         if (unlikely(netif_tx_queue_stopped(txq) &&
4422                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4423                 __netif_tx_lock(txq, smp_processor_id());
4424                 if (netif_tx_queue_stopped(txq) &&
4425                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4426                         netif_tx_wake_queue(txq);
4427                 __netif_tx_unlock(txq);
4428         }
4429 }
4430
4431 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4432 {
4433         if (!ri->skb)
4434                 return;
4435
4436         pci_unmap_single(tp->pdev, pci_unmap_addr(ri, mapping),
4437                          map_sz, PCI_DMA_FROMDEVICE);
4438         dev_kfree_skb_any(ri->skb);
4439         ri->skb = NULL;
4440 }
4441
4442 /* Returns size of skb allocated or < 0 on error.
4443  *
4444  * We only need to fill in the address because the other members
4445  * of the RX descriptor are invariant, see tg3_init_rings.
4446  *
4447  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4448  * posting buffers we only dirty the first cache line of the RX
4449  * descriptor (containing the address).  Whereas for the RX status
4450  * buffers the cpu only reads the last cacheline of the RX descriptor
4451  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4452  */
4453 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4454                             u32 opaque_key, u32 dest_idx_unmasked)
4455 {
4456         struct tg3_rx_buffer_desc *desc;
4457         struct ring_info *map, *src_map;
4458         struct sk_buff *skb;
4459         dma_addr_t mapping;
4460         int skb_size, dest_idx;
4461
4462         src_map = NULL;
4463         switch (opaque_key) {
4464         case RXD_OPAQUE_RING_STD:
4465                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4466                 desc = &tpr->rx_std[dest_idx];
4467                 map = &tpr->rx_std_buffers[dest_idx];
4468                 skb_size = tp->rx_pkt_map_sz;
4469                 break;
4470
4471         case RXD_OPAQUE_RING_JUMBO:
4472                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4473                 desc = &tpr->rx_jmb[dest_idx].std;
4474                 map = &tpr->rx_jmb_buffers[dest_idx];
4475                 skb_size = TG3_RX_JMB_MAP_SZ;
4476                 break;
4477
4478         default:
4479                 return -EINVAL;
4480         }
4481
4482         /* Do not overwrite any of the map or rp information
4483          * until we are sure we can commit to a new buffer.
4484          *
4485          * Callers depend upon this behavior and assume that
4486          * we leave everything unchanged if we fail.
4487          */
4488         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4489         if (skb == NULL)
4490                 return -ENOMEM;
4491
4492         skb_reserve(skb, tp->rx_offset);
4493
4494         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4495                                  PCI_DMA_FROMDEVICE);
4496         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4497                 dev_kfree_skb(skb);
4498                 return -EIO;
4499         }
4500
4501         map->skb = skb;
4502         pci_unmap_addr_set(map, mapping, mapping);
4503
4504         desc->addr_hi = ((u64)mapping >> 32);
4505         desc->addr_lo = ((u64)mapping & 0xffffffff);
4506
4507         return skb_size;
4508 }
4509
4510 /* We only need to move over in the address because the other
4511  * members of the RX descriptor are invariant.  See notes above
4512  * tg3_alloc_rx_skb for full details.
4513  */
4514 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4515                            struct tg3_rx_prodring_set *dpr,
4516                            u32 opaque_key, int src_idx,
4517                            u32 dest_idx_unmasked)
4518 {
4519         struct tg3 *tp = tnapi->tp;
4520         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4521         struct ring_info *src_map, *dest_map;
4522         int dest_idx;
4523         struct tg3_rx_prodring_set *spr = &tp->prodring[0];
4524
4525         switch (opaque_key) {
4526         case RXD_OPAQUE_RING_STD:
4527                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4528                 dest_desc = &dpr->rx_std[dest_idx];
4529                 dest_map = &dpr->rx_std_buffers[dest_idx];
4530                 src_desc = &spr->rx_std[src_idx];
4531                 src_map = &spr->rx_std_buffers[src_idx];
4532                 break;
4533
4534         case RXD_OPAQUE_RING_JUMBO:
4535                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4536                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4537                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4538                 src_desc = &spr->rx_jmb[src_idx].std;
4539                 src_map = &spr->rx_jmb_buffers[src_idx];
4540                 break;
4541
4542         default:
4543                 return;
4544         }
4545
4546         dest_map->skb = src_map->skb;
4547         pci_unmap_addr_set(dest_map, mapping,
4548                            pci_unmap_addr(src_map, mapping));
4549         dest_desc->addr_hi = src_desc->addr_hi;
4550         dest_desc->addr_lo = src_desc->addr_lo;
4551
4552         /* Ensure that the update to the skb happens after the physical
4553          * addresses have been transferred to the new BD location.
4554          */
4555         smp_wmb();
4556
4557         src_map->skb = NULL;
4558 }
4559
4560 /* The RX ring scheme is composed of multiple rings which post fresh
4561  * buffers to the chip, and one special ring the chip uses to report
4562  * status back to the host.
4563  *
4564  * The special ring reports the status of received packets to the
4565  * host.  The chip does not write into the original descriptor the
4566  * RX buffer was obtained from.  The chip simply takes the original
4567  * descriptor as provided by the host, updates the status and length
4568  * field, then writes this into the next status ring entry.
4569  *
4570  * Each ring the host uses to post buffers to the chip is described
4571  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4572  * it is first placed into the on-chip ram.  When the packet's length
4573  * is known, it walks down the TG3_BDINFO entries to select the ring.
4574  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4575  * which is within the range of the new packet's length is chosen.
4576  *
4577  * The "separate ring for rx status" scheme may sound queer, but it makes
4578  * sense from a cache coherency perspective.  If only the host writes
4579  * to the buffer post rings, and only the chip writes to the rx status
4580  * rings, then cache lines never move beyond shared-modified state.
4581  * If both the host and chip were to write into the same ring, cache line
4582  * eviction could occur since both entities want it in an exclusive state.
4583  */
4584 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4585 {
4586         struct tg3 *tp = tnapi->tp;
4587         u32 work_mask, rx_std_posted = 0;
4588         u32 std_prod_idx, jmb_prod_idx;
4589         u32 sw_idx = tnapi->rx_rcb_ptr;
4590         u16 hw_idx;
4591         int received;
4592         struct tg3_rx_prodring_set *tpr = tnapi->prodring;
4593
4594         hw_idx = *(tnapi->rx_rcb_prod_idx);
4595         /*
4596          * We need to order the read of hw_idx and the read of
4597          * the opaque cookie.
4598          */
4599         rmb();
4600         work_mask = 0;
4601         received = 0;
4602         std_prod_idx = tpr->rx_std_prod_idx;
4603         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4604         while (sw_idx != hw_idx && budget > 0) {
4605                 struct ring_info *ri;
4606                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4607                 unsigned int len;
4608                 struct sk_buff *skb;
4609                 dma_addr_t dma_addr;
4610                 u32 opaque_key, desc_idx, *post_ptr;
4611
4612                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4613                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4614                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4615                         ri = &tp->prodring[0].rx_std_buffers[desc_idx];
4616                         dma_addr = pci_unmap_addr(ri, mapping);
4617                         skb = ri->skb;
4618                         post_ptr = &std_prod_idx;
4619                         rx_std_posted++;
4620                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4621                         ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
4622                         dma_addr = pci_unmap_addr(ri, mapping);
4623                         skb = ri->skb;
4624                         post_ptr = &jmb_prod_idx;
4625                 } else
4626                         goto next_pkt_nopost;
4627
4628                 work_mask |= opaque_key;
4629
4630                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4631                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4632                 drop_it:
4633                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4634                                        desc_idx, *post_ptr);
4635                 drop_it_no_recycle:
4636                         /* Other statistics kept track of by card. */
4637                         tp->net_stats.rx_dropped++;
4638                         goto next_pkt;
4639                 }
4640
4641                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4642                       ETH_FCS_LEN;
4643
4644                 if (len > RX_COPY_THRESHOLD &&
4645                     tp->rx_offset == NET_IP_ALIGN) {
4646                     /* rx_offset will likely not equal NET_IP_ALIGN
4647                      * if this is a 5701 card running in PCI-X mode
4648                      * [see tg3_get_invariants()]
4649                      */
4650                         int skb_size;
4651
4652                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4653                                                     *post_ptr);
4654                         if (skb_size < 0)
4655                                 goto drop_it;
4656
4657                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4658                                          PCI_DMA_FROMDEVICE);
4659
4660                         /* Ensure that the update to the skb happens
4661                          * after the usage of the old DMA mapping.
4662                          */
4663                         smp_wmb();
4664
4665                         ri->skb = NULL;
4666
4667                         skb_put(skb, len);
4668                 } else {
4669                         struct sk_buff *copy_skb;
4670
4671                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4672                                        desc_idx, *post_ptr);
4673
4674                         copy_skb = netdev_alloc_skb(tp->dev,
4675                                                     len + TG3_RAW_IP_ALIGN);
4676                         if (copy_skb == NULL)
4677                                 goto drop_it_no_recycle;
4678
4679                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4680                         skb_put(copy_skb, len);
4681                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4682                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4683                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4684
4685                         /* We'll reuse the original ring buffer. */
4686                         skb = copy_skb;
4687                 }
4688
4689                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4690                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4691                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4692                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4693                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4694                 else
4695                         skb->ip_summed = CHECKSUM_NONE;
4696
4697                 skb->protocol = eth_type_trans(skb, tp->dev);
4698
4699                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4700                     skb->protocol != htons(ETH_P_8021Q)) {
4701                         dev_kfree_skb(skb);
4702                         goto next_pkt;
4703                 }
4704
4705 #if TG3_VLAN_TAG_USED
4706                 if (tp->vlgrp != NULL &&
4707                     desc->type_flags & RXD_FLAG_VLAN) {
4708                         vlan_gro_receive(&tnapi->napi, tp->vlgrp,
4709                                          desc->err_vlan & RXD_VLAN_MASK, skb);
4710                 } else
4711 #endif
4712                         napi_gro_receive(&tnapi->napi, skb);
4713
4714                 received++;
4715                 budget--;
4716
4717 next_pkt:
4718                 (*post_ptr)++;
4719
4720                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4721                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4722                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4723                                      tpr->rx_std_prod_idx);
4724                         work_mask &= ~RXD_OPAQUE_RING_STD;
4725                         rx_std_posted = 0;
4726                 }
4727 next_pkt_nopost:
4728                 sw_idx++;
4729                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4730
4731                 /* Refresh hw_idx to see if there is new work */
4732                 if (sw_idx == hw_idx) {
4733                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4734                         rmb();
4735                 }
4736         }
4737
4738         /* ACK the status ring. */
4739         tnapi->rx_rcb_ptr = sw_idx;
4740         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4741
4742         /* Refill RX ring(s). */
4743         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4744                 if (work_mask & RXD_OPAQUE_RING_STD) {
4745                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4746                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4747                                      tpr->rx_std_prod_idx);
4748                 }
4749                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4750                         tpr->rx_jmb_prod_idx = jmb_prod_idx %
4751                                                TG3_RX_JUMBO_RING_SIZE;
4752                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4753                                      tpr->rx_jmb_prod_idx);
4754                 }
4755                 mmiowb();
4756         } else if (work_mask) {
4757                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4758                  * updated before the producer indices can be updated.
4759                  */
4760                 smp_wmb();
4761
4762                 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4763                 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
4764
4765                 if (tnapi != &tp->napi[1])
4766                         napi_schedule(&tp->napi[1].napi);
4767         }
4768
4769         return received;
4770 }
4771
4772 static void tg3_poll_link(struct tg3 *tp)
4773 {
4774         /* handle link change and other phy events */
4775         if (!(tp->tg3_flags &
4776               (TG3_FLAG_USE_LINKCHG_REG |
4777                TG3_FLAG_POLL_SERDES))) {
4778                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4779
4780                 if (sblk->status & SD_STATUS_LINK_CHG) {
4781                         sblk->status = SD_STATUS_UPDATED |
4782                                        (sblk->status & ~SD_STATUS_LINK_CHG);
4783                         spin_lock(&tp->lock);
4784                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4785                                 tw32_f(MAC_STATUS,
4786                                      (MAC_STATUS_SYNC_CHANGED |
4787                                       MAC_STATUS_CFG_CHANGED |
4788                                       MAC_STATUS_MI_COMPLETION |
4789                                       MAC_STATUS_LNKSTATE_CHANGED));
4790                                 udelay(40);
4791                         } else
4792                                 tg3_setup_phy(tp, 0);
4793                         spin_unlock(&tp->lock);
4794                 }
4795         }
4796 }
4797
4798 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4799                                 struct tg3_rx_prodring_set *dpr,
4800                                 struct tg3_rx_prodring_set *spr)
4801 {
4802         u32 si, di, cpycnt, src_prod_idx;
4803         int i, err = 0;
4804
4805         while (1) {
4806                 src_prod_idx = spr->rx_std_prod_idx;
4807
4808                 /* Make sure updates to the rx_std_buffers[] entries and the
4809                  * standard producer index are seen in the correct order.
4810                  */
4811                 smp_rmb();
4812
4813                 if (spr->rx_std_cons_idx == src_prod_idx)
4814                         break;
4815
4816                 if (spr->rx_std_cons_idx < src_prod_idx)
4817                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4818                 else
4819                         cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4820
4821                 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4822
4823                 si = spr->rx_std_cons_idx;
4824                 di = dpr->rx_std_prod_idx;
4825
4826                 for (i = di; i < di + cpycnt; i++) {
4827                         if (dpr->rx_std_buffers[i].skb) {
4828                                 cpycnt = i - di;
4829                                 err = -ENOSPC;
4830                                 break;
4831                         }
4832                 }
4833
4834                 if (!cpycnt)
4835                         break;
4836
4837                 /* Ensure that updates to the rx_std_buffers ring and the
4838                  * shadowed hardware producer ring from tg3_recycle_skb() are
4839                  * ordered correctly WRT the skb check above.
4840                  */
4841                 smp_rmb();
4842
4843                 memcpy(&dpr->rx_std_buffers[di],
4844                        &spr->rx_std_buffers[si],
4845                        cpycnt * sizeof(struct ring_info));
4846
4847                 for (i = 0; i < cpycnt; i++, di++, si++) {
4848                         struct tg3_rx_buffer_desc *sbd, *dbd;
4849                         sbd = &spr->rx_std[si];
4850                         dbd = &dpr->rx_std[di];
4851                         dbd->addr_hi = sbd->addr_hi;
4852                         dbd->addr_lo = sbd->addr_lo;
4853                 }
4854
4855                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4856                                        TG3_RX_RING_SIZE;
4857                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4858                                        TG3_RX_RING_SIZE;
4859         }
4860
4861         while (1) {
4862                 src_prod_idx = spr->rx_jmb_prod_idx;
4863
4864                 /* Make sure updates to the rx_jmb_buffers[] entries and
4865                  * the jumbo producer index are seen in the correct order.
4866                  */
4867                 smp_rmb();
4868
4869                 if (spr->rx_jmb_cons_idx == src_prod_idx)
4870                         break;
4871
4872                 if (spr->rx_jmb_cons_idx < src_prod_idx)
4873                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4874                 else
4875                         cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4876
4877                 cpycnt = min(cpycnt,
4878                              TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4879
4880                 si = spr->rx_jmb_cons_idx;
4881                 di = dpr->rx_jmb_prod_idx;
4882
4883                 for (i = di; i < di + cpycnt; i++) {
4884                         if (dpr->rx_jmb_buffers[i].skb) {
4885                                 cpycnt = i - di;
4886                                 err = -ENOSPC;
4887                                 break;
4888                         }
4889                 }
4890
4891                 if (!cpycnt)
4892                         break;
4893
4894                 /* Ensure that updates to the rx_jmb_buffers ring and the
4895                  * shadowed hardware producer ring from tg3_recycle_skb() are
4896                  * ordered correctly WRT the skb check above.
4897                  */
4898                 smp_rmb();
4899
4900                 memcpy(&dpr->rx_jmb_buffers[di],
4901                        &spr->rx_jmb_buffers[si],
4902                        cpycnt * sizeof(struct ring_info));
4903
4904                 for (i = 0; i < cpycnt; i++, di++, si++) {
4905                         struct tg3_rx_buffer_desc *sbd, *dbd;
4906                         sbd = &spr->rx_jmb[si].std;
4907                         dbd = &dpr->rx_jmb[di].std;
4908                         dbd->addr_hi = sbd->addr_hi;
4909                         dbd->addr_lo = sbd->addr_lo;
4910                 }
4911
4912                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4913                                        TG3_RX_JUMBO_RING_SIZE;
4914                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4915                                        TG3_RX_JUMBO_RING_SIZE;
4916         }
4917
4918         return err;
4919 }
4920
4921 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4922 {
4923         struct tg3 *tp = tnapi->tp;
4924
4925         /* run TX completion thread */
4926         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4927                 tg3_tx(tnapi);
4928                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4929                         return work_done;
4930         }
4931
4932         /* run RX thread, within the bounds set by NAPI.
4933          * All RX "locking" is done by ensuring outside
4934          * code synchronizes with tg3->napi.poll()
4935          */
4936         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4937                 work_done += tg3_rx(tnapi, budget - work_done);
4938
4939         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4940                 struct tg3_rx_prodring_set *dpr = &tp->prodring[0];
4941                 int i, err = 0;
4942                 u32 std_prod_idx = dpr->rx_std_prod_idx;
4943                 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
4944
4945                 for (i = 1; i < tp->irq_cnt; i++)
4946                         err |= tg3_rx_prodring_xfer(tp, dpr,
4947                                                     tp->napi[i].prodring);
4948
4949                 wmb();
4950
4951                 if (std_prod_idx != dpr->rx_std_prod_idx)
4952                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4953                                      dpr->rx_std_prod_idx);
4954
4955                 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
4956                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4957                                      dpr->rx_jmb_prod_idx);
4958
4959                 mmiowb();
4960
4961                 if (err)
4962                         tw32_f(HOSTCC_MODE, tp->coal_now);
4963         }
4964
4965         return work_done;
4966 }
4967
4968 static int tg3_poll_msix(struct napi_struct *napi, int budget)
4969 {
4970         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4971         struct tg3 *tp = tnapi->tp;
4972         int work_done = 0;
4973         struct tg3_hw_status *sblk = tnapi->hw_status;
4974
4975         while (1) {
4976                 work_done = tg3_poll_work(tnapi, work_done, budget);
4977
4978                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4979                         goto tx_recovery;
4980
4981                 if (unlikely(work_done >= budget))
4982                         break;
4983
4984                 /* tp->last_tag is used in tg3_restart_ints() below
4985                  * to tell the hw how much work has been processed,
4986                  * so we must read it before checking for more work.
4987                  */
4988                 tnapi->last_tag = sblk->status_tag;
4989                 tnapi->last_irq_tag = tnapi->last_tag;
4990                 rmb();
4991
4992                 /* check for RX/TX work to do */
4993                 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
4994                            *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
4995                         napi_complete(napi);
4996                         /* Reenable interrupts. */
4997                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
4998                         mmiowb();
4999                         break;
5000                 }
5001         }
5002
5003         return work_done;
5004
5005 tx_recovery:
5006         /* work_done is guaranteed to be less than budget. */
5007         napi_complete(napi);
5008         schedule_work(&tp->reset_task);
5009         return work_done;
5010 }
5011
5012 static int tg3_poll(struct napi_struct *napi, int budget)
5013 {
5014         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5015         struct tg3 *tp = tnapi->tp;
5016         int work_done = 0;
5017         struct tg3_hw_status *sblk = tnapi->hw_status;
5018
5019         while (1) {
5020                 tg3_poll_link(tp);
5021
5022                 work_done = tg3_poll_work(tnapi, work_done, budget);
5023
5024                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5025                         goto tx_recovery;
5026
5027                 if (unlikely(work_done >= budget))
5028                         break;
5029
5030                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5031                         /* tp->last_tag is used in tg3_int_reenable() below
5032                          * to tell the hw how much work has been processed,
5033                          * so we must read it before checking for more work.
5034                          */
5035                         tnapi->last_tag = sblk->status_tag;
5036                         tnapi->last_irq_tag = tnapi->last_tag;
5037                         rmb();
5038                 } else
5039                         sblk->status &= ~SD_STATUS_UPDATED;
5040
5041                 if (likely(!tg3_has_work(tnapi))) {
5042                         napi_complete(napi);
5043                         tg3_int_reenable(tnapi);
5044                         break;
5045                 }
5046         }
5047
5048         return work_done;
5049
5050 tx_recovery:
5051         /* work_done is guaranteed to be less than budget. */
5052         napi_complete(napi);
5053         schedule_work(&tp->reset_task);
5054         return work_done;
5055 }
5056
5057 static void tg3_irq_quiesce(struct tg3 *tp)
5058 {
5059         int i;
5060
5061         BUG_ON(tp->irq_sync);
5062
5063         tp->irq_sync = 1;
5064         smp_mb();
5065
5066         for (i = 0; i < tp->irq_cnt; i++)
5067                 synchronize_irq(tp->napi[i].irq_vec);
5068 }
5069
5070 static inline int tg3_irq_sync(struct tg3 *tp)
5071 {
5072         return tp->irq_sync;
5073 }
5074
5075 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5076  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5077  * with as well.  Most of the time, this is not necessary except when
5078  * shutting down the device.
5079  */
5080 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5081 {
5082         spin_lock_bh(&tp->lock);
5083         if (irq_sync)
5084                 tg3_irq_quiesce(tp);
5085 }
5086
5087 static inline void tg3_full_unlock(struct tg3 *tp)
5088 {
5089         spin_unlock_bh(&tp->lock);
5090 }
5091
5092 /* One-shot MSI handler - Chip automatically disables interrupt
5093  * after sending MSI so driver doesn't have to do it.
5094  */
5095 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5096 {
5097         struct tg3_napi *tnapi = dev_id;
5098         struct tg3 *tp = tnapi->tp;
5099
5100         prefetch(tnapi->hw_status);
5101         if (tnapi->rx_rcb)
5102                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5103
5104         if (likely(!tg3_irq_sync(tp)))
5105                 napi_schedule(&tnapi->napi);
5106
5107         return IRQ_HANDLED;
5108 }
5109
5110 /* MSI ISR - No need to check for interrupt sharing and no need to
5111  * flush status block and interrupt mailbox. PCI ordering rules
5112  * guarantee that MSI will arrive after the status block.
5113  */
5114 static irqreturn_t tg3_msi(int irq, void *dev_id)
5115 {
5116         struct tg3_napi *tnapi = dev_id;
5117         struct tg3 *tp = tnapi->tp;
5118
5119         prefetch(tnapi->hw_status);
5120         if (tnapi->rx_rcb)
5121                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5122         /*
5123          * Writing any value to intr-mbox-0 clears PCI INTA# and
5124          * chip-internal interrupt pending events.
5125          * Writing non-zero to intr-mbox-0 additional tells the
5126          * NIC to stop sending us irqs, engaging "in-intr-handler"
5127          * event coalescing.
5128          */
5129         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5130         if (likely(!tg3_irq_sync(tp)))
5131                 napi_schedule(&tnapi->napi);
5132
5133         return IRQ_RETVAL(1);
5134 }
5135
5136 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5137 {
5138         struct tg3_napi *tnapi = dev_id;
5139         struct tg3 *tp = tnapi->tp;
5140         struct tg3_hw_status *sblk = tnapi->hw_status;
5141         unsigned int handled = 1;
5142
5143         /* In INTx mode, it is possible for the interrupt to arrive at
5144          * the CPU before the status block posted prior to the interrupt.
5145          * Reading the PCI State register will confirm whether the
5146          * interrupt is ours and will flush the status block.
5147          */
5148         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5149                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5150                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5151                         handled = 0;
5152                         goto out;
5153                 }
5154         }
5155
5156         /*
5157          * Writing any value to intr-mbox-0 clears PCI INTA# and
5158          * chip-internal interrupt pending events.
5159          * Writing non-zero to intr-mbox-0 additional tells the
5160          * NIC to stop sending us irqs, engaging "in-intr-handler"
5161          * event coalescing.
5162          *
5163          * Flush the mailbox to de-assert the IRQ immediately to prevent
5164          * spurious interrupts.  The flush impacts performance but
5165          * excessive spurious interrupts can be worse in some cases.
5166          */
5167         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5168         if (tg3_irq_sync(tp))
5169                 goto out;
5170         sblk->status &= ~SD_STATUS_UPDATED;
5171         if (likely(tg3_has_work(tnapi))) {
5172                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5173                 napi_schedule(&tnapi->napi);
5174         } else {
5175                 /* No work, shared interrupt perhaps?  re-enable
5176                  * interrupts, and flush that PCI write
5177                  */
5178                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5179                                0x00000000);
5180         }
5181 out:
5182         return IRQ_RETVAL(handled);
5183 }
5184
5185 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5186 {
5187         struct tg3_napi *tnapi = dev_id;
5188         struct tg3 *tp = tnapi->tp;
5189         struct tg3_hw_status *sblk = tnapi->hw_status;
5190         unsigned int handled = 1;
5191
5192         /* In INTx mode, it is possible for the interrupt to arrive at
5193          * the CPU before the status block posted prior to the interrupt.
5194          * Reading the PCI State register will confirm whether the
5195          * interrupt is ours and will flush the status block.
5196          */
5197         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5198                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5199                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5200                         handled = 0;
5201                         goto out;
5202                 }
5203         }
5204
5205         /*
5206          * writing any value to intr-mbox-0 clears PCI INTA# and
5207          * chip-internal interrupt pending events.
5208          * writing non-zero to intr-mbox-0 additional tells the
5209          * NIC to stop sending us irqs, engaging "in-intr-handler"
5210          * event coalescing.
5211          *
5212          * Flush the mailbox to de-assert the IRQ immediately to prevent
5213          * spurious interrupts.  The flush impacts performance but
5214          * excessive spurious interrupts can be worse in some cases.
5215          */
5216         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5217
5218         /*
5219          * In a shared interrupt configuration, sometimes other devices'
5220          * interrupts will scream.  We record the current status tag here
5221          * so that the above check can report that the screaming interrupts
5222          * are unhandled.  Eventually they will be silenced.
5223          */
5224         tnapi->last_irq_tag = sblk->status_tag;
5225
5226         if (tg3_irq_sync(tp))
5227                 goto out;
5228
5229         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5230
5231         napi_schedule(&tnapi->napi);
5232
5233 out:
5234         return IRQ_RETVAL(handled);
5235 }
5236
5237 /* ISR for interrupt test */
5238 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5239 {
5240         struct tg3_napi *tnapi = dev_id;
5241         struct tg3 *tp = tnapi->tp;
5242         struct tg3_hw_status *sblk = tnapi->hw_status;
5243
5244         if ((sblk->status & SD_STATUS_UPDATED) ||
5245             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5246                 tg3_disable_ints(tp);
5247                 return IRQ_RETVAL(1);
5248         }
5249         return IRQ_RETVAL(0);
5250 }
5251
5252 static int tg3_init_hw(struct tg3 *, int);
5253 static int tg3_halt(struct tg3 *, int, int);
5254
5255 /* Restart hardware after configuration changes, self-test, etc.
5256  * Invoked with tp->lock held.
5257  */
5258 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5259         __releases(tp->lock)
5260         __acquires(tp->lock)
5261 {
5262         int err;
5263
5264         err = tg3_init_hw(tp, reset_phy);
5265         if (err) {
5266                 netdev_err(tp->dev,
5267                            "Failed to re-initialize device, aborting\n");
5268                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5269                 tg3_full_unlock(tp);
5270                 del_timer_sync(&tp->timer);
5271                 tp->irq_sync = 0;
5272                 tg3_napi_enable(tp);
5273                 dev_close(tp->dev);
5274                 tg3_full_lock(tp, 0);
5275         }
5276         return err;
5277 }
5278
5279 #ifdef CONFIG_NET_POLL_CONTROLLER
5280 static void tg3_poll_controller(struct net_device *dev)
5281 {
5282         int i;
5283         struct tg3 *tp = netdev_priv(dev);
5284
5285         for (i = 0; i < tp->irq_cnt; i++)
5286                 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5287 }
5288 #endif
5289
5290 static void tg3_reset_task(struct work_struct *work)
5291 {
5292         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5293         int err;
5294         unsigned int restart_timer;
5295
5296         tg3_full_lock(tp, 0);
5297
5298         if (!netif_running(tp->dev)) {
5299                 tg3_full_unlock(tp);
5300                 return;
5301         }
5302
5303         tg3_full_unlock(tp);
5304
5305         tg3_phy_stop(tp);
5306
5307         tg3_netif_stop(tp);
5308
5309         tg3_full_lock(tp, 1);
5310
5311         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5312         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5313
5314         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5315                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5316                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5317                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5318                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5319         }
5320
5321         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5322         err = tg3_init_hw(tp, 1);
5323         if (err)
5324                 goto out;
5325
5326         tg3_netif_start(tp);
5327
5328         if (restart_timer)
5329                 mod_timer(&tp->timer, jiffies + 1);
5330
5331 out:
5332         tg3_full_unlock(tp);
5333
5334         if (!err)
5335                 tg3_phy_start(tp);
5336 }
5337
5338 static void tg3_dump_short_state(struct tg3 *tp)
5339 {
5340         netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5341                    tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5342         netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5343                    tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5344 }
5345
5346 static void tg3_tx_timeout(struct net_device *dev)
5347 {
5348         struct tg3 *tp = netdev_priv(dev);
5349
5350         if (netif_msg_tx_err(tp)) {
5351                 netdev_err(dev, "transmit timed out, resetting\n");
5352                 tg3_dump_short_state(tp);
5353         }
5354
5355         schedule_work(&tp->reset_task);
5356 }
5357
5358 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5359 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5360 {
5361         u32 base = (u32) mapping & 0xffffffff;
5362
5363         return ((base > 0xffffdcc0) &&
5364                 (base + len + 8 < base));
5365 }
5366
5367 /* Test for DMA addresses > 40-bit */
5368 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5369                                           int len)
5370 {
5371 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5372         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5373                 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5374         return 0;
5375 #else
5376         return 0;
5377 #endif
5378 }
5379
5380 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5381
5382 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5383 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5384                                        struct sk_buff *skb, u32 last_plus_one,
5385                                        u32 *start, u32 base_flags, u32 mss)
5386 {
5387         struct tg3 *tp = tnapi->tp;
5388         struct sk_buff *new_skb;
5389         dma_addr_t new_addr = 0;
5390         u32 entry = *start;
5391         int i, ret = 0;
5392
5393         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5394                 new_skb = skb_copy(skb, GFP_ATOMIC);
5395         else {
5396                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5397
5398                 new_skb = skb_copy_expand(skb,
5399                                           skb_headroom(skb) + more_headroom,
5400                                           skb_tailroom(skb), GFP_ATOMIC);
5401         }
5402
5403         if (!new_skb) {
5404                 ret = -1;
5405         } else {
5406                 /* New SKB is guaranteed to be linear. */
5407                 entry = *start;
5408                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5409                                           PCI_DMA_TODEVICE);
5410                 /* Make sure the mapping succeeded */
5411                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5412                         ret = -1;
5413                         dev_kfree_skb(new_skb);
5414                         new_skb = NULL;
5415
5416                 /* Make sure new skb does not cross any 4G boundaries.
5417                  * Drop the packet if it does.
5418                  */
5419                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5420                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5421                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5422                                          PCI_DMA_TODEVICE);
5423                         ret = -1;
5424                         dev_kfree_skb(new_skb);
5425                         new_skb = NULL;
5426                 } else {
5427                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5428                                     base_flags, 1 | (mss << 1));
5429                         *start = NEXT_TX(entry);
5430                 }
5431         }
5432
5433         /* Now clean up the sw ring entries. */
5434         i = 0;
5435         while (entry != last_plus_one) {
5436                 int len;
5437
5438                 if (i == 0)
5439                         len = skb_headlen(skb);
5440                 else
5441                         len = skb_shinfo(skb)->frags[i-1].size;
5442
5443                 pci_unmap_single(tp->pdev,
5444                                  pci_unmap_addr(&tnapi->tx_buffers[entry],
5445                                                 mapping),
5446                                  len, PCI_DMA_TODEVICE);
5447                 if (i == 0) {
5448                         tnapi->tx_buffers[entry].skb = new_skb;
5449                         pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5450                                            new_addr);
5451                 } else {
5452                         tnapi->tx_buffers[entry].skb = NULL;
5453                 }
5454                 entry = NEXT_TX(entry);
5455                 i++;
5456         }
5457
5458         dev_kfree_skb(skb);
5459
5460         return ret;
5461 }
5462
5463 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5464                         dma_addr_t mapping, int len, u32 flags,
5465                         u32 mss_and_is_end)
5466 {
5467         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5468         int is_end = (mss_and_is_end & 0x1);
5469         u32 mss = (mss_and_is_end >> 1);
5470         u32 vlan_tag = 0;
5471
5472         if (is_end)
5473                 flags |= TXD_FLAG_END;
5474         if (flags & TXD_FLAG_VLAN) {
5475                 vlan_tag = flags >> 16;
5476                 flags &= 0xffff;
5477         }
5478         vlan_tag |= (mss << TXD_MSS_SHIFT);
5479
5480         txd->addr_hi = ((u64) mapping >> 32);
5481         txd->addr_lo = ((u64) mapping & 0xffffffff);
5482         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5483         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5484 }
5485
5486 /* hard_start_xmit for devices that don't have any bugs and
5487  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5488  */
5489 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5490                                   struct net_device *dev)
5491 {
5492         struct tg3 *tp = netdev_priv(dev);
5493         u32 len, entry, base_flags, mss;
5494         dma_addr_t mapping;
5495         struct tg3_napi *tnapi;
5496         struct netdev_queue *txq;
5497         unsigned int i, last;
5498
5499
5500         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5501         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5502         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5503                 tnapi++;
5504
5505         /* We are running in BH disabled context with netif_tx_lock
5506          * and TX reclaim runs via tp->napi.poll inside of a software
5507          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5508          * no IRQ context deadlocks to worry about either.  Rejoice!
5509          */
5510         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5511                 if (!netif_tx_queue_stopped(txq)) {
5512                         netif_tx_stop_queue(txq);
5513
5514                         /* This is a hard error, log it. */
5515                         netdev_err(dev,
5516                                    "BUG! Tx Ring full when queue awake!\n");
5517                 }
5518                 return NETDEV_TX_BUSY;
5519         }
5520
5521         entry = tnapi->tx_prod;
5522         base_flags = 0;
5523         mss = 0;
5524         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5525                 int tcp_opt_len, ip_tcp_len;
5526                 u32 hdrlen;
5527
5528                 if (skb_header_cloned(skb) &&
5529                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5530                         dev_kfree_skb(skb);
5531                         goto out_unlock;
5532                 }
5533
5534                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5535                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5536                 else {
5537                         struct iphdr *iph = ip_hdr(skb);
5538
5539                         tcp_opt_len = tcp_optlen(skb);
5540                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5541
5542                         iph->check = 0;
5543                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5544                         hdrlen = ip_tcp_len + tcp_opt_len;
5545                 }
5546
5547                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5548                         mss |= (hdrlen & 0xc) << 12;
5549                         if (hdrlen & 0x10)
5550                                 base_flags |= 0x00000010;
5551                         base_flags |= (hdrlen & 0x3e0) << 5;
5552                 } else
5553                         mss |= hdrlen << 9;
5554
5555                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5556                                TXD_FLAG_CPU_POST_DMA);
5557
5558                 tcp_hdr(skb)->check = 0;
5559
5560         }
5561         else if (skb->ip_summed == CHECKSUM_PARTIAL)
5562                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5563 #if TG3_VLAN_TAG_USED
5564         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5565                 base_flags |= (TXD_FLAG_VLAN |
5566                                (vlan_tx_tag_get(skb) << 16));
5567 #endif
5568
5569         len = skb_headlen(skb);
5570
5571         /* Queue skb data, a.k.a. the main skb fragment. */
5572         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5573         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5574                 dev_kfree_skb(skb);
5575                 goto out_unlock;
5576         }
5577
5578         tnapi->tx_buffers[entry].skb = skb;
5579         pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5580
5581         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5582             !mss && skb->len > ETH_DATA_LEN)
5583                 base_flags |= TXD_FLAG_JMB_PKT;
5584
5585         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5586                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5587
5588         entry = NEXT_TX(entry);
5589
5590         /* Now loop through additional data fragments, and queue them. */
5591         if (skb_shinfo(skb)->nr_frags > 0) {
5592                 last = skb_shinfo(skb)->nr_frags - 1;
5593                 for (i = 0; i <= last; i++) {
5594                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5595
5596                         len = frag->size;
5597                         mapping = pci_map_page(tp->pdev,
5598                                                frag->page,
5599                                                frag->page_offset,
5600                                                len, PCI_DMA_TODEVICE);
5601                         if (pci_dma_mapping_error(tp->pdev, mapping))
5602                                 goto dma_error;
5603
5604                         tnapi->tx_buffers[entry].skb = NULL;
5605                         pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5606                                            mapping);
5607
5608                         tg3_set_txd(tnapi, entry, mapping, len,
5609                                     base_flags, (i == last) | (mss << 1));
5610
5611                         entry = NEXT_TX(entry);
5612                 }
5613         }
5614
5615         /* Packets are ready, update Tx producer idx local and on card. */
5616         tw32_tx_mbox(tnapi->prodmbox, entry);
5617
5618         tnapi->tx_prod = entry;
5619         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5620                 netif_tx_stop_queue(txq);
5621                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5622                         netif_tx_wake_queue(txq);
5623         }
5624
5625 out_unlock:
5626         mmiowb();
5627
5628         return NETDEV_TX_OK;
5629
5630 dma_error:
5631         last = i;
5632         entry = tnapi->tx_prod;
5633         tnapi->tx_buffers[entry].skb = NULL;
5634         pci_unmap_single(tp->pdev,
5635                          pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5636                          skb_headlen(skb),
5637                          PCI_DMA_TODEVICE);
5638         for (i = 0; i <= last; i++) {
5639                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5640                 entry = NEXT_TX(entry);
5641
5642                 pci_unmap_page(tp->pdev,
5643                                pci_unmap_addr(&tnapi->tx_buffers[entry],
5644                                               mapping),
5645                                frag->size, PCI_DMA_TODEVICE);
5646         }
5647
5648         dev_kfree_skb(skb);
5649         return NETDEV_TX_OK;
5650 }
5651
5652 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5653                                           struct net_device *);
5654
5655 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5656  * TSO header is greater than 80 bytes.
5657  */
5658 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5659 {
5660         struct sk_buff *segs, *nskb;
5661         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5662
5663         /* Estimate the number of fragments in the worst case */
5664         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5665                 netif_stop_queue(tp->dev);
5666                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5667                         return NETDEV_TX_BUSY;
5668
5669                 netif_wake_queue(tp->dev);
5670         }
5671
5672         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5673         if (IS_ERR(segs))
5674                 goto tg3_tso_bug_end;
5675
5676         do {
5677                 nskb = segs;
5678                 segs = segs->next;
5679                 nskb->next = NULL;
5680                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5681         } while (segs);
5682
5683 tg3_tso_bug_end:
5684         dev_kfree_skb(skb);
5685
5686         return NETDEV_TX_OK;
5687 }
5688
5689 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5690  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5691  */
5692 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5693                                           struct net_device *dev)
5694 {
5695         struct tg3 *tp = netdev_priv(dev);
5696         u32 len, entry, base_flags, mss;
5697         int would_hit_hwbug;
5698         dma_addr_t mapping;
5699         struct tg3_napi *tnapi;
5700         struct netdev_queue *txq;
5701         unsigned int i, last;
5702
5703
5704         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5705         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5706         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5707                 tnapi++;
5708
5709         /* We are running in BH disabled context with netif_tx_lock
5710          * and TX reclaim runs via tp->napi.poll inside of a software
5711          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5712          * no IRQ context deadlocks to worry about either.  Rejoice!
5713          */
5714         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5715                 if (!netif_tx_queue_stopped(txq)) {
5716                         netif_tx_stop_queue(txq);
5717
5718                         /* This is a hard error, log it. */
5719                         netdev_err(dev,
5720                                    "BUG! Tx Ring full when queue awake!\n");
5721                 }
5722                 return NETDEV_TX_BUSY;
5723         }
5724
5725         entry = tnapi->tx_prod;
5726         base_flags = 0;
5727         if (skb->ip_summed == CHECKSUM_PARTIAL)
5728                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5729
5730         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5731                 struct iphdr *iph;
5732                 u32 tcp_opt_len, ip_tcp_len, hdr_len;
5733
5734                 if (skb_header_cloned(skb) &&
5735                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5736                         dev_kfree_skb(skb);
5737                         goto out_unlock;
5738                 }
5739
5740                 tcp_opt_len = tcp_optlen(skb);
5741                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5742
5743                 hdr_len = ip_tcp_len + tcp_opt_len;
5744                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5745                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5746                         return (tg3_tso_bug(tp, skb));
5747
5748                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5749                                TXD_FLAG_CPU_POST_DMA);
5750
5751                 iph = ip_hdr(skb);
5752                 iph->check = 0;
5753                 iph->tot_len = htons(mss + hdr_len);
5754                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5755                         tcp_hdr(skb)->check = 0;
5756                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5757                 } else
5758                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5759                                                                  iph->daddr, 0,
5760                                                                  IPPROTO_TCP,
5761                                                                  0);
5762
5763                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5764                         mss |= (hdr_len & 0xc) << 12;
5765                         if (hdr_len & 0x10)
5766                                 base_flags |= 0x00000010;
5767                         base_flags |= (hdr_len & 0x3e0) << 5;
5768                 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5769                         mss |= hdr_len << 9;
5770                 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5771                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5772                         if (tcp_opt_len || iph->ihl > 5) {
5773                                 int tsflags;
5774
5775                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5776                                 mss |= (tsflags << 11);
5777                         }
5778                 } else {
5779                         if (tcp_opt_len || iph->ihl > 5) {
5780                                 int tsflags;
5781
5782                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5783                                 base_flags |= tsflags << 12;
5784                         }
5785                 }
5786         }
5787 #if TG3_VLAN_TAG_USED
5788         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5789                 base_flags |= (TXD_FLAG_VLAN |
5790                                (vlan_tx_tag_get(skb) << 16));
5791 #endif
5792
5793         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5794             !mss && skb->len > ETH_DATA_LEN)
5795                 base_flags |= TXD_FLAG_JMB_PKT;
5796
5797         len = skb_headlen(skb);
5798
5799         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5800         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5801                 dev_kfree_skb(skb);
5802                 goto out_unlock;
5803         }
5804
5805         tnapi->tx_buffers[entry].skb = skb;
5806         pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5807
5808         would_hit_hwbug = 0;
5809
5810         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5811                 would_hit_hwbug = 1;
5812
5813         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5814             tg3_4g_overflow_test(mapping, len))
5815                 would_hit_hwbug = 1;
5816
5817         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5818             tg3_40bit_overflow_test(tp, mapping, len))
5819                 would_hit_hwbug = 1;
5820
5821         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5822                 would_hit_hwbug = 1;
5823
5824         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5825                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5826
5827         entry = NEXT_TX(entry);
5828
5829         /* Now loop through additional data fragments, and queue them. */
5830         if (skb_shinfo(skb)->nr_frags > 0) {
5831                 last = skb_shinfo(skb)->nr_frags - 1;
5832                 for (i = 0; i <= last; i++) {
5833                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5834
5835                         len = frag->size;
5836                         mapping = pci_map_page(tp->pdev,
5837                                                frag->page,
5838                                                frag->page_offset,
5839                                                len, PCI_DMA_TODEVICE);
5840
5841                         tnapi->tx_buffers[entry].skb = NULL;
5842                         pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5843                                            mapping);
5844                         if (pci_dma_mapping_error(tp->pdev, mapping))
5845                                 goto dma_error;
5846
5847                         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5848                             len <= 8)
5849                                 would_hit_hwbug = 1;
5850
5851                         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5852                             tg3_4g_overflow_test(mapping, len))
5853                                 would_hit_hwbug = 1;
5854
5855                         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5856                             tg3_40bit_overflow_test(tp, mapping, len))
5857                                 would_hit_hwbug = 1;
5858
5859                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5860                                 tg3_set_txd(tnapi, entry, mapping, len,
5861                                             base_flags, (i == last)|(mss << 1));
5862                         else
5863                                 tg3_set_txd(tnapi, entry, mapping, len,
5864                                             base_flags, (i == last));
5865
5866                         entry = NEXT_TX(entry);
5867                 }
5868         }
5869
5870         if (would_hit_hwbug) {
5871                 u32 last_plus_one = entry;
5872                 u32 start;
5873
5874                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5875                 start &= (TG3_TX_RING_SIZE - 1);
5876
5877                 /* If the workaround fails due to memory/mapping
5878                  * failure, silently drop this packet.
5879                  */
5880                 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
5881                                                 &start, base_flags, mss))
5882                         goto out_unlock;
5883
5884                 entry = start;
5885         }
5886
5887         /* Packets are ready, update Tx producer idx local and on card. */
5888         tw32_tx_mbox(tnapi->prodmbox, entry);
5889
5890         tnapi->tx_prod = entry;
5891         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5892                 netif_tx_stop_queue(txq);
5893                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5894                         netif_tx_wake_queue(txq);
5895         }
5896
5897 out_unlock:
5898         mmiowb();
5899
5900         return NETDEV_TX_OK;
5901
5902 dma_error:
5903         last = i;
5904         entry = tnapi->tx_prod;
5905         tnapi->tx_buffers[entry].skb = NULL;
5906         pci_unmap_single(tp->pdev,
5907                          pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5908                          skb_headlen(skb),
5909                          PCI_DMA_TODEVICE);
5910         for (i = 0; i <= last; i++) {
5911                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5912                 entry = NEXT_TX(entry);
5913
5914                 pci_unmap_page(tp->pdev,
5915                                pci_unmap_addr(&tnapi->tx_buffers[entry],
5916                                               mapping),
5917                                frag->size, PCI_DMA_TODEVICE);
5918         }
5919
5920         dev_kfree_skb(skb);
5921         return NETDEV_TX_OK;
5922 }
5923
5924 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5925                                int new_mtu)
5926 {
5927         dev->mtu = new_mtu;
5928
5929         if (new_mtu > ETH_DATA_LEN) {
5930                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5931                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5932                         ethtool_op_set_tso(dev, 0);
5933                 }
5934                 else
5935                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5936         } else {
5937                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5938                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5939                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5940         }
5941 }
5942
5943 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5944 {
5945         struct tg3 *tp = netdev_priv(dev);
5946         int err;
5947
5948         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5949                 return -EINVAL;
5950
5951         if (!netif_running(dev)) {
5952                 /* We'll just catch it later when the
5953                  * device is up'd.
5954                  */
5955                 tg3_set_mtu(dev, tp, new_mtu);
5956                 return 0;
5957         }
5958
5959         tg3_phy_stop(tp);
5960
5961         tg3_netif_stop(tp);
5962
5963         tg3_full_lock(tp, 1);
5964
5965         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5966
5967         tg3_set_mtu(dev, tp, new_mtu);
5968
5969         err = tg3_restart_hw(tp, 0);
5970
5971         if (!err)
5972                 tg3_netif_start(tp);
5973
5974         tg3_full_unlock(tp);
5975
5976         if (!err)
5977                 tg3_phy_start(tp);
5978
5979         return err;
5980 }
5981
5982 static void tg3_rx_prodring_free(struct tg3 *tp,
5983                                  struct tg3_rx_prodring_set *tpr)
5984 {
5985         int i;
5986
5987         if (tpr != &tp->prodring[0]) {
5988                 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
5989                      i = (i + 1) % TG3_RX_RING_SIZE)
5990                         tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
5991                                         tp->rx_pkt_map_sz);
5992
5993                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5994                         for (i = tpr->rx_jmb_cons_idx;
5995                              i != tpr->rx_jmb_prod_idx;
5996                              i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
5997                                 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
5998                                                 TG3_RX_JMB_MAP_SZ);
5999                         }
6000                 }
6001
6002                 return;
6003         }
6004
6005         for (i = 0; i < TG3_RX_RING_SIZE; i++)
6006                 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6007                                 tp->rx_pkt_map_sz);
6008
6009         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6010                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
6011                         tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6012                                         TG3_RX_JMB_MAP_SZ);
6013         }
6014 }
6015
6016 /* Initialize tx/rx rings for packet processing.
6017  *
6018  * The chip has been shut down and the driver detached from
6019  * the networking, so no interrupts or new tx packets will
6020  * end up in the driver.  tp->{tx,}lock are held and thus
6021  * we may not sleep.
6022  */
6023 static int tg3_rx_prodring_alloc(struct tg3 *tp,
6024                                  struct tg3_rx_prodring_set *tpr)
6025 {
6026         u32 i, rx_pkt_dma_sz;
6027
6028         tpr->rx_std_cons_idx = 0;
6029         tpr->rx_std_prod_idx = 0;
6030         tpr->rx_jmb_cons_idx = 0;
6031         tpr->rx_jmb_prod_idx = 0;
6032
6033         if (tpr != &tp->prodring[0]) {
6034                 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
6035                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
6036                         memset(&tpr->rx_jmb_buffers[0], 0,
6037                                TG3_RX_JMB_BUFF_RING_SIZE);
6038                 goto done;
6039         }
6040
6041         /* Zero out all descriptors. */
6042         memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
6043
6044         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6045         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
6046             tp->dev->mtu > ETH_DATA_LEN)
6047                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6048         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6049
6050         /* Initialize invariants of the rings, we only set this
6051          * stuff once.  This works because the card does not
6052          * write into the rx buffer posting rings.
6053          */
6054         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
6055                 struct tg3_rx_buffer_desc *rxd;
6056
6057                 rxd = &tpr->rx_std[i];
6058                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6059                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6060                 rxd->opaque = (RXD_OPAQUE_RING_STD |
6061                                (i << RXD_OPAQUE_INDEX_SHIFT));
6062         }
6063
6064         /* Now allocate fresh SKBs for each rx ring. */
6065         for (i = 0; i < tp->rx_pending; i++) {
6066                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6067                         netdev_warn(tp->dev,
6068                                     "Using a smaller RX standard ring. Only "
6069                                     "%d out of %d buffers were allocated "
6070                                     "successfully\n", i, tp->rx_pending);
6071                         if (i == 0)
6072                                 goto initfail;
6073                         tp->rx_pending = i;
6074                         break;
6075                 }
6076         }
6077
6078         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6079                 goto done;
6080
6081         memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
6082
6083         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
6084                 goto done;
6085
6086         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
6087                 struct tg3_rx_buffer_desc *rxd;
6088
6089                 rxd = &tpr->rx_jmb[i].std;
6090                 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6091                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6092                                   RXD_FLAG_JUMBO;
6093                 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6094                        (i << RXD_OPAQUE_INDEX_SHIFT));
6095         }
6096
6097         for (i = 0; i < tp->rx_jumbo_pending; i++) {
6098                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
6099                         netdev_warn(tp->dev,
6100                                     "Using a smaller RX jumbo ring. Only %d "
6101                                     "out of %d buffers were allocated "
6102                                     "successfully\n", i, tp->rx_jumbo_pending);
6103                         if (i == 0)
6104                                 goto initfail;
6105                         tp->rx_jumbo_pending = i;
6106                         break;
6107                 }
6108         }
6109
6110 done:
6111         return 0;
6112
6113 initfail:
6114         tg3_rx_prodring_free(tp, tpr);
6115         return -ENOMEM;
6116 }
6117
6118 static void tg3_rx_prodring_fini(struct tg3 *tp,
6119                                  struct tg3_rx_prodring_set *tpr)
6120 {
6121         kfree(tpr->rx_std_buffers);
6122         tpr->rx_std_buffers = NULL;
6123         kfree(tpr->rx_jmb_buffers);
6124         tpr->rx_jmb_buffers = NULL;
6125         if (tpr->rx_std) {
6126                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
6127                                     tpr->rx_std, tpr->rx_std_mapping);
6128                 tpr->rx_std = NULL;
6129         }
6130         if (tpr->rx_jmb) {
6131                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
6132                                     tpr->rx_jmb, tpr->rx_jmb_mapping);
6133                 tpr->rx_jmb = NULL;
6134         }
6135 }
6136
6137 static int tg3_rx_prodring_init(struct tg3 *tp,
6138                                 struct tg3_rx_prodring_set *tpr)
6139 {
6140         tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
6141         if (!tpr->rx_std_buffers)
6142                 return -ENOMEM;
6143
6144         tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6145                                            &tpr->rx_std_mapping);
6146         if (!tpr->rx_std)
6147                 goto err_out;
6148
6149         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6150                 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
6151                                               GFP_KERNEL);
6152                 if (!tpr->rx_jmb_buffers)
6153                         goto err_out;
6154
6155                 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6156                                                    TG3_RX_JUMBO_RING_BYTES,
6157                                                    &tpr->rx_jmb_mapping);
6158                 if (!tpr->rx_jmb)
6159                         goto err_out;
6160         }
6161
6162         return 0;
6163
6164 err_out:
6165         tg3_rx_prodring_fini(tp, tpr);
6166         return -ENOMEM;
6167 }
6168
6169 /* Free up pending packets in all rx/tx rings.
6170  *
6171  * The chip has been shut down and the driver detached from
6172  * the networking, so no interrupts or new tx packets will
6173  * end up in the driver.  tp->{tx,}lock is not held and we are not
6174  * in an interrupt context and thus may sleep.
6175  */
6176 static void tg3_free_rings(struct tg3 *tp)
6177 {
6178         int i, j;
6179
6180         for (j = 0; j < tp->irq_cnt; j++) {
6181                 struct tg3_napi *tnapi = &tp->napi[j];
6182
6183                 if (!tnapi->tx_buffers)
6184                         continue;
6185
6186                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6187                         struct ring_info *txp;
6188                         struct sk_buff *skb;
6189                         unsigned int k;
6190
6191                         txp = &tnapi->tx_buffers[i];
6192                         skb = txp->skb;
6193
6194                         if (skb == NULL) {
6195                                 i++;
6196                                 continue;
6197                         }
6198
6199                         pci_unmap_single(tp->pdev,
6200                                          pci_unmap_addr(txp, mapping),
6201                                          skb_headlen(skb),
6202                                          PCI_DMA_TODEVICE);
6203                         txp->skb = NULL;
6204
6205                         i++;
6206
6207                         for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6208                                 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6209                                 pci_unmap_page(tp->pdev,
6210                                                pci_unmap_addr(txp, mapping),
6211                                                skb_shinfo(skb)->frags[k].size,
6212                                                PCI_DMA_TODEVICE);
6213                                 i++;
6214                         }
6215
6216                         dev_kfree_skb_any(skb);
6217                 }
6218
6219                 tg3_rx_prodring_free(tp, &tp->prodring[j]);
6220         }
6221 }
6222
6223 /* Initialize tx/rx rings for packet processing.
6224  *
6225  * The chip has been shut down and the driver detached from
6226  * the networking, so no interrupts or new tx packets will
6227  * end up in the driver.  tp->{tx,}lock are held and thus
6228  * we may not sleep.
6229  */
6230 static int tg3_init_rings(struct tg3 *tp)
6231 {
6232         int i;
6233
6234         /* Free up all the SKBs. */
6235         tg3_free_rings(tp);
6236
6237         for (i = 0; i < tp->irq_cnt; i++) {
6238                 struct tg3_napi *tnapi = &tp->napi[i];
6239
6240                 tnapi->last_tag = 0;
6241                 tnapi->last_irq_tag = 0;
6242                 tnapi->hw_status->status = 0;
6243                 tnapi->hw_status->status_tag = 0;
6244                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6245
6246                 tnapi->tx_prod = 0;
6247                 tnapi->tx_cons = 0;
6248                 if (tnapi->tx_ring)
6249                         memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6250
6251                 tnapi->rx_rcb_ptr = 0;
6252                 if (tnapi->rx_rcb)
6253                         memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6254
6255                 if (tg3_rx_prodring_alloc(tp, &tp->prodring[i])) {
6256                         tg3_free_rings(tp);
6257                         return -ENOMEM;
6258                 }
6259         }
6260
6261         return 0;
6262 }
6263
6264 /*
6265  * Must not be invoked with interrupt sources disabled and
6266  * the hardware shutdown down.
6267  */
6268 static void tg3_free_consistent(struct tg3 *tp)
6269 {
6270         int i;
6271
6272         for (i = 0; i < tp->irq_cnt; i++) {
6273                 struct tg3_napi *tnapi = &tp->napi[i];
6274
6275                 if (tnapi->tx_ring) {
6276                         pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6277                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
6278                         tnapi->tx_ring = NULL;
6279                 }
6280
6281                 kfree(tnapi->tx_buffers);
6282                 tnapi->tx_buffers = NULL;
6283
6284                 if (tnapi->rx_rcb) {
6285                         pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6286                                             tnapi->rx_rcb,
6287                                             tnapi->rx_rcb_mapping);
6288                         tnapi->rx_rcb = NULL;
6289                 }
6290
6291                 if (tnapi->hw_status) {
6292                         pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6293                                             tnapi->hw_status,
6294                                             tnapi->status_mapping);
6295                         tnapi->hw_status = NULL;
6296                 }
6297         }
6298
6299         if (tp->hw_stats) {
6300                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6301                                     tp->hw_stats, tp->stats_mapping);
6302                 tp->hw_stats = NULL;
6303         }
6304
6305         for (i = 0; i < tp->irq_cnt; i++)
6306                 tg3_rx_prodring_fini(tp, &tp->prodring[i]);
6307 }
6308
6309 /*
6310  * Must not be invoked with interrupt sources disabled and
6311  * the hardware shutdown down.  Can sleep.
6312  */
6313 static int tg3_alloc_consistent(struct tg3 *tp)
6314 {
6315         int i;
6316
6317         for (i = 0; i < tp->irq_cnt; i++) {
6318                 if (tg3_rx_prodring_init(tp, &tp->prodring[i]))
6319                         goto err_out;
6320         }
6321
6322         tp->hw_stats = pci_alloc_consistent(tp->pdev,
6323                                             sizeof(struct tg3_hw_stats),
6324                                             &tp->stats_mapping);
6325         if (!tp->hw_stats)
6326                 goto err_out;
6327
6328         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6329
6330         for (i = 0; i < tp->irq_cnt; i++) {
6331                 struct tg3_napi *tnapi = &tp->napi[i];
6332                 struct tg3_hw_status *sblk;
6333
6334                 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6335                                                         TG3_HW_STATUS_SIZE,
6336                                                         &tnapi->status_mapping);
6337                 if (!tnapi->hw_status)
6338                         goto err_out;
6339
6340                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6341                 sblk = tnapi->hw_status;
6342
6343                 /* If multivector TSS is enabled, vector 0 does not handle
6344                  * tx interrupts.  Don't allocate any resources for it.
6345                  */
6346                 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6347                     (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6348                         tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6349                                                     TG3_TX_RING_SIZE,
6350                                                     GFP_KERNEL);
6351                         if (!tnapi->tx_buffers)
6352                                 goto err_out;
6353
6354                         tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6355                                                               TG3_TX_RING_BYTES,
6356                                                        &tnapi->tx_desc_mapping);
6357                         if (!tnapi->tx_ring)
6358                                 goto err_out;
6359                 }
6360
6361                 /*
6362                  * When RSS is enabled, the status block format changes
6363                  * slightly.  The "rx_jumbo_consumer", "reserved",
6364                  * and "rx_mini_consumer" members get mapped to the
6365                  * other three rx return ring producer indexes.
6366                  */
6367                 switch (i) {
6368                 default:
6369                         tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6370                         break;
6371                 case 2:
6372                         tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6373                         break;
6374                 case 3:
6375                         tnapi->rx_rcb_prod_idx = &sblk->reserved;
6376                         break;
6377                 case 4:
6378                         tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6379                         break;
6380                 }
6381
6382                 tnapi->prodring = &tp->prodring[i];
6383
6384                 /*
6385                  * If multivector RSS is enabled, vector 0 does not handle
6386                  * rx or tx interrupts.  Don't allocate any resources for it.
6387                  */
6388                 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6389                         continue;
6390
6391                 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6392                                                      TG3_RX_RCB_RING_BYTES(tp),
6393                                                      &tnapi->rx_rcb_mapping);
6394                 if (!tnapi->rx_rcb)
6395                         goto err_out;
6396
6397                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6398         }
6399
6400         return 0;
6401
6402 err_out:
6403         tg3_free_consistent(tp);
6404         return -ENOMEM;
6405 }
6406
6407 #define MAX_WAIT_CNT 1000
6408
6409 /* To stop a block, clear the enable bit and poll till it
6410  * clears.  tp->lock is held.
6411  */
6412 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6413 {
6414         unsigned int i;
6415         u32 val;
6416
6417         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6418                 switch (ofs) {
6419                 case RCVLSC_MODE:
6420                 case DMAC_MODE:
6421                 case MBFREE_MODE:
6422                 case BUFMGR_MODE:
6423                 case MEMARB_MODE:
6424                         /* We can't enable/disable these bits of the
6425                          * 5705/5750, just say success.
6426                          */
6427                         return 0;
6428
6429                 default:
6430                         break;
6431                 }
6432         }
6433
6434         val = tr32(ofs);
6435         val &= ~enable_bit;
6436         tw32_f(ofs, val);
6437
6438         for (i = 0; i < MAX_WAIT_CNT; i++) {
6439                 udelay(100);
6440                 val = tr32(ofs);
6441                 if ((val & enable_bit) == 0)
6442                         break;
6443         }
6444
6445         if (i == MAX_WAIT_CNT && !silent) {
6446                 dev_err(&tp->pdev->dev,
6447                         "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6448                         ofs, enable_bit);
6449                 return -ENODEV;
6450         }
6451
6452         return 0;
6453 }
6454
6455 /* tp->lock is held. */
6456 static int tg3_abort_hw(struct tg3 *tp, int silent)
6457 {
6458         int i, err;
6459
6460         tg3_disable_ints(tp);
6461
6462         tp->rx_mode &= ~RX_MODE_ENABLE;
6463         tw32_f(MAC_RX_MODE, tp->rx_mode);
6464         udelay(10);
6465
6466         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6467         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6468         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6469         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6470         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6471         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6472
6473         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6474         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6475         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6476         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6477         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6478         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6479         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6480
6481         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6482         tw32_f(MAC_MODE, tp->mac_mode);
6483         udelay(40);
6484
6485         tp->tx_mode &= ~TX_MODE_ENABLE;
6486         tw32_f(MAC_TX_MODE, tp->tx_mode);
6487
6488         for (i = 0; i < MAX_WAIT_CNT; i++) {
6489                 udelay(100);
6490                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6491                         break;
6492         }
6493         if (i >= MAX_WAIT_CNT) {
6494                 dev_err(&tp->pdev->dev,
6495                         "%s timed out, TX_MODE_ENABLE will not clear "
6496                         "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
6497                 err |= -ENODEV;
6498         }
6499
6500         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6501         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6502         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6503
6504         tw32(FTQ_RESET, 0xffffffff);
6505         tw32(FTQ_RESET, 0x00000000);
6506
6507         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6508         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6509
6510         for (i = 0; i < tp->irq_cnt; i++) {
6511                 struct tg3_napi *tnapi = &tp->napi[i];
6512                 if (tnapi->hw_status)
6513                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6514         }
6515         if (tp->hw_stats)
6516                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6517
6518         return err;
6519 }
6520
6521 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6522 {
6523         int i;
6524         u32 apedata;
6525
6526         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6527         if (apedata != APE_SEG_SIG_MAGIC)
6528                 return;
6529
6530         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6531         if (!(apedata & APE_FW_STATUS_READY))
6532                 return;
6533
6534         /* Wait for up to 1 millisecond for APE to service previous event. */
6535         for (i = 0; i < 10; i++) {
6536                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6537                         return;
6538
6539                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6540
6541                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6542                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6543                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6544
6545                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6546
6547                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6548                         break;
6549
6550                 udelay(100);
6551         }
6552
6553         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6554                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6555 }
6556
6557 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6558 {
6559         u32 event;
6560         u32 apedata;
6561
6562         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6563                 return;
6564
6565         switch (kind) {
6566                 case RESET_KIND_INIT:
6567                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6568                                         APE_HOST_SEG_SIG_MAGIC);
6569                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6570                                         APE_HOST_SEG_LEN_MAGIC);
6571                         apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6572                         tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6573                         tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6574                                         APE_HOST_DRIVER_ID_MAGIC);
6575                         tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6576                                         APE_HOST_BEHAV_NO_PHYLOCK);
6577
6578                         event = APE_EVENT_STATUS_STATE_START;
6579                         break;
6580                 case RESET_KIND_SHUTDOWN:
6581                         /* With the interface we are currently using,
6582                          * APE does not track driver state.  Wiping
6583                          * out the HOST SEGMENT SIGNATURE forces
6584                          * the APE to assume OS absent status.
6585                          */
6586                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6587
6588                         event = APE_EVENT_STATUS_STATE_UNLOAD;
6589                         break;
6590                 case RESET_KIND_SUSPEND:
6591                         event = APE_EVENT_STATUS_STATE_SUSPEND;
6592                         break;
6593                 default:
6594                         return;
6595         }
6596
6597         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6598
6599         tg3_ape_send_event(tp, event);
6600 }
6601
6602 /* tp->lock is held. */
6603 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6604 {
6605         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6606                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6607
6608         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6609                 switch (kind) {
6610                 case RESET_KIND_INIT:
6611                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6612                                       DRV_STATE_START);
6613                         break;
6614
6615                 case RESET_KIND_SHUTDOWN:
6616                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6617                                       DRV_STATE_UNLOAD);
6618                         break;
6619
6620                 case RESET_KIND_SUSPEND:
6621                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6622                                       DRV_STATE_SUSPEND);
6623                         break;
6624
6625                 default:
6626                         break;
6627                 }
6628         }
6629
6630         if (kind == RESET_KIND_INIT ||
6631             kind == RESET_KIND_SUSPEND)
6632                 tg3_ape_driver_state_change(tp, kind);
6633 }
6634
6635 /* tp->lock is held. */
6636 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6637 {
6638         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6639                 switch (kind) {
6640                 case RESET_KIND_INIT:
6641                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6642                                       DRV_STATE_START_DONE);
6643                         break;
6644
6645                 case RESET_KIND_SHUTDOWN:
6646                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6647                                       DRV_STATE_UNLOAD_DONE);
6648                         break;
6649
6650                 default:
6651                         break;
6652                 }
6653         }
6654
6655         if (kind == RESET_KIND_SHUTDOWN)
6656                 tg3_ape_driver_state_change(tp, kind);
6657 }
6658
6659 /* tp->lock is held. */
6660 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6661 {
6662         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6663                 switch (kind) {
6664                 case RESET_KIND_INIT:
6665                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6666                                       DRV_STATE_START);
6667                         break;
6668
6669                 case RESET_KIND_SHUTDOWN:
6670                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6671                                       DRV_STATE_UNLOAD);
6672                         break;
6673
6674                 case RESET_KIND_SUSPEND:
6675                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6676                                       DRV_STATE_SUSPEND);
6677                         break;
6678
6679                 default:
6680                         break;
6681                 }
6682         }
6683 }
6684
6685 static int tg3_poll_fw(struct tg3 *tp)
6686 {
6687         int i;
6688         u32 val;
6689
6690         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6691                 /* Wait up to 20ms for init done. */
6692                 for (i = 0; i < 200; i++) {
6693                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6694                                 return 0;
6695                         udelay(100);
6696                 }
6697                 return -ENODEV;
6698         }
6699
6700         /* Wait for firmware initialization to complete. */
6701         for (i = 0; i < 100000; i++) {
6702                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6703                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6704                         break;
6705                 udelay(10);
6706         }
6707
6708         /* Chip might not be fitted with firmware.  Some Sun onboard
6709          * parts are configured like that.  So don't signal the timeout
6710          * of the above loop as an error, but do report the lack of
6711          * running firmware once.
6712          */
6713         if (i >= 100000 &&
6714             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6715                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6716
6717                 netdev_info(tp->dev, "No firmware running\n");
6718         }
6719
6720         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6721                 /* The 57765 A0 needs a little more
6722                  * time to do some important work.
6723                  */
6724                 mdelay(10);
6725         }
6726
6727         return 0;
6728 }
6729
6730 /* Save PCI command register before chip reset */
6731 static void tg3_save_pci_state(struct tg3 *tp)
6732 {
6733         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6734 }
6735
6736 /* Restore PCI state after chip reset */
6737 static void tg3_restore_pci_state(struct tg3 *tp)
6738 {
6739         u32 val;
6740
6741         /* Re-enable indirect register accesses. */
6742         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6743                                tp->misc_host_ctrl);
6744
6745         /* Set MAX PCI retry to zero. */
6746         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6747         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6748             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6749                 val |= PCISTATE_RETRY_SAME_DMA;
6750         /* Allow reads and writes to the APE register and memory space. */
6751         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6752                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6753                        PCISTATE_ALLOW_APE_SHMEM_WR;
6754         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6755
6756         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6757
6758         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6759                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6760                         pcie_set_readrq(tp->pdev, 4096);
6761                 else {
6762                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6763                                               tp->pci_cacheline_sz);
6764                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6765                                               tp->pci_lat_timer);
6766                 }
6767         }
6768
6769         /* Make sure PCI-X relaxed ordering bit is clear. */
6770         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6771                 u16 pcix_cmd;
6772
6773                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6774                                      &pcix_cmd);
6775                 pcix_cmd &= ~PCI_X_CMD_ERO;
6776                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6777                                       pcix_cmd);
6778         }
6779
6780         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6781
6782                 /* Chip reset on 5780 will reset MSI enable bit,
6783                  * so need to restore it.
6784                  */
6785                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6786                         u16 ctrl;
6787
6788                         pci_read_config_word(tp->pdev,
6789                                              tp->msi_cap + PCI_MSI_FLAGS,
6790                                              &ctrl);
6791                         pci_write_config_word(tp->pdev,
6792                                               tp->msi_cap + PCI_MSI_FLAGS,
6793                                               ctrl | PCI_MSI_FLAGS_ENABLE);
6794                         val = tr32(MSGINT_MODE);
6795                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6796                 }
6797         }
6798 }
6799
6800 static void tg3_stop_fw(struct tg3 *);
6801
6802 /* tp->lock is held. */
6803 static int tg3_chip_reset(struct tg3 *tp)
6804 {
6805         u32 val;
6806         void (*write_op)(struct tg3 *, u32, u32);
6807         int i, err;
6808
6809         tg3_nvram_lock(tp);
6810
6811         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6812
6813         /* No matching tg3_nvram_unlock() after this because
6814          * chip reset below will undo the nvram lock.
6815          */
6816         tp->nvram_lock_cnt = 0;
6817
6818         /* GRC_MISC_CFG core clock reset will clear the memory
6819          * enable bit in PCI register 4 and the MSI enable bit
6820          * on some chips, so we save relevant registers here.
6821          */
6822         tg3_save_pci_state(tp);
6823
6824         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6825             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6826                 tw32(GRC_FASTBOOT_PC, 0);
6827
6828         /*
6829          * We must avoid the readl() that normally takes place.
6830          * It locks machines, causes machine checks, and other
6831          * fun things.  So, temporarily disable the 5701
6832          * hardware workaround, while we do the reset.
6833          */
6834         write_op = tp->write32;
6835         if (write_op == tg3_write_flush_reg32)
6836                 tp->write32 = tg3_write32;
6837
6838         /* Prevent the irq handler from reading or writing PCI registers
6839          * during chip reset when the memory enable bit in the PCI command
6840          * register may be cleared.  The chip does not generate interrupt
6841          * at this time, but the irq handler may still be called due to irq
6842          * sharing or irqpoll.
6843          */
6844         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6845         for (i = 0; i < tp->irq_cnt; i++) {
6846                 struct tg3_napi *tnapi = &tp->napi[i];
6847                 if (tnapi->hw_status) {
6848                         tnapi->hw_status->status = 0;
6849                         tnapi->hw_status->status_tag = 0;
6850                 }
6851                 tnapi->last_tag = 0;
6852                 tnapi->last_irq_tag = 0;
6853         }
6854         smp_mb();
6855
6856         for (i = 0; i < tp->irq_cnt; i++)
6857                 synchronize_irq(tp->napi[i].irq_vec);
6858
6859         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6860                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6861                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6862         }
6863
6864         /* do the reset */
6865         val = GRC_MISC_CFG_CORECLK_RESET;
6866
6867         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6868                 if (tr32(0x7e2c) == 0x60) {
6869                         tw32(0x7e2c, 0x20);
6870                 }
6871                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6872                         tw32(GRC_MISC_CFG, (1 << 29));
6873                         val |= (1 << 29);
6874                 }
6875         }
6876
6877         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6878                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6879                 tw32(GRC_VCPU_EXT_CTRL,
6880                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6881         }
6882
6883         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6884                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6885         tw32(GRC_MISC_CFG, val);
6886
6887         /* restore 5701 hardware bug workaround write method */
6888         tp->write32 = write_op;
6889
6890         /* Unfortunately, we have to delay before the PCI read back.
6891          * Some 575X chips even will not respond to a PCI cfg access
6892          * when the reset command is given to the chip.
6893          *
6894          * How do these hardware designers expect things to work
6895          * properly if the PCI write is posted for a long period
6896          * of time?  It is always necessary to have some method by
6897          * which a register read back can occur to push the write
6898          * out which does the reset.
6899          *
6900          * For most tg3 variants the trick below was working.
6901          * Ho hum...
6902          */
6903         udelay(120);
6904
6905         /* Flush PCI posted writes.  The normal MMIO registers
6906          * are inaccessible at this time so this is the only
6907          * way to make this reliably (actually, this is no longer
6908          * the case, see above).  I tried to use indirect
6909          * register read/write but this upset some 5701 variants.
6910          */
6911         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6912
6913         udelay(120);
6914
6915         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6916                 u16 val16;
6917
6918                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6919                         int i;
6920                         u32 cfg_val;
6921
6922                         /* Wait for link training to complete.  */
6923                         for (i = 0; i < 5000; i++)
6924                                 udelay(100);
6925
6926                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6927                         pci_write_config_dword(tp->pdev, 0xc4,
6928                                                cfg_val | (1 << 15));
6929                 }
6930
6931                 /* Clear the "no snoop" and "relaxed ordering" bits. */
6932                 pci_read_config_word(tp->pdev,
6933                                      tp->pcie_cap + PCI_EXP_DEVCTL,
6934                                      &val16);
6935                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6936                            PCI_EXP_DEVCTL_NOSNOOP_EN);
6937                 /*
6938                  * Older PCIe devices only support the 128 byte
6939                  * MPS setting.  Enforce the restriction.
6940                  */
6941                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6942                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6943                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
6944                 pci_write_config_word(tp->pdev,
6945                                       tp->pcie_cap + PCI_EXP_DEVCTL,
6946                                       val16);
6947
6948                 pcie_set_readrq(tp->pdev, 4096);
6949
6950                 /* Clear error status */
6951                 pci_write_config_word(tp->pdev,
6952                                       tp->pcie_cap + PCI_EXP_DEVSTA,
6953                                       PCI_EXP_DEVSTA_CED |
6954                                       PCI_EXP_DEVSTA_NFED |
6955                                       PCI_EXP_DEVSTA_FED |
6956                                       PCI_EXP_DEVSTA_URD);
6957         }
6958
6959         tg3_restore_pci_state(tp);
6960
6961         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6962
6963         val = 0;
6964         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6965                 val = tr32(MEMARB_MODE);
6966         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6967
6968         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6969                 tg3_stop_fw(tp);
6970                 tw32(0x5000, 0x400);
6971         }
6972
6973         tw32(GRC_MODE, tp->grc_mode);
6974
6975         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6976                 val = tr32(0xc4);
6977
6978                 tw32(0xc4, val | (1 << 15));
6979         }
6980
6981         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6982             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6983                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6984                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6985                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6986                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6987         }
6988
6989         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6990                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6991                 tw32_f(MAC_MODE, tp->mac_mode);
6992         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6993                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6994                 tw32_f(MAC_MODE, tp->mac_mode);
6995         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6996                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6997                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6998                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6999                 tw32_f(MAC_MODE, tp->mac_mode);
7000         } else
7001                 tw32_f(MAC_MODE, 0);
7002         udelay(40);
7003
7004         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7005
7006         err = tg3_poll_fw(tp);
7007         if (err)
7008                 return err;
7009
7010         tg3_mdio_start(tp);
7011
7012         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7013                 u8 phy_addr;
7014
7015                 phy_addr = tp->phy_addr;
7016                 tp->phy_addr = TG3_PHY_PCIE_ADDR;
7017
7018                 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
7019                              TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
7020                 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
7021                       TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
7022                       TG3_PCIEPHY_TX0CTRL1_NB_EN;
7023                 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
7024                 udelay(10);
7025
7026                 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
7027                              TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
7028                 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
7029                       TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
7030                 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
7031                 udelay(10);
7032
7033                 tp->phy_addr = phy_addr;
7034         }
7035
7036         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
7037             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7038             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7039             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
7040             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
7041                 val = tr32(0x7c00);
7042
7043                 tw32(0x7c00, val | (1 << 25));
7044         }
7045
7046         /* Reprobe ASF enable state.  */
7047         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7048         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7049         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7050         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7051                 u32 nic_cfg;
7052
7053                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7054                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7055                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7056                         tp->last_event_jiffies = jiffies;
7057                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7058                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7059                 }
7060         }
7061
7062         return 0;
7063 }
7064
7065 /* tp->lock is held. */
7066 static void tg3_stop_fw(struct tg3 *tp)
7067 {
7068         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7069            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7070                 /* Wait for RX cpu to ACK the previous event. */
7071                 tg3_wait_for_event_ack(tp);
7072
7073                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7074
7075                 tg3_generate_fw_event(tp);
7076
7077                 /* Wait for RX cpu to ACK this event. */
7078                 tg3_wait_for_event_ack(tp);
7079         }
7080 }
7081
7082 /* tp->lock is held. */
7083 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7084 {
7085         int err;
7086
7087         tg3_stop_fw(tp);
7088
7089         tg3_write_sig_pre_reset(tp, kind);
7090
7091         tg3_abort_hw(tp, silent);
7092         err = tg3_chip_reset(tp);
7093
7094         __tg3_set_mac_addr(tp, 0);
7095
7096         tg3_write_sig_legacy(tp, kind);
7097         tg3_write_sig_post_reset(tp, kind);
7098
7099         if (err)
7100                 return err;
7101
7102         return 0;
7103 }
7104
7105 #define RX_CPU_SCRATCH_BASE     0x30000
7106 #define RX_CPU_SCRATCH_SIZE     0x04000
7107 #define TX_CPU_SCRATCH_BASE     0x34000
7108 #define TX_CPU_SCRATCH_SIZE     0x04000
7109
7110 /* tp->lock is held. */
7111 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7112 {
7113         int i;
7114
7115         BUG_ON(offset == TX_CPU_BASE &&
7116             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7117
7118         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7119                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7120
7121                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7122                 return 0;
7123         }
7124         if (offset == RX_CPU_BASE) {
7125                 for (i = 0; i < 10000; i++) {
7126                         tw32(offset + CPU_STATE, 0xffffffff);
7127                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7128                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7129                                 break;
7130                 }
7131
7132                 tw32(offset + CPU_STATE, 0xffffffff);
7133                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
7134                 udelay(10);
7135         } else {
7136                 for (i = 0; i < 10000; i++) {
7137                         tw32(offset + CPU_STATE, 0xffffffff);
7138                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7139                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7140                                 break;
7141                 }
7142         }
7143
7144         if (i >= 10000) {
7145                 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7146                            __func__, offset == RX_CPU_BASE ? "RX" : "TX");
7147                 return -ENODEV;
7148         }
7149
7150         /* Clear firmware's nvram arbitration. */
7151         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7152                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7153         return 0;
7154 }
7155
7156 struct fw_info {
7157         unsigned int fw_base;
7158         unsigned int fw_len;
7159         const __be32 *fw_data;
7160 };
7161
7162 /* tp->lock is held. */
7163 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7164                                  int cpu_scratch_size, struct fw_info *info)
7165 {
7166         int err, lock_err, i;
7167         void (*write_op)(struct tg3 *, u32, u32);
7168
7169         if (cpu_base == TX_CPU_BASE &&
7170             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7171                 netdev_err(tp->dev,
7172                            "%s: Trying to load TX cpu firmware which is 5705\n",
7173                            __func__);
7174                 return -EINVAL;
7175         }
7176
7177         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7178                 write_op = tg3_write_mem;
7179         else
7180                 write_op = tg3_write_indirect_reg32;
7181
7182         /* It is possible that bootcode is still loading at this point.
7183          * Get the nvram lock first before halting the cpu.
7184          */
7185         lock_err = tg3_nvram_lock(tp);
7186         err = tg3_halt_cpu(tp, cpu_base);
7187         if (!lock_err)
7188                 tg3_nvram_unlock(tp);
7189         if (err)
7190                 goto out;
7191
7192         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7193                 write_op(tp, cpu_scratch_base + i, 0);
7194         tw32(cpu_base + CPU_STATE, 0xffffffff);
7195         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7196         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7197                 write_op(tp, (cpu_scratch_base +
7198                               (info->fw_base & 0xffff) +
7199                               (i * sizeof(u32))),
7200                               be32_to_cpu(info->fw_data[i]));
7201
7202         err = 0;
7203
7204 out:
7205         return err;
7206 }
7207
7208 /* tp->lock is held. */
7209 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7210 {
7211         struct fw_info info;
7212         const __be32 *fw_data;
7213         int err, i;
7214
7215         fw_data = (void *)tp->fw->data;
7216
7217         /* Firmware blob starts with version numbers, followed by
7218            start address and length. We are setting complete length.
7219            length = end_address_of_bss - start_address_of_text.
7220            Remainder is the blob to be loaded contiguously
7221            from start address. */
7222
7223         info.fw_base = be32_to_cpu(fw_data[1]);
7224         info.fw_len = tp->fw->size - 12;
7225         info.fw_data = &fw_data[3];
7226
7227         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7228                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7229                                     &info);
7230         if (err)
7231                 return err;
7232
7233         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7234                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7235                                     &info);
7236         if (err)
7237                 return err;
7238
7239         /* Now startup only the RX cpu. */
7240         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7241         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7242
7243         for (i = 0; i < 5; i++) {
7244                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7245                         break;
7246                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7247                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
7248                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7249                 udelay(1000);
7250         }
7251         if (i >= 5) {
7252                 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7253                            "should be %08x\n", __func__,
7254                            tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
7255                 return -ENODEV;
7256         }
7257         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7258         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
7259
7260         return 0;
7261 }
7262
7263 /* 5705 needs a special version of the TSO firmware.  */
7264
7265 /* tp->lock is held. */
7266 static int tg3_load_tso_firmware(struct tg3 *tp)
7267 {
7268         struct fw_info info;
7269         const __be32 *fw_data;
7270         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7271         int err, i;
7272
7273         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7274                 return 0;
7275
7276         fw_data = (void *)tp->fw->data;
7277
7278         /* Firmware blob starts with version numbers, followed by
7279            start address and length. We are setting complete length.
7280            length = end_address_of_bss - start_address_of_text.
7281            Remainder is the blob to be loaded contiguously
7282            from start address. */
7283
7284         info.fw_base = be32_to_cpu(fw_data[1]);
7285         cpu_scratch_size = tp->fw_len;
7286         info.fw_len = tp->fw->size - 12;
7287         info.fw_data = &fw_data[3];
7288
7289         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7290                 cpu_base = RX_CPU_BASE;
7291                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7292         } else {
7293                 cpu_base = TX_CPU_BASE;
7294                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7295                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7296         }
7297
7298         err = tg3_load_firmware_cpu(tp, cpu_base,
7299                                     cpu_scratch_base, cpu_scratch_size,
7300                                     &info);
7301         if (err)
7302                 return err;
7303
7304         /* Now startup the cpu. */
7305         tw32(cpu_base + CPU_STATE, 0xffffffff);
7306         tw32_f(cpu_base + CPU_PC, info.fw_base);
7307
7308         for (i = 0; i < 5; i++) {
7309                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7310                         break;
7311                 tw32(cpu_base + CPU_STATE, 0xffffffff);
7312                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
7313                 tw32_f(cpu_base + CPU_PC, info.fw_base);
7314                 udelay(1000);
7315         }
7316         if (i >= 5) {
7317                 netdev_err(tp->dev,
7318                            "%s fails to set CPU PC, is %08x should be %08x\n",
7319                            __func__, tr32(cpu_base + CPU_PC), info.fw_base);
7320                 return -ENODEV;
7321         }
7322         tw32(cpu_base + CPU_STATE, 0xffffffff);
7323         tw32_f(cpu_base + CPU_MODE,  0x00000000);
7324         return 0;
7325 }
7326
7327
7328 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7329 {
7330         struct tg3 *tp = netdev_priv(dev);
7331         struct sockaddr *addr = p;
7332         int err = 0, skip_mac_1 = 0;
7333
7334         if (!is_valid_ether_addr(addr->sa_data))
7335                 return -EINVAL;
7336
7337         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7338
7339         if (!netif_running(dev))
7340                 return 0;
7341
7342         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7343                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7344
7345                 addr0_high = tr32(MAC_ADDR_0_HIGH);
7346                 addr0_low = tr32(MAC_ADDR_0_LOW);
7347                 addr1_high = tr32(MAC_ADDR_1_HIGH);
7348                 addr1_low = tr32(MAC_ADDR_1_LOW);
7349
7350                 /* Skip MAC addr 1 if ASF is using it. */
7351                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7352                     !(addr1_high == 0 && addr1_low == 0))
7353                         skip_mac_1 = 1;
7354         }
7355         spin_lock_bh(&tp->lock);
7356         __tg3_set_mac_addr(tp, skip_mac_1);
7357         spin_unlock_bh(&tp->lock);
7358
7359         return err;
7360 }
7361
7362 /* tp->lock is held. */
7363 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7364                            dma_addr_t mapping, u32 maxlen_flags,
7365                            u32 nic_addr)
7366 {
7367         tg3_write_mem(tp,
7368                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7369                       ((u64) mapping >> 32));
7370         tg3_write_mem(tp,
7371                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7372                       ((u64) mapping & 0xffffffff));
7373         tg3_write_mem(tp,
7374                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7375                        maxlen_flags);
7376
7377         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7378                 tg3_write_mem(tp,
7379                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7380                               nic_addr);
7381 }
7382
7383 static void __tg3_set_rx_mode(struct net_device *);
7384 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7385 {
7386         int i;
7387
7388         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7389                 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7390                 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7391                 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7392         } else {
7393                 tw32(HOSTCC_TXCOL_TICKS, 0);
7394                 tw32(HOSTCC_TXMAX_FRAMES, 0);
7395                 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7396         }
7397
7398         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7399                 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7400                 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7401                 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7402         } else {
7403                 tw32(HOSTCC_RXCOL_TICKS, 0);
7404                 tw32(HOSTCC_RXMAX_FRAMES, 0);
7405                 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7406         }
7407
7408         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7409                 u32 val = ec->stats_block_coalesce_usecs;
7410
7411                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7412                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7413
7414                 if (!netif_carrier_ok(tp->dev))
7415                         val = 0;
7416
7417                 tw32(HOSTCC_STAT_COAL_TICKS, val);
7418         }
7419
7420         for (i = 0; i < tp->irq_cnt - 1; i++) {
7421                 u32 reg;
7422
7423                 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7424                 tw32(reg, ec->rx_coalesce_usecs);
7425                 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7426                 tw32(reg, ec->rx_max_coalesced_frames);
7427                 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7428                 tw32(reg, ec->rx_max_coalesced_frames_irq);
7429
7430                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7431                         reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7432                         tw32(reg, ec->tx_coalesce_usecs);
7433                         reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7434                         tw32(reg, ec->tx_max_coalesced_frames);
7435                         reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7436                         tw32(reg, ec->tx_max_coalesced_frames_irq);
7437                 }
7438         }
7439
7440         for (; i < tp->irq_max - 1; i++) {
7441                 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7442                 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7443                 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7444
7445                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7446                         tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7447                         tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7448                         tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7449                 }
7450         }
7451 }
7452
7453 /* tp->lock is held. */
7454 static void tg3_rings_reset(struct tg3 *tp)
7455 {
7456         int i;
7457         u32 stblk, txrcb, rxrcb, limit;
7458         struct tg3_napi *tnapi = &tp->napi[0];
7459
7460         /* Disable all transmit rings but the first. */
7461         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7462                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7463         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7464                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7465         else
7466                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7467
7468         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7469              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7470                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7471                               BDINFO_FLAGS_DISABLED);
7472
7473
7474         /* Disable all receive return rings but the first. */
7475         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7476                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7477         else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7478                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7479         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7480                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7481                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7482         else
7483                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7484
7485         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7486              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7487                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7488                               BDINFO_FLAGS_DISABLED);
7489
7490         /* Disable interrupts */
7491         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7492
7493         /* Zero mailbox registers. */
7494         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7495                 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7496                         tp->napi[i].tx_prod = 0;
7497                         tp->napi[i].tx_cons = 0;
7498                         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7499                                 tw32_mailbox(tp->napi[i].prodmbox, 0);
7500                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
7501                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7502                 }
7503                 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7504                         tw32_mailbox(tp->napi[0].prodmbox, 0);
7505         } else {
7506                 tp->napi[0].tx_prod = 0;
7507                 tp->napi[0].tx_cons = 0;
7508                 tw32_mailbox(tp->napi[0].prodmbox, 0);
7509                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7510         }
7511
7512         /* Make sure the NIC-based send BD rings are disabled. */
7513         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7514                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7515                 for (i = 0; i < 16; i++)
7516                         tw32_tx_mbox(mbox + i * 8, 0);
7517         }
7518
7519         txrcb = NIC_SRAM_SEND_RCB;
7520         rxrcb = NIC_SRAM_RCV_RET_RCB;
7521
7522         /* Clear status block in ram. */
7523         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7524
7525         /* Set status block DMA address */
7526         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7527              ((u64) tnapi->status_mapping >> 32));
7528         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7529              ((u64) tnapi->status_mapping & 0xffffffff));
7530
7531         if (tnapi->tx_ring) {
7532                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7533                                (TG3_TX_RING_SIZE <<
7534                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7535                                NIC_SRAM_TX_BUFFER_DESC);
7536                 txrcb += TG3_BDINFO_SIZE;
7537         }
7538
7539         if (tnapi->rx_rcb) {
7540                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7541                                (TG3_RX_RCB_RING_SIZE(tp) <<
7542                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7543                 rxrcb += TG3_BDINFO_SIZE;
7544         }
7545
7546         stblk = HOSTCC_STATBLCK_RING1;
7547
7548         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7549                 u64 mapping = (u64)tnapi->status_mapping;
7550                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7551                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7552
7553                 /* Clear status block in ram. */
7554                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7555
7556                 if (tnapi->tx_ring) {
7557                         tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7558                                        (TG3_TX_RING_SIZE <<
7559                                         BDINFO_FLAGS_MAXLEN_SHIFT),
7560                                        NIC_SRAM_TX_BUFFER_DESC);
7561                         txrcb += TG3_BDINFO_SIZE;
7562                 }
7563
7564                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7565                                (TG3_RX_RCB_RING_SIZE(tp) <<
7566                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7567
7568                 stblk += 8;
7569                 rxrcb += TG3_BDINFO_SIZE;
7570         }
7571 }
7572
7573 /* tp->lock is held. */
7574 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7575 {
7576         u32 val, rdmac_mode;
7577         int i, err, limit;
7578         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
7579
7580         tg3_disable_ints(tp);
7581
7582         tg3_stop_fw(tp);
7583
7584         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7585
7586         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
7587                 tg3_abort_hw(tp, 1);
7588         }
7589
7590         if (reset_phy)
7591                 tg3_phy_reset(tp);
7592
7593         err = tg3_chip_reset(tp);
7594         if (err)
7595                 return err;
7596
7597         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7598
7599         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7600                 val = tr32(TG3_CPMU_CTRL);
7601                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7602                 tw32(TG3_CPMU_CTRL, val);
7603
7604                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7605                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7606                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7607                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7608
7609                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7610                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7611                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7612                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7613
7614                 val = tr32(TG3_CPMU_HST_ACC);
7615                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7616                 val |= CPMU_HST_ACC_MACCLK_6_25;
7617                 tw32(TG3_CPMU_HST_ACC, val);
7618         }
7619
7620         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7621                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7622                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7623                        PCIE_PWR_MGMT_L1_THRESH_4MS;
7624                 tw32(PCIE_PWR_MGMT_THRESH, val);
7625
7626                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7627                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7628
7629                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7630
7631                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7632                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7633         }
7634
7635         if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7636                 u32 grc_mode = tr32(GRC_MODE);
7637
7638                 /* Access the lower 1K of PL PCIE block registers. */
7639                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7640                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7641
7642                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7643                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7644                      val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7645
7646                 tw32(GRC_MODE, grc_mode);
7647         }
7648
7649         /* This works around an issue with Athlon chipsets on
7650          * B3 tigon3 silicon.  This bit has no effect on any
7651          * other revision.  But do not set this on PCI Express
7652          * chips and don't even touch the clocks if the CPMU is present.
7653          */
7654         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7655                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7656                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7657                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7658         }
7659
7660         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7661             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7662                 val = tr32(TG3PCI_PCISTATE);
7663                 val |= PCISTATE_RETRY_SAME_DMA;
7664                 tw32(TG3PCI_PCISTATE, val);
7665         }
7666
7667         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7668                 /* Allow reads and writes to the
7669                  * APE register and memory space.
7670                  */
7671                 val = tr32(TG3PCI_PCISTATE);
7672                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7673                        PCISTATE_ALLOW_APE_SHMEM_WR;
7674                 tw32(TG3PCI_PCISTATE, val);
7675         }
7676
7677         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7678                 /* Enable some hw fixes.  */
7679                 val = tr32(TG3PCI_MSI_DATA);
7680                 val |= (1 << 26) | (1 << 28) | (1 << 29);
7681                 tw32(TG3PCI_MSI_DATA, val);
7682         }
7683
7684         /* Descriptor ring init may make accesses to the
7685          * NIC SRAM area to setup the TX descriptors, so we
7686          * can only do this after the hardware has been
7687          * successfully reset.
7688          */
7689         err = tg3_init_rings(tp);
7690         if (err)
7691                 return err;
7692
7693         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7694             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7695                 val = tr32(TG3PCI_DMA_RW_CTRL) &
7696                       ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7697                 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7698         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7699                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7700                 /* This value is determined during the probe time DMA
7701                  * engine test, tg3_test_dma.
7702                  */
7703                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7704         }
7705
7706         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7707                           GRC_MODE_4X_NIC_SEND_RINGS |
7708                           GRC_MODE_NO_TX_PHDR_CSUM |
7709                           GRC_MODE_NO_RX_PHDR_CSUM);
7710         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7711
7712         /* Pseudo-header checksum is done by hardware logic and not
7713          * the offload processers, so make the chip do the pseudo-
7714          * header checksums on receive.  For transmit it is more
7715          * convenient to do the pseudo-header checksum in software
7716          * as Linux does that on transmit for us in all cases.
7717          */
7718         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7719
7720         tw32(GRC_MODE,
7721              tp->grc_mode |
7722              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7723
7724         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7725         val = tr32(GRC_MISC_CFG);
7726         val &= ~0xff;
7727         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7728         tw32(GRC_MISC_CFG, val);
7729
7730         /* Initialize MBUF/DESC pool. */
7731         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7732                 /* Do nothing.  */
7733         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7734                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7735                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7736                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7737                 else
7738                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7739                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7740                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7741         }
7742         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7743                 int fw_len;
7744
7745                 fw_len = tp->fw_len;
7746                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7747                 tw32(BUFMGR_MB_POOL_ADDR,
7748                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7749                 tw32(BUFMGR_MB_POOL_SIZE,
7750                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7751         }
7752
7753         if (tp->dev->mtu <= ETH_DATA_LEN) {
7754                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7755                      tp->bufmgr_config.mbuf_read_dma_low_water);
7756                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7757                      tp->bufmgr_config.mbuf_mac_rx_low_water);
7758                 tw32(BUFMGR_MB_HIGH_WATER,
7759                      tp->bufmgr_config.mbuf_high_water);
7760         } else {
7761                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7762                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7763                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7764                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7765                 tw32(BUFMGR_MB_HIGH_WATER,
7766                      tp->bufmgr_config.mbuf_high_water_jumbo);
7767         }
7768         tw32(BUFMGR_DMA_LOW_WATER,
7769              tp->bufmgr_config.dma_low_water);
7770         tw32(BUFMGR_DMA_HIGH_WATER,
7771              tp->bufmgr_config.dma_high_water);
7772
7773         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7774         for (i = 0; i < 2000; i++) {
7775                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7776                         break;
7777                 udelay(10);
7778         }
7779         if (i >= 2000) {
7780                 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
7781                 return -ENODEV;
7782         }
7783
7784         /* Setup replenish threshold. */
7785         val = tp->rx_pending / 8;
7786         if (val == 0)
7787                 val = 1;
7788         else if (val > tp->rx_std_max_post)
7789                 val = tp->rx_std_max_post;
7790         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7791                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7792                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7793
7794                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7795                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7796         }
7797
7798         tw32(RCVBDI_STD_THRESH, val);
7799
7800         /* Initialize TG3_BDINFO's at:
7801          *  RCVDBDI_STD_BD:     standard eth size rx ring
7802          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
7803          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
7804          *
7805          * like so:
7806          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
7807          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
7808          *                              ring attribute flags
7809          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
7810          *
7811          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7812          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7813          *
7814          * The size of each ring is fixed in the firmware, but the location is
7815          * configurable.
7816          */
7817         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7818              ((u64) tpr->rx_std_mapping >> 32));
7819         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7820              ((u64) tpr->rx_std_mapping & 0xffffffff));
7821         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
7822                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7823                      NIC_SRAM_RX_BUFFER_DESC);
7824
7825         /* Disable the mini ring */
7826         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7827                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7828                      BDINFO_FLAGS_DISABLED);
7829
7830         /* Program the jumbo buffer descriptor ring control
7831          * blocks on those devices that have them.
7832          */
7833         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7834             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7835                 /* Setup replenish threshold. */
7836                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7837
7838                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7839                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7840                              ((u64) tpr->rx_jmb_mapping >> 32));
7841                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7842                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7843                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7844                              (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7845                              BDINFO_FLAGS_USE_EXT_RECV);
7846                         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
7847                                 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7848                                      NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7849                 } else {
7850                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7851                              BDINFO_FLAGS_DISABLED);
7852                 }
7853
7854                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7855                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7856                         val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7857                               (RX_STD_MAX_SIZE << 2);
7858                 else
7859                         val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
7860         } else
7861                 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7862
7863         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7864
7865         tpr->rx_std_prod_idx = tp->rx_pending;
7866         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
7867
7868         tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7869                           tp->rx_jumbo_pending : 0;
7870         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
7871
7872         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7873             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7874                 tw32(STD_REPLENISH_LWM, 32);
7875                 tw32(JMB_REPLENISH_LWM, 16);
7876         }
7877
7878         tg3_rings_reset(tp);
7879
7880         /* Initialize MAC address and backoff seed. */
7881         __tg3_set_mac_addr(tp, 0);
7882
7883         /* MTU + ethernet header + FCS + optional VLAN tag */
7884         tw32(MAC_RX_MTU_SIZE,
7885              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7886
7887         /* The slot time is changed by tg3_setup_phy if we
7888          * run at gigabit with half duplex.
7889          */
7890         tw32(MAC_TX_LENGTHS,
7891              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7892              (6 << TX_LENGTHS_IPG_SHIFT) |
7893              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7894
7895         /* Receive rules. */
7896         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7897         tw32(RCVLPC_CONFIG, 0x0181);
7898
7899         /* Calculate RDMAC_MODE setting early, we need it to determine
7900          * the RCVLPC_STATE_ENABLE mask.
7901          */
7902         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7903                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7904                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7905                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7906                       RDMAC_MODE_LNGREAD_ENAB);
7907
7908         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7909                 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
7910
7911         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7912             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7913             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7914                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7915                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7916                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7917
7918         /* If statement applies to 5705 and 5750 PCI devices only */
7919         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7920              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7921             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7922                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7923                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7924                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7925                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7926                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7927                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7928                 }
7929         }
7930
7931         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7932                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7933
7934         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7935                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7936
7937         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
7938             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7939             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7940                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7941
7942         /* Receive/send statistics. */
7943         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7944                 val = tr32(RCVLPC_STATS_ENABLE);
7945                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7946                 tw32(RCVLPC_STATS_ENABLE, val);
7947         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7948                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7949                 val = tr32(RCVLPC_STATS_ENABLE);
7950                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7951                 tw32(RCVLPC_STATS_ENABLE, val);
7952         } else {
7953                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7954         }
7955         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7956         tw32(SNDDATAI_STATSENAB, 0xffffff);
7957         tw32(SNDDATAI_STATSCTRL,
7958              (SNDDATAI_SCTRL_ENABLE |
7959               SNDDATAI_SCTRL_FASTUPD));
7960
7961         /* Setup host coalescing engine. */
7962         tw32(HOSTCC_MODE, 0);
7963         for (i = 0; i < 2000; i++) {
7964                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7965                         break;
7966                 udelay(10);
7967         }
7968
7969         __tg3_set_coalesce(tp, &tp->coal);
7970
7971         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7972                 /* Status/statistics block address.  See tg3_timer,
7973                  * the tg3_periodic_fetch_stats call there, and
7974                  * tg3_get_stats to see how this works for 5705/5750 chips.
7975                  */
7976                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7977                      ((u64) tp->stats_mapping >> 32));
7978                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7979                      ((u64) tp->stats_mapping & 0xffffffff));
7980                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7981
7982                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7983
7984                 /* Clear statistics and status block memory areas */
7985                 for (i = NIC_SRAM_STATS_BLK;
7986                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7987                      i += sizeof(u32)) {
7988                         tg3_write_mem(tp, i, 0);
7989                         udelay(40);
7990                 }
7991         }
7992
7993         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7994
7995         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7996         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7997         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7998                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7999
8000         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8001                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
8002                 /* reset to prevent losing 1st rx packet intermittently */
8003                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8004                 udelay(10);
8005         }
8006
8007         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8008                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8009         else
8010                 tp->mac_mode = 0;
8011         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8012                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
8013         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8014             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8015             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8016                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8017         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8018         udelay(40);
8019
8020         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8021          * If TG3_FLG2_IS_NIC is zero, we should read the
8022          * register to preserve the GPIO settings for LOMs. The GPIOs,
8023          * whether used as inputs or outputs, are set by boot code after
8024          * reset.
8025          */
8026         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
8027                 u32 gpio_mask;
8028
8029                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8030                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8031                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8032
8033                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8034                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8035                                      GRC_LCLCTRL_GPIO_OUTPUT3;
8036
8037                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8038                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8039
8040                 tp->grc_local_ctrl &= ~gpio_mask;
8041                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8042
8043                 /* GPIO1 must be driven high for eeprom write protect */
8044                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8045                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8046                                                GRC_LCLCTRL_GPIO_OUTPUT1);
8047         }
8048         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8049         udelay(100);
8050
8051         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
8052                 val = tr32(MSGINT_MODE);
8053                 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8054                 tw32(MSGINT_MODE, val);
8055         }
8056
8057         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8058                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8059                 udelay(40);
8060         }
8061
8062         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8063                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8064                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8065                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8066                WDMAC_MODE_LNGREAD_ENAB);
8067
8068         /* If statement applies to 5705 and 5750 PCI devices only */
8069         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8070              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8071             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
8072                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8073                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8074                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8075                         /* nothing */
8076                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8077                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8078                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8079                         val |= WDMAC_MODE_RX_ACCEL;
8080                 }
8081         }
8082
8083         /* Enable host coalescing bug fix */
8084         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8085                 val |= WDMAC_MODE_STATUS_TAG_FIX;
8086
8087         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8088                 val |= WDMAC_MODE_BURST_ALL_DATA;
8089
8090         tw32_f(WDMAC_MODE, val);
8091         udelay(40);
8092
8093         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8094                 u16 pcix_cmd;
8095
8096                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8097                                      &pcix_cmd);
8098                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8099                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8100                         pcix_cmd |= PCI_X_CMD_READ_2K;
8101                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8102                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8103                         pcix_cmd |= PCI_X_CMD_READ_2K;
8104                 }
8105                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8106                                       pcix_cmd);
8107         }
8108
8109         tw32_f(RDMAC_MODE, rdmac_mode);
8110         udelay(40);
8111
8112         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8113         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8114                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8115
8116         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8117                 tw32(SNDDATAC_MODE,
8118                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8119         else
8120                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8121
8122         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8123         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8124         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8125         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8126         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8127                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8128         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8129         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8130                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8131         tw32(SNDBDI_MODE, val);
8132         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8133
8134         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8135                 err = tg3_load_5701_a0_firmware_fix(tp);
8136                 if (err)
8137                         return err;
8138         }
8139
8140         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8141                 err = tg3_load_tso_firmware(tp);
8142                 if (err)
8143                         return err;
8144         }
8145
8146         tp->tx_mode = TX_MODE_ENABLE;
8147         tw32_f(MAC_TX_MODE, tp->tx_mode);
8148         udelay(100);
8149
8150         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8151                 u32 reg = MAC_RSS_INDIR_TBL_0;
8152                 u8 *ent = (u8 *)&val;
8153
8154                 /* Setup the indirection table */
8155                 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8156                         int idx = i % sizeof(val);
8157
8158                         ent[idx] = i % (tp->irq_cnt - 1);
8159                         if (idx == sizeof(val) - 1) {
8160                                 tw32(reg, val);
8161                                 reg += 4;
8162                         }
8163                 }
8164
8165                 /* Setup the "secret" hash key. */
8166                 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8167                 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8168                 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8169                 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8170                 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8171                 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8172                 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8173                 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8174                 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8175                 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8176         }
8177
8178         tp->rx_mode = RX_MODE_ENABLE;
8179         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8180                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8181
8182         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8183                 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8184                                RX_MODE_RSS_ITBL_HASH_BITS_7 |
8185                                RX_MODE_RSS_IPV6_HASH_EN |
8186                                RX_MODE_RSS_TCP_IPV6_HASH_EN |
8187                                RX_MODE_RSS_IPV4_HASH_EN |
8188                                RX_MODE_RSS_TCP_IPV4_HASH_EN;
8189
8190         tw32_f(MAC_RX_MODE, tp->rx_mode);
8191         udelay(10);
8192
8193         tw32(MAC_LED_CTRL, tp->led_ctrl);
8194
8195         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8196         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8197                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8198                 udelay(10);
8199         }
8200         tw32_f(MAC_RX_MODE, tp->rx_mode);
8201         udelay(10);
8202
8203         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8204                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8205                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
8206                         /* Set drive transmission level to 1.2V  */
8207                         /* only if the signal pre-emphasis bit is not set  */
8208                         val = tr32(MAC_SERDES_CFG);
8209                         val &= 0xfffff000;
8210                         val |= 0x880;
8211                         tw32(MAC_SERDES_CFG, val);
8212                 }
8213                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8214                         tw32(MAC_SERDES_CFG, 0x616000);
8215         }
8216
8217         /* Prevent chip from dropping frames when flow control
8218          * is enabled.
8219          */
8220         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8221                 val = 1;
8222         else
8223                 val = 2;
8224         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8225
8226         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8227             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8228                 /* Use hardware link auto-negotiation */
8229                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8230         }
8231
8232         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8233             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8234                 u32 tmp;
8235
8236                 tmp = tr32(SERDES_RX_CTRL);
8237                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8238                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8239                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8240                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8241         }
8242
8243         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8244                 if (tp->link_config.phy_is_low_power) {
8245                         tp->link_config.phy_is_low_power = 0;
8246                         tp->link_config.speed = tp->link_config.orig_speed;
8247                         tp->link_config.duplex = tp->link_config.orig_duplex;
8248                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
8249                 }
8250
8251                 err = tg3_setup_phy(tp, 0);
8252                 if (err)
8253                         return err;
8254
8255                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8256                     !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
8257                         u32 tmp;
8258
8259                         /* Clear CRC stats. */
8260                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8261                                 tg3_writephy(tp, MII_TG3_TEST1,
8262                                              tmp | MII_TG3_TEST1_CRC_EN);
8263                                 tg3_readphy(tp, 0x14, &tmp);
8264                         }
8265                 }
8266         }
8267
8268         __tg3_set_rx_mode(tp->dev);
8269
8270         /* Initialize receive rules. */
8271         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
8272         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8273         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
8274         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8275
8276         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8277             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8278                 limit = 8;
8279         else
8280                 limit = 16;
8281         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8282                 limit -= 4;
8283         switch (limit) {
8284         case 16:
8285                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
8286         case 15:
8287                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
8288         case 14:
8289                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
8290         case 13:
8291                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
8292         case 12:
8293                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
8294         case 11:
8295                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
8296         case 10:
8297                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
8298         case 9:
8299                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
8300         case 8:
8301                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
8302         case 7:
8303                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
8304         case 6:
8305                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
8306         case 5:
8307                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
8308         case 4:
8309                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
8310         case 3:
8311                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
8312         case 2:
8313         case 1:
8314
8315         default:
8316                 break;
8317         }
8318
8319         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8320                 /* Write our heartbeat update interval to APE. */
8321                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8322                                 APE_HOST_HEARTBEAT_INT_DISABLE);
8323
8324         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8325
8326         return 0;
8327 }
8328
8329 /* Called at device open time to get the chip ready for
8330  * packet processing.  Invoked with tp->lock held.
8331  */
8332 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8333 {
8334         tg3_switch_clocks(tp);
8335
8336         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8337
8338         return tg3_reset_hw(tp, reset_phy);
8339 }
8340
8341 #define TG3_STAT_ADD32(PSTAT, REG) \
8342 do {    u32 __val = tr32(REG); \
8343         (PSTAT)->low += __val; \
8344         if ((PSTAT)->low < __val) \
8345                 (PSTAT)->high += 1; \
8346 } while (0)
8347
8348 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8349 {
8350         struct tg3_hw_stats *sp = tp->hw_stats;
8351
8352         if (!netif_carrier_ok(tp->dev))
8353                 return;
8354
8355         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8356         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8357         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8358         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8359         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8360         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8361         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8362         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8363         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8364         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8365         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8366         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8367         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8368
8369         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8370         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8371         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8372         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8373         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8374         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8375         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8376         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8377         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8378         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8379         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8380         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8381         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8382         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8383
8384         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8385         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8386         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8387 }
8388
8389 static void tg3_timer(unsigned long __opaque)
8390 {
8391         struct tg3 *tp = (struct tg3 *) __opaque;
8392
8393         if (tp->irq_sync)
8394                 goto restart_timer;
8395
8396         spin_lock(&tp->lock);
8397
8398         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8399                 /* All of this garbage is because when using non-tagged
8400                  * IRQ status the mailbox/status_block protocol the chip
8401                  * uses with the cpu is race prone.
8402                  */
8403                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8404                         tw32(GRC_LOCAL_CTRL,
8405                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8406                 } else {
8407                         tw32(HOSTCC_MODE, tp->coalesce_mode |
8408                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8409                 }
8410
8411                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8412                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8413                         spin_unlock(&tp->lock);
8414                         schedule_work(&tp->reset_task);
8415                         return;
8416                 }
8417         }
8418
8419         /* This part only runs once per second. */
8420         if (!--tp->timer_counter) {
8421                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8422                         tg3_periodic_fetch_stats(tp);
8423
8424                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8425                         u32 mac_stat;
8426                         int phy_event;
8427
8428                         mac_stat = tr32(MAC_STATUS);
8429
8430                         phy_event = 0;
8431                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8432                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8433                                         phy_event = 1;
8434                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8435                                 phy_event = 1;
8436
8437                         if (phy_event)
8438                                 tg3_setup_phy(tp, 0);
8439                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8440                         u32 mac_stat = tr32(MAC_STATUS);
8441                         int need_setup = 0;
8442
8443                         if (netif_carrier_ok(tp->dev) &&
8444                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8445                                 need_setup = 1;
8446                         }
8447                         if (! netif_carrier_ok(tp->dev) &&
8448                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
8449                                          MAC_STATUS_SIGNAL_DET))) {
8450                                 need_setup = 1;
8451                         }
8452                         if (need_setup) {
8453                                 if (!tp->serdes_counter) {
8454                                         tw32_f(MAC_MODE,
8455                                              (tp->mac_mode &
8456                                               ~MAC_MODE_PORT_MODE_MASK));
8457                                         udelay(40);
8458                                         tw32_f(MAC_MODE, tp->mac_mode);
8459                                         udelay(40);
8460                                 }
8461                                 tg3_setup_phy(tp, 0);
8462                         }
8463                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8464                         tg3_serdes_parallel_detect(tp);
8465
8466                 tp->timer_counter = tp->timer_multiplier;
8467         }
8468
8469         /* Heartbeat is only sent once every 2 seconds.
8470          *
8471          * The heartbeat is to tell the ASF firmware that the host
8472          * driver is still alive.  In the event that the OS crashes,
8473          * ASF needs to reset the hardware to free up the FIFO space
8474          * that may be filled with rx packets destined for the host.
8475          * If the FIFO is full, ASF will no longer function properly.
8476          *
8477          * Unintended resets have been reported on real time kernels
8478          * where the timer doesn't run on time.  Netpoll will also have
8479          * same problem.
8480          *
8481          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8482          * to check the ring condition when the heartbeat is expiring
8483          * before doing the reset.  This will prevent most unintended
8484          * resets.
8485          */
8486         if (!--tp->asf_counter) {
8487                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8488                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8489                         tg3_wait_for_event_ack(tp);
8490
8491                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8492                                       FWCMD_NICDRV_ALIVE3);
8493                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8494                         /* 5 seconds timeout */
8495                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
8496
8497                         tg3_generate_fw_event(tp);
8498                 }
8499                 tp->asf_counter = tp->asf_multiplier;
8500         }
8501
8502         spin_unlock(&tp->lock);
8503
8504 restart_timer:
8505         tp->timer.expires = jiffies + tp->timer_offset;
8506         add_timer(&tp->timer);
8507 }
8508
8509 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8510 {
8511         irq_handler_t fn;
8512         unsigned long flags;
8513         char *name;
8514         struct tg3_napi *tnapi = &tp->napi[irq_num];
8515
8516         if (tp->irq_cnt == 1)
8517                 name = tp->dev->name;
8518         else {
8519                 name = &tnapi->irq_lbl[0];
8520                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8521                 name[IFNAMSIZ-1] = 0;
8522         }
8523
8524         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8525                 fn = tg3_msi;
8526                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8527                         fn = tg3_msi_1shot;
8528                 flags = IRQF_SAMPLE_RANDOM;
8529         } else {
8530                 fn = tg3_interrupt;
8531                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8532                         fn = tg3_interrupt_tagged;
8533                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8534         }
8535
8536         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8537 }
8538
8539 static int tg3_test_interrupt(struct tg3 *tp)
8540 {
8541         struct tg3_napi *tnapi = &tp->napi[0];
8542         struct net_device *dev = tp->dev;
8543         int err, i, intr_ok = 0;
8544         u32 val;
8545
8546         if (!netif_running(dev))
8547                 return -ENODEV;
8548
8549         tg3_disable_ints(tp);
8550
8551         free_irq(tnapi->irq_vec, tnapi);
8552
8553         /*
8554          * Turn off MSI one shot mode.  Otherwise this test has no
8555          * observable way to know whether the interrupt was delivered.
8556          */
8557         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8558              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
8559             (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8560                 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8561                 tw32(MSGINT_MODE, val);
8562         }
8563
8564         err = request_irq(tnapi->irq_vec, tg3_test_isr,
8565                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8566         if (err)
8567                 return err;
8568
8569         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8570         tg3_enable_ints(tp);
8571
8572         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8573                tnapi->coal_now);
8574
8575         for (i = 0; i < 5; i++) {
8576                 u32 int_mbox, misc_host_ctrl;
8577
8578                 int_mbox = tr32_mailbox(tnapi->int_mbox);
8579                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8580
8581                 if ((int_mbox != 0) ||
8582                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8583                         intr_ok = 1;
8584                         break;
8585                 }
8586
8587                 msleep(10);
8588         }
8589
8590         tg3_disable_ints(tp);
8591
8592         free_irq(tnapi->irq_vec, tnapi);
8593
8594         err = tg3_request_irq(tp, 0);
8595
8596         if (err)
8597                 return err;
8598
8599         if (intr_ok) {
8600                 /* Reenable MSI one shot mode. */
8601                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8602                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
8603                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8604                         val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8605                         tw32(MSGINT_MODE, val);
8606                 }
8607                 return 0;
8608         }
8609
8610         return -EIO;
8611 }
8612
8613 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8614  * successfully restored
8615  */
8616 static int tg3_test_msi(struct tg3 *tp)
8617 {
8618         int err;
8619         u16 pci_cmd;
8620
8621         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8622                 return 0;
8623
8624         /* Turn off SERR reporting in case MSI terminates with Master
8625          * Abort.
8626          */
8627         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8628         pci_write_config_word(tp->pdev, PCI_COMMAND,
8629                               pci_cmd & ~PCI_COMMAND_SERR);
8630
8631         err = tg3_test_interrupt(tp);
8632
8633         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8634
8635         if (!err)
8636                 return 0;
8637
8638         /* other failures */
8639         if (err != -EIO)
8640                 return err;
8641
8642         /* MSI test failed, go back to INTx mode */
8643         netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
8644                     "to INTx mode. Please report this failure to the PCI "
8645                     "maintainer and include system chipset information\n");
8646
8647         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8648
8649         pci_disable_msi(tp->pdev);
8650
8651         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8652
8653         err = tg3_request_irq(tp, 0);
8654         if (err)
8655                 return err;
8656
8657         /* Need to reset the chip because the MSI cycle may have terminated
8658          * with Master Abort.
8659          */
8660         tg3_full_lock(tp, 1);
8661
8662         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8663         err = tg3_init_hw(tp, 1);
8664
8665         tg3_full_unlock(tp);
8666
8667         if (err)
8668                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8669
8670         return err;
8671 }
8672
8673 static int tg3_request_firmware(struct tg3 *tp)
8674 {
8675         const __be32 *fw_data;
8676
8677         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8678                 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
8679                            tp->fw_needed);
8680                 return -ENOENT;
8681         }
8682
8683         fw_data = (void *)tp->fw->data;
8684
8685         /* Firmware blob starts with version numbers, followed by
8686          * start address and _full_ length including BSS sections
8687          * (which must be longer than the actual data, of course
8688          */
8689
8690         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
8691         if (tp->fw_len < (tp->fw->size - 12)) {
8692                 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
8693                            tp->fw_len, tp->fw_needed);
8694                 release_firmware(tp->fw);
8695                 tp->fw = NULL;
8696                 return -EINVAL;
8697         }
8698
8699         /* We no longer need firmware; we have it. */
8700         tp->fw_needed = NULL;
8701         return 0;
8702 }
8703
8704 static bool tg3_enable_msix(struct tg3 *tp)
8705 {
8706         int i, rc, cpus = num_online_cpus();
8707         struct msix_entry msix_ent[tp->irq_max];
8708
8709         if (cpus == 1)
8710                 /* Just fallback to the simpler MSI mode. */
8711                 return false;
8712
8713         /*
8714          * We want as many rx rings enabled as there are cpus.
8715          * The first MSIX vector only deals with link interrupts, etc,
8716          * so we add one to the number of vectors we are requesting.
8717          */
8718         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8719
8720         for (i = 0; i < tp->irq_max; i++) {
8721                 msix_ent[i].entry  = i;
8722                 msix_ent[i].vector = 0;
8723         }
8724
8725         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8726         if (rc != 0) {
8727                 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8728                         return false;
8729                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8730                         return false;
8731                 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
8732                               tp->irq_cnt, rc);
8733                 tp->irq_cnt = rc;
8734         }
8735
8736         tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8737
8738         for (i = 0; i < tp->irq_max; i++)
8739                 tp->napi[i].irq_vec = msix_ent[i].vector;
8740
8741         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8742                 tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
8743                 tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8744         } else
8745                 tp->dev->real_num_tx_queues = 1;
8746
8747         return true;
8748 }
8749
8750 static void tg3_ints_init(struct tg3 *tp)
8751 {
8752         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8753             !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8754                 /* All MSI supporting chips should support tagged
8755                  * status.  Assert that this is the case.
8756                  */
8757                 netdev_warn(tp->dev,
8758                             "MSI without TAGGED_STATUS? Not using MSI\n");
8759                 goto defcfg;
8760         }
8761
8762         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8763                 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8764         else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8765                  pci_enable_msi(tp->pdev) == 0)
8766                 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8767
8768         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8769                 u32 msi_mode = tr32(MSGINT_MODE);
8770                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8771                         msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8772                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8773         }
8774 defcfg:
8775         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8776                 tp->irq_cnt = 1;
8777                 tp->napi[0].irq_vec = tp->pdev->irq;
8778                 tp->dev->real_num_tx_queues = 1;
8779         }
8780 }
8781
8782 static void tg3_ints_fini(struct tg3 *tp)
8783 {
8784         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8785                 pci_disable_msix(tp->pdev);
8786         else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8787                 pci_disable_msi(tp->pdev);
8788         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8789         tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
8790 }
8791
8792 static int tg3_open(struct net_device *dev)
8793 {
8794         struct tg3 *tp = netdev_priv(dev);
8795         int i, err;
8796
8797         if (tp->fw_needed) {
8798                 err = tg3_request_firmware(tp);
8799                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8800                         if (err)
8801                                 return err;
8802                 } else if (err) {
8803                         netdev_warn(tp->dev, "TSO capability disabled\n");
8804                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8805                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8806                         netdev_notice(tp->dev, "TSO capability restored\n");
8807                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8808                 }
8809         }
8810
8811         netif_carrier_off(tp->dev);
8812
8813         err = tg3_set_power_state(tp, PCI_D0);
8814         if (err)
8815                 return err;
8816
8817         tg3_full_lock(tp, 0);
8818
8819         tg3_disable_ints(tp);
8820         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8821
8822         tg3_full_unlock(tp);
8823
8824         /*
8825          * Setup interrupts first so we know how
8826          * many NAPI resources to allocate
8827          */
8828         tg3_ints_init(tp);
8829
8830         /* The placement of this call is tied
8831          * to the setup and use of Host TX descriptors.
8832          */
8833         err = tg3_alloc_consistent(tp);
8834         if (err)
8835                 goto err_out1;
8836
8837         tg3_napi_enable(tp);
8838
8839         for (i = 0; i < tp->irq_cnt; i++) {
8840                 struct tg3_napi *tnapi = &tp->napi[i];
8841                 err = tg3_request_irq(tp, i);
8842                 if (err) {
8843                         for (i--; i >= 0; i--)
8844                                 free_irq(tnapi->irq_vec, tnapi);
8845                         break;
8846                 }
8847         }
8848
8849         if (err)
8850                 goto err_out2;
8851
8852         tg3_full_lock(tp, 0);
8853
8854         err = tg3_init_hw(tp, 1);
8855         if (err) {
8856                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8857                 tg3_free_rings(tp);
8858         } else {
8859                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8860                         tp->timer_offset = HZ;
8861                 else
8862                         tp->timer_offset = HZ / 10;
8863
8864                 BUG_ON(tp->timer_offset > HZ);
8865                 tp->timer_counter = tp->timer_multiplier =
8866                         (HZ / tp->timer_offset);
8867                 tp->asf_counter = tp->asf_multiplier =
8868                         ((HZ / tp->timer_offset) * 2);
8869
8870                 init_timer(&tp->timer);
8871                 tp->timer.expires = jiffies + tp->timer_offset;
8872                 tp->timer.data = (unsigned long) tp;
8873                 tp->timer.function = tg3_timer;
8874         }
8875
8876         tg3_full_unlock(tp);
8877
8878         if (err)
8879                 goto err_out3;
8880
8881         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8882                 err = tg3_test_msi(tp);
8883
8884                 if (err) {
8885                         tg3_full_lock(tp, 0);
8886                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8887                         tg3_free_rings(tp);
8888                         tg3_full_unlock(tp);
8889
8890                         goto err_out2;
8891                 }
8892
8893                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8894                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 &&
8895                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8896                     (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8897                         u32 val = tr32(PCIE_TRANSACTION_CFG);
8898
8899                         tw32(PCIE_TRANSACTION_CFG,
8900                              val | PCIE_TRANS_CFG_1SHOT_MSI);
8901                 }
8902         }
8903
8904         tg3_phy_start(tp);
8905
8906         tg3_full_lock(tp, 0);
8907
8908         add_timer(&tp->timer);
8909         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8910         tg3_enable_ints(tp);
8911
8912         tg3_full_unlock(tp);
8913
8914         netif_tx_start_all_queues(dev);
8915
8916         return 0;
8917
8918 err_out3:
8919         for (i = tp->irq_cnt - 1; i >= 0; i--) {
8920                 struct tg3_napi *tnapi = &tp->napi[i];
8921                 free_irq(tnapi->irq_vec, tnapi);
8922         }
8923
8924 err_out2:
8925         tg3_napi_disable(tp);
8926         tg3_free_consistent(tp);
8927
8928 err_out1:
8929         tg3_ints_fini(tp);
8930         return err;
8931 }
8932
8933 #if 0
8934 /*static*/ void tg3_dump_state(struct tg3 *tp)
8935 {
8936         u32 val32, val32_2, val32_3, val32_4, val32_5;
8937         u16 val16;
8938         int i;
8939         struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
8940
8941         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8942         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8943         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8944                val16, val32);
8945
8946         /* MAC block */
8947         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8948                tr32(MAC_MODE), tr32(MAC_STATUS));
8949         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8950                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8951         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8952                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8953         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8954                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8955
8956         /* Send data initiator control block */
8957         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8958                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8959         printk("       SNDDATAI_STATSCTRL[%08x]\n",
8960                tr32(SNDDATAI_STATSCTRL));
8961
8962         /* Send data completion control block */
8963         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8964
8965         /* Send BD ring selector block */
8966         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8967                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8968
8969         /* Send BD initiator control block */
8970         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8971                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8972
8973         /* Send BD completion control block */
8974         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8975
8976         /* Receive list placement control block */
8977         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8978                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8979         printk("       RCVLPC_STATSCTRL[%08x]\n",
8980                tr32(RCVLPC_STATSCTRL));
8981
8982         /* Receive data and receive BD initiator control block */
8983         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8984                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8985
8986         /* Receive data completion control block */
8987         printk("DEBUG: RCVDCC_MODE[%08x]\n",
8988                tr32(RCVDCC_MODE));
8989
8990         /* Receive BD initiator control block */
8991         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8992                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8993
8994         /* Receive BD completion control block */
8995         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8996                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8997
8998         /* Receive list selector control block */
8999         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
9000                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
9001
9002         /* Mbuf cluster free block */
9003         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
9004                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
9005
9006         /* Host coalescing control block */
9007         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
9008                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
9009         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
9010                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
9011                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
9012         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
9013                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
9014                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
9015         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
9016                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
9017         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
9018                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
9019
9020         /* Memory arbiter control block */
9021         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
9022                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
9023
9024         /* Buffer manager control block */
9025         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
9026                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
9027         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
9028                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
9029         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
9030                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
9031                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
9032                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
9033
9034         /* Read DMA control block */
9035         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
9036                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
9037
9038         /* Write DMA control block */
9039         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
9040                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
9041
9042         /* DMA completion block */
9043         printk("DEBUG: DMAC_MODE[%08x]\n",
9044                tr32(DMAC_MODE));
9045
9046         /* GRC block */
9047         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
9048                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
9049         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
9050                tr32(GRC_LOCAL_CTRL));
9051
9052         /* TG3_BDINFOs */
9053         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
9054                tr32(RCVDBDI_JUMBO_BD + 0x0),
9055                tr32(RCVDBDI_JUMBO_BD + 0x4),
9056                tr32(RCVDBDI_JUMBO_BD + 0x8),
9057                tr32(RCVDBDI_JUMBO_BD + 0xc));
9058         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
9059                tr32(RCVDBDI_STD_BD + 0x0),
9060                tr32(RCVDBDI_STD_BD + 0x4),
9061                tr32(RCVDBDI_STD_BD + 0x8),
9062                tr32(RCVDBDI_STD_BD + 0xc));
9063         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
9064                tr32(RCVDBDI_MINI_BD + 0x0),
9065                tr32(RCVDBDI_MINI_BD + 0x4),
9066                tr32(RCVDBDI_MINI_BD + 0x8),
9067                tr32(RCVDBDI_MINI_BD + 0xc));
9068
9069         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
9070         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
9071         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
9072         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
9073         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
9074                val32, val32_2, val32_3, val32_4);
9075
9076         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
9077         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
9078         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
9079         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
9080         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
9081                val32, val32_2, val32_3, val32_4);
9082
9083         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
9084         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
9085         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
9086         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
9087         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
9088         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
9089                val32, val32_2, val32_3, val32_4, val32_5);
9090
9091         /* SW status block */
9092         printk(KERN_DEBUG
9093          "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
9094                sblk->status,
9095                sblk->status_tag,
9096                sblk->rx_jumbo_consumer,
9097                sblk->rx_consumer,
9098                sblk->rx_mini_consumer,
9099                sblk->idx[0].rx_producer,
9100                sblk->idx[0].tx_consumer);
9101
9102         /* SW statistics block */
9103         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
9104                ((u32 *)tp->hw_stats)[0],
9105                ((u32 *)tp->hw_stats)[1],
9106                ((u32 *)tp->hw_stats)[2],
9107                ((u32 *)tp->hw_stats)[3]);
9108
9109         /* Mailboxes */
9110         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
9111                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
9112                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
9113                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
9114                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
9115
9116         /* NIC side send descriptors. */
9117         for (i = 0; i < 6; i++) {
9118                 unsigned long txd;
9119
9120                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
9121                         + (i * sizeof(struct tg3_tx_buffer_desc));
9122                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
9123                        i,
9124                        readl(txd + 0x0), readl(txd + 0x4),
9125                        readl(txd + 0x8), readl(txd + 0xc));
9126         }
9127
9128         /* NIC side RX descriptors. */
9129         for (i = 0; i < 6; i++) {
9130                 unsigned long rxd;
9131
9132                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
9133                         + (i * sizeof(struct tg3_rx_buffer_desc));
9134                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
9135                        i,
9136                        readl(rxd + 0x0), readl(rxd + 0x4),
9137                        readl(rxd + 0x8), readl(rxd + 0xc));
9138                 rxd += (4 * sizeof(u32));
9139                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
9140                        i,
9141                        readl(rxd + 0x0), readl(rxd + 0x4),
9142                        readl(rxd + 0x8), readl(rxd + 0xc));
9143         }
9144
9145         for (i = 0; i < 6; i++) {
9146                 unsigned long rxd;
9147
9148                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
9149                         + (i * sizeof(struct tg3_rx_buffer_desc));
9150                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
9151                        i,
9152                        readl(rxd + 0x0), readl(rxd + 0x4),
9153                        readl(rxd + 0x8), readl(rxd + 0xc));
9154                 rxd += (4 * sizeof(u32));
9155                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
9156                        i,
9157                        readl(rxd + 0x0), readl(rxd + 0x4),
9158                        readl(rxd + 0x8), readl(rxd + 0xc));
9159         }
9160 }
9161 #endif
9162
9163 static struct net_device_stats *tg3_get_stats(struct net_device *);
9164 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9165
9166 static int tg3_close(struct net_device *dev)
9167 {
9168         int i;
9169         struct tg3 *tp = netdev_priv(dev);
9170
9171         tg3_napi_disable(tp);
9172         cancel_work_sync(&tp->reset_task);
9173
9174         netif_tx_stop_all_queues(dev);
9175
9176         del_timer_sync(&tp->timer);
9177
9178         tg3_phy_stop(tp);
9179
9180         tg3_full_lock(tp, 1);
9181 #if 0
9182         tg3_dump_state(tp);
9183 #endif
9184
9185         tg3_disable_ints(tp);
9186
9187         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9188         tg3_free_rings(tp);
9189         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9190
9191         tg3_full_unlock(tp);
9192
9193         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9194                 struct tg3_napi *tnapi = &tp->napi[i];
9195                 free_irq(tnapi->irq_vec, tnapi);
9196         }
9197
9198         tg3_ints_fini(tp);
9199
9200         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
9201                sizeof(tp->net_stats_prev));
9202         memcpy(&tp->estats_prev, tg3_get_estats(tp),
9203                sizeof(tp->estats_prev));
9204
9205         tg3_free_consistent(tp);
9206
9207         tg3_set_power_state(tp, PCI_D3hot);
9208
9209         netif_carrier_off(tp->dev);
9210
9211         return 0;
9212 }
9213
9214 static inline unsigned long get_stat64(tg3_stat64_t *val)
9215 {
9216         unsigned long ret;
9217
9218 #if (BITS_PER_LONG == 32)
9219         ret = val->low;
9220 #else
9221         ret = ((u64)val->high << 32) | ((u64)val->low);
9222 #endif
9223         return ret;
9224 }
9225
9226 static inline u64 get_estat64(tg3_stat64_t *val)
9227 {
9228        return ((u64)val->high << 32) | ((u64)val->low);
9229 }
9230
9231 static unsigned long calc_crc_errors(struct tg3 *tp)
9232 {
9233         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9234
9235         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9236             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9237              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9238                 u32 val;
9239
9240                 spin_lock_bh(&tp->lock);
9241                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9242                         tg3_writephy(tp, MII_TG3_TEST1,
9243                                      val | MII_TG3_TEST1_CRC_EN);
9244                         tg3_readphy(tp, 0x14, &val);
9245                 } else
9246                         val = 0;
9247                 spin_unlock_bh(&tp->lock);
9248
9249                 tp->phy_crc_errors += val;
9250
9251                 return tp->phy_crc_errors;
9252         }
9253
9254         return get_stat64(&hw_stats->rx_fcs_errors);
9255 }
9256
9257 #define ESTAT_ADD(member) \
9258         estats->member =        old_estats->member + \
9259                                 get_estat64(&hw_stats->member)
9260
9261 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9262 {
9263         struct tg3_ethtool_stats *estats = &tp->estats;
9264         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9265         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9266
9267         if (!hw_stats)
9268                 return old_estats;
9269
9270         ESTAT_ADD(rx_octets);
9271         ESTAT_ADD(rx_fragments);
9272         ESTAT_ADD(rx_ucast_packets);
9273         ESTAT_ADD(rx_mcast_packets);
9274         ESTAT_ADD(rx_bcast_packets);
9275         ESTAT_ADD(rx_fcs_errors);
9276         ESTAT_ADD(rx_align_errors);
9277         ESTAT_ADD(rx_xon_pause_rcvd);
9278         ESTAT_ADD(rx_xoff_pause_rcvd);
9279         ESTAT_ADD(rx_mac_ctrl_rcvd);
9280         ESTAT_ADD(rx_xoff_entered);
9281         ESTAT_ADD(rx_frame_too_long_errors);
9282         ESTAT_ADD(rx_jabbers);
9283         ESTAT_ADD(rx_undersize_packets);
9284         ESTAT_ADD(rx_in_length_errors);
9285         ESTAT_ADD(rx_out_length_errors);
9286         ESTAT_ADD(rx_64_or_less_octet_packets);
9287         ESTAT_ADD(rx_65_to_127_octet_packets);
9288         ESTAT_ADD(rx_128_to_255_octet_packets);
9289         ESTAT_ADD(rx_256_to_511_octet_packets);
9290         ESTAT_ADD(rx_512_to_1023_octet_packets);
9291         ESTAT_ADD(rx_1024_to_1522_octet_packets);
9292         ESTAT_ADD(rx_1523_to_2047_octet_packets);
9293         ESTAT_ADD(rx_2048_to_4095_octet_packets);
9294         ESTAT_ADD(rx_4096_to_8191_octet_packets);
9295         ESTAT_ADD(rx_8192_to_9022_octet_packets);
9296
9297         ESTAT_ADD(tx_octets);
9298         ESTAT_ADD(tx_collisions);
9299         ESTAT_ADD(tx_xon_sent);
9300         ESTAT_ADD(tx_xoff_sent);
9301         ESTAT_ADD(tx_flow_control);
9302         ESTAT_ADD(tx_mac_errors);
9303         ESTAT_ADD(tx_single_collisions);
9304         ESTAT_ADD(tx_mult_collisions);
9305         ESTAT_ADD(tx_deferred);
9306         ESTAT_ADD(tx_excessive_collisions);
9307         ESTAT_ADD(tx_late_collisions);
9308         ESTAT_ADD(tx_collide_2times);
9309         ESTAT_ADD(tx_collide_3times);
9310         ESTAT_ADD(tx_collide_4times);
9311         ESTAT_ADD(tx_collide_5times);
9312         ESTAT_ADD(tx_collide_6times);
9313         ESTAT_ADD(tx_collide_7times);
9314         ESTAT_ADD(tx_collide_8times);
9315         ESTAT_ADD(tx_collide_9times);
9316         ESTAT_ADD(tx_collide_10times);
9317         ESTAT_ADD(tx_collide_11times);
9318         ESTAT_ADD(tx_collide_12times);
9319         ESTAT_ADD(tx_collide_13times);
9320         ESTAT_ADD(tx_collide_14times);
9321         ESTAT_ADD(tx_collide_15times);
9322         ESTAT_ADD(tx_ucast_packets);
9323         ESTAT_ADD(tx_mcast_packets);
9324         ESTAT_ADD(tx_bcast_packets);
9325         ESTAT_ADD(tx_carrier_sense_errors);
9326         ESTAT_ADD(tx_discards);
9327         ESTAT_ADD(tx_errors);
9328
9329         ESTAT_ADD(dma_writeq_full);
9330         ESTAT_ADD(dma_write_prioq_full);
9331         ESTAT_ADD(rxbds_empty);
9332         ESTAT_ADD(rx_discards);
9333         ESTAT_ADD(rx_errors);
9334         ESTAT_ADD(rx_threshold_hit);
9335
9336         ESTAT_ADD(dma_readq_full);
9337         ESTAT_ADD(dma_read_prioq_full);
9338         ESTAT_ADD(tx_comp_queue_full);
9339
9340         ESTAT_ADD(ring_set_send_prod_index);
9341         ESTAT_ADD(ring_status_update);
9342         ESTAT_ADD(nic_irqs);
9343         ESTAT_ADD(nic_avoided_irqs);
9344         ESTAT_ADD(nic_tx_threshold_hit);
9345
9346         return estats;
9347 }
9348
9349 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
9350 {
9351         struct tg3 *tp = netdev_priv(dev);
9352         struct net_device_stats *stats = &tp->net_stats;
9353         struct net_device_stats *old_stats = &tp->net_stats_prev;
9354         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9355
9356         if (!hw_stats)
9357                 return old_stats;
9358
9359         stats->rx_packets = old_stats->rx_packets +
9360                 get_stat64(&hw_stats->rx_ucast_packets) +
9361                 get_stat64(&hw_stats->rx_mcast_packets) +
9362                 get_stat64(&hw_stats->rx_bcast_packets);
9363
9364         stats->tx_packets = old_stats->tx_packets +
9365                 get_stat64(&hw_stats->tx_ucast_packets) +
9366                 get_stat64(&hw_stats->tx_mcast_packets) +
9367                 get_stat64(&hw_stats->tx_bcast_packets);
9368
9369         stats->rx_bytes = old_stats->rx_bytes +
9370                 get_stat64(&hw_stats->rx_octets);
9371         stats->tx_bytes = old_stats->tx_bytes +
9372                 get_stat64(&hw_stats->tx_octets);
9373
9374         stats->rx_errors = old_stats->rx_errors +
9375                 get_stat64(&hw_stats->rx_errors);
9376         stats->tx_errors = old_stats->tx_errors +
9377                 get_stat64(&hw_stats->tx_errors) +
9378                 get_stat64(&hw_stats->tx_mac_errors) +
9379                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9380                 get_stat64(&hw_stats->tx_discards);
9381
9382         stats->multicast = old_stats->multicast +
9383                 get_stat64(&hw_stats->rx_mcast_packets);
9384         stats->collisions = old_stats->collisions +
9385                 get_stat64(&hw_stats->tx_collisions);
9386
9387         stats->rx_length_errors = old_stats->rx_length_errors +
9388                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9389                 get_stat64(&hw_stats->rx_undersize_packets);
9390
9391         stats->rx_over_errors = old_stats->rx_over_errors +
9392                 get_stat64(&hw_stats->rxbds_empty);
9393         stats->rx_frame_errors = old_stats->rx_frame_errors +
9394                 get_stat64(&hw_stats->rx_align_errors);
9395         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9396                 get_stat64(&hw_stats->tx_discards);
9397         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9398                 get_stat64(&hw_stats->tx_carrier_sense_errors);
9399
9400         stats->rx_crc_errors = old_stats->rx_crc_errors +
9401                 calc_crc_errors(tp);
9402
9403         stats->rx_missed_errors = old_stats->rx_missed_errors +
9404                 get_stat64(&hw_stats->rx_discards);
9405
9406         return stats;
9407 }
9408
9409 static inline u32 calc_crc(unsigned char *buf, int len)
9410 {
9411         u32 reg;
9412         u32 tmp;
9413         int j, k;
9414
9415         reg = 0xffffffff;
9416
9417         for (j = 0; j < len; j++) {
9418                 reg ^= buf[j];
9419
9420                 for (k = 0; k < 8; k++) {
9421                         tmp = reg & 0x01;
9422
9423                         reg >>= 1;
9424
9425                         if (tmp) {
9426                                 reg ^= 0xedb88320;
9427                         }
9428                 }
9429         }
9430
9431         return ~reg;
9432 }
9433
9434 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9435 {
9436         /* accept or reject all multicast frames */
9437         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9438         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9439         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9440         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9441 }
9442
9443 static void __tg3_set_rx_mode(struct net_device *dev)
9444 {
9445         struct tg3 *tp = netdev_priv(dev);
9446         u32 rx_mode;
9447
9448         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9449                                   RX_MODE_KEEP_VLAN_TAG);
9450
9451         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9452          * flag clear.
9453          */
9454 #if TG3_VLAN_TAG_USED
9455         if (!tp->vlgrp &&
9456             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9457                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9458 #else
9459         /* By definition, VLAN is disabled always in this
9460          * case.
9461          */
9462         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9463                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9464 #endif
9465
9466         if (dev->flags & IFF_PROMISC) {
9467                 /* Promiscuous mode. */
9468                 rx_mode |= RX_MODE_PROMISC;
9469         } else if (dev->flags & IFF_ALLMULTI) {
9470                 /* Accept all multicast. */
9471                 tg3_set_multi (tp, 1);
9472         } else if (netdev_mc_empty(dev)) {
9473                 /* Reject all multicast. */
9474                 tg3_set_multi (tp, 0);
9475         } else {
9476                 /* Accept one or more multicast(s). */
9477                 struct netdev_hw_addr *ha;
9478                 u32 mc_filter[4] = { 0, };
9479                 u32 regidx;
9480                 u32 bit;
9481                 u32 crc;
9482
9483                 netdev_for_each_mc_addr(ha, dev) {
9484                         crc = calc_crc(ha->addr, ETH_ALEN);
9485                         bit = ~crc & 0x7f;
9486                         regidx = (bit & 0x60) >> 5;
9487                         bit &= 0x1f;
9488                         mc_filter[regidx] |= (1 << bit);
9489                 }
9490
9491                 tw32(MAC_HASH_REG_0, mc_filter[0]);
9492                 tw32(MAC_HASH_REG_1, mc_filter[1]);
9493                 tw32(MAC_HASH_REG_2, mc_filter[2]);
9494                 tw32(MAC_HASH_REG_3, mc_filter[3]);
9495         }
9496
9497         if (rx_mode != tp->rx_mode) {
9498                 tp->rx_mode = rx_mode;
9499                 tw32_f(MAC_RX_MODE, rx_mode);
9500                 udelay(10);
9501         }
9502 }
9503
9504 static void tg3_set_rx_mode(struct net_device *dev)
9505 {
9506         struct tg3 *tp = netdev_priv(dev);
9507
9508         if (!netif_running(dev))
9509                 return;
9510
9511         tg3_full_lock(tp, 0);
9512         __tg3_set_rx_mode(dev);
9513         tg3_full_unlock(tp);
9514 }
9515
9516 #define TG3_REGDUMP_LEN         (32 * 1024)
9517
9518 static int tg3_get_regs_len(struct net_device *dev)
9519 {
9520         return TG3_REGDUMP_LEN;
9521 }
9522
9523 static void tg3_get_regs(struct net_device *dev,
9524                 struct ethtool_regs *regs, void *_p)
9525 {
9526         u32 *p = _p;
9527         struct tg3 *tp = netdev_priv(dev);
9528         u8 *orig_p = _p;
9529         int i;
9530
9531         regs->version = 0;
9532
9533         memset(p, 0, TG3_REGDUMP_LEN);
9534
9535         if (tp->link_config.phy_is_low_power)
9536                 return;
9537
9538         tg3_full_lock(tp, 0);
9539
9540 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
9541 #define GET_REG32_LOOP(base,len)                \
9542 do {    p = (u32 *)(orig_p + (base));           \
9543         for (i = 0; i < len; i += 4)            \
9544                 __GET_REG32((base) + i);        \
9545 } while (0)
9546 #define GET_REG32_1(reg)                        \
9547 do {    p = (u32 *)(orig_p + (reg));            \
9548         __GET_REG32((reg));                     \
9549 } while (0)
9550
9551         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9552         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9553         GET_REG32_LOOP(MAC_MODE, 0x4f0);
9554         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9555         GET_REG32_1(SNDDATAC_MODE);
9556         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9557         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9558         GET_REG32_1(SNDBDC_MODE);
9559         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9560         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9561         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9562         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9563         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9564         GET_REG32_1(RCVDCC_MODE);
9565         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9566         GET_REG32_LOOP(RCVCC_MODE, 0x14);
9567         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9568         GET_REG32_1(MBFREE_MODE);
9569         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9570         GET_REG32_LOOP(MEMARB_MODE, 0x10);
9571         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9572         GET_REG32_LOOP(RDMAC_MODE, 0x08);
9573         GET_REG32_LOOP(WDMAC_MODE, 0x08);
9574         GET_REG32_1(RX_CPU_MODE);
9575         GET_REG32_1(RX_CPU_STATE);
9576         GET_REG32_1(RX_CPU_PGMCTR);
9577         GET_REG32_1(RX_CPU_HWBKPT);
9578         GET_REG32_1(TX_CPU_MODE);
9579         GET_REG32_1(TX_CPU_STATE);
9580         GET_REG32_1(TX_CPU_PGMCTR);
9581         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9582         GET_REG32_LOOP(FTQ_RESET, 0x120);
9583         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9584         GET_REG32_1(DMAC_MODE);
9585         GET_REG32_LOOP(GRC_MODE, 0x4c);
9586         if (tp->tg3_flags & TG3_FLAG_NVRAM)
9587                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9588
9589 #undef __GET_REG32
9590 #undef GET_REG32_LOOP
9591 #undef GET_REG32_1
9592
9593         tg3_full_unlock(tp);
9594 }
9595
9596 static int tg3_get_eeprom_len(struct net_device *dev)
9597 {
9598         struct tg3 *tp = netdev_priv(dev);
9599
9600         return tp->nvram_size;
9601 }
9602
9603 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9604 {
9605         struct tg3 *tp = netdev_priv(dev);
9606         int ret;
9607         u8  *pd;
9608         u32 i, offset, len, b_offset, b_count;
9609         __be32 val;
9610
9611         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9612                 return -EINVAL;
9613
9614         if (tp->link_config.phy_is_low_power)
9615                 return -EAGAIN;
9616
9617         offset = eeprom->offset;
9618         len = eeprom->len;
9619         eeprom->len = 0;
9620
9621         eeprom->magic = TG3_EEPROM_MAGIC;
9622
9623         if (offset & 3) {
9624                 /* adjustments to start on required 4 byte boundary */
9625                 b_offset = offset & 3;
9626                 b_count = 4 - b_offset;
9627                 if (b_count > len) {
9628                         /* i.e. offset=1 len=2 */
9629                         b_count = len;
9630                 }
9631                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9632                 if (ret)
9633                         return ret;
9634                 memcpy(data, ((char*)&val) + b_offset, b_count);
9635                 len -= b_count;
9636                 offset += b_count;
9637                 eeprom->len += b_count;
9638         }
9639
9640         /* read bytes upto the last 4 byte boundary */
9641         pd = &data[eeprom->len];
9642         for (i = 0; i < (len - (len & 3)); i += 4) {
9643                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9644                 if (ret) {
9645                         eeprom->len += i;
9646                         return ret;
9647                 }
9648                 memcpy(pd + i, &val, 4);
9649         }
9650         eeprom->len += i;
9651
9652         if (len & 3) {
9653                 /* read last bytes not ending on 4 byte boundary */
9654                 pd = &data[eeprom->len];
9655                 b_count = len & 3;
9656                 b_offset = offset + len - b_count;
9657                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9658                 if (ret)
9659                         return ret;
9660                 memcpy(pd, &val, b_count);
9661                 eeprom->len += b_count;
9662         }
9663         return 0;
9664 }
9665
9666 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9667
9668 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9669 {
9670         struct tg3 *tp = netdev_priv(dev);
9671         int ret;
9672         u32 offset, len, b_offset, odd_len;
9673         u8 *buf;
9674         __be32 start, end;
9675
9676         if (tp->link_config.phy_is_low_power)
9677                 return -EAGAIN;
9678
9679         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9680             eeprom->magic != TG3_EEPROM_MAGIC)
9681                 return -EINVAL;
9682
9683         offset = eeprom->offset;
9684         len = eeprom->len;
9685
9686         if ((b_offset = (offset & 3))) {
9687                 /* adjustments to start on required 4 byte boundary */
9688                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9689                 if (ret)
9690                         return ret;
9691                 len += b_offset;
9692                 offset &= ~3;
9693                 if (len < 4)
9694                         len = 4;
9695         }
9696
9697         odd_len = 0;
9698         if (len & 3) {
9699                 /* adjustments to end on required 4 byte boundary */
9700                 odd_len = 1;
9701                 len = (len + 3) & ~3;
9702                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9703                 if (ret)
9704                         return ret;
9705         }
9706
9707         buf = data;
9708         if (b_offset || odd_len) {
9709                 buf = kmalloc(len, GFP_KERNEL);
9710                 if (!buf)
9711                         return -ENOMEM;
9712                 if (b_offset)
9713                         memcpy(buf, &start, 4);
9714                 if (odd_len)
9715                         memcpy(buf+len-4, &end, 4);
9716                 memcpy(buf + b_offset, data, eeprom->len);
9717         }
9718
9719         ret = tg3_nvram_write_block(tp, offset, len, buf);
9720
9721         if (buf != data)
9722                 kfree(buf);
9723
9724         return ret;
9725 }
9726
9727 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9728 {
9729         struct tg3 *tp = netdev_priv(dev);
9730
9731         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9732                 struct phy_device *phydev;
9733                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9734                         return -EAGAIN;
9735                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9736                 return phy_ethtool_gset(phydev, cmd);
9737         }
9738
9739         cmd->supported = (SUPPORTED_Autoneg);
9740
9741         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9742                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9743                                    SUPPORTED_1000baseT_Full);
9744
9745         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
9746                 cmd->supported |= (SUPPORTED_100baseT_Half |
9747                                   SUPPORTED_100baseT_Full |
9748                                   SUPPORTED_10baseT_Half |
9749                                   SUPPORTED_10baseT_Full |
9750                                   SUPPORTED_TP);
9751                 cmd->port = PORT_TP;
9752         } else {
9753                 cmd->supported |= SUPPORTED_FIBRE;
9754                 cmd->port = PORT_FIBRE;
9755         }
9756
9757         cmd->advertising = tp->link_config.advertising;
9758         if (netif_running(dev)) {
9759                 cmd->speed = tp->link_config.active_speed;
9760                 cmd->duplex = tp->link_config.active_duplex;
9761         }
9762         cmd->phy_address = tp->phy_addr;
9763         cmd->transceiver = XCVR_INTERNAL;
9764         cmd->autoneg = tp->link_config.autoneg;
9765         cmd->maxtxpkt = 0;
9766         cmd->maxrxpkt = 0;
9767         return 0;
9768 }
9769
9770 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9771 {
9772         struct tg3 *tp = netdev_priv(dev);
9773
9774         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9775                 struct phy_device *phydev;
9776                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9777                         return -EAGAIN;
9778                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9779                 return phy_ethtool_sset(phydev, cmd);
9780         }
9781
9782         if (cmd->autoneg != AUTONEG_ENABLE &&
9783             cmd->autoneg != AUTONEG_DISABLE)
9784                 return -EINVAL;
9785
9786         if (cmd->autoneg == AUTONEG_DISABLE &&
9787             cmd->duplex != DUPLEX_FULL &&
9788             cmd->duplex != DUPLEX_HALF)
9789                 return -EINVAL;
9790
9791         if (cmd->autoneg == AUTONEG_ENABLE) {
9792                 u32 mask = ADVERTISED_Autoneg |
9793                            ADVERTISED_Pause |
9794                            ADVERTISED_Asym_Pause;
9795
9796                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9797                         mask |= ADVERTISED_1000baseT_Half |
9798                                 ADVERTISED_1000baseT_Full;
9799
9800                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9801                         mask |= ADVERTISED_100baseT_Half |
9802                                 ADVERTISED_100baseT_Full |
9803                                 ADVERTISED_10baseT_Half |
9804                                 ADVERTISED_10baseT_Full |
9805                                 ADVERTISED_TP;
9806                 else
9807                         mask |= ADVERTISED_FIBRE;
9808
9809                 if (cmd->advertising & ~mask)
9810                         return -EINVAL;
9811
9812                 mask &= (ADVERTISED_1000baseT_Half |
9813                          ADVERTISED_1000baseT_Full |
9814                          ADVERTISED_100baseT_Half |
9815                          ADVERTISED_100baseT_Full |
9816                          ADVERTISED_10baseT_Half |
9817                          ADVERTISED_10baseT_Full);
9818
9819                 cmd->advertising &= mask;
9820         } else {
9821                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9822                         if (cmd->speed != SPEED_1000)
9823                                 return -EINVAL;
9824
9825                         if (cmd->duplex != DUPLEX_FULL)
9826                                 return -EINVAL;
9827                 } else {
9828                         if (cmd->speed != SPEED_100 &&
9829                             cmd->speed != SPEED_10)
9830                                 return -EINVAL;
9831                 }
9832         }
9833
9834         tg3_full_lock(tp, 0);
9835
9836         tp->link_config.autoneg = cmd->autoneg;
9837         if (cmd->autoneg == AUTONEG_ENABLE) {
9838                 tp->link_config.advertising = (cmd->advertising |
9839                                               ADVERTISED_Autoneg);
9840                 tp->link_config.speed = SPEED_INVALID;
9841                 tp->link_config.duplex = DUPLEX_INVALID;
9842         } else {
9843                 tp->link_config.advertising = 0;
9844                 tp->link_config.speed = cmd->speed;
9845                 tp->link_config.duplex = cmd->duplex;
9846         }
9847
9848         tp->link_config.orig_speed = tp->link_config.speed;
9849         tp->link_config.orig_duplex = tp->link_config.duplex;
9850         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9851
9852         if (netif_running(dev))
9853                 tg3_setup_phy(tp, 1);
9854
9855         tg3_full_unlock(tp);
9856
9857         return 0;
9858 }
9859
9860 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9861 {
9862         struct tg3 *tp = netdev_priv(dev);
9863
9864         strcpy(info->driver, DRV_MODULE_NAME);
9865         strcpy(info->version, DRV_MODULE_VERSION);
9866         strcpy(info->fw_version, tp->fw_ver);
9867         strcpy(info->bus_info, pci_name(tp->pdev));
9868 }
9869
9870 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9871 {
9872         struct tg3 *tp = netdev_priv(dev);
9873
9874         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9875             device_can_wakeup(&tp->pdev->dev))
9876                 wol->supported = WAKE_MAGIC;
9877         else
9878                 wol->supported = 0;
9879         wol->wolopts = 0;
9880         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9881             device_can_wakeup(&tp->pdev->dev))
9882                 wol->wolopts = WAKE_MAGIC;
9883         memset(&wol->sopass, 0, sizeof(wol->sopass));
9884 }
9885
9886 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9887 {
9888         struct tg3 *tp = netdev_priv(dev);
9889         struct device *dp = &tp->pdev->dev;
9890
9891         if (wol->wolopts & ~WAKE_MAGIC)
9892                 return -EINVAL;
9893         if ((wol->wolopts & WAKE_MAGIC) &&
9894             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9895                 return -EINVAL;
9896
9897         spin_lock_bh(&tp->lock);
9898         if (wol->wolopts & WAKE_MAGIC) {
9899                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9900                 device_set_wakeup_enable(dp, true);
9901         } else {
9902                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9903                 device_set_wakeup_enable(dp, false);
9904         }
9905         spin_unlock_bh(&tp->lock);
9906
9907         return 0;
9908 }
9909
9910 static u32 tg3_get_msglevel(struct net_device *dev)
9911 {
9912         struct tg3 *tp = netdev_priv(dev);
9913         return tp->msg_enable;
9914 }
9915
9916 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9917 {
9918         struct tg3 *tp = netdev_priv(dev);
9919         tp->msg_enable = value;
9920 }
9921
9922 static int tg3_set_tso(struct net_device *dev, u32 value)
9923 {
9924         struct tg3 *tp = netdev_priv(dev);
9925
9926         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9927                 if (value)
9928                         return -EINVAL;
9929                 return 0;
9930         }
9931         if ((dev->features & NETIF_F_IPV6_CSUM) &&
9932             ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9933              (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9934                 if (value) {
9935                         dev->features |= NETIF_F_TSO6;
9936                         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9937                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9938                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9939                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9940                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9941                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9942                                 dev->features |= NETIF_F_TSO_ECN;
9943                 } else
9944                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9945         }
9946         return ethtool_op_set_tso(dev, value);
9947 }
9948
9949 static int tg3_nway_reset(struct net_device *dev)
9950 {
9951         struct tg3 *tp = netdev_priv(dev);
9952         int r;
9953
9954         if (!netif_running(dev))
9955                 return -EAGAIN;
9956
9957         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9958                 return -EINVAL;
9959
9960         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9961                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9962                         return -EAGAIN;
9963                 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9964         } else {
9965                 u32 bmcr;
9966
9967                 spin_lock_bh(&tp->lock);
9968                 r = -EINVAL;
9969                 tg3_readphy(tp, MII_BMCR, &bmcr);
9970                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9971                     ((bmcr & BMCR_ANENABLE) ||
9972                      (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9973                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9974                                                    BMCR_ANENABLE);
9975                         r = 0;
9976                 }
9977                 spin_unlock_bh(&tp->lock);
9978         }
9979
9980         return r;
9981 }
9982
9983 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9984 {
9985         struct tg3 *tp = netdev_priv(dev);
9986
9987         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9988         ering->rx_mini_max_pending = 0;
9989         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9990                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9991         else
9992                 ering->rx_jumbo_max_pending = 0;
9993
9994         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9995
9996         ering->rx_pending = tp->rx_pending;
9997         ering->rx_mini_pending = 0;
9998         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9999                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
10000         else
10001                 ering->rx_jumbo_pending = 0;
10002
10003         ering->tx_pending = tp->napi[0].tx_pending;
10004 }
10005
10006 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10007 {
10008         struct tg3 *tp = netdev_priv(dev);
10009         int i, irq_sync = 0, err = 0;
10010
10011         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
10012             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
10013             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
10014             (ering->tx_pending <= MAX_SKB_FRAGS) ||
10015             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
10016              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
10017                 return -EINVAL;
10018
10019         if (netif_running(dev)) {
10020                 tg3_phy_stop(tp);
10021                 tg3_netif_stop(tp);
10022                 irq_sync = 1;
10023         }
10024
10025         tg3_full_lock(tp, irq_sync);
10026
10027         tp->rx_pending = ering->rx_pending;
10028
10029         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
10030             tp->rx_pending > 63)
10031                 tp->rx_pending = 63;
10032         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
10033
10034         for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
10035                 tp->napi[i].tx_pending = ering->tx_pending;
10036
10037         if (netif_running(dev)) {
10038                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10039                 err = tg3_restart_hw(tp, 1);
10040                 if (!err)
10041                         tg3_netif_start(tp);
10042         }
10043
10044         tg3_full_unlock(tp);
10045
10046         if (irq_sync && !err)
10047                 tg3_phy_start(tp);
10048
10049         return err;
10050 }
10051
10052 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10053 {
10054         struct tg3 *tp = netdev_priv(dev);
10055
10056         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
10057
10058         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
10059                 epause->rx_pause = 1;
10060         else
10061                 epause->rx_pause = 0;
10062
10063         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
10064                 epause->tx_pause = 1;
10065         else
10066                 epause->tx_pause = 0;
10067 }
10068
10069 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10070 {
10071         struct tg3 *tp = netdev_priv(dev);
10072         int err = 0;
10073
10074         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10075                 u32 newadv;
10076                 struct phy_device *phydev;
10077
10078                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10079
10080                 if (!(phydev->supported & SUPPORTED_Pause) ||
10081                     (!(phydev->supported & SUPPORTED_Asym_Pause) &&
10082                      ((epause->rx_pause && !epause->tx_pause) ||
10083                       (!epause->rx_pause && epause->tx_pause))))
10084                         return -EINVAL;
10085
10086                 tp->link_config.flowctrl = 0;
10087                 if (epause->rx_pause) {
10088                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
10089
10090                         if (epause->tx_pause) {
10091                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10092                                 newadv = ADVERTISED_Pause;
10093                         } else
10094                                 newadv = ADVERTISED_Pause |
10095                                          ADVERTISED_Asym_Pause;
10096                 } else if (epause->tx_pause) {
10097                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
10098                         newadv = ADVERTISED_Asym_Pause;
10099                 } else
10100                         newadv = 0;
10101
10102                 if (epause->autoneg)
10103                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10104                 else
10105                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10106
10107                 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
10108                         u32 oldadv = phydev->advertising &
10109                                      (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
10110                         if (oldadv != newadv) {
10111                                 phydev->advertising &=
10112                                         ~(ADVERTISED_Pause |
10113                                           ADVERTISED_Asym_Pause);
10114                                 phydev->advertising |= newadv;
10115                                 if (phydev->autoneg) {
10116                                         /*
10117                                          * Always renegotiate the link to
10118                                          * inform our link partner of our
10119                                          * flow control settings, even if the
10120                                          * flow control is forced.  Let
10121                                          * tg3_adjust_link() do the final
10122                                          * flow control setup.
10123                                          */
10124                                         return phy_start_aneg(phydev);
10125                                 }
10126                         }
10127
10128                         if (!epause->autoneg)
10129                                 tg3_setup_flow_control(tp, 0, 0);
10130                 } else {
10131                         tp->link_config.orig_advertising &=
10132                                         ~(ADVERTISED_Pause |
10133                                           ADVERTISED_Asym_Pause);
10134                         tp->link_config.orig_advertising |= newadv;
10135                 }
10136         } else {
10137                 int irq_sync = 0;
10138
10139                 if (netif_running(dev)) {
10140                         tg3_netif_stop(tp);
10141                         irq_sync = 1;
10142                 }
10143
10144                 tg3_full_lock(tp, irq_sync);
10145
10146                 if (epause->autoneg)
10147                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10148                 else
10149                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10150                 if (epause->rx_pause)
10151                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
10152                 else
10153                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10154                 if (epause->tx_pause)
10155                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
10156                 else
10157                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10158
10159                 if (netif_running(dev)) {
10160                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10161                         err = tg3_restart_hw(tp, 1);
10162                         if (!err)
10163                                 tg3_netif_start(tp);
10164                 }
10165
10166                 tg3_full_unlock(tp);
10167         }
10168
10169         return err;
10170 }
10171
10172 static u32 tg3_get_rx_csum(struct net_device *dev)
10173 {
10174         struct tg3 *tp = netdev_priv(dev);
10175         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10176 }
10177
10178 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10179 {
10180         struct tg3 *tp = netdev_priv(dev);
10181
10182         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10183                 if (data != 0)
10184                         return -EINVAL;
10185                 return 0;
10186         }
10187
10188         spin_lock_bh(&tp->lock);
10189         if (data)
10190                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10191         else
10192                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10193         spin_unlock_bh(&tp->lock);
10194
10195         return 0;
10196 }
10197
10198 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10199 {
10200         struct tg3 *tp = netdev_priv(dev);
10201
10202         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10203                 if (data != 0)
10204                         return -EINVAL;
10205                 return 0;
10206         }
10207
10208         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10209                 ethtool_op_set_tx_ipv6_csum(dev, data);
10210         else
10211                 ethtool_op_set_tx_csum(dev, data);
10212
10213         return 0;
10214 }
10215
10216 static int tg3_get_sset_count (struct net_device *dev, int sset)
10217 {
10218         switch (sset) {
10219         case ETH_SS_TEST:
10220                 return TG3_NUM_TEST;
10221         case ETH_SS_STATS:
10222                 return TG3_NUM_STATS;
10223         default:
10224                 return -EOPNOTSUPP;
10225         }
10226 }
10227
10228 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
10229 {
10230         switch (stringset) {
10231         case ETH_SS_STATS:
10232                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10233                 break;
10234         case ETH_SS_TEST:
10235                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10236                 break;
10237         default:
10238                 WARN_ON(1);     /* we need a WARN() */
10239                 break;
10240         }
10241 }
10242
10243 static int tg3_phys_id(struct net_device *dev, u32 data)
10244 {
10245         struct tg3 *tp = netdev_priv(dev);
10246         int i;
10247
10248         if (!netif_running(tp->dev))
10249                 return -EAGAIN;
10250
10251         if (data == 0)
10252                 data = UINT_MAX / 2;
10253
10254         for (i = 0; i < (data * 2); i++) {
10255                 if ((i % 2) == 0)
10256                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10257                                            LED_CTRL_1000MBPS_ON |
10258                                            LED_CTRL_100MBPS_ON |
10259                                            LED_CTRL_10MBPS_ON |
10260                                            LED_CTRL_TRAFFIC_OVERRIDE |
10261                                            LED_CTRL_TRAFFIC_BLINK |
10262                                            LED_CTRL_TRAFFIC_LED);
10263
10264                 else
10265                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10266                                            LED_CTRL_TRAFFIC_OVERRIDE);
10267
10268                 if (msleep_interruptible(500))
10269                         break;
10270         }
10271         tw32(MAC_LED_CTRL, tp->led_ctrl);
10272         return 0;
10273 }
10274
10275 static void tg3_get_ethtool_stats (struct net_device *dev,
10276                                    struct ethtool_stats *estats, u64 *tmp_stats)
10277 {
10278         struct tg3 *tp = netdev_priv(dev);
10279         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10280 }
10281
10282 #define NVRAM_TEST_SIZE 0x100
10283 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
10284 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
10285 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
10286 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10287 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10288
10289 static int tg3_test_nvram(struct tg3 *tp)
10290 {
10291         u32 csum, magic;
10292         __be32 *buf;
10293         int i, j, k, err = 0, size;
10294
10295         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10296                 return 0;
10297
10298         if (tg3_nvram_read(tp, 0, &magic) != 0)
10299                 return -EIO;
10300
10301         if (magic == TG3_EEPROM_MAGIC)
10302                 size = NVRAM_TEST_SIZE;
10303         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10304                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10305                     TG3_EEPROM_SB_FORMAT_1) {
10306                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10307                         case TG3_EEPROM_SB_REVISION_0:
10308                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10309                                 break;
10310                         case TG3_EEPROM_SB_REVISION_2:
10311                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10312                                 break;
10313                         case TG3_EEPROM_SB_REVISION_3:
10314                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10315                                 break;
10316                         default:
10317                                 return 0;
10318                         }
10319                 } else
10320                         return 0;
10321         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10322                 size = NVRAM_SELFBOOT_HW_SIZE;
10323         else
10324                 return -EIO;
10325
10326         buf = kmalloc(size, GFP_KERNEL);
10327         if (buf == NULL)
10328                 return -ENOMEM;
10329
10330         err = -EIO;
10331         for (i = 0, j = 0; i < size; i += 4, j++) {
10332                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10333                 if (err)
10334                         break;
10335         }
10336         if (i < size)
10337                 goto out;
10338
10339         /* Selfboot format */
10340         magic = be32_to_cpu(buf[0]);
10341         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10342             TG3_EEPROM_MAGIC_FW) {
10343                 u8 *buf8 = (u8 *) buf, csum8 = 0;
10344
10345                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10346                     TG3_EEPROM_SB_REVISION_2) {
10347                         /* For rev 2, the csum doesn't include the MBA. */
10348                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10349                                 csum8 += buf8[i];
10350                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10351                                 csum8 += buf8[i];
10352                 } else {
10353                         for (i = 0; i < size; i++)
10354                                 csum8 += buf8[i];
10355                 }
10356
10357                 if (csum8 == 0) {
10358                         err = 0;
10359                         goto out;
10360                 }
10361
10362                 err = -EIO;
10363                 goto out;
10364         }
10365
10366         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10367             TG3_EEPROM_MAGIC_HW) {
10368                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10369                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10370                 u8 *buf8 = (u8 *) buf;
10371
10372                 /* Separate the parity bits and the data bytes.  */
10373                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10374                         if ((i == 0) || (i == 8)) {
10375                                 int l;
10376                                 u8 msk;
10377
10378                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10379                                         parity[k++] = buf8[i] & msk;
10380                                 i++;
10381                         }
10382                         else if (i == 16) {
10383                                 int l;
10384                                 u8 msk;
10385
10386                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10387                                         parity[k++] = buf8[i] & msk;
10388                                 i++;
10389
10390                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10391                                         parity[k++] = buf8[i] & msk;
10392                                 i++;
10393                         }
10394                         data[j++] = buf8[i];
10395                 }
10396
10397                 err = -EIO;
10398                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10399                         u8 hw8 = hweight8(data[i]);
10400
10401                         if ((hw8 & 0x1) && parity[i])
10402                                 goto out;
10403                         else if (!(hw8 & 0x1) && !parity[i])
10404                                 goto out;
10405                 }
10406                 err = 0;
10407                 goto out;
10408         }
10409
10410         /* Bootstrap checksum at offset 0x10 */
10411         csum = calc_crc((unsigned char *) buf, 0x10);
10412         if (csum != be32_to_cpu(buf[0x10/4]))
10413                 goto out;
10414
10415         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10416         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10417         if (csum != be32_to_cpu(buf[0xfc/4]))
10418                 goto out;
10419
10420         err = 0;
10421
10422 out:
10423         kfree(buf);
10424         return err;
10425 }
10426
10427 #define TG3_SERDES_TIMEOUT_SEC  2
10428 #define TG3_COPPER_TIMEOUT_SEC  6
10429
10430 static int tg3_test_link(struct tg3 *tp)
10431 {
10432         int i, max;
10433
10434         if (!netif_running(tp->dev))
10435                 return -ENODEV;
10436
10437         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10438                 max = TG3_SERDES_TIMEOUT_SEC;
10439         else
10440                 max = TG3_COPPER_TIMEOUT_SEC;
10441
10442         for (i = 0; i < max; i++) {
10443                 if (netif_carrier_ok(tp->dev))
10444                         return 0;
10445
10446                 if (msleep_interruptible(1000))
10447                         break;
10448         }
10449
10450         return -EIO;
10451 }
10452
10453 /* Only test the commonly used registers */
10454 static int tg3_test_registers(struct tg3 *tp)
10455 {
10456         int i, is_5705, is_5750;
10457         u32 offset, read_mask, write_mask, val, save_val, read_val;
10458         static struct {
10459                 u16 offset;
10460                 u16 flags;
10461 #define TG3_FL_5705     0x1
10462 #define TG3_FL_NOT_5705 0x2
10463 #define TG3_FL_NOT_5788 0x4
10464 #define TG3_FL_NOT_5750 0x8
10465                 u32 read_mask;
10466                 u32 write_mask;
10467         } reg_tbl[] = {
10468                 /* MAC Control Registers */
10469                 { MAC_MODE, TG3_FL_NOT_5705,
10470                         0x00000000, 0x00ef6f8c },
10471                 { MAC_MODE, TG3_FL_5705,
10472                         0x00000000, 0x01ef6b8c },
10473                 { MAC_STATUS, TG3_FL_NOT_5705,
10474                         0x03800107, 0x00000000 },
10475                 { MAC_STATUS, TG3_FL_5705,
10476                         0x03800100, 0x00000000 },
10477                 { MAC_ADDR_0_HIGH, 0x0000,
10478                         0x00000000, 0x0000ffff },
10479                 { MAC_ADDR_0_LOW, 0x0000,
10480                         0x00000000, 0xffffffff },
10481                 { MAC_RX_MTU_SIZE, 0x0000,
10482                         0x00000000, 0x0000ffff },
10483                 { MAC_TX_MODE, 0x0000,
10484                         0x00000000, 0x00000070 },
10485                 { MAC_TX_LENGTHS, 0x0000,
10486                         0x00000000, 0x00003fff },
10487                 { MAC_RX_MODE, TG3_FL_NOT_5705,
10488                         0x00000000, 0x000007fc },
10489                 { MAC_RX_MODE, TG3_FL_5705,
10490                         0x00000000, 0x000007dc },
10491                 { MAC_HASH_REG_0, 0x0000,
10492                         0x00000000, 0xffffffff },
10493                 { MAC_HASH_REG_1, 0x0000,
10494                         0x00000000, 0xffffffff },
10495                 { MAC_HASH_REG_2, 0x0000,
10496                         0x00000000, 0xffffffff },
10497                 { MAC_HASH_REG_3, 0x0000,
10498                         0x00000000, 0xffffffff },
10499
10500                 /* Receive Data and Receive BD Initiator Control Registers. */
10501                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10502                         0x00000000, 0xffffffff },
10503                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10504                         0x00000000, 0xffffffff },
10505                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10506                         0x00000000, 0x00000003 },
10507                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10508                         0x00000000, 0xffffffff },
10509                 { RCVDBDI_STD_BD+0, 0x0000,
10510                         0x00000000, 0xffffffff },
10511                 { RCVDBDI_STD_BD+4, 0x0000,
10512                         0x00000000, 0xffffffff },
10513                 { RCVDBDI_STD_BD+8, 0x0000,
10514                         0x00000000, 0xffff0002 },
10515                 { RCVDBDI_STD_BD+0xc, 0x0000,
10516                         0x00000000, 0xffffffff },
10517
10518                 /* Receive BD Initiator Control Registers. */
10519                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10520                         0x00000000, 0xffffffff },
10521                 { RCVBDI_STD_THRESH, TG3_FL_5705,
10522                         0x00000000, 0x000003ff },
10523                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10524                         0x00000000, 0xffffffff },
10525
10526                 /* Host Coalescing Control Registers. */
10527                 { HOSTCC_MODE, TG3_FL_NOT_5705,
10528                         0x00000000, 0x00000004 },
10529                 { HOSTCC_MODE, TG3_FL_5705,
10530                         0x00000000, 0x000000f6 },
10531                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10532                         0x00000000, 0xffffffff },
10533                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10534                         0x00000000, 0x000003ff },
10535                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10536                         0x00000000, 0xffffffff },
10537                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10538                         0x00000000, 0x000003ff },
10539                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10540                         0x00000000, 0xffffffff },
10541                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10542                         0x00000000, 0x000000ff },
10543                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10544                         0x00000000, 0xffffffff },
10545                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10546                         0x00000000, 0x000000ff },
10547                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10548                         0x00000000, 0xffffffff },
10549                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10550                         0x00000000, 0xffffffff },
10551                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10552                         0x00000000, 0xffffffff },
10553                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10554                         0x00000000, 0x000000ff },
10555                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10556                         0x00000000, 0xffffffff },
10557                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10558                         0x00000000, 0x000000ff },
10559                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10560                         0x00000000, 0xffffffff },
10561                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10562                         0x00000000, 0xffffffff },
10563                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10564                         0x00000000, 0xffffffff },
10565                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10566                         0x00000000, 0xffffffff },
10567                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10568                         0x00000000, 0xffffffff },
10569                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10570                         0xffffffff, 0x00000000 },
10571                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10572                         0xffffffff, 0x00000000 },
10573
10574                 /* Buffer Manager Control Registers. */
10575                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10576                         0x00000000, 0x007fff80 },
10577                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10578                         0x00000000, 0x007fffff },
10579                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10580                         0x00000000, 0x0000003f },
10581                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10582                         0x00000000, 0x000001ff },
10583                 { BUFMGR_MB_HIGH_WATER, 0x0000,
10584                         0x00000000, 0x000001ff },
10585                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10586                         0xffffffff, 0x00000000 },
10587                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10588                         0xffffffff, 0x00000000 },
10589
10590                 /* Mailbox Registers */
10591                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10592                         0x00000000, 0x000001ff },
10593                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10594                         0x00000000, 0x000001ff },
10595                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10596                         0x00000000, 0x000007ff },
10597                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10598                         0x00000000, 0x000001ff },
10599
10600                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10601         };
10602
10603         is_5705 = is_5750 = 0;
10604         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10605                 is_5705 = 1;
10606                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10607                         is_5750 = 1;
10608         }
10609
10610         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10611                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10612                         continue;
10613
10614                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10615                         continue;
10616
10617                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10618                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
10619                         continue;
10620
10621                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10622                         continue;
10623
10624                 offset = (u32) reg_tbl[i].offset;
10625                 read_mask = reg_tbl[i].read_mask;
10626                 write_mask = reg_tbl[i].write_mask;
10627
10628                 /* Save the original register content */
10629                 save_val = tr32(offset);
10630
10631                 /* Determine the read-only value. */
10632                 read_val = save_val & read_mask;
10633
10634                 /* Write zero to the register, then make sure the read-only bits
10635                  * are not changed and the read/write bits are all zeros.
10636                  */
10637                 tw32(offset, 0);
10638
10639                 val = tr32(offset);
10640
10641                 /* Test the read-only and read/write bits. */
10642                 if (((val & read_mask) != read_val) || (val & write_mask))
10643                         goto out;
10644
10645                 /* Write ones to all the bits defined by RdMask and WrMask, then
10646                  * make sure the read-only bits are not changed and the
10647                  * read/write bits are all ones.
10648                  */
10649                 tw32(offset, read_mask | write_mask);
10650
10651                 val = tr32(offset);
10652
10653                 /* Test the read-only bits. */
10654                 if ((val & read_mask) != read_val)
10655                         goto out;
10656
10657                 /* Test the read/write bits. */
10658                 if ((val & write_mask) != write_mask)
10659                         goto out;
10660
10661                 tw32(offset, save_val);
10662         }
10663
10664         return 0;
10665
10666 out:
10667         if (netif_msg_hw(tp))
10668                 netdev_err(tp->dev,
10669                            "Register test failed at offset %x\n", offset);
10670         tw32(offset, save_val);
10671         return -EIO;
10672 }
10673
10674 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10675 {
10676         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10677         int i;
10678         u32 j;
10679
10680         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10681                 for (j = 0; j < len; j += 4) {
10682                         u32 val;
10683
10684                         tg3_write_mem(tp, offset + j, test_pattern[i]);
10685                         tg3_read_mem(tp, offset + j, &val);
10686                         if (val != test_pattern[i])
10687                                 return -EIO;
10688                 }
10689         }
10690         return 0;
10691 }
10692
10693 static int tg3_test_memory(struct tg3 *tp)
10694 {
10695         static struct mem_entry {
10696                 u32 offset;
10697                 u32 len;
10698         } mem_tbl_570x[] = {
10699                 { 0x00000000, 0x00b50},
10700                 { 0x00002000, 0x1c000},
10701                 { 0xffffffff, 0x00000}
10702         }, mem_tbl_5705[] = {
10703                 { 0x00000100, 0x0000c},
10704                 { 0x00000200, 0x00008},
10705                 { 0x00004000, 0x00800},
10706                 { 0x00006000, 0x01000},
10707                 { 0x00008000, 0x02000},
10708                 { 0x00010000, 0x0e000},
10709                 { 0xffffffff, 0x00000}
10710         }, mem_tbl_5755[] = {
10711                 { 0x00000200, 0x00008},
10712                 { 0x00004000, 0x00800},
10713                 { 0x00006000, 0x00800},
10714                 { 0x00008000, 0x02000},
10715                 { 0x00010000, 0x0c000},
10716                 { 0xffffffff, 0x00000}
10717         }, mem_tbl_5906[] = {
10718                 { 0x00000200, 0x00008},
10719                 { 0x00004000, 0x00400},
10720                 { 0x00006000, 0x00400},
10721                 { 0x00008000, 0x01000},
10722                 { 0x00010000, 0x01000},
10723                 { 0xffffffff, 0x00000}
10724         }, mem_tbl_5717[] = {
10725                 { 0x00000200, 0x00008},
10726                 { 0x00010000, 0x0a000},
10727                 { 0x00020000, 0x13c00},
10728                 { 0xffffffff, 0x00000}
10729         }, mem_tbl_57765[] = {
10730                 { 0x00000200, 0x00008},
10731                 { 0x00004000, 0x00800},
10732                 { 0x00006000, 0x09800},
10733                 { 0x00010000, 0x0a000},
10734                 { 0xffffffff, 0x00000}
10735         };
10736         struct mem_entry *mem_tbl;
10737         int err = 0;
10738         int i;
10739
10740         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
10741                 mem_tbl = mem_tbl_5717;
10742         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10743                 mem_tbl = mem_tbl_57765;
10744         else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10745                 mem_tbl = mem_tbl_5755;
10746         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10747                 mem_tbl = mem_tbl_5906;
10748         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10749                 mem_tbl = mem_tbl_5705;
10750         else
10751                 mem_tbl = mem_tbl_570x;
10752
10753         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10754                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10755                     mem_tbl[i].len)) != 0)
10756                         break;
10757         }
10758
10759         return err;
10760 }
10761
10762 #define TG3_MAC_LOOPBACK        0
10763 #define TG3_PHY_LOOPBACK        1
10764
10765 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10766 {
10767         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10768         u32 desc_idx, coal_now;
10769         struct sk_buff *skb, *rx_skb;
10770         u8 *tx_data;
10771         dma_addr_t map;
10772         int num_pkts, tx_len, rx_len, i, err;
10773         struct tg3_rx_buffer_desc *desc;
10774         struct tg3_napi *tnapi, *rnapi;
10775         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
10776
10777         tnapi = &tp->napi[0];
10778         rnapi = &tp->napi[0];
10779         if (tp->irq_cnt > 1) {
10780                 rnapi = &tp->napi[1];
10781                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
10782                         tnapi = &tp->napi[1];
10783         }
10784         coal_now = tnapi->coal_now | rnapi->coal_now;
10785
10786         if (loopback_mode == TG3_MAC_LOOPBACK) {
10787                 /* HW errata - mac loopback fails in some cases on 5780.
10788                  * Normal traffic and PHY loopback are not affected by
10789                  * errata.
10790                  */
10791                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10792                         return 0;
10793
10794                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10795                            MAC_MODE_PORT_INT_LPBACK;
10796                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10797                         mac_mode |= MAC_MODE_LINK_POLARITY;
10798                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10799                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10800                 else
10801                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10802                 tw32(MAC_MODE, mac_mode);
10803         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10804                 u32 val;
10805
10806                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10807                         tg3_phy_fet_toggle_apd(tp, false);
10808                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10809                 } else
10810                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10811
10812                 tg3_phy_toggle_automdix(tp, 0);
10813
10814                 tg3_writephy(tp, MII_BMCR, val);
10815                 udelay(40);
10816
10817                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10818                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10819                         tg3_writephy(tp, MII_TG3_FET_PTEST,
10820                                      MII_TG3_FET_PTEST_FRC_TX_LINK |
10821                                      MII_TG3_FET_PTEST_FRC_TX_LOCK);
10822                         /* The write needs to be flushed for the AC131 */
10823                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10824                                 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
10825                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10826                 } else
10827                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10828
10829                 /* reset to prevent losing 1st rx packet intermittently */
10830                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10831                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10832                         udelay(10);
10833                         tw32_f(MAC_RX_MODE, tp->rx_mode);
10834                 }
10835                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10836                         u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
10837                         if (masked_phy_id == TG3_PHY_ID_BCM5401)
10838                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10839                         else if (masked_phy_id == TG3_PHY_ID_BCM5411)
10840                                 mac_mode |= MAC_MODE_LINK_POLARITY;
10841                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
10842                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10843                 }
10844                 tw32(MAC_MODE, mac_mode);
10845         }
10846         else
10847                 return -EINVAL;
10848
10849         err = -EIO;
10850
10851         tx_len = 1514;
10852         skb = netdev_alloc_skb(tp->dev, tx_len);
10853         if (!skb)
10854                 return -ENOMEM;
10855
10856         tx_data = skb_put(skb, tx_len);
10857         memcpy(tx_data, tp->dev->dev_addr, 6);
10858         memset(tx_data + 6, 0x0, 8);
10859
10860         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10861
10862         for (i = 14; i < tx_len; i++)
10863                 tx_data[i] = (u8) (i & 0xff);
10864
10865         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10866         if (pci_dma_mapping_error(tp->pdev, map)) {
10867                 dev_kfree_skb(skb);
10868                 return -EIO;
10869         }
10870
10871         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10872                rnapi->coal_now);
10873
10874         udelay(10);
10875
10876         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10877
10878         num_pkts = 0;
10879
10880         tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10881
10882         tnapi->tx_prod++;
10883         num_pkts++;
10884
10885         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10886         tr32_mailbox(tnapi->prodmbox);
10887
10888         udelay(10);
10889
10890         /* 350 usec to allow enough time on some 10/100 Mbps devices.  */
10891         for (i = 0; i < 35; i++) {
10892                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10893                        coal_now);
10894
10895                 udelay(10);
10896
10897                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10898                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10899                 if ((tx_idx == tnapi->tx_prod) &&
10900                     (rx_idx == (rx_start_idx + num_pkts)))
10901                         break;
10902         }
10903
10904         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10905         dev_kfree_skb(skb);
10906
10907         if (tx_idx != tnapi->tx_prod)
10908                 goto out;
10909
10910         if (rx_idx != rx_start_idx + num_pkts)
10911                 goto out;
10912
10913         desc = &rnapi->rx_rcb[rx_start_idx];
10914         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10915         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10916         if (opaque_key != RXD_OPAQUE_RING_STD)
10917                 goto out;
10918
10919         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10920             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10921                 goto out;
10922
10923         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10924         if (rx_len != tx_len)
10925                 goto out;
10926
10927         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10928
10929         map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10930         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10931
10932         for (i = 14; i < tx_len; i++) {
10933                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10934                         goto out;
10935         }
10936         err = 0;
10937
10938         /* tg3_free_rings will unmap and free the rx_skb */
10939 out:
10940         return err;
10941 }
10942
10943 #define TG3_MAC_LOOPBACK_FAILED         1
10944 #define TG3_PHY_LOOPBACK_FAILED         2
10945 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
10946                                          TG3_PHY_LOOPBACK_FAILED)
10947
10948 static int tg3_test_loopback(struct tg3 *tp)
10949 {
10950         int err = 0;
10951         u32 cpmuctrl = 0;
10952
10953         if (!netif_running(tp->dev))
10954                 return TG3_LOOPBACK_FAILED;
10955
10956         err = tg3_reset_hw(tp, 1);
10957         if (err)
10958                 return TG3_LOOPBACK_FAILED;
10959
10960         /* Turn off gphy autopowerdown. */
10961         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10962                 tg3_phy_toggle_apd(tp, false);
10963
10964         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10965                 int i;
10966                 u32 status;
10967
10968                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10969
10970                 /* Wait for up to 40 microseconds to acquire lock. */
10971                 for (i = 0; i < 4; i++) {
10972                         status = tr32(TG3_CPMU_MUTEX_GNT);
10973                         if (status == CPMU_MUTEX_GNT_DRIVER)
10974                                 break;
10975                         udelay(10);
10976                 }
10977
10978                 if (status != CPMU_MUTEX_GNT_DRIVER)
10979                         return TG3_LOOPBACK_FAILED;
10980
10981                 /* Turn off link-based power management. */
10982                 cpmuctrl = tr32(TG3_CPMU_CTRL);
10983                 tw32(TG3_CPMU_CTRL,
10984                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10985                                   CPMU_CTRL_LINK_AWARE_MODE));
10986         }
10987
10988         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10989                 err |= TG3_MAC_LOOPBACK_FAILED;
10990
10991         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10992                 tw32(TG3_CPMU_CTRL, cpmuctrl);
10993
10994                 /* Release the mutex */
10995                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10996         }
10997
10998         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10999             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
11000                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
11001                         err |= TG3_PHY_LOOPBACK_FAILED;
11002         }
11003
11004         /* Re-enable gphy autopowerdown. */
11005         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
11006                 tg3_phy_toggle_apd(tp, true);
11007
11008         return err;
11009 }
11010
11011 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
11012                           u64 *data)
11013 {
11014         struct tg3 *tp = netdev_priv(dev);
11015
11016         if (tp->link_config.phy_is_low_power)
11017                 tg3_set_power_state(tp, PCI_D0);
11018
11019         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
11020
11021         if (tg3_test_nvram(tp) != 0) {
11022                 etest->flags |= ETH_TEST_FL_FAILED;
11023                 data[0] = 1;
11024         }
11025         if (tg3_test_link(tp) != 0) {
11026                 etest->flags |= ETH_TEST_FL_FAILED;
11027                 data[1] = 1;
11028         }
11029         if (etest->flags & ETH_TEST_FL_OFFLINE) {
11030                 int err, err2 = 0, irq_sync = 0;
11031
11032                 if (netif_running(dev)) {
11033                         tg3_phy_stop(tp);
11034                         tg3_netif_stop(tp);
11035                         irq_sync = 1;
11036                 }
11037
11038                 tg3_full_lock(tp, irq_sync);
11039
11040                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
11041                 err = tg3_nvram_lock(tp);
11042                 tg3_halt_cpu(tp, RX_CPU_BASE);
11043                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11044                         tg3_halt_cpu(tp, TX_CPU_BASE);
11045                 if (!err)
11046                         tg3_nvram_unlock(tp);
11047
11048                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
11049                         tg3_phy_reset(tp);
11050
11051                 if (tg3_test_registers(tp) != 0) {
11052                         etest->flags |= ETH_TEST_FL_FAILED;
11053                         data[2] = 1;
11054                 }
11055                 if (tg3_test_memory(tp) != 0) {
11056                         etest->flags |= ETH_TEST_FL_FAILED;
11057                         data[3] = 1;
11058                 }
11059                 if ((data[4] = tg3_test_loopback(tp)) != 0)
11060                         etest->flags |= ETH_TEST_FL_FAILED;
11061
11062                 tg3_full_unlock(tp);
11063
11064                 if (tg3_test_interrupt(tp) != 0) {
11065                         etest->flags |= ETH_TEST_FL_FAILED;
11066                         data[5] = 1;
11067                 }
11068
11069                 tg3_full_lock(tp, 0);
11070
11071                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11072                 if (netif_running(dev)) {
11073                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11074                         err2 = tg3_restart_hw(tp, 1);
11075                         if (!err2)
11076                                 tg3_netif_start(tp);
11077                 }
11078
11079                 tg3_full_unlock(tp);
11080
11081                 if (irq_sync && !err2)
11082                         tg3_phy_start(tp);
11083         }
11084         if (tp->link_config.phy_is_low_power)
11085                 tg3_set_power_state(tp, PCI_D3hot);
11086
11087 }
11088
11089 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11090 {
11091         struct mii_ioctl_data *data = if_mii(ifr);
11092         struct tg3 *tp = netdev_priv(dev);
11093         int err;
11094
11095         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
11096                 struct phy_device *phydev;
11097                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
11098                         return -EAGAIN;
11099                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11100                 return phy_mii_ioctl(phydev, data, cmd);
11101         }
11102
11103         switch(cmd) {
11104         case SIOCGMIIPHY:
11105                 data->phy_id = tp->phy_addr;
11106
11107                 /* fallthru */
11108         case SIOCGMIIREG: {
11109                 u32 mii_regval;
11110
11111                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11112                         break;                  /* We have no PHY */
11113
11114                 if (tp->link_config.phy_is_low_power)
11115                         return -EAGAIN;
11116
11117                 spin_lock_bh(&tp->lock);
11118                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
11119                 spin_unlock_bh(&tp->lock);
11120
11121                 data->val_out = mii_regval;
11122
11123                 return err;
11124         }
11125
11126         case SIOCSMIIREG:
11127                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11128                         break;                  /* We have no PHY */
11129
11130                 if (tp->link_config.phy_is_low_power)
11131                         return -EAGAIN;
11132
11133                 spin_lock_bh(&tp->lock);
11134                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
11135                 spin_unlock_bh(&tp->lock);
11136
11137                 return err;
11138
11139         default:
11140                 /* do nothing */
11141                 break;
11142         }
11143         return -EOPNOTSUPP;
11144 }
11145
11146 #if TG3_VLAN_TAG_USED
11147 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
11148 {
11149         struct tg3 *tp = netdev_priv(dev);
11150
11151         if (!netif_running(dev)) {
11152                 tp->vlgrp = grp;
11153                 return;
11154         }
11155
11156         tg3_netif_stop(tp);
11157
11158         tg3_full_lock(tp, 0);
11159
11160         tp->vlgrp = grp;
11161
11162         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11163         __tg3_set_rx_mode(dev);
11164
11165         tg3_netif_start(tp);
11166
11167         tg3_full_unlock(tp);
11168 }
11169 #endif
11170
11171 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11172 {
11173         struct tg3 *tp = netdev_priv(dev);
11174
11175         memcpy(ec, &tp->coal, sizeof(*ec));
11176         return 0;
11177 }
11178
11179 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11180 {
11181         struct tg3 *tp = netdev_priv(dev);
11182         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11183         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11184
11185         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11186                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11187                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11188                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11189                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11190         }
11191
11192         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11193             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11194             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11195             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11196             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11197             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11198             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11199             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11200             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11201             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11202                 return -EINVAL;
11203
11204         /* No rx interrupts will be generated if both are zero */
11205         if ((ec->rx_coalesce_usecs == 0) &&
11206             (ec->rx_max_coalesced_frames == 0))
11207                 return -EINVAL;
11208
11209         /* No tx interrupts will be generated if both are zero */
11210         if ((ec->tx_coalesce_usecs == 0) &&
11211             (ec->tx_max_coalesced_frames == 0))
11212                 return -EINVAL;
11213
11214         /* Only copy relevant parameters, ignore all others. */
11215         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11216         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11217         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11218         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11219         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11220         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11221         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11222         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11223         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11224
11225         if (netif_running(dev)) {
11226                 tg3_full_lock(tp, 0);
11227                 __tg3_set_coalesce(tp, &tp->coal);
11228                 tg3_full_unlock(tp);
11229         }
11230         return 0;
11231 }
11232
11233 static const struct ethtool_ops tg3_ethtool_ops = {
11234         .get_settings           = tg3_get_settings,
11235         .set_settings           = tg3_set_settings,
11236         .get_drvinfo            = tg3_get_drvinfo,
11237         .get_regs_len           = tg3_get_regs_len,
11238         .get_regs               = tg3_get_regs,
11239         .get_wol                = tg3_get_wol,
11240         .set_wol                = tg3_set_wol,
11241         .get_msglevel           = tg3_get_msglevel,
11242         .set_msglevel           = tg3_set_msglevel,
11243         .nway_reset             = tg3_nway_reset,
11244         .get_link               = ethtool_op_get_link,
11245         .get_eeprom_len         = tg3_get_eeprom_len,
11246         .get_eeprom             = tg3_get_eeprom,
11247         .set_eeprom             = tg3_set_eeprom,
11248         .get_ringparam          = tg3_get_ringparam,
11249         .set_ringparam          = tg3_set_ringparam,
11250         .get_pauseparam         = tg3_get_pauseparam,
11251         .set_pauseparam         = tg3_set_pauseparam,
11252         .get_rx_csum            = tg3_get_rx_csum,
11253         .set_rx_csum            = tg3_set_rx_csum,
11254         .set_tx_csum            = tg3_set_tx_csum,
11255         .set_sg                 = ethtool_op_set_sg,
11256         .set_tso                = tg3_set_tso,
11257         .self_test              = tg3_self_test,
11258         .get_strings            = tg3_get_strings,
11259         .phys_id                = tg3_phys_id,
11260         .get_ethtool_stats      = tg3_get_ethtool_stats,
11261         .get_coalesce           = tg3_get_coalesce,
11262         .set_coalesce           = tg3_set_coalesce,
11263         .get_sset_count         = tg3_get_sset_count,
11264 };
11265
11266 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11267 {
11268         u32 cursize, val, magic;
11269
11270         tp->nvram_size = EEPROM_CHIP_SIZE;
11271
11272         if (tg3_nvram_read(tp, 0, &magic) != 0)
11273                 return;
11274
11275         if ((magic != TG3_EEPROM_MAGIC) &&
11276             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11277             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11278                 return;
11279
11280         /*
11281          * Size the chip by reading offsets at increasing powers of two.
11282          * When we encounter our validation signature, we know the addressing
11283          * has wrapped around, and thus have our chip size.
11284          */
11285         cursize = 0x10;
11286
11287         while (cursize < tp->nvram_size) {
11288                 if (tg3_nvram_read(tp, cursize, &val) != 0)
11289                         return;
11290
11291                 if (val == magic)
11292                         break;
11293
11294                 cursize <<= 1;
11295         }
11296
11297         tp->nvram_size = cursize;
11298 }
11299
11300 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11301 {
11302         u32 val;
11303
11304         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11305             tg3_nvram_read(tp, 0, &val) != 0)
11306                 return;
11307
11308         /* Selfboot format */
11309         if (val != TG3_EEPROM_MAGIC) {
11310                 tg3_get_eeprom_size(tp);
11311                 return;
11312         }
11313
11314         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11315                 if (val != 0) {
11316                         /* This is confusing.  We want to operate on the
11317                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
11318                          * call will read from NVRAM and byteswap the data
11319                          * according to the byteswapping settings for all
11320                          * other register accesses.  This ensures the data we
11321                          * want will always reside in the lower 16-bits.
11322                          * However, the data in NVRAM is in LE format, which
11323                          * means the data from the NVRAM read will always be
11324                          * opposite the endianness of the CPU.  The 16-bit
11325                          * byteswap then brings the data to CPU endianness.
11326                          */
11327                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11328                         return;
11329                 }
11330         }
11331         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11332 }
11333
11334 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11335 {
11336         u32 nvcfg1;
11337
11338         nvcfg1 = tr32(NVRAM_CFG1);
11339         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11340                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11341         } else {
11342                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11343                 tw32(NVRAM_CFG1, nvcfg1);
11344         }
11345
11346         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11347             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11348                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11349                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11350                         tp->nvram_jedecnum = JEDEC_ATMEL;
11351                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11352                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11353                         break;
11354                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11355                         tp->nvram_jedecnum = JEDEC_ATMEL;
11356                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11357                         break;
11358                 case FLASH_VENDOR_ATMEL_EEPROM:
11359                         tp->nvram_jedecnum = JEDEC_ATMEL;
11360                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11361                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11362                         break;
11363                 case FLASH_VENDOR_ST:
11364                         tp->nvram_jedecnum = JEDEC_ST;
11365                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11366                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11367                         break;
11368                 case FLASH_VENDOR_SAIFUN:
11369                         tp->nvram_jedecnum = JEDEC_SAIFUN;
11370                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11371                         break;
11372                 case FLASH_VENDOR_SST_SMALL:
11373                 case FLASH_VENDOR_SST_LARGE:
11374                         tp->nvram_jedecnum = JEDEC_SST;
11375                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11376                         break;
11377                 }
11378         } else {
11379                 tp->nvram_jedecnum = JEDEC_ATMEL;
11380                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11381                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11382         }
11383 }
11384
11385 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11386 {
11387         switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11388         case FLASH_5752PAGE_SIZE_256:
11389                 tp->nvram_pagesize = 256;
11390                 break;
11391         case FLASH_5752PAGE_SIZE_512:
11392                 tp->nvram_pagesize = 512;
11393                 break;
11394         case FLASH_5752PAGE_SIZE_1K:
11395                 tp->nvram_pagesize = 1024;
11396                 break;
11397         case FLASH_5752PAGE_SIZE_2K:
11398                 tp->nvram_pagesize = 2048;
11399                 break;
11400         case FLASH_5752PAGE_SIZE_4K:
11401                 tp->nvram_pagesize = 4096;
11402                 break;
11403         case FLASH_5752PAGE_SIZE_264:
11404                 tp->nvram_pagesize = 264;
11405                 break;
11406         case FLASH_5752PAGE_SIZE_528:
11407                 tp->nvram_pagesize = 528;
11408                 break;
11409         }
11410 }
11411
11412 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11413 {
11414         u32 nvcfg1;
11415
11416         nvcfg1 = tr32(NVRAM_CFG1);
11417
11418         /* NVRAM protection for TPM */
11419         if (nvcfg1 & (1 << 27))
11420                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11421
11422         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11423         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11424         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11425                 tp->nvram_jedecnum = JEDEC_ATMEL;
11426                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11427                 break;
11428         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11429                 tp->nvram_jedecnum = JEDEC_ATMEL;
11430                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11431                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11432                 break;
11433         case FLASH_5752VENDOR_ST_M45PE10:
11434         case FLASH_5752VENDOR_ST_M45PE20:
11435         case FLASH_5752VENDOR_ST_M45PE40:
11436                 tp->nvram_jedecnum = JEDEC_ST;
11437                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11438                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11439                 break;
11440         }
11441
11442         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11443                 tg3_nvram_get_pagesize(tp, nvcfg1);
11444         } else {
11445                 /* For eeprom, set pagesize to maximum eeprom size */
11446                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11447
11448                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11449                 tw32(NVRAM_CFG1, nvcfg1);
11450         }
11451 }
11452
11453 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11454 {
11455         u32 nvcfg1, protect = 0;
11456
11457         nvcfg1 = tr32(NVRAM_CFG1);
11458
11459         /* NVRAM protection for TPM */
11460         if (nvcfg1 & (1 << 27)) {
11461                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11462                 protect = 1;
11463         }
11464
11465         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11466         switch (nvcfg1) {
11467         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11468         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11469         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11470         case FLASH_5755VENDOR_ATMEL_FLASH_5:
11471                 tp->nvram_jedecnum = JEDEC_ATMEL;
11472                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11473                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11474                 tp->nvram_pagesize = 264;
11475                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11476                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11477                         tp->nvram_size = (protect ? 0x3e200 :
11478                                           TG3_NVRAM_SIZE_512KB);
11479                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11480                         tp->nvram_size = (protect ? 0x1f200 :
11481                                           TG3_NVRAM_SIZE_256KB);
11482                 else
11483                         tp->nvram_size = (protect ? 0x1f200 :
11484                                           TG3_NVRAM_SIZE_128KB);
11485                 break;
11486         case FLASH_5752VENDOR_ST_M45PE10:
11487         case FLASH_5752VENDOR_ST_M45PE20:
11488         case FLASH_5752VENDOR_ST_M45PE40:
11489                 tp->nvram_jedecnum = JEDEC_ST;
11490                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11491                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11492                 tp->nvram_pagesize = 256;
11493                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11494                         tp->nvram_size = (protect ?
11495                                           TG3_NVRAM_SIZE_64KB :
11496                                           TG3_NVRAM_SIZE_128KB);
11497                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11498                         tp->nvram_size = (protect ?
11499                                           TG3_NVRAM_SIZE_64KB :
11500                                           TG3_NVRAM_SIZE_256KB);
11501                 else
11502                         tp->nvram_size = (protect ?
11503                                           TG3_NVRAM_SIZE_128KB :
11504                                           TG3_NVRAM_SIZE_512KB);
11505                 break;
11506         }
11507 }
11508
11509 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11510 {
11511         u32 nvcfg1;
11512
11513         nvcfg1 = tr32(NVRAM_CFG1);
11514
11515         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11516         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11517         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11518         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11519         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11520                 tp->nvram_jedecnum = JEDEC_ATMEL;
11521                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11522                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11523
11524                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11525                 tw32(NVRAM_CFG1, nvcfg1);
11526                 break;
11527         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11528         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11529         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11530         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11531                 tp->nvram_jedecnum = JEDEC_ATMEL;
11532                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11533                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11534                 tp->nvram_pagesize = 264;
11535                 break;
11536         case FLASH_5752VENDOR_ST_M45PE10:
11537         case FLASH_5752VENDOR_ST_M45PE20:
11538         case FLASH_5752VENDOR_ST_M45PE40:
11539                 tp->nvram_jedecnum = JEDEC_ST;
11540                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11541                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11542                 tp->nvram_pagesize = 256;
11543                 break;
11544         }
11545 }
11546
11547 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11548 {
11549         u32 nvcfg1, protect = 0;
11550
11551         nvcfg1 = tr32(NVRAM_CFG1);
11552
11553         /* NVRAM protection for TPM */
11554         if (nvcfg1 & (1 << 27)) {
11555                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11556                 protect = 1;
11557         }
11558
11559         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11560         switch (nvcfg1) {
11561         case FLASH_5761VENDOR_ATMEL_ADB021D:
11562         case FLASH_5761VENDOR_ATMEL_ADB041D:
11563         case FLASH_5761VENDOR_ATMEL_ADB081D:
11564         case FLASH_5761VENDOR_ATMEL_ADB161D:
11565         case FLASH_5761VENDOR_ATMEL_MDB021D:
11566         case FLASH_5761VENDOR_ATMEL_MDB041D:
11567         case FLASH_5761VENDOR_ATMEL_MDB081D:
11568         case FLASH_5761VENDOR_ATMEL_MDB161D:
11569                 tp->nvram_jedecnum = JEDEC_ATMEL;
11570                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11571                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11572                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11573                 tp->nvram_pagesize = 256;
11574                 break;
11575         case FLASH_5761VENDOR_ST_A_M45PE20:
11576         case FLASH_5761VENDOR_ST_A_M45PE40:
11577         case FLASH_5761VENDOR_ST_A_M45PE80:
11578         case FLASH_5761VENDOR_ST_A_M45PE16:
11579         case FLASH_5761VENDOR_ST_M_M45PE20:
11580         case FLASH_5761VENDOR_ST_M_M45PE40:
11581         case FLASH_5761VENDOR_ST_M_M45PE80:
11582         case FLASH_5761VENDOR_ST_M_M45PE16:
11583                 tp->nvram_jedecnum = JEDEC_ST;
11584                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11585                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11586                 tp->nvram_pagesize = 256;
11587                 break;
11588         }
11589
11590         if (protect) {
11591                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11592         } else {
11593                 switch (nvcfg1) {
11594                 case FLASH_5761VENDOR_ATMEL_ADB161D:
11595                 case FLASH_5761VENDOR_ATMEL_MDB161D:
11596                 case FLASH_5761VENDOR_ST_A_M45PE16:
11597                 case FLASH_5761VENDOR_ST_M_M45PE16:
11598                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11599                         break;
11600                 case FLASH_5761VENDOR_ATMEL_ADB081D:
11601                 case FLASH_5761VENDOR_ATMEL_MDB081D:
11602                 case FLASH_5761VENDOR_ST_A_M45PE80:
11603                 case FLASH_5761VENDOR_ST_M_M45PE80:
11604                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11605                         break;
11606                 case FLASH_5761VENDOR_ATMEL_ADB041D:
11607                 case FLASH_5761VENDOR_ATMEL_MDB041D:
11608                 case FLASH_5761VENDOR_ST_A_M45PE40:
11609                 case FLASH_5761VENDOR_ST_M_M45PE40:
11610                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11611                         break;
11612                 case FLASH_5761VENDOR_ATMEL_ADB021D:
11613                 case FLASH_5761VENDOR_ATMEL_MDB021D:
11614                 case FLASH_5761VENDOR_ST_A_M45PE20:
11615                 case FLASH_5761VENDOR_ST_M_M45PE20:
11616                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11617                         break;
11618                 }
11619         }
11620 }
11621
11622 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11623 {
11624         tp->nvram_jedecnum = JEDEC_ATMEL;
11625         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11626         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11627 }
11628
11629 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11630 {
11631         u32 nvcfg1;
11632
11633         nvcfg1 = tr32(NVRAM_CFG1);
11634
11635         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11636         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11637         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11638                 tp->nvram_jedecnum = JEDEC_ATMEL;
11639                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11640                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11641
11642                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11643                 tw32(NVRAM_CFG1, nvcfg1);
11644                 return;
11645         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11646         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11647         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11648         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11649         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11650         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11651         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11652                 tp->nvram_jedecnum = JEDEC_ATMEL;
11653                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11654                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11655
11656                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11657                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11658                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11659                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11660                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11661                         break;
11662                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11663                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11664                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11665                         break;
11666                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11667                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11668                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11669                         break;
11670                 }
11671                 break;
11672         case FLASH_5752VENDOR_ST_M45PE10:
11673         case FLASH_5752VENDOR_ST_M45PE20:
11674         case FLASH_5752VENDOR_ST_M45PE40:
11675                 tp->nvram_jedecnum = JEDEC_ST;
11676                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11677                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11678
11679                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11680                 case FLASH_5752VENDOR_ST_M45PE10:
11681                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11682                         break;
11683                 case FLASH_5752VENDOR_ST_M45PE20:
11684                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11685                         break;
11686                 case FLASH_5752VENDOR_ST_M45PE40:
11687                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11688                         break;
11689                 }
11690                 break;
11691         default:
11692                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11693                 return;
11694         }
11695
11696         tg3_nvram_get_pagesize(tp, nvcfg1);
11697         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11698                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11699 }
11700
11701
11702 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11703 {
11704         u32 nvcfg1;
11705
11706         nvcfg1 = tr32(NVRAM_CFG1);
11707
11708         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11709         case FLASH_5717VENDOR_ATMEL_EEPROM:
11710         case FLASH_5717VENDOR_MICRO_EEPROM:
11711                 tp->nvram_jedecnum = JEDEC_ATMEL;
11712                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11713                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11714
11715                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11716                 tw32(NVRAM_CFG1, nvcfg1);
11717                 return;
11718         case FLASH_5717VENDOR_ATMEL_MDB011D:
11719         case FLASH_5717VENDOR_ATMEL_ADB011B:
11720         case FLASH_5717VENDOR_ATMEL_ADB011D:
11721         case FLASH_5717VENDOR_ATMEL_MDB021D:
11722         case FLASH_5717VENDOR_ATMEL_ADB021B:
11723         case FLASH_5717VENDOR_ATMEL_ADB021D:
11724         case FLASH_5717VENDOR_ATMEL_45USPT:
11725                 tp->nvram_jedecnum = JEDEC_ATMEL;
11726                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11727                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11728
11729                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11730                 case FLASH_5717VENDOR_ATMEL_MDB021D:
11731                 case FLASH_5717VENDOR_ATMEL_ADB021B:
11732                 case FLASH_5717VENDOR_ATMEL_ADB021D:
11733                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11734                         break;
11735                 default:
11736                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11737                         break;
11738                 }
11739                 break;
11740         case FLASH_5717VENDOR_ST_M_M25PE10:
11741         case FLASH_5717VENDOR_ST_A_M25PE10:
11742         case FLASH_5717VENDOR_ST_M_M45PE10:
11743         case FLASH_5717VENDOR_ST_A_M45PE10:
11744         case FLASH_5717VENDOR_ST_M_M25PE20:
11745         case FLASH_5717VENDOR_ST_A_M25PE20:
11746         case FLASH_5717VENDOR_ST_M_M45PE20:
11747         case FLASH_5717VENDOR_ST_A_M45PE20:
11748         case FLASH_5717VENDOR_ST_25USPT:
11749         case FLASH_5717VENDOR_ST_45USPT:
11750                 tp->nvram_jedecnum = JEDEC_ST;
11751                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11752                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11753
11754                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11755                 case FLASH_5717VENDOR_ST_M_M25PE20:
11756                 case FLASH_5717VENDOR_ST_A_M25PE20:
11757                 case FLASH_5717VENDOR_ST_M_M45PE20:
11758                 case FLASH_5717VENDOR_ST_A_M45PE20:
11759                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11760                         break;
11761                 default:
11762                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11763                         break;
11764                 }
11765                 break;
11766         default:
11767                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11768                 return;
11769         }
11770
11771         tg3_nvram_get_pagesize(tp, nvcfg1);
11772         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11773                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11774 }
11775
11776 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11777 static void __devinit tg3_nvram_init(struct tg3 *tp)
11778 {
11779         tw32_f(GRC_EEPROM_ADDR,
11780              (EEPROM_ADDR_FSM_RESET |
11781               (EEPROM_DEFAULT_CLOCK_PERIOD <<
11782                EEPROM_ADDR_CLKPERD_SHIFT)));
11783
11784         msleep(1);
11785
11786         /* Enable seeprom accesses. */
11787         tw32_f(GRC_LOCAL_CTRL,
11788              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11789         udelay(100);
11790
11791         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11792             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11793                 tp->tg3_flags |= TG3_FLAG_NVRAM;
11794
11795                 if (tg3_nvram_lock(tp)) {
11796                         netdev_warn(tp->dev,
11797                                     "Cannot get nvram lock, %s failed\n",
11798                                     __func__);
11799                         return;
11800                 }
11801                 tg3_enable_nvram_access(tp);
11802
11803                 tp->nvram_size = 0;
11804
11805                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11806                         tg3_get_5752_nvram_info(tp);
11807                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11808                         tg3_get_5755_nvram_info(tp);
11809                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11810                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11811                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11812                         tg3_get_5787_nvram_info(tp);
11813                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11814                         tg3_get_5761_nvram_info(tp);
11815                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11816                         tg3_get_5906_nvram_info(tp);
11817                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11818                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11819                         tg3_get_57780_nvram_info(tp);
11820                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11821                         tg3_get_5717_nvram_info(tp);
11822                 else
11823                         tg3_get_nvram_info(tp);
11824
11825                 if (tp->nvram_size == 0)
11826                         tg3_get_nvram_size(tp);
11827
11828                 tg3_disable_nvram_access(tp);
11829                 tg3_nvram_unlock(tp);
11830
11831         } else {
11832                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11833
11834                 tg3_get_eeprom_size(tp);
11835         }
11836 }
11837
11838 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11839                                     u32 offset, u32 len, u8 *buf)
11840 {
11841         int i, j, rc = 0;
11842         u32 val;
11843
11844         for (i = 0; i < len; i += 4) {
11845                 u32 addr;
11846                 __be32 data;
11847
11848                 addr = offset + i;
11849
11850                 memcpy(&data, buf + i, 4);
11851
11852                 /*
11853                  * The SEEPROM interface expects the data to always be opposite
11854                  * the native endian format.  We accomplish this by reversing
11855                  * all the operations that would have been performed on the
11856                  * data from a call to tg3_nvram_read_be32().
11857                  */
11858                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11859
11860                 val = tr32(GRC_EEPROM_ADDR);
11861                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11862
11863                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11864                         EEPROM_ADDR_READ);
11865                 tw32(GRC_EEPROM_ADDR, val |
11866                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
11867                         (addr & EEPROM_ADDR_ADDR_MASK) |
11868                         EEPROM_ADDR_START |
11869                         EEPROM_ADDR_WRITE);
11870
11871                 for (j = 0; j < 1000; j++) {
11872                         val = tr32(GRC_EEPROM_ADDR);
11873
11874                         if (val & EEPROM_ADDR_COMPLETE)
11875                                 break;
11876                         msleep(1);
11877                 }
11878                 if (!(val & EEPROM_ADDR_COMPLETE)) {
11879                         rc = -EBUSY;
11880                         break;
11881                 }
11882         }
11883
11884         return rc;
11885 }
11886
11887 /* offset and length are dword aligned */
11888 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11889                 u8 *buf)
11890 {
11891         int ret = 0;
11892         u32 pagesize = tp->nvram_pagesize;
11893         u32 pagemask = pagesize - 1;
11894         u32 nvram_cmd;
11895         u8 *tmp;
11896
11897         tmp = kmalloc(pagesize, GFP_KERNEL);
11898         if (tmp == NULL)
11899                 return -ENOMEM;
11900
11901         while (len) {
11902                 int j;
11903                 u32 phy_addr, page_off, size;
11904
11905                 phy_addr = offset & ~pagemask;
11906
11907                 for (j = 0; j < pagesize; j += 4) {
11908                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
11909                                                   (__be32 *) (tmp + j));
11910                         if (ret)
11911                                 break;
11912                 }
11913                 if (ret)
11914                         break;
11915
11916                 page_off = offset & pagemask;
11917                 size = pagesize;
11918                 if (len < size)
11919                         size = len;
11920
11921                 len -= size;
11922
11923                 memcpy(tmp + page_off, buf, size);
11924
11925                 offset = offset + (pagesize - page_off);
11926
11927                 tg3_enable_nvram_access(tp);
11928
11929                 /*
11930                  * Before we can erase the flash page, we need
11931                  * to issue a special "write enable" command.
11932                  */
11933                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11934
11935                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11936                         break;
11937
11938                 /* Erase the target page */
11939                 tw32(NVRAM_ADDR, phy_addr);
11940
11941                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11942                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11943
11944                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11945                         break;
11946
11947                 /* Issue another write enable to start the write. */
11948                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11949
11950                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11951                         break;
11952
11953                 for (j = 0; j < pagesize; j += 4) {
11954                         __be32 data;
11955
11956                         data = *((__be32 *) (tmp + j));
11957
11958                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
11959
11960                         tw32(NVRAM_ADDR, phy_addr + j);
11961
11962                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11963                                 NVRAM_CMD_WR;
11964
11965                         if (j == 0)
11966                                 nvram_cmd |= NVRAM_CMD_FIRST;
11967                         else if (j == (pagesize - 4))
11968                                 nvram_cmd |= NVRAM_CMD_LAST;
11969
11970                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11971                                 break;
11972                 }
11973                 if (ret)
11974                         break;
11975         }
11976
11977         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11978         tg3_nvram_exec_cmd(tp, nvram_cmd);
11979
11980         kfree(tmp);
11981
11982         return ret;
11983 }
11984
11985 /* offset and length are dword aligned */
11986 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11987                 u8 *buf)
11988 {
11989         int i, ret = 0;
11990
11991         for (i = 0; i < len; i += 4, offset += 4) {
11992                 u32 page_off, phy_addr, nvram_cmd;
11993                 __be32 data;
11994
11995                 memcpy(&data, buf + i, 4);
11996                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11997
11998                 page_off = offset % tp->nvram_pagesize;
11999
12000                 phy_addr = tg3_nvram_phys_addr(tp, offset);
12001
12002                 tw32(NVRAM_ADDR, phy_addr);
12003
12004                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
12005
12006                 if ((page_off == 0) || (i == 0))
12007                         nvram_cmd |= NVRAM_CMD_FIRST;
12008                 if (page_off == (tp->nvram_pagesize - 4))
12009                         nvram_cmd |= NVRAM_CMD_LAST;
12010
12011                 if (i == (len - 4))
12012                         nvram_cmd |= NVRAM_CMD_LAST;
12013
12014                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
12015                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
12016                     (tp->nvram_jedecnum == JEDEC_ST) &&
12017                     (nvram_cmd & NVRAM_CMD_FIRST)) {
12018
12019                         if ((ret = tg3_nvram_exec_cmd(tp,
12020                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
12021                                 NVRAM_CMD_DONE)))
12022
12023                                 break;
12024                 }
12025                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12026                         /* We always do complete word writes to eeprom. */
12027                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
12028                 }
12029
12030                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12031                         break;
12032         }
12033         return ret;
12034 }
12035
12036 /* offset and length are dword aligned */
12037 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
12038 {
12039         int ret;
12040
12041         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12042                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
12043                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
12044                 udelay(40);
12045         }
12046
12047         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
12048                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
12049         }
12050         else {
12051                 u32 grc_mode;
12052
12053                 ret = tg3_nvram_lock(tp);
12054                 if (ret)
12055                         return ret;
12056
12057                 tg3_enable_nvram_access(tp);
12058                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
12059                     !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
12060                         tw32(NVRAM_WRITE1, 0x406);
12061
12062                 grc_mode = tr32(GRC_MODE);
12063                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
12064
12065                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
12066                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12067
12068                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
12069                                 buf);
12070                 }
12071                 else {
12072                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12073                                 buf);
12074                 }
12075
12076                 grc_mode = tr32(GRC_MODE);
12077                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
12078
12079                 tg3_disable_nvram_access(tp);
12080                 tg3_nvram_unlock(tp);
12081         }
12082
12083         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12084                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
12085                 udelay(40);
12086         }
12087
12088         return ret;
12089 }
12090
12091 struct subsys_tbl_ent {
12092         u16 subsys_vendor, subsys_devid;
12093         u32 phy_id;
12094 };
12095
12096 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
12097         /* Broadcom boards. */
12098         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12099           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
12100         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12101           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
12102         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12103           TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
12104         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12105           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
12106         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12107           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
12108         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12109           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
12110         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12111           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
12112         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12113           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
12114         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12115           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
12116         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12117           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
12118         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12119           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
12120
12121         /* 3com boards. */
12122         { TG3PCI_SUBVENDOR_ID_3COM,
12123           TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
12124         { TG3PCI_SUBVENDOR_ID_3COM,
12125           TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
12126         { TG3PCI_SUBVENDOR_ID_3COM,
12127           TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
12128         { TG3PCI_SUBVENDOR_ID_3COM,
12129           TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
12130         { TG3PCI_SUBVENDOR_ID_3COM,
12131           TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
12132
12133         /* DELL boards. */
12134         { TG3PCI_SUBVENDOR_ID_DELL,
12135           TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
12136         { TG3PCI_SUBVENDOR_ID_DELL,
12137           TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
12138         { TG3PCI_SUBVENDOR_ID_DELL,
12139           TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
12140         { TG3PCI_SUBVENDOR_ID_DELL,
12141           TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
12142
12143         /* Compaq boards. */
12144         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12145           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
12146         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12147           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
12148         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12149           TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
12150         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12151           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
12152         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12153           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
12154
12155         /* IBM boards. */
12156         { TG3PCI_SUBVENDOR_ID_IBM,
12157           TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
12158 };
12159
12160 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
12161 {
12162         int i;
12163
12164         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12165                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12166                      tp->pdev->subsystem_vendor) &&
12167                     (subsys_id_to_phy_id[i].subsys_devid ==
12168                      tp->pdev->subsystem_device))
12169                         return &subsys_id_to_phy_id[i];
12170         }
12171         return NULL;
12172 }
12173
12174 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12175 {
12176         u32 val;
12177         u16 pmcsr;
12178
12179         /* On some early chips the SRAM cannot be accessed in D3hot state,
12180          * so need make sure we're in D0.
12181          */
12182         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12183         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12184         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12185         msleep(1);
12186
12187         /* Make sure register accesses (indirect or otherwise)
12188          * will function correctly.
12189          */
12190         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12191                                tp->misc_host_ctrl);
12192
12193         /* The memory arbiter has to be enabled in order for SRAM accesses
12194          * to succeed.  Normally on powerup the tg3 chip firmware will make
12195          * sure it is enabled, but other entities such as system netboot
12196          * code might disable it.
12197          */
12198         val = tr32(MEMARB_MODE);
12199         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12200
12201         tp->phy_id = TG3_PHY_ID_INVALID;
12202         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12203
12204         /* Assume an onboard device and WOL capable by default.  */
12205         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12206
12207         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12208                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12209                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12210                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12211                 }
12212                 val = tr32(VCPU_CFGSHDW);
12213                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12214                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12215                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12216                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
12217                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12218                 goto done;
12219         }
12220
12221         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12222         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12223                 u32 nic_cfg, led_cfg;
12224                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12225                 int eeprom_phy_serdes = 0;
12226
12227                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12228                 tp->nic_sram_data_cfg = nic_cfg;
12229
12230                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12231                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12232                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12233                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12234                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12235                     (ver > 0) && (ver < 0x100))
12236                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12237
12238                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12239                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12240
12241                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12242                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12243                         eeprom_phy_serdes = 1;
12244
12245                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12246                 if (nic_phy_id != 0) {
12247                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12248                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12249
12250                         eeprom_phy_id  = (id1 >> 16) << 10;
12251                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
12252                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
12253                 } else
12254                         eeprom_phy_id = 0;
12255
12256                 tp->phy_id = eeprom_phy_id;
12257                 if (eeprom_phy_serdes) {
12258                         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
12259                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12260                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
12261                         else
12262                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12263                 }
12264
12265                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12266                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12267                                     SHASTA_EXT_LED_MODE_MASK);
12268                 else
12269                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12270
12271                 switch (led_cfg) {
12272                 default:
12273                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12274                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12275                         break;
12276
12277                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12278                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12279                         break;
12280
12281                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12282                         tp->led_ctrl = LED_CTRL_MODE_MAC;
12283
12284                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12285                          * read on some older 5700/5701 bootcode.
12286                          */
12287                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12288                             ASIC_REV_5700 ||
12289                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
12290                             ASIC_REV_5701)
12291                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12292
12293                         break;
12294
12295                 case SHASTA_EXT_LED_SHARED:
12296                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
12297                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12298                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12299                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12300                                                  LED_CTRL_MODE_PHY_2);
12301                         break;
12302
12303                 case SHASTA_EXT_LED_MAC:
12304                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12305                         break;
12306
12307                 case SHASTA_EXT_LED_COMBO:
12308                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
12309                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12310                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12311                                                  LED_CTRL_MODE_PHY_2);
12312                         break;
12313
12314                 }
12315
12316                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12317                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12318                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12319                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12320
12321                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12322                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12323
12324                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12325                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12326                         if ((tp->pdev->subsystem_vendor ==
12327                              PCI_VENDOR_ID_ARIMA) &&
12328                             (tp->pdev->subsystem_device == 0x205a ||
12329                              tp->pdev->subsystem_device == 0x2063))
12330                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12331                 } else {
12332                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12333                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12334                 }
12335
12336                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12337                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12338                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12339                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12340                 }
12341
12342                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12343                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12344                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12345
12346                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
12347                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12348                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12349
12350                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12351                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12352                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12353
12354                 if (cfg2 & (1 << 17))
12355                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
12356
12357                 /* serdes signal pre-emphasis in register 0x590 set by */
12358                 /* bootcode if bit 18 is set */
12359                 if (cfg2 & (1 << 18))
12360                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
12361
12362                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12363                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
12364                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12365                         tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
12366
12367                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12368                         u32 cfg3;
12369
12370                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12371                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12372                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12373                 }
12374
12375                 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12376                         tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
12377                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12378                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12379                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12380                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12381         }
12382 done:
12383         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12384         device_set_wakeup_enable(&tp->pdev->dev,
12385                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12386 }
12387
12388 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12389 {
12390         int i;
12391         u32 val;
12392
12393         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12394         tw32(OTP_CTRL, cmd);
12395
12396         /* Wait for up to 1 ms for command to execute. */
12397         for (i = 0; i < 100; i++) {
12398                 val = tr32(OTP_STATUS);
12399                 if (val & OTP_STATUS_CMD_DONE)
12400                         break;
12401                 udelay(10);
12402         }
12403
12404         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12405 }
12406
12407 /* Read the gphy configuration from the OTP region of the chip.  The gphy
12408  * configuration is a 32-bit value that straddles the alignment boundary.
12409  * We do two 32-bit reads and then shift and merge the results.
12410  */
12411 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12412 {
12413         u32 bhalf_otp, thalf_otp;
12414
12415         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12416
12417         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12418                 return 0;
12419
12420         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12421
12422         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12423                 return 0;
12424
12425         thalf_otp = tr32(OTP_READ_DATA);
12426
12427         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12428
12429         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12430                 return 0;
12431
12432         bhalf_otp = tr32(OTP_READ_DATA);
12433
12434         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12435 }
12436
12437 static int __devinit tg3_phy_probe(struct tg3 *tp)
12438 {
12439         u32 hw_phy_id_1, hw_phy_id_2;
12440         u32 hw_phy_id, hw_phy_id_masked;
12441         int err;
12442
12443         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12444                 return tg3_phy_init(tp);
12445
12446         /* Reading the PHY ID register can conflict with ASF
12447          * firmware access to the PHY hardware.
12448          */
12449         err = 0;
12450         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12451             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12452                 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
12453         } else {
12454                 /* Now read the physical PHY_ID from the chip and verify
12455                  * that it is sane.  If it doesn't look good, we fall back
12456                  * to either the hard-coded table based PHY_ID and failing
12457                  * that the value found in the eeprom area.
12458                  */
12459                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12460                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12461
12462                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
12463                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12464                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
12465
12466                 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
12467         }
12468
12469         if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
12470                 tp->phy_id = hw_phy_id;
12471                 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
12472                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12473                 else
12474                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
12475         } else {
12476                 if (tp->phy_id != TG3_PHY_ID_INVALID) {
12477                         /* Do nothing, phy ID already set up in
12478                          * tg3_get_eeprom_hw_cfg().
12479                          */
12480                 } else {
12481                         struct subsys_tbl_ent *p;
12482
12483                         /* No eeprom signature?  Try the hardcoded
12484                          * subsys device table.
12485                          */
12486                         p = tg3_lookup_by_subsys(tp);
12487                         if (!p)
12488                                 return -ENODEV;
12489
12490                         tp->phy_id = p->phy_id;
12491                         if (!tp->phy_id ||
12492                             tp->phy_id == TG3_PHY_ID_BCM8002)
12493                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12494                 }
12495         }
12496
12497         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
12498             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12499             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12500                 u32 bmsr, adv_reg, tg3_ctrl, mask;
12501
12502                 tg3_readphy(tp, MII_BMSR, &bmsr);
12503                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12504                     (bmsr & BMSR_LSTATUS))
12505                         goto skip_phy_reset;
12506
12507                 err = tg3_phy_reset(tp);
12508                 if (err)
12509                         return err;
12510
12511                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12512                            ADVERTISE_100HALF | ADVERTISE_100FULL |
12513                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12514                 tg3_ctrl = 0;
12515                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12516                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12517                                     MII_TG3_CTRL_ADV_1000_FULL);
12518                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12519                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12520                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12521                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
12522                 }
12523
12524                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12525                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12526                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12527                 if (!tg3_copper_is_advertising_all(tp, mask)) {
12528                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12529
12530                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12531                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12532
12533                         tg3_writephy(tp, MII_BMCR,
12534                                      BMCR_ANENABLE | BMCR_ANRESTART);
12535                 }
12536                 tg3_phy_set_wirespeed(tp);
12537
12538                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12539                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12540                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12541         }
12542
12543 skip_phy_reset:
12544         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
12545                 err = tg3_init_5401phy_dsp(tp);
12546                 if (err)
12547                         return err;
12548
12549                 err = tg3_init_5401phy_dsp(tp);
12550         }
12551
12552         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
12553                 tp->link_config.advertising =
12554                         (ADVERTISED_1000baseT_Half |
12555                          ADVERTISED_1000baseT_Full |
12556                          ADVERTISED_Autoneg |
12557                          ADVERTISED_FIBRE);
12558         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12559                 tp->link_config.advertising &=
12560                         ~(ADVERTISED_1000baseT_Half |
12561                           ADVERTISED_1000baseT_Full);
12562
12563         return err;
12564 }
12565
12566 static void __devinit tg3_read_partno(struct tg3 *tp)
12567 {
12568         unsigned char vpd_data[TG3_NVM_VPD_LEN];   /* in little-endian format */
12569         unsigned int block_end, rosize, len;
12570         int i = 0;
12571         u32 magic;
12572
12573         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12574             tg3_nvram_read(tp, 0x0, &magic))
12575                 goto out_not_found;
12576
12577         if (magic == TG3_EEPROM_MAGIC) {
12578                 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12579                         u32 tmp;
12580
12581                         /* The data is in little-endian format in NVRAM.
12582                          * Use the big-endian read routines to preserve
12583                          * the byte order as it exists in NVRAM.
12584                          */
12585                         if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12586                                 goto out_not_found;
12587
12588                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12589                 }
12590         } else {
12591                 ssize_t cnt;
12592                 unsigned int pos = 0;
12593
12594                 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12595                         cnt = pci_read_vpd(tp->pdev, pos,
12596                                            TG3_NVM_VPD_LEN - pos,
12597                                            &vpd_data[pos]);
12598                         if (cnt == -ETIMEDOUT || -EINTR)
12599                                 cnt = 0;
12600                         else if (cnt < 0)
12601                                 goto out_not_found;
12602                 }
12603                 if (pos != TG3_NVM_VPD_LEN)
12604                         goto out_not_found;
12605         }
12606
12607         i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
12608                              PCI_VPD_LRDT_RO_DATA);
12609         if (i < 0)
12610                 goto out_not_found;
12611
12612         rosize = pci_vpd_lrdt_size(&vpd_data[i]);
12613         block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
12614         i += PCI_VPD_LRDT_TAG_SIZE;
12615
12616         if (block_end > TG3_NVM_VPD_LEN)
12617                 goto out_not_found;
12618
12619         i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12620                                       PCI_VPD_RO_KEYWORD_PARTNO);
12621         if (i < 0)
12622                 goto out_not_found;
12623
12624         len = pci_vpd_info_field_size(&vpd_data[i]);
12625
12626         i += PCI_VPD_INFO_FLD_HDR_SIZE;
12627         if (len > TG3_BPN_SIZE ||
12628             (len + i) > TG3_NVM_VPD_LEN)
12629                 goto out_not_found;
12630
12631         memcpy(tp->board_part_number, &vpd_data[i], len);
12632
12633         return;
12634
12635 out_not_found:
12636         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12637                 strcpy(tp->board_part_number, "BCM95906");
12638         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12639                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12640                 strcpy(tp->board_part_number, "BCM57780");
12641         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12642                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12643                 strcpy(tp->board_part_number, "BCM57760");
12644         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12645                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12646                 strcpy(tp->board_part_number, "BCM57790");
12647         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12648                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12649                 strcpy(tp->board_part_number, "BCM57788");
12650         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12651                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
12652                 strcpy(tp->board_part_number, "BCM57761");
12653         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12654                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
12655                 strcpy(tp->board_part_number, "BCM57765");
12656         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12657                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
12658                 strcpy(tp->board_part_number, "BCM57781");
12659         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12660                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
12661                 strcpy(tp->board_part_number, "BCM57785");
12662         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12663                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
12664                 strcpy(tp->board_part_number, "BCM57791");
12665         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12666                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12667                 strcpy(tp->board_part_number, "BCM57795");
12668         else
12669                 strcpy(tp->board_part_number, "none");
12670 }
12671
12672 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12673 {
12674         u32 val;
12675
12676         if (tg3_nvram_read(tp, offset, &val) ||
12677             (val & 0xfc000000) != 0x0c000000 ||
12678             tg3_nvram_read(tp, offset + 4, &val) ||
12679             val != 0)
12680                 return 0;
12681
12682         return 1;
12683 }
12684
12685 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12686 {
12687         u32 val, offset, start, ver_offset;
12688         int i, dst_off;
12689         bool newver = false;
12690
12691         if (tg3_nvram_read(tp, 0xc, &offset) ||
12692             tg3_nvram_read(tp, 0x4, &start))
12693                 return;
12694
12695         offset = tg3_nvram_logical_addr(tp, offset);
12696
12697         if (tg3_nvram_read(tp, offset, &val))
12698                 return;
12699
12700         if ((val & 0xfc000000) == 0x0c000000) {
12701                 if (tg3_nvram_read(tp, offset + 4, &val))
12702                         return;
12703
12704                 if (val == 0)
12705                         newver = true;
12706         }
12707
12708         dst_off = strlen(tp->fw_ver);
12709
12710         if (newver) {
12711                 if (TG3_VER_SIZE - dst_off < 16 ||
12712                     tg3_nvram_read(tp, offset + 8, &ver_offset))
12713                         return;
12714
12715                 offset = offset + ver_offset - start;
12716                 for (i = 0; i < 16; i += 4) {
12717                         __be32 v;
12718                         if (tg3_nvram_read_be32(tp, offset + i, &v))
12719                                 return;
12720
12721                         memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
12722                 }
12723         } else {
12724                 u32 major, minor;
12725
12726                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12727                         return;
12728
12729                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12730                         TG3_NVM_BCVER_MAJSFT;
12731                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12732                 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
12733                          "v%d.%02d", major, minor);
12734         }
12735 }
12736
12737 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12738 {
12739         u32 val, major, minor;
12740
12741         /* Use native endian representation */
12742         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12743                 return;
12744
12745         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12746                 TG3_NVM_HWSB_CFG1_MAJSFT;
12747         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12748                 TG3_NVM_HWSB_CFG1_MINSFT;
12749
12750         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12751 }
12752
12753 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12754 {
12755         u32 offset, major, minor, build;
12756
12757         strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
12758
12759         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12760                 return;
12761
12762         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12763         case TG3_EEPROM_SB_REVISION_0:
12764                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12765                 break;
12766         case TG3_EEPROM_SB_REVISION_2:
12767                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12768                 break;
12769         case TG3_EEPROM_SB_REVISION_3:
12770                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12771                 break;
12772         case TG3_EEPROM_SB_REVISION_4:
12773                 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
12774                 break;
12775         case TG3_EEPROM_SB_REVISION_5:
12776                 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
12777                 break;
12778         default:
12779                 return;
12780         }
12781
12782         if (tg3_nvram_read(tp, offset, &val))
12783                 return;
12784
12785         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12786                 TG3_EEPROM_SB_EDH_BLD_SHFT;
12787         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12788                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12789         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
12790
12791         if (minor > 99 || build > 26)
12792                 return;
12793
12794         offset = strlen(tp->fw_ver);
12795         snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
12796                  " v%d.%02d", major, minor);
12797
12798         if (build > 0) {
12799                 offset = strlen(tp->fw_ver);
12800                 if (offset < TG3_VER_SIZE - 1)
12801                         tp->fw_ver[offset] = 'a' + build - 1;
12802         }
12803 }
12804
12805 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12806 {
12807         u32 val, offset, start;
12808         int i, vlen;
12809
12810         for (offset = TG3_NVM_DIR_START;
12811              offset < TG3_NVM_DIR_END;
12812              offset += TG3_NVM_DIRENT_SIZE) {
12813                 if (tg3_nvram_read(tp, offset, &val))
12814                         return;
12815
12816                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12817                         break;
12818         }
12819
12820         if (offset == TG3_NVM_DIR_END)
12821                 return;
12822
12823         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12824                 start = 0x08000000;
12825         else if (tg3_nvram_read(tp, offset - 4, &start))
12826                 return;
12827
12828         if (tg3_nvram_read(tp, offset + 4, &offset) ||
12829             !tg3_fw_img_is_valid(tp, offset) ||
12830             tg3_nvram_read(tp, offset + 8, &val))
12831                 return;
12832
12833         offset += val - start;
12834
12835         vlen = strlen(tp->fw_ver);
12836
12837         tp->fw_ver[vlen++] = ',';
12838         tp->fw_ver[vlen++] = ' ';
12839
12840         for (i = 0; i < 4; i++) {
12841                 __be32 v;
12842                 if (tg3_nvram_read_be32(tp, offset, &v))
12843                         return;
12844
12845                 offset += sizeof(v);
12846
12847                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12848                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12849                         break;
12850                 }
12851
12852                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12853                 vlen += sizeof(v);
12854         }
12855 }
12856
12857 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12858 {
12859         int vlen;
12860         u32 apedata;
12861
12862         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12863             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
12864                 return;
12865
12866         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12867         if (apedata != APE_SEG_SIG_MAGIC)
12868                 return;
12869
12870         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12871         if (!(apedata & APE_FW_STATUS_READY))
12872                 return;
12873
12874         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12875
12876         vlen = strlen(tp->fw_ver);
12877
12878         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12879                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12880                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12881                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12882                  (apedata & APE_FW_VERSION_BLDMSK));
12883 }
12884
12885 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12886 {
12887         u32 val;
12888         bool vpd_vers = false;
12889
12890         if (tp->fw_ver[0] != 0)
12891                 vpd_vers = true;
12892
12893         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12894                 strcat(tp->fw_ver, "sb");
12895                 return;
12896         }
12897
12898         if (tg3_nvram_read(tp, 0, &val))
12899                 return;
12900
12901         if (val == TG3_EEPROM_MAGIC)
12902                 tg3_read_bc_ver(tp);
12903         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12904                 tg3_read_sb_ver(tp, val);
12905         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12906                 tg3_read_hwsb_ver(tp);
12907         else
12908                 return;
12909
12910         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12911              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
12912                 goto done;
12913
12914         tg3_read_mgmtfw_ver(tp);
12915
12916 done:
12917         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12918 }
12919
12920 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12921
12922 static int __devinit tg3_get_invariants(struct tg3 *tp)
12923 {
12924         static struct pci_device_id write_reorder_chipsets[] = {
12925                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12926                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12927                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12928                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12929                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12930                              PCI_DEVICE_ID_VIA_8385_0) },
12931                 { },
12932         };
12933         u32 misc_ctrl_reg;
12934         u32 pci_state_reg, grc_misc_cfg;
12935         u32 val;
12936         u16 pci_cmd;
12937         int err;
12938
12939         /* Force memory write invalidate off.  If we leave it on,
12940          * then on 5700_BX chips we have to enable a workaround.
12941          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12942          * to match the cacheline size.  The Broadcom driver have this
12943          * workaround but turns MWI off all the times so never uses
12944          * it.  This seems to suggest that the workaround is insufficient.
12945          */
12946         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12947         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12948         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12949
12950         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12951          * has the register indirect write enable bit set before
12952          * we try to access any of the MMIO registers.  It is also
12953          * critical that the PCI-X hw workaround situation is decided
12954          * before that as well.
12955          */
12956         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12957                               &misc_ctrl_reg);
12958
12959         tp->pci_chip_rev_id = (misc_ctrl_reg >>
12960                                MISC_HOST_CTRL_CHIPREV_SHIFT);
12961         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12962                 u32 prod_id_asic_rev;
12963
12964                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12965                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12966                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724)
12967                         pci_read_config_dword(tp->pdev,
12968                                               TG3PCI_GEN2_PRODID_ASICREV,
12969                                               &prod_id_asic_rev);
12970                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
12971                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
12972                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
12973                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
12974                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
12975                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12976                         pci_read_config_dword(tp->pdev,
12977                                               TG3PCI_GEN15_PRODID_ASICREV,
12978                                               &prod_id_asic_rev);
12979                 else
12980                         pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12981                                               &prod_id_asic_rev);
12982
12983                 tp->pci_chip_rev_id = prod_id_asic_rev;
12984         }
12985
12986         /* Wrong chip ID in 5752 A0. This code can be removed later
12987          * as A0 is not in production.
12988          */
12989         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12990                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12991
12992         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12993          * we need to disable memory and use config. cycles
12994          * only to access all registers. The 5702/03 chips
12995          * can mistakenly decode the special cycles from the
12996          * ICH chipsets as memory write cycles, causing corruption
12997          * of register and memory space. Only certain ICH bridges
12998          * will drive special cycles with non-zero data during the
12999          * address phase which can fall within the 5703's address
13000          * range. This is not an ICH bug as the PCI spec allows
13001          * non-zero address during special cycles. However, only
13002          * these ICH bridges are known to drive non-zero addresses
13003          * during special cycles.
13004          *
13005          * Since special cycles do not cross PCI bridges, we only
13006          * enable this workaround if the 5703 is on the secondary
13007          * bus of these ICH bridges.
13008          */
13009         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
13010             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
13011                 static struct tg3_dev_id {
13012                         u32     vendor;
13013                         u32     device;
13014                         u32     rev;
13015                 } ich_chipsets[] = {
13016                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
13017                           PCI_ANY_ID },
13018                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
13019                           PCI_ANY_ID },
13020                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
13021                           0xa },
13022                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
13023                           PCI_ANY_ID },
13024                         { },
13025                 };
13026                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
13027                 struct pci_dev *bridge = NULL;
13028
13029                 while (pci_id->vendor != 0) {
13030                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
13031                                                 bridge);
13032                         if (!bridge) {
13033                                 pci_id++;
13034                                 continue;
13035                         }
13036                         if (pci_id->rev != PCI_ANY_ID) {
13037                                 if (bridge->revision > pci_id->rev)
13038                                         continue;
13039                         }
13040                         if (bridge->subordinate &&
13041                             (bridge->subordinate->number ==
13042                              tp->pdev->bus->number)) {
13043
13044                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
13045                                 pci_dev_put(bridge);
13046                                 break;
13047                         }
13048                 }
13049         }
13050
13051         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
13052                 static struct tg3_dev_id {
13053                         u32     vendor;
13054                         u32     device;
13055                 } bridge_chipsets[] = {
13056                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
13057                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
13058                         { },
13059                 };
13060                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
13061                 struct pci_dev *bridge = NULL;
13062
13063                 while (pci_id->vendor != 0) {
13064                         bridge = pci_get_device(pci_id->vendor,
13065                                                 pci_id->device,
13066                                                 bridge);
13067                         if (!bridge) {
13068                                 pci_id++;
13069                                 continue;
13070                         }
13071                         if (bridge->subordinate &&
13072                             (bridge->subordinate->number <=
13073                              tp->pdev->bus->number) &&
13074                             (bridge->subordinate->subordinate >=
13075                              tp->pdev->bus->number)) {
13076                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
13077                                 pci_dev_put(bridge);
13078                                 break;
13079                         }
13080                 }
13081         }
13082
13083         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
13084          * DMA addresses > 40-bit. This bridge may have other additional
13085          * 57xx devices behind it in some 4-port NIC designs for example.
13086          * Any tg3 device found behind the bridge will also need the 40-bit
13087          * DMA workaround.
13088          */
13089         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
13090             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13091                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
13092                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13093                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
13094         }
13095         else {
13096                 struct pci_dev *bridge = NULL;
13097
13098                 do {
13099                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
13100                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
13101                                                 bridge);
13102                         if (bridge && bridge->subordinate &&
13103                             (bridge->subordinate->number <=
13104                              tp->pdev->bus->number) &&
13105                             (bridge->subordinate->subordinate >=
13106                              tp->pdev->bus->number)) {
13107                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13108                                 pci_dev_put(bridge);
13109                                 break;
13110                         }
13111                 } while (bridge);
13112         }
13113
13114         /* Initialize misc host control in PCI block. */
13115         tp->misc_host_ctrl |= (misc_ctrl_reg &
13116                                MISC_HOST_CTRL_CHIPREV);
13117         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13118                                tp->misc_host_ctrl);
13119
13120         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13121             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13122             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13123                 tp->pdev_peer = tg3_find_peer(tp);
13124
13125         /* Intentionally exclude ASIC_REV_5906 */
13126         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13127             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13128             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13129             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13130             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13131             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13132             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13133             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13134                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13135
13136         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13137             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13138             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13139             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13140             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13141                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13142
13143         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13144             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13145                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13146
13147         /* 5700 B0 chips do not support checksumming correctly due
13148          * to hardware bugs.
13149          */
13150         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13151                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13152         else {
13153                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13154                 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
13155                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13156                         tp->dev->features |= NETIF_F_IPV6_CSUM;
13157         }
13158
13159         /* Determine TSO capabilities */
13160         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13161             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13162                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13163         else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13164                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13165                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13166         else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13167                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13168                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13169                     tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13170                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13171         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13172                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13173                    tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13174                 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13175                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13176                         tp->fw_needed = FIRMWARE_TG3TSO5;
13177                 else
13178                         tp->fw_needed = FIRMWARE_TG3TSO;
13179         }
13180
13181         tp->irq_max = 1;
13182
13183         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13184                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13185                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13186                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13187                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13188                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13189                      tp->pdev_peer == tp->pdev))
13190                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13191
13192                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13193                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13194                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13195                 }
13196
13197                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13198                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13199                         tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13200                         tp->irq_max = TG3_IRQ_MAX_VECS;
13201                 }
13202         }
13203
13204         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13205             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13206                 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13207         else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13208                 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13209                 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13210         }
13211
13212         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13213             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13214                 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13215
13216         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13217              (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13218                  (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13219                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13220
13221         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13222                               &pci_state_reg);
13223
13224         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13225         if (tp->pcie_cap != 0) {
13226                 u16 lnkctl;
13227
13228                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13229
13230                 pcie_set_readrq(tp->pdev, 4096);
13231
13232                 pci_read_config_word(tp->pdev,
13233                                      tp->pcie_cap + PCI_EXP_LNKCTL,
13234                                      &lnkctl);
13235                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13236                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13237                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13238                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13239                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13240                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13241                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13242                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13243                 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13244                         tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13245                 }
13246         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13247                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13248         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13249                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13250                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13251                 if (!tp->pcix_cap) {
13252                         dev_err(&tp->pdev->dev,
13253                                 "Cannot find PCI-X capability, aborting\n");
13254                         return -EIO;
13255                 }
13256
13257                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13258                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13259         }
13260
13261         /* If we have an AMD 762 or VIA K8T800 chipset, write
13262          * reordering to the mailbox registers done by the host
13263          * controller can cause major troubles.  We read back from
13264          * every mailbox register write to force the writes to be
13265          * posted to the chip in order.
13266          */
13267         if (pci_dev_present(write_reorder_chipsets) &&
13268             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13269                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13270
13271         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13272                              &tp->pci_cacheline_sz);
13273         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13274                              &tp->pci_lat_timer);
13275         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13276             tp->pci_lat_timer < 64) {
13277                 tp->pci_lat_timer = 64;
13278                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13279                                       tp->pci_lat_timer);
13280         }
13281
13282         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13283                 /* 5700 BX chips need to have their TX producer index
13284                  * mailboxes written twice to workaround a bug.
13285                  */
13286                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13287
13288                 /* If we are in PCI-X mode, enable register write workaround.
13289                  *
13290                  * The workaround is to use indirect register accesses
13291                  * for all chip writes not to mailbox registers.
13292                  */
13293                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13294                         u32 pm_reg;
13295
13296                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13297
13298                         /* The chip can have it's power management PCI config
13299                          * space registers clobbered due to this bug.
13300                          * So explicitly force the chip into D0 here.
13301                          */
13302                         pci_read_config_dword(tp->pdev,
13303                                               tp->pm_cap + PCI_PM_CTRL,
13304                                               &pm_reg);
13305                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13306                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13307                         pci_write_config_dword(tp->pdev,
13308                                                tp->pm_cap + PCI_PM_CTRL,
13309                                                pm_reg);
13310
13311                         /* Also, force SERR#/PERR# in PCI command. */
13312                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13313                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13314                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13315                 }
13316         }
13317
13318         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13319                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13320         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13321                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13322
13323         /* Chip-specific fixup from Broadcom driver */
13324         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13325             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13326                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13327                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13328         }
13329
13330         /* Default fast path register access methods */
13331         tp->read32 = tg3_read32;
13332         tp->write32 = tg3_write32;
13333         tp->read32_mbox = tg3_read32;
13334         tp->write32_mbox = tg3_write32;
13335         tp->write32_tx_mbox = tg3_write32;
13336         tp->write32_rx_mbox = tg3_write32;
13337
13338         /* Various workaround register access methods */
13339         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13340                 tp->write32 = tg3_write_indirect_reg32;
13341         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13342                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13343                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13344                 /*
13345                  * Back to back register writes can cause problems on these
13346                  * chips, the workaround is to read back all reg writes
13347                  * except those to mailbox regs.
13348                  *
13349                  * See tg3_write_indirect_reg32().
13350                  */
13351                 tp->write32 = tg3_write_flush_reg32;
13352         }
13353
13354         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13355             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13356                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13357                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13358                         tp->write32_rx_mbox = tg3_write_flush_reg32;
13359         }
13360
13361         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13362                 tp->read32 = tg3_read_indirect_reg32;
13363                 tp->write32 = tg3_write_indirect_reg32;
13364                 tp->read32_mbox = tg3_read_indirect_mbox;
13365                 tp->write32_mbox = tg3_write_indirect_mbox;
13366                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13367                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13368
13369                 iounmap(tp->regs);
13370                 tp->regs = NULL;
13371
13372                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13373                 pci_cmd &= ~PCI_COMMAND_MEMORY;
13374                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13375         }
13376         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13377                 tp->read32_mbox = tg3_read32_mbox_5906;
13378                 tp->write32_mbox = tg3_write32_mbox_5906;
13379                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13380                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13381         }
13382
13383         if (tp->write32 == tg3_write_indirect_reg32 ||
13384             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13385              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13386               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13387                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13388
13389         /* Get eeprom hw config before calling tg3_set_power_state().
13390          * In particular, the TG3_FLG2_IS_NIC flag must be
13391          * determined before calling tg3_set_power_state() so that
13392          * we know whether or not to switch out of Vaux power.
13393          * When the flag is set, it means that GPIO1 is used for eeprom
13394          * write protect and also implies that it is a LOM where GPIOs
13395          * are not used to switch power.
13396          */
13397         tg3_get_eeprom_hw_cfg(tp);
13398
13399         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13400                 /* Allow reads and writes to the
13401                  * APE register and memory space.
13402                  */
13403                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13404                                  PCISTATE_ALLOW_APE_SHMEM_WR;
13405                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13406                                        pci_state_reg);
13407         }
13408
13409         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13410             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13411             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13412             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13413             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13414             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13415                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13416
13417         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13418          * GPIO1 driven high will bring 5700's external PHY out of reset.
13419          * It is also used as eeprom write protect on LOMs.
13420          */
13421         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13422         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13423             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13424                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13425                                        GRC_LCLCTRL_GPIO_OUTPUT1);
13426         /* Unused GPIO3 must be driven as output on 5752 because there
13427          * are no pull-up resistors on unused GPIO pins.
13428          */
13429         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13430                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13431
13432         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13433             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13434             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13435                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13436
13437         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13438             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13439                 /* Turn off the debug UART. */
13440                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13441                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13442                         /* Keep VMain power. */
13443                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13444                                               GRC_LCLCTRL_GPIO_OUTPUT0;
13445         }
13446
13447         /* Force the chip into D0. */
13448         err = tg3_set_power_state(tp, PCI_D0);
13449         if (err) {
13450                 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
13451                 return err;
13452         }
13453
13454         /* Derive initial jumbo mode from MTU assigned in
13455          * ether_setup() via the alloc_etherdev() call
13456          */
13457         if (tp->dev->mtu > ETH_DATA_LEN &&
13458             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13459                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13460
13461         /* Determine WakeOnLan speed to use. */
13462         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13463             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13464             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13465             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13466                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13467         } else {
13468                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13469         }
13470
13471         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13472                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
13473
13474         /* A few boards don't want Ethernet@WireSpeed phy feature */
13475         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13476             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13477              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13478              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13479             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
13480             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
13481                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
13482
13483         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13484             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13485                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
13486         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13487                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
13488
13489         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13490             !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
13491             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13492             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13493             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
13494             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
13495                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13496                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13497                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13498                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13499                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13500                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13501                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
13502                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13503                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
13504                 } else
13505                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
13506         }
13507
13508         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13509             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13510                 tp->phy_otp = tg3_read_otp_phycfg(tp);
13511                 if (tp->phy_otp == 0)
13512                         tp->phy_otp = TG3_OTP_DEFAULT;
13513         }
13514
13515         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13516                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13517         else
13518                 tp->mi_mode = MAC_MI_MODE_BASE;
13519
13520         tp->coalesce_mode = 0;
13521         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13522             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13523                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13524
13525         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13526             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13527                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13528
13529         err = tg3_mdio_init(tp);
13530         if (err)
13531                 return err;
13532
13533         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
13534             (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0 ||
13535                  (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
13536                 return -ENOTSUPP;
13537
13538         /* Initialize data/descriptor byte/word swapping. */
13539         val = tr32(GRC_MODE);
13540         val &= GRC_MODE_HOST_STACKUP;
13541         tw32(GRC_MODE, val | tp->grc_mode);
13542
13543         tg3_switch_clocks(tp);
13544
13545         /* Clear this out for sanity. */
13546         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13547
13548         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13549                               &pci_state_reg);
13550         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13551             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13552                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13553
13554                 if (chiprevid == CHIPREV_ID_5701_A0 ||
13555                     chiprevid == CHIPREV_ID_5701_B0 ||
13556                     chiprevid == CHIPREV_ID_5701_B2 ||
13557                     chiprevid == CHIPREV_ID_5701_B5) {
13558                         void __iomem *sram_base;
13559
13560                         /* Write some dummy words into the SRAM status block
13561                          * area, see if it reads back correctly.  If the return
13562                          * value is bad, force enable the PCIX workaround.
13563                          */
13564                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13565
13566                         writel(0x00000000, sram_base);
13567                         writel(0x00000000, sram_base + 4);
13568                         writel(0xffffffff, sram_base + 4);
13569                         if (readl(sram_base) != 0x00000000)
13570                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13571                 }
13572         }
13573
13574         udelay(50);
13575         tg3_nvram_init(tp);
13576
13577         grc_misc_cfg = tr32(GRC_MISC_CFG);
13578         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13579
13580         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13581             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13582              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13583                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13584
13585         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13586             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13587                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13588         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13589                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13590                                       HOSTCC_MODE_CLRTICK_TXBD);
13591
13592                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13593                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13594                                        tp->misc_host_ctrl);
13595         }
13596
13597         /* Preserve the APE MAC_MODE bits */
13598         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13599                 tp->mac_mode = tr32(MAC_MODE) |
13600                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13601         else
13602                 tp->mac_mode = TG3_DEF_MAC_MODE;
13603
13604         /* these are limited to 10/100 only */
13605         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13606              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13607             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13608              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13609              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13610               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13611               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13612             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13613              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13614               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13615               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13616             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13617             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13618             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
13619             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
13620                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13621
13622         err = tg3_phy_probe(tp);
13623         if (err) {
13624                 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
13625                 /* ... but do not return immediately ... */
13626                 tg3_mdio_fini(tp);
13627         }
13628
13629         tg3_read_partno(tp);
13630         tg3_read_fw_ver(tp);
13631
13632         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13633                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13634         } else {
13635                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13636                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13637                 else
13638                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13639         }
13640
13641         /* 5700 {AX,BX} chips have a broken status block link
13642          * change bit implementation, so we must use the
13643          * status register in those cases.
13644          */
13645         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13646                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13647         else
13648                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13649
13650         /* The led_ctrl is set during tg3_phy_probe, here we might
13651          * have to force the link status polling mechanism based
13652          * upon subsystem IDs.
13653          */
13654         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13655             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13656             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13657                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13658                                   TG3_FLAG_USE_LINKCHG_REG);
13659         }
13660
13661         /* For all SERDES we poll the MAC status register. */
13662         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13663                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13664         else
13665                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13666
13667         tp->rx_offset = NET_IP_ALIGN;
13668         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13669             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13670                 tp->rx_offset = 0;
13671
13672         tp->rx_std_max_post = TG3_RX_RING_SIZE;
13673
13674         /* Increment the rx prod index on the rx std ring by at most
13675          * 8 for these chips to workaround hw errata.
13676          */
13677         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13678             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13679             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13680                 tp->rx_std_max_post = 8;
13681
13682         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13683                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13684                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
13685
13686         return err;
13687 }
13688
13689 #ifdef CONFIG_SPARC
13690 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13691 {
13692         struct net_device *dev = tp->dev;
13693         struct pci_dev *pdev = tp->pdev;
13694         struct device_node *dp = pci_device_to_OF_node(pdev);
13695         const unsigned char *addr;
13696         int len;
13697
13698         addr = of_get_property(dp, "local-mac-address", &len);
13699         if (addr && len == 6) {
13700                 memcpy(dev->dev_addr, addr, 6);
13701                 memcpy(dev->perm_addr, dev->dev_addr, 6);
13702                 return 0;
13703         }
13704         return -ENODEV;
13705 }
13706
13707 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13708 {
13709         struct net_device *dev = tp->dev;
13710
13711         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13712         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13713         return 0;
13714 }
13715 #endif
13716
13717 static int __devinit tg3_get_device_address(struct tg3 *tp)
13718 {
13719         struct net_device *dev = tp->dev;
13720         u32 hi, lo, mac_offset;
13721         int addr_ok = 0;
13722
13723 #ifdef CONFIG_SPARC
13724         if (!tg3_get_macaddr_sparc(tp))
13725                 return 0;
13726 #endif
13727
13728         mac_offset = 0x7c;
13729         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13730             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13731                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13732                         mac_offset = 0xcc;
13733                 if (tg3_nvram_lock(tp))
13734                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13735                 else
13736                         tg3_nvram_unlock(tp);
13737         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13738                 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13739                         mac_offset = 0xcc;
13740         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13741                 mac_offset = 0x10;
13742
13743         /* First try to get it from MAC address mailbox. */
13744         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13745         if ((hi >> 16) == 0x484b) {
13746                 dev->dev_addr[0] = (hi >>  8) & 0xff;
13747                 dev->dev_addr[1] = (hi >>  0) & 0xff;
13748
13749                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13750                 dev->dev_addr[2] = (lo >> 24) & 0xff;
13751                 dev->dev_addr[3] = (lo >> 16) & 0xff;
13752                 dev->dev_addr[4] = (lo >>  8) & 0xff;
13753                 dev->dev_addr[5] = (lo >>  0) & 0xff;
13754
13755                 /* Some old bootcode may report a 0 MAC address in SRAM */
13756                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13757         }
13758         if (!addr_ok) {
13759                 /* Next, try NVRAM. */
13760                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13761                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13762                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13763                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13764                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13765                 }
13766                 /* Finally just fetch it out of the MAC control regs. */
13767                 else {
13768                         hi = tr32(MAC_ADDR_0_HIGH);
13769                         lo = tr32(MAC_ADDR_0_LOW);
13770
13771                         dev->dev_addr[5] = lo & 0xff;
13772                         dev->dev_addr[4] = (lo >> 8) & 0xff;
13773                         dev->dev_addr[3] = (lo >> 16) & 0xff;
13774                         dev->dev_addr[2] = (lo >> 24) & 0xff;
13775                         dev->dev_addr[1] = hi & 0xff;
13776                         dev->dev_addr[0] = (hi >> 8) & 0xff;
13777                 }
13778         }
13779
13780         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13781 #ifdef CONFIG_SPARC
13782                 if (!tg3_get_default_macaddr_sparc(tp))
13783                         return 0;
13784 #endif
13785                 return -EINVAL;
13786         }
13787         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13788         return 0;
13789 }
13790
13791 #define BOUNDARY_SINGLE_CACHELINE       1
13792 #define BOUNDARY_MULTI_CACHELINE        2
13793
13794 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13795 {
13796         int cacheline_size;
13797         u8 byte;
13798         int goal;
13799
13800         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13801         if (byte == 0)
13802                 cacheline_size = 1024;
13803         else
13804                 cacheline_size = (int) byte * 4;
13805
13806         /* On 5703 and later chips, the boundary bits have no
13807          * effect.
13808          */
13809         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13810             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13811             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13812                 goto out;
13813
13814 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13815         goal = BOUNDARY_MULTI_CACHELINE;
13816 #else
13817 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13818         goal = BOUNDARY_SINGLE_CACHELINE;
13819 #else
13820         goal = 0;
13821 #endif
13822 #endif
13823
13824         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13825             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13826                 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13827                 goto out;
13828         }
13829
13830         if (!goal)
13831                 goto out;
13832
13833         /* PCI controllers on most RISC systems tend to disconnect
13834          * when a device tries to burst across a cache-line boundary.
13835          * Therefore, letting tg3 do so just wastes PCI bandwidth.
13836          *
13837          * Unfortunately, for PCI-E there are only limited
13838          * write-side controls for this, and thus for reads
13839          * we will still get the disconnects.  We'll also waste
13840          * these PCI cycles for both read and write for chips
13841          * other than 5700 and 5701 which do not implement the
13842          * boundary bits.
13843          */
13844         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13845             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13846                 switch (cacheline_size) {
13847                 case 16:
13848                 case 32:
13849                 case 64:
13850                 case 128:
13851                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13852                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13853                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13854                         } else {
13855                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13856                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13857                         }
13858                         break;
13859
13860                 case 256:
13861                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13862                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13863                         break;
13864
13865                 default:
13866                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13867                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13868                         break;
13869                 }
13870         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13871                 switch (cacheline_size) {
13872                 case 16:
13873                 case 32:
13874                 case 64:
13875                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13876                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13877                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13878                                 break;
13879                         }
13880                         /* fallthrough */
13881                 case 128:
13882                 default:
13883                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13884                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13885                         break;
13886                 }
13887         } else {
13888                 switch (cacheline_size) {
13889                 case 16:
13890                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13891                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13892                                         DMA_RWCTRL_WRITE_BNDRY_16);
13893                                 break;
13894                         }
13895                         /* fallthrough */
13896                 case 32:
13897                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13898                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13899                                         DMA_RWCTRL_WRITE_BNDRY_32);
13900                                 break;
13901                         }
13902                         /* fallthrough */
13903                 case 64:
13904                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13905                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13906                                         DMA_RWCTRL_WRITE_BNDRY_64);
13907                                 break;
13908                         }
13909                         /* fallthrough */
13910                 case 128:
13911                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13912                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13913                                         DMA_RWCTRL_WRITE_BNDRY_128);
13914                                 break;
13915                         }
13916                         /* fallthrough */
13917                 case 256:
13918                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
13919                                 DMA_RWCTRL_WRITE_BNDRY_256);
13920                         break;
13921                 case 512:
13922                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
13923                                 DMA_RWCTRL_WRITE_BNDRY_512);
13924                         break;
13925                 case 1024:
13926                 default:
13927                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13928                                 DMA_RWCTRL_WRITE_BNDRY_1024);
13929                         break;
13930                 }
13931         }
13932
13933 out:
13934         return val;
13935 }
13936
13937 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13938 {
13939         struct tg3_internal_buffer_desc test_desc;
13940         u32 sram_dma_descs;
13941         int i, ret;
13942
13943         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13944
13945         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13946         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13947         tw32(RDMAC_STATUS, 0);
13948         tw32(WDMAC_STATUS, 0);
13949
13950         tw32(BUFMGR_MODE, 0);
13951         tw32(FTQ_RESET, 0);
13952
13953         test_desc.addr_hi = ((u64) buf_dma) >> 32;
13954         test_desc.addr_lo = buf_dma & 0xffffffff;
13955         test_desc.nic_mbuf = 0x00002100;
13956         test_desc.len = size;
13957
13958         /*
13959          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13960          * the *second* time the tg3 driver was getting loaded after an
13961          * initial scan.
13962          *
13963          * Broadcom tells me:
13964          *   ...the DMA engine is connected to the GRC block and a DMA
13965          *   reset may affect the GRC block in some unpredictable way...
13966          *   The behavior of resets to individual blocks has not been tested.
13967          *
13968          * Broadcom noted the GRC reset will also reset all sub-components.
13969          */
13970         if (to_device) {
13971                 test_desc.cqid_sqid = (13 << 8) | 2;
13972
13973                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13974                 udelay(40);
13975         } else {
13976                 test_desc.cqid_sqid = (16 << 8) | 7;
13977
13978                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13979                 udelay(40);
13980         }
13981         test_desc.flags = 0x00000005;
13982
13983         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13984                 u32 val;
13985
13986                 val = *(((u32 *)&test_desc) + i);
13987                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13988                                        sram_dma_descs + (i * sizeof(u32)));
13989                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13990         }
13991         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13992
13993         if (to_device) {
13994                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13995         } else {
13996                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13997         }
13998
13999         ret = -ENODEV;
14000         for (i = 0; i < 40; i++) {
14001                 u32 val;
14002
14003                 if (to_device)
14004                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
14005                 else
14006                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
14007                 if ((val & 0xffff) == sram_dma_descs) {
14008                         ret = 0;
14009                         break;
14010                 }
14011
14012                 udelay(100);
14013         }
14014
14015         return ret;
14016 }
14017
14018 #define TEST_BUFFER_SIZE        0x2000
14019
14020 static int __devinit tg3_test_dma(struct tg3 *tp)
14021 {
14022         dma_addr_t buf_dma;
14023         u32 *buf, saved_dma_rwctrl;
14024         int ret = 0;
14025
14026         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
14027         if (!buf) {
14028                 ret = -ENOMEM;
14029                 goto out_nofree;
14030         }
14031
14032         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
14033                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
14034
14035         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
14036
14037         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14038             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
14039                 goto out;
14040
14041         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14042                 /* DMA read watermark not used on PCIE */
14043                 tp->dma_rwctrl |= 0x00180000;
14044         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
14045                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
14046                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
14047                         tp->dma_rwctrl |= 0x003f0000;
14048                 else
14049                         tp->dma_rwctrl |= 0x003f000f;
14050         } else {
14051                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14052                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
14053                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
14054                         u32 read_water = 0x7;
14055
14056                         /* If the 5704 is behind the EPB bridge, we can
14057                          * do the less restrictive ONE_DMA workaround for
14058                          * better performance.
14059                          */
14060                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
14061                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14062                                 tp->dma_rwctrl |= 0x8000;
14063                         else if (ccval == 0x6 || ccval == 0x7)
14064                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
14065
14066                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
14067                                 read_water = 4;
14068                         /* Set bit 23 to enable PCIX hw bug fix */
14069                         tp->dma_rwctrl |=
14070                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
14071                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
14072                                 (1 << 23);
14073                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
14074                         /* 5780 always in PCIX mode */
14075                         tp->dma_rwctrl |= 0x00144000;
14076                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
14077                         /* 5714 always in PCIX mode */
14078                         tp->dma_rwctrl |= 0x00148000;
14079                 } else {
14080                         tp->dma_rwctrl |= 0x001b000f;
14081                 }
14082         }
14083
14084         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14085             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14086                 tp->dma_rwctrl &= 0xfffffff0;
14087
14088         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14089             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
14090                 /* Remove this if it causes problems for some boards. */
14091                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
14092
14093                 /* On 5700/5701 chips, we need to set this bit.
14094                  * Otherwise the chip will issue cacheline transactions
14095                  * to streamable DMA memory with not all the byte
14096                  * enables turned on.  This is an error on several
14097                  * RISC PCI controllers, in particular sparc64.
14098                  *
14099                  * On 5703/5704 chips, this bit has been reassigned
14100                  * a different meaning.  In particular, it is used
14101                  * on those chips to enable a PCI-X workaround.
14102                  */
14103                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
14104         }
14105
14106         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14107
14108 #if 0
14109         /* Unneeded, already done by tg3_get_invariants.  */
14110         tg3_switch_clocks(tp);
14111 #endif
14112
14113         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14114             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14115                 goto out;
14116
14117         /* It is best to perform DMA test with maximum write burst size
14118          * to expose the 5700/5701 write DMA bug.
14119          */
14120         saved_dma_rwctrl = tp->dma_rwctrl;
14121         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14122         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14123
14124         while (1) {
14125                 u32 *p = buf, i;
14126
14127                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14128                         p[i] = i;
14129
14130                 /* Send the buffer to the chip. */
14131                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14132                 if (ret) {
14133                         dev_err(&tp->pdev->dev,
14134                                 "%s: Buffer write failed. err = %d\n",
14135                                 __func__, ret);
14136                         break;
14137                 }
14138
14139 #if 0
14140                 /* validate data reached card RAM correctly. */
14141                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14142                         u32 val;
14143                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
14144                         if (le32_to_cpu(val) != p[i]) {
14145                                 dev_err(&tp->pdev->dev,
14146                                         "%s: Buffer corrupted on device! "
14147                                         "(%d != %d)\n", __func__, val, i);
14148                                 /* ret = -ENODEV here? */
14149                         }
14150                         p[i] = 0;
14151                 }
14152 #endif
14153                 /* Now read it back. */
14154                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14155                 if (ret) {
14156                         dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
14157                                 "err = %d\n", __func__, ret);
14158                         break;
14159                 }
14160
14161                 /* Verify it. */
14162                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14163                         if (p[i] == i)
14164                                 continue;
14165
14166                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14167                             DMA_RWCTRL_WRITE_BNDRY_16) {
14168                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14169                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14170                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14171                                 break;
14172                         } else {
14173                                 dev_err(&tp->pdev->dev,
14174                                         "%s: Buffer corrupted on read back! "
14175                                         "(%d != %d)\n", __func__, p[i], i);
14176                                 ret = -ENODEV;
14177                                 goto out;
14178                         }
14179                 }
14180
14181                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14182                         /* Success. */
14183                         ret = 0;
14184                         break;
14185                 }
14186         }
14187         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14188             DMA_RWCTRL_WRITE_BNDRY_16) {
14189                 static struct pci_device_id dma_wait_state_chipsets[] = {
14190                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14191                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14192                         { },
14193                 };
14194
14195                 /* DMA test passed without adjusting DMA boundary,
14196                  * now look for chipsets that are known to expose the
14197                  * DMA bug without failing the test.
14198                  */
14199                 if (pci_dev_present(dma_wait_state_chipsets)) {
14200                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14201                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14202                 }
14203                 else
14204                         /* Safe to use the calculated DMA boundary. */
14205                         tp->dma_rwctrl = saved_dma_rwctrl;
14206
14207                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14208         }
14209
14210 out:
14211         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14212 out_nofree:
14213         return ret;
14214 }
14215
14216 static void __devinit tg3_init_link_config(struct tg3 *tp)
14217 {
14218         tp->link_config.advertising =
14219                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14220                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14221                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14222                  ADVERTISED_Autoneg | ADVERTISED_MII);
14223         tp->link_config.speed = SPEED_INVALID;
14224         tp->link_config.duplex = DUPLEX_INVALID;
14225         tp->link_config.autoneg = AUTONEG_ENABLE;
14226         tp->link_config.active_speed = SPEED_INVALID;
14227         tp->link_config.active_duplex = DUPLEX_INVALID;
14228         tp->link_config.phy_is_low_power = 0;
14229         tp->link_config.orig_speed = SPEED_INVALID;
14230         tp->link_config.orig_duplex = DUPLEX_INVALID;
14231         tp->link_config.orig_autoneg = AUTONEG_INVALID;
14232 }
14233
14234 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14235 {
14236         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14237             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
14238                 tp->bufmgr_config.mbuf_read_dma_low_water =
14239                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14240                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14241                         DEFAULT_MB_MACRX_LOW_WATER_57765;
14242                 tp->bufmgr_config.mbuf_high_water =
14243                         DEFAULT_MB_HIGH_WATER_57765;
14244
14245                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14246                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14247                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14248                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14249                 tp->bufmgr_config.mbuf_high_water_jumbo =
14250                         DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14251         } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14252                 tp->bufmgr_config.mbuf_read_dma_low_water =
14253                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14254                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14255                         DEFAULT_MB_MACRX_LOW_WATER_5705;
14256                 tp->bufmgr_config.mbuf_high_water =
14257                         DEFAULT_MB_HIGH_WATER_5705;
14258                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14259                         tp->bufmgr_config.mbuf_mac_rx_low_water =
14260                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
14261                         tp->bufmgr_config.mbuf_high_water =
14262                                 DEFAULT_MB_HIGH_WATER_5906;
14263                 }
14264
14265                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14266                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14267                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14268                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14269                 tp->bufmgr_config.mbuf_high_water_jumbo =
14270                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14271         } else {
14272                 tp->bufmgr_config.mbuf_read_dma_low_water =
14273                         DEFAULT_MB_RDMA_LOW_WATER;
14274                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14275                         DEFAULT_MB_MACRX_LOW_WATER;
14276                 tp->bufmgr_config.mbuf_high_water =
14277                         DEFAULT_MB_HIGH_WATER;
14278
14279                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14280                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14281                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14282                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14283                 tp->bufmgr_config.mbuf_high_water_jumbo =
14284                         DEFAULT_MB_HIGH_WATER_JUMBO;
14285         }
14286
14287         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14288         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14289 }
14290
14291 static char * __devinit tg3_phy_string(struct tg3 *tp)
14292 {
14293         switch (tp->phy_id & TG3_PHY_ID_MASK) {
14294         case TG3_PHY_ID_BCM5400:        return "5400";
14295         case TG3_PHY_ID_BCM5401:        return "5401";
14296         case TG3_PHY_ID_BCM5411:        return "5411";
14297         case TG3_PHY_ID_BCM5701:        return "5701";
14298         case TG3_PHY_ID_BCM5703:        return "5703";
14299         case TG3_PHY_ID_BCM5704:        return "5704";
14300         case TG3_PHY_ID_BCM5705:        return "5705";
14301         case TG3_PHY_ID_BCM5750:        return "5750";
14302         case TG3_PHY_ID_BCM5752:        return "5752";
14303         case TG3_PHY_ID_BCM5714:        return "5714";
14304         case TG3_PHY_ID_BCM5780:        return "5780";
14305         case TG3_PHY_ID_BCM5755:        return "5755";
14306         case TG3_PHY_ID_BCM5787:        return "5787";
14307         case TG3_PHY_ID_BCM5784:        return "5784";
14308         case TG3_PHY_ID_BCM5756:        return "5722/5756";
14309         case TG3_PHY_ID_BCM5906:        return "5906";
14310         case TG3_PHY_ID_BCM5761:        return "5761";
14311         case TG3_PHY_ID_BCM5718C:       return "5718C";
14312         case TG3_PHY_ID_BCM5718S:       return "5718S";
14313         case TG3_PHY_ID_BCM57765:       return "57765";
14314         case TG3_PHY_ID_BCM8002:        return "8002/serdes";
14315         case 0:                 return "serdes";
14316         default:                return "unknown";
14317         }
14318 }
14319
14320 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14321 {
14322         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14323                 strcpy(str, "PCI Express");
14324                 return str;
14325         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14326                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14327
14328                 strcpy(str, "PCIX:");
14329
14330                 if ((clock_ctrl == 7) ||
14331                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14332                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14333                         strcat(str, "133MHz");
14334                 else if (clock_ctrl == 0)
14335                         strcat(str, "33MHz");
14336                 else if (clock_ctrl == 2)
14337                         strcat(str, "50MHz");
14338                 else if (clock_ctrl == 4)
14339                         strcat(str, "66MHz");
14340                 else if (clock_ctrl == 6)
14341                         strcat(str, "100MHz");
14342         } else {
14343                 strcpy(str, "PCI:");
14344                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14345                         strcat(str, "66MHz");
14346                 else
14347                         strcat(str, "33MHz");
14348         }
14349         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14350                 strcat(str, ":32-bit");
14351         else
14352                 strcat(str, ":64-bit");
14353         return str;
14354 }
14355
14356 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14357 {
14358         struct pci_dev *peer;
14359         unsigned int func, devnr = tp->pdev->devfn & ~7;
14360
14361         for (func = 0; func < 8; func++) {
14362                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14363                 if (peer && peer != tp->pdev)
14364                         break;
14365                 pci_dev_put(peer);
14366         }
14367         /* 5704 can be configured in single-port mode, set peer to
14368          * tp->pdev in that case.
14369          */
14370         if (!peer) {
14371                 peer = tp->pdev;
14372                 return peer;
14373         }
14374
14375         /*
14376          * We don't need to keep the refcount elevated; there's no way
14377          * to remove one half of this device without removing the other
14378          */
14379         pci_dev_put(peer);
14380
14381         return peer;
14382 }
14383
14384 static void __devinit tg3_init_coal(struct tg3 *tp)
14385 {
14386         struct ethtool_coalesce *ec = &tp->coal;
14387
14388         memset(ec, 0, sizeof(*ec));
14389         ec->cmd = ETHTOOL_GCOALESCE;
14390         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14391         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14392         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14393         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14394         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14395         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14396         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14397         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14398         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14399
14400         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14401                                  HOSTCC_MODE_CLRTICK_TXBD)) {
14402                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14403                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14404                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14405                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14406         }
14407
14408         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14409                 ec->rx_coalesce_usecs_irq = 0;
14410                 ec->tx_coalesce_usecs_irq = 0;
14411                 ec->stats_block_coalesce_usecs = 0;
14412         }
14413 }
14414
14415 static const struct net_device_ops tg3_netdev_ops = {
14416         .ndo_open               = tg3_open,
14417         .ndo_stop               = tg3_close,
14418         .ndo_start_xmit         = tg3_start_xmit,
14419         .ndo_get_stats          = tg3_get_stats,
14420         .ndo_validate_addr      = eth_validate_addr,
14421         .ndo_set_multicast_list = tg3_set_rx_mode,
14422         .ndo_set_mac_address    = tg3_set_mac_addr,
14423         .ndo_do_ioctl           = tg3_ioctl,
14424         .ndo_tx_timeout         = tg3_tx_timeout,
14425         .ndo_change_mtu         = tg3_change_mtu,
14426 #if TG3_VLAN_TAG_USED
14427         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14428 #endif
14429 #ifdef CONFIG_NET_POLL_CONTROLLER
14430         .ndo_poll_controller    = tg3_poll_controller,
14431 #endif
14432 };
14433
14434 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14435         .ndo_open               = tg3_open,
14436         .ndo_stop               = tg3_close,
14437         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
14438         .ndo_get_stats          = tg3_get_stats,
14439         .ndo_validate_addr      = eth_validate_addr,
14440         .ndo_set_multicast_list = tg3_set_rx_mode,
14441         .ndo_set_mac_address    = tg3_set_mac_addr,
14442         .ndo_do_ioctl           = tg3_ioctl,
14443         .ndo_tx_timeout         = tg3_tx_timeout,
14444         .ndo_change_mtu         = tg3_change_mtu,
14445 #if TG3_VLAN_TAG_USED
14446         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14447 #endif
14448 #ifdef CONFIG_NET_POLL_CONTROLLER
14449         .ndo_poll_controller    = tg3_poll_controller,
14450 #endif
14451 };
14452
14453 static int __devinit tg3_init_one(struct pci_dev *pdev,
14454                                   const struct pci_device_id *ent)
14455 {
14456         struct net_device *dev;
14457         struct tg3 *tp;
14458         int i, err, pm_cap;
14459         u32 sndmbx, rcvmbx, intmbx;
14460         char str[40];
14461         u64 dma_mask, persist_dma_mask;
14462
14463         printk_once(KERN_INFO "%s\n", version);
14464
14465         err = pci_enable_device(pdev);
14466         if (err) {
14467                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
14468                 return err;
14469         }
14470
14471         err = pci_request_regions(pdev, DRV_MODULE_NAME);
14472         if (err) {
14473                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
14474                 goto err_out_disable_pdev;
14475         }
14476
14477         pci_set_master(pdev);
14478
14479         /* Find power-management capability. */
14480         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14481         if (pm_cap == 0) {
14482                 dev_err(&pdev->dev,
14483                         "Cannot find Power Management capability, aborting\n");
14484                 err = -EIO;
14485                 goto err_out_free_res;
14486         }
14487
14488         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14489         if (!dev) {
14490                 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
14491                 err = -ENOMEM;
14492                 goto err_out_free_res;
14493         }
14494
14495         SET_NETDEV_DEV(dev, &pdev->dev);
14496
14497 #if TG3_VLAN_TAG_USED
14498         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14499 #endif
14500
14501         tp = netdev_priv(dev);
14502         tp->pdev = pdev;
14503         tp->dev = dev;
14504         tp->pm_cap = pm_cap;
14505         tp->rx_mode = TG3_DEF_RX_MODE;
14506         tp->tx_mode = TG3_DEF_TX_MODE;
14507
14508         if (tg3_debug > 0)
14509                 tp->msg_enable = tg3_debug;
14510         else
14511                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14512
14513         /* The word/byte swap controls here control register access byte
14514          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
14515          * setting below.
14516          */
14517         tp->misc_host_ctrl =
14518                 MISC_HOST_CTRL_MASK_PCI_INT |
14519                 MISC_HOST_CTRL_WORD_SWAP |
14520                 MISC_HOST_CTRL_INDIR_ACCESS |
14521                 MISC_HOST_CTRL_PCISTATE_RW;
14522
14523         /* The NONFRM (non-frame) byte/word swap controls take effect
14524          * on descriptor entries, anything which isn't packet data.
14525          *
14526          * The StrongARM chips on the board (one for tx, one for rx)
14527          * are running in big-endian mode.
14528          */
14529         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14530                         GRC_MODE_WSWAP_NONFRM_DATA);
14531 #ifdef __BIG_ENDIAN
14532         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14533 #endif
14534         spin_lock_init(&tp->lock);
14535         spin_lock_init(&tp->indirect_lock);
14536         INIT_WORK(&tp->reset_task, tg3_reset_task);
14537
14538         tp->regs = pci_ioremap_bar(pdev, BAR_0);
14539         if (!tp->regs) {
14540                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
14541                 err = -ENOMEM;
14542                 goto err_out_free_dev;
14543         }
14544
14545         tg3_init_link_config(tp);
14546
14547         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14548         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14549
14550         dev->ethtool_ops = &tg3_ethtool_ops;
14551         dev->watchdog_timeo = TG3_TX_TIMEOUT;
14552         dev->irq = pdev->irq;
14553
14554         err = tg3_get_invariants(tp);
14555         if (err) {
14556                 dev_err(&pdev->dev,
14557                         "Problem fetching invariants of chip, aborting\n");
14558                 goto err_out_iounmap;
14559         }
14560
14561         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14562             tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
14563                 dev->netdev_ops = &tg3_netdev_ops;
14564         else
14565                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14566
14567
14568         /* The EPB bridge inside 5714, 5715, and 5780 and any
14569          * device behind the EPB cannot support DMA addresses > 40-bit.
14570          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14571          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14572          * do DMA address check in tg3_start_xmit().
14573          */
14574         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14575                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14576         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14577                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14578 #ifdef CONFIG_HIGHMEM
14579                 dma_mask = DMA_BIT_MASK(64);
14580 #endif
14581         } else
14582                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14583
14584         /* Configure DMA attributes. */
14585         if (dma_mask > DMA_BIT_MASK(32)) {
14586                 err = pci_set_dma_mask(pdev, dma_mask);
14587                 if (!err) {
14588                         dev->features |= NETIF_F_HIGHDMA;
14589                         err = pci_set_consistent_dma_mask(pdev,
14590                                                           persist_dma_mask);
14591                         if (err < 0) {
14592                                 dev_err(&pdev->dev, "Unable to obtain 64 bit "
14593                                         "DMA for consistent allocations\n");
14594                                 goto err_out_iounmap;
14595                         }
14596                 }
14597         }
14598         if (err || dma_mask == DMA_BIT_MASK(32)) {
14599                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14600                 if (err) {
14601                         dev_err(&pdev->dev,
14602                                 "No usable DMA configuration, aborting\n");
14603                         goto err_out_iounmap;
14604                 }
14605         }
14606
14607         tg3_init_bufmgr_config(tp);
14608
14609         /* Selectively allow TSO based on operating conditions */
14610         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14611             (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14612                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14613         else {
14614                 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14615                 tp->fw_needed = NULL;
14616         }
14617
14618         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14619                 tp->fw_needed = FIRMWARE_TG3;
14620
14621         /* TSO is on by default on chips that support hardware TSO.
14622          * Firmware TSO on older chips gives lower performance, so it
14623          * is off by default, but can be enabled using ethtool.
14624          */
14625         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14626             (dev->features & NETIF_F_IP_CSUM))
14627                 dev->features |= NETIF_F_TSO;
14628
14629         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14630             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14631                 if (dev->features & NETIF_F_IPV6_CSUM)
14632                         dev->features |= NETIF_F_TSO6;
14633                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14634                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14635                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14636                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14637                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14638                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
14639                         dev->features |= NETIF_F_TSO_ECN;
14640         }
14641
14642         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14643             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14644             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14645                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14646                 tp->rx_pending = 63;
14647         }
14648
14649         err = tg3_get_device_address(tp);
14650         if (err) {
14651                 dev_err(&pdev->dev,
14652                         "Could not obtain valid ethernet address, aborting\n");
14653                 goto err_out_iounmap;
14654         }
14655
14656         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14657                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14658                 if (!tp->aperegs) {
14659                         dev_err(&pdev->dev,
14660                                 "Cannot map APE registers, aborting\n");
14661                         err = -ENOMEM;
14662                         goto err_out_iounmap;
14663                 }
14664
14665                 tg3_ape_lock_init(tp);
14666
14667                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14668                         tg3_read_dash_ver(tp);
14669         }
14670
14671         /*
14672          * Reset chip in case UNDI or EFI driver did not shutdown
14673          * DMA self test will enable WDMAC and we'll see (spurious)
14674          * pending DMA on the PCI bus at that point.
14675          */
14676         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14677             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14678                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14679                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14680         }
14681
14682         err = tg3_test_dma(tp);
14683         if (err) {
14684                 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
14685                 goto err_out_apeunmap;
14686         }
14687
14688         /* flow control autonegotiation is default behavior */
14689         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14690         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14691
14692         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14693         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14694         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14695         for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14696                 struct tg3_napi *tnapi = &tp->napi[i];
14697
14698                 tnapi->tp = tp;
14699                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14700
14701                 tnapi->int_mbox = intmbx;
14702                 if (i < 4)
14703                         intmbx += 0x8;
14704                 else
14705                         intmbx += 0x4;
14706
14707                 tnapi->consmbox = rcvmbx;
14708                 tnapi->prodmbox = sndmbx;
14709
14710                 if (i) {
14711                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14712                         netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14713                 } else {
14714                         tnapi->coal_now = HOSTCC_MODE_NOW;
14715                         netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14716                 }
14717
14718                 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14719                         break;
14720
14721                 /*
14722                  * If we support MSIX, we'll be using RSS.  If we're using
14723                  * RSS, the first vector only handles link interrupts and the
14724                  * remaining vectors handle rx and tx interrupts.  Reuse the
14725                  * mailbox values for the next iteration.  The values we setup
14726                  * above are still useful for the single vectored mode.
14727                  */
14728                 if (!i)
14729                         continue;
14730
14731                 rcvmbx += 0x8;
14732
14733                 if (sndmbx & 0x4)
14734                         sndmbx -= 0x4;
14735                 else
14736                         sndmbx += 0xc;
14737         }
14738
14739         tg3_init_coal(tp);
14740
14741         pci_set_drvdata(pdev, dev);
14742
14743         err = register_netdev(dev);
14744         if (err) {
14745                 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
14746                 goto err_out_apeunmap;
14747         }
14748
14749         netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14750                     tp->board_part_number,
14751                     tp->pci_chip_rev_id,
14752                     tg3_bus_string(tp, str),
14753                     dev->dev_addr);
14754
14755         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14756                 struct phy_device *phydev;
14757                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14758                 netdev_info(dev,
14759                             "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14760                             phydev->drv->name, dev_name(&phydev->dev));
14761         } else
14762                 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
14763                             "(WireSpeed[%d])\n", tg3_phy_string(tp),
14764                             ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14765                              ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14766                               "10/100/1000Base-T")),
14767                             (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14768
14769         netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14770                     (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14771                     (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14772                     (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14773                     (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14774                     (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14775         netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14776                     tp->dma_rwctrl,
14777                     pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
14778                     ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
14779
14780         return 0;
14781
14782 err_out_apeunmap:
14783         if (tp->aperegs) {
14784                 iounmap(tp->aperegs);
14785                 tp->aperegs = NULL;
14786         }
14787
14788 err_out_iounmap:
14789         if (tp->regs) {
14790                 iounmap(tp->regs);
14791                 tp->regs = NULL;
14792         }
14793
14794 err_out_free_dev:
14795         free_netdev(dev);
14796
14797 err_out_free_res:
14798         pci_release_regions(pdev);
14799
14800 err_out_disable_pdev:
14801         pci_disable_device(pdev);
14802         pci_set_drvdata(pdev, NULL);
14803         return err;
14804 }
14805
14806 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14807 {
14808         struct net_device *dev = pci_get_drvdata(pdev);
14809
14810         if (dev) {
14811                 struct tg3 *tp = netdev_priv(dev);
14812
14813                 if (tp->fw)
14814                         release_firmware(tp->fw);
14815
14816                 flush_scheduled_work();
14817
14818                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14819                         tg3_phy_fini(tp);
14820                         tg3_mdio_fini(tp);
14821                 }
14822
14823                 unregister_netdev(dev);
14824                 if (tp->aperegs) {
14825                         iounmap(tp->aperegs);
14826                         tp->aperegs = NULL;
14827                 }
14828                 if (tp->regs) {
14829                         iounmap(tp->regs);
14830                         tp->regs = NULL;
14831                 }
14832                 free_netdev(dev);
14833                 pci_release_regions(pdev);
14834                 pci_disable_device(pdev);
14835                 pci_set_drvdata(pdev, NULL);
14836         }
14837 }
14838
14839 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14840 {
14841         struct net_device *dev = pci_get_drvdata(pdev);
14842         struct tg3 *tp = netdev_priv(dev);
14843         pci_power_t target_state;
14844         int err;
14845
14846         /* PCI register 4 needs to be saved whether netif_running() or not.
14847          * MSI address and data need to be saved if using MSI and
14848          * netif_running().
14849          */
14850         pci_save_state(pdev);
14851
14852         if (!netif_running(dev))
14853                 return 0;
14854
14855         flush_scheduled_work();
14856         tg3_phy_stop(tp);
14857         tg3_netif_stop(tp);
14858
14859         del_timer_sync(&tp->timer);
14860
14861         tg3_full_lock(tp, 1);
14862         tg3_disable_ints(tp);
14863         tg3_full_unlock(tp);
14864
14865         netif_device_detach(dev);
14866
14867         tg3_full_lock(tp, 0);
14868         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14869         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14870         tg3_full_unlock(tp);
14871
14872         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14873
14874         err = tg3_set_power_state(tp, target_state);
14875         if (err) {
14876                 int err2;
14877
14878                 tg3_full_lock(tp, 0);
14879
14880                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14881                 err2 = tg3_restart_hw(tp, 1);
14882                 if (err2)
14883                         goto out;
14884
14885                 tp->timer.expires = jiffies + tp->timer_offset;
14886                 add_timer(&tp->timer);
14887
14888                 netif_device_attach(dev);
14889                 tg3_netif_start(tp);
14890
14891 out:
14892                 tg3_full_unlock(tp);
14893
14894                 if (!err2)
14895                         tg3_phy_start(tp);
14896         }
14897
14898         return err;
14899 }
14900
14901 static int tg3_resume(struct pci_dev *pdev)
14902 {
14903         struct net_device *dev = pci_get_drvdata(pdev);
14904         struct tg3 *tp = netdev_priv(dev);
14905         int err;
14906
14907         pci_restore_state(tp->pdev);
14908
14909         if (!netif_running(dev))
14910                 return 0;
14911
14912         err = tg3_set_power_state(tp, PCI_D0);
14913         if (err)
14914                 return err;
14915
14916         netif_device_attach(dev);
14917
14918         tg3_full_lock(tp, 0);
14919
14920         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14921         err = tg3_restart_hw(tp, 1);
14922         if (err)
14923                 goto out;
14924
14925         tp->timer.expires = jiffies + tp->timer_offset;
14926         add_timer(&tp->timer);
14927
14928         tg3_netif_start(tp);
14929
14930 out:
14931         tg3_full_unlock(tp);
14932
14933         if (!err)
14934                 tg3_phy_start(tp);
14935
14936         return err;
14937 }
14938
14939 static struct pci_driver tg3_driver = {
14940         .name           = DRV_MODULE_NAME,
14941         .id_table       = tg3_pci_tbl,
14942         .probe          = tg3_init_one,
14943         .remove         = __devexit_p(tg3_remove_one),
14944         .suspend        = tg3_suspend,
14945         .resume         = tg3_resume
14946 };
14947
14948 static int __init tg3_init(void)
14949 {
14950         return pci_register_driver(&tg3_driver);
14951 }
14952
14953 static void __exit tg3_cleanup(void)
14954 {
14955         pci_unregister_driver(&tg3_driver);
14956 }
14957
14958 module_init(tg3_init);
14959 module_exit(tg3_cleanup);