2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2010 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
28 #include <linux/init.h>
29 #include <linux/ioport.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/ethtool.h>
35 #include <linux/mii.h>
36 #include <linux/phy.h>
37 #include <linux/brcmphy.h>
38 #include <linux/if_vlan.h>
40 #include <linux/tcp.h>
41 #include <linux/workqueue.h>
42 #include <linux/prefetch.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/firmware.h>
46 #include <net/checksum.h>
49 #include <asm/system.h>
51 #include <asm/byteorder.h>
52 #include <asm/uaccess.h>
55 #include <asm/idprom.h>
62 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
63 #define TG3_VLAN_TAG_USED 1
65 #define TG3_VLAN_TAG_USED 0
70 #define DRV_MODULE_NAME "tg3"
72 #define TG3_MIN_NUM 113
73 #define DRV_MODULE_VERSION \
74 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
75 #define DRV_MODULE_RELDATE "August 2, 2010"
77 #define TG3_DEF_MAC_MODE 0
78 #define TG3_DEF_RX_MODE 0
79 #define TG3_DEF_TX_MODE 0
80 #define TG3_DEF_MSG_ENABLE \
90 /* length of time before we decide the hardware is borked,
91 * and dev->tx_timeout() should be called to fix the problem
93 #define TG3_TX_TIMEOUT (5 * HZ)
95 /* hardware minimum and maximum for a single frame's data payload */
96 #define TG3_MIN_MTU 60
97 #define TG3_MAX_MTU(tp) \
98 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
100 /* These numbers seem to be hard coded in the NIC firmware somehow.
101 * You can't change the ring sizes, but you can change where you place
102 * them in the NIC onboard memory.
104 #define TG3_RX_RING_SIZE 512
105 #define TG3_DEF_RX_RING_PENDING 200
106 #define TG3_RX_JUMBO_RING_SIZE 256
107 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
108 #define TG3_RSS_INDIR_TBL_SIZE 128
110 /* Do not place this n-ring entries value into the tp struct itself,
111 * we really want to expose these constants to GCC so that modulo et
112 * al. operations are done with shifts and masks instead of with
113 * hw multiply/modulo instructions. Another solution would be to
114 * replace things like '% foo' with '& (foo - 1)'.
116 #define TG3_RX_RCB_RING_SIZE(tp) \
117 (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
118 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
120 #define TG3_TX_RING_SIZE 512
121 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
123 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
125 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
126 TG3_RX_JUMBO_RING_SIZE)
127 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
128 TG3_RX_RCB_RING_SIZE(tp))
129 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
131 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
133 #define TG3_RX_DMA_ALIGN 16
134 #define TG3_RX_HEADROOM ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
136 #define TG3_DMA_BYTE_ENAB 64
138 #define TG3_RX_STD_DMA_SZ 1536
139 #define TG3_RX_JMB_DMA_SZ 9046
141 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
143 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
144 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
146 #define TG3_RX_STD_BUFF_RING_SIZE \
147 (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
149 #define TG3_RX_JMB_BUFF_RING_SIZE \
150 (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
152 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
153 * that are at least dword aligned when used in PCIX mode. The driver
154 * works around this bug by double copying the packet. This workaround
155 * is built into the normal double copy length check for efficiency.
157 * However, the double copy is only necessary on those architectures
158 * where unaligned memory accesses are inefficient. For those architectures
159 * where unaligned memory accesses incur little penalty, we can reintegrate
160 * the 5701 in the normal rx path. Doing so saves a device structure
161 * dereference by hardcoding the double copy threshold in place.
163 #define TG3_RX_COPY_THRESHOLD 256
164 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
165 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
167 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
170 /* minimum number of free TX descriptors required to wake up TX process */
171 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
173 #define TG3_RAW_IP_ALIGN 2
175 /* number of ETHTOOL_GSTATS u64's */
176 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
178 #define TG3_NUM_TEST 6
180 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
182 #define FIRMWARE_TG3 "tigon/tg3.bin"
183 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
184 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
186 static char version[] __devinitdata =
187 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
189 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
190 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
191 MODULE_LICENSE("GPL");
192 MODULE_VERSION(DRV_MODULE_VERSION);
193 MODULE_FIRMWARE(FIRMWARE_TG3);
194 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
195 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
197 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
198 module_param(tg3_debug, int, 0);
199 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
201 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
260 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
261 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
264 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
267 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
268 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
274 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
275 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
276 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
277 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
278 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
279 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
280 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
284 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
286 static const struct {
287 const char string[ETH_GSTRING_LEN];
288 } ethtool_stats_keys[TG3_NUM_STATS] = {
291 { "rx_ucast_packets" },
292 { "rx_mcast_packets" },
293 { "rx_bcast_packets" },
295 { "rx_align_errors" },
296 { "rx_xon_pause_rcvd" },
297 { "rx_xoff_pause_rcvd" },
298 { "rx_mac_ctrl_rcvd" },
299 { "rx_xoff_entered" },
300 { "rx_frame_too_long_errors" },
302 { "rx_undersize_packets" },
303 { "rx_in_length_errors" },
304 { "rx_out_length_errors" },
305 { "rx_64_or_less_octet_packets" },
306 { "rx_65_to_127_octet_packets" },
307 { "rx_128_to_255_octet_packets" },
308 { "rx_256_to_511_octet_packets" },
309 { "rx_512_to_1023_octet_packets" },
310 { "rx_1024_to_1522_octet_packets" },
311 { "rx_1523_to_2047_octet_packets" },
312 { "rx_2048_to_4095_octet_packets" },
313 { "rx_4096_to_8191_octet_packets" },
314 { "rx_8192_to_9022_octet_packets" },
321 { "tx_flow_control" },
323 { "tx_single_collisions" },
324 { "tx_mult_collisions" },
326 { "tx_excessive_collisions" },
327 { "tx_late_collisions" },
328 { "tx_collide_2times" },
329 { "tx_collide_3times" },
330 { "tx_collide_4times" },
331 { "tx_collide_5times" },
332 { "tx_collide_6times" },
333 { "tx_collide_7times" },
334 { "tx_collide_8times" },
335 { "tx_collide_9times" },
336 { "tx_collide_10times" },
337 { "tx_collide_11times" },
338 { "tx_collide_12times" },
339 { "tx_collide_13times" },
340 { "tx_collide_14times" },
341 { "tx_collide_15times" },
342 { "tx_ucast_packets" },
343 { "tx_mcast_packets" },
344 { "tx_bcast_packets" },
345 { "tx_carrier_sense_errors" },
349 { "dma_writeq_full" },
350 { "dma_write_prioq_full" },
354 { "rx_threshold_hit" },
356 { "dma_readq_full" },
357 { "dma_read_prioq_full" },
358 { "tx_comp_queue_full" },
360 { "ring_set_send_prod_index" },
361 { "ring_status_update" },
363 { "nic_avoided_irqs" },
364 { "nic_tx_threshold_hit" }
367 static const struct {
368 const char string[ETH_GSTRING_LEN];
369 } ethtool_test_keys[TG3_NUM_TEST] = {
370 { "nvram test (online) " },
371 { "link test (online) " },
372 { "register test (offline)" },
373 { "memory test (offline)" },
374 { "loopback test (offline)" },
375 { "interrupt test (offline)" },
378 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
380 writel(val, tp->regs + off);
383 static u32 tg3_read32(struct tg3 *tp, u32 off)
385 return readl(tp->regs + off);
388 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
390 writel(val, tp->aperegs + off);
393 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
395 return readl(tp->aperegs + off);
398 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
402 spin_lock_irqsave(&tp->indirect_lock, flags);
403 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
404 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
405 spin_unlock_irqrestore(&tp->indirect_lock, flags);
408 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
410 writel(val, tp->regs + off);
411 readl(tp->regs + off);
414 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
419 spin_lock_irqsave(&tp->indirect_lock, flags);
420 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
421 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
422 spin_unlock_irqrestore(&tp->indirect_lock, flags);
426 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
430 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
431 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
432 TG3_64BIT_REG_LOW, val);
435 if (off == TG3_RX_STD_PROD_IDX_REG) {
436 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
437 TG3_64BIT_REG_LOW, val);
441 spin_lock_irqsave(&tp->indirect_lock, flags);
442 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
443 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
444 spin_unlock_irqrestore(&tp->indirect_lock, flags);
446 /* In indirect mode when disabling interrupts, we also need
447 * to clear the interrupt bit in the GRC local ctrl register.
449 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
451 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
452 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
456 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
461 spin_lock_irqsave(&tp->indirect_lock, flags);
462 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
463 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
464 spin_unlock_irqrestore(&tp->indirect_lock, flags);
468 /* usec_wait specifies the wait time in usec when writing to certain registers
469 * where it is unsafe to read back the register without some delay.
470 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
471 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
473 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
475 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
476 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
477 /* Non-posted methods */
478 tp->write32(tp, off, val);
481 tg3_write32(tp, off, val);
486 /* Wait again after the read for the posted method to guarantee that
487 * the wait time is met.
493 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
495 tp->write32_mbox(tp, off, val);
496 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
497 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
498 tp->read32_mbox(tp, off);
501 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
503 void __iomem *mbox = tp->regs + off;
505 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
507 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
511 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
513 return readl(tp->regs + off + GRCMBOX_BASE);
516 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
518 writel(val, tp->regs + off + GRCMBOX_BASE);
521 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
522 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
523 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
524 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
525 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
527 #define tw32(reg, val) tp->write32(tp, reg, val)
528 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
529 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
530 #define tr32(reg) tp->read32(tp, reg)
532 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
536 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
537 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
540 spin_lock_irqsave(&tp->indirect_lock, flags);
541 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
542 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
543 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
545 /* Always leave this as zero. */
546 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
548 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
549 tw32_f(TG3PCI_MEM_WIN_DATA, val);
551 /* Always leave this as zero. */
552 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
554 spin_unlock_irqrestore(&tp->indirect_lock, flags);
557 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
561 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
562 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
567 spin_lock_irqsave(&tp->indirect_lock, flags);
568 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
569 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
570 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
572 /* Always leave this as zero. */
573 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
575 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
576 *val = tr32(TG3PCI_MEM_WIN_DATA);
578 /* Always leave this as zero. */
579 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
581 spin_unlock_irqrestore(&tp->indirect_lock, flags);
584 static void tg3_ape_lock_init(struct tg3 *tp)
589 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
590 regbase = TG3_APE_LOCK_GRANT;
592 regbase = TG3_APE_PER_LOCK_GRANT;
594 /* Make sure the driver hasn't any stale locks. */
595 for (i = 0; i < 8; i++)
596 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
599 static int tg3_ape_lock(struct tg3 *tp, int locknum)
603 u32 status, req, gnt;
605 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
609 case TG3_APE_LOCK_GRC:
610 case TG3_APE_LOCK_MEM:
616 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
617 req = TG3_APE_LOCK_REQ;
618 gnt = TG3_APE_LOCK_GRANT;
620 req = TG3_APE_PER_LOCK_REQ;
621 gnt = TG3_APE_PER_LOCK_GRANT;
626 tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
628 /* Wait for up to 1 millisecond to acquire lock. */
629 for (i = 0; i < 100; i++) {
630 status = tg3_ape_read32(tp, gnt + off);
631 if (status == APE_LOCK_GRANT_DRIVER)
636 if (status != APE_LOCK_GRANT_DRIVER) {
637 /* Revoke the lock request. */
638 tg3_ape_write32(tp, gnt + off,
639 APE_LOCK_GRANT_DRIVER);
647 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
651 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
655 case TG3_APE_LOCK_GRC:
656 case TG3_APE_LOCK_MEM:
662 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
663 gnt = TG3_APE_LOCK_GRANT;
665 gnt = TG3_APE_PER_LOCK_GRANT;
667 tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
670 static void tg3_disable_ints(struct tg3 *tp)
674 tw32(TG3PCI_MISC_HOST_CTRL,
675 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
676 for (i = 0; i < tp->irq_max; i++)
677 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
680 static void tg3_enable_ints(struct tg3 *tp)
687 tw32(TG3PCI_MISC_HOST_CTRL,
688 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
690 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
691 for (i = 0; i < tp->irq_cnt; i++) {
692 struct tg3_napi *tnapi = &tp->napi[i];
694 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
695 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
696 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
698 tp->coal_now |= tnapi->coal_now;
701 /* Force an initial interrupt */
702 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
703 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
704 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
706 tw32(HOSTCC_MODE, tp->coal_now);
708 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
711 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
713 struct tg3 *tp = tnapi->tp;
714 struct tg3_hw_status *sblk = tnapi->hw_status;
715 unsigned int work_exists = 0;
717 /* check for phy events */
718 if (!(tp->tg3_flags &
719 (TG3_FLAG_USE_LINKCHG_REG |
720 TG3_FLAG_POLL_SERDES))) {
721 if (sblk->status & SD_STATUS_LINK_CHG)
724 /* check for RX/TX work to do */
725 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
726 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
733 * similar to tg3_enable_ints, but it accurately determines whether there
734 * is new work pending and can return without flushing the PIO write
735 * which reenables interrupts
737 static void tg3_int_reenable(struct tg3_napi *tnapi)
739 struct tg3 *tp = tnapi->tp;
741 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
744 /* When doing tagged status, this work check is unnecessary.
745 * The last_tag we write above tells the chip which piece of
746 * work we've completed.
748 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
750 tw32(HOSTCC_MODE, tp->coalesce_mode |
751 HOSTCC_MODE_ENABLE | tnapi->coal_now);
754 static void tg3_switch_clocks(struct tg3 *tp)
759 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
760 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
763 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
765 orig_clock_ctrl = clock_ctrl;
766 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
767 CLOCK_CTRL_CLKRUN_OENABLE |
769 tp->pci_clock_ctrl = clock_ctrl;
771 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
772 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
773 tw32_wait_f(TG3PCI_CLOCK_CTRL,
774 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
776 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
777 tw32_wait_f(TG3PCI_CLOCK_CTRL,
779 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
781 tw32_wait_f(TG3PCI_CLOCK_CTRL,
782 clock_ctrl | (CLOCK_CTRL_ALTCLK),
785 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
788 #define PHY_BUSY_LOOPS 5000
790 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
796 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
798 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
804 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
805 MI_COM_PHY_ADDR_MASK);
806 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
807 MI_COM_REG_ADDR_MASK);
808 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
810 tw32_f(MAC_MI_COM, frame_val);
812 loops = PHY_BUSY_LOOPS;
815 frame_val = tr32(MAC_MI_COM);
817 if ((frame_val & MI_COM_BUSY) == 0) {
819 frame_val = tr32(MAC_MI_COM);
827 *val = frame_val & MI_COM_DATA_MASK;
831 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
832 tw32_f(MAC_MI_MODE, tp->mi_mode);
839 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
845 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
846 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
849 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
851 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
855 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
856 MI_COM_PHY_ADDR_MASK);
857 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
858 MI_COM_REG_ADDR_MASK);
859 frame_val |= (val & MI_COM_DATA_MASK);
860 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
862 tw32_f(MAC_MI_COM, frame_val);
864 loops = PHY_BUSY_LOOPS;
867 frame_val = tr32(MAC_MI_COM);
868 if ((frame_val & MI_COM_BUSY) == 0) {
870 frame_val = tr32(MAC_MI_COM);
880 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
881 tw32_f(MAC_MI_MODE, tp->mi_mode);
888 static int tg3_bmcr_reset(struct tg3 *tp)
893 /* OK, reset it, and poll the BMCR_RESET bit until it
894 * clears or we time out.
896 phy_control = BMCR_RESET;
897 err = tg3_writephy(tp, MII_BMCR, phy_control);
903 err = tg3_readphy(tp, MII_BMCR, &phy_control);
907 if ((phy_control & BMCR_RESET) == 0) {
919 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
921 struct tg3 *tp = bp->priv;
924 spin_lock_bh(&tp->lock);
926 if (tg3_readphy(tp, reg, &val))
929 spin_unlock_bh(&tp->lock);
934 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
936 struct tg3 *tp = bp->priv;
939 spin_lock_bh(&tp->lock);
941 if (tg3_writephy(tp, reg, val))
944 spin_unlock_bh(&tp->lock);
949 static int tg3_mdio_reset(struct mii_bus *bp)
954 static void tg3_mdio_config_5785(struct tg3 *tp)
957 struct phy_device *phydev;
959 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
960 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
961 case PHY_ID_BCM50610:
962 case PHY_ID_BCM50610M:
963 val = MAC_PHYCFG2_50610_LED_MODES;
965 case PHY_ID_BCMAC131:
966 val = MAC_PHYCFG2_AC131_LED_MODES;
968 case PHY_ID_RTL8211C:
969 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
971 case PHY_ID_RTL8201E:
972 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
978 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
979 tw32(MAC_PHYCFG2, val);
981 val = tr32(MAC_PHYCFG1);
982 val &= ~(MAC_PHYCFG1_RGMII_INT |
983 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
984 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
985 tw32(MAC_PHYCFG1, val);
990 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
991 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
992 MAC_PHYCFG2_FMODE_MASK_MASK |
993 MAC_PHYCFG2_GMODE_MASK_MASK |
994 MAC_PHYCFG2_ACT_MASK_MASK |
995 MAC_PHYCFG2_QUAL_MASK_MASK |
996 MAC_PHYCFG2_INBAND_ENABLE;
998 tw32(MAC_PHYCFG2, val);
1000 val = tr32(MAC_PHYCFG1);
1001 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1002 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1003 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1004 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1005 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1006 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1007 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1009 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1010 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1011 tw32(MAC_PHYCFG1, val);
1013 val = tr32(MAC_EXT_RGMII_MODE);
1014 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1015 MAC_RGMII_MODE_RX_QUALITY |
1016 MAC_RGMII_MODE_RX_ACTIVITY |
1017 MAC_RGMII_MODE_RX_ENG_DET |
1018 MAC_RGMII_MODE_TX_ENABLE |
1019 MAC_RGMII_MODE_TX_LOWPWR |
1020 MAC_RGMII_MODE_TX_RESET);
1021 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1022 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1023 val |= MAC_RGMII_MODE_RX_INT_B |
1024 MAC_RGMII_MODE_RX_QUALITY |
1025 MAC_RGMII_MODE_RX_ACTIVITY |
1026 MAC_RGMII_MODE_RX_ENG_DET;
1027 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1028 val |= MAC_RGMII_MODE_TX_ENABLE |
1029 MAC_RGMII_MODE_TX_LOWPWR |
1030 MAC_RGMII_MODE_TX_RESET;
1032 tw32(MAC_EXT_RGMII_MODE, val);
1035 static void tg3_mdio_start(struct tg3 *tp)
1037 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1038 tw32_f(MAC_MI_MODE, tp->mi_mode);
1041 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1042 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1043 tg3_mdio_config_5785(tp);
1046 static int tg3_mdio_init(struct tg3 *tp)
1050 struct phy_device *phydev;
1052 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1053 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
1056 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1058 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1059 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1061 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1062 TG3_CPMU_PHY_STRAP_IS_SERDES;
1066 tp->phy_addr = TG3_PHY_MII_ADDR;
1070 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1071 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1074 tp->mdio_bus = mdiobus_alloc();
1075 if (tp->mdio_bus == NULL)
1078 tp->mdio_bus->name = "tg3 mdio bus";
1079 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1080 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1081 tp->mdio_bus->priv = tp;
1082 tp->mdio_bus->parent = &tp->pdev->dev;
1083 tp->mdio_bus->read = &tg3_mdio_read;
1084 tp->mdio_bus->write = &tg3_mdio_write;
1085 tp->mdio_bus->reset = &tg3_mdio_reset;
1086 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1087 tp->mdio_bus->irq = &tp->mdio_irq[0];
1089 for (i = 0; i < PHY_MAX_ADDR; i++)
1090 tp->mdio_bus->irq[i] = PHY_POLL;
1092 /* The bus registration will look for all the PHYs on the mdio bus.
1093 * Unfortunately, it does not ensure the PHY is powered up before
1094 * accessing the PHY ID registers. A chip reset is the
1095 * quickest way to bring the device back to an operational state..
1097 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN))
1100 i = mdiobus_register(tp->mdio_bus);
1102 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1103 mdiobus_free(tp->mdio_bus);
1107 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1109 if (!phydev || !phydev->drv) {
1110 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1111 mdiobus_unregister(tp->mdio_bus);
1112 mdiobus_free(tp->mdio_bus);
1116 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1117 case PHY_ID_BCM57780:
1118 phydev->interface = PHY_INTERFACE_MODE_GMII;
1119 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1121 case PHY_ID_BCM50610:
1122 case PHY_ID_BCM50610M:
1123 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1124 PHY_BRCM_RX_REFCLK_UNUSED |
1125 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1126 PHY_BRCM_AUTO_PWRDWN_ENABLE;
1127 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1128 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1129 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1130 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1131 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1132 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1134 case PHY_ID_RTL8211C:
1135 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1137 case PHY_ID_RTL8201E:
1138 case PHY_ID_BCMAC131:
1139 phydev->interface = PHY_INTERFACE_MODE_MII;
1140 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1141 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1145 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1147 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1148 tg3_mdio_config_5785(tp);
1153 static void tg3_mdio_fini(struct tg3 *tp)
1155 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1156 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1157 mdiobus_unregister(tp->mdio_bus);
1158 mdiobus_free(tp->mdio_bus);
1162 /* tp->lock is held. */
1163 static inline void tg3_generate_fw_event(struct tg3 *tp)
1167 val = tr32(GRC_RX_CPU_EVENT);
1168 val |= GRC_RX_CPU_DRIVER_EVENT;
1169 tw32_f(GRC_RX_CPU_EVENT, val);
1171 tp->last_event_jiffies = jiffies;
1174 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1176 /* tp->lock is held. */
1177 static void tg3_wait_for_event_ack(struct tg3 *tp)
1180 unsigned int delay_cnt;
1183 /* If enough time has passed, no wait is necessary. */
1184 time_remain = (long)(tp->last_event_jiffies + 1 +
1185 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1187 if (time_remain < 0)
1190 /* Check if we can shorten the wait time. */
1191 delay_cnt = jiffies_to_usecs(time_remain);
1192 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1193 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1194 delay_cnt = (delay_cnt >> 3) + 1;
1196 for (i = 0; i < delay_cnt; i++) {
1197 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1203 /* tp->lock is held. */
1204 static void tg3_ump_link_report(struct tg3 *tp)
1209 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1210 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1213 tg3_wait_for_event_ack(tp);
1215 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1217 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1220 if (!tg3_readphy(tp, MII_BMCR, ®))
1222 if (!tg3_readphy(tp, MII_BMSR, ®))
1223 val |= (reg & 0xffff);
1224 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1227 if (!tg3_readphy(tp, MII_ADVERTISE, ®))
1229 if (!tg3_readphy(tp, MII_LPA, ®))
1230 val |= (reg & 0xffff);
1231 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1234 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1235 if (!tg3_readphy(tp, MII_CTRL1000, ®))
1237 if (!tg3_readphy(tp, MII_STAT1000, ®))
1238 val |= (reg & 0xffff);
1240 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1242 if (!tg3_readphy(tp, MII_PHYADDR, ®))
1246 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1248 tg3_generate_fw_event(tp);
1251 static void tg3_link_report(struct tg3 *tp)
1253 if (!netif_carrier_ok(tp->dev)) {
1254 netif_info(tp, link, tp->dev, "Link is down\n");
1255 tg3_ump_link_report(tp);
1256 } else if (netif_msg_link(tp)) {
1257 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1258 (tp->link_config.active_speed == SPEED_1000 ?
1260 (tp->link_config.active_speed == SPEED_100 ?
1262 (tp->link_config.active_duplex == DUPLEX_FULL ?
1265 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1266 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1268 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1270 tg3_ump_link_report(tp);
1274 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1278 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1279 miireg = ADVERTISE_PAUSE_CAP;
1280 else if (flow_ctrl & FLOW_CTRL_TX)
1281 miireg = ADVERTISE_PAUSE_ASYM;
1282 else if (flow_ctrl & FLOW_CTRL_RX)
1283 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1290 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1294 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1295 miireg = ADVERTISE_1000XPAUSE;
1296 else if (flow_ctrl & FLOW_CTRL_TX)
1297 miireg = ADVERTISE_1000XPSE_ASYM;
1298 else if (flow_ctrl & FLOW_CTRL_RX)
1299 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1306 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1310 if (lcladv & ADVERTISE_1000XPAUSE) {
1311 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1312 if (rmtadv & LPA_1000XPAUSE)
1313 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1314 else if (rmtadv & LPA_1000XPAUSE_ASYM)
1317 if (rmtadv & LPA_1000XPAUSE)
1318 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1320 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1321 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1328 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1332 u32 old_rx_mode = tp->rx_mode;
1333 u32 old_tx_mode = tp->tx_mode;
1335 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1336 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1338 autoneg = tp->link_config.autoneg;
1340 if (autoneg == AUTONEG_ENABLE &&
1341 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1342 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1343 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1345 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1347 flowctrl = tp->link_config.flowctrl;
1349 tp->link_config.active_flowctrl = flowctrl;
1351 if (flowctrl & FLOW_CTRL_RX)
1352 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1354 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1356 if (old_rx_mode != tp->rx_mode)
1357 tw32_f(MAC_RX_MODE, tp->rx_mode);
1359 if (flowctrl & FLOW_CTRL_TX)
1360 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1362 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1364 if (old_tx_mode != tp->tx_mode)
1365 tw32_f(MAC_TX_MODE, tp->tx_mode);
1368 static void tg3_adjust_link(struct net_device *dev)
1370 u8 oldflowctrl, linkmesg = 0;
1371 u32 mac_mode, lcl_adv, rmt_adv;
1372 struct tg3 *tp = netdev_priv(dev);
1373 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1375 spin_lock_bh(&tp->lock);
1377 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1378 MAC_MODE_HALF_DUPLEX);
1380 oldflowctrl = tp->link_config.active_flowctrl;
1386 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1387 mac_mode |= MAC_MODE_PORT_MODE_MII;
1388 else if (phydev->speed == SPEED_1000 ||
1389 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1390 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1392 mac_mode |= MAC_MODE_PORT_MODE_MII;
1394 if (phydev->duplex == DUPLEX_HALF)
1395 mac_mode |= MAC_MODE_HALF_DUPLEX;
1397 lcl_adv = tg3_advert_flowctrl_1000T(
1398 tp->link_config.flowctrl);
1401 rmt_adv = LPA_PAUSE_CAP;
1402 if (phydev->asym_pause)
1403 rmt_adv |= LPA_PAUSE_ASYM;
1406 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1408 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1410 if (mac_mode != tp->mac_mode) {
1411 tp->mac_mode = mac_mode;
1412 tw32_f(MAC_MODE, tp->mac_mode);
1416 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1417 if (phydev->speed == SPEED_10)
1419 MAC_MI_STAT_10MBPS_MODE |
1420 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1422 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1425 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1426 tw32(MAC_TX_LENGTHS,
1427 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1428 (6 << TX_LENGTHS_IPG_SHIFT) |
1429 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1431 tw32(MAC_TX_LENGTHS,
1432 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1433 (6 << TX_LENGTHS_IPG_SHIFT) |
1434 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1436 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1437 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1438 phydev->speed != tp->link_config.active_speed ||
1439 phydev->duplex != tp->link_config.active_duplex ||
1440 oldflowctrl != tp->link_config.active_flowctrl)
1443 tp->link_config.active_speed = phydev->speed;
1444 tp->link_config.active_duplex = phydev->duplex;
1446 spin_unlock_bh(&tp->lock);
1449 tg3_link_report(tp);
1452 static int tg3_phy_init(struct tg3 *tp)
1454 struct phy_device *phydev;
1456 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1459 /* Bring the PHY back to a known state. */
1462 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1464 /* Attach the MAC to the PHY. */
1465 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1466 phydev->dev_flags, phydev->interface);
1467 if (IS_ERR(phydev)) {
1468 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1469 return PTR_ERR(phydev);
1472 /* Mask with MAC supported features. */
1473 switch (phydev->interface) {
1474 case PHY_INTERFACE_MODE_GMII:
1475 case PHY_INTERFACE_MODE_RGMII:
1476 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1477 phydev->supported &= (PHY_GBIT_FEATURES |
1479 SUPPORTED_Asym_Pause);
1483 case PHY_INTERFACE_MODE_MII:
1484 phydev->supported &= (PHY_BASIC_FEATURES |
1486 SUPPORTED_Asym_Pause);
1489 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1493 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1495 phydev->advertising = phydev->supported;
1500 static void tg3_phy_start(struct tg3 *tp)
1502 struct phy_device *phydev;
1504 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1507 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1509 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1510 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1511 phydev->speed = tp->link_config.orig_speed;
1512 phydev->duplex = tp->link_config.orig_duplex;
1513 phydev->autoneg = tp->link_config.orig_autoneg;
1514 phydev->advertising = tp->link_config.orig_advertising;
1519 phy_start_aneg(phydev);
1522 static void tg3_phy_stop(struct tg3 *tp)
1524 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1527 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1530 static void tg3_phy_fini(struct tg3 *tp)
1532 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1533 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1534 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1538 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1542 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1544 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1549 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1553 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1556 tg3_writephy(tp, MII_TG3_FET_TEST,
1557 phytest | MII_TG3_FET_SHADOW_EN);
1558 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1560 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1562 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1563 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1565 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1569 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1573 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1574 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1575 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1576 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1579 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1580 tg3_phy_fet_toggle_apd(tp, enable);
1584 reg = MII_TG3_MISC_SHDW_WREN |
1585 MII_TG3_MISC_SHDW_SCR5_SEL |
1586 MII_TG3_MISC_SHDW_SCR5_LPED |
1587 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1588 MII_TG3_MISC_SHDW_SCR5_SDTL |
1589 MII_TG3_MISC_SHDW_SCR5_C125OE;
1590 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1591 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1593 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1596 reg = MII_TG3_MISC_SHDW_WREN |
1597 MII_TG3_MISC_SHDW_APD_SEL |
1598 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1600 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1602 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1605 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1609 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1610 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
1613 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1616 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1617 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1619 tg3_writephy(tp, MII_TG3_FET_TEST,
1620 ephy | MII_TG3_FET_SHADOW_EN);
1621 if (!tg3_readphy(tp, reg, &phy)) {
1623 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1625 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1626 tg3_writephy(tp, reg, phy);
1628 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1631 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1632 MII_TG3_AUXCTL_SHDWSEL_MISC;
1633 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1634 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1636 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1638 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1639 phy |= MII_TG3_AUXCTL_MISC_WREN;
1640 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1645 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1649 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1652 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1653 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1654 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1655 (val | (1 << 15) | (1 << 4)));
1658 static void tg3_phy_apply_otp(struct tg3 *tp)
1667 /* Enable SM_DSP clock and tx 6dB coding. */
1668 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1669 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1670 MII_TG3_AUXCTL_ACTL_TX_6DB;
1671 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1673 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1674 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1675 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1677 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1678 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1679 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1681 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1682 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1683 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1685 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1686 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1688 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1689 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1691 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1692 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1693 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1695 /* Turn off SM_DSP clock. */
1696 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1697 MII_TG3_AUXCTL_ACTL_TX_6DB;
1698 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1701 static int tg3_wait_macro_done(struct tg3 *tp)
1708 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1709 if ((tmp32 & 0x1000) == 0)
1719 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1721 static const u32 test_pat[4][6] = {
1722 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1723 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1724 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1725 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1729 for (chan = 0; chan < 4; chan++) {
1732 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1733 (chan * 0x2000) | 0x0200);
1734 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1736 for (i = 0; i < 6; i++)
1737 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1740 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1741 if (tg3_wait_macro_done(tp)) {
1746 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1747 (chan * 0x2000) | 0x0200);
1748 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1749 if (tg3_wait_macro_done(tp)) {
1754 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1755 if (tg3_wait_macro_done(tp)) {
1760 for (i = 0; i < 6; i += 2) {
1763 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1764 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1765 tg3_wait_macro_done(tp)) {
1771 if (low != test_pat[chan][i] ||
1772 high != test_pat[chan][i+1]) {
1773 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1774 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1775 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1785 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1789 for (chan = 0; chan < 4; chan++) {
1792 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1793 (chan * 0x2000) | 0x0200);
1794 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1795 for (i = 0; i < 6; i++)
1796 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1797 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1798 if (tg3_wait_macro_done(tp))
1805 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1807 u32 reg32, phy9_orig;
1808 int retries, do_phy_reset, err;
1814 err = tg3_bmcr_reset(tp);
1820 /* Disable transmitter and interrupt. */
1821 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
1825 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1827 /* Set full-duplex, 1000 mbps. */
1828 tg3_writephy(tp, MII_BMCR,
1829 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1831 /* Set to master mode. */
1832 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1835 tg3_writephy(tp, MII_TG3_CTRL,
1836 (MII_TG3_CTRL_AS_MASTER |
1837 MII_TG3_CTRL_ENABLE_AS_MASTER));
1839 /* Enable SM_DSP_CLOCK and 6dB. */
1840 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1842 /* Block the PHY control access. */
1843 tg3_phydsp_write(tp, 0x8005, 0x0800);
1845 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1848 } while (--retries);
1850 err = tg3_phy_reset_chanpat(tp);
1854 tg3_phydsp_write(tp, 0x8005, 0x0000);
1856 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1857 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1859 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1860 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1861 /* Set Extended packet length bit for jumbo frames */
1862 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1864 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1867 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1869 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) {
1871 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1878 /* This will reset the tigon3 PHY if there is no valid
1879 * link unless the FORCE argument is non-zero.
1881 static int tg3_phy_reset(struct tg3 *tp)
1886 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1887 val = tr32(GRC_MISC_CFG);
1888 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1891 err = tg3_readphy(tp, MII_BMSR, &val);
1892 err |= tg3_readphy(tp, MII_BMSR, &val);
1896 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1897 netif_carrier_off(tp->dev);
1898 tg3_link_report(tp);
1901 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1902 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1903 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1904 err = tg3_phy_reset_5703_4_5(tp);
1911 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1912 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1913 cpmuctrl = tr32(TG3_CPMU_CTRL);
1914 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1916 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1919 err = tg3_bmcr_reset(tp);
1923 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1924 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1925 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
1927 tw32(TG3_CPMU_CTRL, cpmuctrl);
1930 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1931 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1932 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1933 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1934 CPMU_LSPD_1000MB_MACCLK_12_5) {
1935 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1937 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1941 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1942 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1943 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
1946 tg3_phy_apply_otp(tp);
1948 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
1949 tg3_phy_toggle_apd(tp, true);
1951 tg3_phy_toggle_apd(tp, false);
1954 if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) {
1955 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1956 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
1957 tg3_phydsp_write(tp, 0x000a, 0x0323);
1958 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1960 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
1961 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
1962 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
1964 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
1965 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1966 tg3_phydsp_write(tp, 0x000a, 0x310b);
1967 tg3_phydsp_write(tp, 0x201f, 0x9506);
1968 tg3_phydsp_write(tp, 0x401f, 0x14e2);
1969 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1970 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
1971 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1972 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1973 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
1974 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1975 tg3_writephy(tp, MII_TG3_TEST1,
1976 MII_TG3_TEST1_TRIM_EN | 0x4);
1978 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1979 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1981 /* Set Extended packet length bit (bit 14) on all chips that */
1982 /* support jumbo frames */
1983 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1984 /* Cannot do read-modify-write on 5401 */
1985 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1986 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1987 /* Set bit 14 with read-modify-write to preserve other bits */
1988 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1989 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1990 tg3_writephy(tp, MII_TG3_AUX_CTRL, val | 0x4000);
1993 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1994 * jumbo frames transmission.
1996 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1997 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
1998 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1999 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2002 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2003 /* adjust output voltage */
2004 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2007 tg3_phy_toggle_automdix(tp, 1);
2008 tg3_phy_set_wirespeed(tp);
2012 static void tg3_frob_aux_power(struct tg3 *tp)
2014 struct tg3 *tp_peer = tp;
2016 /* The GPIOs do something completely different on 57765. */
2017 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2018 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2019 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2022 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2023 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2024 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2025 struct net_device *dev_peer;
2027 dev_peer = pci_get_drvdata(tp->pdev_peer);
2028 /* remove_one() may have been run on the peer. */
2032 tp_peer = netdev_priv(dev_peer);
2035 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2036 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2037 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2038 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2039 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2040 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2041 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2042 (GRC_LCLCTRL_GPIO_OE0 |
2043 GRC_LCLCTRL_GPIO_OE1 |
2044 GRC_LCLCTRL_GPIO_OE2 |
2045 GRC_LCLCTRL_GPIO_OUTPUT0 |
2046 GRC_LCLCTRL_GPIO_OUTPUT1),
2048 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2049 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2050 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2051 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2052 GRC_LCLCTRL_GPIO_OE1 |
2053 GRC_LCLCTRL_GPIO_OE2 |
2054 GRC_LCLCTRL_GPIO_OUTPUT0 |
2055 GRC_LCLCTRL_GPIO_OUTPUT1 |
2057 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2059 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2060 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2062 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2063 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2066 u32 grc_local_ctrl = 0;
2068 if (tp_peer != tp &&
2069 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2072 /* Workaround to prevent overdrawing Amps. */
2073 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2075 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2076 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2077 grc_local_ctrl, 100);
2080 /* On 5753 and variants, GPIO2 cannot be used. */
2081 no_gpio2 = tp->nic_sram_data_cfg &
2082 NIC_SRAM_DATA_CFG_NO_GPIO2;
2084 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2085 GRC_LCLCTRL_GPIO_OE1 |
2086 GRC_LCLCTRL_GPIO_OE2 |
2087 GRC_LCLCTRL_GPIO_OUTPUT1 |
2088 GRC_LCLCTRL_GPIO_OUTPUT2;
2090 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2091 GRC_LCLCTRL_GPIO_OUTPUT2);
2093 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2094 grc_local_ctrl, 100);
2096 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2098 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2099 grc_local_ctrl, 100);
2102 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2103 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2104 grc_local_ctrl, 100);
2108 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2109 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2110 if (tp_peer != tp &&
2111 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2114 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2115 (GRC_LCLCTRL_GPIO_OE1 |
2116 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2118 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2119 GRC_LCLCTRL_GPIO_OE1, 100);
2121 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2122 (GRC_LCLCTRL_GPIO_OE1 |
2123 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2128 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2130 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2132 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2133 if (speed != SPEED_10)
2135 } else if (speed == SPEED_10)
2141 static int tg3_setup_phy(struct tg3 *, int);
2143 #define RESET_KIND_SHUTDOWN 0
2144 #define RESET_KIND_INIT 1
2145 #define RESET_KIND_SUSPEND 2
2147 static void tg3_write_sig_post_reset(struct tg3 *, int);
2148 static int tg3_halt_cpu(struct tg3 *, u32);
2150 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2154 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2155 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2156 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2157 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2160 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2161 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2162 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2167 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2169 val = tr32(GRC_MISC_CFG);
2170 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2173 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2175 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2178 tg3_writephy(tp, MII_ADVERTISE, 0);
2179 tg3_writephy(tp, MII_BMCR,
2180 BMCR_ANENABLE | BMCR_ANRESTART);
2182 tg3_writephy(tp, MII_TG3_FET_TEST,
2183 phytest | MII_TG3_FET_SHADOW_EN);
2184 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2185 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2187 MII_TG3_FET_SHDW_AUXMODE4,
2190 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2193 } else if (do_low_power) {
2194 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2195 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2197 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2198 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2199 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2200 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2201 MII_TG3_AUXCTL_PCTL_VREG_11V);
2204 /* The PHY should not be powered down on some chips because
2207 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2208 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2209 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2210 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2213 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2214 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2215 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2216 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2217 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2218 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2221 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2224 /* tp->lock is held. */
2225 static int tg3_nvram_lock(struct tg3 *tp)
2227 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2230 if (tp->nvram_lock_cnt == 0) {
2231 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2232 for (i = 0; i < 8000; i++) {
2233 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2238 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2242 tp->nvram_lock_cnt++;
2247 /* tp->lock is held. */
2248 static void tg3_nvram_unlock(struct tg3 *tp)
2250 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2251 if (tp->nvram_lock_cnt > 0)
2252 tp->nvram_lock_cnt--;
2253 if (tp->nvram_lock_cnt == 0)
2254 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2258 /* tp->lock is held. */
2259 static void tg3_enable_nvram_access(struct tg3 *tp)
2261 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2262 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2263 u32 nvaccess = tr32(NVRAM_ACCESS);
2265 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2269 /* tp->lock is held. */
2270 static void tg3_disable_nvram_access(struct tg3 *tp)
2272 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2273 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2274 u32 nvaccess = tr32(NVRAM_ACCESS);
2276 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2280 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2281 u32 offset, u32 *val)
2286 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2289 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2290 EEPROM_ADDR_DEVID_MASK |
2292 tw32(GRC_EEPROM_ADDR,
2294 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2295 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2296 EEPROM_ADDR_ADDR_MASK) |
2297 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2299 for (i = 0; i < 1000; i++) {
2300 tmp = tr32(GRC_EEPROM_ADDR);
2302 if (tmp & EEPROM_ADDR_COMPLETE)
2306 if (!(tmp & EEPROM_ADDR_COMPLETE))
2309 tmp = tr32(GRC_EEPROM_DATA);
2312 * The data will always be opposite the native endian
2313 * format. Perform a blind byteswap to compensate.
2320 #define NVRAM_CMD_TIMEOUT 10000
2322 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2326 tw32(NVRAM_CMD, nvram_cmd);
2327 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2329 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2335 if (i == NVRAM_CMD_TIMEOUT)
2341 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2343 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2344 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2345 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2346 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2347 (tp->nvram_jedecnum == JEDEC_ATMEL))
2349 addr = ((addr / tp->nvram_pagesize) <<
2350 ATMEL_AT45DB0X1B_PAGE_POS) +
2351 (addr % tp->nvram_pagesize);
2356 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2358 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2359 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2360 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2361 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2362 (tp->nvram_jedecnum == JEDEC_ATMEL))
2364 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2365 tp->nvram_pagesize) +
2366 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2371 /* NOTE: Data read in from NVRAM is byteswapped according to
2372 * the byteswapping settings for all other register accesses.
2373 * tg3 devices are BE devices, so on a BE machine, the data
2374 * returned will be exactly as it is seen in NVRAM. On a LE
2375 * machine, the 32-bit value will be byteswapped.
2377 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2381 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2382 return tg3_nvram_read_using_eeprom(tp, offset, val);
2384 offset = tg3_nvram_phys_addr(tp, offset);
2386 if (offset > NVRAM_ADDR_MSK)
2389 ret = tg3_nvram_lock(tp);
2393 tg3_enable_nvram_access(tp);
2395 tw32(NVRAM_ADDR, offset);
2396 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2397 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2400 *val = tr32(NVRAM_RDDATA);
2402 tg3_disable_nvram_access(tp);
2404 tg3_nvram_unlock(tp);
2409 /* Ensures NVRAM data is in bytestream format. */
2410 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2413 int res = tg3_nvram_read(tp, offset, &v);
2415 *val = cpu_to_be32(v);
2419 /* tp->lock is held. */
2420 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2422 u32 addr_high, addr_low;
2425 addr_high = ((tp->dev->dev_addr[0] << 8) |
2426 tp->dev->dev_addr[1]);
2427 addr_low = ((tp->dev->dev_addr[2] << 24) |
2428 (tp->dev->dev_addr[3] << 16) |
2429 (tp->dev->dev_addr[4] << 8) |
2430 (tp->dev->dev_addr[5] << 0));
2431 for (i = 0; i < 4; i++) {
2432 if (i == 1 && skip_mac_1)
2434 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2435 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2438 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2439 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2440 for (i = 0; i < 12; i++) {
2441 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2442 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2446 addr_high = (tp->dev->dev_addr[0] +
2447 tp->dev->dev_addr[1] +
2448 tp->dev->dev_addr[2] +
2449 tp->dev->dev_addr[3] +
2450 tp->dev->dev_addr[4] +
2451 tp->dev->dev_addr[5]) &
2452 TX_BACKOFF_SEED_MASK;
2453 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2456 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2459 bool device_should_wake, do_low_power;
2461 /* Make sure register accesses (indirect or otherwise)
2462 * will function correctly.
2464 pci_write_config_dword(tp->pdev,
2465 TG3PCI_MISC_HOST_CTRL,
2466 tp->misc_host_ctrl);
2470 pci_enable_wake(tp->pdev, state, false);
2471 pci_set_power_state(tp->pdev, PCI_D0);
2473 /* Switch out of Vaux if it is a NIC */
2474 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2475 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2485 netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
2490 /* Restore the CLKREQ setting. */
2491 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2494 pci_read_config_word(tp->pdev,
2495 tp->pcie_cap + PCI_EXP_LNKCTL,
2497 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2498 pci_write_config_word(tp->pdev,
2499 tp->pcie_cap + PCI_EXP_LNKCTL,
2503 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2504 tw32(TG3PCI_MISC_HOST_CTRL,
2505 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2507 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2508 device_may_wakeup(&tp->pdev->dev) &&
2509 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2511 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2512 do_low_power = false;
2513 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
2514 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2515 struct phy_device *phydev;
2516 u32 phyid, advertising;
2518 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2520 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2522 tp->link_config.orig_speed = phydev->speed;
2523 tp->link_config.orig_duplex = phydev->duplex;
2524 tp->link_config.orig_autoneg = phydev->autoneg;
2525 tp->link_config.orig_advertising = phydev->advertising;
2527 advertising = ADVERTISED_TP |
2529 ADVERTISED_Autoneg |
2530 ADVERTISED_10baseT_Half;
2532 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2533 device_should_wake) {
2534 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2536 ADVERTISED_100baseT_Half |
2537 ADVERTISED_100baseT_Full |
2538 ADVERTISED_10baseT_Full;
2540 advertising |= ADVERTISED_10baseT_Full;
2543 phydev->advertising = advertising;
2545 phy_start_aneg(phydev);
2547 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2548 if (phyid != PHY_ID_BCMAC131) {
2549 phyid &= PHY_BCM_OUI_MASK;
2550 if (phyid == PHY_BCM_OUI_1 ||
2551 phyid == PHY_BCM_OUI_2 ||
2552 phyid == PHY_BCM_OUI_3)
2553 do_low_power = true;
2557 do_low_power = true;
2559 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2560 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2561 tp->link_config.orig_speed = tp->link_config.speed;
2562 tp->link_config.orig_duplex = tp->link_config.duplex;
2563 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2566 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
2567 tp->link_config.speed = SPEED_10;
2568 tp->link_config.duplex = DUPLEX_HALF;
2569 tp->link_config.autoneg = AUTONEG_ENABLE;
2570 tg3_setup_phy(tp, 0);
2574 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2577 val = tr32(GRC_VCPU_EXT_CTRL);
2578 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2579 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2583 for (i = 0; i < 200; i++) {
2584 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2585 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2590 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2591 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2592 WOL_DRV_STATE_SHUTDOWN |
2596 if (device_should_wake) {
2599 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
2601 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2605 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
2606 mac_mode = MAC_MODE_PORT_MODE_GMII;
2608 mac_mode = MAC_MODE_PORT_MODE_MII;
2610 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2611 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2613 u32 speed = (tp->tg3_flags &
2614 TG3_FLAG_WOL_SPEED_100MB) ?
2615 SPEED_100 : SPEED_10;
2616 if (tg3_5700_link_polarity(tp, speed))
2617 mac_mode |= MAC_MODE_LINK_POLARITY;
2619 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2622 mac_mode = MAC_MODE_PORT_MODE_TBI;
2625 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2626 tw32(MAC_LED_CTRL, tp->led_ctrl);
2628 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2629 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2630 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2631 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2632 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2633 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2635 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2636 mac_mode |= tp->mac_mode &
2637 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2638 if (mac_mode & MAC_MODE_APE_TX_EN)
2639 mac_mode |= MAC_MODE_TDE_ENABLE;
2642 tw32_f(MAC_MODE, mac_mode);
2645 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2649 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2650 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2651 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2654 base_val = tp->pci_clock_ctrl;
2655 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2656 CLOCK_CTRL_TXCLK_DISABLE);
2658 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2659 CLOCK_CTRL_PWRDOWN_PLL133, 40);
2660 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2661 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2662 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2664 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2665 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2666 u32 newbits1, newbits2;
2668 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2669 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2670 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2671 CLOCK_CTRL_TXCLK_DISABLE |
2673 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2674 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2675 newbits1 = CLOCK_CTRL_625_CORE;
2676 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2678 newbits1 = CLOCK_CTRL_ALTCLK;
2679 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2682 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2685 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2688 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2691 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2692 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2693 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2694 CLOCK_CTRL_TXCLK_DISABLE |
2695 CLOCK_CTRL_44MHZ_CORE);
2697 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2700 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2701 tp->pci_clock_ctrl | newbits3, 40);
2705 if (!(device_should_wake) &&
2706 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2707 tg3_power_down_phy(tp, do_low_power);
2709 tg3_frob_aux_power(tp);
2711 /* Workaround for unstable PLL clock */
2712 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2713 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2714 u32 val = tr32(0x7d00);
2716 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2718 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2721 err = tg3_nvram_lock(tp);
2722 tg3_halt_cpu(tp, RX_CPU_BASE);
2724 tg3_nvram_unlock(tp);
2728 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2730 if (device_should_wake)
2731 pci_enable_wake(tp->pdev, state, true);
2733 /* Finally, set the new power state. */
2734 pci_set_power_state(tp->pdev, state);
2739 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2741 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2742 case MII_TG3_AUX_STAT_10HALF:
2744 *duplex = DUPLEX_HALF;
2747 case MII_TG3_AUX_STAT_10FULL:
2749 *duplex = DUPLEX_FULL;
2752 case MII_TG3_AUX_STAT_100HALF:
2754 *duplex = DUPLEX_HALF;
2757 case MII_TG3_AUX_STAT_100FULL:
2759 *duplex = DUPLEX_FULL;
2762 case MII_TG3_AUX_STAT_1000HALF:
2763 *speed = SPEED_1000;
2764 *duplex = DUPLEX_HALF;
2767 case MII_TG3_AUX_STAT_1000FULL:
2768 *speed = SPEED_1000;
2769 *duplex = DUPLEX_FULL;
2773 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2774 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2776 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2780 *speed = SPEED_INVALID;
2781 *duplex = DUPLEX_INVALID;
2786 static void tg3_phy_copper_begin(struct tg3 *tp)
2791 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2792 /* Entering low power mode. Disable gigabit and
2793 * 100baseT advertisements.
2795 tg3_writephy(tp, MII_TG3_CTRL, 0);
2797 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2798 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2799 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2800 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2802 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2803 } else if (tp->link_config.speed == SPEED_INVALID) {
2804 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
2805 tp->link_config.advertising &=
2806 ~(ADVERTISED_1000baseT_Half |
2807 ADVERTISED_1000baseT_Full);
2809 new_adv = ADVERTISE_CSMA;
2810 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2811 new_adv |= ADVERTISE_10HALF;
2812 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2813 new_adv |= ADVERTISE_10FULL;
2814 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2815 new_adv |= ADVERTISE_100HALF;
2816 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2817 new_adv |= ADVERTISE_100FULL;
2819 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2821 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2823 if (tp->link_config.advertising &
2824 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2826 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2827 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2828 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2829 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2830 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) &&
2831 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2832 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2833 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2834 MII_TG3_CTRL_ENABLE_AS_MASTER);
2835 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2837 tg3_writephy(tp, MII_TG3_CTRL, 0);
2840 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2841 new_adv |= ADVERTISE_CSMA;
2843 /* Asking for a specific link mode. */
2844 if (tp->link_config.speed == SPEED_1000) {
2845 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2847 if (tp->link_config.duplex == DUPLEX_FULL)
2848 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2850 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2851 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2852 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2853 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2854 MII_TG3_CTRL_ENABLE_AS_MASTER);
2856 if (tp->link_config.speed == SPEED_100) {
2857 if (tp->link_config.duplex == DUPLEX_FULL)
2858 new_adv |= ADVERTISE_100FULL;
2860 new_adv |= ADVERTISE_100HALF;
2862 if (tp->link_config.duplex == DUPLEX_FULL)
2863 new_adv |= ADVERTISE_10FULL;
2865 new_adv |= ADVERTISE_10HALF;
2867 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2872 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2875 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2876 tp->link_config.speed != SPEED_INVALID) {
2877 u32 bmcr, orig_bmcr;
2879 tp->link_config.active_speed = tp->link_config.speed;
2880 tp->link_config.active_duplex = tp->link_config.duplex;
2883 switch (tp->link_config.speed) {
2889 bmcr |= BMCR_SPEED100;
2893 bmcr |= TG3_BMCR_SPEED1000;
2897 if (tp->link_config.duplex == DUPLEX_FULL)
2898 bmcr |= BMCR_FULLDPLX;
2900 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2901 (bmcr != orig_bmcr)) {
2902 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2903 for (i = 0; i < 1500; i++) {
2907 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2908 tg3_readphy(tp, MII_BMSR, &tmp))
2910 if (!(tmp & BMSR_LSTATUS)) {
2915 tg3_writephy(tp, MII_BMCR, bmcr);
2919 tg3_writephy(tp, MII_BMCR,
2920 BMCR_ANENABLE | BMCR_ANRESTART);
2924 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2928 /* Turn off tap power management. */
2929 /* Set Extended packet length bit */
2930 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2932 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
2933 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
2934 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
2935 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
2936 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
2943 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2945 u32 adv_reg, all_mask = 0;
2947 if (mask & ADVERTISED_10baseT_Half)
2948 all_mask |= ADVERTISE_10HALF;
2949 if (mask & ADVERTISED_10baseT_Full)
2950 all_mask |= ADVERTISE_10FULL;
2951 if (mask & ADVERTISED_100baseT_Half)
2952 all_mask |= ADVERTISE_100HALF;
2953 if (mask & ADVERTISED_100baseT_Full)
2954 all_mask |= ADVERTISE_100FULL;
2956 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2959 if ((adv_reg & all_mask) != all_mask)
2961 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
2965 if (mask & ADVERTISED_1000baseT_Half)
2966 all_mask |= ADVERTISE_1000HALF;
2967 if (mask & ADVERTISED_1000baseT_Full)
2968 all_mask |= ADVERTISE_1000FULL;
2970 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2973 if ((tg3_ctrl & all_mask) != all_mask)
2979 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2983 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2986 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2987 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2989 if (tp->link_config.active_duplex == DUPLEX_FULL) {
2990 if (curadv != reqadv)
2993 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2994 tg3_readphy(tp, MII_LPA, rmtadv);
2996 /* Reprogram the advertisement register, even if it
2997 * does not affect the current link. If the link
2998 * gets renegotiated in the future, we can save an
2999 * additional renegotiation cycle by advertising
3000 * it correctly in the first place.
3002 if (curadv != reqadv) {
3003 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3004 ADVERTISE_PAUSE_ASYM);
3005 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3012 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3014 int current_link_up;
3016 u32 lcl_adv, rmt_adv;
3024 (MAC_STATUS_SYNC_CHANGED |
3025 MAC_STATUS_CFG_CHANGED |
3026 MAC_STATUS_MI_COMPLETION |
3027 MAC_STATUS_LNKSTATE_CHANGED));
3030 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3032 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3036 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3038 /* Some third-party PHYs need to be reset on link going
3041 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3042 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3043 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3044 netif_carrier_ok(tp->dev)) {
3045 tg3_readphy(tp, MII_BMSR, &bmsr);
3046 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3047 !(bmsr & BMSR_LSTATUS))
3053 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3054 tg3_readphy(tp, MII_BMSR, &bmsr);
3055 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3056 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3059 if (!(bmsr & BMSR_LSTATUS)) {
3060 err = tg3_init_5401phy_dsp(tp);
3064 tg3_readphy(tp, MII_BMSR, &bmsr);
3065 for (i = 0; i < 1000; i++) {
3067 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3068 (bmsr & BMSR_LSTATUS)) {
3074 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3075 TG3_PHY_REV_BCM5401_B0 &&
3076 !(bmsr & BMSR_LSTATUS) &&
3077 tp->link_config.active_speed == SPEED_1000) {
3078 err = tg3_phy_reset(tp);
3080 err = tg3_init_5401phy_dsp(tp);
3085 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3086 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3087 /* 5701 {A0,B0} CRC bug workaround */
3088 tg3_writephy(tp, 0x15, 0x0a75);
3089 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3090 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3091 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3094 /* Clear pending interrupts... */
3095 tg3_readphy(tp, MII_TG3_ISTAT, &val);
3096 tg3_readphy(tp, MII_TG3_ISTAT, &val);
3098 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3099 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3100 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3101 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3103 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3104 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3105 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3106 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3107 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3109 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3112 current_link_up = 0;
3113 current_speed = SPEED_INVALID;
3114 current_duplex = DUPLEX_INVALID;
3116 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3117 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3118 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3119 if (!(val & (1 << 10))) {
3121 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3127 for (i = 0; i < 100; i++) {
3128 tg3_readphy(tp, MII_BMSR, &bmsr);
3129 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3130 (bmsr & BMSR_LSTATUS))
3135 if (bmsr & BMSR_LSTATUS) {
3138 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3139 for (i = 0; i < 2000; i++) {
3141 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3146 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3151 for (i = 0; i < 200; i++) {
3152 tg3_readphy(tp, MII_BMCR, &bmcr);
3153 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3155 if (bmcr && bmcr != 0x7fff)
3163 tp->link_config.active_speed = current_speed;
3164 tp->link_config.active_duplex = current_duplex;
3166 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3167 if ((bmcr & BMCR_ANENABLE) &&
3168 tg3_copper_is_advertising_all(tp,
3169 tp->link_config.advertising)) {
3170 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3172 current_link_up = 1;
3175 if (!(bmcr & BMCR_ANENABLE) &&
3176 tp->link_config.speed == current_speed &&
3177 tp->link_config.duplex == current_duplex &&
3178 tp->link_config.flowctrl ==
3179 tp->link_config.active_flowctrl) {
3180 current_link_up = 1;
3184 if (current_link_up == 1 &&
3185 tp->link_config.active_duplex == DUPLEX_FULL)
3186 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3190 if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3191 tg3_phy_copper_begin(tp);
3193 tg3_readphy(tp, MII_BMSR, &bmsr);
3194 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3195 (bmsr & BMSR_LSTATUS))
3196 current_link_up = 1;
3199 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3200 if (current_link_up == 1) {
3201 if (tp->link_config.active_speed == SPEED_100 ||
3202 tp->link_config.active_speed == SPEED_10)
3203 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3205 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3206 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
3207 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3209 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3211 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3212 if (tp->link_config.active_duplex == DUPLEX_HALF)
3213 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3215 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3216 if (current_link_up == 1 &&
3217 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3218 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3220 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3223 /* ??? Without this setting Netgear GA302T PHY does not
3224 * ??? send/receive packets...
3226 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3227 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3228 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3229 tw32_f(MAC_MI_MODE, tp->mi_mode);
3233 tw32_f(MAC_MODE, tp->mac_mode);
3236 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3237 /* Polled via timer. */
3238 tw32_f(MAC_EVENT, 0);
3240 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3244 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3245 current_link_up == 1 &&
3246 tp->link_config.active_speed == SPEED_1000 &&
3247 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3248 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3251 (MAC_STATUS_SYNC_CHANGED |
3252 MAC_STATUS_CFG_CHANGED));
3255 NIC_SRAM_FIRMWARE_MBOX,
3256 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3259 /* Prevent send BD corruption. */
3260 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3261 u16 oldlnkctl, newlnkctl;
3263 pci_read_config_word(tp->pdev,
3264 tp->pcie_cap + PCI_EXP_LNKCTL,
3266 if (tp->link_config.active_speed == SPEED_100 ||
3267 tp->link_config.active_speed == SPEED_10)
3268 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3270 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3271 if (newlnkctl != oldlnkctl)
3272 pci_write_config_word(tp->pdev,
3273 tp->pcie_cap + PCI_EXP_LNKCTL,
3277 if (current_link_up != netif_carrier_ok(tp->dev)) {
3278 if (current_link_up)
3279 netif_carrier_on(tp->dev);
3281 netif_carrier_off(tp->dev);
3282 tg3_link_report(tp);
3288 struct tg3_fiber_aneginfo {
3290 #define ANEG_STATE_UNKNOWN 0
3291 #define ANEG_STATE_AN_ENABLE 1
3292 #define ANEG_STATE_RESTART_INIT 2
3293 #define ANEG_STATE_RESTART 3
3294 #define ANEG_STATE_DISABLE_LINK_OK 4
3295 #define ANEG_STATE_ABILITY_DETECT_INIT 5
3296 #define ANEG_STATE_ABILITY_DETECT 6
3297 #define ANEG_STATE_ACK_DETECT_INIT 7
3298 #define ANEG_STATE_ACK_DETECT 8
3299 #define ANEG_STATE_COMPLETE_ACK_INIT 9
3300 #define ANEG_STATE_COMPLETE_ACK 10
3301 #define ANEG_STATE_IDLE_DETECT_INIT 11
3302 #define ANEG_STATE_IDLE_DETECT 12
3303 #define ANEG_STATE_LINK_OK 13
3304 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3305 #define ANEG_STATE_NEXT_PAGE_WAIT 15
3308 #define MR_AN_ENABLE 0x00000001
3309 #define MR_RESTART_AN 0x00000002
3310 #define MR_AN_COMPLETE 0x00000004
3311 #define MR_PAGE_RX 0x00000008
3312 #define MR_NP_LOADED 0x00000010
3313 #define MR_TOGGLE_TX 0x00000020
3314 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
3315 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
3316 #define MR_LP_ADV_SYM_PAUSE 0x00000100
3317 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
3318 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3319 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3320 #define MR_LP_ADV_NEXT_PAGE 0x00001000
3321 #define MR_TOGGLE_RX 0x00002000
3322 #define MR_NP_RX 0x00004000
3324 #define MR_LINK_OK 0x80000000
3326 unsigned long link_time, cur_time;
3328 u32 ability_match_cfg;
3329 int ability_match_count;
3331 char ability_match, idle_match, ack_match;
3333 u32 txconfig, rxconfig;
3334 #define ANEG_CFG_NP 0x00000080
3335 #define ANEG_CFG_ACK 0x00000040
3336 #define ANEG_CFG_RF2 0x00000020
3337 #define ANEG_CFG_RF1 0x00000010
3338 #define ANEG_CFG_PS2 0x00000001
3339 #define ANEG_CFG_PS1 0x00008000
3340 #define ANEG_CFG_HD 0x00004000
3341 #define ANEG_CFG_FD 0x00002000
3342 #define ANEG_CFG_INVAL 0x00001f06
3347 #define ANEG_TIMER_ENAB 2
3348 #define ANEG_FAILED -1
3350 #define ANEG_STATE_SETTLE_TIME 10000
3352 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3353 struct tg3_fiber_aneginfo *ap)
3356 unsigned long delta;
3360 if (ap->state == ANEG_STATE_UNKNOWN) {
3364 ap->ability_match_cfg = 0;
3365 ap->ability_match_count = 0;
3366 ap->ability_match = 0;
3372 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3373 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3375 if (rx_cfg_reg != ap->ability_match_cfg) {
3376 ap->ability_match_cfg = rx_cfg_reg;
3377 ap->ability_match = 0;
3378 ap->ability_match_count = 0;
3380 if (++ap->ability_match_count > 1) {
3381 ap->ability_match = 1;
3382 ap->ability_match_cfg = rx_cfg_reg;
3385 if (rx_cfg_reg & ANEG_CFG_ACK)
3393 ap->ability_match_cfg = 0;
3394 ap->ability_match_count = 0;
3395 ap->ability_match = 0;
3401 ap->rxconfig = rx_cfg_reg;
3404 switch (ap->state) {
3405 case ANEG_STATE_UNKNOWN:
3406 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3407 ap->state = ANEG_STATE_AN_ENABLE;
3410 case ANEG_STATE_AN_ENABLE:
3411 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3412 if (ap->flags & MR_AN_ENABLE) {
3415 ap->ability_match_cfg = 0;
3416 ap->ability_match_count = 0;
3417 ap->ability_match = 0;
3421 ap->state = ANEG_STATE_RESTART_INIT;
3423 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3427 case ANEG_STATE_RESTART_INIT:
3428 ap->link_time = ap->cur_time;
3429 ap->flags &= ~(MR_NP_LOADED);
3431 tw32(MAC_TX_AUTO_NEG, 0);
3432 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3433 tw32_f(MAC_MODE, tp->mac_mode);
3436 ret = ANEG_TIMER_ENAB;
3437 ap->state = ANEG_STATE_RESTART;
3440 case ANEG_STATE_RESTART:
3441 delta = ap->cur_time - ap->link_time;
3442 if (delta > ANEG_STATE_SETTLE_TIME)
3443 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3445 ret = ANEG_TIMER_ENAB;
3448 case ANEG_STATE_DISABLE_LINK_OK:
3452 case ANEG_STATE_ABILITY_DETECT_INIT:
3453 ap->flags &= ~(MR_TOGGLE_TX);
3454 ap->txconfig = ANEG_CFG_FD;
3455 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3456 if (flowctrl & ADVERTISE_1000XPAUSE)
3457 ap->txconfig |= ANEG_CFG_PS1;
3458 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3459 ap->txconfig |= ANEG_CFG_PS2;
3460 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3461 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3462 tw32_f(MAC_MODE, tp->mac_mode);
3465 ap->state = ANEG_STATE_ABILITY_DETECT;
3468 case ANEG_STATE_ABILITY_DETECT:
3469 if (ap->ability_match != 0 && ap->rxconfig != 0)
3470 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3473 case ANEG_STATE_ACK_DETECT_INIT:
3474 ap->txconfig |= ANEG_CFG_ACK;
3475 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3476 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3477 tw32_f(MAC_MODE, tp->mac_mode);
3480 ap->state = ANEG_STATE_ACK_DETECT;
3483 case ANEG_STATE_ACK_DETECT:
3484 if (ap->ack_match != 0) {
3485 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3486 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3487 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3489 ap->state = ANEG_STATE_AN_ENABLE;
3491 } else if (ap->ability_match != 0 &&
3492 ap->rxconfig == 0) {
3493 ap->state = ANEG_STATE_AN_ENABLE;
3497 case ANEG_STATE_COMPLETE_ACK_INIT:
3498 if (ap->rxconfig & ANEG_CFG_INVAL) {
3502 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3503 MR_LP_ADV_HALF_DUPLEX |
3504 MR_LP_ADV_SYM_PAUSE |
3505 MR_LP_ADV_ASYM_PAUSE |
3506 MR_LP_ADV_REMOTE_FAULT1 |
3507 MR_LP_ADV_REMOTE_FAULT2 |
3508 MR_LP_ADV_NEXT_PAGE |
3511 if (ap->rxconfig & ANEG_CFG_FD)
3512 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3513 if (ap->rxconfig & ANEG_CFG_HD)
3514 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3515 if (ap->rxconfig & ANEG_CFG_PS1)
3516 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3517 if (ap->rxconfig & ANEG_CFG_PS2)
3518 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3519 if (ap->rxconfig & ANEG_CFG_RF1)
3520 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3521 if (ap->rxconfig & ANEG_CFG_RF2)
3522 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3523 if (ap->rxconfig & ANEG_CFG_NP)
3524 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3526 ap->link_time = ap->cur_time;
3528 ap->flags ^= (MR_TOGGLE_TX);
3529 if (ap->rxconfig & 0x0008)
3530 ap->flags |= MR_TOGGLE_RX;
3531 if (ap->rxconfig & ANEG_CFG_NP)
3532 ap->flags |= MR_NP_RX;
3533 ap->flags |= MR_PAGE_RX;
3535 ap->state = ANEG_STATE_COMPLETE_ACK;
3536 ret = ANEG_TIMER_ENAB;
3539 case ANEG_STATE_COMPLETE_ACK:
3540 if (ap->ability_match != 0 &&
3541 ap->rxconfig == 0) {
3542 ap->state = ANEG_STATE_AN_ENABLE;
3545 delta = ap->cur_time - ap->link_time;
3546 if (delta > ANEG_STATE_SETTLE_TIME) {
3547 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3548 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3550 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3551 !(ap->flags & MR_NP_RX)) {
3552 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3560 case ANEG_STATE_IDLE_DETECT_INIT:
3561 ap->link_time = ap->cur_time;
3562 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3563 tw32_f(MAC_MODE, tp->mac_mode);
3566 ap->state = ANEG_STATE_IDLE_DETECT;
3567 ret = ANEG_TIMER_ENAB;
3570 case ANEG_STATE_IDLE_DETECT:
3571 if (ap->ability_match != 0 &&
3572 ap->rxconfig == 0) {
3573 ap->state = ANEG_STATE_AN_ENABLE;
3576 delta = ap->cur_time - ap->link_time;
3577 if (delta > ANEG_STATE_SETTLE_TIME) {
3578 /* XXX another gem from the Broadcom driver :( */
3579 ap->state = ANEG_STATE_LINK_OK;
3583 case ANEG_STATE_LINK_OK:
3584 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3588 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3589 /* ??? unimplemented */
3592 case ANEG_STATE_NEXT_PAGE_WAIT:
3593 /* ??? unimplemented */
3604 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3607 struct tg3_fiber_aneginfo aninfo;
3608 int status = ANEG_FAILED;
3612 tw32_f(MAC_TX_AUTO_NEG, 0);
3614 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3615 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3618 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3621 memset(&aninfo, 0, sizeof(aninfo));
3622 aninfo.flags |= MR_AN_ENABLE;
3623 aninfo.state = ANEG_STATE_UNKNOWN;
3624 aninfo.cur_time = 0;
3626 while (++tick < 195000) {
3627 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3628 if (status == ANEG_DONE || status == ANEG_FAILED)
3634 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3635 tw32_f(MAC_MODE, tp->mac_mode);
3638 *txflags = aninfo.txconfig;
3639 *rxflags = aninfo.flags;
3641 if (status == ANEG_DONE &&
3642 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3643 MR_LP_ADV_FULL_DUPLEX)))
3649 static void tg3_init_bcm8002(struct tg3 *tp)
3651 u32 mac_status = tr32(MAC_STATUS);
3654 /* Reset when initting first time or we have a link. */
3655 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3656 !(mac_status & MAC_STATUS_PCS_SYNCED))
3659 /* Set PLL lock range. */
3660 tg3_writephy(tp, 0x16, 0x8007);
3663 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3665 /* Wait for reset to complete. */
3666 /* XXX schedule_timeout() ... */
3667 for (i = 0; i < 500; i++)
3670 /* Config mode; select PMA/Ch 1 regs. */
3671 tg3_writephy(tp, 0x10, 0x8411);
3673 /* Enable auto-lock and comdet, select txclk for tx. */
3674 tg3_writephy(tp, 0x11, 0x0a10);
3676 tg3_writephy(tp, 0x18, 0x00a0);
3677 tg3_writephy(tp, 0x16, 0x41ff);
3679 /* Assert and deassert POR. */
3680 tg3_writephy(tp, 0x13, 0x0400);
3682 tg3_writephy(tp, 0x13, 0x0000);
3684 tg3_writephy(tp, 0x11, 0x0a50);
3686 tg3_writephy(tp, 0x11, 0x0a10);
3688 /* Wait for signal to stabilize */
3689 /* XXX schedule_timeout() ... */
3690 for (i = 0; i < 15000; i++)
3693 /* Deselect the channel register so we can read the PHYID
3696 tg3_writephy(tp, 0x10, 0x8011);
3699 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3702 u32 sg_dig_ctrl, sg_dig_status;
3703 u32 serdes_cfg, expected_sg_dig_ctrl;
3704 int workaround, port_a;
3705 int current_link_up;
3708 expected_sg_dig_ctrl = 0;
3711 current_link_up = 0;
3713 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3714 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3716 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3719 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3720 /* preserve bits 20-23 for voltage regulator */
3721 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3724 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3726 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3727 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3729 u32 val = serdes_cfg;
3735 tw32_f(MAC_SERDES_CFG, val);
3738 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3740 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3741 tg3_setup_flow_control(tp, 0, 0);
3742 current_link_up = 1;
3747 /* Want auto-negotiation. */
3748 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3750 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3751 if (flowctrl & ADVERTISE_1000XPAUSE)
3752 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3753 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3754 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3756 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3757 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3758 tp->serdes_counter &&
3759 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3760 MAC_STATUS_RCVD_CFG)) ==
3761 MAC_STATUS_PCS_SYNCED)) {
3762 tp->serdes_counter--;
3763 current_link_up = 1;
3768 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3769 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3771 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3773 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3774 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3775 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3776 MAC_STATUS_SIGNAL_DET)) {
3777 sg_dig_status = tr32(SG_DIG_STATUS);
3778 mac_status = tr32(MAC_STATUS);
3780 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3781 (mac_status & MAC_STATUS_PCS_SYNCED)) {
3782 u32 local_adv = 0, remote_adv = 0;
3784 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3785 local_adv |= ADVERTISE_1000XPAUSE;
3786 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3787 local_adv |= ADVERTISE_1000XPSE_ASYM;
3789 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3790 remote_adv |= LPA_1000XPAUSE;
3791 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3792 remote_adv |= LPA_1000XPAUSE_ASYM;
3794 tg3_setup_flow_control(tp, local_adv, remote_adv);
3795 current_link_up = 1;
3796 tp->serdes_counter = 0;
3797 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3798 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3799 if (tp->serdes_counter)
3800 tp->serdes_counter--;
3803 u32 val = serdes_cfg;
3810 tw32_f(MAC_SERDES_CFG, val);
3813 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3816 /* Link parallel detection - link is up */
3817 /* only if we have PCS_SYNC and not */
3818 /* receiving config code words */
3819 mac_status = tr32(MAC_STATUS);
3820 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3821 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3822 tg3_setup_flow_control(tp, 0, 0);
3823 current_link_up = 1;
3825 TG3_PHYFLG_PARALLEL_DETECT;
3826 tp->serdes_counter =
3827 SERDES_PARALLEL_DET_TIMEOUT;
3829 goto restart_autoneg;
3833 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3834 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3838 return current_link_up;
3841 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3843 int current_link_up = 0;
3845 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3848 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3849 u32 txflags, rxflags;
3852 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3853 u32 local_adv = 0, remote_adv = 0;
3855 if (txflags & ANEG_CFG_PS1)
3856 local_adv |= ADVERTISE_1000XPAUSE;
3857 if (txflags & ANEG_CFG_PS2)
3858 local_adv |= ADVERTISE_1000XPSE_ASYM;
3860 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3861 remote_adv |= LPA_1000XPAUSE;
3862 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3863 remote_adv |= LPA_1000XPAUSE_ASYM;
3865 tg3_setup_flow_control(tp, local_adv, remote_adv);
3867 current_link_up = 1;
3869 for (i = 0; i < 30; i++) {
3872 (MAC_STATUS_SYNC_CHANGED |
3873 MAC_STATUS_CFG_CHANGED));
3875 if ((tr32(MAC_STATUS) &
3876 (MAC_STATUS_SYNC_CHANGED |
3877 MAC_STATUS_CFG_CHANGED)) == 0)
3881 mac_status = tr32(MAC_STATUS);
3882 if (current_link_up == 0 &&
3883 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3884 !(mac_status & MAC_STATUS_RCVD_CFG))
3885 current_link_up = 1;
3887 tg3_setup_flow_control(tp, 0, 0);
3889 /* Forcing 1000FD link up. */
3890 current_link_up = 1;
3892 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3895 tw32_f(MAC_MODE, tp->mac_mode);
3900 return current_link_up;
3903 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3906 u16 orig_active_speed;
3907 u8 orig_active_duplex;
3909 int current_link_up;
3912 orig_pause_cfg = tp->link_config.active_flowctrl;
3913 orig_active_speed = tp->link_config.active_speed;
3914 orig_active_duplex = tp->link_config.active_duplex;
3916 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3917 netif_carrier_ok(tp->dev) &&
3918 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3919 mac_status = tr32(MAC_STATUS);
3920 mac_status &= (MAC_STATUS_PCS_SYNCED |
3921 MAC_STATUS_SIGNAL_DET |
3922 MAC_STATUS_CFG_CHANGED |
3923 MAC_STATUS_RCVD_CFG);
3924 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3925 MAC_STATUS_SIGNAL_DET)) {
3926 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3927 MAC_STATUS_CFG_CHANGED));
3932 tw32_f(MAC_TX_AUTO_NEG, 0);
3934 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3935 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3936 tw32_f(MAC_MODE, tp->mac_mode);
3939 if (tp->phy_id == TG3_PHY_ID_BCM8002)
3940 tg3_init_bcm8002(tp);
3942 /* Enable link change event even when serdes polling. */
3943 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3946 current_link_up = 0;
3947 mac_status = tr32(MAC_STATUS);
3949 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3950 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3952 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3954 tp->napi[0].hw_status->status =
3955 (SD_STATUS_UPDATED |
3956 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3958 for (i = 0; i < 100; i++) {
3959 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3960 MAC_STATUS_CFG_CHANGED));
3962 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3963 MAC_STATUS_CFG_CHANGED |
3964 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3968 mac_status = tr32(MAC_STATUS);
3969 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3970 current_link_up = 0;
3971 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3972 tp->serdes_counter == 0) {
3973 tw32_f(MAC_MODE, (tp->mac_mode |
3974 MAC_MODE_SEND_CONFIGS));
3976 tw32_f(MAC_MODE, tp->mac_mode);
3980 if (current_link_up == 1) {
3981 tp->link_config.active_speed = SPEED_1000;
3982 tp->link_config.active_duplex = DUPLEX_FULL;
3983 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3984 LED_CTRL_LNKLED_OVERRIDE |
3985 LED_CTRL_1000MBPS_ON));
3987 tp->link_config.active_speed = SPEED_INVALID;
3988 tp->link_config.active_duplex = DUPLEX_INVALID;
3989 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3990 LED_CTRL_LNKLED_OVERRIDE |
3991 LED_CTRL_TRAFFIC_OVERRIDE));
3994 if (current_link_up != netif_carrier_ok(tp->dev)) {
3995 if (current_link_up)
3996 netif_carrier_on(tp->dev);
3998 netif_carrier_off(tp->dev);
3999 tg3_link_report(tp);
4001 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4002 if (orig_pause_cfg != now_pause_cfg ||
4003 orig_active_speed != tp->link_config.active_speed ||
4004 orig_active_duplex != tp->link_config.active_duplex)
4005 tg3_link_report(tp);
4011 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4013 int current_link_up, err = 0;
4017 u32 local_adv, remote_adv;
4019 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4020 tw32_f(MAC_MODE, tp->mac_mode);
4026 (MAC_STATUS_SYNC_CHANGED |
4027 MAC_STATUS_CFG_CHANGED |
4028 MAC_STATUS_MI_COMPLETION |
4029 MAC_STATUS_LNKSTATE_CHANGED));
4035 current_link_up = 0;
4036 current_speed = SPEED_INVALID;
4037 current_duplex = DUPLEX_INVALID;
4039 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4040 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4041 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4042 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4043 bmsr |= BMSR_LSTATUS;
4045 bmsr &= ~BMSR_LSTATUS;
4048 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4050 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4051 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4052 /* do nothing, just check for link up at the end */
4053 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4056 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4057 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4058 ADVERTISE_1000XPAUSE |
4059 ADVERTISE_1000XPSE_ASYM |
4062 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4064 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4065 new_adv |= ADVERTISE_1000XHALF;
4066 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4067 new_adv |= ADVERTISE_1000XFULL;
4069 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4070 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4071 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4072 tg3_writephy(tp, MII_BMCR, bmcr);
4074 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4075 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4076 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4083 bmcr &= ~BMCR_SPEED1000;
4084 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4086 if (tp->link_config.duplex == DUPLEX_FULL)
4087 new_bmcr |= BMCR_FULLDPLX;
4089 if (new_bmcr != bmcr) {
4090 /* BMCR_SPEED1000 is a reserved bit that needs
4091 * to be set on write.
4093 new_bmcr |= BMCR_SPEED1000;
4095 /* Force a linkdown */
4096 if (netif_carrier_ok(tp->dev)) {
4099 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4100 adv &= ~(ADVERTISE_1000XFULL |
4101 ADVERTISE_1000XHALF |
4103 tg3_writephy(tp, MII_ADVERTISE, adv);
4104 tg3_writephy(tp, MII_BMCR, bmcr |
4108 netif_carrier_off(tp->dev);
4110 tg3_writephy(tp, MII_BMCR, new_bmcr);
4112 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4113 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4114 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4116 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4117 bmsr |= BMSR_LSTATUS;
4119 bmsr &= ~BMSR_LSTATUS;
4121 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4125 if (bmsr & BMSR_LSTATUS) {
4126 current_speed = SPEED_1000;
4127 current_link_up = 1;
4128 if (bmcr & BMCR_FULLDPLX)
4129 current_duplex = DUPLEX_FULL;
4131 current_duplex = DUPLEX_HALF;
4136 if (bmcr & BMCR_ANENABLE) {
4139 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4140 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4141 common = local_adv & remote_adv;
4142 if (common & (ADVERTISE_1000XHALF |
4143 ADVERTISE_1000XFULL)) {
4144 if (common & ADVERTISE_1000XFULL)
4145 current_duplex = DUPLEX_FULL;
4147 current_duplex = DUPLEX_HALF;
4148 } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4149 /* Link is up via parallel detect */
4151 current_link_up = 0;
4156 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4157 tg3_setup_flow_control(tp, local_adv, remote_adv);
4159 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4160 if (tp->link_config.active_duplex == DUPLEX_HALF)
4161 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4163 tw32_f(MAC_MODE, tp->mac_mode);
4166 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4168 tp->link_config.active_speed = current_speed;
4169 tp->link_config.active_duplex = current_duplex;
4171 if (current_link_up != netif_carrier_ok(tp->dev)) {
4172 if (current_link_up)
4173 netif_carrier_on(tp->dev);
4175 netif_carrier_off(tp->dev);
4176 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4178 tg3_link_report(tp);
4183 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4185 if (tp->serdes_counter) {
4186 /* Give autoneg time to complete. */
4187 tp->serdes_counter--;
4191 if (!netif_carrier_ok(tp->dev) &&
4192 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4195 tg3_readphy(tp, MII_BMCR, &bmcr);
4196 if (bmcr & BMCR_ANENABLE) {
4199 /* Select shadow register 0x1f */
4200 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
4201 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
4203 /* Select expansion interrupt status register */
4204 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4205 MII_TG3_DSP_EXP1_INT_STAT);
4206 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4207 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4209 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4210 /* We have signal detect and not receiving
4211 * config code words, link is up by parallel
4215 bmcr &= ~BMCR_ANENABLE;
4216 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4217 tg3_writephy(tp, MII_BMCR, bmcr);
4218 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
4221 } else if (netif_carrier_ok(tp->dev) &&
4222 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4223 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4226 /* Select expansion interrupt status register */
4227 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4228 MII_TG3_DSP_EXP1_INT_STAT);
4229 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4233 /* Config code words received, turn on autoneg. */
4234 tg3_readphy(tp, MII_BMCR, &bmcr);
4235 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4237 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4243 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4247 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
4248 err = tg3_setup_fiber_phy(tp, force_reset);
4249 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4250 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4252 err = tg3_setup_copper_phy(tp, force_reset);
4254 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4257 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4258 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4260 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4265 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4266 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4267 tw32(GRC_MISC_CFG, val);
4270 if (tp->link_config.active_speed == SPEED_1000 &&
4271 tp->link_config.active_duplex == DUPLEX_HALF)
4272 tw32(MAC_TX_LENGTHS,
4273 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4274 (6 << TX_LENGTHS_IPG_SHIFT) |
4275 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4277 tw32(MAC_TX_LENGTHS,
4278 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4279 (6 << TX_LENGTHS_IPG_SHIFT) |
4280 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4282 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4283 if (netif_carrier_ok(tp->dev)) {
4284 tw32(HOSTCC_STAT_COAL_TICKS,
4285 tp->coal.stats_block_coalesce_usecs);
4287 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4291 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4292 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4293 if (!netif_carrier_ok(tp->dev))
4294 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4297 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4298 tw32(PCIE_PWR_MGMT_THRESH, val);
4304 static inline int tg3_irq_sync(struct tg3 *tp)
4306 return tp->irq_sync;
4309 /* This is called whenever we suspect that the system chipset is re-
4310 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4311 * is bogus tx completions. We try to recover by setting the
4312 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4315 static void tg3_tx_recover(struct tg3 *tp)
4317 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4318 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4320 netdev_warn(tp->dev,
4321 "The system may be re-ordering memory-mapped I/O "
4322 "cycles to the network device, attempting to recover. "
4323 "Please report the problem to the driver maintainer "
4324 "and include system chipset information.\n");
4326 spin_lock(&tp->lock);
4327 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4328 spin_unlock(&tp->lock);
4331 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4333 /* Tell compiler to fetch tx indices from memory. */
4335 return tnapi->tx_pending -
4336 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4339 /* Tigon3 never reports partial packet sends. So we do not
4340 * need special logic to handle SKBs that have not had all
4341 * of their frags sent yet, like SunGEM does.
4343 static void tg3_tx(struct tg3_napi *tnapi)
4345 struct tg3 *tp = tnapi->tp;
4346 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4347 u32 sw_idx = tnapi->tx_cons;
4348 struct netdev_queue *txq;
4349 int index = tnapi - tp->napi;
4351 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4354 txq = netdev_get_tx_queue(tp->dev, index);
4356 while (sw_idx != hw_idx) {
4357 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4358 struct sk_buff *skb = ri->skb;
4361 if (unlikely(skb == NULL)) {
4366 pci_unmap_single(tp->pdev,
4367 dma_unmap_addr(ri, mapping),
4373 sw_idx = NEXT_TX(sw_idx);
4375 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4376 ri = &tnapi->tx_buffers[sw_idx];
4377 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4380 pci_unmap_page(tp->pdev,
4381 dma_unmap_addr(ri, mapping),
4382 skb_shinfo(skb)->frags[i].size,
4384 sw_idx = NEXT_TX(sw_idx);
4389 if (unlikely(tx_bug)) {
4395 tnapi->tx_cons = sw_idx;
4397 /* Need to make the tx_cons update visible to tg3_start_xmit()
4398 * before checking for netif_queue_stopped(). Without the
4399 * memory barrier, there is a small possibility that tg3_start_xmit()
4400 * will miss it and cause the queue to be stopped forever.
4404 if (unlikely(netif_tx_queue_stopped(txq) &&
4405 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4406 __netif_tx_lock(txq, smp_processor_id());
4407 if (netif_tx_queue_stopped(txq) &&
4408 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4409 netif_tx_wake_queue(txq);
4410 __netif_tx_unlock(txq);
4414 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4419 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4420 map_sz, PCI_DMA_FROMDEVICE);
4421 dev_kfree_skb_any(ri->skb);
4425 /* Returns size of skb allocated or < 0 on error.
4427 * We only need to fill in the address because the other members
4428 * of the RX descriptor are invariant, see tg3_init_rings.
4430 * Note the purposeful assymetry of cpu vs. chip accesses. For
4431 * posting buffers we only dirty the first cache line of the RX
4432 * descriptor (containing the address). Whereas for the RX status
4433 * buffers the cpu only reads the last cacheline of the RX descriptor
4434 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4436 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4437 u32 opaque_key, u32 dest_idx_unmasked)
4439 struct tg3_rx_buffer_desc *desc;
4440 struct ring_info *map, *src_map;
4441 struct sk_buff *skb;
4443 int skb_size, dest_idx;
4446 switch (opaque_key) {
4447 case RXD_OPAQUE_RING_STD:
4448 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4449 desc = &tpr->rx_std[dest_idx];
4450 map = &tpr->rx_std_buffers[dest_idx];
4451 skb_size = tp->rx_pkt_map_sz;
4454 case RXD_OPAQUE_RING_JUMBO:
4455 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4456 desc = &tpr->rx_jmb[dest_idx].std;
4457 map = &tpr->rx_jmb_buffers[dest_idx];
4458 skb_size = TG3_RX_JMB_MAP_SZ;
4465 /* Do not overwrite any of the map or rp information
4466 * until we are sure we can commit to a new buffer.
4468 * Callers depend upon this behavior and assume that
4469 * we leave everything unchanged if we fail.
4471 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4475 skb_reserve(skb, tp->rx_offset);
4477 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4478 PCI_DMA_FROMDEVICE);
4479 if (pci_dma_mapping_error(tp->pdev, mapping)) {
4485 dma_unmap_addr_set(map, mapping, mapping);
4487 desc->addr_hi = ((u64)mapping >> 32);
4488 desc->addr_lo = ((u64)mapping & 0xffffffff);
4493 /* We only need to move over in the address because the other
4494 * members of the RX descriptor are invariant. See notes above
4495 * tg3_alloc_rx_skb for full details.
4497 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4498 struct tg3_rx_prodring_set *dpr,
4499 u32 opaque_key, int src_idx,
4500 u32 dest_idx_unmasked)
4502 struct tg3 *tp = tnapi->tp;
4503 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4504 struct ring_info *src_map, *dest_map;
4505 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
4508 switch (opaque_key) {
4509 case RXD_OPAQUE_RING_STD:
4510 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4511 dest_desc = &dpr->rx_std[dest_idx];
4512 dest_map = &dpr->rx_std_buffers[dest_idx];
4513 src_desc = &spr->rx_std[src_idx];
4514 src_map = &spr->rx_std_buffers[src_idx];
4517 case RXD_OPAQUE_RING_JUMBO:
4518 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4519 dest_desc = &dpr->rx_jmb[dest_idx].std;
4520 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4521 src_desc = &spr->rx_jmb[src_idx].std;
4522 src_map = &spr->rx_jmb_buffers[src_idx];
4529 dest_map->skb = src_map->skb;
4530 dma_unmap_addr_set(dest_map, mapping,
4531 dma_unmap_addr(src_map, mapping));
4532 dest_desc->addr_hi = src_desc->addr_hi;
4533 dest_desc->addr_lo = src_desc->addr_lo;
4535 /* Ensure that the update to the skb happens after the physical
4536 * addresses have been transferred to the new BD location.
4540 src_map->skb = NULL;
4543 /* The RX ring scheme is composed of multiple rings which post fresh
4544 * buffers to the chip, and one special ring the chip uses to report
4545 * status back to the host.
4547 * The special ring reports the status of received packets to the
4548 * host. The chip does not write into the original descriptor the
4549 * RX buffer was obtained from. The chip simply takes the original
4550 * descriptor as provided by the host, updates the status and length
4551 * field, then writes this into the next status ring entry.
4553 * Each ring the host uses to post buffers to the chip is described
4554 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4555 * it is first placed into the on-chip ram. When the packet's length
4556 * is known, it walks down the TG3_BDINFO entries to select the ring.
4557 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4558 * which is within the range of the new packet's length is chosen.
4560 * The "separate ring for rx status" scheme may sound queer, but it makes
4561 * sense from a cache coherency perspective. If only the host writes
4562 * to the buffer post rings, and only the chip writes to the rx status
4563 * rings, then cache lines never move beyond shared-modified state.
4564 * If both the host and chip were to write into the same ring, cache line
4565 * eviction could occur since both entities want it in an exclusive state.
4567 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4569 struct tg3 *tp = tnapi->tp;
4570 u32 work_mask, rx_std_posted = 0;
4571 u32 std_prod_idx, jmb_prod_idx;
4572 u32 sw_idx = tnapi->rx_rcb_ptr;
4575 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
4577 hw_idx = *(tnapi->rx_rcb_prod_idx);
4579 * We need to order the read of hw_idx and the read of
4580 * the opaque cookie.
4585 std_prod_idx = tpr->rx_std_prod_idx;
4586 jmb_prod_idx = tpr->rx_jmb_prod_idx;
4587 while (sw_idx != hw_idx && budget > 0) {
4588 struct ring_info *ri;
4589 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4591 struct sk_buff *skb;
4592 dma_addr_t dma_addr;
4593 u32 opaque_key, desc_idx, *post_ptr;
4594 bool hw_vlan __maybe_unused = false;
4595 u16 vtag __maybe_unused = 0;
4597 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4598 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4599 if (opaque_key == RXD_OPAQUE_RING_STD) {
4600 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4601 dma_addr = dma_unmap_addr(ri, mapping);
4603 post_ptr = &std_prod_idx;
4605 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4606 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4607 dma_addr = dma_unmap_addr(ri, mapping);
4609 post_ptr = &jmb_prod_idx;
4611 goto next_pkt_nopost;
4613 work_mask |= opaque_key;
4615 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4616 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4618 tg3_recycle_rx(tnapi, tpr, opaque_key,
4619 desc_idx, *post_ptr);
4621 /* Other statistics kept track of by card. */
4622 tp->net_stats.rx_dropped++;
4626 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4629 if (len > TG3_RX_COPY_THRESH(tp)) {
4632 skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4637 pci_unmap_single(tp->pdev, dma_addr, skb_size,
4638 PCI_DMA_FROMDEVICE);
4640 /* Ensure that the update to the skb happens
4641 * after the usage of the old DMA mapping.
4649 struct sk_buff *copy_skb;
4651 tg3_recycle_rx(tnapi, tpr, opaque_key,
4652 desc_idx, *post_ptr);
4654 copy_skb = netdev_alloc_skb(tp->dev, len + VLAN_HLEN +
4656 if (copy_skb == NULL)
4657 goto drop_it_no_recycle;
4659 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN + VLAN_HLEN);
4660 skb_put(copy_skb, len);
4661 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4662 skb_copy_from_linear_data(skb, copy_skb->data, len);
4663 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4665 /* We'll reuse the original ring buffer. */
4669 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4670 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4671 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4672 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4673 skb->ip_summed = CHECKSUM_UNNECESSARY;
4675 skb_checksum_none_assert(skb);
4677 skb->protocol = eth_type_trans(skb, tp->dev);
4679 if (len > (tp->dev->mtu + ETH_HLEN) &&
4680 skb->protocol != htons(ETH_P_8021Q)) {
4685 if (desc->type_flags & RXD_FLAG_VLAN &&
4686 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) {
4687 vtag = desc->err_vlan & RXD_VLAN_MASK;
4688 #if TG3_VLAN_TAG_USED
4694 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
4695 __skb_push(skb, VLAN_HLEN);
4697 memmove(ve, skb->data + VLAN_HLEN,
4699 ve->h_vlan_proto = htons(ETH_P_8021Q);
4700 ve->h_vlan_TCI = htons(vtag);
4704 #if TG3_VLAN_TAG_USED
4706 vlan_gro_receive(&tnapi->napi, tp->vlgrp, vtag, skb);
4709 napi_gro_receive(&tnapi->napi, skb);
4717 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4718 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4719 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4720 tpr->rx_std_prod_idx);
4721 work_mask &= ~RXD_OPAQUE_RING_STD;
4726 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4728 /* Refresh hw_idx to see if there is new work */
4729 if (sw_idx == hw_idx) {
4730 hw_idx = *(tnapi->rx_rcb_prod_idx);
4735 /* ACK the status ring. */
4736 tnapi->rx_rcb_ptr = sw_idx;
4737 tw32_rx_mbox(tnapi->consmbox, sw_idx);
4739 /* Refill RX ring(s). */
4740 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4741 if (work_mask & RXD_OPAQUE_RING_STD) {
4742 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4743 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4744 tpr->rx_std_prod_idx);
4746 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4747 tpr->rx_jmb_prod_idx = jmb_prod_idx %
4748 TG3_RX_JUMBO_RING_SIZE;
4749 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4750 tpr->rx_jmb_prod_idx);
4753 } else if (work_mask) {
4754 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4755 * updated before the producer indices can be updated.
4759 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4760 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
4762 if (tnapi != &tp->napi[1])
4763 napi_schedule(&tp->napi[1].napi);
4769 static void tg3_poll_link(struct tg3 *tp)
4771 /* handle link change and other phy events */
4772 if (!(tp->tg3_flags &
4773 (TG3_FLAG_USE_LINKCHG_REG |
4774 TG3_FLAG_POLL_SERDES))) {
4775 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4777 if (sblk->status & SD_STATUS_LINK_CHG) {
4778 sblk->status = SD_STATUS_UPDATED |
4779 (sblk->status & ~SD_STATUS_LINK_CHG);
4780 spin_lock(&tp->lock);
4781 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4783 (MAC_STATUS_SYNC_CHANGED |
4784 MAC_STATUS_CFG_CHANGED |
4785 MAC_STATUS_MI_COMPLETION |
4786 MAC_STATUS_LNKSTATE_CHANGED));
4789 tg3_setup_phy(tp, 0);
4790 spin_unlock(&tp->lock);
4795 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4796 struct tg3_rx_prodring_set *dpr,
4797 struct tg3_rx_prodring_set *spr)
4799 u32 si, di, cpycnt, src_prod_idx;
4803 src_prod_idx = spr->rx_std_prod_idx;
4805 /* Make sure updates to the rx_std_buffers[] entries and the
4806 * standard producer index are seen in the correct order.
4810 if (spr->rx_std_cons_idx == src_prod_idx)
4813 if (spr->rx_std_cons_idx < src_prod_idx)
4814 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4816 cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4818 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4820 si = spr->rx_std_cons_idx;
4821 di = dpr->rx_std_prod_idx;
4823 for (i = di; i < di + cpycnt; i++) {
4824 if (dpr->rx_std_buffers[i].skb) {
4834 /* Ensure that updates to the rx_std_buffers ring and the
4835 * shadowed hardware producer ring from tg3_recycle_skb() are
4836 * ordered correctly WRT the skb check above.
4840 memcpy(&dpr->rx_std_buffers[di],
4841 &spr->rx_std_buffers[si],
4842 cpycnt * sizeof(struct ring_info));
4844 for (i = 0; i < cpycnt; i++, di++, si++) {
4845 struct tg3_rx_buffer_desc *sbd, *dbd;
4846 sbd = &spr->rx_std[si];
4847 dbd = &dpr->rx_std[di];
4848 dbd->addr_hi = sbd->addr_hi;
4849 dbd->addr_lo = sbd->addr_lo;
4852 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4854 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4859 src_prod_idx = spr->rx_jmb_prod_idx;
4861 /* Make sure updates to the rx_jmb_buffers[] entries and
4862 * the jumbo producer index are seen in the correct order.
4866 if (spr->rx_jmb_cons_idx == src_prod_idx)
4869 if (spr->rx_jmb_cons_idx < src_prod_idx)
4870 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4872 cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4874 cpycnt = min(cpycnt,
4875 TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4877 si = spr->rx_jmb_cons_idx;
4878 di = dpr->rx_jmb_prod_idx;
4880 for (i = di; i < di + cpycnt; i++) {
4881 if (dpr->rx_jmb_buffers[i].skb) {
4891 /* Ensure that updates to the rx_jmb_buffers ring and the
4892 * shadowed hardware producer ring from tg3_recycle_skb() are
4893 * ordered correctly WRT the skb check above.
4897 memcpy(&dpr->rx_jmb_buffers[di],
4898 &spr->rx_jmb_buffers[si],
4899 cpycnt * sizeof(struct ring_info));
4901 for (i = 0; i < cpycnt; i++, di++, si++) {
4902 struct tg3_rx_buffer_desc *sbd, *dbd;
4903 sbd = &spr->rx_jmb[si].std;
4904 dbd = &dpr->rx_jmb[di].std;
4905 dbd->addr_hi = sbd->addr_hi;
4906 dbd->addr_lo = sbd->addr_lo;
4909 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4910 TG3_RX_JUMBO_RING_SIZE;
4911 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4912 TG3_RX_JUMBO_RING_SIZE;
4918 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4920 struct tg3 *tp = tnapi->tp;
4922 /* run TX completion thread */
4923 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4925 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4929 /* run RX thread, within the bounds set by NAPI.
4930 * All RX "locking" is done by ensuring outside
4931 * code synchronizes with tg3->napi.poll()
4933 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4934 work_done += tg3_rx(tnapi, budget - work_done);
4936 if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4937 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
4939 u32 std_prod_idx = dpr->rx_std_prod_idx;
4940 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
4942 for (i = 1; i < tp->irq_cnt; i++)
4943 err |= tg3_rx_prodring_xfer(tp, dpr,
4944 &tp->napi[i].prodring);
4948 if (std_prod_idx != dpr->rx_std_prod_idx)
4949 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4950 dpr->rx_std_prod_idx);
4952 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
4953 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4954 dpr->rx_jmb_prod_idx);
4959 tw32_f(HOSTCC_MODE, tp->coal_now);
4965 static int tg3_poll_msix(struct napi_struct *napi, int budget)
4967 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4968 struct tg3 *tp = tnapi->tp;
4970 struct tg3_hw_status *sblk = tnapi->hw_status;
4973 work_done = tg3_poll_work(tnapi, work_done, budget);
4975 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4978 if (unlikely(work_done >= budget))
4981 /* tp->last_tag is used in tg3_int_reenable() below
4982 * to tell the hw how much work has been processed,
4983 * so we must read it before checking for more work.
4985 tnapi->last_tag = sblk->status_tag;
4986 tnapi->last_irq_tag = tnapi->last_tag;
4989 /* check for RX/TX work to do */
4990 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
4991 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
4992 napi_complete(napi);
4993 /* Reenable interrupts. */
4994 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5003 /* work_done is guaranteed to be less than budget. */
5004 napi_complete(napi);
5005 schedule_work(&tp->reset_task);
5009 static int tg3_poll(struct napi_struct *napi, int budget)
5011 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5012 struct tg3 *tp = tnapi->tp;
5014 struct tg3_hw_status *sblk = tnapi->hw_status;
5019 work_done = tg3_poll_work(tnapi, work_done, budget);
5021 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5024 if (unlikely(work_done >= budget))
5027 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5028 /* tp->last_tag is used in tg3_int_reenable() below
5029 * to tell the hw how much work has been processed,
5030 * so we must read it before checking for more work.
5032 tnapi->last_tag = sblk->status_tag;
5033 tnapi->last_irq_tag = tnapi->last_tag;
5036 sblk->status &= ~SD_STATUS_UPDATED;
5038 if (likely(!tg3_has_work(tnapi))) {
5039 napi_complete(napi);
5040 tg3_int_reenable(tnapi);
5048 /* work_done is guaranteed to be less than budget. */
5049 napi_complete(napi);
5050 schedule_work(&tp->reset_task);
5054 static void tg3_napi_disable(struct tg3 *tp)
5058 for (i = tp->irq_cnt - 1; i >= 0; i--)
5059 napi_disable(&tp->napi[i].napi);
5062 static void tg3_napi_enable(struct tg3 *tp)
5066 for (i = 0; i < tp->irq_cnt; i++)
5067 napi_enable(&tp->napi[i].napi);
5070 static void tg3_napi_init(struct tg3 *tp)
5074 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
5075 for (i = 1; i < tp->irq_cnt; i++)
5076 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
5079 static void tg3_napi_fini(struct tg3 *tp)
5083 for (i = 0; i < tp->irq_cnt; i++)
5084 netif_napi_del(&tp->napi[i].napi);
5087 static inline void tg3_netif_stop(struct tg3 *tp)
5089 tp->dev->trans_start = jiffies; /* prevent tx timeout */
5090 tg3_napi_disable(tp);
5091 netif_tx_disable(tp->dev);
5094 static inline void tg3_netif_start(struct tg3 *tp)
5096 /* NOTE: unconditional netif_tx_wake_all_queues is only
5097 * appropriate so long as all callers are assured to
5098 * have free tx slots (such as after tg3_init_hw)
5100 netif_tx_wake_all_queues(tp->dev);
5102 tg3_napi_enable(tp);
5103 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
5104 tg3_enable_ints(tp);
5107 static void tg3_irq_quiesce(struct tg3 *tp)
5111 BUG_ON(tp->irq_sync);
5116 for (i = 0; i < tp->irq_cnt; i++)
5117 synchronize_irq(tp->napi[i].irq_vec);
5120 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5121 * If irq_sync is non-zero, then the IRQ handler must be synchronized
5122 * with as well. Most of the time, this is not necessary except when
5123 * shutting down the device.
5125 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5127 spin_lock_bh(&tp->lock);
5129 tg3_irq_quiesce(tp);
5132 static inline void tg3_full_unlock(struct tg3 *tp)
5134 spin_unlock_bh(&tp->lock);
5137 /* One-shot MSI handler - Chip automatically disables interrupt
5138 * after sending MSI so driver doesn't have to do it.
5140 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5142 struct tg3_napi *tnapi = dev_id;
5143 struct tg3 *tp = tnapi->tp;
5145 prefetch(tnapi->hw_status);
5147 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5149 if (likely(!tg3_irq_sync(tp)))
5150 napi_schedule(&tnapi->napi);
5155 /* MSI ISR - No need to check for interrupt sharing and no need to
5156 * flush status block and interrupt mailbox. PCI ordering rules
5157 * guarantee that MSI will arrive after the status block.
5159 static irqreturn_t tg3_msi(int irq, void *dev_id)
5161 struct tg3_napi *tnapi = dev_id;
5162 struct tg3 *tp = tnapi->tp;
5164 prefetch(tnapi->hw_status);
5166 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5168 * Writing any value to intr-mbox-0 clears PCI INTA# and
5169 * chip-internal interrupt pending events.
5170 * Writing non-zero to intr-mbox-0 additional tells the
5171 * NIC to stop sending us irqs, engaging "in-intr-handler"
5174 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5175 if (likely(!tg3_irq_sync(tp)))
5176 napi_schedule(&tnapi->napi);
5178 return IRQ_RETVAL(1);
5181 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5183 struct tg3_napi *tnapi = dev_id;
5184 struct tg3 *tp = tnapi->tp;
5185 struct tg3_hw_status *sblk = tnapi->hw_status;
5186 unsigned int handled = 1;
5188 /* In INTx mode, it is possible for the interrupt to arrive at
5189 * the CPU before the status block posted prior to the interrupt.
5190 * Reading the PCI State register will confirm whether the
5191 * interrupt is ours and will flush the status block.
5193 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5194 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5195 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5202 * Writing any value to intr-mbox-0 clears PCI INTA# and
5203 * chip-internal interrupt pending events.
5204 * Writing non-zero to intr-mbox-0 additional tells the
5205 * NIC to stop sending us irqs, engaging "in-intr-handler"
5208 * Flush the mailbox to de-assert the IRQ immediately to prevent
5209 * spurious interrupts. The flush impacts performance but
5210 * excessive spurious interrupts can be worse in some cases.
5212 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5213 if (tg3_irq_sync(tp))
5215 sblk->status &= ~SD_STATUS_UPDATED;
5216 if (likely(tg3_has_work(tnapi))) {
5217 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5218 napi_schedule(&tnapi->napi);
5220 /* No work, shared interrupt perhaps? re-enable
5221 * interrupts, and flush that PCI write
5223 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5227 return IRQ_RETVAL(handled);
5230 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5232 struct tg3_napi *tnapi = dev_id;
5233 struct tg3 *tp = tnapi->tp;
5234 struct tg3_hw_status *sblk = tnapi->hw_status;
5235 unsigned int handled = 1;
5237 /* In INTx mode, it is possible for the interrupt to arrive at
5238 * the CPU before the status block posted prior to the interrupt.
5239 * Reading the PCI State register will confirm whether the
5240 * interrupt is ours and will flush the status block.
5242 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5243 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5244 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5251 * writing any value to intr-mbox-0 clears PCI INTA# and
5252 * chip-internal interrupt pending events.
5253 * writing non-zero to intr-mbox-0 additional tells the
5254 * NIC to stop sending us irqs, engaging "in-intr-handler"
5257 * Flush the mailbox to de-assert the IRQ immediately to prevent
5258 * spurious interrupts. The flush impacts performance but
5259 * excessive spurious interrupts can be worse in some cases.
5261 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5264 * In a shared interrupt configuration, sometimes other devices'
5265 * interrupts will scream. We record the current status tag here
5266 * so that the above check can report that the screaming interrupts
5267 * are unhandled. Eventually they will be silenced.
5269 tnapi->last_irq_tag = sblk->status_tag;
5271 if (tg3_irq_sync(tp))
5274 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5276 napi_schedule(&tnapi->napi);
5279 return IRQ_RETVAL(handled);
5282 /* ISR for interrupt test */
5283 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5285 struct tg3_napi *tnapi = dev_id;
5286 struct tg3 *tp = tnapi->tp;
5287 struct tg3_hw_status *sblk = tnapi->hw_status;
5289 if ((sblk->status & SD_STATUS_UPDATED) ||
5290 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5291 tg3_disable_ints(tp);
5292 return IRQ_RETVAL(1);
5294 return IRQ_RETVAL(0);
5297 static int tg3_init_hw(struct tg3 *, int);
5298 static int tg3_halt(struct tg3 *, int, int);
5300 /* Restart hardware after configuration changes, self-test, etc.
5301 * Invoked with tp->lock held.
5303 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5304 __releases(tp->lock)
5305 __acquires(tp->lock)
5309 err = tg3_init_hw(tp, reset_phy);
5312 "Failed to re-initialize device, aborting\n");
5313 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5314 tg3_full_unlock(tp);
5315 del_timer_sync(&tp->timer);
5317 tg3_napi_enable(tp);
5319 tg3_full_lock(tp, 0);
5324 #ifdef CONFIG_NET_POLL_CONTROLLER
5325 static void tg3_poll_controller(struct net_device *dev)
5328 struct tg3 *tp = netdev_priv(dev);
5330 for (i = 0; i < tp->irq_cnt; i++)
5331 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5335 static void tg3_reset_task(struct work_struct *work)
5337 struct tg3 *tp = container_of(work, struct tg3, reset_task);
5339 unsigned int restart_timer;
5341 tg3_full_lock(tp, 0);
5343 if (!netif_running(tp->dev)) {
5344 tg3_full_unlock(tp);
5348 tg3_full_unlock(tp);
5354 tg3_full_lock(tp, 1);
5356 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5357 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5359 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5360 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5361 tp->write32_rx_mbox = tg3_write_flush_reg32;
5362 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5363 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5366 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5367 err = tg3_init_hw(tp, 1);
5371 tg3_netif_start(tp);
5374 mod_timer(&tp->timer, jiffies + 1);
5377 tg3_full_unlock(tp);
5383 static void tg3_dump_short_state(struct tg3 *tp)
5385 netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5386 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5387 netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5388 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5391 static void tg3_tx_timeout(struct net_device *dev)
5393 struct tg3 *tp = netdev_priv(dev);
5395 if (netif_msg_tx_err(tp)) {
5396 netdev_err(dev, "transmit timed out, resetting\n");
5397 tg3_dump_short_state(tp);
5400 schedule_work(&tp->reset_task);
5403 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5404 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5406 u32 base = (u32) mapping & 0xffffffff;
5408 return (base > 0xffffdcc0) && (base + len + 8 < base);
5411 /* Test for DMA addresses > 40-bit */
5412 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5415 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5416 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5417 return ((u64) mapping + len) > DMA_BIT_MASK(40);
5424 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5426 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5427 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5428 struct sk_buff *skb, u32 last_plus_one,
5429 u32 *start, u32 base_flags, u32 mss)
5431 struct tg3 *tp = tnapi->tp;
5432 struct sk_buff *new_skb;
5433 dma_addr_t new_addr = 0;
5437 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5438 new_skb = skb_copy(skb, GFP_ATOMIC);
5440 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5442 new_skb = skb_copy_expand(skb,
5443 skb_headroom(skb) + more_headroom,
5444 skb_tailroom(skb), GFP_ATOMIC);
5450 /* New SKB is guaranteed to be linear. */
5452 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5454 /* Make sure the mapping succeeded */
5455 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5457 dev_kfree_skb(new_skb);
5460 /* Make sure new skb does not cross any 4G boundaries.
5461 * Drop the packet if it does.
5463 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5464 tg3_4g_overflow_test(new_addr, new_skb->len)) {
5465 pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5468 dev_kfree_skb(new_skb);
5471 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5472 base_flags, 1 | (mss << 1));
5473 *start = NEXT_TX(entry);
5477 /* Now clean up the sw ring entries. */
5479 while (entry != last_plus_one) {
5483 len = skb_headlen(skb);
5485 len = skb_shinfo(skb)->frags[i-1].size;
5487 pci_unmap_single(tp->pdev,
5488 dma_unmap_addr(&tnapi->tx_buffers[entry],
5490 len, PCI_DMA_TODEVICE);
5492 tnapi->tx_buffers[entry].skb = new_skb;
5493 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5496 tnapi->tx_buffers[entry].skb = NULL;
5498 entry = NEXT_TX(entry);
5507 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5508 dma_addr_t mapping, int len, u32 flags,
5511 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5512 int is_end = (mss_and_is_end & 0x1);
5513 u32 mss = (mss_and_is_end >> 1);
5517 flags |= TXD_FLAG_END;
5518 if (flags & TXD_FLAG_VLAN) {
5519 vlan_tag = flags >> 16;
5522 vlan_tag |= (mss << TXD_MSS_SHIFT);
5524 txd->addr_hi = ((u64) mapping >> 32);
5525 txd->addr_lo = ((u64) mapping & 0xffffffff);
5526 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5527 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5530 /* hard_start_xmit for devices that don't have any bugs and
5531 * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5533 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5534 struct net_device *dev)
5536 struct tg3 *tp = netdev_priv(dev);
5537 u32 len, entry, base_flags, mss;
5539 struct tg3_napi *tnapi;
5540 struct netdev_queue *txq;
5541 unsigned int i, last;
5543 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5544 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5545 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5548 /* We are running in BH disabled context with netif_tx_lock
5549 * and TX reclaim runs via tp->napi.poll inside of a software
5550 * interrupt. Furthermore, IRQ processing runs lockless so we have
5551 * no IRQ context deadlocks to worry about either. Rejoice!
5553 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5554 if (!netif_tx_queue_stopped(txq)) {
5555 netif_tx_stop_queue(txq);
5557 /* This is a hard error, log it. */
5559 "BUG! Tx Ring full when queue awake!\n");
5561 return NETDEV_TX_BUSY;
5564 entry = tnapi->tx_prod;
5566 mss = skb_shinfo(skb)->gso_size;
5568 int tcp_opt_len, ip_tcp_len;
5571 if (skb_header_cloned(skb) &&
5572 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5577 if (skb_is_gso_v6(skb)) {
5578 hdrlen = skb_headlen(skb) - ETH_HLEN;
5580 struct iphdr *iph = ip_hdr(skb);
5582 tcp_opt_len = tcp_optlen(skb);
5583 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5586 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5587 hdrlen = ip_tcp_len + tcp_opt_len;
5590 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5591 mss |= (hdrlen & 0xc) << 12;
5593 base_flags |= 0x00000010;
5594 base_flags |= (hdrlen & 0x3e0) << 5;
5598 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5599 TXD_FLAG_CPU_POST_DMA);
5601 tcp_hdr(skb)->check = 0;
5603 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5604 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5607 #if TG3_VLAN_TAG_USED
5608 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5609 base_flags |= (TXD_FLAG_VLAN |
5610 (vlan_tx_tag_get(skb) << 16));
5613 len = skb_headlen(skb);
5615 /* Queue skb data, a.k.a. the main skb fragment. */
5616 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5617 if (pci_dma_mapping_error(tp->pdev, mapping)) {
5622 tnapi->tx_buffers[entry].skb = skb;
5623 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5625 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5626 !mss && skb->len > ETH_DATA_LEN)
5627 base_flags |= TXD_FLAG_JMB_PKT;
5629 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5630 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5632 entry = NEXT_TX(entry);
5634 /* Now loop through additional data fragments, and queue them. */
5635 if (skb_shinfo(skb)->nr_frags > 0) {
5636 last = skb_shinfo(skb)->nr_frags - 1;
5637 for (i = 0; i <= last; i++) {
5638 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5641 mapping = pci_map_page(tp->pdev,
5644 len, PCI_DMA_TODEVICE);
5645 if (pci_dma_mapping_error(tp->pdev, mapping))
5648 tnapi->tx_buffers[entry].skb = NULL;
5649 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5652 tg3_set_txd(tnapi, entry, mapping, len,
5653 base_flags, (i == last) | (mss << 1));
5655 entry = NEXT_TX(entry);
5659 /* Packets are ready, update Tx producer idx local and on card. */
5660 tw32_tx_mbox(tnapi->prodmbox, entry);
5662 tnapi->tx_prod = entry;
5663 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5664 netif_tx_stop_queue(txq);
5666 /* netif_tx_stop_queue() must be done before checking
5667 * checking tx index in tg3_tx_avail() below, because in
5668 * tg3_tx(), we update tx index before checking for
5669 * netif_tx_queue_stopped().
5672 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5673 netif_tx_wake_queue(txq);
5679 return NETDEV_TX_OK;
5683 entry = tnapi->tx_prod;
5684 tnapi->tx_buffers[entry].skb = NULL;
5685 pci_unmap_single(tp->pdev,
5686 dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5689 for (i = 0; i <= last; i++) {
5690 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5691 entry = NEXT_TX(entry);
5693 pci_unmap_page(tp->pdev,
5694 dma_unmap_addr(&tnapi->tx_buffers[entry],
5696 frag->size, PCI_DMA_TODEVICE);
5700 return NETDEV_TX_OK;
5703 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5704 struct net_device *);
5706 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5707 * TSO header is greater than 80 bytes.
5709 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5711 struct sk_buff *segs, *nskb;
5712 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5714 /* Estimate the number of fragments in the worst case */
5715 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5716 netif_stop_queue(tp->dev);
5718 /* netif_tx_stop_queue() must be done before checking
5719 * checking tx index in tg3_tx_avail() below, because in
5720 * tg3_tx(), we update tx index before checking for
5721 * netif_tx_queue_stopped().
5724 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5725 return NETDEV_TX_BUSY;
5727 netif_wake_queue(tp->dev);
5730 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5732 goto tg3_tso_bug_end;
5738 tg3_start_xmit_dma_bug(nskb, tp->dev);
5744 return NETDEV_TX_OK;
5747 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5748 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5750 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5751 struct net_device *dev)
5753 struct tg3 *tp = netdev_priv(dev);
5754 u32 len, entry, base_flags, mss;
5755 int would_hit_hwbug;
5757 struct tg3_napi *tnapi;
5758 struct netdev_queue *txq;
5759 unsigned int i, last;
5761 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5762 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5763 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5766 /* We are running in BH disabled context with netif_tx_lock
5767 * and TX reclaim runs via tp->napi.poll inside of a software
5768 * interrupt. Furthermore, IRQ processing runs lockless so we have
5769 * no IRQ context deadlocks to worry about either. Rejoice!
5771 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5772 if (!netif_tx_queue_stopped(txq)) {
5773 netif_tx_stop_queue(txq);
5775 /* This is a hard error, log it. */
5777 "BUG! Tx Ring full when queue awake!\n");
5779 return NETDEV_TX_BUSY;
5782 entry = tnapi->tx_prod;
5784 if (skb->ip_summed == CHECKSUM_PARTIAL)
5785 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5787 mss = skb_shinfo(skb)->gso_size;
5790 u32 tcp_opt_len, hdr_len;
5792 if (skb_header_cloned(skb) &&
5793 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5799 tcp_opt_len = tcp_optlen(skb);
5801 if (skb_is_gso_v6(skb)) {
5802 hdr_len = skb_headlen(skb) - ETH_HLEN;
5806 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5807 hdr_len = ip_tcp_len + tcp_opt_len;
5810 iph->tot_len = htons(mss + hdr_len);
5813 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5814 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5815 return tg3_tso_bug(tp, skb);
5817 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5818 TXD_FLAG_CPU_POST_DMA);
5820 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5821 tcp_hdr(skb)->check = 0;
5822 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5824 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5829 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5830 mss |= (hdr_len & 0xc) << 12;
5832 base_flags |= 0x00000010;
5833 base_flags |= (hdr_len & 0x3e0) << 5;
5834 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5835 mss |= hdr_len << 9;
5836 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5837 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5838 if (tcp_opt_len || iph->ihl > 5) {
5841 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5842 mss |= (tsflags << 11);
5845 if (tcp_opt_len || iph->ihl > 5) {
5848 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5849 base_flags |= tsflags << 12;
5853 #if TG3_VLAN_TAG_USED
5854 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5855 base_flags |= (TXD_FLAG_VLAN |
5856 (vlan_tx_tag_get(skb) << 16));
5859 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5860 !mss && skb->len > ETH_DATA_LEN)
5861 base_flags |= TXD_FLAG_JMB_PKT;
5863 len = skb_headlen(skb);
5865 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5866 if (pci_dma_mapping_error(tp->pdev, mapping)) {
5871 tnapi->tx_buffers[entry].skb = skb;
5872 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5874 would_hit_hwbug = 0;
5876 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5877 would_hit_hwbug = 1;
5879 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5880 tg3_4g_overflow_test(mapping, len))
5881 would_hit_hwbug = 1;
5883 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5884 tg3_40bit_overflow_test(tp, mapping, len))
5885 would_hit_hwbug = 1;
5887 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5888 would_hit_hwbug = 1;
5890 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5891 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5893 entry = NEXT_TX(entry);
5895 /* Now loop through additional data fragments, and queue them. */
5896 if (skb_shinfo(skb)->nr_frags > 0) {
5897 last = skb_shinfo(skb)->nr_frags - 1;
5898 for (i = 0; i <= last; i++) {
5899 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5902 mapping = pci_map_page(tp->pdev,
5905 len, PCI_DMA_TODEVICE);
5907 tnapi->tx_buffers[entry].skb = NULL;
5908 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5910 if (pci_dma_mapping_error(tp->pdev, mapping))
5913 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5915 would_hit_hwbug = 1;
5917 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5918 tg3_4g_overflow_test(mapping, len))
5919 would_hit_hwbug = 1;
5921 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5922 tg3_40bit_overflow_test(tp, mapping, len))
5923 would_hit_hwbug = 1;
5925 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5926 tg3_set_txd(tnapi, entry, mapping, len,
5927 base_flags, (i == last)|(mss << 1));
5929 tg3_set_txd(tnapi, entry, mapping, len,
5930 base_flags, (i == last));
5932 entry = NEXT_TX(entry);
5936 if (would_hit_hwbug) {
5937 u32 last_plus_one = entry;
5940 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5941 start &= (TG3_TX_RING_SIZE - 1);
5943 /* If the workaround fails due to memory/mapping
5944 * failure, silently drop this packet.
5946 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
5947 &start, base_flags, mss))
5953 /* Packets are ready, update Tx producer idx local and on card. */
5954 tw32_tx_mbox(tnapi->prodmbox, entry);
5956 tnapi->tx_prod = entry;
5957 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5958 netif_tx_stop_queue(txq);
5960 /* netif_tx_stop_queue() must be done before checking
5961 * checking tx index in tg3_tx_avail() below, because in
5962 * tg3_tx(), we update tx index before checking for
5963 * netif_tx_queue_stopped().
5966 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5967 netif_tx_wake_queue(txq);
5973 return NETDEV_TX_OK;
5977 entry = tnapi->tx_prod;
5978 tnapi->tx_buffers[entry].skb = NULL;
5979 pci_unmap_single(tp->pdev,
5980 dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5983 for (i = 0; i <= last; i++) {
5984 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5985 entry = NEXT_TX(entry);
5987 pci_unmap_page(tp->pdev,
5988 dma_unmap_addr(&tnapi->tx_buffers[entry],
5990 frag->size, PCI_DMA_TODEVICE);
5994 return NETDEV_TX_OK;
5997 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
6002 if (new_mtu > ETH_DATA_LEN) {
6003 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6004 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
6005 ethtool_op_set_tso(dev, 0);
6007 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
6010 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6011 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
6012 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
6016 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
6018 struct tg3 *tp = netdev_priv(dev);
6021 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
6024 if (!netif_running(dev)) {
6025 /* We'll just catch it later when the
6028 tg3_set_mtu(dev, tp, new_mtu);
6036 tg3_full_lock(tp, 1);
6038 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6040 tg3_set_mtu(dev, tp, new_mtu);
6042 err = tg3_restart_hw(tp, 0);
6045 tg3_netif_start(tp);
6047 tg3_full_unlock(tp);
6055 static void tg3_rx_prodring_free(struct tg3 *tp,
6056 struct tg3_rx_prodring_set *tpr)
6060 if (tpr != &tp->napi[0].prodring) {
6061 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
6062 i = (i + 1) % TG3_RX_RING_SIZE)
6063 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6066 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6067 for (i = tpr->rx_jmb_cons_idx;
6068 i != tpr->rx_jmb_prod_idx;
6069 i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
6070 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6078 for (i = 0; i < TG3_RX_RING_SIZE; i++)
6079 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6082 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6083 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
6084 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6089 /* Initialize rx rings for packet processing.
6091 * The chip has been shut down and the driver detached from
6092 * the networking, so no interrupts or new tx packets will
6093 * end up in the driver. tp->{tx,}lock are held and thus
6096 static int tg3_rx_prodring_alloc(struct tg3 *tp,
6097 struct tg3_rx_prodring_set *tpr)
6099 u32 i, rx_pkt_dma_sz;
6101 tpr->rx_std_cons_idx = 0;
6102 tpr->rx_std_prod_idx = 0;
6103 tpr->rx_jmb_cons_idx = 0;
6104 tpr->rx_jmb_prod_idx = 0;
6106 if (tpr != &tp->napi[0].prodring) {
6107 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
6108 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
6109 memset(&tpr->rx_jmb_buffers[0], 0,
6110 TG3_RX_JMB_BUFF_RING_SIZE);
6114 /* Zero out all descriptors. */
6115 memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
6117 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6118 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
6119 tp->dev->mtu > ETH_DATA_LEN)
6120 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6121 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6123 /* Initialize invariants of the rings, we only set this
6124 * stuff once. This works because the card does not
6125 * write into the rx buffer posting rings.
6127 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
6128 struct tg3_rx_buffer_desc *rxd;
6130 rxd = &tpr->rx_std[i];
6131 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6132 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6133 rxd->opaque = (RXD_OPAQUE_RING_STD |
6134 (i << RXD_OPAQUE_INDEX_SHIFT));
6137 /* Now allocate fresh SKBs for each rx ring. */
6138 for (i = 0; i < tp->rx_pending; i++) {
6139 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6140 netdev_warn(tp->dev,
6141 "Using a smaller RX standard ring. Only "
6142 "%d out of %d buffers were allocated "
6143 "successfully\n", i, tp->rx_pending);
6151 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6154 memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
6156 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
6159 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
6160 struct tg3_rx_buffer_desc *rxd;
6162 rxd = &tpr->rx_jmb[i].std;
6163 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6164 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6166 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6167 (i << RXD_OPAQUE_INDEX_SHIFT));
6170 for (i = 0; i < tp->rx_jumbo_pending; i++) {
6171 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
6172 netdev_warn(tp->dev,
6173 "Using a smaller RX jumbo ring. Only %d "
6174 "out of %d buffers were allocated "
6175 "successfully\n", i, tp->rx_jumbo_pending);
6178 tp->rx_jumbo_pending = i;
6187 tg3_rx_prodring_free(tp, tpr);
6191 static void tg3_rx_prodring_fini(struct tg3 *tp,
6192 struct tg3_rx_prodring_set *tpr)
6194 kfree(tpr->rx_std_buffers);
6195 tpr->rx_std_buffers = NULL;
6196 kfree(tpr->rx_jmb_buffers);
6197 tpr->rx_jmb_buffers = NULL;
6199 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
6200 tpr->rx_std, tpr->rx_std_mapping);
6204 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
6205 tpr->rx_jmb, tpr->rx_jmb_mapping);
6210 static int tg3_rx_prodring_init(struct tg3 *tp,
6211 struct tg3_rx_prodring_set *tpr)
6213 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
6214 if (!tpr->rx_std_buffers)
6217 tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6218 &tpr->rx_std_mapping);
6222 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6223 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
6225 if (!tpr->rx_jmb_buffers)
6228 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6229 TG3_RX_JUMBO_RING_BYTES,
6230 &tpr->rx_jmb_mapping);
6238 tg3_rx_prodring_fini(tp, tpr);
6242 /* Free up pending packets in all rx/tx rings.
6244 * The chip has been shut down and the driver detached from
6245 * the networking, so no interrupts or new tx packets will
6246 * end up in the driver. tp->{tx,}lock is not held and we are not
6247 * in an interrupt context and thus may sleep.
6249 static void tg3_free_rings(struct tg3 *tp)
6253 for (j = 0; j < tp->irq_cnt; j++) {
6254 struct tg3_napi *tnapi = &tp->napi[j];
6256 tg3_rx_prodring_free(tp, &tnapi->prodring);
6258 if (!tnapi->tx_buffers)
6261 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6262 struct ring_info *txp;
6263 struct sk_buff *skb;
6266 txp = &tnapi->tx_buffers[i];
6274 pci_unmap_single(tp->pdev,
6275 dma_unmap_addr(txp, mapping),
6282 for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6283 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6284 pci_unmap_page(tp->pdev,
6285 dma_unmap_addr(txp, mapping),
6286 skb_shinfo(skb)->frags[k].size,
6291 dev_kfree_skb_any(skb);
6296 /* Initialize tx/rx rings for packet processing.
6298 * The chip has been shut down and the driver detached from
6299 * the networking, so no interrupts or new tx packets will
6300 * end up in the driver. tp->{tx,}lock are held and thus
6303 static int tg3_init_rings(struct tg3 *tp)
6307 /* Free up all the SKBs. */
6310 for (i = 0; i < tp->irq_cnt; i++) {
6311 struct tg3_napi *tnapi = &tp->napi[i];
6313 tnapi->last_tag = 0;
6314 tnapi->last_irq_tag = 0;
6315 tnapi->hw_status->status = 0;
6316 tnapi->hw_status->status_tag = 0;
6317 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6322 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6324 tnapi->rx_rcb_ptr = 0;
6326 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6328 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
6338 * Must not be invoked with interrupt sources disabled and
6339 * the hardware shutdown down.
6341 static void tg3_free_consistent(struct tg3 *tp)
6345 for (i = 0; i < tp->irq_cnt; i++) {
6346 struct tg3_napi *tnapi = &tp->napi[i];
6348 if (tnapi->tx_ring) {
6349 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6350 tnapi->tx_ring, tnapi->tx_desc_mapping);
6351 tnapi->tx_ring = NULL;
6354 kfree(tnapi->tx_buffers);
6355 tnapi->tx_buffers = NULL;
6357 if (tnapi->rx_rcb) {
6358 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6360 tnapi->rx_rcb_mapping);
6361 tnapi->rx_rcb = NULL;
6364 tg3_rx_prodring_fini(tp, &tnapi->prodring);
6366 if (tnapi->hw_status) {
6367 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6369 tnapi->status_mapping);
6370 tnapi->hw_status = NULL;
6375 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6376 tp->hw_stats, tp->stats_mapping);
6377 tp->hw_stats = NULL;
6382 * Must not be invoked with interrupt sources disabled and
6383 * the hardware shutdown down. Can sleep.
6385 static int tg3_alloc_consistent(struct tg3 *tp)
6389 tp->hw_stats = pci_alloc_consistent(tp->pdev,
6390 sizeof(struct tg3_hw_stats),
6391 &tp->stats_mapping);
6395 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6397 for (i = 0; i < tp->irq_cnt; i++) {
6398 struct tg3_napi *tnapi = &tp->napi[i];
6399 struct tg3_hw_status *sblk;
6401 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6403 &tnapi->status_mapping);
6404 if (!tnapi->hw_status)
6407 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6408 sblk = tnapi->hw_status;
6410 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
6413 /* If multivector TSS is enabled, vector 0 does not handle
6414 * tx interrupts. Don't allocate any resources for it.
6416 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6417 (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6418 tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6421 if (!tnapi->tx_buffers)
6424 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6426 &tnapi->tx_desc_mapping);
6427 if (!tnapi->tx_ring)
6432 * When RSS is enabled, the status block format changes
6433 * slightly. The "rx_jumbo_consumer", "reserved",
6434 * and "rx_mini_consumer" members get mapped to the
6435 * other three rx return ring producer indexes.
6439 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6442 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6445 tnapi->rx_rcb_prod_idx = &sblk->reserved;
6448 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6453 * If multivector RSS is enabled, vector 0 does not handle
6454 * rx or tx interrupts. Don't allocate any resources for it.
6456 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6459 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6460 TG3_RX_RCB_RING_BYTES(tp),
6461 &tnapi->rx_rcb_mapping);
6465 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6471 tg3_free_consistent(tp);
6475 #define MAX_WAIT_CNT 1000
6477 /* To stop a block, clear the enable bit and poll till it
6478 * clears. tp->lock is held.
6480 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6485 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6492 /* We can't enable/disable these bits of the
6493 * 5705/5750, just say success.
6506 for (i = 0; i < MAX_WAIT_CNT; i++) {
6509 if ((val & enable_bit) == 0)
6513 if (i == MAX_WAIT_CNT && !silent) {
6514 dev_err(&tp->pdev->dev,
6515 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6523 /* tp->lock is held. */
6524 static int tg3_abort_hw(struct tg3 *tp, int silent)
6528 tg3_disable_ints(tp);
6530 tp->rx_mode &= ~RX_MODE_ENABLE;
6531 tw32_f(MAC_RX_MODE, tp->rx_mode);
6534 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6535 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6536 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6537 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6538 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6539 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6541 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6542 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6543 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6544 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6545 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6546 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6547 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6549 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6550 tw32_f(MAC_MODE, tp->mac_mode);
6553 tp->tx_mode &= ~TX_MODE_ENABLE;
6554 tw32_f(MAC_TX_MODE, tp->tx_mode);
6556 for (i = 0; i < MAX_WAIT_CNT; i++) {
6558 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6561 if (i >= MAX_WAIT_CNT) {
6562 dev_err(&tp->pdev->dev,
6563 "%s timed out, TX_MODE_ENABLE will not clear "
6564 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
6568 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6569 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6570 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6572 tw32(FTQ_RESET, 0xffffffff);
6573 tw32(FTQ_RESET, 0x00000000);
6575 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6576 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6578 for (i = 0; i < tp->irq_cnt; i++) {
6579 struct tg3_napi *tnapi = &tp->napi[i];
6580 if (tnapi->hw_status)
6581 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6584 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6589 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6594 /* NCSI does not support APE events */
6595 if (tp->tg3_flags3 & TG3_FLG3_APE_HAS_NCSI)
6598 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6599 if (apedata != APE_SEG_SIG_MAGIC)
6602 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6603 if (!(apedata & APE_FW_STATUS_READY))
6606 /* Wait for up to 1 millisecond for APE to service previous event. */
6607 for (i = 0; i < 10; i++) {
6608 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6611 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6613 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6614 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6615 event | APE_EVENT_STATUS_EVENT_PENDING);
6617 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6619 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6625 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6626 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6629 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6634 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6638 case RESET_KIND_INIT:
6639 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6640 APE_HOST_SEG_SIG_MAGIC);
6641 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6642 APE_HOST_SEG_LEN_MAGIC);
6643 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6644 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6645 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6646 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
6647 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6648 APE_HOST_BEHAV_NO_PHYLOCK);
6649 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
6650 TG3_APE_HOST_DRVR_STATE_START);
6652 event = APE_EVENT_STATUS_STATE_START;
6654 case RESET_KIND_SHUTDOWN:
6655 /* With the interface we are currently using,
6656 * APE does not track driver state. Wiping
6657 * out the HOST SEGMENT SIGNATURE forces
6658 * the APE to assume OS absent status.
6660 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6662 if (device_may_wakeup(&tp->pdev->dev) &&
6663 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) {
6664 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
6665 TG3_APE_HOST_WOL_SPEED_AUTO);
6666 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
6668 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
6670 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
6672 event = APE_EVENT_STATUS_STATE_UNLOAD;
6674 case RESET_KIND_SUSPEND:
6675 event = APE_EVENT_STATUS_STATE_SUSPEND;
6681 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6683 tg3_ape_send_event(tp, event);
6686 /* tp->lock is held. */
6687 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6689 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6690 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6692 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6694 case RESET_KIND_INIT:
6695 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6699 case RESET_KIND_SHUTDOWN:
6700 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6704 case RESET_KIND_SUSPEND:
6705 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6714 if (kind == RESET_KIND_INIT ||
6715 kind == RESET_KIND_SUSPEND)
6716 tg3_ape_driver_state_change(tp, kind);
6719 /* tp->lock is held. */
6720 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6722 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6724 case RESET_KIND_INIT:
6725 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6726 DRV_STATE_START_DONE);
6729 case RESET_KIND_SHUTDOWN:
6730 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6731 DRV_STATE_UNLOAD_DONE);
6739 if (kind == RESET_KIND_SHUTDOWN)
6740 tg3_ape_driver_state_change(tp, kind);
6743 /* tp->lock is held. */
6744 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6746 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6748 case RESET_KIND_INIT:
6749 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6753 case RESET_KIND_SHUTDOWN:
6754 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6758 case RESET_KIND_SUSPEND:
6759 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6769 static int tg3_poll_fw(struct tg3 *tp)
6774 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6775 /* Wait up to 20ms for init done. */
6776 for (i = 0; i < 200; i++) {
6777 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6784 /* Wait for firmware initialization to complete. */
6785 for (i = 0; i < 100000; i++) {
6786 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6787 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6792 /* Chip might not be fitted with firmware. Some Sun onboard
6793 * parts are configured like that. So don't signal the timeout
6794 * of the above loop as an error, but do report the lack of
6795 * running firmware once.
6798 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6799 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6801 netdev_info(tp->dev, "No firmware running\n");
6804 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6805 /* The 57765 A0 needs a little more
6806 * time to do some important work.
6814 /* Save PCI command register before chip reset */
6815 static void tg3_save_pci_state(struct tg3 *tp)
6817 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6820 /* Restore PCI state after chip reset */
6821 static void tg3_restore_pci_state(struct tg3 *tp)
6825 /* Re-enable indirect register accesses. */
6826 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6827 tp->misc_host_ctrl);
6829 /* Set MAX PCI retry to zero. */
6830 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6831 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6832 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6833 val |= PCISTATE_RETRY_SAME_DMA;
6834 /* Allow reads and writes to the APE register and memory space. */
6835 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6836 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6837 PCISTATE_ALLOW_APE_SHMEM_WR |
6838 PCISTATE_ALLOW_APE_PSPACE_WR;
6839 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6841 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6843 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6844 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6845 pcie_set_readrq(tp->pdev, 4096);
6847 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6848 tp->pci_cacheline_sz);
6849 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6854 /* Make sure PCI-X relaxed ordering bit is clear. */
6855 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6858 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6860 pcix_cmd &= ~PCI_X_CMD_ERO;
6861 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6865 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6867 /* Chip reset on 5780 will reset MSI enable bit,
6868 * so need to restore it.
6870 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6873 pci_read_config_word(tp->pdev,
6874 tp->msi_cap + PCI_MSI_FLAGS,
6876 pci_write_config_word(tp->pdev,
6877 tp->msi_cap + PCI_MSI_FLAGS,
6878 ctrl | PCI_MSI_FLAGS_ENABLE);
6879 val = tr32(MSGINT_MODE);
6880 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6885 static void tg3_stop_fw(struct tg3 *);
6887 /* tp->lock is held. */
6888 static int tg3_chip_reset(struct tg3 *tp)
6891 void (*write_op)(struct tg3 *, u32, u32);
6896 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6898 /* No matching tg3_nvram_unlock() after this because
6899 * chip reset below will undo the nvram lock.
6901 tp->nvram_lock_cnt = 0;
6903 /* GRC_MISC_CFG core clock reset will clear the memory
6904 * enable bit in PCI register 4 and the MSI enable bit
6905 * on some chips, so we save relevant registers here.
6907 tg3_save_pci_state(tp);
6909 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6910 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6911 tw32(GRC_FASTBOOT_PC, 0);
6914 * We must avoid the readl() that normally takes place.
6915 * It locks machines, causes machine checks, and other
6916 * fun things. So, temporarily disable the 5701
6917 * hardware workaround, while we do the reset.
6919 write_op = tp->write32;
6920 if (write_op == tg3_write_flush_reg32)
6921 tp->write32 = tg3_write32;
6923 /* Prevent the irq handler from reading or writing PCI registers
6924 * during chip reset when the memory enable bit in the PCI command
6925 * register may be cleared. The chip does not generate interrupt
6926 * at this time, but the irq handler may still be called due to irq
6927 * sharing or irqpoll.
6929 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6930 for (i = 0; i < tp->irq_cnt; i++) {
6931 struct tg3_napi *tnapi = &tp->napi[i];
6932 if (tnapi->hw_status) {
6933 tnapi->hw_status->status = 0;
6934 tnapi->hw_status->status_tag = 0;
6936 tnapi->last_tag = 0;
6937 tnapi->last_irq_tag = 0;
6941 for (i = 0; i < tp->irq_cnt; i++)
6942 synchronize_irq(tp->napi[i].irq_vec);
6944 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6945 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6946 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6950 val = GRC_MISC_CFG_CORECLK_RESET;
6952 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6953 /* Force PCIe 1.0a mode */
6954 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
6955 !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
6956 tr32(TG3_PCIE_PHY_TSTCTL) ==
6957 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
6958 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
6960 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6961 tw32(GRC_MISC_CFG, (1 << 29));
6966 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6967 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6968 tw32(GRC_VCPU_EXT_CTRL,
6969 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6972 /* Manage gphy power for all CPMU absent PCIe devices. */
6973 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6974 !(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
6975 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6977 tw32(GRC_MISC_CFG, val);
6979 /* restore 5701 hardware bug workaround write method */
6980 tp->write32 = write_op;
6982 /* Unfortunately, we have to delay before the PCI read back.
6983 * Some 575X chips even will not respond to a PCI cfg access
6984 * when the reset command is given to the chip.
6986 * How do these hardware designers expect things to work
6987 * properly if the PCI write is posted for a long period
6988 * of time? It is always necessary to have some method by
6989 * which a register read back can occur to push the write
6990 * out which does the reset.
6992 * For most tg3 variants the trick below was working.
6997 /* Flush PCI posted writes. The normal MMIO registers
6998 * are inaccessible at this time so this is the only
6999 * way to make this reliably (actually, this is no longer
7000 * the case, see above). I tried to use indirect
7001 * register read/write but this upset some 5701 variants.
7003 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
7007 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
7010 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
7014 /* Wait for link training to complete. */
7015 for (i = 0; i < 5000; i++)
7018 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
7019 pci_write_config_dword(tp->pdev, 0xc4,
7020 cfg_val | (1 << 15));
7023 /* Clear the "no snoop" and "relaxed ordering" bits. */
7024 pci_read_config_word(tp->pdev,
7025 tp->pcie_cap + PCI_EXP_DEVCTL,
7027 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
7028 PCI_EXP_DEVCTL_NOSNOOP_EN);
7030 * Older PCIe devices only support the 128 byte
7031 * MPS setting. Enforce the restriction.
7033 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7034 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
7035 pci_write_config_word(tp->pdev,
7036 tp->pcie_cap + PCI_EXP_DEVCTL,
7039 pcie_set_readrq(tp->pdev, 4096);
7041 /* Clear error status */
7042 pci_write_config_word(tp->pdev,
7043 tp->pcie_cap + PCI_EXP_DEVSTA,
7044 PCI_EXP_DEVSTA_CED |
7045 PCI_EXP_DEVSTA_NFED |
7046 PCI_EXP_DEVSTA_FED |
7047 PCI_EXP_DEVSTA_URD);
7050 tg3_restore_pci_state(tp);
7052 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
7055 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
7056 val = tr32(MEMARB_MODE);
7057 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7059 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7061 tw32(0x5000, 0x400);
7064 tw32(GRC_MODE, tp->grc_mode);
7066 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
7069 tw32(0xc4, val | (1 << 15));
7072 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7073 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7074 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7075 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7076 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7077 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7080 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
7081 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
7082 tw32_f(MAC_MODE, tp->mac_mode);
7083 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
7084 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
7085 tw32_f(MAC_MODE, tp->mac_mode);
7086 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7087 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
7088 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
7089 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
7090 tw32_f(MAC_MODE, tp->mac_mode);
7092 tw32_f(MAC_MODE, 0);
7095 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7097 err = tg3_poll_fw(tp);
7103 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
7104 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7105 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7106 !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
7109 tw32(0x7c00, val | (1 << 25));
7112 /* Reprobe ASF enable state. */
7113 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7114 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7115 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7116 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7119 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7120 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7121 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7122 tp->last_event_jiffies = jiffies;
7123 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7124 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7131 /* tp->lock is held. */
7132 static void tg3_stop_fw(struct tg3 *tp)
7134 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7135 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7136 /* Wait for RX cpu to ACK the previous event. */
7137 tg3_wait_for_event_ack(tp);
7139 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7141 tg3_generate_fw_event(tp);
7143 /* Wait for RX cpu to ACK this event. */
7144 tg3_wait_for_event_ack(tp);
7148 /* tp->lock is held. */
7149 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7155 tg3_write_sig_pre_reset(tp, kind);
7157 tg3_abort_hw(tp, silent);
7158 err = tg3_chip_reset(tp);
7160 __tg3_set_mac_addr(tp, 0);
7162 tg3_write_sig_legacy(tp, kind);
7163 tg3_write_sig_post_reset(tp, kind);
7171 #define RX_CPU_SCRATCH_BASE 0x30000
7172 #define RX_CPU_SCRATCH_SIZE 0x04000
7173 #define TX_CPU_SCRATCH_BASE 0x34000
7174 #define TX_CPU_SCRATCH_SIZE 0x04000
7176 /* tp->lock is held. */
7177 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7181 BUG_ON(offset == TX_CPU_BASE &&
7182 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7184 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7185 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7187 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7190 if (offset == RX_CPU_BASE) {
7191 for (i = 0; i < 10000; i++) {
7192 tw32(offset + CPU_STATE, 0xffffffff);
7193 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7194 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7198 tw32(offset + CPU_STATE, 0xffffffff);
7199 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
7202 for (i = 0; i < 10000; i++) {
7203 tw32(offset + CPU_STATE, 0xffffffff);
7204 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7205 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7211 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7212 __func__, offset == RX_CPU_BASE ? "RX" : "TX");
7216 /* Clear firmware's nvram arbitration. */
7217 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7218 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7223 unsigned int fw_base;
7224 unsigned int fw_len;
7225 const __be32 *fw_data;
7228 /* tp->lock is held. */
7229 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7230 int cpu_scratch_size, struct fw_info *info)
7232 int err, lock_err, i;
7233 void (*write_op)(struct tg3 *, u32, u32);
7235 if (cpu_base == TX_CPU_BASE &&
7236 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7238 "%s: Trying to load TX cpu firmware which is 5705\n",
7243 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7244 write_op = tg3_write_mem;
7246 write_op = tg3_write_indirect_reg32;
7248 /* It is possible that bootcode is still loading at this point.
7249 * Get the nvram lock first before halting the cpu.
7251 lock_err = tg3_nvram_lock(tp);
7252 err = tg3_halt_cpu(tp, cpu_base);
7254 tg3_nvram_unlock(tp);
7258 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7259 write_op(tp, cpu_scratch_base + i, 0);
7260 tw32(cpu_base + CPU_STATE, 0xffffffff);
7261 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7262 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7263 write_op(tp, (cpu_scratch_base +
7264 (info->fw_base & 0xffff) +
7266 be32_to_cpu(info->fw_data[i]));
7274 /* tp->lock is held. */
7275 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7277 struct fw_info info;
7278 const __be32 *fw_data;
7281 fw_data = (void *)tp->fw->data;
7283 /* Firmware blob starts with version numbers, followed by
7284 start address and length. We are setting complete length.
7285 length = end_address_of_bss - start_address_of_text.
7286 Remainder is the blob to be loaded contiguously
7287 from start address. */
7289 info.fw_base = be32_to_cpu(fw_data[1]);
7290 info.fw_len = tp->fw->size - 12;
7291 info.fw_data = &fw_data[3];
7293 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7294 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7299 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7300 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7305 /* Now startup only the RX cpu. */
7306 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7307 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7309 for (i = 0; i < 5; i++) {
7310 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7312 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7313 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
7314 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7318 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7319 "should be %08x\n", __func__,
7320 tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
7323 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7324 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
7329 /* 5705 needs a special version of the TSO firmware. */
7331 /* tp->lock is held. */
7332 static int tg3_load_tso_firmware(struct tg3 *tp)
7334 struct fw_info info;
7335 const __be32 *fw_data;
7336 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7339 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7342 fw_data = (void *)tp->fw->data;
7344 /* Firmware blob starts with version numbers, followed by
7345 start address and length. We are setting complete length.
7346 length = end_address_of_bss - start_address_of_text.
7347 Remainder is the blob to be loaded contiguously
7348 from start address. */
7350 info.fw_base = be32_to_cpu(fw_data[1]);
7351 cpu_scratch_size = tp->fw_len;
7352 info.fw_len = tp->fw->size - 12;
7353 info.fw_data = &fw_data[3];
7355 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7356 cpu_base = RX_CPU_BASE;
7357 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7359 cpu_base = TX_CPU_BASE;
7360 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7361 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7364 err = tg3_load_firmware_cpu(tp, cpu_base,
7365 cpu_scratch_base, cpu_scratch_size,
7370 /* Now startup the cpu. */
7371 tw32(cpu_base + CPU_STATE, 0xffffffff);
7372 tw32_f(cpu_base + CPU_PC, info.fw_base);
7374 for (i = 0; i < 5; i++) {
7375 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7377 tw32(cpu_base + CPU_STATE, 0xffffffff);
7378 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
7379 tw32_f(cpu_base + CPU_PC, info.fw_base);
7384 "%s fails to set CPU PC, is %08x should be %08x\n",
7385 __func__, tr32(cpu_base + CPU_PC), info.fw_base);
7388 tw32(cpu_base + CPU_STATE, 0xffffffff);
7389 tw32_f(cpu_base + CPU_MODE, 0x00000000);
7394 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7396 struct tg3 *tp = netdev_priv(dev);
7397 struct sockaddr *addr = p;
7398 int err = 0, skip_mac_1 = 0;
7400 if (!is_valid_ether_addr(addr->sa_data))
7403 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7405 if (!netif_running(dev))
7408 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7409 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7411 addr0_high = tr32(MAC_ADDR_0_HIGH);
7412 addr0_low = tr32(MAC_ADDR_0_LOW);
7413 addr1_high = tr32(MAC_ADDR_1_HIGH);
7414 addr1_low = tr32(MAC_ADDR_1_LOW);
7416 /* Skip MAC addr 1 if ASF is using it. */
7417 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7418 !(addr1_high == 0 && addr1_low == 0))
7421 spin_lock_bh(&tp->lock);
7422 __tg3_set_mac_addr(tp, skip_mac_1);
7423 spin_unlock_bh(&tp->lock);
7428 /* tp->lock is held. */
7429 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7430 dma_addr_t mapping, u32 maxlen_flags,
7434 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7435 ((u64) mapping >> 32));
7437 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7438 ((u64) mapping & 0xffffffff));
7440 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7443 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7445 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7449 static void __tg3_set_rx_mode(struct net_device *);
7450 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7454 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7455 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7456 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7457 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7459 tw32(HOSTCC_TXCOL_TICKS, 0);
7460 tw32(HOSTCC_TXMAX_FRAMES, 0);
7461 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7464 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
7465 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7466 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7467 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7469 tw32(HOSTCC_RXCOL_TICKS, 0);
7470 tw32(HOSTCC_RXMAX_FRAMES, 0);
7471 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7474 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7475 u32 val = ec->stats_block_coalesce_usecs;
7477 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7478 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7480 if (!netif_carrier_ok(tp->dev))
7483 tw32(HOSTCC_STAT_COAL_TICKS, val);
7486 for (i = 0; i < tp->irq_cnt - 1; i++) {
7489 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7490 tw32(reg, ec->rx_coalesce_usecs);
7491 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7492 tw32(reg, ec->rx_max_coalesced_frames);
7493 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7494 tw32(reg, ec->rx_max_coalesced_frames_irq);
7496 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7497 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7498 tw32(reg, ec->tx_coalesce_usecs);
7499 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7500 tw32(reg, ec->tx_max_coalesced_frames);
7501 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7502 tw32(reg, ec->tx_max_coalesced_frames_irq);
7506 for (; i < tp->irq_max - 1; i++) {
7507 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7508 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7509 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7511 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7512 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7513 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7514 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7519 /* tp->lock is held. */
7520 static void tg3_rings_reset(struct tg3 *tp)
7523 u32 stblk, txrcb, rxrcb, limit;
7524 struct tg3_napi *tnapi = &tp->napi[0];
7526 /* Disable all transmit rings but the first. */
7527 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7528 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7529 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7530 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7532 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7534 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7535 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7536 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7537 BDINFO_FLAGS_DISABLED);
7540 /* Disable all receive return rings but the first. */
7541 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7542 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7543 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7544 else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7545 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7546 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7547 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7548 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7550 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7552 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7553 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7554 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7555 BDINFO_FLAGS_DISABLED);
7557 /* Disable interrupts */
7558 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7560 /* Zero mailbox registers. */
7561 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7562 for (i = 1; i < tp->irq_max; i++) {
7563 tp->napi[i].tx_prod = 0;
7564 tp->napi[i].tx_cons = 0;
7565 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7566 tw32_mailbox(tp->napi[i].prodmbox, 0);
7567 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7568 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7570 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7571 tw32_mailbox(tp->napi[0].prodmbox, 0);
7573 tp->napi[0].tx_prod = 0;
7574 tp->napi[0].tx_cons = 0;
7575 tw32_mailbox(tp->napi[0].prodmbox, 0);
7576 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7579 /* Make sure the NIC-based send BD rings are disabled. */
7580 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7581 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7582 for (i = 0; i < 16; i++)
7583 tw32_tx_mbox(mbox + i * 8, 0);
7586 txrcb = NIC_SRAM_SEND_RCB;
7587 rxrcb = NIC_SRAM_RCV_RET_RCB;
7589 /* Clear status block in ram. */
7590 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7592 /* Set status block DMA address */
7593 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7594 ((u64) tnapi->status_mapping >> 32));
7595 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7596 ((u64) tnapi->status_mapping & 0xffffffff));
7598 if (tnapi->tx_ring) {
7599 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7600 (TG3_TX_RING_SIZE <<
7601 BDINFO_FLAGS_MAXLEN_SHIFT),
7602 NIC_SRAM_TX_BUFFER_DESC);
7603 txrcb += TG3_BDINFO_SIZE;
7606 if (tnapi->rx_rcb) {
7607 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7608 (TG3_RX_RCB_RING_SIZE(tp) <<
7609 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7610 rxrcb += TG3_BDINFO_SIZE;
7613 stblk = HOSTCC_STATBLCK_RING1;
7615 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7616 u64 mapping = (u64)tnapi->status_mapping;
7617 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7618 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7620 /* Clear status block in ram. */
7621 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7623 if (tnapi->tx_ring) {
7624 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7625 (TG3_TX_RING_SIZE <<
7626 BDINFO_FLAGS_MAXLEN_SHIFT),
7627 NIC_SRAM_TX_BUFFER_DESC);
7628 txrcb += TG3_BDINFO_SIZE;
7631 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7632 (TG3_RX_RCB_RING_SIZE(tp) <<
7633 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7636 rxrcb += TG3_BDINFO_SIZE;
7640 /* tp->lock is held. */
7641 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7643 u32 val, rdmac_mode;
7645 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
7647 tg3_disable_ints(tp);
7651 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7653 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
7654 tg3_abort_hw(tp, 1);
7659 err = tg3_chip_reset(tp);
7663 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7665 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7666 val = tr32(TG3_CPMU_CTRL);
7667 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7668 tw32(TG3_CPMU_CTRL, val);
7670 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7671 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7672 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7673 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7675 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7676 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7677 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7678 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7680 val = tr32(TG3_CPMU_HST_ACC);
7681 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7682 val |= CPMU_HST_ACC_MACCLK_6_25;
7683 tw32(TG3_CPMU_HST_ACC, val);
7686 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7687 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7688 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7689 PCIE_PWR_MGMT_L1_THRESH_4MS;
7690 tw32(PCIE_PWR_MGMT_THRESH, val);
7692 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7693 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7695 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7697 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7698 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7701 if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7702 u32 grc_mode = tr32(GRC_MODE);
7704 /* Access the lower 1K of PL PCIE block registers. */
7705 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7706 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7708 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7709 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7710 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7712 tw32(GRC_MODE, grc_mode);
7715 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
7716 u32 grc_mode = tr32(GRC_MODE);
7718 /* Access the lower 1K of PL PCIE block registers. */
7719 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7720 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7722 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5);
7723 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
7724 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
7726 tw32(GRC_MODE, grc_mode);
7728 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7729 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7730 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7731 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7734 /* This works around an issue with Athlon chipsets on
7735 * B3 tigon3 silicon. This bit has no effect on any
7736 * other revision. But do not set this on PCI Express
7737 * chips and don't even touch the clocks if the CPMU is present.
7739 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7740 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7741 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7742 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7745 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7746 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7747 val = tr32(TG3PCI_PCISTATE);
7748 val |= PCISTATE_RETRY_SAME_DMA;
7749 tw32(TG3PCI_PCISTATE, val);
7752 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7753 /* Allow reads and writes to the
7754 * APE register and memory space.
7756 val = tr32(TG3PCI_PCISTATE);
7757 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7758 PCISTATE_ALLOW_APE_SHMEM_WR |
7759 PCISTATE_ALLOW_APE_PSPACE_WR;
7760 tw32(TG3PCI_PCISTATE, val);
7763 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7764 /* Enable some hw fixes. */
7765 val = tr32(TG3PCI_MSI_DATA);
7766 val |= (1 << 26) | (1 << 28) | (1 << 29);
7767 tw32(TG3PCI_MSI_DATA, val);
7770 /* Descriptor ring init may make accesses to the
7771 * NIC SRAM area to setup the TX descriptors, so we
7772 * can only do this after the hardware has been
7773 * successfully reset.
7775 err = tg3_init_rings(tp);
7779 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
7780 val = tr32(TG3PCI_DMA_RW_CTRL) &
7781 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7782 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
7783 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
7784 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7785 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7786 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7787 /* This value is determined during the probe time DMA
7788 * engine test, tg3_test_dma.
7790 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7793 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7794 GRC_MODE_4X_NIC_SEND_RINGS |
7795 GRC_MODE_NO_TX_PHDR_CSUM |
7796 GRC_MODE_NO_RX_PHDR_CSUM);
7797 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7799 /* Pseudo-header checksum is done by hardware logic and not
7800 * the offload processers, so make the chip do the pseudo-
7801 * header checksums on receive. For transmit it is more
7802 * convenient to do the pseudo-header checksum in software
7803 * as Linux does that on transmit for us in all cases.
7805 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7809 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7811 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7812 val = tr32(GRC_MISC_CFG);
7814 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7815 tw32(GRC_MISC_CFG, val);
7817 /* Initialize MBUF/DESC pool. */
7818 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7820 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7821 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7822 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7823 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7825 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7826 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7827 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7828 } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7831 fw_len = tp->fw_len;
7832 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7833 tw32(BUFMGR_MB_POOL_ADDR,
7834 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7835 tw32(BUFMGR_MB_POOL_SIZE,
7836 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7839 if (tp->dev->mtu <= ETH_DATA_LEN) {
7840 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7841 tp->bufmgr_config.mbuf_read_dma_low_water);
7842 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7843 tp->bufmgr_config.mbuf_mac_rx_low_water);
7844 tw32(BUFMGR_MB_HIGH_WATER,
7845 tp->bufmgr_config.mbuf_high_water);
7847 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7848 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7849 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7850 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7851 tw32(BUFMGR_MB_HIGH_WATER,
7852 tp->bufmgr_config.mbuf_high_water_jumbo);
7854 tw32(BUFMGR_DMA_LOW_WATER,
7855 tp->bufmgr_config.dma_low_water);
7856 tw32(BUFMGR_DMA_HIGH_WATER,
7857 tp->bufmgr_config.dma_high_water);
7859 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
7860 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7861 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
7862 tw32(BUFMGR_MODE, val);
7863 for (i = 0; i < 2000; i++) {
7864 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7869 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
7873 /* Setup replenish threshold. */
7874 val = tp->rx_pending / 8;
7877 else if (val > tp->rx_std_max_post)
7878 val = tp->rx_std_max_post;
7879 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7880 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7881 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7883 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7884 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7887 tw32(RCVBDI_STD_THRESH, val);
7889 /* Initialize TG3_BDINFO's at:
7890 * RCVDBDI_STD_BD: standard eth size rx ring
7891 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7892 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7895 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7896 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7897 * ring attribute flags
7898 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7900 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7901 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7903 * The size of each ring is fixed in the firmware, but the location is
7906 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7907 ((u64) tpr->rx_std_mapping >> 32));
7908 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7909 ((u64) tpr->rx_std_mapping & 0xffffffff));
7910 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
7911 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
7912 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7913 NIC_SRAM_RX_BUFFER_DESC);
7915 /* Disable the mini ring */
7916 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7917 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7918 BDINFO_FLAGS_DISABLED);
7920 /* Program the jumbo buffer descriptor ring control
7921 * blocks on those devices that have them.
7923 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7924 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7925 /* Setup replenish threshold. */
7926 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7928 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7929 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7930 ((u64) tpr->rx_jmb_mapping >> 32));
7931 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7932 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7933 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7934 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7935 BDINFO_FLAGS_USE_EXT_RECV);
7936 if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) ||
7937 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7938 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7939 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7941 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7942 BDINFO_FLAGS_DISABLED);
7945 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
7946 val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7947 (TG3_RX_STD_DMA_SZ << 2);
7949 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
7951 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7953 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7955 tpr->rx_std_prod_idx = tp->rx_pending;
7956 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
7958 tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7959 tp->rx_jumbo_pending : 0;
7960 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
7962 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
7963 tw32(STD_REPLENISH_LWM, 32);
7964 tw32(JMB_REPLENISH_LWM, 16);
7967 tg3_rings_reset(tp);
7969 /* Initialize MAC address and backoff seed. */
7970 __tg3_set_mac_addr(tp, 0);
7972 /* MTU + ethernet header + FCS + optional VLAN tag */
7973 tw32(MAC_RX_MTU_SIZE,
7974 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7976 /* The slot time is changed by tg3_setup_phy if we
7977 * run at gigabit with half duplex.
7979 tw32(MAC_TX_LENGTHS,
7980 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7981 (6 << TX_LENGTHS_IPG_SHIFT) |
7982 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7984 /* Receive rules. */
7985 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7986 tw32(RCVLPC_CONFIG, 0x0181);
7988 /* Calculate RDMAC_MODE setting early, we need it to determine
7989 * the RCVLPC_STATE_ENABLE mask.
7991 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7992 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7993 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7994 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7995 RDMAC_MODE_LNGREAD_ENAB);
7997 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7998 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7999 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
8001 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8002 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8003 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8004 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
8005 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
8006 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
8008 /* If statement applies to 5705 and 5750 PCI devices only */
8009 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8010 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8011 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
8012 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
8013 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
8014 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
8015 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8016 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
8017 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8021 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
8022 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8024 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8025 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8027 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
8028 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8029 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8030 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
8032 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8033 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8034 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8035 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
8036 (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
8037 val = tr32(TG3_RDMA_RSRVCTRL_REG);
8038 tw32(TG3_RDMA_RSRVCTRL_REG,
8039 val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
8042 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
8043 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
8044 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val |
8045 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
8046 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
8049 /* Receive/send statistics. */
8050 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
8051 val = tr32(RCVLPC_STATS_ENABLE);
8052 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8053 tw32(RCVLPC_STATS_ENABLE, val);
8054 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8055 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8056 val = tr32(RCVLPC_STATS_ENABLE);
8057 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8058 tw32(RCVLPC_STATS_ENABLE, val);
8060 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8062 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8063 tw32(SNDDATAI_STATSENAB, 0xffffff);
8064 tw32(SNDDATAI_STATSCTRL,
8065 (SNDDATAI_SCTRL_ENABLE |
8066 SNDDATAI_SCTRL_FASTUPD));
8068 /* Setup host coalescing engine. */
8069 tw32(HOSTCC_MODE, 0);
8070 for (i = 0; i < 2000; i++) {
8071 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8076 __tg3_set_coalesce(tp, &tp->coal);
8078 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8079 /* Status/statistics block address. See tg3_timer,
8080 * the tg3_periodic_fetch_stats call there, and
8081 * tg3_get_stats to see how this works for 5705/5750 chips.
8083 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8084 ((u64) tp->stats_mapping >> 32));
8085 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8086 ((u64) tp->stats_mapping & 0xffffffff));
8087 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8089 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
8091 /* Clear statistics and status block memory areas */
8092 for (i = NIC_SRAM_STATS_BLK;
8093 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8095 tg3_write_mem(tp, i, 0);
8100 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8102 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8103 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8104 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8105 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8107 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
8108 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
8109 /* reset to prevent losing 1st rx packet intermittently */
8110 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8114 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8115 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8118 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8119 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
8120 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8121 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8122 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8123 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8124 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8127 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8128 * If TG3_FLG2_IS_NIC is zero, we should read the
8129 * register to preserve the GPIO settings for LOMs. The GPIOs,
8130 * whether used as inputs or outputs, are set by boot code after
8133 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
8136 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8137 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8138 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8140 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8141 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8142 GRC_LCLCTRL_GPIO_OUTPUT3;
8144 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8145 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8147 tp->grc_local_ctrl &= ~gpio_mask;
8148 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8150 /* GPIO1 must be driven high for eeprom write protect */
8151 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8152 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8153 GRC_LCLCTRL_GPIO_OUTPUT1);
8155 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8158 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
8159 val = tr32(MSGINT_MODE);
8160 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8161 tw32(MSGINT_MODE, val);
8164 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8165 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8169 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8170 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8171 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8172 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8173 WDMAC_MODE_LNGREAD_ENAB);
8175 /* If statement applies to 5705 and 5750 PCI devices only */
8176 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8177 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8178 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
8179 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8180 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8181 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8183 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8184 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8185 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8186 val |= WDMAC_MODE_RX_ACCEL;
8190 /* Enable host coalescing bug fix */
8191 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8192 val |= WDMAC_MODE_STATUS_TAG_FIX;
8194 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8195 val |= WDMAC_MODE_BURST_ALL_DATA;
8197 tw32_f(WDMAC_MODE, val);
8200 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8203 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8205 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8206 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8207 pcix_cmd |= PCI_X_CMD_READ_2K;
8208 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8209 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8210 pcix_cmd |= PCI_X_CMD_READ_2K;
8212 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8216 tw32_f(RDMAC_MODE, rdmac_mode);
8219 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8220 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8221 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8223 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8225 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8227 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8229 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8230 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8231 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8232 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8233 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8234 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8235 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8236 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8237 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8238 tw32(SNDBDI_MODE, val);
8239 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8241 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8242 err = tg3_load_5701_a0_firmware_fix(tp);
8247 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8248 err = tg3_load_tso_firmware(tp);
8253 tp->tx_mode = TX_MODE_ENABLE;
8254 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
8255 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8256 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
8257 tw32_f(MAC_TX_MODE, tp->tx_mode);
8260 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8261 u32 reg = MAC_RSS_INDIR_TBL_0;
8262 u8 *ent = (u8 *)&val;
8264 /* Setup the indirection table */
8265 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8266 int idx = i % sizeof(val);
8268 ent[idx] = i % (tp->irq_cnt - 1);
8269 if (idx == sizeof(val) - 1) {
8275 /* Setup the "secret" hash key. */
8276 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8277 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8278 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8279 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8280 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8281 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8282 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8283 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8284 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8285 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8288 tp->rx_mode = RX_MODE_ENABLE;
8289 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8290 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8292 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8293 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8294 RX_MODE_RSS_ITBL_HASH_BITS_7 |
8295 RX_MODE_RSS_IPV6_HASH_EN |
8296 RX_MODE_RSS_TCP_IPV6_HASH_EN |
8297 RX_MODE_RSS_IPV4_HASH_EN |
8298 RX_MODE_RSS_TCP_IPV4_HASH_EN;
8300 tw32_f(MAC_RX_MODE, tp->rx_mode);
8303 tw32(MAC_LED_CTRL, tp->led_ctrl);
8305 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8306 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8307 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8310 tw32_f(MAC_RX_MODE, tp->rx_mode);
8313 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8314 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8315 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
8316 /* Set drive transmission level to 1.2V */
8317 /* only if the signal pre-emphasis bit is not set */
8318 val = tr32(MAC_SERDES_CFG);
8321 tw32(MAC_SERDES_CFG, val);
8323 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8324 tw32(MAC_SERDES_CFG, 0x616000);
8327 /* Prevent chip from dropping frames when flow control
8330 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8334 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8336 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8337 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
8338 /* Use hardware link auto-negotiation */
8339 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8342 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8343 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8346 tmp = tr32(SERDES_RX_CTRL);
8347 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8348 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8349 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8350 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8353 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8354 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
8355 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
8356 tp->link_config.speed = tp->link_config.orig_speed;
8357 tp->link_config.duplex = tp->link_config.orig_duplex;
8358 tp->link_config.autoneg = tp->link_config.orig_autoneg;
8361 err = tg3_setup_phy(tp, 0);
8365 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8366 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8369 /* Clear CRC stats. */
8370 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8371 tg3_writephy(tp, MII_TG3_TEST1,
8372 tmp | MII_TG3_TEST1_CRC_EN);
8373 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
8378 __tg3_set_rx_mode(tp->dev);
8380 /* Initialize receive rules. */
8381 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
8382 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8383 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
8384 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8386 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8387 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8391 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8395 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
8397 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
8399 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
8401 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
8403 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
8405 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
8407 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
8409 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
8411 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
8413 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
8415 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
8417 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
8419 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
8421 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
8429 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8430 /* Write our heartbeat update interval to APE. */
8431 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8432 APE_HOST_HEARTBEAT_INT_DISABLE);
8434 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8439 /* Called at device open time to get the chip ready for
8440 * packet processing. Invoked with tp->lock held.
8442 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8444 tg3_switch_clocks(tp);
8446 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8448 return tg3_reset_hw(tp, reset_phy);
8451 #define TG3_STAT_ADD32(PSTAT, REG) \
8452 do { u32 __val = tr32(REG); \
8453 (PSTAT)->low += __val; \
8454 if ((PSTAT)->low < __val) \
8455 (PSTAT)->high += 1; \
8458 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8460 struct tg3_hw_stats *sp = tp->hw_stats;
8462 if (!netif_carrier_ok(tp->dev))
8465 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8466 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8467 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8468 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8469 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8470 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8471 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8472 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8473 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8474 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8475 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8476 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8477 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8479 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8480 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8481 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8482 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8483 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8484 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8485 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8486 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8487 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8488 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8489 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8490 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8491 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8492 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8494 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8495 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8496 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8499 static void tg3_timer(unsigned long __opaque)
8501 struct tg3 *tp = (struct tg3 *) __opaque;
8506 spin_lock(&tp->lock);
8508 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8509 /* All of this garbage is because when using non-tagged
8510 * IRQ status the mailbox/status_block protocol the chip
8511 * uses with the cpu is race prone.
8513 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8514 tw32(GRC_LOCAL_CTRL,
8515 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8517 tw32(HOSTCC_MODE, tp->coalesce_mode |
8518 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8521 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8522 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8523 spin_unlock(&tp->lock);
8524 schedule_work(&tp->reset_task);
8529 /* This part only runs once per second. */
8530 if (!--tp->timer_counter) {
8531 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8532 tg3_periodic_fetch_stats(tp);
8534 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8538 mac_stat = tr32(MAC_STATUS);
8541 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
8542 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8544 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8548 tg3_setup_phy(tp, 0);
8549 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8550 u32 mac_stat = tr32(MAC_STATUS);
8553 if (netif_carrier_ok(tp->dev) &&
8554 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8557 if (!netif_carrier_ok(tp->dev) &&
8558 (mac_stat & (MAC_STATUS_PCS_SYNCED |
8559 MAC_STATUS_SIGNAL_DET))) {
8563 if (!tp->serdes_counter) {
8566 ~MAC_MODE_PORT_MODE_MASK));
8568 tw32_f(MAC_MODE, tp->mac_mode);
8571 tg3_setup_phy(tp, 0);
8573 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8574 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8575 tg3_serdes_parallel_detect(tp);
8578 tp->timer_counter = tp->timer_multiplier;
8581 /* Heartbeat is only sent once every 2 seconds.
8583 * The heartbeat is to tell the ASF firmware that the host
8584 * driver is still alive. In the event that the OS crashes,
8585 * ASF needs to reset the hardware to free up the FIFO space
8586 * that may be filled with rx packets destined for the host.
8587 * If the FIFO is full, ASF will no longer function properly.
8589 * Unintended resets have been reported on real time kernels
8590 * where the timer doesn't run on time. Netpoll will also have
8593 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8594 * to check the ring condition when the heartbeat is expiring
8595 * before doing the reset. This will prevent most unintended
8598 if (!--tp->asf_counter) {
8599 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8600 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8601 tg3_wait_for_event_ack(tp);
8603 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8604 FWCMD_NICDRV_ALIVE3);
8605 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8606 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
8607 TG3_FW_UPDATE_TIMEOUT_SEC);
8609 tg3_generate_fw_event(tp);
8611 tp->asf_counter = tp->asf_multiplier;
8614 spin_unlock(&tp->lock);
8617 tp->timer.expires = jiffies + tp->timer_offset;
8618 add_timer(&tp->timer);
8621 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8624 unsigned long flags;
8626 struct tg3_napi *tnapi = &tp->napi[irq_num];
8628 if (tp->irq_cnt == 1)
8629 name = tp->dev->name;
8631 name = &tnapi->irq_lbl[0];
8632 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8633 name[IFNAMSIZ-1] = 0;
8636 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8638 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8640 flags = IRQF_SAMPLE_RANDOM;
8643 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8644 fn = tg3_interrupt_tagged;
8645 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8648 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8651 static int tg3_test_interrupt(struct tg3 *tp)
8653 struct tg3_napi *tnapi = &tp->napi[0];
8654 struct net_device *dev = tp->dev;
8655 int err, i, intr_ok = 0;
8658 if (!netif_running(dev))
8661 tg3_disable_ints(tp);
8663 free_irq(tnapi->irq_vec, tnapi);
8666 * Turn off MSI one shot mode. Otherwise this test has no
8667 * observable way to know whether the interrupt was delivered.
8669 if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8670 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8671 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8672 tw32(MSGINT_MODE, val);
8675 err = request_irq(tnapi->irq_vec, tg3_test_isr,
8676 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8680 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8681 tg3_enable_ints(tp);
8683 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8686 for (i = 0; i < 5; i++) {
8687 u32 int_mbox, misc_host_ctrl;
8689 int_mbox = tr32_mailbox(tnapi->int_mbox);
8690 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8692 if ((int_mbox != 0) ||
8693 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8701 tg3_disable_ints(tp);
8703 free_irq(tnapi->irq_vec, tnapi);
8705 err = tg3_request_irq(tp, 0);
8711 /* Reenable MSI one shot mode. */
8712 if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8713 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8714 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8715 tw32(MSGINT_MODE, val);
8723 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8724 * successfully restored
8726 static int tg3_test_msi(struct tg3 *tp)
8731 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8734 /* Turn off SERR reporting in case MSI terminates with Master
8737 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8738 pci_write_config_word(tp->pdev, PCI_COMMAND,
8739 pci_cmd & ~PCI_COMMAND_SERR);
8741 err = tg3_test_interrupt(tp);
8743 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8748 /* other failures */
8752 /* MSI test failed, go back to INTx mode */
8753 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
8754 "to INTx mode. Please report this failure to the PCI "
8755 "maintainer and include system chipset information\n");
8757 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8759 pci_disable_msi(tp->pdev);
8761 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8762 tp->napi[0].irq_vec = tp->pdev->irq;
8764 err = tg3_request_irq(tp, 0);
8768 /* Need to reset the chip because the MSI cycle may have terminated
8769 * with Master Abort.
8771 tg3_full_lock(tp, 1);
8773 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8774 err = tg3_init_hw(tp, 1);
8776 tg3_full_unlock(tp);
8779 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8784 static int tg3_request_firmware(struct tg3 *tp)
8786 const __be32 *fw_data;
8788 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8789 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
8794 fw_data = (void *)tp->fw->data;
8796 /* Firmware blob starts with version numbers, followed by
8797 * start address and _full_ length including BSS sections
8798 * (which must be longer than the actual data, of course
8801 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
8802 if (tp->fw_len < (tp->fw->size - 12)) {
8803 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
8804 tp->fw_len, tp->fw_needed);
8805 release_firmware(tp->fw);
8810 /* We no longer need firmware; we have it. */
8811 tp->fw_needed = NULL;
8815 static bool tg3_enable_msix(struct tg3 *tp)
8817 int i, rc, cpus = num_online_cpus();
8818 struct msix_entry msix_ent[tp->irq_max];
8821 /* Just fallback to the simpler MSI mode. */
8825 * We want as many rx rings enabled as there are cpus.
8826 * The first MSIX vector only deals with link interrupts, etc,
8827 * so we add one to the number of vectors we are requesting.
8829 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8831 for (i = 0; i < tp->irq_max; i++) {
8832 msix_ent[i].entry = i;
8833 msix_ent[i].vector = 0;
8836 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8839 } else if (rc != 0) {
8840 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8842 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
8847 for (i = 0; i < tp->irq_max; i++)
8848 tp->napi[i].irq_vec = msix_ent[i].vector;
8850 netif_set_real_num_tx_queues(tp->dev, 1);
8851 rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1;
8852 if (netif_set_real_num_rx_queues(tp->dev, rc)) {
8853 pci_disable_msix(tp->pdev);
8856 if (tp->irq_cnt > 1)
8857 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8862 static void tg3_ints_init(struct tg3 *tp)
8864 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8865 !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8866 /* All MSI supporting chips should support tagged
8867 * status. Assert that this is the case.
8869 netdev_warn(tp->dev,
8870 "MSI without TAGGED_STATUS? Not using MSI\n");
8874 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8875 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8876 else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8877 pci_enable_msi(tp->pdev) == 0)
8878 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8880 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8881 u32 msi_mode = tr32(MSGINT_MODE);
8882 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8883 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8884 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8887 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8889 tp->napi[0].irq_vec = tp->pdev->irq;
8890 netif_set_real_num_tx_queues(tp->dev, 1);
8894 static void tg3_ints_fini(struct tg3 *tp)
8896 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8897 pci_disable_msix(tp->pdev);
8898 else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8899 pci_disable_msi(tp->pdev);
8900 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8901 tp->tg3_flags3 &= ~(TG3_FLG3_ENABLE_RSS | TG3_FLG3_ENABLE_TSS);
8904 static int tg3_open(struct net_device *dev)
8906 struct tg3 *tp = netdev_priv(dev);
8909 if (tp->fw_needed) {
8910 err = tg3_request_firmware(tp);
8911 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8915 netdev_warn(tp->dev, "TSO capability disabled\n");
8916 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8917 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8918 netdev_notice(tp->dev, "TSO capability restored\n");
8919 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8923 netif_carrier_off(tp->dev);
8925 err = tg3_set_power_state(tp, PCI_D0);
8929 tg3_full_lock(tp, 0);
8931 tg3_disable_ints(tp);
8932 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8934 tg3_full_unlock(tp);
8937 * Setup interrupts first so we know how
8938 * many NAPI resources to allocate
8942 /* The placement of this call is tied
8943 * to the setup and use of Host TX descriptors.
8945 err = tg3_alloc_consistent(tp);
8951 tg3_napi_enable(tp);
8953 for (i = 0; i < tp->irq_cnt; i++) {
8954 struct tg3_napi *tnapi = &tp->napi[i];
8955 err = tg3_request_irq(tp, i);
8957 for (i--; i >= 0; i--)
8958 free_irq(tnapi->irq_vec, tnapi);
8966 tg3_full_lock(tp, 0);
8968 err = tg3_init_hw(tp, 1);
8970 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8973 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8974 tp->timer_offset = HZ;
8976 tp->timer_offset = HZ / 10;
8978 BUG_ON(tp->timer_offset > HZ);
8979 tp->timer_counter = tp->timer_multiplier =
8980 (HZ / tp->timer_offset);
8981 tp->asf_counter = tp->asf_multiplier =
8982 ((HZ / tp->timer_offset) * 2);
8984 init_timer(&tp->timer);
8985 tp->timer.expires = jiffies + tp->timer_offset;
8986 tp->timer.data = (unsigned long) tp;
8987 tp->timer.function = tg3_timer;
8990 tg3_full_unlock(tp);
8995 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8996 err = tg3_test_msi(tp);
8999 tg3_full_lock(tp, 0);
9000 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9002 tg3_full_unlock(tp);
9007 if (!(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
9008 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
9009 u32 val = tr32(PCIE_TRANSACTION_CFG);
9011 tw32(PCIE_TRANSACTION_CFG,
9012 val | PCIE_TRANS_CFG_1SHOT_MSI);
9018 tg3_full_lock(tp, 0);
9020 add_timer(&tp->timer);
9021 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9022 tg3_enable_ints(tp);
9024 tg3_full_unlock(tp);
9026 netif_tx_start_all_queues(dev);
9031 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9032 struct tg3_napi *tnapi = &tp->napi[i];
9033 free_irq(tnapi->irq_vec, tnapi);
9037 tg3_napi_disable(tp);
9039 tg3_free_consistent(tp);
9046 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
9047 struct rtnl_link_stats64 *);
9048 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9050 static int tg3_close(struct net_device *dev)
9053 struct tg3 *tp = netdev_priv(dev);
9055 tg3_napi_disable(tp);
9056 cancel_work_sync(&tp->reset_task);
9058 netif_tx_stop_all_queues(dev);
9060 del_timer_sync(&tp->timer);
9064 tg3_full_lock(tp, 1);
9066 tg3_disable_ints(tp);
9068 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9070 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9072 tg3_full_unlock(tp);
9074 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9075 struct tg3_napi *tnapi = &tp->napi[i];
9076 free_irq(tnapi->irq_vec, tnapi);
9081 tg3_get_stats64(tp->dev, &tp->net_stats_prev);
9083 memcpy(&tp->estats_prev, tg3_get_estats(tp),
9084 sizeof(tp->estats_prev));
9088 tg3_free_consistent(tp);
9090 tg3_set_power_state(tp, PCI_D3hot);
9092 netif_carrier_off(tp->dev);
9097 static inline u64 get_stat64(tg3_stat64_t *val)
9099 return ((u64)val->high << 32) | ((u64)val->low);
9102 static u64 calc_crc_errors(struct tg3 *tp)
9104 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9106 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9107 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9108 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9111 spin_lock_bh(&tp->lock);
9112 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9113 tg3_writephy(tp, MII_TG3_TEST1,
9114 val | MII_TG3_TEST1_CRC_EN);
9115 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
9118 spin_unlock_bh(&tp->lock);
9120 tp->phy_crc_errors += val;
9122 return tp->phy_crc_errors;
9125 return get_stat64(&hw_stats->rx_fcs_errors);
9128 #define ESTAT_ADD(member) \
9129 estats->member = old_estats->member + \
9130 get_stat64(&hw_stats->member)
9132 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9134 struct tg3_ethtool_stats *estats = &tp->estats;
9135 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9136 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9141 ESTAT_ADD(rx_octets);
9142 ESTAT_ADD(rx_fragments);
9143 ESTAT_ADD(rx_ucast_packets);
9144 ESTAT_ADD(rx_mcast_packets);
9145 ESTAT_ADD(rx_bcast_packets);
9146 ESTAT_ADD(rx_fcs_errors);
9147 ESTAT_ADD(rx_align_errors);
9148 ESTAT_ADD(rx_xon_pause_rcvd);
9149 ESTAT_ADD(rx_xoff_pause_rcvd);
9150 ESTAT_ADD(rx_mac_ctrl_rcvd);
9151 ESTAT_ADD(rx_xoff_entered);
9152 ESTAT_ADD(rx_frame_too_long_errors);
9153 ESTAT_ADD(rx_jabbers);
9154 ESTAT_ADD(rx_undersize_packets);
9155 ESTAT_ADD(rx_in_length_errors);
9156 ESTAT_ADD(rx_out_length_errors);
9157 ESTAT_ADD(rx_64_or_less_octet_packets);
9158 ESTAT_ADD(rx_65_to_127_octet_packets);
9159 ESTAT_ADD(rx_128_to_255_octet_packets);
9160 ESTAT_ADD(rx_256_to_511_octet_packets);
9161 ESTAT_ADD(rx_512_to_1023_octet_packets);
9162 ESTAT_ADD(rx_1024_to_1522_octet_packets);
9163 ESTAT_ADD(rx_1523_to_2047_octet_packets);
9164 ESTAT_ADD(rx_2048_to_4095_octet_packets);
9165 ESTAT_ADD(rx_4096_to_8191_octet_packets);
9166 ESTAT_ADD(rx_8192_to_9022_octet_packets);
9168 ESTAT_ADD(tx_octets);
9169 ESTAT_ADD(tx_collisions);
9170 ESTAT_ADD(tx_xon_sent);
9171 ESTAT_ADD(tx_xoff_sent);
9172 ESTAT_ADD(tx_flow_control);
9173 ESTAT_ADD(tx_mac_errors);
9174 ESTAT_ADD(tx_single_collisions);
9175 ESTAT_ADD(tx_mult_collisions);
9176 ESTAT_ADD(tx_deferred);
9177 ESTAT_ADD(tx_excessive_collisions);
9178 ESTAT_ADD(tx_late_collisions);
9179 ESTAT_ADD(tx_collide_2times);
9180 ESTAT_ADD(tx_collide_3times);
9181 ESTAT_ADD(tx_collide_4times);
9182 ESTAT_ADD(tx_collide_5times);
9183 ESTAT_ADD(tx_collide_6times);
9184 ESTAT_ADD(tx_collide_7times);
9185 ESTAT_ADD(tx_collide_8times);
9186 ESTAT_ADD(tx_collide_9times);
9187 ESTAT_ADD(tx_collide_10times);
9188 ESTAT_ADD(tx_collide_11times);
9189 ESTAT_ADD(tx_collide_12times);
9190 ESTAT_ADD(tx_collide_13times);
9191 ESTAT_ADD(tx_collide_14times);
9192 ESTAT_ADD(tx_collide_15times);
9193 ESTAT_ADD(tx_ucast_packets);
9194 ESTAT_ADD(tx_mcast_packets);
9195 ESTAT_ADD(tx_bcast_packets);
9196 ESTAT_ADD(tx_carrier_sense_errors);
9197 ESTAT_ADD(tx_discards);
9198 ESTAT_ADD(tx_errors);
9200 ESTAT_ADD(dma_writeq_full);
9201 ESTAT_ADD(dma_write_prioq_full);
9202 ESTAT_ADD(rxbds_empty);
9203 ESTAT_ADD(rx_discards);
9204 ESTAT_ADD(rx_errors);
9205 ESTAT_ADD(rx_threshold_hit);
9207 ESTAT_ADD(dma_readq_full);
9208 ESTAT_ADD(dma_read_prioq_full);
9209 ESTAT_ADD(tx_comp_queue_full);
9211 ESTAT_ADD(ring_set_send_prod_index);
9212 ESTAT_ADD(ring_status_update);
9213 ESTAT_ADD(nic_irqs);
9214 ESTAT_ADD(nic_avoided_irqs);
9215 ESTAT_ADD(nic_tx_threshold_hit);
9220 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
9221 struct rtnl_link_stats64 *stats)
9223 struct tg3 *tp = netdev_priv(dev);
9224 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
9225 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9230 stats->rx_packets = old_stats->rx_packets +
9231 get_stat64(&hw_stats->rx_ucast_packets) +
9232 get_stat64(&hw_stats->rx_mcast_packets) +
9233 get_stat64(&hw_stats->rx_bcast_packets);
9235 stats->tx_packets = old_stats->tx_packets +
9236 get_stat64(&hw_stats->tx_ucast_packets) +
9237 get_stat64(&hw_stats->tx_mcast_packets) +
9238 get_stat64(&hw_stats->tx_bcast_packets);
9240 stats->rx_bytes = old_stats->rx_bytes +
9241 get_stat64(&hw_stats->rx_octets);
9242 stats->tx_bytes = old_stats->tx_bytes +
9243 get_stat64(&hw_stats->tx_octets);
9245 stats->rx_errors = old_stats->rx_errors +
9246 get_stat64(&hw_stats->rx_errors);
9247 stats->tx_errors = old_stats->tx_errors +
9248 get_stat64(&hw_stats->tx_errors) +
9249 get_stat64(&hw_stats->tx_mac_errors) +
9250 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9251 get_stat64(&hw_stats->tx_discards);
9253 stats->multicast = old_stats->multicast +
9254 get_stat64(&hw_stats->rx_mcast_packets);
9255 stats->collisions = old_stats->collisions +
9256 get_stat64(&hw_stats->tx_collisions);
9258 stats->rx_length_errors = old_stats->rx_length_errors +
9259 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9260 get_stat64(&hw_stats->rx_undersize_packets);
9262 stats->rx_over_errors = old_stats->rx_over_errors +
9263 get_stat64(&hw_stats->rxbds_empty);
9264 stats->rx_frame_errors = old_stats->rx_frame_errors +
9265 get_stat64(&hw_stats->rx_align_errors);
9266 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9267 get_stat64(&hw_stats->tx_discards);
9268 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9269 get_stat64(&hw_stats->tx_carrier_sense_errors);
9271 stats->rx_crc_errors = old_stats->rx_crc_errors +
9272 calc_crc_errors(tp);
9274 stats->rx_missed_errors = old_stats->rx_missed_errors +
9275 get_stat64(&hw_stats->rx_discards);
9280 static inline u32 calc_crc(unsigned char *buf, int len)
9288 for (j = 0; j < len; j++) {
9291 for (k = 0; k < 8; k++) {
9304 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9306 /* accept or reject all multicast frames */
9307 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9308 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9309 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9310 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9313 static void __tg3_set_rx_mode(struct net_device *dev)
9315 struct tg3 *tp = netdev_priv(dev);
9318 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9319 RX_MODE_KEEP_VLAN_TAG);
9321 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9324 #if TG3_VLAN_TAG_USED
9326 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9327 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9329 /* By definition, VLAN is disabled always in this
9332 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9333 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9336 if (dev->flags & IFF_PROMISC) {
9337 /* Promiscuous mode. */
9338 rx_mode |= RX_MODE_PROMISC;
9339 } else if (dev->flags & IFF_ALLMULTI) {
9340 /* Accept all multicast. */
9341 tg3_set_multi(tp, 1);
9342 } else if (netdev_mc_empty(dev)) {
9343 /* Reject all multicast. */
9344 tg3_set_multi(tp, 0);
9346 /* Accept one or more multicast(s). */
9347 struct netdev_hw_addr *ha;
9348 u32 mc_filter[4] = { 0, };
9353 netdev_for_each_mc_addr(ha, dev) {
9354 crc = calc_crc(ha->addr, ETH_ALEN);
9356 regidx = (bit & 0x60) >> 5;
9358 mc_filter[regidx] |= (1 << bit);
9361 tw32(MAC_HASH_REG_0, mc_filter[0]);
9362 tw32(MAC_HASH_REG_1, mc_filter[1]);
9363 tw32(MAC_HASH_REG_2, mc_filter[2]);
9364 tw32(MAC_HASH_REG_3, mc_filter[3]);
9367 if (rx_mode != tp->rx_mode) {
9368 tp->rx_mode = rx_mode;
9369 tw32_f(MAC_RX_MODE, rx_mode);
9374 static void tg3_set_rx_mode(struct net_device *dev)
9376 struct tg3 *tp = netdev_priv(dev);
9378 if (!netif_running(dev))
9381 tg3_full_lock(tp, 0);
9382 __tg3_set_rx_mode(dev);
9383 tg3_full_unlock(tp);
9386 #define TG3_REGDUMP_LEN (32 * 1024)
9388 static int tg3_get_regs_len(struct net_device *dev)
9390 return TG3_REGDUMP_LEN;
9393 static void tg3_get_regs(struct net_device *dev,
9394 struct ethtool_regs *regs, void *_p)
9397 struct tg3 *tp = netdev_priv(dev);
9403 memset(p, 0, TG3_REGDUMP_LEN);
9405 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9408 tg3_full_lock(tp, 0);
9410 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
9411 #define GET_REG32_LOOP(base, len) \
9412 do { p = (u32 *)(orig_p + (base)); \
9413 for (i = 0; i < len; i += 4) \
9414 __GET_REG32((base) + i); \
9416 #define GET_REG32_1(reg) \
9417 do { p = (u32 *)(orig_p + (reg)); \
9418 __GET_REG32((reg)); \
9421 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9422 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9423 GET_REG32_LOOP(MAC_MODE, 0x4f0);
9424 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9425 GET_REG32_1(SNDDATAC_MODE);
9426 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9427 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9428 GET_REG32_1(SNDBDC_MODE);
9429 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9430 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9431 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9432 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9433 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9434 GET_REG32_1(RCVDCC_MODE);
9435 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9436 GET_REG32_LOOP(RCVCC_MODE, 0x14);
9437 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9438 GET_REG32_1(MBFREE_MODE);
9439 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9440 GET_REG32_LOOP(MEMARB_MODE, 0x10);
9441 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9442 GET_REG32_LOOP(RDMAC_MODE, 0x08);
9443 GET_REG32_LOOP(WDMAC_MODE, 0x08);
9444 GET_REG32_1(RX_CPU_MODE);
9445 GET_REG32_1(RX_CPU_STATE);
9446 GET_REG32_1(RX_CPU_PGMCTR);
9447 GET_REG32_1(RX_CPU_HWBKPT);
9448 GET_REG32_1(TX_CPU_MODE);
9449 GET_REG32_1(TX_CPU_STATE);
9450 GET_REG32_1(TX_CPU_PGMCTR);
9451 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9452 GET_REG32_LOOP(FTQ_RESET, 0x120);
9453 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9454 GET_REG32_1(DMAC_MODE);
9455 GET_REG32_LOOP(GRC_MODE, 0x4c);
9456 if (tp->tg3_flags & TG3_FLAG_NVRAM)
9457 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9460 #undef GET_REG32_LOOP
9463 tg3_full_unlock(tp);
9466 static int tg3_get_eeprom_len(struct net_device *dev)
9468 struct tg3 *tp = netdev_priv(dev);
9470 return tp->nvram_size;
9473 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9475 struct tg3 *tp = netdev_priv(dev);
9478 u32 i, offset, len, b_offset, b_count;
9481 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9484 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9487 offset = eeprom->offset;
9491 eeprom->magic = TG3_EEPROM_MAGIC;
9494 /* adjustments to start on required 4 byte boundary */
9495 b_offset = offset & 3;
9496 b_count = 4 - b_offset;
9497 if (b_count > len) {
9498 /* i.e. offset=1 len=2 */
9501 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9504 memcpy(data, ((char *)&val) + b_offset, b_count);
9507 eeprom->len += b_count;
9510 /* read bytes upto the last 4 byte boundary */
9511 pd = &data[eeprom->len];
9512 for (i = 0; i < (len - (len & 3)); i += 4) {
9513 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9518 memcpy(pd + i, &val, 4);
9523 /* read last bytes not ending on 4 byte boundary */
9524 pd = &data[eeprom->len];
9526 b_offset = offset + len - b_count;
9527 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9530 memcpy(pd, &val, b_count);
9531 eeprom->len += b_count;
9536 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9538 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9540 struct tg3 *tp = netdev_priv(dev);
9542 u32 offset, len, b_offset, odd_len;
9546 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9549 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9550 eeprom->magic != TG3_EEPROM_MAGIC)
9553 offset = eeprom->offset;
9556 if ((b_offset = (offset & 3))) {
9557 /* adjustments to start on required 4 byte boundary */
9558 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9569 /* adjustments to end on required 4 byte boundary */
9571 len = (len + 3) & ~3;
9572 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9578 if (b_offset || odd_len) {
9579 buf = kmalloc(len, GFP_KERNEL);
9583 memcpy(buf, &start, 4);
9585 memcpy(buf+len-4, &end, 4);
9586 memcpy(buf + b_offset, data, eeprom->len);
9589 ret = tg3_nvram_write_block(tp, offset, len, buf);
9597 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9599 struct tg3 *tp = netdev_priv(dev);
9601 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9602 struct phy_device *phydev;
9603 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9605 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9606 return phy_ethtool_gset(phydev, cmd);
9609 cmd->supported = (SUPPORTED_Autoneg);
9611 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9612 cmd->supported |= (SUPPORTED_1000baseT_Half |
9613 SUPPORTED_1000baseT_Full);
9615 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
9616 cmd->supported |= (SUPPORTED_100baseT_Half |
9617 SUPPORTED_100baseT_Full |
9618 SUPPORTED_10baseT_Half |
9619 SUPPORTED_10baseT_Full |
9621 cmd->port = PORT_TP;
9623 cmd->supported |= SUPPORTED_FIBRE;
9624 cmd->port = PORT_FIBRE;
9627 cmd->advertising = tp->link_config.advertising;
9628 if (netif_running(dev)) {
9629 cmd->speed = tp->link_config.active_speed;
9630 cmd->duplex = tp->link_config.active_duplex;
9632 cmd->phy_address = tp->phy_addr;
9633 cmd->transceiver = XCVR_INTERNAL;
9634 cmd->autoneg = tp->link_config.autoneg;
9640 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9642 struct tg3 *tp = netdev_priv(dev);
9644 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9645 struct phy_device *phydev;
9646 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9648 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9649 return phy_ethtool_sset(phydev, cmd);
9652 if (cmd->autoneg != AUTONEG_ENABLE &&
9653 cmd->autoneg != AUTONEG_DISABLE)
9656 if (cmd->autoneg == AUTONEG_DISABLE &&
9657 cmd->duplex != DUPLEX_FULL &&
9658 cmd->duplex != DUPLEX_HALF)
9661 if (cmd->autoneg == AUTONEG_ENABLE) {
9662 u32 mask = ADVERTISED_Autoneg |
9664 ADVERTISED_Asym_Pause;
9666 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9667 mask |= ADVERTISED_1000baseT_Half |
9668 ADVERTISED_1000baseT_Full;
9670 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
9671 mask |= ADVERTISED_100baseT_Half |
9672 ADVERTISED_100baseT_Full |
9673 ADVERTISED_10baseT_Half |
9674 ADVERTISED_10baseT_Full |
9677 mask |= ADVERTISED_FIBRE;
9679 if (cmd->advertising & ~mask)
9682 mask &= (ADVERTISED_1000baseT_Half |
9683 ADVERTISED_1000baseT_Full |
9684 ADVERTISED_100baseT_Half |
9685 ADVERTISED_100baseT_Full |
9686 ADVERTISED_10baseT_Half |
9687 ADVERTISED_10baseT_Full);
9689 cmd->advertising &= mask;
9691 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
9692 if (cmd->speed != SPEED_1000)
9695 if (cmd->duplex != DUPLEX_FULL)
9698 if (cmd->speed != SPEED_100 &&
9699 cmd->speed != SPEED_10)
9704 tg3_full_lock(tp, 0);
9706 tp->link_config.autoneg = cmd->autoneg;
9707 if (cmd->autoneg == AUTONEG_ENABLE) {
9708 tp->link_config.advertising = (cmd->advertising |
9709 ADVERTISED_Autoneg);
9710 tp->link_config.speed = SPEED_INVALID;
9711 tp->link_config.duplex = DUPLEX_INVALID;
9713 tp->link_config.advertising = 0;
9714 tp->link_config.speed = cmd->speed;
9715 tp->link_config.duplex = cmd->duplex;
9718 tp->link_config.orig_speed = tp->link_config.speed;
9719 tp->link_config.orig_duplex = tp->link_config.duplex;
9720 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9722 if (netif_running(dev))
9723 tg3_setup_phy(tp, 1);
9725 tg3_full_unlock(tp);
9730 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9732 struct tg3 *tp = netdev_priv(dev);
9734 strcpy(info->driver, DRV_MODULE_NAME);
9735 strcpy(info->version, DRV_MODULE_VERSION);
9736 strcpy(info->fw_version, tp->fw_ver);
9737 strcpy(info->bus_info, pci_name(tp->pdev));
9740 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9742 struct tg3 *tp = netdev_priv(dev);
9744 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9745 device_can_wakeup(&tp->pdev->dev))
9746 wol->supported = WAKE_MAGIC;
9750 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9751 device_can_wakeup(&tp->pdev->dev))
9752 wol->wolopts = WAKE_MAGIC;
9753 memset(&wol->sopass, 0, sizeof(wol->sopass));
9756 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9758 struct tg3 *tp = netdev_priv(dev);
9759 struct device *dp = &tp->pdev->dev;
9761 if (wol->wolopts & ~WAKE_MAGIC)
9763 if ((wol->wolopts & WAKE_MAGIC) &&
9764 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9767 spin_lock_bh(&tp->lock);
9768 if (wol->wolopts & WAKE_MAGIC) {
9769 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9770 device_set_wakeup_enable(dp, true);
9772 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9773 device_set_wakeup_enable(dp, false);
9775 spin_unlock_bh(&tp->lock);
9780 static u32 tg3_get_msglevel(struct net_device *dev)
9782 struct tg3 *tp = netdev_priv(dev);
9783 return tp->msg_enable;
9786 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9788 struct tg3 *tp = netdev_priv(dev);
9789 tp->msg_enable = value;
9792 static int tg3_set_tso(struct net_device *dev, u32 value)
9794 struct tg3 *tp = netdev_priv(dev);
9796 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9801 if ((dev->features & NETIF_F_IPV6_CSUM) &&
9802 ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9803 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9805 dev->features |= NETIF_F_TSO6;
9806 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9807 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9808 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9809 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9810 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9811 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9812 dev->features |= NETIF_F_TSO_ECN;
9814 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9816 return ethtool_op_set_tso(dev, value);
9819 static int tg3_nway_reset(struct net_device *dev)
9821 struct tg3 *tp = netdev_priv(dev);
9824 if (!netif_running(dev))
9827 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
9830 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9831 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9833 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9837 spin_lock_bh(&tp->lock);
9839 tg3_readphy(tp, MII_BMCR, &bmcr);
9840 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9841 ((bmcr & BMCR_ANENABLE) ||
9842 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
9843 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9847 spin_unlock_bh(&tp->lock);
9853 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9855 struct tg3 *tp = netdev_priv(dev);
9857 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9858 ering->rx_mini_max_pending = 0;
9859 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9860 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9862 ering->rx_jumbo_max_pending = 0;
9864 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9866 ering->rx_pending = tp->rx_pending;
9867 ering->rx_mini_pending = 0;
9868 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9869 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9871 ering->rx_jumbo_pending = 0;
9873 ering->tx_pending = tp->napi[0].tx_pending;
9876 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9878 struct tg3 *tp = netdev_priv(dev);
9879 int i, irq_sync = 0, err = 0;
9881 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9882 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9883 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9884 (ering->tx_pending <= MAX_SKB_FRAGS) ||
9885 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9886 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9889 if (netif_running(dev)) {
9895 tg3_full_lock(tp, irq_sync);
9897 tp->rx_pending = ering->rx_pending;
9899 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9900 tp->rx_pending > 63)
9901 tp->rx_pending = 63;
9902 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9904 for (i = 0; i < tp->irq_max; i++)
9905 tp->napi[i].tx_pending = ering->tx_pending;
9907 if (netif_running(dev)) {
9908 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9909 err = tg3_restart_hw(tp, 1);
9911 tg3_netif_start(tp);
9914 tg3_full_unlock(tp);
9916 if (irq_sync && !err)
9922 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9924 struct tg3 *tp = netdev_priv(dev);
9926 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9928 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9929 epause->rx_pause = 1;
9931 epause->rx_pause = 0;
9933 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9934 epause->tx_pause = 1;
9936 epause->tx_pause = 0;
9939 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9941 struct tg3 *tp = netdev_priv(dev);
9944 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9946 struct phy_device *phydev;
9948 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9950 if (!(phydev->supported & SUPPORTED_Pause) ||
9951 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
9952 ((epause->rx_pause && !epause->tx_pause) ||
9953 (!epause->rx_pause && epause->tx_pause))))
9956 tp->link_config.flowctrl = 0;
9957 if (epause->rx_pause) {
9958 tp->link_config.flowctrl |= FLOW_CTRL_RX;
9960 if (epause->tx_pause) {
9961 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9962 newadv = ADVERTISED_Pause;
9964 newadv = ADVERTISED_Pause |
9965 ADVERTISED_Asym_Pause;
9966 } else if (epause->tx_pause) {
9967 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9968 newadv = ADVERTISED_Asym_Pause;
9972 if (epause->autoneg)
9973 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9975 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9977 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
9978 u32 oldadv = phydev->advertising &
9979 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
9980 if (oldadv != newadv) {
9981 phydev->advertising &=
9982 ~(ADVERTISED_Pause |
9983 ADVERTISED_Asym_Pause);
9984 phydev->advertising |= newadv;
9985 if (phydev->autoneg) {
9987 * Always renegotiate the link to
9988 * inform our link partner of our
9989 * flow control settings, even if the
9990 * flow control is forced. Let
9991 * tg3_adjust_link() do the final
9992 * flow control setup.
9994 return phy_start_aneg(phydev);
9998 if (!epause->autoneg)
9999 tg3_setup_flow_control(tp, 0, 0);
10001 tp->link_config.orig_advertising &=
10002 ~(ADVERTISED_Pause |
10003 ADVERTISED_Asym_Pause);
10004 tp->link_config.orig_advertising |= newadv;
10009 if (netif_running(dev)) {
10010 tg3_netif_stop(tp);
10014 tg3_full_lock(tp, irq_sync);
10016 if (epause->autoneg)
10017 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10019 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10020 if (epause->rx_pause)
10021 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10023 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10024 if (epause->tx_pause)
10025 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10027 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10029 if (netif_running(dev)) {
10030 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10031 err = tg3_restart_hw(tp, 1);
10033 tg3_netif_start(tp);
10036 tg3_full_unlock(tp);
10042 static u32 tg3_get_rx_csum(struct net_device *dev)
10044 struct tg3 *tp = netdev_priv(dev);
10045 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10048 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10050 struct tg3 *tp = netdev_priv(dev);
10052 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10058 spin_lock_bh(&tp->lock);
10060 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10062 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10063 spin_unlock_bh(&tp->lock);
10068 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10070 struct tg3 *tp = netdev_priv(dev);
10072 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10078 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10079 ethtool_op_set_tx_ipv6_csum(dev, data);
10081 ethtool_op_set_tx_csum(dev, data);
10086 static int tg3_get_sset_count(struct net_device *dev, int sset)
10090 return TG3_NUM_TEST;
10092 return TG3_NUM_STATS;
10094 return -EOPNOTSUPP;
10098 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
10100 switch (stringset) {
10102 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
10105 memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys));
10108 WARN_ON(1); /* we need a WARN() */
10113 static int tg3_phys_id(struct net_device *dev, u32 data)
10115 struct tg3 *tp = netdev_priv(dev);
10118 if (!netif_running(tp->dev))
10122 data = UINT_MAX / 2;
10124 for (i = 0; i < (data * 2); i++) {
10126 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10127 LED_CTRL_1000MBPS_ON |
10128 LED_CTRL_100MBPS_ON |
10129 LED_CTRL_10MBPS_ON |
10130 LED_CTRL_TRAFFIC_OVERRIDE |
10131 LED_CTRL_TRAFFIC_BLINK |
10132 LED_CTRL_TRAFFIC_LED);
10135 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10136 LED_CTRL_TRAFFIC_OVERRIDE);
10138 if (msleep_interruptible(500))
10141 tw32(MAC_LED_CTRL, tp->led_ctrl);
10145 static void tg3_get_ethtool_stats(struct net_device *dev,
10146 struct ethtool_stats *estats, u64 *tmp_stats)
10148 struct tg3 *tp = netdev_priv(dev);
10149 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10152 #define NVRAM_TEST_SIZE 0x100
10153 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10154 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10155 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
10156 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10157 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10159 static int tg3_test_nvram(struct tg3 *tp)
10163 int i, j, k, err = 0, size;
10165 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10168 if (tg3_nvram_read(tp, 0, &magic) != 0)
10171 if (magic == TG3_EEPROM_MAGIC)
10172 size = NVRAM_TEST_SIZE;
10173 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10174 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10175 TG3_EEPROM_SB_FORMAT_1) {
10176 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10177 case TG3_EEPROM_SB_REVISION_0:
10178 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10180 case TG3_EEPROM_SB_REVISION_2:
10181 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10183 case TG3_EEPROM_SB_REVISION_3:
10184 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10191 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10192 size = NVRAM_SELFBOOT_HW_SIZE;
10196 buf = kmalloc(size, GFP_KERNEL);
10201 for (i = 0, j = 0; i < size; i += 4, j++) {
10202 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10209 /* Selfboot format */
10210 magic = be32_to_cpu(buf[0]);
10211 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10212 TG3_EEPROM_MAGIC_FW) {
10213 u8 *buf8 = (u8 *) buf, csum8 = 0;
10215 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10216 TG3_EEPROM_SB_REVISION_2) {
10217 /* For rev 2, the csum doesn't include the MBA. */
10218 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10220 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10223 for (i = 0; i < size; i++)
10236 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10237 TG3_EEPROM_MAGIC_HW) {
10238 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10239 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10240 u8 *buf8 = (u8 *) buf;
10242 /* Separate the parity bits and the data bytes. */
10243 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10244 if ((i == 0) || (i == 8)) {
10248 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10249 parity[k++] = buf8[i] & msk;
10251 } else if (i == 16) {
10255 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10256 parity[k++] = buf8[i] & msk;
10259 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10260 parity[k++] = buf8[i] & msk;
10263 data[j++] = buf8[i];
10267 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10268 u8 hw8 = hweight8(data[i]);
10270 if ((hw8 & 0x1) && parity[i])
10272 else if (!(hw8 & 0x1) && !parity[i])
10279 /* Bootstrap checksum at offset 0x10 */
10280 csum = calc_crc((unsigned char *) buf, 0x10);
10281 if (csum != be32_to_cpu(buf[0x10/4]))
10284 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10285 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10286 if (csum != be32_to_cpu(buf[0xfc/4]))
10296 #define TG3_SERDES_TIMEOUT_SEC 2
10297 #define TG3_COPPER_TIMEOUT_SEC 6
10299 static int tg3_test_link(struct tg3 *tp)
10303 if (!netif_running(tp->dev))
10306 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
10307 max = TG3_SERDES_TIMEOUT_SEC;
10309 max = TG3_COPPER_TIMEOUT_SEC;
10311 for (i = 0; i < max; i++) {
10312 if (netif_carrier_ok(tp->dev))
10315 if (msleep_interruptible(1000))
10322 /* Only test the commonly used registers */
10323 static int tg3_test_registers(struct tg3 *tp)
10325 int i, is_5705, is_5750;
10326 u32 offset, read_mask, write_mask, val, save_val, read_val;
10330 #define TG3_FL_5705 0x1
10331 #define TG3_FL_NOT_5705 0x2
10332 #define TG3_FL_NOT_5788 0x4
10333 #define TG3_FL_NOT_5750 0x8
10337 /* MAC Control Registers */
10338 { MAC_MODE, TG3_FL_NOT_5705,
10339 0x00000000, 0x00ef6f8c },
10340 { MAC_MODE, TG3_FL_5705,
10341 0x00000000, 0x01ef6b8c },
10342 { MAC_STATUS, TG3_FL_NOT_5705,
10343 0x03800107, 0x00000000 },
10344 { MAC_STATUS, TG3_FL_5705,
10345 0x03800100, 0x00000000 },
10346 { MAC_ADDR_0_HIGH, 0x0000,
10347 0x00000000, 0x0000ffff },
10348 { MAC_ADDR_0_LOW, 0x0000,
10349 0x00000000, 0xffffffff },
10350 { MAC_RX_MTU_SIZE, 0x0000,
10351 0x00000000, 0x0000ffff },
10352 { MAC_TX_MODE, 0x0000,
10353 0x00000000, 0x00000070 },
10354 { MAC_TX_LENGTHS, 0x0000,
10355 0x00000000, 0x00003fff },
10356 { MAC_RX_MODE, TG3_FL_NOT_5705,
10357 0x00000000, 0x000007fc },
10358 { MAC_RX_MODE, TG3_FL_5705,
10359 0x00000000, 0x000007dc },
10360 { MAC_HASH_REG_0, 0x0000,
10361 0x00000000, 0xffffffff },
10362 { MAC_HASH_REG_1, 0x0000,
10363 0x00000000, 0xffffffff },
10364 { MAC_HASH_REG_2, 0x0000,
10365 0x00000000, 0xffffffff },
10366 { MAC_HASH_REG_3, 0x0000,
10367 0x00000000, 0xffffffff },
10369 /* Receive Data and Receive BD Initiator Control Registers. */
10370 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10371 0x00000000, 0xffffffff },
10372 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10373 0x00000000, 0xffffffff },
10374 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10375 0x00000000, 0x00000003 },
10376 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10377 0x00000000, 0xffffffff },
10378 { RCVDBDI_STD_BD+0, 0x0000,
10379 0x00000000, 0xffffffff },
10380 { RCVDBDI_STD_BD+4, 0x0000,
10381 0x00000000, 0xffffffff },
10382 { RCVDBDI_STD_BD+8, 0x0000,
10383 0x00000000, 0xffff0002 },
10384 { RCVDBDI_STD_BD+0xc, 0x0000,
10385 0x00000000, 0xffffffff },
10387 /* Receive BD Initiator Control Registers. */
10388 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10389 0x00000000, 0xffffffff },
10390 { RCVBDI_STD_THRESH, TG3_FL_5705,
10391 0x00000000, 0x000003ff },
10392 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10393 0x00000000, 0xffffffff },
10395 /* Host Coalescing Control Registers. */
10396 { HOSTCC_MODE, TG3_FL_NOT_5705,
10397 0x00000000, 0x00000004 },
10398 { HOSTCC_MODE, TG3_FL_5705,
10399 0x00000000, 0x000000f6 },
10400 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10401 0x00000000, 0xffffffff },
10402 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10403 0x00000000, 0x000003ff },
10404 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10405 0x00000000, 0xffffffff },
10406 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10407 0x00000000, 0x000003ff },
10408 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10409 0x00000000, 0xffffffff },
10410 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10411 0x00000000, 0x000000ff },
10412 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10413 0x00000000, 0xffffffff },
10414 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10415 0x00000000, 0x000000ff },
10416 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10417 0x00000000, 0xffffffff },
10418 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10419 0x00000000, 0xffffffff },
10420 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10421 0x00000000, 0xffffffff },
10422 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10423 0x00000000, 0x000000ff },
10424 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10425 0x00000000, 0xffffffff },
10426 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10427 0x00000000, 0x000000ff },
10428 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10429 0x00000000, 0xffffffff },
10430 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10431 0x00000000, 0xffffffff },
10432 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10433 0x00000000, 0xffffffff },
10434 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10435 0x00000000, 0xffffffff },
10436 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10437 0x00000000, 0xffffffff },
10438 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10439 0xffffffff, 0x00000000 },
10440 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10441 0xffffffff, 0x00000000 },
10443 /* Buffer Manager Control Registers. */
10444 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10445 0x00000000, 0x007fff80 },
10446 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10447 0x00000000, 0x007fffff },
10448 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10449 0x00000000, 0x0000003f },
10450 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10451 0x00000000, 0x000001ff },
10452 { BUFMGR_MB_HIGH_WATER, 0x0000,
10453 0x00000000, 0x000001ff },
10454 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10455 0xffffffff, 0x00000000 },
10456 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10457 0xffffffff, 0x00000000 },
10459 /* Mailbox Registers */
10460 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10461 0x00000000, 0x000001ff },
10462 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10463 0x00000000, 0x000001ff },
10464 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10465 0x00000000, 0x000007ff },
10466 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10467 0x00000000, 0x000001ff },
10469 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10472 is_5705 = is_5750 = 0;
10473 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10475 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10479 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10480 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10483 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10486 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10487 (reg_tbl[i].flags & TG3_FL_NOT_5788))
10490 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10493 offset = (u32) reg_tbl[i].offset;
10494 read_mask = reg_tbl[i].read_mask;
10495 write_mask = reg_tbl[i].write_mask;
10497 /* Save the original register content */
10498 save_val = tr32(offset);
10500 /* Determine the read-only value. */
10501 read_val = save_val & read_mask;
10503 /* Write zero to the register, then make sure the read-only bits
10504 * are not changed and the read/write bits are all zeros.
10508 val = tr32(offset);
10510 /* Test the read-only and read/write bits. */
10511 if (((val & read_mask) != read_val) || (val & write_mask))
10514 /* Write ones to all the bits defined by RdMask and WrMask, then
10515 * make sure the read-only bits are not changed and the
10516 * read/write bits are all ones.
10518 tw32(offset, read_mask | write_mask);
10520 val = tr32(offset);
10522 /* Test the read-only bits. */
10523 if ((val & read_mask) != read_val)
10526 /* Test the read/write bits. */
10527 if ((val & write_mask) != write_mask)
10530 tw32(offset, save_val);
10536 if (netif_msg_hw(tp))
10537 netdev_err(tp->dev,
10538 "Register test failed at offset %x\n", offset);
10539 tw32(offset, save_val);
10543 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10545 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10549 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10550 for (j = 0; j < len; j += 4) {
10553 tg3_write_mem(tp, offset + j, test_pattern[i]);
10554 tg3_read_mem(tp, offset + j, &val);
10555 if (val != test_pattern[i])
10562 static int tg3_test_memory(struct tg3 *tp)
10564 static struct mem_entry {
10567 } mem_tbl_570x[] = {
10568 { 0x00000000, 0x00b50},
10569 { 0x00002000, 0x1c000},
10570 { 0xffffffff, 0x00000}
10571 }, mem_tbl_5705[] = {
10572 { 0x00000100, 0x0000c},
10573 { 0x00000200, 0x00008},
10574 { 0x00004000, 0x00800},
10575 { 0x00006000, 0x01000},
10576 { 0x00008000, 0x02000},
10577 { 0x00010000, 0x0e000},
10578 { 0xffffffff, 0x00000}
10579 }, mem_tbl_5755[] = {
10580 { 0x00000200, 0x00008},
10581 { 0x00004000, 0x00800},
10582 { 0x00006000, 0x00800},
10583 { 0x00008000, 0x02000},
10584 { 0x00010000, 0x0c000},
10585 { 0xffffffff, 0x00000}
10586 }, mem_tbl_5906[] = {
10587 { 0x00000200, 0x00008},
10588 { 0x00004000, 0x00400},
10589 { 0x00006000, 0x00400},
10590 { 0x00008000, 0x01000},
10591 { 0x00010000, 0x01000},
10592 { 0xffffffff, 0x00000}
10593 }, mem_tbl_5717[] = {
10594 { 0x00000200, 0x00008},
10595 { 0x00010000, 0x0a000},
10596 { 0x00020000, 0x13c00},
10597 { 0xffffffff, 0x00000}
10598 }, mem_tbl_57765[] = {
10599 { 0x00000200, 0x00008},
10600 { 0x00004000, 0x00800},
10601 { 0x00006000, 0x09800},
10602 { 0x00010000, 0x0a000},
10603 { 0xffffffff, 0x00000}
10605 struct mem_entry *mem_tbl;
10609 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
10610 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
10611 mem_tbl = mem_tbl_5717;
10612 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10613 mem_tbl = mem_tbl_57765;
10614 else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10615 mem_tbl = mem_tbl_5755;
10616 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10617 mem_tbl = mem_tbl_5906;
10618 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10619 mem_tbl = mem_tbl_5705;
10621 mem_tbl = mem_tbl_570x;
10623 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10624 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
10632 #define TG3_MAC_LOOPBACK 0
10633 #define TG3_PHY_LOOPBACK 1
10635 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10637 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10638 u32 desc_idx, coal_now;
10639 struct sk_buff *skb, *rx_skb;
10642 int num_pkts, tx_len, rx_len, i, err;
10643 struct tg3_rx_buffer_desc *desc;
10644 struct tg3_napi *tnapi, *rnapi;
10645 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
10647 tnapi = &tp->napi[0];
10648 rnapi = &tp->napi[0];
10649 if (tp->irq_cnt > 1) {
10650 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
10651 rnapi = &tp->napi[1];
10652 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
10653 tnapi = &tp->napi[1];
10655 coal_now = tnapi->coal_now | rnapi->coal_now;
10657 if (loopback_mode == TG3_MAC_LOOPBACK) {
10658 /* HW errata - mac loopback fails in some cases on 5780.
10659 * Normal traffic and PHY loopback are not affected by
10662 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10665 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10666 MAC_MODE_PORT_INT_LPBACK;
10667 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10668 mac_mode |= MAC_MODE_LINK_POLARITY;
10669 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
10670 mac_mode |= MAC_MODE_PORT_MODE_MII;
10672 mac_mode |= MAC_MODE_PORT_MODE_GMII;
10673 tw32(MAC_MODE, mac_mode);
10674 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10677 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10678 tg3_phy_fet_toggle_apd(tp, false);
10679 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10681 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10683 tg3_phy_toggle_automdix(tp, 0);
10685 tg3_writephy(tp, MII_BMCR, val);
10688 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10689 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10690 tg3_writephy(tp, MII_TG3_FET_PTEST,
10691 MII_TG3_FET_PTEST_FRC_TX_LINK |
10692 MII_TG3_FET_PTEST_FRC_TX_LOCK);
10693 /* The write needs to be flushed for the AC131 */
10694 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10695 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
10696 mac_mode |= MAC_MODE_PORT_MODE_MII;
10698 mac_mode |= MAC_MODE_PORT_MODE_GMII;
10700 /* reset to prevent losing 1st rx packet intermittently */
10701 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10702 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10704 tw32_f(MAC_RX_MODE, tp->rx_mode);
10706 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10707 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
10708 if (masked_phy_id == TG3_PHY_ID_BCM5401)
10709 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10710 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
10711 mac_mode |= MAC_MODE_LINK_POLARITY;
10712 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10713 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10715 tw32(MAC_MODE, mac_mode);
10723 skb = netdev_alloc_skb(tp->dev, tx_len);
10727 tx_data = skb_put(skb, tx_len);
10728 memcpy(tx_data, tp->dev->dev_addr, 6);
10729 memset(tx_data + 6, 0x0, 8);
10731 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10733 for (i = 14; i < tx_len; i++)
10734 tx_data[i] = (u8) (i & 0xff);
10736 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10737 if (pci_dma_mapping_error(tp->pdev, map)) {
10738 dev_kfree_skb(skb);
10742 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10747 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10751 tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10756 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10757 tr32_mailbox(tnapi->prodmbox);
10761 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
10762 for (i = 0; i < 35; i++) {
10763 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10768 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10769 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10770 if ((tx_idx == tnapi->tx_prod) &&
10771 (rx_idx == (rx_start_idx + num_pkts)))
10775 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10776 dev_kfree_skb(skb);
10778 if (tx_idx != tnapi->tx_prod)
10781 if (rx_idx != rx_start_idx + num_pkts)
10784 desc = &rnapi->rx_rcb[rx_start_idx];
10785 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10786 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10787 if (opaque_key != RXD_OPAQUE_RING_STD)
10790 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10791 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10794 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10795 if (rx_len != tx_len)
10798 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10800 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10801 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10803 for (i = 14; i < tx_len; i++) {
10804 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10809 /* tg3_free_rings will unmap and free the rx_skb */
10814 #define TG3_MAC_LOOPBACK_FAILED 1
10815 #define TG3_PHY_LOOPBACK_FAILED 2
10816 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10817 TG3_PHY_LOOPBACK_FAILED)
10819 static int tg3_test_loopback(struct tg3 *tp)
10824 if (!netif_running(tp->dev))
10825 return TG3_LOOPBACK_FAILED;
10827 err = tg3_reset_hw(tp, 1);
10829 return TG3_LOOPBACK_FAILED;
10831 /* Turn off gphy autopowerdown. */
10832 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
10833 tg3_phy_toggle_apd(tp, false);
10835 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10839 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10841 /* Wait for up to 40 microseconds to acquire lock. */
10842 for (i = 0; i < 4; i++) {
10843 status = tr32(TG3_CPMU_MUTEX_GNT);
10844 if (status == CPMU_MUTEX_GNT_DRIVER)
10849 if (status != CPMU_MUTEX_GNT_DRIVER)
10850 return TG3_LOOPBACK_FAILED;
10852 /* Turn off link-based power management. */
10853 cpmuctrl = tr32(TG3_CPMU_CTRL);
10854 tw32(TG3_CPMU_CTRL,
10855 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10856 CPMU_CTRL_LINK_AWARE_MODE));
10859 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10860 err |= TG3_MAC_LOOPBACK_FAILED;
10862 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10863 tw32(TG3_CPMU_CTRL, cpmuctrl);
10865 /* Release the mutex */
10866 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10869 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10870 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10871 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10872 err |= TG3_PHY_LOOPBACK_FAILED;
10875 /* Re-enable gphy autopowerdown. */
10876 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
10877 tg3_phy_toggle_apd(tp, true);
10882 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10885 struct tg3 *tp = netdev_priv(dev);
10887 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10888 tg3_set_power_state(tp, PCI_D0);
10890 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10892 if (tg3_test_nvram(tp) != 0) {
10893 etest->flags |= ETH_TEST_FL_FAILED;
10896 if (tg3_test_link(tp) != 0) {
10897 etest->flags |= ETH_TEST_FL_FAILED;
10900 if (etest->flags & ETH_TEST_FL_OFFLINE) {
10901 int err, err2 = 0, irq_sync = 0;
10903 if (netif_running(dev)) {
10905 tg3_netif_stop(tp);
10909 tg3_full_lock(tp, irq_sync);
10911 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10912 err = tg3_nvram_lock(tp);
10913 tg3_halt_cpu(tp, RX_CPU_BASE);
10914 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10915 tg3_halt_cpu(tp, TX_CPU_BASE);
10917 tg3_nvram_unlock(tp);
10919 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
10922 if (tg3_test_registers(tp) != 0) {
10923 etest->flags |= ETH_TEST_FL_FAILED;
10926 if (tg3_test_memory(tp) != 0) {
10927 etest->flags |= ETH_TEST_FL_FAILED;
10930 if ((data[4] = tg3_test_loopback(tp)) != 0)
10931 etest->flags |= ETH_TEST_FL_FAILED;
10933 tg3_full_unlock(tp);
10935 if (tg3_test_interrupt(tp) != 0) {
10936 etest->flags |= ETH_TEST_FL_FAILED;
10940 tg3_full_lock(tp, 0);
10942 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10943 if (netif_running(dev)) {
10944 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10945 err2 = tg3_restart_hw(tp, 1);
10947 tg3_netif_start(tp);
10950 tg3_full_unlock(tp);
10952 if (irq_sync && !err2)
10955 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10956 tg3_set_power_state(tp, PCI_D3hot);
10960 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10962 struct mii_ioctl_data *data = if_mii(ifr);
10963 struct tg3 *tp = netdev_priv(dev);
10966 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10967 struct phy_device *phydev;
10968 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10970 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10971 return phy_mii_ioctl(phydev, ifr, cmd);
10976 data->phy_id = tp->phy_addr;
10979 case SIOCGMIIREG: {
10982 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
10983 break; /* We have no PHY */
10985 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10988 spin_lock_bh(&tp->lock);
10989 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10990 spin_unlock_bh(&tp->lock);
10992 data->val_out = mii_regval;
10998 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
10999 break; /* We have no PHY */
11001 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11004 spin_lock_bh(&tp->lock);
11005 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
11006 spin_unlock_bh(&tp->lock);
11014 return -EOPNOTSUPP;
11017 #if TG3_VLAN_TAG_USED
11018 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
11020 struct tg3 *tp = netdev_priv(dev);
11022 if (!netif_running(dev)) {
11027 tg3_netif_stop(tp);
11029 tg3_full_lock(tp, 0);
11033 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11034 __tg3_set_rx_mode(dev);
11036 tg3_netif_start(tp);
11038 tg3_full_unlock(tp);
11042 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11044 struct tg3 *tp = netdev_priv(dev);
11046 memcpy(ec, &tp->coal, sizeof(*ec));
11050 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11052 struct tg3 *tp = netdev_priv(dev);
11053 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11054 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11056 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11057 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11058 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11059 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11060 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11063 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11064 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11065 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11066 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11067 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11068 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11069 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11070 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11071 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11072 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11075 /* No rx interrupts will be generated if both are zero */
11076 if ((ec->rx_coalesce_usecs == 0) &&
11077 (ec->rx_max_coalesced_frames == 0))
11080 /* No tx interrupts will be generated if both are zero */
11081 if ((ec->tx_coalesce_usecs == 0) &&
11082 (ec->tx_max_coalesced_frames == 0))
11085 /* Only copy relevant parameters, ignore all others. */
11086 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11087 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11088 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11089 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11090 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11091 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11092 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11093 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11094 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11096 if (netif_running(dev)) {
11097 tg3_full_lock(tp, 0);
11098 __tg3_set_coalesce(tp, &tp->coal);
11099 tg3_full_unlock(tp);
11104 static const struct ethtool_ops tg3_ethtool_ops = {
11105 .get_settings = tg3_get_settings,
11106 .set_settings = tg3_set_settings,
11107 .get_drvinfo = tg3_get_drvinfo,
11108 .get_regs_len = tg3_get_regs_len,
11109 .get_regs = tg3_get_regs,
11110 .get_wol = tg3_get_wol,
11111 .set_wol = tg3_set_wol,
11112 .get_msglevel = tg3_get_msglevel,
11113 .set_msglevel = tg3_set_msglevel,
11114 .nway_reset = tg3_nway_reset,
11115 .get_link = ethtool_op_get_link,
11116 .get_eeprom_len = tg3_get_eeprom_len,
11117 .get_eeprom = tg3_get_eeprom,
11118 .set_eeprom = tg3_set_eeprom,
11119 .get_ringparam = tg3_get_ringparam,
11120 .set_ringparam = tg3_set_ringparam,
11121 .get_pauseparam = tg3_get_pauseparam,
11122 .set_pauseparam = tg3_set_pauseparam,
11123 .get_rx_csum = tg3_get_rx_csum,
11124 .set_rx_csum = tg3_set_rx_csum,
11125 .set_tx_csum = tg3_set_tx_csum,
11126 .set_sg = ethtool_op_set_sg,
11127 .set_tso = tg3_set_tso,
11128 .self_test = tg3_self_test,
11129 .get_strings = tg3_get_strings,
11130 .phys_id = tg3_phys_id,
11131 .get_ethtool_stats = tg3_get_ethtool_stats,
11132 .get_coalesce = tg3_get_coalesce,
11133 .set_coalesce = tg3_set_coalesce,
11134 .get_sset_count = tg3_get_sset_count,
11137 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11139 u32 cursize, val, magic;
11141 tp->nvram_size = EEPROM_CHIP_SIZE;
11143 if (tg3_nvram_read(tp, 0, &magic) != 0)
11146 if ((magic != TG3_EEPROM_MAGIC) &&
11147 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11148 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11152 * Size the chip by reading offsets at increasing powers of two.
11153 * When we encounter our validation signature, we know the addressing
11154 * has wrapped around, and thus have our chip size.
11158 while (cursize < tp->nvram_size) {
11159 if (tg3_nvram_read(tp, cursize, &val) != 0)
11168 tp->nvram_size = cursize;
11171 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11175 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11176 tg3_nvram_read(tp, 0, &val) != 0)
11179 /* Selfboot format */
11180 if (val != TG3_EEPROM_MAGIC) {
11181 tg3_get_eeprom_size(tp);
11185 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11187 /* This is confusing. We want to operate on the
11188 * 16-bit value at offset 0xf2. The tg3_nvram_read()
11189 * call will read from NVRAM and byteswap the data
11190 * according to the byteswapping settings for all
11191 * other register accesses. This ensures the data we
11192 * want will always reside in the lower 16-bits.
11193 * However, the data in NVRAM is in LE format, which
11194 * means the data from the NVRAM read will always be
11195 * opposite the endianness of the CPU. The 16-bit
11196 * byteswap then brings the data to CPU endianness.
11198 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11202 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11205 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11209 nvcfg1 = tr32(NVRAM_CFG1);
11210 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11211 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11213 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11214 tw32(NVRAM_CFG1, nvcfg1);
11217 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11218 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11219 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11220 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11221 tp->nvram_jedecnum = JEDEC_ATMEL;
11222 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11223 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11225 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11226 tp->nvram_jedecnum = JEDEC_ATMEL;
11227 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11229 case FLASH_VENDOR_ATMEL_EEPROM:
11230 tp->nvram_jedecnum = JEDEC_ATMEL;
11231 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11232 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11234 case FLASH_VENDOR_ST:
11235 tp->nvram_jedecnum = JEDEC_ST;
11236 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11237 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11239 case FLASH_VENDOR_SAIFUN:
11240 tp->nvram_jedecnum = JEDEC_SAIFUN;
11241 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11243 case FLASH_VENDOR_SST_SMALL:
11244 case FLASH_VENDOR_SST_LARGE:
11245 tp->nvram_jedecnum = JEDEC_SST;
11246 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11250 tp->nvram_jedecnum = JEDEC_ATMEL;
11251 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11252 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11256 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11258 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11259 case FLASH_5752PAGE_SIZE_256:
11260 tp->nvram_pagesize = 256;
11262 case FLASH_5752PAGE_SIZE_512:
11263 tp->nvram_pagesize = 512;
11265 case FLASH_5752PAGE_SIZE_1K:
11266 tp->nvram_pagesize = 1024;
11268 case FLASH_5752PAGE_SIZE_2K:
11269 tp->nvram_pagesize = 2048;
11271 case FLASH_5752PAGE_SIZE_4K:
11272 tp->nvram_pagesize = 4096;
11274 case FLASH_5752PAGE_SIZE_264:
11275 tp->nvram_pagesize = 264;
11277 case FLASH_5752PAGE_SIZE_528:
11278 tp->nvram_pagesize = 528;
11283 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11287 nvcfg1 = tr32(NVRAM_CFG1);
11289 /* NVRAM protection for TPM */
11290 if (nvcfg1 & (1 << 27))
11291 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11293 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11294 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11295 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11296 tp->nvram_jedecnum = JEDEC_ATMEL;
11297 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11299 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11300 tp->nvram_jedecnum = JEDEC_ATMEL;
11301 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11302 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11304 case FLASH_5752VENDOR_ST_M45PE10:
11305 case FLASH_5752VENDOR_ST_M45PE20:
11306 case FLASH_5752VENDOR_ST_M45PE40:
11307 tp->nvram_jedecnum = JEDEC_ST;
11308 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11309 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11313 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11314 tg3_nvram_get_pagesize(tp, nvcfg1);
11316 /* For eeprom, set pagesize to maximum eeprom size */
11317 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11319 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11320 tw32(NVRAM_CFG1, nvcfg1);
11324 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11326 u32 nvcfg1, protect = 0;
11328 nvcfg1 = tr32(NVRAM_CFG1);
11330 /* NVRAM protection for TPM */
11331 if (nvcfg1 & (1 << 27)) {
11332 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11336 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11338 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11339 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11340 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11341 case FLASH_5755VENDOR_ATMEL_FLASH_5:
11342 tp->nvram_jedecnum = JEDEC_ATMEL;
11343 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11344 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11345 tp->nvram_pagesize = 264;
11346 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11347 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11348 tp->nvram_size = (protect ? 0x3e200 :
11349 TG3_NVRAM_SIZE_512KB);
11350 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11351 tp->nvram_size = (protect ? 0x1f200 :
11352 TG3_NVRAM_SIZE_256KB);
11354 tp->nvram_size = (protect ? 0x1f200 :
11355 TG3_NVRAM_SIZE_128KB);
11357 case FLASH_5752VENDOR_ST_M45PE10:
11358 case FLASH_5752VENDOR_ST_M45PE20:
11359 case FLASH_5752VENDOR_ST_M45PE40:
11360 tp->nvram_jedecnum = JEDEC_ST;
11361 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11362 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11363 tp->nvram_pagesize = 256;
11364 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11365 tp->nvram_size = (protect ?
11366 TG3_NVRAM_SIZE_64KB :
11367 TG3_NVRAM_SIZE_128KB);
11368 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11369 tp->nvram_size = (protect ?
11370 TG3_NVRAM_SIZE_64KB :
11371 TG3_NVRAM_SIZE_256KB);
11373 tp->nvram_size = (protect ?
11374 TG3_NVRAM_SIZE_128KB :
11375 TG3_NVRAM_SIZE_512KB);
11380 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11384 nvcfg1 = tr32(NVRAM_CFG1);
11386 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11387 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11388 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11389 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11390 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11391 tp->nvram_jedecnum = JEDEC_ATMEL;
11392 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11393 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11395 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11396 tw32(NVRAM_CFG1, nvcfg1);
11398 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11399 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11400 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11401 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11402 tp->nvram_jedecnum = JEDEC_ATMEL;
11403 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11404 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11405 tp->nvram_pagesize = 264;
11407 case FLASH_5752VENDOR_ST_M45PE10:
11408 case FLASH_5752VENDOR_ST_M45PE20:
11409 case FLASH_5752VENDOR_ST_M45PE40:
11410 tp->nvram_jedecnum = JEDEC_ST;
11411 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11412 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11413 tp->nvram_pagesize = 256;
11418 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11420 u32 nvcfg1, protect = 0;
11422 nvcfg1 = tr32(NVRAM_CFG1);
11424 /* NVRAM protection for TPM */
11425 if (nvcfg1 & (1 << 27)) {
11426 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11430 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11432 case FLASH_5761VENDOR_ATMEL_ADB021D:
11433 case FLASH_5761VENDOR_ATMEL_ADB041D:
11434 case FLASH_5761VENDOR_ATMEL_ADB081D:
11435 case FLASH_5761VENDOR_ATMEL_ADB161D:
11436 case FLASH_5761VENDOR_ATMEL_MDB021D:
11437 case FLASH_5761VENDOR_ATMEL_MDB041D:
11438 case FLASH_5761VENDOR_ATMEL_MDB081D:
11439 case FLASH_5761VENDOR_ATMEL_MDB161D:
11440 tp->nvram_jedecnum = JEDEC_ATMEL;
11441 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11442 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11443 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11444 tp->nvram_pagesize = 256;
11446 case FLASH_5761VENDOR_ST_A_M45PE20:
11447 case FLASH_5761VENDOR_ST_A_M45PE40:
11448 case FLASH_5761VENDOR_ST_A_M45PE80:
11449 case FLASH_5761VENDOR_ST_A_M45PE16:
11450 case FLASH_5761VENDOR_ST_M_M45PE20:
11451 case FLASH_5761VENDOR_ST_M_M45PE40:
11452 case FLASH_5761VENDOR_ST_M_M45PE80:
11453 case FLASH_5761VENDOR_ST_M_M45PE16:
11454 tp->nvram_jedecnum = JEDEC_ST;
11455 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11456 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11457 tp->nvram_pagesize = 256;
11462 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11465 case FLASH_5761VENDOR_ATMEL_ADB161D:
11466 case FLASH_5761VENDOR_ATMEL_MDB161D:
11467 case FLASH_5761VENDOR_ST_A_M45PE16:
11468 case FLASH_5761VENDOR_ST_M_M45PE16:
11469 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11471 case FLASH_5761VENDOR_ATMEL_ADB081D:
11472 case FLASH_5761VENDOR_ATMEL_MDB081D:
11473 case FLASH_5761VENDOR_ST_A_M45PE80:
11474 case FLASH_5761VENDOR_ST_M_M45PE80:
11475 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11477 case FLASH_5761VENDOR_ATMEL_ADB041D:
11478 case FLASH_5761VENDOR_ATMEL_MDB041D:
11479 case FLASH_5761VENDOR_ST_A_M45PE40:
11480 case FLASH_5761VENDOR_ST_M_M45PE40:
11481 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11483 case FLASH_5761VENDOR_ATMEL_ADB021D:
11484 case FLASH_5761VENDOR_ATMEL_MDB021D:
11485 case FLASH_5761VENDOR_ST_A_M45PE20:
11486 case FLASH_5761VENDOR_ST_M_M45PE20:
11487 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11493 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11495 tp->nvram_jedecnum = JEDEC_ATMEL;
11496 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11497 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11500 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11504 nvcfg1 = tr32(NVRAM_CFG1);
11506 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11507 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11508 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11509 tp->nvram_jedecnum = JEDEC_ATMEL;
11510 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11511 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11513 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11514 tw32(NVRAM_CFG1, nvcfg1);
11516 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11517 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11518 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11519 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11520 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11521 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11522 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11523 tp->nvram_jedecnum = JEDEC_ATMEL;
11524 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11525 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11527 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11528 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11529 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11530 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11531 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11533 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11534 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11535 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11537 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11538 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11539 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11543 case FLASH_5752VENDOR_ST_M45PE10:
11544 case FLASH_5752VENDOR_ST_M45PE20:
11545 case FLASH_5752VENDOR_ST_M45PE40:
11546 tp->nvram_jedecnum = JEDEC_ST;
11547 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11548 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11550 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11551 case FLASH_5752VENDOR_ST_M45PE10:
11552 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11554 case FLASH_5752VENDOR_ST_M45PE20:
11555 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11557 case FLASH_5752VENDOR_ST_M45PE40:
11558 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11563 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11567 tg3_nvram_get_pagesize(tp, nvcfg1);
11568 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11569 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11573 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11577 nvcfg1 = tr32(NVRAM_CFG1);
11579 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11580 case FLASH_5717VENDOR_ATMEL_EEPROM:
11581 case FLASH_5717VENDOR_MICRO_EEPROM:
11582 tp->nvram_jedecnum = JEDEC_ATMEL;
11583 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11584 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11586 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11587 tw32(NVRAM_CFG1, nvcfg1);
11589 case FLASH_5717VENDOR_ATMEL_MDB011D:
11590 case FLASH_5717VENDOR_ATMEL_ADB011B:
11591 case FLASH_5717VENDOR_ATMEL_ADB011D:
11592 case FLASH_5717VENDOR_ATMEL_MDB021D:
11593 case FLASH_5717VENDOR_ATMEL_ADB021B:
11594 case FLASH_5717VENDOR_ATMEL_ADB021D:
11595 case FLASH_5717VENDOR_ATMEL_45USPT:
11596 tp->nvram_jedecnum = JEDEC_ATMEL;
11597 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11598 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11600 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11601 case FLASH_5717VENDOR_ATMEL_MDB021D:
11602 case FLASH_5717VENDOR_ATMEL_ADB021B:
11603 case FLASH_5717VENDOR_ATMEL_ADB021D:
11604 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11607 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11611 case FLASH_5717VENDOR_ST_M_M25PE10:
11612 case FLASH_5717VENDOR_ST_A_M25PE10:
11613 case FLASH_5717VENDOR_ST_M_M45PE10:
11614 case FLASH_5717VENDOR_ST_A_M45PE10:
11615 case FLASH_5717VENDOR_ST_M_M25PE20:
11616 case FLASH_5717VENDOR_ST_A_M25PE20:
11617 case FLASH_5717VENDOR_ST_M_M45PE20:
11618 case FLASH_5717VENDOR_ST_A_M45PE20:
11619 case FLASH_5717VENDOR_ST_25USPT:
11620 case FLASH_5717VENDOR_ST_45USPT:
11621 tp->nvram_jedecnum = JEDEC_ST;
11622 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11623 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11625 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11626 case FLASH_5717VENDOR_ST_M_M25PE20:
11627 case FLASH_5717VENDOR_ST_A_M25PE20:
11628 case FLASH_5717VENDOR_ST_M_M45PE20:
11629 case FLASH_5717VENDOR_ST_A_M45PE20:
11630 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11633 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11638 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11642 tg3_nvram_get_pagesize(tp, nvcfg1);
11643 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11644 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11647 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11648 static void __devinit tg3_nvram_init(struct tg3 *tp)
11650 tw32_f(GRC_EEPROM_ADDR,
11651 (EEPROM_ADDR_FSM_RESET |
11652 (EEPROM_DEFAULT_CLOCK_PERIOD <<
11653 EEPROM_ADDR_CLKPERD_SHIFT)));
11657 /* Enable seeprom accesses. */
11658 tw32_f(GRC_LOCAL_CTRL,
11659 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11662 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11663 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11664 tp->tg3_flags |= TG3_FLAG_NVRAM;
11666 if (tg3_nvram_lock(tp)) {
11667 netdev_warn(tp->dev,
11668 "Cannot get nvram lock, %s failed\n",
11672 tg3_enable_nvram_access(tp);
11674 tp->nvram_size = 0;
11676 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11677 tg3_get_5752_nvram_info(tp);
11678 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11679 tg3_get_5755_nvram_info(tp);
11680 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11681 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11682 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11683 tg3_get_5787_nvram_info(tp);
11684 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11685 tg3_get_5761_nvram_info(tp);
11686 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11687 tg3_get_5906_nvram_info(tp);
11688 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11689 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11690 tg3_get_57780_nvram_info(tp);
11691 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
11692 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
11693 tg3_get_5717_nvram_info(tp);
11695 tg3_get_nvram_info(tp);
11697 if (tp->nvram_size == 0)
11698 tg3_get_nvram_size(tp);
11700 tg3_disable_nvram_access(tp);
11701 tg3_nvram_unlock(tp);
11704 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11706 tg3_get_eeprom_size(tp);
11710 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11711 u32 offset, u32 len, u8 *buf)
11716 for (i = 0; i < len; i += 4) {
11722 memcpy(&data, buf + i, 4);
11725 * The SEEPROM interface expects the data to always be opposite
11726 * the native endian format. We accomplish this by reversing
11727 * all the operations that would have been performed on the
11728 * data from a call to tg3_nvram_read_be32().
11730 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11732 val = tr32(GRC_EEPROM_ADDR);
11733 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11735 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11737 tw32(GRC_EEPROM_ADDR, val |
11738 (0 << EEPROM_ADDR_DEVID_SHIFT) |
11739 (addr & EEPROM_ADDR_ADDR_MASK) |
11740 EEPROM_ADDR_START |
11741 EEPROM_ADDR_WRITE);
11743 for (j = 0; j < 1000; j++) {
11744 val = tr32(GRC_EEPROM_ADDR);
11746 if (val & EEPROM_ADDR_COMPLETE)
11750 if (!(val & EEPROM_ADDR_COMPLETE)) {
11759 /* offset and length are dword aligned */
11760 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11764 u32 pagesize = tp->nvram_pagesize;
11765 u32 pagemask = pagesize - 1;
11769 tmp = kmalloc(pagesize, GFP_KERNEL);
11775 u32 phy_addr, page_off, size;
11777 phy_addr = offset & ~pagemask;
11779 for (j = 0; j < pagesize; j += 4) {
11780 ret = tg3_nvram_read_be32(tp, phy_addr + j,
11781 (__be32 *) (tmp + j));
11788 page_off = offset & pagemask;
11795 memcpy(tmp + page_off, buf, size);
11797 offset = offset + (pagesize - page_off);
11799 tg3_enable_nvram_access(tp);
11802 * Before we can erase the flash page, we need
11803 * to issue a special "write enable" command.
11805 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11807 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11810 /* Erase the target page */
11811 tw32(NVRAM_ADDR, phy_addr);
11813 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11814 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11816 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11819 /* Issue another write enable to start the write. */
11820 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11822 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11825 for (j = 0; j < pagesize; j += 4) {
11828 data = *((__be32 *) (tmp + j));
11830 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11832 tw32(NVRAM_ADDR, phy_addr + j);
11834 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11838 nvram_cmd |= NVRAM_CMD_FIRST;
11839 else if (j == (pagesize - 4))
11840 nvram_cmd |= NVRAM_CMD_LAST;
11842 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11849 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11850 tg3_nvram_exec_cmd(tp, nvram_cmd);
11857 /* offset and length are dword aligned */
11858 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11863 for (i = 0; i < len; i += 4, offset += 4) {
11864 u32 page_off, phy_addr, nvram_cmd;
11867 memcpy(&data, buf + i, 4);
11868 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11870 page_off = offset % tp->nvram_pagesize;
11872 phy_addr = tg3_nvram_phys_addr(tp, offset);
11874 tw32(NVRAM_ADDR, phy_addr);
11876 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11878 if (page_off == 0 || i == 0)
11879 nvram_cmd |= NVRAM_CMD_FIRST;
11880 if (page_off == (tp->nvram_pagesize - 4))
11881 nvram_cmd |= NVRAM_CMD_LAST;
11883 if (i == (len - 4))
11884 nvram_cmd |= NVRAM_CMD_LAST;
11886 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11887 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11888 (tp->nvram_jedecnum == JEDEC_ST) &&
11889 (nvram_cmd & NVRAM_CMD_FIRST)) {
11891 if ((ret = tg3_nvram_exec_cmd(tp,
11892 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11897 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11898 /* We always do complete word writes to eeprom. */
11899 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11902 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11908 /* offset and length are dword aligned */
11909 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11913 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11914 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11915 ~GRC_LCLCTRL_GPIO_OUTPUT1);
11919 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11920 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11924 ret = tg3_nvram_lock(tp);
11928 tg3_enable_nvram_access(tp);
11929 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11930 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
11931 tw32(NVRAM_WRITE1, 0x406);
11933 grc_mode = tr32(GRC_MODE);
11934 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11936 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11937 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11939 ret = tg3_nvram_write_block_buffered(tp, offset, len,
11942 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11946 grc_mode = tr32(GRC_MODE);
11947 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11949 tg3_disable_nvram_access(tp);
11950 tg3_nvram_unlock(tp);
11953 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11954 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11961 struct subsys_tbl_ent {
11962 u16 subsys_vendor, subsys_devid;
11966 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
11967 /* Broadcom boards. */
11968 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11969 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
11970 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11971 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
11972 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11973 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
11974 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11975 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
11976 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11977 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
11978 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11979 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
11980 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11981 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
11982 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11983 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
11984 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11985 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
11986 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11987 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
11988 { TG3PCI_SUBVENDOR_ID_BROADCOM,
11989 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
11992 { TG3PCI_SUBVENDOR_ID_3COM,
11993 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
11994 { TG3PCI_SUBVENDOR_ID_3COM,
11995 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
11996 { TG3PCI_SUBVENDOR_ID_3COM,
11997 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
11998 { TG3PCI_SUBVENDOR_ID_3COM,
11999 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
12000 { TG3PCI_SUBVENDOR_ID_3COM,
12001 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
12004 { TG3PCI_SUBVENDOR_ID_DELL,
12005 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
12006 { TG3PCI_SUBVENDOR_ID_DELL,
12007 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
12008 { TG3PCI_SUBVENDOR_ID_DELL,
12009 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
12010 { TG3PCI_SUBVENDOR_ID_DELL,
12011 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
12013 /* Compaq boards. */
12014 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12015 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
12016 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12017 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
12018 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12019 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
12020 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12021 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
12022 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12023 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
12026 { TG3PCI_SUBVENDOR_ID_IBM,
12027 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
12030 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
12034 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12035 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12036 tp->pdev->subsystem_vendor) &&
12037 (subsys_id_to_phy_id[i].subsys_devid ==
12038 tp->pdev->subsystem_device))
12039 return &subsys_id_to_phy_id[i];
12044 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12049 /* On some early chips the SRAM cannot be accessed in D3hot state,
12050 * so need make sure we're in D0.
12052 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12053 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12054 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12057 /* Make sure register accesses (indirect or otherwise)
12058 * will function correctly.
12060 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12061 tp->misc_host_ctrl);
12063 /* The memory arbiter has to be enabled in order for SRAM accesses
12064 * to succeed. Normally on powerup the tg3 chip firmware will make
12065 * sure it is enabled, but other entities such as system netboot
12066 * code might disable it.
12068 val = tr32(MEMARB_MODE);
12069 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12071 tp->phy_id = TG3_PHY_ID_INVALID;
12072 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12074 /* Assume an onboard device and WOL capable by default. */
12075 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12077 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12078 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12079 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12080 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12082 val = tr32(VCPU_CFGSHDW);
12083 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12084 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12085 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12086 (val & VCPU_CFGSHDW_WOL_MAGPKT))
12087 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12091 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12092 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12093 u32 nic_cfg, led_cfg;
12094 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12095 int eeprom_phy_serdes = 0;
12097 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12098 tp->nic_sram_data_cfg = nic_cfg;
12100 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12101 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12102 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12103 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12104 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12105 (ver > 0) && (ver < 0x100))
12106 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12108 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12109 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12111 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12112 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12113 eeprom_phy_serdes = 1;
12115 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12116 if (nic_phy_id != 0) {
12117 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12118 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12120 eeprom_phy_id = (id1 >> 16) << 10;
12121 eeprom_phy_id |= (id2 & 0xfc00) << 16;
12122 eeprom_phy_id |= (id2 & 0x03ff) << 0;
12126 tp->phy_id = eeprom_phy_id;
12127 if (eeprom_phy_serdes) {
12128 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12129 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12131 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
12134 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12135 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12136 SHASTA_EXT_LED_MODE_MASK);
12138 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12142 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12143 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12146 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12147 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12150 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12151 tp->led_ctrl = LED_CTRL_MODE_MAC;
12153 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12154 * read on some older 5700/5701 bootcode.
12156 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12158 GET_ASIC_REV(tp->pci_chip_rev_id) ==
12160 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12164 case SHASTA_EXT_LED_SHARED:
12165 tp->led_ctrl = LED_CTRL_MODE_SHARED;
12166 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12167 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12168 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12169 LED_CTRL_MODE_PHY_2);
12172 case SHASTA_EXT_LED_MAC:
12173 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12176 case SHASTA_EXT_LED_COMBO:
12177 tp->led_ctrl = LED_CTRL_MODE_COMBO;
12178 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12179 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12180 LED_CTRL_MODE_PHY_2);
12185 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12186 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12187 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12188 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12190 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12191 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12193 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12194 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12195 if ((tp->pdev->subsystem_vendor ==
12196 PCI_VENDOR_ID_ARIMA) &&
12197 (tp->pdev->subsystem_device == 0x205a ||
12198 tp->pdev->subsystem_device == 0x2063))
12199 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12201 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12202 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12205 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12206 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12207 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12208 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12211 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12212 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12213 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12215 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
12216 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12217 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12219 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12220 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12221 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12223 if (cfg2 & (1 << 17))
12224 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
12226 /* serdes signal pre-emphasis in register 0x590 set by */
12227 /* bootcode if bit 18 is set */
12228 if (cfg2 & (1 << 18))
12229 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
12231 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12232 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
12233 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12234 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
12236 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12237 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12238 !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
12241 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12242 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12243 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12246 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12247 tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
12248 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12249 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12250 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12251 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12254 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12255 device_set_wakeup_enable(&tp->pdev->dev,
12256 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12259 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12264 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12265 tw32(OTP_CTRL, cmd);
12267 /* Wait for up to 1 ms for command to execute. */
12268 for (i = 0; i < 100; i++) {
12269 val = tr32(OTP_STATUS);
12270 if (val & OTP_STATUS_CMD_DONE)
12275 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12278 /* Read the gphy configuration from the OTP region of the chip. The gphy
12279 * configuration is a 32-bit value that straddles the alignment boundary.
12280 * We do two 32-bit reads and then shift and merge the results.
12282 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12284 u32 bhalf_otp, thalf_otp;
12286 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12288 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12291 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12293 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12296 thalf_otp = tr32(OTP_READ_DATA);
12298 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12300 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12303 bhalf_otp = tr32(OTP_READ_DATA);
12305 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12308 static int __devinit tg3_phy_probe(struct tg3 *tp)
12310 u32 hw_phy_id_1, hw_phy_id_2;
12311 u32 hw_phy_id, hw_phy_id_masked;
12314 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12315 return tg3_phy_init(tp);
12317 /* Reading the PHY ID register can conflict with ASF
12318 * firmware access to the PHY hardware.
12321 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12322 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12323 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
12325 /* Now read the physical PHY_ID from the chip and verify
12326 * that it is sane. If it doesn't look good, we fall back
12327 * to either the hard-coded table based PHY_ID and failing
12328 * that the value found in the eeprom area.
12330 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12331 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12333 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
12334 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12335 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
12337 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
12340 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
12341 tp->phy_id = hw_phy_id;
12342 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
12343 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12345 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
12347 if (tp->phy_id != TG3_PHY_ID_INVALID) {
12348 /* Do nothing, phy ID already set up in
12349 * tg3_get_eeprom_hw_cfg().
12352 struct subsys_tbl_ent *p;
12354 /* No eeprom signature? Try the hardcoded
12355 * subsys device table.
12357 p = tg3_lookup_by_subsys(tp);
12361 tp->phy_id = p->phy_id;
12363 tp->phy_id == TG3_PHY_ID_BCM8002)
12364 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12368 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
12369 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12370 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12371 u32 bmsr, adv_reg, tg3_ctrl, mask;
12373 tg3_readphy(tp, MII_BMSR, &bmsr);
12374 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12375 (bmsr & BMSR_LSTATUS))
12376 goto skip_phy_reset;
12378 err = tg3_phy_reset(tp);
12382 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12383 ADVERTISE_100HALF | ADVERTISE_100FULL |
12384 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12386 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
12387 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12388 MII_TG3_CTRL_ADV_1000_FULL);
12389 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12390 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12391 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12392 MII_TG3_CTRL_ENABLE_AS_MASTER);
12395 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12396 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12397 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12398 if (!tg3_copper_is_advertising_all(tp, mask)) {
12399 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12401 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12402 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12404 tg3_writephy(tp, MII_BMCR,
12405 BMCR_ANENABLE | BMCR_ANRESTART);
12407 tg3_phy_set_wirespeed(tp);
12409 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12410 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12411 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12415 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
12416 err = tg3_init_5401phy_dsp(tp);
12420 err = tg3_init_5401phy_dsp(tp);
12423 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
12424 tp->link_config.advertising =
12425 (ADVERTISED_1000baseT_Half |
12426 ADVERTISED_1000baseT_Full |
12427 ADVERTISED_Autoneg |
12429 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
12430 tp->link_config.advertising &=
12431 ~(ADVERTISED_1000baseT_Half |
12432 ADVERTISED_1000baseT_Full);
12437 static void __devinit tg3_read_vpd(struct tg3 *tp)
12440 unsigned int block_end, rosize, len;
12444 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12445 tg3_nvram_read(tp, 0x0, &magic))
12448 vpd_data = kmalloc(TG3_NVM_VPD_LEN, GFP_KERNEL);
12452 if (magic == TG3_EEPROM_MAGIC) {
12453 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12456 /* The data is in little-endian format in NVRAM.
12457 * Use the big-endian read routines to preserve
12458 * the byte order as it exists in NVRAM.
12460 if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12461 goto out_not_found;
12463 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12467 unsigned int pos = 0;
12469 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12470 cnt = pci_read_vpd(tp->pdev, pos,
12471 TG3_NVM_VPD_LEN - pos,
12473 if (cnt == -ETIMEDOUT || -EINTR)
12476 goto out_not_found;
12478 if (pos != TG3_NVM_VPD_LEN)
12479 goto out_not_found;
12482 i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
12483 PCI_VPD_LRDT_RO_DATA);
12485 goto out_not_found;
12487 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
12488 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
12489 i += PCI_VPD_LRDT_TAG_SIZE;
12491 if (block_end > TG3_NVM_VPD_LEN)
12492 goto out_not_found;
12494 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12495 PCI_VPD_RO_KEYWORD_MFR_ID);
12497 len = pci_vpd_info_field_size(&vpd_data[j]);
12499 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12500 if (j + len > block_end || len != 4 ||
12501 memcmp(&vpd_data[j], "1028", 4))
12504 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12505 PCI_VPD_RO_KEYWORD_VENDOR0);
12509 len = pci_vpd_info_field_size(&vpd_data[j]);
12511 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12512 if (j + len > block_end)
12515 memcpy(tp->fw_ver, &vpd_data[j], len);
12516 strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
12520 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12521 PCI_VPD_RO_KEYWORD_PARTNO);
12523 goto out_not_found;
12525 len = pci_vpd_info_field_size(&vpd_data[i]);
12527 i += PCI_VPD_INFO_FLD_HDR_SIZE;
12528 if (len > TG3_BPN_SIZE ||
12529 (len + i) > TG3_NVM_VPD_LEN)
12530 goto out_not_found;
12532 memcpy(tp->board_part_number, &vpd_data[i], len);
12536 if (tp->board_part_number[0])
12540 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
12541 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717)
12542 strcpy(tp->board_part_number, "BCM5717");
12543 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
12544 strcpy(tp->board_part_number, "BCM5718");
12547 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
12548 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12549 strcpy(tp->board_part_number, "BCM57780");
12550 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12551 strcpy(tp->board_part_number, "BCM57760");
12552 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12553 strcpy(tp->board_part_number, "BCM57790");
12554 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12555 strcpy(tp->board_part_number, "BCM57788");
12558 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
12559 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
12560 strcpy(tp->board_part_number, "BCM57761");
12561 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
12562 strcpy(tp->board_part_number, "BCM57765");
12563 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
12564 strcpy(tp->board_part_number, "BCM57781");
12565 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
12566 strcpy(tp->board_part_number, "BCM57785");
12567 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
12568 strcpy(tp->board_part_number, "BCM57791");
12569 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12570 strcpy(tp->board_part_number, "BCM57795");
12573 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12574 strcpy(tp->board_part_number, "BCM95906");
12577 strcpy(tp->board_part_number, "none");
12581 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12585 if (tg3_nvram_read(tp, offset, &val) ||
12586 (val & 0xfc000000) != 0x0c000000 ||
12587 tg3_nvram_read(tp, offset + 4, &val) ||
12594 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12596 u32 val, offset, start, ver_offset;
12598 bool newver = false;
12600 if (tg3_nvram_read(tp, 0xc, &offset) ||
12601 tg3_nvram_read(tp, 0x4, &start))
12604 offset = tg3_nvram_logical_addr(tp, offset);
12606 if (tg3_nvram_read(tp, offset, &val))
12609 if ((val & 0xfc000000) == 0x0c000000) {
12610 if (tg3_nvram_read(tp, offset + 4, &val))
12617 dst_off = strlen(tp->fw_ver);
12620 if (TG3_VER_SIZE - dst_off < 16 ||
12621 tg3_nvram_read(tp, offset + 8, &ver_offset))
12624 offset = offset + ver_offset - start;
12625 for (i = 0; i < 16; i += 4) {
12627 if (tg3_nvram_read_be32(tp, offset + i, &v))
12630 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
12635 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12638 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12639 TG3_NVM_BCVER_MAJSFT;
12640 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12641 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
12642 "v%d.%02d", major, minor);
12646 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12648 u32 val, major, minor;
12650 /* Use native endian representation */
12651 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12654 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12655 TG3_NVM_HWSB_CFG1_MAJSFT;
12656 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12657 TG3_NVM_HWSB_CFG1_MINSFT;
12659 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12662 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12664 u32 offset, major, minor, build;
12666 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
12668 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12671 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12672 case TG3_EEPROM_SB_REVISION_0:
12673 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12675 case TG3_EEPROM_SB_REVISION_2:
12676 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12678 case TG3_EEPROM_SB_REVISION_3:
12679 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12681 case TG3_EEPROM_SB_REVISION_4:
12682 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
12684 case TG3_EEPROM_SB_REVISION_5:
12685 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
12691 if (tg3_nvram_read(tp, offset, &val))
12694 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12695 TG3_EEPROM_SB_EDH_BLD_SHFT;
12696 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12697 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12698 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
12700 if (minor > 99 || build > 26)
12703 offset = strlen(tp->fw_ver);
12704 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
12705 " v%d.%02d", major, minor);
12708 offset = strlen(tp->fw_ver);
12709 if (offset < TG3_VER_SIZE - 1)
12710 tp->fw_ver[offset] = 'a' + build - 1;
12714 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12716 u32 val, offset, start;
12719 for (offset = TG3_NVM_DIR_START;
12720 offset < TG3_NVM_DIR_END;
12721 offset += TG3_NVM_DIRENT_SIZE) {
12722 if (tg3_nvram_read(tp, offset, &val))
12725 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12729 if (offset == TG3_NVM_DIR_END)
12732 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12733 start = 0x08000000;
12734 else if (tg3_nvram_read(tp, offset - 4, &start))
12737 if (tg3_nvram_read(tp, offset + 4, &offset) ||
12738 !tg3_fw_img_is_valid(tp, offset) ||
12739 tg3_nvram_read(tp, offset + 8, &val))
12742 offset += val - start;
12744 vlen = strlen(tp->fw_ver);
12746 tp->fw_ver[vlen++] = ',';
12747 tp->fw_ver[vlen++] = ' ';
12749 for (i = 0; i < 4; i++) {
12751 if (tg3_nvram_read_be32(tp, offset, &v))
12754 offset += sizeof(v);
12756 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12757 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12761 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12766 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12772 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12773 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
12776 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12777 if (apedata != APE_SEG_SIG_MAGIC)
12780 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12781 if (!(apedata & APE_FW_STATUS_READY))
12784 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12786 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) {
12787 tp->tg3_flags3 |= TG3_FLG3_APE_HAS_NCSI;
12793 vlen = strlen(tp->fw_ver);
12795 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
12797 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12798 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12799 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12800 (apedata & APE_FW_VERSION_BLDMSK));
12803 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12806 bool vpd_vers = false;
12808 if (tp->fw_ver[0] != 0)
12811 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12812 strcat(tp->fw_ver, "sb");
12816 if (tg3_nvram_read(tp, 0, &val))
12819 if (val == TG3_EEPROM_MAGIC)
12820 tg3_read_bc_ver(tp);
12821 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12822 tg3_read_sb_ver(tp, val);
12823 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12824 tg3_read_hwsb_ver(tp);
12828 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12829 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
12832 tg3_read_mgmtfw_ver(tp);
12835 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12838 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12840 static void inline vlan_features_add(struct net_device *dev, unsigned long flags)
12842 #if TG3_VLAN_TAG_USED
12843 dev->vlan_features |= flags;
12847 static int __devinit tg3_get_invariants(struct tg3 *tp)
12849 static struct pci_device_id write_reorder_chipsets[] = {
12850 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12851 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12852 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12853 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12854 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12855 PCI_DEVICE_ID_VIA_8385_0) },
12859 u32 pci_state_reg, grc_misc_cfg;
12864 /* Force memory write invalidate off. If we leave it on,
12865 * then on 5700_BX chips we have to enable a workaround.
12866 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12867 * to match the cacheline size. The Broadcom driver have this
12868 * workaround but turns MWI off all the times so never uses
12869 * it. This seems to suggest that the workaround is insufficient.
12871 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12872 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12873 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12875 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12876 * has the register indirect write enable bit set before
12877 * we try to access any of the MMIO registers. It is also
12878 * critical that the PCI-X hw workaround situation is decided
12879 * before that as well.
12881 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12884 tp->pci_chip_rev_id = (misc_ctrl_reg >>
12885 MISC_HOST_CTRL_CHIPREV_SHIFT);
12886 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12887 u32 prod_id_asic_rev;
12889 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12890 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12891 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719)
12892 pci_read_config_dword(tp->pdev,
12893 TG3PCI_GEN2_PRODID_ASICREV,
12894 &prod_id_asic_rev);
12895 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
12896 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
12897 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
12898 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
12899 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
12900 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12901 pci_read_config_dword(tp->pdev,
12902 TG3PCI_GEN15_PRODID_ASICREV,
12903 &prod_id_asic_rev);
12905 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12906 &prod_id_asic_rev);
12908 tp->pci_chip_rev_id = prod_id_asic_rev;
12911 /* Wrong chip ID in 5752 A0. This code can be removed later
12912 * as A0 is not in production.
12914 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12915 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12917 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12918 * we need to disable memory and use config. cycles
12919 * only to access all registers. The 5702/03 chips
12920 * can mistakenly decode the special cycles from the
12921 * ICH chipsets as memory write cycles, causing corruption
12922 * of register and memory space. Only certain ICH bridges
12923 * will drive special cycles with non-zero data during the
12924 * address phase which can fall within the 5703's address
12925 * range. This is not an ICH bug as the PCI spec allows
12926 * non-zero address during special cycles. However, only
12927 * these ICH bridges are known to drive non-zero addresses
12928 * during special cycles.
12930 * Since special cycles do not cross PCI bridges, we only
12931 * enable this workaround if the 5703 is on the secondary
12932 * bus of these ICH bridges.
12934 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12935 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12936 static struct tg3_dev_id {
12940 } ich_chipsets[] = {
12941 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12943 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12945 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12947 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12951 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12952 struct pci_dev *bridge = NULL;
12954 while (pci_id->vendor != 0) {
12955 bridge = pci_get_device(pci_id->vendor, pci_id->device,
12961 if (pci_id->rev != PCI_ANY_ID) {
12962 if (bridge->revision > pci_id->rev)
12965 if (bridge->subordinate &&
12966 (bridge->subordinate->number ==
12967 tp->pdev->bus->number)) {
12969 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12970 pci_dev_put(bridge);
12976 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12977 static struct tg3_dev_id {
12980 } bridge_chipsets[] = {
12981 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12982 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12985 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12986 struct pci_dev *bridge = NULL;
12988 while (pci_id->vendor != 0) {
12989 bridge = pci_get_device(pci_id->vendor,
12996 if (bridge->subordinate &&
12997 (bridge->subordinate->number <=
12998 tp->pdev->bus->number) &&
12999 (bridge->subordinate->subordinate >=
13000 tp->pdev->bus->number)) {
13001 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
13002 pci_dev_put(bridge);
13008 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
13009 * DMA addresses > 40-bit. This bridge may have other additional
13010 * 57xx devices behind it in some 4-port NIC designs for example.
13011 * Any tg3 device found behind the bridge will also need the 40-bit
13014 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
13015 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13016 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
13017 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13018 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
13020 struct pci_dev *bridge = NULL;
13023 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
13024 PCI_DEVICE_ID_SERVERWORKS_EPB,
13026 if (bridge && bridge->subordinate &&
13027 (bridge->subordinate->number <=
13028 tp->pdev->bus->number) &&
13029 (bridge->subordinate->subordinate >=
13030 tp->pdev->bus->number)) {
13031 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13032 pci_dev_put(bridge);
13038 /* Initialize misc host control in PCI block. */
13039 tp->misc_host_ctrl |= (misc_ctrl_reg &
13040 MISC_HOST_CTRL_CHIPREV);
13041 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13042 tp->misc_host_ctrl);
13044 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13045 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13046 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13047 tp->pdev_peer = tg3_find_peer(tp);
13049 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13050 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13051 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13052 tp->tg3_flags3 |= TG3_FLG3_5717_PLUS;
13054 /* Intentionally exclude ASIC_REV_5906 */
13055 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13056 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13057 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13058 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13059 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13060 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13061 (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13062 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13064 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13065 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13066 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13067 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13068 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13069 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13071 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13072 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13073 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13075 /* 5700 B0 chips do not support checksumming correctly due
13076 * to hardware bugs.
13078 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13079 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13081 unsigned long features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_GRO;
13083 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13084 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13085 features |= NETIF_F_IPV6_CSUM;
13086 tp->dev->features |= features;
13087 vlan_features_add(tp->dev, features);
13090 /* Determine TSO capabilities */
13091 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13092 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13093 else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13094 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13095 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13096 else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13097 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13098 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13099 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13100 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13101 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13102 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13103 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13104 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13105 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13106 tp->fw_needed = FIRMWARE_TG3TSO5;
13108 tp->fw_needed = FIRMWARE_TG3TSO;
13113 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13114 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13115 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13116 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13117 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13118 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13119 tp->pdev_peer == tp->pdev))
13120 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13122 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13123 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13124 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13127 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
13128 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13129 tp->irq_max = TG3_IRQ_MAX_VECS;
13133 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13134 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13135 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13136 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13137 else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13138 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13139 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13142 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13143 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13145 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13146 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13147 (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13148 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13150 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13153 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13154 if (tp->pcie_cap != 0) {
13157 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13159 pcie_set_readrq(tp->pdev, 4096);
13161 pci_read_config_word(tp->pdev,
13162 tp->pcie_cap + PCI_EXP_LNKCTL,
13164 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13165 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13166 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13167 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13168 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13169 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13170 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13171 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13172 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13173 tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13175 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13176 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13177 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13178 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13179 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13180 if (!tp->pcix_cap) {
13181 dev_err(&tp->pdev->dev,
13182 "Cannot find PCI-X capability, aborting\n");
13186 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13187 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13190 /* If we have an AMD 762 or VIA K8T800 chipset, write
13191 * reordering to the mailbox registers done by the host
13192 * controller can cause major troubles. We read back from
13193 * every mailbox register write to force the writes to be
13194 * posted to the chip in order.
13196 if (pci_dev_present(write_reorder_chipsets) &&
13197 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13198 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13200 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13201 &tp->pci_cacheline_sz);
13202 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13203 &tp->pci_lat_timer);
13204 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13205 tp->pci_lat_timer < 64) {
13206 tp->pci_lat_timer = 64;
13207 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13208 tp->pci_lat_timer);
13211 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13212 /* 5700 BX chips need to have their TX producer index
13213 * mailboxes written twice to workaround a bug.
13215 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13217 /* If we are in PCI-X mode, enable register write workaround.
13219 * The workaround is to use indirect register accesses
13220 * for all chip writes not to mailbox registers.
13222 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13225 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13227 /* The chip can have it's power management PCI config
13228 * space registers clobbered due to this bug.
13229 * So explicitly force the chip into D0 here.
13231 pci_read_config_dword(tp->pdev,
13232 tp->pm_cap + PCI_PM_CTRL,
13234 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13235 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13236 pci_write_config_dword(tp->pdev,
13237 tp->pm_cap + PCI_PM_CTRL,
13240 /* Also, force SERR#/PERR# in PCI command. */
13241 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13242 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13243 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13247 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13248 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13249 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13250 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13252 /* Chip-specific fixup from Broadcom driver */
13253 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13254 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13255 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13256 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13259 /* Default fast path register access methods */
13260 tp->read32 = tg3_read32;
13261 tp->write32 = tg3_write32;
13262 tp->read32_mbox = tg3_read32;
13263 tp->write32_mbox = tg3_write32;
13264 tp->write32_tx_mbox = tg3_write32;
13265 tp->write32_rx_mbox = tg3_write32;
13267 /* Various workaround register access methods */
13268 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13269 tp->write32 = tg3_write_indirect_reg32;
13270 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13271 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13272 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13274 * Back to back register writes can cause problems on these
13275 * chips, the workaround is to read back all reg writes
13276 * except those to mailbox regs.
13278 * See tg3_write_indirect_reg32().
13280 tp->write32 = tg3_write_flush_reg32;
13283 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13284 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13285 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13286 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13287 tp->write32_rx_mbox = tg3_write_flush_reg32;
13290 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13291 tp->read32 = tg3_read_indirect_reg32;
13292 tp->write32 = tg3_write_indirect_reg32;
13293 tp->read32_mbox = tg3_read_indirect_mbox;
13294 tp->write32_mbox = tg3_write_indirect_mbox;
13295 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13296 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13301 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13302 pci_cmd &= ~PCI_COMMAND_MEMORY;
13303 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13305 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13306 tp->read32_mbox = tg3_read32_mbox_5906;
13307 tp->write32_mbox = tg3_write32_mbox_5906;
13308 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13309 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13312 if (tp->write32 == tg3_write_indirect_reg32 ||
13313 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13314 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13315 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13316 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13318 /* Get eeprom hw config before calling tg3_set_power_state().
13319 * In particular, the TG3_FLG2_IS_NIC flag must be
13320 * determined before calling tg3_set_power_state() so that
13321 * we know whether or not to switch out of Vaux power.
13322 * When the flag is set, it means that GPIO1 is used for eeprom
13323 * write protect and also implies that it is a LOM where GPIOs
13324 * are not used to switch power.
13326 tg3_get_eeprom_hw_cfg(tp);
13328 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13329 /* Allow reads and writes to the
13330 * APE register and memory space.
13332 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13333 PCISTATE_ALLOW_APE_SHMEM_WR |
13334 PCISTATE_ALLOW_APE_PSPACE_WR;
13335 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13339 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13340 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13341 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13342 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13343 (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13344 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13346 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13347 * GPIO1 driven high will bring 5700's external PHY out of reset.
13348 * It is also used as eeprom write protect on LOMs.
13350 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13351 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13352 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13353 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13354 GRC_LCLCTRL_GPIO_OUTPUT1);
13355 /* Unused GPIO3 must be driven as output on 5752 because there
13356 * are no pull-up resistors on unused GPIO pins.
13358 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13359 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13361 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13362 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13363 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13364 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13366 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13367 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13368 /* Turn off the debug UART. */
13369 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13370 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13371 /* Keep VMain power. */
13372 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13373 GRC_LCLCTRL_GPIO_OUTPUT0;
13376 /* Force the chip into D0. */
13377 err = tg3_set_power_state(tp, PCI_D0);
13379 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
13383 /* Derive initial jumbo mode from MTU assigned in
13384 * ether_setup() via the alloc_etherdev() call
13386 if (tp->dev->mtu > ETH_DATA_LEN &&
13387 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13388 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13390 /* Determine WakeOnLan speed to use. */
13391 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13392 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13393 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13394 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13395 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13397 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13400 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13401 tp->phy_flags |= TG3_PHYFLG_IS_FET;
13403 /* A few boards don't want Ethernet@WireSpeed phy feature */
13404 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13405 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13406 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13407 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13408 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
13409 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
13410 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
13412 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13413 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13414 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
13415 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13416 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
13418 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13419 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
13420 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13421 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13422 !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
13423 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13424 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13425 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13426 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13427 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13428 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13429 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
13430 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13431 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
13433 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
13436 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13437 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13438 tp->phy_otp = tg3_read_otp_phycfg(tp);
13439 if (tp->phy_otp == 0)
13440 tp->phy_otp = TG3_OTP_DEFAULT;
13443 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13444 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13446 tp->mi_mode = MAC_MI_MODE_BASE;
13448 tp->coalesce_mode = 0;
13449 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13450 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13451 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13453 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13454 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13455 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13457 err = tg3_mdio_init(tp);
13461 /* Initialize data/descriptor byte/word swapping. */
13462 val = tr32(GRC_MODE);
13463 val &= GRC_MODE_HOST_STACKUP;
13464 tw32(GRC_MODE, val | tp->grc_mode);
13466 tg3_switch_clocks(tp);
13468 /* Clear this out for sanity. */
13469 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13471 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13473 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13474 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13475 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13477 if (chiprevid == CHIPREV_ID_5701_A0 ||
13478 chiprevid == CHIPREV_ID_5701_B0 ||
13479 chiprevid == CHIPREV_ID_5701_B2 ||
13480 chiprevid == CHIPREV_ID_5701_B5) {
13481 void __iomem *sram_base;
13483 /* Write some dummy words into the SRAM status block
13484 * area, see if it reads back correctly. If the return
13485 * value is bad, force enable the PCIX workaround.
13487 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13489 writel(0x00000000, sram_base);
13490 writel(0x00000000, sram_base + 4);
13491 writel(0xffffffff, sram_base + 4);
13492 if (readl(sram_base) != 0x00000000)
13493 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13498 tg3_nvram_init(tp);
13500 grc_misc_cfg = tr32(GRC_MISC_CFG);
13501 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13503 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13504 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13505 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13506 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13508 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13509 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13510 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13511 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13512 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13513 HOSTCC_MODE_CLRTICK_TXBD);
13515 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13516 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13517 tp->misc_host_ctrl);
13520 /* Preserve the APE MAC_MODE bits */
13521 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13522 tp->mac_mode = tr32(MAC_MODE) |
13523 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13525 tp->mac_mode = TG3_DEF_MAC_MODE;
13527 /* these are limited to 10/100 only */
13528 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13529 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13530 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13531 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13532 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13533 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13534 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13535 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13536 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13537 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13538 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13539 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13540 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13541 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
13542 (tp->phy_flags & TG3_PHYFLG_IS_FET))
13543 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
13545 err = tg3_phy_probe(tp);
13547 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
13548 /* ... but do not return immediately ... */
13553 tg3_read_fw_ver(tp);
13555 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
13556 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
13558 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13559 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
13561 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
13564 /* 5700 {AX,BX} chips have a broken status block link
13565 * change bit implementation, so we must use the
13566 * status register in those cases.
13568 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13569 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13571 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13573 /* The led_ctrl is set during tg3_phy_probe, here we might
13574 * have to force the link status polling mechanism based
13575 * upon subsystem IDs.
13577 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13578 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13579 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
13580 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
13581 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13584 /* For all SERDES we poll the MAC status register. */
13585 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
13586 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13588 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13590 tp->rx_offset = NET_IP_ALIGN + TG3_RX_HEADROOM;
13591 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
13592 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13593 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
13594 tp->rx_offset -= NET_IP_ALIGN;
13595 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
13596 tp->rx_copy_thresh = ~(u16)0;
13600 tp->rx_std_max_post = TG3_RX_RING_SIZE;
13602 /* Increment the rx prod index on the rx std ring by at most
13603 * 8 for these chips to workaround hw errata.
13605 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13606 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13607 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13608 tp->rx_std_max_post = 8;
13610 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13611 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13612 PCIE_PWR_MGMT_L1_THRESH_MSK;
13617 #ifdef CONFIG_SPARC
13618 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13620 struct net_device *dev = tp->dev;
13621 struct pci_dev *pdev = tp->pdev;
13622 struct device_node *dp = pci_device_to_OF_node(pdev);
13623 const unsigned char *addr;
13626 addr = of_get_property(dp, "local-mac-address", &len);
13627 if (addr && len == 6) {
13628 memcpy(dev->dev_addr, addr, 6);
13629 memcpy(dev->perm_addr, dev->dev_addr, 6);
13635 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13637 struct net_device *dev = tp->dev;
13639 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13640 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13645 static int __devinit tg3_get_device_address(struct tg3 *tp)
13647 struct net_device *dev = tp->dev;
13648 u32 hi, lo, mac_offset;
13651 #ifdef CONFIG_SPARC
13652 if (!tg3_get_macaddr_sparc(tp))
13657 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13658 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13659 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13661 if (tg3_nvram_lock(tp))
13662 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13664 tg3_nvram_unlock(tp);
13665 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13666 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
13667 if (PCI_FUNC(tp->pdev->devfn) & 1)
13669 if (PCI_FUNC(tp->pdev->devfn) > 1)
13670 mac_offset += 0x18c;
13671 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13674 /* First try to get it from MAC address mailbox. */
13675 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13676 if ((hi >> 16) == 0x484b) {
13677 dev->dev_addr[0] = (hi >> 8) & 0xff;
13678 dev->dev_addr[1] = (hi >> 0) & 0xff;
13680 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13681 dev->dev_addr[2] = (lo >> 24) & 0xff;
13682 dev->dev_addr[3] = (lo >> 16) & 0xff;
13683 dev->dev_addr[4] = (lo >> 8) & 0xff;
13684 dev->dev_addr[5] = (lo >> 0) & 0xff;
13686 /* Some old bootcode may report a 0 MAC address in SRAM */
13687 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13690 /* Next, try NVRAM. */
13691 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13692 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13693 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13694 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13695 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13697 /* Finally just fetch it out of the MAC control regs. */
13699 hi = tr32(MAC_ADDR_0_HIGH);
13700 lo = tr32(MAC_ADDR_0_LOW);
13702 dev->dev_addr[5] = lo & 0xff;
13703 dev->dev_addr[4] = (lo >> 8) & 0xff;
13704 dev->dev_addr[3] = (lo >> 16) & 0xff;
13705 dev->dev_addr[2] = (lo >> 24) & 0xff;
13706 dev->dev_addr[1] = hi & 0xff;
13707 dev->dev_addr[0] = (hi >> 8) & 0xff;
13711 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13712 #ifdef CONFIG_SPARC
13713 if (!tg3_get_default_macaddr_sparc(tp))
13718 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13722 #define BOUNDARY_SINGLE_CACHELINE 1
13723 #define BOUNDARY_MULTI_CACHELINE 2
13725 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13727 int cacheline_size;
13731 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13733 cacheline_size = 1024;
13735 cacheline_size = (int) byte * 4;
13737 /* On 5703 and later chips, the boundary bits have no
13740 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13741 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13742 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13745 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13746 goal = BOUNDARY_MULTI_CACHELINE;
13748 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13749 goal = BOUNDARY_SINGLE_CACHELINE;
13755 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
13756 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13763 /* PCI controllers on most RISC systems tend to disconnect
13764 * when a device tries to burst across a cache-line boundary.
13765 * Therefore, letting tg3 do so just wastes PCI bandwidth.
13767 * Unfortunately, for PCI-E there are only limited
13768 * write-side controls for this, and thus for reads
13769 * we will still get the disconnects. We'll also waste
13770 * these PCI cycles for both read and write for chips
13771 * other than 5700 and 5701 which do not implement the
13774 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13775 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13776 switch (cacheline_size) {
13781 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13782 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13783 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13785 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13786 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13791 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13792 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13796 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13797 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13800 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13801 switch (cacheline_size) {
13805 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13806 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13807 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13813 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13814 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13818 switch (cacheline_size) {
13820 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13821 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13822 DMA_RWCTRL_WRITE_BNDRY_16);
13827 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13828 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13829 DMA_RWCTRL_WRITE_BNDRY_32);
13834 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13835 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13836 DMA_RWCTRL_WRITE_BNDRY_64);
13841 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13842 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13843 DMA_RWCTRL_WRITE_BNDRY_128);
13848 val |= (DMA_RWCTRL_READ_BNDRY_256 |
13849 DMA_RWCTRL_WRITE_BNDRY_256);
13852 val |= (DMA_RWCTRL_READ_BNDRY_512 |
13853 DMA_RWCTRL_WRITE_BNDRY_512);
13857 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13858 DMA_RWCTRL_WRITE_BNDRY_1024);
13867 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13869 struct tg3_internal_buffer_desc test_desc;
13870 u32 sram_dma_descs;
13873 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13875 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13876 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13877 tw32(RDMAC_STATUS, 0);
13878 tw32(WDMAC_STATUS, 0);
13880 tw32(BUFMGR_MODE, 0);
13881 tw32(FTQ_RESET, 0);
13883 test_desc.addr_hi = ((u64) buf_dma) >> 32;
13884 test_desc.addr_lo = buf_dma & 0xffffffff;
13885 test_desc.nic_mbuf = 0x00002100;
13886 test_desc.len = size;
13889 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13890 * the *second* time the tg3 driver was getting loaded after an
13893 * Broadcom tells me:
13894 * ...the DMA engine is connected to the GRC block and a DMA
13895 * reset may affect the GRC block in some unpredictable way...
13896 * The behavior of resets to individual blocks has not been tested.
13898 * Broadcom noted the GRC reset will also reset all sub-components.
13901 test_desc.cqid_sqid = (13 << 8) | 2;
13903 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13906 test_desc.cqid_sqid = (16 << 8) | 7;
13908 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13911 test_desc.flags = 0x00000005;
13913 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13916 val = *(((u32 *)&test_desc) + i);
13917 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13918 sram_dma_descs + (i * sizeof(u32)));
13919 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13921 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13924 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13926 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13929 for (i = 0; i < 40; i++) {
13933 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13935 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13936 if ((val & 0xffff) == sram_dma_descs) {
13947 #define TEST_BUFFER_SIZE 0x2000
13949 static int __devinit tg3_test_dma(struct tg3 *tp)
13951 dma_addr_t buf_dma;
13952 u32 *buf, saved_dma_rwctrl;
13955 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13961 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13962 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13964 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13966 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13969 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13970 /* DMA read watermark not used on PCIE */
13971 tp->dma_rwctrl |= 0x00180000;
13972 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
13973 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13974 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
13975 tp->dma_rwctrl |= 0x003f0000;
13977 tp->dma_rwctrl |= 0x003f000f;
13979 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13980 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13981 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
13982 u32 read_water = 0x7;
13984 /* If the 5704 is behind the EPB bridge, we can
13985 * do the less restrictive ONE_DMA workaround for
13986 * better performance.
13988 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13989 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13990 tp->dma_rwctrl |= 0x8000;
13991 else if (ccval == 0x6 || ccval == 0x7)
13992 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13994 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13996 /* Set bit 23 to enable PCIX hw bug fix */
13998 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13999 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
14001 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
14002 /* 5780 always in PCIX mode */
14003 tp->dma_rwctrl |= 0x00144000;
14004 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
14005 /* 5714 always in PCIX mode */
14006 tp->dma_rwctrl |= 0x00148000;
14008 tp->dma_rwctrl |= 0x001b000f;
14012 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14013 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14014 tp->dma_rwctrl &= 0xfffffff0;
14016 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14017 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
14018 /* Remove this if it causes problems for some boards. */
14019 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
14021 /* On 5700/5701 chips, we need to set this bit.
14022 * Otherwise the chip will issue cacheline transactions
14023 * to streamable DMA memory with not all the byte
14024 * enables turned on. This is an error on several
14025 * RISC PCI controllers, in particular sparc64.
14027 * On 5703/5704 chips, this bit has been reassigned
14028 * a different meaning. In particular, it is used
14029 * on those chips to enable a PCI-X workaround.
14031 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
14034 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14037 /* Unneeded, already done by tg3_get_invariants. */
14038 tg3_switch_clocks(tp);
14041 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14042 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14045 /* It is best to perform DMA test with maximum write burst size
14046 * to expose the 5700/5701 write DMA bug.
14048 saved_dma_rwctrl = tp->dma_rwctrl;
14049 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14050 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14055 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14058 /* Send the buffer to the chip. */
14059 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14061 dev_err(&tp->pdev->dev,
14062 "%s: Buffer write failed. err = %d\n",
14068 /* validate data reached card RAM correctly. */
14069 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14071 tg3_read_mem(tp, 0x2100 + (i*4), &val);
14072 if (le32_to_cpu(val) != p[i]) {
14073 dev_err(&tp->pdev->dev,
14074 "%s: Buffer corrupted on device! "
14075 "(%d != %d)\n", __func__, val, i);
14076 /* ret = -ENODEV here? */
14081 /* Now read it back. */
14082 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14084 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
14085 "err = %d\n", __func__, ret);
14090 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14094 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14095 DMA_RWCTRL_WRITE_BNDRY_16) {
14096 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14097 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14098 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14101 dev_err(&tp->pdev->dev,
14102 "%s: Buffer corrupted on read back! "
14103 "(%d != %d)\n", __func__, p[i], i);
14109 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14115 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14116 DMA_RWCTRL_WRITE_BNDRY_16) {
14117 static struct pci_device_id dma_wait_state_chipsets[] = {
14118 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14119 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14123 /* DMA test passed without adjusting DMA boundary,
14124 * now look for chipsets that are known to expose the
14125 * DMA bug without failing the test.
14127 if (pci_dev_present(dma_wait_state_chipsets)) {
14128 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14129 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14131 /* Safe to use the calculated DMA boundary. */
14132 tp->dma_rwctrl = saved_dma_rwctrl;
14135 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14139 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14144 static void __devinit tg3_init_link_config(struct tg3 *tp)
14146 tp->link_config.advertising =
14147 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14148 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14149 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14150 ADVERTISED_Autoneg | ADVERTISED_MII);
14151 tp->link_config.speed = SPEED_INVALID;
14152 tp->link_config.duplex = DUPLEX_INVALID;
14153 tp->link_config.autoneg = AUTONEG_ENABLE;
14154 tp->link_config.active_speed = SPEED_INVALID;
14155 tp->link_config.active_duplex = DUPLEX_INVALID;
14156 tp->link_config.orig_speed = SPEED_INVALID;
14157 tp->link_config.orig_duplex = DUPLEX_INVALID;
14158 tp->link_config.orig_autoneg = AUTONEG_INVALID;
14161 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14163 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
14164 tp->bufmgr_config.mbuf_read_dma_low_water =
14165 DEFAULT_MB_RDMA_LOW_WATER_5705;
14166 tp->bufmgr_config.mbuf_mac_rx_low_water =
14167 DEFAULT_MB_MACRX_LOW_WATER_57765;
14168 tp->bufmgr_config.mbuf_high_water =
14169 DEFAULT_MB_HIGH_WATER_57765;
14171 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14172 DEFAULT_MB_RDMA_LOW_WATER_5705;
14173 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14174 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14175 tp->bufmgr_config.mbuf_high_water_jumbo =
14176 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14177 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14178 tp->bufmgr_config.mbuf_read_dma_low_water =
14179 DEFAULT_MB_RDMA_LOW_WATER_5705;
14180 tp->bufmgr_config.mbuf_mac_rx_low_water =
14181 DEFAULT_MB_MACRX_LOW_WATER_5705;
14182 tp->bufmgr_config.mbuf_high_water =
14183 DEFAULT_MB_HIGH_WATER_5705;
14184 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14185 tp->bufmgr_config.mbuf_mac_rx_low_water =
14186 DEFAULT_MB_MACRX_LOW_WATER_5906;
14187 tp->bufmgr_config.mbuf_high_water =
14188 DEFAULT_MB_HIGH_WATER_5906;
14191 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14192 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14193 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14194 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14195 tp->bufmgr_config.mbuf_high_water_jumbo =
14196 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14198 tp->bufmgr_config.mbuf_read_dma_low_water =
14199 DEFAULT_MB_RDMA_LOW_WATER;
14200 tp->bufmgr_config.mbuf_mac_rx_low_water =
14201 DEFAULT_MB_MACRX_LOW_WATER;
14202 tp->bufmgr_config.mbuf_high_water =
14203 DEFAULT_MB_HIGH_WATER;
14205 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14206 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14207 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14208 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14209 tp->bufmgr_config.mbuf_high_water_jumbo =
14210 DEFAULT_MB_HIGH_WATER_JUMBO;
14213 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14214 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14217 static char * __devinit tg3_phy_string(struct tg3 *tp)
14219 switch (tp->phy_id & TG3_PHY_ID_MASK) {
14220 case TG3_PHY_ID_BCM5400: return "5400";
14221 case TG3_PHY_ID_BCM5401: return "5401";
14222 case TG3_PHY_ID_BCM5411: return "5411";
14223 case TG3_PHY_ID_BCM5701: return "5701";
14224 case TG3_PHY_ID_BCM5703: return "5703";
14225 case TG3_PHY_ID_BCM5704: return "5704";
14226 case TG3_PHY_ID_BCM5705: return "5705";
14227 case TG3_PHY_ID_BCM5750: return "5750";
14228 case TG3_PHY_ID_BCM5752: return "5752";
14229 case TG3_PHY_ID_BCM5714: return "5714";
14230 case TG3_PHY_ID_BCM5780: return "5780";
14231 case TG3_PHY_ID_BCM5755: return "5755";
14232 case TG3_PHY_ID_BCM5787: return "5787";
14233 case TG3_PHY_ID_BCM5784: return "5784";
14234 case TG3_PHY_ID_BCM5756: return "5722/5756";
14235 case TG3_PHY_ID_BCM5906: return "5906";
14236 case TG3_PHY_ID_BCM5761: return "5761";
14237 case TG3_PHY_ID_BCM5718C: return "5718C";
14238 case TG3_PHY_ID_BCM5718S: return "5718S";
14239 case TG3_PHY_ID_BCM57765: return "57765";
14240 case TG3_PHY_ID_BCM5719C: return "5719C";
14241 case TG3_PHY_ID_BCM8002: return "8002/serdes";
14242 case 0: return "serdes";
14243 default: return "unknown";
14247 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14249 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14250 strcpy(str, "PCI Express");
14252 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14253 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14255 strcpy(str, "PCIX:");
14257 if ((clock_ctrl == 7) ||
14258 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14259 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14260 strcat(str, "133MHz");
14261 else if (clock_ctrl == 0)
14262 strcat(str, "33MHz");
14263 else if (clock_ctrl == 2)
14264 strcat(str, "50MHz");
14265 else if (clock_ctrl == 4)
14266 strcat(str, "66MHz");
14267 else if (clock_ctrl == 6)
14268 strcat(str, "100MHz");
14270 strcpy(str, "PCI:");
14271 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14272 strcat(str, "66MHz");
14274 strcat(str, "33MHz");
14276 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14277 strcat(str, ":32-bit");
14279 strcat(str, ":64-bit");
14283 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14285 struct pci_dev *peer;
14286 unsigned int func, devnr = tp->pdev->devfn & ~7;
14288 for (func = 0; func < 8; func++) {
14289 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14290 if (peer && peer != tp->pdev)
14294 /* 5704 can be configured in single-port mode, set peer to
14295 * tp->pdev in that case.
14303 * We don't need to keep the refcount elevated; there's no way
14304 * to remove one half of this device without removing the other
14311 static void __devinit tg3_init_coal(struct tg3 *tp)
14313 struct ethtool_coalesce *ec = &tp->coal;
14315 memset(ec, 0, sizeof(*ec));
14316 ec->cmd = ETHTOOL_GCOALESCE;
14317 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14318 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14319 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14320 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14321 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14322 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14323 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14324 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14325 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14327 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14328 HOSTCC_MODE_CLRTICK_TXBD)) {
14329 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14330 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14331 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14332 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14335 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14336 ec->rx_coalesce_usecs_irq = 0;
14337 ec->tx_coalesce_usecs_irq = 0;
14338 ec->stats_block_coalesce_usecs = 0;
14342 static const struct net_device_ops tg3_netdev_ops = {
14343 .ndo_open = tg3_open,
14344 .ndo_stop = tg3_close,
14345 .ndo_start_xmit = tg3_start_xmit,
14346 .ndo_get_stats64 = tg3_get_stats64,
14347 .ndo_validate_addr = eth_validate_addr,
14348 .ndo_set_multicast_list = tg3_set_rx_mode,
14349 .ndo_set_mac_address = tg3_set_mac_addr,
14350 .ndo_do_ioctl = tg3_ioctl,
14351 .ndo_tx_timeout = tg3_tx_timeout,
14352 .ndo_change_mtu = tg3_change_mtu,
14353 #if TG3_VLAN_TAG_USED
14354 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14356 #ifdef CONFIG_NET_POLL_CONTROLLER
14357 .ndo_poll_controller = tg3_poll_controller,
14361 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14362 .ndo_open = tg3_open,
14363 .ndo_stop = tg3_close,
14364 .ndo_start_xmit = tg3_start_xmit_dma_bug,
14365 .ndo_get_stats64 = tg3_get_stats64,
14366 .ndo_validate_addr = eth_validate_addr,
14367 .ndo_set_multicast_list = tg3_set_rx_mode,
14368 .ndo_set_mac_address = tg3_set_mac_addr,
14369 .ndo_do_ioctl = tg3_ioctl,
14370 .ndo_tx_timeout = tg3_tx_timeout,
14371 .ndo_change_mtu = tg3_change_mtu,
14372 #if TG3_VLAN_TAG_USED
14373 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14375 #ifdef CONFIG_NET_POLL_CONTROLLER
14376 .ndo_poll_controller = tg3_poll_controller,
14380 static int __devinit tg3_init_one(struct pci_dev *pdev,
14381 const struct pci_device_id *ent)
14383 struct net_device *dev;
14385 int i, err, pm_cap;
14386 u32 sndmbx, rcvmbx, intmbx;
14388 u64 dma_mask, persist_dma_mask;
14390 printk_once(KERN_INFO "%s\n", version);
14392 err = pci_enable_device(pdev);
14394 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
14398 err = pci_request_regions(pdev, DRV_MODULE_NAME);
14400 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
14401 goto err_out_disable_pdev;
14404 pci_set_master(pdev);
14406 /* Find power-management capability. */
14407 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14409 dev_err(&pdev->dev,
14410 "Cannot find Power Management capability, aborting\n");
14412 goto err_out_free_res;
14415 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14417 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
14419 goto err_out_free_res;
14422 SET_NETDEV_DEV(dev, &pdev->dev);
14424 #if TG3_VLAN_TAG_USED
14425 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14428 tp = netdev_priv(dev);
14431 tp->pm_cap = pm_cap;
14432 tp->rx_mode = TG3_DEF_RX_MODE;
14433 tp->tx_mode = TG3_DEF_TX_MODE;
14436 tp->msg_enable = tg3_debug;
14438 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14440 /* The word/byte swap controls here control register access byte
14441 * swapping. DMA data byte swapping is controlled in the GRC_MODE
14444 tp->misc_host_ctrl =
14445 MISC_HOST_CTRL_MASK_PCI_INT |
14446 MISC_HOST_CTRL_WORD_SWAP |
14447 MISC_HOST_CTRL_INDIR_ACCESS |
14448 MISC_HOST_CTRL_PCISTATE_RW;
14450 /* The NONFRM (non-frame) byte/word swap controls take effect
14451 * on descriptor entries, anything which isn't packet data.
14453 * The StrongARM chips on the board (one for tx, one for rx)
14454 * are running in big-endian mode.
14456 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14457 GRC_MODE_WSWAP_NONFRM_DATA);
14458 #ifdef __BIG_ENDIAN
14459 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14461 spin_lock_init(&tp->lock);
14462 spin_lock_init(&tp->indirect_lock);
14463 INIT_WORK(&tp->reset_task, tg3_reset_task);
14465 tp->regs = pci_ioremap_bar(pdev, BAR_0);
14467 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
14469 goto err_out_free_dev;
14472 tg3_init_link_config(tp);
14474 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14475 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14477 dev->ethtool_ops = &tg3_ethtool_ops;
14478 dev->watchdog_timeo = TG3_TX_TIMEOUT;
14479 dev->irq = pdev->irq;
14481 err = tg3_get_invariants(tp);
14483 dev_err(&pdev->dev,
14484 "Problem fetching invariants of chip, aborting\n");
14485 goto err_out_iounmap;
14488 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14489 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
14490 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
14491 dev->netdev_ops = &tg3_netdev_ops;
14493 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14496 /* The EPB bridge inside 5714, 5715, and 5780 and any
14497 * device behind the EPB cannot support DMA addresses > 40-bit.
14498 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14499 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14500 * do DMA address check in tg3_start_xmit().
14502 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14503 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14504 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14505 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14506 #ifdef CONFIG_HIGHMEM
14507 dma_mask = DMA_BIT_MASK(64);
14510 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14512 /* Configure DMA attributes. */
14513 if (dma_mask > DMA_BIT_MASK(32)) {
14514 err = pci_set_dma_mask(pdev, dma_mask);
14516 dev->features |= NETIF_F_HIGHDMA;
14517 err = pci_set_consistent_dma_mask(pdev,
14520 dev_err(&pdev->dev, "Unable to obtain 64 bit "
14521 "DMA for consistent allocations\n");
14522 goto err_out_iounmap;
14526 if (err || dma_mask == DMA_BIT_MASK(32)) {
14527 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14529 dev_err(&pdev->dev,
14530 "No usable DMA configuration, aborting\n");
14531 goto err_out_iounmap;
14535 tg3_init_bufmgr_config(tp);
14537 /* Selectively allow TSO based on operating conditions */
14538 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14539 (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14540 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14542 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14543 tp->fw_needed = NULL;
14546 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14547 tp->fw_needed = FIRMWARE_TG3;
14549 /* TSO is on by default on chips that support hardware TSO.
14550 * Firmware TSO on older chips gives lower performance, so it
14551 * is off by default, but can be enabled using ethtool.
14553 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14554 (dev->features & NETIF_F_IP_CSUM)) {
14555 dev->features |= NETIF_F_TSO;
14556 vlan_features_add(dev, NETIF_F_TSO);
14558 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14559 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14560 if (dev->features & NETIF_F_IPV6_CSUM) {
14561 dev->features |= NETIF_F_TSO6;
14562 vlan_features_add(dev, NETIF_F_TSO6);
14564 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14565 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14566 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14567 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14568 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14569 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
14570 dev->features |= NETIF_F_TSO_ECN;
14571 vlan_features_add(dev, NETIF_F_TSO_ECN);
14575 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14576 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14577 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14578 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14579 tp->rx_pending = 63;
14582 err = tg3_get_device_address(tp);
14584 dev_err(&pdev->dev,
14585 "Could not obtain valid ethernet address, aborting\n");
14586 goto err_out_iounmap;
14589 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14590 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14591 if (!tp->aperegs) {
14592 dev_err(&pdev->dev,
14593 "Cannot map APE registers, aborting\n");
14595 goto err_out_iounmap;
14598 tg3_ape_lock_init(tp);
14600 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14601 tg3_read_dash_ver(tp);
14605 * Reset chip in case UNDI or EFI driver did not shutdown
14606 * DMA self test will enable WDMAC and we'll see (spurious)
14607 * pending DMA on the PCI bus at that point.
14609 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14610 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14611 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14612 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14615 err = tg3_test_dma(tp);
14617 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
14618 goto err_out_apeunmap;
14621 /* flow control autonegotiation is default behavior */
14622 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14623 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14625 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14626 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14627 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14628 for (i = 0; i < tp->irq_max; i++) {
14629 struct tg3_napi *tnapi = &tp->napi[i];
14632 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14634 tnapi->int_mbox = intmbx;
14640 tnapi->consmbox = rcvmbx;
14641 tnapi->prodmbox = sndmbx;
14644 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14646 tnapi->coal_now = HOSTCC_MODE_NOW;
14648 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14652 * If we support MSIX, we'll be using RSS. If we're using
14653 * RSS, the first vector only handles link interrupts and the
14654 * remaining vectors handle rx and tx interrupts. Reuse the
14655 * mailbox values for the next iteration. The values we setup
14656 * above are still useful for the single vectored mode.
14671 pci_set_drvdata(pdev, dev);
14673 err = register_netdev(dev);
14675 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
14676 goto err_out_apeunmap;
14679 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14680 tp->board_part_number,
14681 tp->pci_chip_rev_id,
14682 tg3_bus_string(tp, str),
14685 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
14686 struct phy_device *phydev;
14687 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14689 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14690 phydev->drv->name, dev_name(&phydev->dev));
14694 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
14695 ethtype = "10/100Base-TX";
14696 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
14697 ethtype = "1000Base-SX";
14699 ethtype = "10/100/1000Base-T";
14701 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
14702 "(WireSpeed[%d])\n", tg3_phy_string(tp), ethtype,
14703 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0);
14706 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14707 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14708 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14709 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
14710 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14711 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14712 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14714 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
14715 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
14721 iounmap(tp->aperegs);
14722 tp->aperegs = NULL;
14735 pci_release_regions(pdev);
14737 err_out_disable_pdev:
14738 pci_disable_device(pdev);
14739 pci_set_drvdata(pdev, NULL);
14743 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14745 struct net_device *dev = pci_get_drvdata(pdev);
14748 struct tg3 *tp = netdev_priv(dev);
14751 release_firmware(tp->fw);
14753 flush_scheduled_work();
14755 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14760 unregister_netdev(dev);
14762 iounmap(tp->aperegs);
14763 tp->aperegs = NULL;
14770 pci_release_regions(pdev);
14771 pci_disable_device(pdev);
14772 pci_set_drvdata(pdev, NULL);
14776 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14778 struct net_device *dev = pci_get_drvdata(pdev);
14779 struct tg3 *tp = netdev_priv(dev);
14780 pci_power_t target_state;
14783 /* PCI register 4 needs to be saved whether netif_running() or not.
14784 * MSI address and data need to be saved if using MSI and
14787 pci_save_state(pdev);
14789 if (!netif_running(dev))
14792 flush_scheduled_work();
14794 tg3_netif_stop(tp);
14796 del_timer_sync(&tp->timer);
14798 tg3_full_lock(tp, 1);
14799 tg3_disable_ints(tp);
14800 tg3_full_unlock(tp);
14802 netif_device_detach(dev);
14804 tg3_full_lock(tp, 0);
14805 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14806 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14807 tg3_full_unlock(tp);
14809 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14811 err = tg3_set_power_state(tp, target_state);
14815 tg3_full_lock(tp, 0);
14817 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14818 err2 = tg3_restart_hw(tp, 1);
14822 tp->timer.expires = jiffies + tp->timer_offset;
14823 add_timer(&tp->timer);
14825 netif_device_attach(dev);
14826 tg3_netif_start(tp);
14829 tg3_full_unlock(tp);
14838 static int tg3_resume(struct pci_dev *pdev)
14840 struct net_device *dev = pci_get_drvdata(pdev);
14841 struct tg3 *tp = netdev_priv(dev);
14844 pci_restore_state(tp->pdev);
14846 if (!netif_running(dev))
14849 err = tg3_set_power_state(tp, PCI_D0);
14853 netif_device_attach(dev);
14855 tg3_full_lock(tp, 0);
14857 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14858 err = tg3_restart_hw(tp, 1);
14862 tp->timer.expires = jiffies + tp->timer_offset;
14863 add_timer(&tp->timer);
14865 tg3_netif_start(tp);
14868 tg3_full_unlock(tp);
14876 static struct pci_driver tg3_driver = {
14877 .name = DRV_MODULE_NAME,
14878 .id_table = tg3_pci_tbl,
14879 .probe = tg3_init_one,
14880 .remove = __devexit_p(tg3_remove_one),
14881 .suspend = tg3_suspend,
14882 .resume = tg3_resume
14885 static int __init tg3_init(void)
14887 return pci_register_driver(&tg3_driver);
14890 static void __exit tg3_cleanup(void)
14892 pci_unregister_driver(&tg3_driver);
14895 module_init(tg3_init);
14896 module_exit(tg3_cleanup);