drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2010 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/stringify.h>
  22 #include <linux/kernel.h>
  23 #include <linux/types.h>
  24 #include <linux/compiler.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/in.h>
  28 #include <linux/init.h>
  29 #include <linux/ioport.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/ethtool.h>
  35 #include <linux/mii.h>
  36 #include <linux/phy.h>
  37 #include <linux/brcmphy.h>
  38 #include <linux/if_vlan.h>
  39 #include <linux/ip.h>
  40 #include <linux/tcp.h>
  41 #include <linux/workqueue.h>
  42 #include <linux/prefetch.h>
  43 #include <linux/dma-mapping.h>
  44 #include <linux/firmware.h>
  45
  46 #include <net/checksum.h>
  47 #include <net/ip.h>
  48
  49 #include <asm/system.h>
  50 #include <asm/io.h>
  51 #include <asm/byteorder.h>
  52 #include <asm/uaccess.h>
  53
  54 #ifdef CONFIG_SPARC
  55 #include <asm/idprom.h>
  56 #include <asm/prom.h>
  57 #endif
  58
  59 #define BAR_0   0
  60 #define BAR_2   2
  61
  62 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  63 #define TG3_VLAN_TAG_USED 1
  64 #else
  65 #define TG3_VLAN_TAG_USED 0
  66 #endif
  67
  68 #include "tg3.h"
  69
  70 #define DRV_MODULE_NAME         "tg3"
  71 #define TG3_MAJ_NUM                     3
  72 #define TG3_MIN_NUM                     112
  73 #define DRV_MODULE_VERSION      \
  74         __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
  75 #define DRV_MODULE_RELDATE      "July 11, 2010"
  76
  77 #define TG3_DEF_MAC_MODE        0
  78 #define TG3_DEF_RX_MODE         0
  79 #define TG3_DEF_TX_MODE         0
  80 #define TG3_DEF_MSG_ENABLE        \
  81         (NETIF_MSG_DRV          | \
  82          NETIF_MSG_PROBE        | \
  83          NETIF_MSG_LINK         | \
  84          NETIF_MSG_TIMER        | \
  85          NETIF_MSG_IFDOWN       | \
  86          NETIF_MSG_IFUP         | \
  87          NETIF_MSG_RX_ERR       | \
  88          NETIF_MSG_TX_ERR)
  89
  90 /* length of time before we decide the hardware is borked,
  91  * and dev->tx_timeout() should be called to fix the problem
  92  */
  93 #define TG3_TX_TIMEOUT                  (5 * HZ)
  94
  95 /* hardware minimum and maximum for a single frame's data payload */
  96 #define TG3_MIN_MTU                     60
  97 #define TG3_MAX_MTU(tp) \
  98         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  99
 100 /* These numbers seem to be hard coded in the NIC firmware somehow.
 101  * You can't change the ring sizes, but you can change where you place
 102  * them in the NIC onboard memory.
 103  */
 104 #define TG3_RX_RING_SIZE                512
 105 #define TG3_DEF_RX_RING_PENDING         200
 106 #define TG3_RX_JUMBO_RING_SIZE          256
 107 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 108 #define TG3_RSS_INDIR_TBL_SIZE          128
 109
 110 /* Do not place this n-ring entries value into the tp struct itself,
 111  * we really want to expose these constants to GCC so that modulo et
 112  * al.  operations are done with shifts and masks instead of with
 113  * hw multiply/modulo instructions.  Another solution would be to
 114  * replace things like '% foo' with '& (foo - 1)'.
 115  */
 116 #define TG3_RX_RCB_RING_SIZE(tp)        \
 117         (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
 118           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
 119
 120 #define TG3_TX_RING_SIZE                512
 121 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 122
 123 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 124                                  TG3_RX_RING_SIZE)
 125 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
 126                                  TG3_RX_JUMBO_RING_SIZE)
 127 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 128                                  TG3_RX_RCB_RING_SIZE(tp))
 129 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 130                                  TG3_TX_RING_SIZE)
 131 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 132
 133 #define TG3_RX_DMA_ALIGN                16
 134 #define TG3_RX_HEADROOM                 ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
 135
 136 #define TG3_DMA_BYTE_ENAB               64
 137
 138 #define TG3_RX_STD_DMA_SZ               1536
 139 #define TG3_RX_JMB_DMA_SZ               9046
 140
 141 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 142
 143 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 144 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 145
 146 #define TG3_RX_STD_BUFF_RING_SIZE \
 147         (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
 148
 149 #define TG3_RX_JMB_BUFF_RING_SIZE \
 150         (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
 151
 152 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
 153  * that are at least dword aligned when used in PCIX mode.  The driver
 154  * works around this bug by double copying the packet.  This workaround
 155  * is built into the normal double copy length check for efficiency.
 156  *
 157  * However, the double copy is only necessary on those architectures
 158  * where unaligned memory accesses are inefficient.  For those architectures
 159  * where unaligned memory accesses incur little penalty, we can reintegrate
 160  * the 5701 in the normal rx path.  Doing so saves a device structure
 161  * dereference by hardcoding the double copy threshold in place.
 162  */
 163 #define TG3_RX_COPY_THRESHOLD           256
 164 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
 165         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
 166 #else
 167         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
 168 #endif
 169
 170 /* minimum number of free TX descriptors required to wake up TX process */
 171 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 172
 173 #define TG3_RAW_IP_ALIGN 2
 174
 175 /* number of ETHTOOL_GSTATS u64's */
 176 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 177
 178 #define TG3_NUM_TEST            6
 179
 180 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
 181
 182 #define FIRMWARE_TG3            "tigon/tg3.bin"
 183 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 184 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 185
 186 static char version[] __devinitdata =
 187         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
 188
 189 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 190 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 191 MODULE_LICENSE("GPL");
 192 MODULE_VERSION(DRV_MODULE_VERSION);
 193 MODULE_FIRMWARE(FIRMWARE_TG3);
 194 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 195 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 196
 197 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 198 module_param(tg3_debug, int, 0);
 199 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 200
 201 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 255         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 256         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 257         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 258         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 259         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 260         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 261         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 262         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 263         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 264         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 265         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
 266         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
 267         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
 268         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
 269         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
 270         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
 271         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
 272         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
 273         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
 274         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
 275         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 276         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 277         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 278         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 279         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 280         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 281         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 282         {}
 283 };
 284
 285 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 286
 287 static const struct {
 288         const char string[ETH_GSTRING_LEN];
 289 } ethtool_stats_keys[TG3_NUM_STATS] = {
 290         { "rx_octets" },
 291         { "rx_fragments" },
 292         { "rx_ucast_packets" },
 293         { "rx_mcast_packets" },
 294         { "rx_bcast_packets" },
 295         { "rx_fcs_errors" },
 296         { "rx_align_errors" },
 297         { "rx_xon_pause_rcvd" },
 298         { "rx_xoff_pause_rcvd" },
 299         { "rx_mac_ctrl_rcvd" },
 300         { "rx_xoff_entered" },
 301         { "rx_frame_too_long_errors" },
 302         { "rx_jabbers" },
 303         { "rx_undersize_packets" },
 304         { "rx_in_length_errors" },
 305         { "rx_out_length_errors" },
 306         { "rx_64_or_less_octet_packets" },
 307         { "rx_65_to_127_octet_packets" },
 308         { "rx_128_to_255_octet_packets" },
 309         { "rx_256_to_511_octet_packets" },
 310         { "rx_512_to_1023_octet_packets" },
 311         { "rx_1024_to_1522_octet_packets" },
 312         { "rx_1523_to_2047_octet_packets" },
 313         { "rx_2048_to_4095_octet_packets" },
 314         { "rx_4096_to_8191_octet_packets" },
 315         { "rx_8192_to_9022_octet_packets" },
 316
 317         { "tx_octets" },
 318         { "tx_collisions" },
 319
 320         { "tx_xon_sent" },
 321         { "tx_xoff_sent" },
 322         { "tx_flow_control" },
 323         { "tx_mac_errors" },
 324         { "tx_single_collisions" },
 325         { "tx_mult_collisions" },
 326         { "tx_deferred" },
 327         { "tx_excessive_collisions" },
 328         { "tx_late_collisions" },
 329         { "tx_collide_2times" },
 330         { "tx_collide_3times" },
 331         { "tx_collide_4times" },
 332         { "tx_collide_5times" },
 333         { "tx_collide_6times" },
 334         { "tx_collide_7times" },
 335         { "tx_collide_8times" },
 336         { "tx_collide_9times" },
 337         { "tx_collide_10times" },
 338         { "tx_collide_11times" },
 339         { "tx_collide_12times" },
 340         { "tx_collide_13times" },
 341         { "tx_collide_14times" },
 342         { "tx_collide_15times" },
 343         { "tx_ucast_packets" },
 344         { "tx_mcast_packets" },
 345         { "tx_bcast_packets" },
 346         { "tx_carrier_sense_errors" },
 347         { "tx_discards" },
 348         { "tx_errors" },
 349
 350         { "dma_writeq_full" },
 351         { "dma_write_prioq_full" },
 352         { "rxbds_empty" },
 353         { "rx_discards" },
 354         { "rx_errors" },
 355         { "rx_threshold_hit" },
 356
 357         { "dma_readq_full" },
 358         { "dma_read_prioq_full" },
 359         { "tx_comp_queue_full" },
 360
 361         { "ring_set_send_prod_index" },
 362         { "ring_status_update" },
 363         { "nic_irqs" },
 364         { "nic_avoided_irqs" },
 365         { "nic_tx_threshold_hit" }
 366 };
 367
 368 static const struct {
 369         const char string[ETH_GSTRING_LEN];
 370 } ethtool_test_keys[TG3_NUM_TEST] = {
 371         { "nvram test     (online) " },
 372         { "link test      (online) " },
 373         { "register test  (offline)" },
 374         { "memory test    (offline)" },
 375         { "loopback test  (offline)" },
 376         { "interrupt test (offline)" },
 377 };
 378
 379 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 380 {
 381         writel(val, tp->regs + off);
 382 }
 383
 384 static u32 tg3_read32(struct tg3 *tp, u32 off)
 385 {
 386         return readl(tp->regs + off);
 387 }
 388
 389 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 390 {
 391         writel(val, tp->aperegs + off);
 392 }
 393
 394 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 395 {
 396         return readl(tp->aperegs + off);
 397 }
 398
 399 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 400 {
 401         unsigned long flags;
 402
 403         spin_lock_irqsave(&tp->indirect_lock, flags);
 404         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 405         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 406         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 407 }
 408
 409 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 410 {
 411         writel(val, tp->regs + off);
 412         readl(tp->regs + off);
 413 }
 414
 415 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 416 {
 417         unsigned long flags;
 418         u32 val;
 419
 420         spin_lock_irqsave(&tp->indirect_lock, flags);
 421         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 422         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 423         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 424         return val;
 425 }
 426
 427 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 428 {
 429         unsigned long flags;
 430
 431         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 432                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 433                                        TG3_64BIT_REG_LOW, val);
 434                 return;
 435         }
 436         if (off == TG3_RX_STD_PROD_IDX_REG) {
 437                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 438                                        TG3_64BIT_REG_LOW, val);
 439                 return;
 440         }
 441
 442         spin_lock_irqsave(&tp->indirect_lock, flags);
 443         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 444         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 445         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 446
 447         /* In indirect mode when disabling interrupts, we also need
 448          * to clear the interrupt bit in the GRC local ctrl register.
 449          */
 450         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 451             (val == 0x1)) {
 452                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 453                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 454         }
 455 }
 456
 457 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 458 {
 459         unsigned long flags;
 460         u32 val;
 461
 462         spin_lock_irqsave(&tp->indirect_lock, flags);
 463         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 464         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 465         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 466         return val;
 467 }
 468
 469 /* usec_wait specifies the wait time in usec when writing to certain registers
 470  * where it is unsafe to read back the register without some delay.
 471  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 472  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 473  */
 474 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 475 {
 476         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 477             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 478                 /* Non-posted methods */
 479                 tp->write32(tp, off, val);
 480         else {
 481                 /* Posted method */
 482                 tg3_write32(tp, off, val);
 483                 if (usec_wait)
 484                         udelay(usec_wait);
 485                 tp->read32(tp, off);
 486         }
 487         /* Wait again after the read for the posted method to guarantee that
 488          * the wait time is met.
 489          */
 490         if (usec_wait)
 491                 udelay(usec_wait);
 492 }
 493
 494 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 495 {
 496         tp->write32_mbox(tp, off, val);
 497         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 498             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 499                 tp->read32_mbox(tp, off);
 500 }
 501
 502 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 503 {
 504         void __iomem *mbox = tp->regs + off;
 505         writel(val, mbox);
 506         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 507                 writel(val, mbox);
 508         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 509                 readl(mbox);
 510 }
 511
 512 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 513 {
 514         return readl(tp->regs + off + GRCMBOX_BASE);
 515 }
 516
 517 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 518 {
 519         writel(val, tp->regs + off + GRCMBOX_BASE);
 520 }
 521
 522 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
 523 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 524 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
 525 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
 526 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
 527
 528 #define tw32(reg, val)                  tp->write32(tp, reg, val)
 529 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
 530 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
 531 #define tr32(reg)                       tp->read32(tp, reg)
 532
 533 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 534 {
 535         unsigned long flags;
 536
 537         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 538             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 539                 return;
 540
 541         spin_lock_irqsave(&tp->indirect_lock, flags);
 542         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 543                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 544                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 545
 546                 /* Always leave this as zero. */
 547                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 548         } else {
 549                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 550                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 551
 552                 /* Always leave this as zero. */
 553                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 554         }
 555         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 556 }
 557
 558 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 559 {
 560         unsigned long flags;
 561
 562         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 563             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 564                 *val = 0;
 565                 return;
 566         }
 567
 568         spin_lock_irqsave(&tp->indirect_lock, flags);
 569         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 570                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 571                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 572
 573                 /* Always leave this as zero. */
 574                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 575         } else {
 576                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 577                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 578
 579                 /* Always leave this as zero. */
 580                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 581         }
 582         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 583 }
 584
 585 static void tg3_ape_lock_init(struct tg3 *tp)
 586 {
 587         int i;
 588         u32 regbase;
 589
 590         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 591                 regbase = TG3_APE_LOCK_GRANT;
 592         else
 593                 regbase = TG3_APE_PER_LOCK_GRANT;
 594
 595         /* Make sure the driver hasn't any stale locks. */
 596         for (i = 0; i < 8; i++)
 597                 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
 598 }
 599
 600 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 601 {
 602         int i, off;
 603         int ret = 0;
 604         u32 status, req, gnt;
 605
 606         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 607                 return 0;
 608
 609         switch (locknum) {
 610         case TG3_APE_LOCK_GRC:
 611         case TG3_APE_LOCK_MEM:
 612                 break;
 613         default:
 614                 return -EINVAL;
 615         }
 616
 617         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
 618                 req = TG3_APE_LOCK_REQ;
 619                 gnt = TG3_APE_LOCK_GRANT;
 620         } else {
 621                 req = TG3_APE_PER_LOCK_REQ;
 622                 gnt = TG3_APE_PER_LOCK_GRANT;
 623         }
 624
 625         off = 4 * locknum;
 626
 627         tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
 628
 629         /* Wait for up to 1 millisecond to acquire lock. */
 630         for (i = 0; i < 100; i++) {
 631                 status = tg3_ape_read32(tp, gnt + off);
 632                 if (status == APE_LOCK_GRANT_DRIVER)
 633                         break;
 634                 udelay(10);
 635         }
 636
 637         if (status != APE_LOCK_GRANT_DRIVER) {
 638                 /* Revoke the lock request. */
 639                 tg3_ape_write32(tp, gnt + off,
 640                                 APE_LOCK_GRANT_DRIVER);
 641
 642                 ret = -EBUSY;
 643         }
 644
 645         return ret;
 646 }
 647
 648 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 649 {
 650         u32 gnt;
 651
 652         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 653                 return;
 654
 655         switch (locknum) {
 656         case TG3_APE_LOCK_GRC:
 657         case TG3_APE_LOCK_MEM:
 658                 break;
 659         default:
 660                 return;
 661         }
 662
 663         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 664                 gnt = TG3_APE_LOCK_GRANT;
 665         else
 666                 gnt = TG3_APE_PER_LOCK_GRANT;
 667
 668         tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
 669 }
 670
 671 static void tg3_disable_ints(struct tg3 *tp)
 672 {
 673         int i;
 674
 675         tw32(TG3PCI_MISC_HOST_CTRL,
 676              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 677         for (i = 0; i < tp->irq_max; i++)
 678                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 679 }
 680
 681 static void tg3_enable_ints(struct tg3 *tp)
 682 {
 683         int i;
 684
 685         tp->irq_sync = 0;
 686         wmb();
 687
 688         tw32(TG3PCI_MISC_HOST_CTRL,
 689              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 690
 691         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
 692         for (i = 0; i < tp->irq_cnt; i++) {
 693                 struct tg3_napi *tnapi = &tp->napi[i];
 694
 695                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 696                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 697                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 698
 699                 tp->coal_now |= tnapi->coal_now;
 700         }
 701
 702         /* Force an initial interrupt */
 703         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 704             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 705                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 706         else
 707                 tw32(HOSTCC_MODE, tp->coal_now);
 708
 709         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
 710 }
 711
 712 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 713 {
 714         struct tg3 *tp = tnapi->tp;
 715         struct tg3_hw_status *sblk = tnapi->hw_status;
 716         unsigned int work_exists = 0;
 717
 718         /* check for phy events */
 719         if (!(tp->tg3_flags &
 720               (TG3_FLAG_USE_LINKCHG_REG |
 721                TG3_FLAG_POLL_SERDES))) {
 722                 if (sblk->status & SD_STATUS_LINK_CHG)
 723                         work_exists = 1;
 724         }
 725         /* check for RX/TX work to do */
 726         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 727             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
 728                 work_exists = 1;
 729
 730         return work_exists;
 731 }
 732
 733 /* tg3_int_reenable
 734  *  similar to tg3_enable_ints, but it accurately determines whether there
 735  *  is new work pending and can return without flushing the PIO write
 736  *  which reenables interrupts
 737  */
 738 static void tg3_int_reenable(struct tg3_napi *tnapi)
 739 {
 740         struct tg3 *tp = tnapi->tp;
 741
 742         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 743         mmiowb();
 744
 745         /* When doing tagged status, this work check is unnecessary.
 746          * The last_tag we write above tells the chip which piece of
 747          * work we've completed.
 748          */
 749         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 750             tg3_has_work(tnapi))
 751                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 752                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 753 }
 754
 755 static void tg3_napi_disable(struct tg3 *tp)
 756 {
 757         int i;
 758
 759         for (i = tp->irq_cnt - 1; i >= 0; i--)
 760                 napi_disable(&tp->napi[i].napi);
 761 }
 762
 763 static void tg3_napi_enable(struct tg3 *tp)
 764 {
 765         int i;
 766
 767         for (i = 0; i < tp->irq_cnt; i++)
 768                 napi_enable(&tp->napi[i].napi);
 769 }
 770
 771 static inline void tg3_netif_stop(struct tg3 *tp)
 772 {
 773         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 774         tg3_napi_disable(tp);
 775         netif_tx_disable(tp->dev);
 776 }
 777
 778 static inline void tg3_netif_start(struct tg3 *tp)
 779 {
 780         /* NOTE: unconditional netif_tx_wake_all_queues is only
 781          * appropriate so long as all callers are assured to
 782          * have free tx slots (such as after tg3_init_hw)
 783          */
 784         netif_tx_wake_all_queues(tp->dev);
 785
 786         tg3_napi_enable(tp);
 787         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
 788         tg3_enable_ints(tp);
 789 }
 790
 791 static void tg3_switch_clocks(struct tg3 *tp)
 792 {
 793         u32 clock_ctrl;
 794         u32 orig_clock_ctrl;
 795
 796         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 797             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 798                 return;
 799
 800         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 801
 802         orig_clock_ctrl = clock_ctrl;
 803         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 804                        CLOCK_CTRL_CLKRUN_OENABLE |
 805                        0x1f);
 806         tp->pci_clock_ctrl = clock_ctrl;
 807
 808         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 809                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 810                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 811                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 812                 }
 813         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 814                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 815                             clock_ctrl |
 816                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 817                             40);
 818                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 819                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 820                             40);
 821         }
 822         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 823 }
 824
 825 #define PHY_BUSY_LOOPS  5000
 826
 827 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 828 {
 829         u32 frame_val;
 830         unsigned int loops;
 831         int ret;
 832
 833         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 834                 tw32_f(MAC_MI_MODE,
 835                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 836                 udelay(80);
 837         }
 838
 839         *val = 0x0;
 840
 841         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 842                       MI_COM_PHY_ADDR_MASK);
 843         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 844                       MI_COM_REG_ADDR_MASK);
 845         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 846
 847         tw32_f(MAC_MI_COM, frame_val);
 848
 849         loops = PHY_BUSY_LOOPS;
 850         while (loops != 0) {
 851                 udelay(10);
 852                 frame_val = tr32(MAC_MI_COM);
 853
 854                 if ((frame_val & MI_COM_BUSY) == 0) {
 855                         udelay(5);
 856                         frame_val = tr32(MAC_MI_COM);
 857                         break;
 858                 }
 859                 loops -= 1;
 860         }
 861
 862         ret = -EBUSY;
 863         if (loops != 0) {
 864                 *val = frame_val & MI_COM_DATA_MASK;
 865                 ret = 0;
 866         }
 867
 868         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 869                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 870                 udelay(80);
 871         }
 872
 873         return ret;
 874 }
 875
 876 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 877 {
 878         u32 frame_val;
 879         unsigned int loops;
 880         int ret;
 881
 882         if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
 883             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 884                 return 0;
 885
 886         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 887                 tw32_f(MAC_MI_MODE,
 888                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 889                 udelay(80);
 890         }
 891
 892         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 893                       MI_COM_PHY_ADDR_MASK);
 894         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 895                       MI_COM_REG_ADDR_MASK);
 896         frame_val |= (val & MI_COM_DATA_MASK);
 897         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 898
 899         tw32_f(MAC_MI_COM, frame_val);
 900
 901         loops = PHY_BUSY_LOOPS;
 902         while (loops != 0) {
 903                 udelay(10);
 904                 frame_val = tr32(MAC_MI_COM);
 905                 if ((frame_val & MI_COM_BUSY) == 0) {
 906                         udelay(5);
 907                         frame_val = tr32(MAC_MI_COM);
 908                         break;
 909                 }
 910                 loops -= 1;
 911         }
 912
 913         ret = -EBUSY;
 914         if (loops != 0)
 915                 ret = 0;
 916
 917         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 918                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 919                 udelay(80);
 920         }
 921
 922         return ret;
 923 }
 924
 925 static int tg3_bmcr_reset(struct tg3 *tp)
 926 {
 927         u32 phy_control;
 928         int limit, err;
 929
 930         /* OK, reset it, and poll the BMCR_RESET bit until it
 931          * clears or we time out.
 932          */
 933         phy_control = BMCR_RESET;
 934         err = tg3_writephy(tp, MII_BMCR, phy_control);
 935         if (err != 0)
 936                 return -EBUSY;
 937
 938         limit = 5000;
 939         while (limit--) {
 940                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 941                 if (err != 0)
 942                         return -EBUSY;
 943
 944                 if ((phy_control & BMCR_RESET) == 0) {
 945                         udelay(40);
 946                         break;
 947                 }
 948                 udelay(10);
 949         }
 950         if (limit < 0)
 951                 return -EBUSY;
 952
 953         return 0;
 954 }
 955
 956 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 957 {
 958         struct tg3 *tp = bp->priv;
 959         u32 val;
 960
 961         spin_lock_bh(&tp->lock);
 962
 963         if (tg3_readphy(tp, reg, &val))
 964                 val = -EIO;
 965
 966         spin_unlock_bh(&tp->lock);
 967
 968         return val;
 969 }
 970
 971 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 972 {
 973         struct tg3 *tp = bp->priv;
 974         u32 ret = 0;
 975
 976         spin_lock_bh(&tp->lock);
 977
 978         if (tg3_writephy(tp, reg, val))
 979                 ret = -EIO;
 980
 981         spin_unlock_bh(&tp->lock);
 982
 983         return ret;
 984 }
 985
 986 static int tg3_mdio_reset(struct mii_bus *bp)
 987 {
 988         return 0;
 989 }
 990
 991 static void tg3_mdio_config_5785(struct tg3 *tp)
 992 {
 993         u32 val;
 994         struct phy_device *phydev;
 995
 996         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
 997         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 998         case PHY_ID_BCM50610:
 999         case PHY_ID_BCM50610M:
1000                 val = MAC_PHYCFG2_50610_LED_MODES;
1001                 break;
1002         case PHY_ID_BCMAC131:
1003                 val = MAC_PHYCFG2_AC131_LED_MODES;
1004                 break;
1005         case PHY_ID_RTL8211C:
1006                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1007                 break;
1008         case PHY_ID_RTL8201E:
1009                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1010                 break;
1011         default:
1012                 return;
1013         }
1014
1015         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1016                 tw32(MAC_PHYCFG2, val);
1017
1018                 val = tr32(MAC_PHYCFG1);
1019                 val &= ~(MAC_PHYCFG1_RGMII_INT |
1020                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1021                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1022                 tw32(MAC_PHYCFG1, val);
1023
1024                 return;
1025         }
1026
1027         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
1028                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1029                        MAC_PHYCFG2_FMODE_MASK_MASK |
1030                        MAC_PHYCFG2_GMODE_MASK_MASK |
1031                        MAC_PHYCFG2_ACT_MASK_MASK   |
1032                        MAC_PHYCFG2_QUAL_MASK_MASK |
1033                        MAC_PHYCFG2_INBAND_ENABLE;
1034
1035         tw32(MAC_PHYCFG2, val);
1036
1037         val = tr32(MAC_PHYCFG1);
1038         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1039                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1040         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1041                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1042                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1043                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1044                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1045         }
1046         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1047                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1048         tw32(MAC_PHYCFG1, val);
1049
1050         val = tr32(MAC_EXT_RGMII_MODE);
1051         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1052                  MAC_RGMII_MODE_RX_QUALITY |
1053                  MAC_RGMII_MODE_RX_ACTIVITY |
1054                  MAC_RGMII_MODE_RX_ENG_DET |
1055                  MAC_RGMII_MODE_TX_ENABLE |
1056                  MAC_RGMII_MODE_TX_LOWPWR |
1057                  MAC_RGMII_MODE_TX_RESET);
1058         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1059                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1060                         val |= MAC_RGMII_MODE_RX_INT_B |
1061                                MAC_RGMII_MODE_RX_QUALITY |
1062                                MAC_RGMII_MODE_RX_ACTIVITY |
1063                                MAC_RGMII_MODE_RX_ENG_DET;
1064                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1065                         val |= MAC_RGMII_MODE_TX_ENABLE |
1066                                MAC_RGMII_MODE_TX_LOWPWR |
1067                                MAC_RGMII_MODE_TX_RESET;
1068         }
1069         tw32(MAC_EXT_RGMII_MODE, val);
1070 }
1071
1072 static void tg3_mdio_start(struct tg3 *tp)
1073 {
1074         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1075         tw32_f(MAC_MI_MODE, tp->mi_mode);
1076         udelay(80);
1077
1078         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1079             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1080                 tg3_mdio_config_5785(tp);
1081 }
1082
1083 static int tg3_mdio_init(struct tg3 *tp)
1084 {
1085         int i;
1086         u32 reg;
1087         struct phy_device *phydev;
1088
1089         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1090             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
1091                 u32 is_serdes;
1092
1093                 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1094
1095                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1096                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1097                 else
1098                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1099                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1100                 if (is_serdes)
1101                         tp->phy_addr += 7;
1102         } else
1103                 tp->phy_addr = TG3_PHY_MII_ADDR;
1104
1105         tg3_mdio_start(tp);
1106
1107         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1108             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1109                 return 0;
1110
1111         tp->mdio_bus = mdiobus_alloc();
1112         if (tp->mdio_bus == NULL)
1113                 return -ENOMEM;
1114
1115         tp->mdio_bus->name     = "tg3 mdio bus";
1116         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1117                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1118         tp->mdio_bus->priv     = tp;
1119         tp->mdio_bus->parent   = &tp->pdev->dev;
1120         tp->mdio_bus->read     = &tg3_mdio_read;
1121         tp->mdio_bus->write    = &tg3_mdio_write;
1122         tp->mdio_bus->reset    = &tg3_mdio_reset;
1123         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1124         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1125
1126         for (i = 0; i < PHY_MAX_ADDR; i++)
1127                 tp->mdio_bus->irq[i] = PHY_POLL;
1128
1129         /* The bus registration will look for all the PHYs on the mdio bus.
1130          * Unfortunately, it does not ensure the PHY is powered up before
1131          * accessing the PHY ID registers.  A chip reset is the
1132          * quickest way to bring the device back to an operational state..
1133          */
1134         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1135                 tg3_bmcr_reset(tp);
1136
1137         i = mdiobus_register(tp->mdio_bus);
1138         if (i) {
1139                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1140                 mdiobus_free(tp->mdio_bus);
1141                 return i;
1142         }
1143
1144         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1145
1146         if (!phydev || !phydev->drv) {
1147                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1148                 mdiobus_unregister(tp->mdio_bus);
1149                 mdiobus_free(tp->mdio_bus);
1150                 return -ENODEV;
1151         }
1152
1153         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1154         case PHY_ID_BCM57780:
1155                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1156                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1157                 break;
1158         case PHY_ID_BCM50610:
1159         case PHY_ID_BCM50610M:
1160                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1161                                      PHY_BRCM_RX_REFCLK_UNUSED |
1162                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1163                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1164                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1165                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1166                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1167                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1168                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1169                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1170                 /* fallthru */
1171         case PHY_ID_RTL8211C:
1172                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1173                 break;
1174         case PHY_ID_RTL8201E:
1175         case PHY_ID_BCMAC131:
1176                 phydev->interface = PHY_INTERFACE_MODE_MII;
1177                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1178                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1179                 break;
1180         }
1181
1182         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1183
1184         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1185                 tg3_mdio_config_5785(tp);
1186
1187         return 0;
1188 }
1189
1190 static void tg3_mdio_fini(struct tg3 *tp)
1191 {
1192         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1193                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1194                 mdiobus_unregister(tp->mdio_bus);
1195                 mdiobus_free(tp->mdio_bus);
1196         }
1197 }
1198
1199 /* tp->lock is held. */
1200 static inline void tg3_generate_fw_event(struct tg3 *tp)
1201 {
1202         u32 val;
1203
1204         val = tr32(GRC_RX_CPU_EVENT);
1205         val |= GRC_RX_CPU_DRIVER_EVENT;
1206         tw32_f(GRC_RX_CPU_EVENT, val);
1207
1208         tp->last_event_jiffies = jiffies;
1209 }
1210
1211 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1212
1213 /* tp->lock is held. */
1214 static void tg3_wait_for_event_ack(struct tg3 *tp)
1215 {
1216         int i;
1217         unsigned int delay_cnt;
1218         long time_remain;
1219
1220         /* If enough time has passed, no wait is necessary. */
1221         time_remain = (long)(tp->last_event_jiffies + 1 +
1222                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1223                       (long)jiffies;
1224         if (time_remain < 0)
1225                 return;
1226
1227         /* Check if we can shorten the wait time. */
1228         delay_cnt = jiffies_to_usecs(time_remain);
1229         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1230                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1231         delay_cnt = (delay_cnt >> 3) + 1;
1232
1233         for (i = 0; i < delay_cnt; i++) {
1234                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1235                         break;
1236                 udelay(8);
1237         }
1238 }
1239
1240 /* tp->lock is held. */
1241 static void tg3_ump_link_report(struct tg3 *tp)
1242 {
1243         u32 reg;
1244         u32 val;
1245
1246         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1247             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1248                 return;
1249
1250         tg3_wait_for_event_ack(tp);
1251
1252         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1253
1254         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1255
1256         val = 0;
1257         if (!tg3_readphy(tp, MII_BMCR, &reg))
1258                 val = reg << 16;
1259         if (!tg3_readphy(tp, MII_BMSR, &reg))
1260                 val |= (reg & 0xffff);
1261         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1262
1263         val = 0;
1264         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1265                 val = reg << 16;
1266         if (!tg3_readphy(tp, MII_LPA, &reg))
1267                 val |= (reg & 0xffff);
1268         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1269
1270         val = 0;
1271         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1272                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1273                         val = reg << 16;
1274                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1275                         val |= (reg & 0xffff);
1276         }
1277         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1278
1279         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1280                 val = reg << 16;
1281         else
1282                 val = 0;
1283         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1284
1285         tg3_generate_fw_event(tp);
1286 }
1287
1288 static void tg3_link_report(struct tg3 *tp)
1289 {
1290         if (!netif_carrier_ok(tp->dev)) {
1291                 netif_info(tp, link, tp->dev, "Link is down\n");
1292                 tg3_ump_link_report(tp);
1293         } else if (netif_msg_link(tp)) {
1294                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1295                             (tp->link_config.active_speed == SPEED_1000 ?
1296                              1000 :
1297                              (tp->link_config.active_speed == SPEED_100 ?
1298                               100 : 10)),
1299                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1300                              "full" : "half"));
1301
1302                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1303                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1304                             "on" : "off",
1305                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1306                             "on" : "off");
1307                 tg3_ump_link_report(tp);
1308         }
1309 }
1310
1311 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1312 {
1313         u16 miireg;
1314
1315         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1316                 miireg = ADVERTISE_PAUSE_CAP;
1317         else if (flow_ctrl & FLOW_CTRL_TX)
1318                 miireg = ADVERTISE_PAUSE_ASYM;
1319         else if (flow_ctrl & FLOW_CTRL_RX)
1320                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1321         else
1322                 miireg = 0;
1323
1324         return miireg;
1325 }
1326
1327 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1328 {
1329         u16 miireg;
1330
1331         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1332                 miireg = ADVERTISE_1000XPAUSE;
1333         else if (flow_ctrl & FLOW_CTRL_TX)
1334                 miireg = ADVERTISE_1000XPSE_ASYM;
1335         else if (flow_ctrl & FLOW_CTRL_RX)
1336                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1337         else
1338                 miireg = 0;
1339
1340         return miireg;
1341 }
1342
1343 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1344 {
1345         u8 cap = 0;
1346
1347         if (lcladv & ADVERTISE_1000XPAUSE) {
1348                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1349                         if (rmtadv & LPA_1000XPAUSE)
1350                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1351                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1352                                 cap = FLOW_CTRL_RX;
1353                 } else {
1354                         if (rmtadv & LPA_1000XPAUSE)
1355                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1356                 }
1357         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1358                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1359                         cap = FLOW_CTRL_TX;
1360         }
1361
1362         return cap;
1363 }
1364
1365 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1366 {
1367         u8 autoneg;
1368         u8 flowctrl = 0;
1369         u32 old_rx_mode = tp->rx_mode;
1370         u32 old_tx_mode = tp->tx_mode;
1371
1372         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1373                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1374         else
1375                 autoneg = tp->link_config.autoneg;
1376
1377         if (autoneg == AUTONEG_ENABLE &&
1378             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1379                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1380                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1381                 else
1382                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1383         } else
1384                 flowctrl = tp->link_config.flowctrl;
1385
1386         tp->link_config.active_flowctrl = flowctrl;
1387
1388         if (flowctrl & FLOW_CTRL_RX)
1389                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1390         else
1391                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1392
1393         if (old_rx_mode != tp->rx_mode)
1394                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1395
1396         if (flowctrl & FLOW_CTRL_TX)
1397                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1398         else
1399                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1400
1401         if (old_tx_mode != tp->tx_mode)
1402                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1403 }
1404
1405 static void tg3_adjust_link(struct net_device *dev)
1406 {
1407         u8 oldflowctrl, linkmesg = 0;
1408         u32 mac_mode, lcl_adv, rmt_adv;
1409         struct tg3 *tp = netdev_priv(dev);
1410         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1411
1412         spin_lock_bh(&tp->lock);
1413
1414         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1415                                     MAC_MODE_HALF_DUPLEX);
1416
1417         oldflowctrl = tp->link_config.active_flowctrl;
1418
1419         if (phydev->link) {
1420                 lcl_adv = 0;
1421                 rmt_adv = 0;
1422
1423                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1424                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1425                 else if (phydev->speed == SPEED_1000 ||
1426                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1427                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1428                 else
1429                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1430
1431                 if (phydev->duplex == DUPLEX_HALF)
1432                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1433                 else {
1434                         lcl_adv = tg3_advert_flowctrl_1000T(
1435                                   tp->link_config.flowctrl);
1436
1437                         if (phydev->pause)
1438                                 rmt_adv = LPA_PAUSE_CAP;
1439                         if (phydev->asym_pause)
1440                                 rmt_adv |= LPA_PAUSE_ASYM;
1441                 }
1442
1443                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1444         } else
1445                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1446
1447         if (mac_mode != tp->mac_mode) {
1448                 tp->mac_mode = mac_mode;
1449                 tw32_f(MAC_MODE, tp->mac_mode);
1450                 udelay(40);
1451         }
1452
1453         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1454                 if (phydev->speed == SPEED_10)
1455                         tw32(MAC_MI_STAT,
1456                              MAC_MI_STAT_10MBPS_MODE |
1457                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1458                 else
1459                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1460         }
1461
1462         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1463                 tw32(MAC_TX_LENGTHS,
1464                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1465                       (6 << TX_LENGTHS_IPG_SHIFT) |
1466                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1467         else
1468                 tw32(MAC_TX_LENGTHS,
1469                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1470                       (6 << TX_LENGTHS_IPG_SHIFT) |
1471                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1472
1473         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1474             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1475             phydev->speed != tp->link_config.active_speed ||
1476             phydev->duplex != tp->link_config.active_duplex ||
1477             oldflowctrl != tp->link_config.active_flowctrl)
1478                 linkmesg = 1;
1479
1480         tp->link_config.active_speed = phydev->speed;
1481         tp->link_config.active_duplex = phydev->duplex;
1482
1483         spin_unlock_bh(&tp->lock);
1484
1485         if (linkmesg)
1486                 tg3_link_report(tp);
1487 }
1488
1489 static int tg3_phy_init(struct tg3 *tp)
1490 {
1491         struct phy_device *phydev;
1492
1493         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1494                 return 0;
1495
1496         /* Bring the PHY back to a known state. */
1497         tg3_bmcr_reset(tp);
1498
1499         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1500
1501         /* Attach the MAC to the PHY. */
1502         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1503                              phydev->dev_flags, phydev->interface);
1504         if (IS_ERR(phydev)) {
1505                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1506                 return PTR_ERR(phydev);
1507         }
1508
1509         /* Mask with MAC supported features. */
1510         switch (phydev->interface) {
1511         case PHY_INTERFACE_MODE_GMII:
1512         case PHY_INTERFACE_MODE_RGMII:
1513                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1514                         phydev->supported &= (PHY_GBIT_FEATURES |
1515                                               SUPPORTED_Pause |
1516                                               SUPPORTED_Asym_Pause);
1517                         break;
1518                 }
1519                 /* fallthru */
1520         case PHY_INTERFACE_MODE_MII:
1521                 phydev->supported &= (PHY_BASIC_FEATURES |
1522                                       SUPPORTED_Pause |
1523                                       SUPPORTED_Asym_Pause);
1524                 break;
1525         default:
1526                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1527                 return -EINVAL;
1528         }
1529
1530         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1531
1532         phydev->advertising = phydev->supported;
1533
1534         return 0;
1535 }
1536
1537 static void tg3_phy_start(struct tg3 *tp)
1538 {
1539         struct phy_device *phydev;
1540
1541         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1542                 return;
1543
1544         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1545
1546         if (tp->link_config.phy_is_low_power) {
1547                 tp->link_config.phy_is_low_power = 0;
1548                 phydev->speed = tp->link_config.orig_speed;
1549                 phydev->duplex = tp->link_config.orig_duplex;
1550                 phydev->autoneg = tp->link_config.orig_autoneg;
1551                 phydev->advertising = tp->link_config.orig_advertising;
1552         }
1553
1554         phy_start(phydev);
1555
1556         phy_start_aneg(phydev);
1557 }
1558
1559 static void tg3_phy_stop(struct tg3 *tp)
1560 {
1561         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1562                 return;
1563
1564         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1565 }
1566
1567 static void tg3_phy_fini(struct tg3 *tp)
1568 {
1569         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1570                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1571                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1572         }
1573 }
1574
1575 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1576 {
1577         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1578         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1579 }
1580
1581 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1582 {
1583         u32 phytest;
1584
1585         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1586                 u32 phy;
1587
1588                 tg3_writephy(tp, MII_TG3_FET_TEST,
1589                              phytest | MII_TG3_FET_SHADOW_EN);
1590                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1591                         if (enable)
1592                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1593                         else
1594                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1595                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1596                 }
1597                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1598         }
1599 }
1600
1601 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1602 {
1603         u32 reg;
1604
1605         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1606             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1607               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1608              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1609                 return;
1610
1611         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1612                 tg3_phy_fet_toggle_apd(tp, enable);
1613                 return;
1614         }
1615
1616         reg = MII_TG3_MISC_SHDW_WREN |
1617               MII_TG3_MISC_SHDW_SCR5_SEL |
1618               MII_TG3_MISC_SHDW_SCR5_LPED |
1619               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1620               MII_TG3_MISC_SHDW_SCR5_SDTL |
1621               MII_TG3_MISC_SHDW_SCR5_C125OE;
1622         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1623                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1624
1625         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1626
1627
1628         reg = MII_TG3_MISC_SHDW_WREN |
1629               MII_TG3_MISC_SHDW_APD_SEL |
1630               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1631         if (enable)
1632                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1633
1634         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1635 }
1636
1637 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1638 {
1639         u32 phy;
1640
1641         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1642             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1643                 return;
1644
1645         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1646                 u32 ephy;
1647
1648                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1649                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1650
1651                         tg3_writephy(tp, MII_TG3_FET_TEST,
1652                                      ephy | MII_TG3_FET_SHADOW_EN);
1653                         if (!tg3_readphy(tp, reg, &phy)) {
1654                                 if (enable)
1655                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1656                                 else
1657                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1658                                 tg3_writephy(tp, reg, phy);
1659                         }
1660                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1661                 }
1662         } else {
1663                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1664                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1665                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1666                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1667                         if (enable)
1668                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1669                         else
1670                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1671                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1672                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1673                 }
1674         }
1675 }
1676
1677 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1678 {
1679         u32 val;
1680
1681         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1682                 return;
1683
1684         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1685             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1686                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1687                              (val | (1 << 15) | (1 << 4)));
1688 }
1689
1690 static void tg3_phy_apply_otp(struct tg3 *tp)
1691 {
1692         u32 otp, phy;
1693
1694         if (!tp->phy_otp)
1695                 return;
1696
1697         otp = tp->phy_otp;
1698
1699         /* Enable SM_DSP clock and tx 6dB coding. */
1700         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1701               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1702               MII_TG3_AUXCTL_ACTL_TX_6DB;
1703         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1704
1705         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1706         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1707         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1708
1709         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1710               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1711         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1712
1713         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1714         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1715         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1716
1717         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1718         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1719
1720         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1721         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1722
1723         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1724               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1725         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1726
1727         /* Turn off SM_DSP clock. */
1728         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1729               MII_TG3_AUXCTL_ACTL_TX_6DB;
1730         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1731 }
1732
1733 static int tg3_wait_macro_done(struct tg3 *tp)
1734 {
1735         int limit = 100;
1736
1737         while (limit--) {
1738                 u32 tmp32;
1739
1740                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1741                         if ((tmp32 & 0x1000) == 0)
1742                                 break;
1743                 }
1744         }
1745         if (limit < 0)
1746                 return -EBUSY;
1747
1748         return 0;
1749 }
1750
1751 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1752 {
1753         static const u32 test_pat[4][6] = {
1754         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1755         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1756         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1757         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1758         };
1759         int chan;
1760
1761         for (chan = 0; chan < 4; chan++) {
1762                 int i;
1763
1764                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1765                              (chan * 0x2000) | 0x0200);
1766                 tg3_writephy(tp, 0x16, 0x0002);
1767
1768                 for (i = 0; i < 6; i++)
1769                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1770                                      test_pat[chan][i]);
1771
1772                 tg3_writephy(tp, 0x16, 0x0202);
1773                 if (tg3_wait_macro_done(tp)) {
1774                         *resetp = 1;
1775                         return -EBUSY;
1776                 }
1777
1778                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1779                              (chan * 0x2000) | 0x0200);
1780                 tg3_writephy(tp, 0x16, 0x0082);
1781                 if (tg3_wait_macro_done(tp)) {
1782                         *resetp = 1;
1783                         return -EBUSY;
1784                 }
1785
1786                 tg3_writephy(tp, 0x16, 0x0802);
1787                 if (tg3_wait_macro_done(tp)) {
1788                         *resetp = 1;
1789                         return -EBUSY;
1790                 }
1791
1792                 for (i = 0; i < 6; i += 2) {
1793                         u32 low, high;
1794
1795                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1796                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1797                             tg3_wait_macro_done(tp)) {
1798                                 *resetp = 1;
1799                                 return -EBUSY;
1800                         }
1801                         low &= 0x7fff;
1802                         high &= 0x000f;
1803                         if (low != test_pat[chan][i] ||
1804                             high != test_pat[chan][i+1]) {
1805                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1806                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1807                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1808
1809                                 return -EBUSY;
1810                         }
1811                 }
1812         }
1813
1814         return 0;
1815 }
1816
1817 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1818 {
1819         int chan;
1820
1821         for (chan = 0; chan < 4; chan++) {
1822                 int i;
1823
1824                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1825                              (chan * 0x2000) | 0x0200);
1826                 tg3_writephy(tp, 0x16, 0x0002);
1827                 for (i = 0; i < 6; i++)
1828                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1829                 tg3_writephy(tp, 0x16, 0x0202);
1830                 if (tg3_wait_macro_done(tp))
1831                         return -EBUSY;
1832         }
1833
1834         return 0;
1835 }
1836
1837 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1838 {
1839         u32 reg32, phy9_orig;
1840         int retries, do_phy_reset, err;
1841
1842         retries = 10;
1843         do_phy_reset = 1;
1844         do {
1845                 if (do_phy_reset) {
1846                         err = tg3_bmcr_reset(tp);
1847                         if (err)
1848                                 return err;
1849                         do_phy_reset = 0;
1850                 }
1851
1852                 /* Disable transmitter and interrupt.  */
1853                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1854                         continue;
1855
1856                 reg32 |= 0x3000;
1857                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1858
1859                 /* Set full-duplex, 1000 mbps.  */
1860                 tg3_writephy(tp, MII_BMCR,
1861                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1862
1863                 /* Set to master mode.  */
1864                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1865                         continue;
1866
1867                 tg3_writephy(tp, MII_TG3_CTRL,
1868                              (MII_TG3_CTRL_AS_MASTER |
1869                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1870
1871                 /* Enable SM_DSP_CLOCK and 6dB.  */
1872                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1873
1874                 /* Block the PHY control access.  */
1875                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1876                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1877
1878                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1879                 if (!err)
1880                         break;
1881         } while (--retries);
1882
1883         err = tg3_phy_reset_chanpat(tp);
1884         if (err)
1885                 return err;
1886
1887         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1888         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1889
1890         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1891         tg3_writephy(tp, 0x16, 0x0000);
1892
1893         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1894             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1895                 /* Set Extended packet length bit for jumbo frames */
1896                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1897         } else {
1898                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1899         }
1900
1901         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1902
1903         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1904                 reg32 &= ~0x3000;
1905                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1906         } else if (!err)
1907                 err = -EBUSY;
1908
1909         return err;
1910 }
1911
1912 /* This will reset the tigon3 PHY if there is no valid
1913  * link unless the FORCE argument is non-zero.
1914  */
1915 static int tg3_phy_reset(struct tg3 *tp)
1916 {
1917         u32 cpmuctrl;
1918         u32 phy_status;
1919         int err;
1920
1921         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1922                 u32 val;
1923
1924                 val = tr32(GRC_MISC_CFG);
1925                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1926                 udelay(40);
1927         }
1928         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1929         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1930         if (err != 0)
1931                 return -EBUSY;
1932
1933         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1934                 netif_carrier_off(tp->dev);
1935                 tg3_link_report(tp);
1936         }
1937
1938         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1939             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1940             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1941                 err = tg3_phy_reset_5703_4_5(tp);
1942                 if (err)
1943                         return err;
1944                 goto out;
1945         }
1946
1947         cpmuctrl = 0;
1948         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1949             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1950                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1951                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1952                         tw32(TG3_CPMU_CTRL,
1953                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1954         }
1955
1956         err = tg3_bmcr_reset(tp);
1957         if (err)
1958                 return err;
1959
1960         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1961                 u32 phy;
1962
1963                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1964                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1965
1966                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1967         }
1968
1969         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1970             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1971                 u32 val;
1972
1973                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1974                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1975                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1976                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1977                         udelay(40);
1978                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1979                 }
1980         }
1981
1982         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1983              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1984             (tp->tg3_flags2 & TG3_FLG2_MII_SERDES))
1985                 return 0;
1986
1987         tg3_phy_apply_otp(tp);
1988
1989         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1990                 tg3_phy_toggle_apd(tp, true);
1991         else
1992                 tg3_phy_toggle_apd(tp, false);
1993
1994 out:
1995         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1996                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1997                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1998                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1999                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2000                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
2001                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2002         }
2003         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
2004                 tg3_writephy(tp, 0x1c, 0x8d68);
2005                 tg3_writephy(tp, 0x1c, 0x8d68);
2006         }
2007         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
2008                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2009                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2010                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
2011                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2012                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
2013                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
2014                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
2015                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2016         } else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
2017                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2018                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2019                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
2020                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2021                         tg3_writephy(tp, MII_TG3_TEST1,
2022                                      MII_TG3_TEST1_TRIM_EN | 0x4);
2023                 } else
2024                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2025                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2026         }
2027         /* Set Extended packet length bit (bit 14) on all chips that */
2028         /* support jumbo frames */
2029         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2030                 /* Cannot do read-modify-write on 5401 */
2031                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2032         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2033                 u32 phy_reg;
2034
2035                 /* Set bit 14 with read-modify-write to preserve other bits */
2036                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2037                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
2038                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
2039         }
2040
2041         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2042          * jumbo frames transmission.
2043          */
2044         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2045                 u32 phy_reg;
2046
2047                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
2048                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2049                                      phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2050         }
2051
2052         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2053                 /* adjust output voltage */
2054                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2055         }
2056
2057         tg3_phy_toggle_automdix(tp, 1);
2058         tg3_phy_set_wirespeed(tp);
2059         return 0;
2060 }
2061
2062 static void tg3_frob_aux_power(struct tg3 *tp)
2063 {
2064         struct tg3 *tp_peer = tp;
2065
2066         /* The GPIOs do something completely different on 57765. */
2067         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2068             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2069             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2070                 return;
2071
2072         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2073             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2074             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2075                 struct net_device *dev_peer;
2076
2077                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2078                 /* remove_one() may have been run on the peer. */
2079                 if (!dev_peer)
2080                         tp_peer = tp;
2081                 else
2082                         tp_peer = netdev_priv(dev_peer);
2083         }
2084
2085         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2086             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2087             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2088             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2089                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2090                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2091                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2092                                     (GRC_LCLCTRL_GPIO_OE0 |
2093                                      GRC_LCLCTRL_GPIO_OE1 |
2094                                      GRC_LCLCTRL_GPIO_OE2 |
2095                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2096                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2097                                     100);
2098                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2099                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2100                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2101                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2102                                              GRC_LCLCTRL_GPIO_OE1 |
2103                                              GRC_LCLCTRL_GPIO_OE2 |
2104                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2105                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2106                                              tp->grc_local_ctrl;
2107                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2108
2109                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2110                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2111
2112                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2113                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2114                 } else {
2115                         u32 no_gpio2;
2116                         u32 grc_local_ctrl = 0;
2117
2118                         if (tp_peer != tp &&
2119                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2120                                 return;
2121
2122                         /* Workaround to prevent overdrawing Amps. */
2123                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2124                             ASIC_REV_5714) {
2125                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2126                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2127                                             grc_local_ctrl, 100);
2128                         }
2129
2130                         /* On 5753 and variants, GPIO2 cannot be used. */
2131                         no_gpio2 = tp->nic_sram_data_cfg &
2132                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2133
2134                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2135                                          GRC_LCLCTRL_GPIO_OE1 |
2136                                          GRC_LCLCTRL_GPIO_OE2 |
2137                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2138                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2139                         if (no_gpio2) {
2140                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2141                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2142                         }
2143                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2144                                                     grc_local_ctrl, 100);
2145
2146                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2147
2148                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2149                                                     grc_local_ctrl, 100);
2150
2151                         if (!no_gpio2) {
2152                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2153                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2154                                             grc_local_ctrl, 100);
2155                         }
2156                 }
2157         } else {
2158                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2159                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2160                         if (tp_peer != tp &&
2161                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2162                                 return;
2163
2164                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2165                                     (GRC_LCLCTRL_GPIO_OE1 |
2166                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2167
2168                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2169                                     GRC_LCLCTRL_GPIO_OE1, 100);
2170
2171                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2172                                     (GRC_LCLCTRL_GPIO_OE1 |
2173                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2174                 }
2175         }
2176 }
2177
2178 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2179 {
2180         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2181                 return 1;
2182         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2183                 if (speed != SPEED_10)
2184                         return 1;
2185         } else if (speed == SPEED_10)
2186                 return 1;
2187
2188         return 0;
2189 }
2190
2191 static int tg3_setup_phy(struct tg3 *, int);
2192
2193 #define RESET_KIND_SHUTDOWN     0
2194 #define RESET_KIND_INIT         1
2195 #define RESET_KIND_SUSPEND      2
2196
2197 static void tg3_write_sig_post_reset(struct tg3 *, int);
2198 static int tg3_halt_cpu(struct tg3 *, u32);
2199
2200 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2201 {
2202         u32 val;
2203
2204         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2205                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2206                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2207                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2208
2209                         sg_dig_ctrl |=
2210                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2211                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2212                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2213                 }
2214                 return;
2215         }
2216
2217         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2218                 tg3_bmcr_reset(tp);
2219                 val = tr32(GRC_MISC_CFG);
2220                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2221                 udelay(40);
2222                 return;
2223         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2224                 u32 phytest;
2225                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2226                         u32 phy;
2227
2228                         tg3_writephy(tp, MII_ADVERTISE, 0);
2229                         tg3_writephy(tp, MII_BMCR,
2230                                      BMCR_ANENABLE | BMCR_ANRESTART);
2231
2232                         tg3_writephy(tp, MII_TG3_FET_TEST,
2233                                      phytest | MII_TG3_FET_SHADOW_EN);
2234                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2235                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2236                                 tg3_writephy(tp,
2237                                              MII_TG3_FET_SHDW_AUXMODE4,
2238                                              phy);
2239                         }
2240                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2241                 }
2242                 return;
2243         } else if (do_low_power) {
2244                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2245                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2246
2247                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2248                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2249                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2250                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2251                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2252         }
2253
2254         /* The PHY should not be powered down on some chips because
2255          * of bugs.
2256          */
2257         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2258             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2259             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2260              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2261                 return;
2262
2263         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2264             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2265                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2266                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2267                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2268                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2269         }
2270
2271         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2272 }
2273
2274 /* tp->lock is held. */
2275 static int tg3_nvram_lock(struct tg3 *tp)
2276 {
2277         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2278                 int i;
2279
2280                 if (tp->nvram_lock_cnt == 0) {
2281                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2282                         for (i = 0; i < 8000; i++) {
2283                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2284                                         break;
2285                                 udelay(20);
2286                         }
2287                         if (i == 8000) {
2288                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2289                                 return -ENODEV;
2290                         }
2291                 }
2292                 tp->nvram_lock_cnt++;
2293         }
2294         return 0;
2295 }
2296
2297 /* tp->lock is held. */
2298 static void tg3_nvram_unlock(struct tg3 *tp)
2299 {
2300         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2301                 if (tp->nvram_lock_cnt > 0)
2302                         tp->nvram_lock_cnt--;
2303                 if (tp->nvram_lock_cnt == 0)
2304                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2305         }
2306 }
2307
2308 /* tp->lock is held. */
2309 static void tg3_enable_nvram_access(struct tg3 *tp)
2310 {
2311         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2312             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2313                 u32 nvaccess = tr32(NVRAM_ACCESS);
2314
2315                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2316         }
2317 }
2318
2319 /* tp->lock is held. */
2320 static void tg3_disable_nvram_access(struct tg3 *tp)
2321 {
2322         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2323             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2324                 u32 nvaccess = tr32(NVRAM_ACCESS);
2325
2326                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2327         }
2328 }
2329
2330 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2331                                         u32 offset, u32 *val)
2332 {
2333         u32 tmp;
2334         int i;
2335
2336         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2337                 return -EINVAL;
2338
2339         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2340                                         EEPROM_ADDR_DEVID_MASK |
2341                                         EEPROM_ADDR_READ);
2342         tw32(GRC_EEPROM_ADDR,
2343              tmp |
2344              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2345              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2346               EEPROM_ADDR_ADDR_MASK) |
2347              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2348
2349         for (i = 0; i < 1000; i++) {
2350                 tmp = tr32(GRC_EEPROM_ADDR);
2351
2352                 if (tmp & EEPROM_ADDR_COMPLETE)
2353                         break;
2354                 msleep(1);
2355         }
2356         if (!(tmp & EEPROM_ADDR_COMPLETE))
2357                 return -EBUSY;
2358
2359         tmp = tr32(GRC_EEPROM_DATA);
2360
2361         /*
2362          * The data will always be opposite the native endian
2363          * format.  Perform a blind byteswap to compensate.
2364          */
2365         *val = swab32(tmp);
2366
2367         return 0;
2368 }
2369
2370 #define NVRAM_CMD_TIMEOUT 10000
2371
2372 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2373 {
2374         int i;
2375
2376         tw32(NVRAM_CMD, nvram_cmd);
2377         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2378                 udelay(10);
2379                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2380                         udelay(10);
2381                         break;
2382                 }
2383         }
2384
2385         if (i == NVRAM_CMD_TIMEOUT)
2386                 return -EBUSY;
2387
2388         return 0;
2389 }
2390
2391 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2392 {
2393         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2394             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2395             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2396            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2397             (tp->nvram_jedecnum == JEDEC_ATMEL))
2398
2399                 addr = ((addr / tp->nvram_pagesize) <<
2400                         ATMEL_AT45DB0X1B_PAGE_POS) +
2401                        (addr % tp->nvram_pagesize);
2402
2403         return addr;
2404 }
2405
2406 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2407 {
2408         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2409             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2410             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2411            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2412             (tp->nvram_jedecnum == JEDEC_ATMEL))
2413
2414                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2415                         tp->nvram_pagesize) +
2416                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2417
2418         return addr;
2419 }
2420
2421 /* NOTE: Data read in from NVRAM is byteswapped according to
2422  * the byteswapping settings for all other register accesses.
2423  * tg3 devices are BE devices, so on a BE machine, the data
2424  * returned will be exactly as it is seen in NVRAM.  On a LE
2425  * machine, the 32-bit value will be byteswapped.
2426  */
2427 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2428 {
2429         int ret;
2430
2431         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2432                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2433
2434         offset = tg3_nvram_phys_addr(tp, offset);
2435
2436         if (offset > NVRAM_ADDR_MSK)
2437                 return -EINVAL;
2438
2439         ret = tg3_nvram_lock(tp);
2440         if (ret)
2441                 return ret;
2442
2443         tg3_enable_nvram_access(tp);
2444
2445         tw32(NVRAM_ADDR, offset);
2446         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2447                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2448
2449         if (ret == 0)
2450                 *val = tr32(NVRAM_RDDATA);
2451
2452         tg3_disable_nvram_access(tp);
2453
2454         tg3_nvram_unlock(tp);
2455
2456         return ret;
2457 }
2458
2459 /* Ensures NVRAM data is in bytestream format. */
2460 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2461 {
2462         u32 v;
2463         int res = tg3_nvram_read(tp, offset, &v);
2464         if (!res)
2465                 *val = cpu_to_be32(v);
2466         return res;
2467 }
2468
2469 /* tp->lock is held. */
2470 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2471 {
2472         u32 addr_high, addr_low;
2473         int i;
2474
2475         addr_high = ((tp->dev->dev_addr[0] << 8) |
2476                      tp->dev->dev_addr[1]);
2477         addr_low = ((tp->dev->dev_addr[2] << 24) |
2478                     (tp->dev->dev_addr[3] << 16) |
2479                     (tp->dev->dev_addr[4] <<  8) |
2480                     (tp->dev->dev_addr[5] <<  0));
2481         for (i = 0; i < 4; i++) {
2482                 if (i == 1 && skip_mac_1)
2483                         continue;
2484                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2485                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2486         }
2487
2488         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2489             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2490                 for (i = 0; i < 12; i++) {
2491                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2492                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2493                 }
2494         }
2495
2496         addr_high = (tp->dev->dev_addr[0] +
2497                      tp->dev->dev_addr[1] +
2498                      tp->dev->dev_addr[2] +
2499                      tp->dev->dev_addr[3] +
2500                      tp->dev->dev_addr[4] +
2501                      tp->dev->dev_addr[5]) &
2502                 TX_BACKOFF_SEED_MASK;
2503         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2504 }
2505
2506 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2507 {
2508         u32 misc_host_ctrl;
2509         bool device_should_wake, do_low_power;
2510
2511         /* Make sure register accesses (indirect or otherwise)
2512          * will function correctly.
2513          */
2514         pci_write_config_dword(tp->pdev,
2515                                TG3PCI_MISC_HOST_CTRL,
2516                                tp->misc_host_ctrl);
2517
2518         switch (state) {
2519         case PCI_D0:
2520                 pci_enable_wake(tp->pdev, state, false);
2521                 pci_set_power_state(tp->pdev, PCI_D0);
2522
2523                 /* Switch out of Vaux if it is a NIC */
2524                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2525                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2526
2527                 return 0;
2528
2529         case PCI_D1:
2530         case PCI_D2:
2531         case PCI_D3hot:
2532                 break;
2533
2534         default:
2535                 netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
2536                            state);
2537                 return -EINVAL;
2538         }
2539
2540         /* Restore the CLKREQ setting. */
2541         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2542                 u16 lnkctl;
2543
2544                 pci_read_config_word(tp->pdev,
2545                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2546                                      &lnkctl);
2547                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2548                 pci_write_config_word(tp->pdev,
2549                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2550                                       lnkctl);
2551         }
2552
2553         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2554         tw32(TG3PCI_MISC_HOST_CTRL,
2555              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2556
2557         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2558                              device_may_wakeup(&tp->pdev->dev) &&
2559                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2560
2561         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2562                 do_low_power = false;
2563                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2564                     !tp->link_config.phy_is_low_power) {
2565                         struct phy_device *phydev;
2566                         u32 phyid, advertising;
2567
2568                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2569
2570                         tp->link_config.phy_is_low_power = 1;
2571
2572                         tp->link_config.orig_speed = phydev->speed;
2573                         tp->link_config.orig_duplex = phydev->duplex;
2574                         tp->link_config.orig_autoneg = phydev->autoneg;
2575                         tp->link_config.orig_advertising = phydev->advertising;
2576
2577                         advertising = ADVERTISED_TP |
2578                                       ADVERTISED_Pause |
2579                                       ADVERTISED_Autoneg |
2580                                       ADVERTISED_10baseT_Half;
2581
2582                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2583                             device_should_wake) {
2584                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2585                                         advertising |=
2586                                                 ADVERTISED_100baseT_Half |
2587                                                 ADVERTISED_100baseT_Full |
2588                                                 ADVERTISED_10baseT_Full;
2589                                 else
2590                                         advertising |= ADVERTISED_10baseT_Full;
2591                         }
2592
2593                         phydev->advertising = advertising;
2594
2595                         phy_start_aneg(phydev);
2596
2597                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2598                         if (phyid != PHY_ID_BCMAC131) {
2599                                 phyid &= PHY_BCM_OUI_MASK;
2600                                 if (phyid == PHY_BCM_OUI_1 ||
2601                                     phyid == PHY_BCM_OUI_2 ||
2602                                     phyid == PHY_BCM_OUI_3)
2603                                         do_low_power = true;
2604                         }
2605                 }
2606         } else {
2607                 do_low_power = true;
2608
2609                 if (tp->link_config.phy_is_low_power == 0) {
2610                         tp->link_config.phy_is_low_power = 1;
2611                         tp->link_config.orig_speed = tp->link_config.speed;
2612                         tp->link_config.orig_duplex = tp->link_config.duplex;
2613                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2614                 }
2615
2616                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2617                         tp->link_config.speed = SPEED_10;
2618                         tp->link_config.duplex = DUPLEX_HALF;
2619                         tp->link_config.autoneg = AUTONEG_ENABLE;
2620                         tg3_setup_phy(tp, 0);
2621                 }
2622         }
2623
2624         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2625                 u32 val;
2626
2627                 val = tr32(GRC_VCPU_EXT_CTRL);
2628                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2629         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2630                 int i;
2631                 u32 val;
2632
2633                 for (i = 0; i < 200; i++) {
2634                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2635                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2636                                 break;
2637                         msleep(1);
2638                 }
2639         }
2640         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2641                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2642                                                      WOL_DRV_STATE_SHUTDOWN |
2643                                                      WOL_DRV_WOL |
2644                                                      WOL_SET_MAGIC_PKT);
2645
2646         if (device_should_wake) {
2647                 u32 mac_mode;
2648
2649                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2650                         if (do_low_power) {
2651                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2652                                 udelay(40);
2653                         }
2654
2655                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2656                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2657                         else
2658                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2659
2660                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2661                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2662                             ASIC_REV_5700) {
2663                                 u32 speed = (tp->tg3_flags &
2664                                              TG3_FLAG_WOL_SPEED_100MB) ?
2665                                              SPEED_100 : SPEED_10;
2666                                 if (tg3_5700_link_polarity(tp, speed))
2667                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2668                                 else
2669                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2670                         }
2671                 } else {
2672                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2673                 }
2674
2675                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2676                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2677
2678                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2679                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2680                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2681                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2682                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2683                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2684
2685                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2686                         mac_mode |= tp->mac_mode &
2687                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2688                         if (mac_mode & MAC_MODE_APE_TX_EN)
2689                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2690                 }
2691
2692                 tw32_f(MAC_MODE, mac_mode);
2693                 udelay(100);
2694
2695                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2696                 udelay(10);
2697         }
2698
2699         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2700             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2701              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2702                 u32 base_val;
2703
2704                 base_val = tp->pci_clock_ctrl;
2705                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2706                              CLOCK_CTRL_TXCLK_DISABLE);
2707
2708                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2709                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2710         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2711                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2712                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2713                 /* do nothing */
2714         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2715                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2716                 u32 newbits1, newbits2;
2717
2718                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2719                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2720                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2721                                     CLOCK_CTRL_TXCLK_DISABLE |
2722                                     CLOCK_CTRL_ALTCLK);
2723                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2724                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2725                         newbits1 = CLOCK_CTRL_625_CORE;
2726                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2727                 } else {
2728                         newbits1 = CLOCK_CTRL_ALTCLK;
2729                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2730                 }
2731
2732                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2733                             40);
2734
2735                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2736                             40);
2737
2738                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2739                         u32 newbits3;
2740
2741                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2742                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2743                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2744                                             CLOCK_CTRL_TXCLK_DISABLE |
2745                                             CLOCK_CTRL_44MHZ_CORE);
2746                         } else {
2747                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2748                         }
2749
2750                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2751                                     tp->pci_clock_ctrl | newbits3, 40);
2752                 }
2753         }
2754
2755         if (!(device_should_wake) &&
2756             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2757                 tg3_power_down_phy(tp, do_low_power);
2758
2759         tg3_frob_aux_power(tp);
2760
2761         /* Workaround for unstable PLL clock */
2762         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2763             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2764                 u32 val = tr32(0x7d00);
2765
2766                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2767                 tw32(0x7d00, val);
2768                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2769                         int err;
2770
2771                         err = tg3_nvram_lock(tp);
2772                         tg3_halt_cpu(tp, RX_CPU_BASE);
2773                         if (!err)
2774                                 tg3_nvram_unlock(tp);
2775                 }
2776         }
2777
2778         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2779
2780         if (device_should_wake)
2781                 pci_enable_wake(tp->pdev, state, true);
2782
2783         /* Finally, set the new power state. */
2784         pci_set_power_state(tp->pdev, state);
2785
2786         return 0;
2787 }
2788
2789 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2790 {
2791         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2792         case MII_TG3_AUX_STAT_10HALF:
2793                 *speed = SPEED_10;
2794                 *duplex = DUPLEX_HALF;
2795                 break;
2796
2797         case MII_TG3_AUX_STAT_10FULL:
2798                 *speed = SPEED_10;
2799                 *duplex = DUPLEX_FULL;
2800                 break;
2801
2802         case MII_TG3_AUX_STAT_100HALF:
2803                 *speed = SPEED_100;
2804                 *duplex = DUPLEX_HALF;
2805                 break;
2806
2807         case MII_TG3_AUX_STAT_100FULL:
2808                 *speed = SPEED_100;
2809                 *duplex = DUPLEX_FULL;
2810                 break;
2811
2812         case MII_TG3_AUX_STAT_1000HALF:
2813                 *speed = SPEED_1000;
2814                 *duplex = DUPLEX_HALF;
2815                 break;
2816
2817         case MII_TG3_AUX_STAT_1000FULL:
2818                 *speed = SPEED_1000;
2819                 *duplex = DUPLEX_FULL;
2820                 break;
2821
2822         default:
2823                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2824                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2825                                  SPEED_10;
2826                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2827                                   DUPLEX_HALF;
2828                         break;
2829                 }
2830                 *speed = SPEED_INVALID;
2831                 *duplex = DUPLEX_INVALID;
2832                 break;
2833         }
2834 }
2835
2836 static void tg3_phy_copper_begin(struct tg3 *tp)
2837 {
2838         u32 new_adv;
2839         int i;
2840
2841         if (tp->link_config.phy_is_low_power) {
2842                 /* Entering low power mode.  Disable gigabit and
2843                  * 100baseT advertisements.
2844                  */
2845                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2846
2847                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2848                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2849                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2850                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2851
2852                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2853         } else if (tp->link_config.speed == SPEED_INVALID) {
2854                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2855                         tp->link_config.advertising &=
2856                                 ~(ADVERTISED_1000baseT_Half |
2857                                   ADVERTISED_1000baseT_Full);
2858
2859                 new_adv = ADVERTISE_CSMA;
2860                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2861                         new_adv |= ADVERTISE_10HALF;
2862                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2863                         new_adv |= ADVERTISE_10FULL;
2864                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2865                         new_adv |= ADVERTISE_100HALF;
2866                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2867                         new_adv |= ADVERTISE_100FULL;
2868
2869                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2870
2871                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2872
2873                 if (tp->link_config.advertising &
2874                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2875                         new_adv = 0;
2876                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2877                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2878                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2879                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2880                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2881                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2882                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2883                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2884                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2885                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2886                 } else {
2887                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2888                 }
2889         } else {
2890                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2891                 new_adv |= ADVERTISE_CSMA;
2892
2893                 /* Asking for a specific link mode. */
2894                 if (tp->link_config.speed == SPEED_1000) {
2895                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2896
2897                         if (tp->link_config.duplex == DUPLEX_FULL)
2898                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2899                         else
2900                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2901                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2902                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2903                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2904                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2905                 } else {
2906                         if (tp->link_config.speed == SPEED_100) {
2907                                 if (tp->link_config.duplex == DUPLEX_FULL)
2908                                         new_adv |= ADVERTISE_100FULL;
2909                                 else
2910                                         new_adv |= ADVERTISE_100HALF;
2911                         } else {
2912                                 if (tp->link_config.duplex == DUPLEX_FULL)
2913                                         new_adv |= ADVERTISE_10FULL;
2914                                 else
2915                                         new_adv |= ADVERTISE_10HALF;
2916                         }
2917                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2918
2919                         new_adv = 0;
2920                 }
2921
2922                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2923         }
2924
2925         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2926             tp->link_config.speed != SPEED_INVALID) {
2927                 u32 bmcr, orig_bmcr;
2928
2929                 tp->link_config.active_speed = tp->link_config.speed;
2930                 tp->link_config.active_duplex = tp->link_config.duplex;
2931
2932                 bmcr = 0;
2933                 switch (tp->link_config.speed) {
2934                 default:
2935                 case SPEED_10:
2936                         break;
2937
2938                 case SPEED_100:
2939                         bmcr |= BMCR_SPEED100;
2940                         break;
2941
2942                 case SPEED_1000:
2943                         bmcr |= TG3_BMCR_SPEED1000;
2944                         break;
2945                 }
2946
2947                 if (tp->link_config.duplex == DUPLEX_FULL)
2948                         bmcr |= BMCR_FULLDPLX;
2949
2950                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2951                     (bmcr != orig_bmcr)) {
2952                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2953                         for (i = 0; i < 1500; i++) {
2954                                 u32 tmp;
2955
2956                                 udelay(10);
2957                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2958                                     tg3_readphy(tp, MII_BMSR, &tmp))
2959                                         continue;
2960                                 if (!(tmp & BMSR_LSTATUS)) {
2961                                         udelay(40);
2962                                         break;
2963                                 }
2964                         }
2965                         tg3_writephy(tp, MII_BMCR, bmcr);
2966                         udelay(40);
2967                 }
2968         } else {
2969                 tg3_writephy(tp, MII_BMCR,
2970                              BMCR_ANENABLE | BMCR_ANRESTART);
2971         }
2972 }
2973
2974 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2975 {
2976         int err;
2977
2978         /* Turn off tap power management. */
2979         /* Set Extended packet length bit */
2980         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2981
2982         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2983         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2984
2985         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2986         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2987
2988         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2989         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2990
2991         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2992         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2993
2994         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2995         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2996
2997         udelay(40);
2998
2999         return err;
3000 }
3001
3002 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
3003 {
3004         u32 adv_reg, all_mask = 0;
3005
3006         if (mask & ADVERTISED_10baseT_Half)
3007                 all_mask |= ADVERTISE_10HALF;
3008         if (mask & ADVERTISED_10baseT_Full)
3009                 all_mask |= ADVERTISE_10FULL;
3010         if (mask & ADVERTISED_100baseT_Half)
3011                 all_mask |= ADVERTISE_100HALF;
3012         if (mask & ADVERTISED_100baseT_Full)
3013                 all_mask |= ADVERTISE_100FULL;
3014
3015         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3016                 return 0;
3017
3018         if ((adv_reg & all_mask) != all_mask)
3019                 return 0;
3020         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
3021                 u32 tg3_ctrl;
3022
3023                 all_mask = 0;
3024                 if (mask & ADVERTISED_1000baseT_Half)
3025                         all_mask |= ADVERTISE_1000HALF;
3026                 if (mask & ADVERTISED_1000baseT_Full)
3027                         all_mask |= ADVERTISE_1000FULL;
3028
3029                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3030                         return 0;
3031
3032                 if ((tg3_ctrl & all_mask) != all_mask)
3033                         return 0;
3034         }
3035         return 1;
3036 }
3037
3038 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3039 {
3040         u32 curadv, reqadv;
3041
3042         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3043                 return 1;
3044
3045         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3046         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3047
3048         if (tp->link_config.active_duplex == DUPLEX_FULL) {
3049                 if (curadv != reqadv)
3050                         return 0;
3051
3052                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3053                         tg3_readphy(tp, MII_LPA, rmtadv);
3054         } else {
3055                 /* Reprogram the advertisement register, even if it
3056                  * does not affect the current link.  If the link
3057                  * gets renegotiated in the future, we can save an
3058                  * additional renegotiation cycle by advertising
3059                  * it correctly in the first place.
3060                  */
3061                 if (curadv != reqadv) {
3062                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3063                                      ADVERTISE_PAUSE_ASYM);
3064                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3065                 }
3066         }
3067
3068         return 1;
3069 }
3070
3071 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3072 {
3073         int current_link_up;
3074         u32 bmsr, dummy;
3075         u32 lcl_adv, rmt_adv;
3076         u16 current_speed;
3077         u8 current_duplex;
3078         int i, err;
3079
3080         tw32(MAC_EVENT, 0);
3081
3082         tw32_f(MAC_STATUS,
3083              (MAC_STATUS_SYNC_CHANGED |
3084               MAC_STATUS_CFG_CHANGED |
3085               MAC_STATUS_MI_COMPLETION |
3086               MAC_STATUS_LNKSTATE_CHANGED));
3087         udelay(40);
3088
3089         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3090                 tw32_f(MAC_MI_MODE,
3091                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3092                 udelay(80);
3093         }
3094
3095         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3096
3097         /* Some third-party PHYs need to be reset on link going
3098          * down.
3099          */
3100         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3101              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3102              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3103             netif_carrier_ok(tp->dev)) {
3104                 tg3_readphy(tp, MII_BMSR, &bmsr);
3105                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3106                     !(bmsr & BMSR_LSTATUS))
3107                         force_reset = 1;
3108         }
3109         if (force_reset)
3110                 tg3_phy_reset(tp);
3111
3112         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3113                 tg3_readphy(tp, MII_BMSR, &bmsr);
3114                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3115                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3116                         bmsr = 0;
3117
3118                 if (!(bmsr & BMSR_LSTATUS)) {
3119                         err = tg3_init_5401phy_dsp(tp);
3120                         if (err)
3121                                 return err;
3122
3123                         tg3_readphy(tp, MII_BMSR, &bmsr);
3124                         for (i = 0; i < 1000; i++) {
3125                                 udelay(10);
3126                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3127                                     (bmsr & BMSR_LSTATUS)) {
3128                                         udelay(40);
3129                                         break;
3130                                 }
3131                         }
3132
3133                         if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3134                             TG3_PHY_REV_BCM5401_B0 &&
3135                             !(bmsr & BMSR_LSTATUS) &&
3136                             tp->link_config.active_speed == SPEED_1000) {
3137                                 err = tg3_phy_reset(tp);
3138                                 if (!err)
3139                                         err = tg3_init_5401phy_dsp(tp);
3140                                 if (err)
3141                                         return err;
3142                         }
3143                 }
3144         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3145                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3146                 /* 5701 {A0,B0} CRC bug workaround */
3147                 tg3_writephy(tp, 0x15, 0x0a75);
3148                 tg3_writephy(tp, 0x1c, 0x8c68);
3149                 tg3_writephy(tp, 0x1c, 0x8d68);
3150                 tg3_writephy(tp, 0x1c, 0x8c68);
3151         }
3152
3153         /* Clear pending interrupts... */
3154         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3155         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3156
3157         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3158                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3159         else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3160                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3161
3162         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3163             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3164                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3165                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3166                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3167                 else
3168                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3169         }
3170
3171         current_link_up = 0;
3172         current_speed = SPEED_INVALID;
3173         current_duplex = DUPLEX_INVALID;
3174
3175         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3176                 u32 val;
3177
3178                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3179                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3180                 if (!(val & (1 << 10))) {
3181                         val |= (1 << 10);
3182                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3183                         goto relink;
3184                 }
3185         }
3186
3187         bmsr = 0;
3188         for (i = 0; i < 100; i++) {
3189                 tg3_readphy(tp, MII_BMSR, &bmsr);
3190                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3191                     (bmsr & BMSR_LSTATUS))
3192                         break;
3193                 udelay(40);
3194         }
3195
3196         if (bmsr & BMSR_LSTATUS) {
3197                 u32 aux_stat, bmcr;
3198
3199                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3200                 for (i = 0; i < 2000; i++) {
3201                         udelay(10);
3202                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3203                             aux_stat)
3204                                 break;
3205                 }
3206
3207                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3208                                              &current_speed,
3209                                              &current_duplex);
3210
3211                 bmcr = 0;
3212                 for (i = 0; i < 200; i++) {
3213                         tg3_readphy(tp, MII_BMCR, &bmcr);
3214                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3215                                 continue;
3216                         if (bmcr && bmcr != 0x7fff)
3217                                 break;
3218                         udelay(10);
3219                 }
3220
3221                 lcl_adv = 0;
3222                 rmt_adv = 0;
3223
3224                 tp->link_config.active_speed = current_speed;
3225                 tp->link_config.active_duplex = current_duplex;
3226
3227                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3228                         if ((bmcr & BMCR_ANENABLE) &&
3229                             tg3_copper_is_advertising_all(tp,
3230                                                 tp->link_config.advertising)) {
3231                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3232                                                                   &rmt_adv))
3233                                         current_link_up = 1;
3234                         }
3235                 } else {
3236                         if (!(bmcr & BMCR_ANENABLE) &&
3237                             tp->link_config.speed == current_speed &&
3238                             tp->link_config.duplex == current_duplex &&
3239                             tp->link_config.flowctrl ==
3240                             tp->link_config.active_flowctrl) {
3241                                 current_link_up = 1;
3242                         }
3243                 }
3244
3245                 if (current_link_up == 1 &&
3246                     tp->link_config.active_duplex == DUPLEX_FULL)
3247                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3248         }
3249
3250 relink:
3251         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3252                 u32 tmp;
3253
3254                 tg3_phy_copper_begin(tp);
3255
3256                 tg3_readphy(tp, MII_BMSR, &tmp);
3257                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3258                     (tmp & BMSR_LSTATUS))
3259                         current_link_up = 1;
3260         }
3261
3262         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3263         if (current_link_up == 1) {
3264                 if (tp->link_config.active_speed == SPEED_100 ||
3265                     tp->link_config.active_speed == SPEED_10)
3266                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3267                 else
3268                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3269         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3270                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3271         else
3272                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3273
3274         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3275         if (tp->link_config.active_duplex == DUPLEX_HALF)
3276                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3277
3278         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3279                 if (current_link_up == 1 &&
3280                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3281                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3282                 else
3283                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3284         }
3285
3286         /* ??? Without this setting Netgear GA302T PHY does not
3287          * ??? send/receive packets...
3288          */
3289         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3290             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3291                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3292                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3293                 udelay(80);
3294         }
3295
3296         tw32_f(MAC_MODE, tp->mac_mode);
3297         udelay(40);
3298
3299         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3300                 /* Polled via timer. */
3301                 tw32_f(MAC_EVENT, 0);
3302         } else {
3303                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3304         }
3305         udelay(40);
3306
3307         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3308             current_link_up == 1 &&
3309             tp->link_config.active_speed == SPEED_1000 &&
3310             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3311              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3312                 udelay(120);
3313                 tw32_f(MAC_STATUS,
3314                      (MAC_STATUS_SYNC_CHANGED |
3315                       MAC_STATUS_CFG_CHANGED));
3316                 udelay(40);
3317                 tg3_write_mem(tp,
3318                               NIC_SRAM_FIRMWARE_MBOX,
3319                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3320         }
3321
3322         /* Prevent send BD corruption. */
3323         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3324                 u16 oldlnkctl, newlnkctl;
3325
3326                 pci_read_config_word(tp->pdev,
3327                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3328                                      &oldlnkctl);
3329                 if (tp->link_config.active_speed == SPEED_100 ||
3330                     tp->link_config.active_speed == SPEED_10)
3331                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3332                 else
3333                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3334                 if (newlnkctl != oldlnkctl)
3335                         pci_write_config_word(tp->pdev,
3336                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3337                                               newlnkctl);
3338         }
3339
3340         if (current_link_up != netif_carrier_ok(tp->dev)) {
3341                 if (current_link_up)
3342                         netif_carrier_on(tp->dev);
3343                 else
3344                         netif_carrier_off(tp->dev);
3345                 tg3_link_report(tp);
3346         }
3347
3348         return 0;
3349 }
3350
3351 struct tg3_fiber_aneginfo {
3352         int state;
3353 #define ANEG_STATE_UNKNOWN              0
3354 #define ANEG_STATE_AN_ENABLE            1
3355 #define ANEG_STATE_RESTART_INIT         2
3356 #define ANEG_STATE_RESTART              3
3357 #define ANEG_STATE_DISABLE_LINK_OK      4
3358 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3359 #define ANEG_STATE_ABILITY_DETECT       6
3360 #define ANEG_STATE_ACK_DETECT_INIT      7
3361 #define ANEG_STATE_ACK_DETECT           8
3362 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3363 #define ANEG_STATE_COMPLETE_ACK         10
3364 #define ANEG_STATE_IDLE_DETECT_INIT     11
3365 #define ANEG_STATE_IDLE_DETECT          12
3366 #define ANEG_STATE_LINK_OK              13
3367 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3368 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3369
3370         u32 flags;
3371 #define MR_AN_ENABLE            0x00000001
3372 #define MR_RESTART_AN           0x00000002
3373 #define MR_AN_COMPLETE          0x00000004
3374 #define MR_PAGE_RX              0x00000008
3375 #define MR_NP_LOADED            0x00000010
3376 #define MR_TOGGLE_TX            0x00000020
3377 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3378 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3379 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3380 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3381 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3382 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3383 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3384 #define MR_TOGGLE_RX            0x00002000
3385 #define MR_NP_RX                0x00004000
3386
3387 #define MR_LINK_OK              0x80000000
3388
3389         unsigned long link_time, cur_time;
3390
3391         u32 ability_match_cfg;
3392         int ability_match_count;
3393
3394         char ability_match, idle_match, ack_match;
3395
3396         u32 txconfig, rxconfig;
3397 #define ANEG_CFG_NP             0x00000080
3398 #define ANEG_CFG_ACK            0x00000040
3399 #define ANEG_CFG_RF2            0x00000020
3400 #define ANEG_CFG_RF1            0x00000010
3401 #define ANEG_CFG_PS2            0x00000001
3402 #define ANEG_CFG_PS1            0x00008000
3403 #define ANEG_CFG_HD             0x00004000
3404 #define ANEG_CFG_FD             0x00002000
3405 #define ANEG_CFG_INVAL          0x00001f06
3406
3407 };
3408 #define ANEG_OK         0
3409 #define ANEG_DONE       1
3410 #define ANEG_TIMER_ENAB 2
3411 #define ANEG_FAILED     -1
3412
3413 #define ANEG_STATE_SETTLE_TIME  10000
3414
3415 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3416                                    struct tg3_fiber_aneginfo *ap)
3417 {
3418         u16 flowctrl;
3419         unsigned long delta;
3420         u32 rx_cfg_reg;
3421         int ret;
3422
3423         if (ap->state == ANEG_STATE_UNKNOWN) {
3424                 ap->rxconfig = 0;
3425                 ap->link_time = 0;
3426                 ap->cur_time = 0;
3427                 ap->ability_match_cfg = 0;
3428                 ap->ability_match_count = 0;
3429                 ap->ability_match = 0;
3430                 ap->idle_match = 0;
3431                 ap->ack_match = 0;
3432         }
3433         ap->cur_time++;
3434
3435         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3436                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3437
3438                 if (rx_cfg_reg != ap->ability_match_cfg) {
3439                         ap->ability_match_cfg = rx_cfg_reg;
3440                         ap->ability_match = 0;
3441                         ap->ability_match_count = 0;
3442                 } else {
3443                         if (++ap->ability_match_count > 1) {
3444                                 ap->ability_match = 1;
3445                                 ap->ability_match_cfg = rx_cfg_reg;
3446                         }
3447                 }
3448                 if (rx_cfg_reg & ANEG_CFG_ACK)
3449                         ap->ack_match = 1;
3450                 else
3451                         ap->ack_match = 0;
3452
3453                 ap->idle_match = 0;
3454         } else {
3455                 ap->idle_match = 1;
3456                 ap->ability_match_cfg = 0;
3457                 ap->ability_match_count = 0;
3458                 ap->ability_match = 0;
3459                 ap->ack_match = 0;
3460
3461                 rx_cfg_reg = 0;
3462         }
3463
3464         ap->rxconfig = rx_cfg_reg;
3465         ret = ANEG_OK;
3466
3467         switch (ap->state) {
3468         case ANEG_STATE_UNKNOWN:
3469                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3470                         ap->state = ANEG_STATE_AN_ENABLE;
3471
3472                 /* fallthru */
3473         case ANEG_STATE_AN_ENABLE:
3474                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3475                 if (ap->flags & MR_AN_ENABLE) {
3476                         ap->link_time = 0;
3477                         ap->cur_time = 0;
3478                         ap->ability_match_cfg = 0;
3479                         ap->ability_match_count = 0;
3480                         ap->ability_match = 0;
3481                         ap->idle_match = 0;
3482                         ap->ack_match = 0;
3483
3484                         ap->state = ANEG_STATE_RESTART_INIT;
3485                 } else {
3486                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3487                 }
3488                 break;
3489
3490         case ANEG_STATE_RESTART_INIT:
3491                 ap->link_time = ap->cur_time;
3492                 ap->flags &= ~(MR_NP_LOADED);
3493                 ap->txconfig = 0;
3494                 tw32(MAC_TX_AUTO_NEG, 0);
3495                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3496                 tw32_f(MAC_MODE, tp->mac_mode);
3497                 udelay(40);
3498
3499                 ret = ANEG_TIMER_ENAB;
3500                 ap->state = ANEG_STATE_RESTART;
3501
3502                 /* fallthru */
3503         case ANEG_STATE_RESTART:
3504                 delta = ap->cur_time - ap->link_time;
3505                 if (delta > ANEG_STATE_SETTLE_TIME)
3506                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3507                 else
3508                         ret = ANEG_TIMER_ENAB;
3509                 break;
3510
3511         case ANEG_STATE_DISABLE_LINK_OK:
3512                 ret = ANEG_DONE;
3513                 break;
3514
3515         case ANEG_STATE_ABILITY_DETECT_INIT:
3516                 ap->flags &= ~(MR_TOGGLE_TX);
3517                 ap->txconfig = ANEG_CFG_FD;
3518                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3519                 if (flowctrl & ADVERTISE_1000XPAUSE)
3520                         ap->txconfig |= ANEG_CFG_PS1;
3521                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3522                         ap->txconfig |= ANEG_CFG_PS2;
3523                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3524                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3525                 tw32_f(MAC_MODE, tp->mac_mode);
3526                 udelay(40);
3527
3528                 ap->state = ANEG_STATE_ABILITY_DETECT;
3529                 break;
3530
3531         case ANEG_STATE_ABILITY_DETECT:
3532                 if (ap->ability_match != 0 && ap->rxconfig != 0)
3533                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3534                 break;
3535
3536         case ANEG_STATE_ACK_DETECT_INIT:
3537                 ap->txconfig |= ANEG_CFG_ACK;
3538                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3539                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3540                 tw32_f(MAC_MODE, tp->mac_mode);
3541                 udelay(40);
3542
3543                 ap->state = ANEG_STATE_ACK_DETECT;
3544
3545                 /* fallthru */
3546         case ANEG_STATE_ACK_DETECT:
3547                 if (ap->ack_match != 0) {
3548                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3549                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3550                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3551                         } else {
3552                                 ap->state = ANEG_STATE_AN_ENABLE;
3553                         }
3554                 } else if (ap->ability_match != 0 &&
3555                            ap->rxconfig == 0) {
3556                         ap->state = ANEG_STATE_AN_ENABLE;
3557                 }
3558                 break;
3559
3560         case ANEG_STATE_COMPLETE_ACK_INIT:
3561                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3562                         ret = ANEG_FAILED;
3563                         break;
3564                 }
3565                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3566                                MR_LP_ADV_HALF_DUPLEX |
3567                                MR_LP_ADV_SYM_PAUSE |
3568                                MR_LP_ADV_ASYM_PAUSE |
3569                                MR_LP_ADV_REMOTE_FAULT1 |
3570                                MR_LP_ADV_REMOTE_FAULT2 |
3571                                MR_LP_ADV_NEXT_PAGE |
3572                                MR_TOGGLE_RX |
3573                                MR_NP_RX);
3574                 if (ap->rxconfig & ANEG_CFG_FD)
3575                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3576                 if (ap->rxconfig & ANEG_CFG_HD)
3577                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3578                 if (ap->rxconfig & ANEG_CFG_PS1)
3579                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3580                 if (ap->rxconfig & ANEG_CFG_PS2)
3581                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3582                 if (ap->rxconfig & ANEG_CFG_RF1)
3583                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3584                 if (ap->rxconfig & ANEG_CFG_RF2)
3585                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3586                 if (ap->rxconfig & ANEG_CFG_NP)
3587                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3588
3589                 ap->link_time = ap->cur_time;
3590
3591                 ap->flags ^= (MR_TOGGLE_TX);
3592                 if (ap->rxconfig & 0x0008)
3593                         ap->flags |= MR_TOGGLE_RX;
3594                 if (ap->rxconfig & ANEG_CFG_NP)
3595                         ap->flags |= MR_NP_RX;
3596                 ap->flags |= MR_PAGE_RX;
3597
3598                 ap->state = ANEG_STATE_COMPLETE_ACK;
3599                 ret = ANEG_TIMER_ENAB;
3600                 break;
3601
3602         case ANEG_STATE_COMPLETE_ACK:
3603                 if (ap->ability_match != 0 &&
3604                     ap->rxconfig == 0) {
3605                         ap->state = ANEG_STATE_AN_ENABLE;
3606                         break;
3607                 }
3608                 delta = ap->cur_time - ap->link_time;
3609                 if (delta > ANEG_STATE_SETTLE_TIME) {
3610                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3611                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3612                         } else {
3613                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3614                                     !(ap->flags & MR_NP_RX)) {
3615                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3616                                 } else {
3617                                         ret = ANEG_FAILED;
3618                                 }
3619                         }
3620                 }
3621                 break;
3622
3623         case ANEG_STATE_IDLE_DETECT_INIT:
3624                 ap->link_time = ap->cur_time;
3625                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3626                 tw32_f(MAC_MODE, tp->mac_mode);
3627                 udelay(40);
3628
3629                 ap->state = ANEG_STATE_IDLE_DETECT;
3630                 ret = ANEG_TIMER_ENAB;
3631                 break;
3632
3633         case ANEG_STATE_IDLE_DETECT:
3634                 if (ap->ability_match != 0 &&
3635                     ap->rxconfig == 0) {
3636                         ap->state = ANEG_STATE_AN_ENABLE;
3637                         break;
3638                 }
3639                 delta = ap->cur_time - ap->link_time;
3640                 if (delta > ANEG_STATE_SETTLE_TIME) {
3641                         /* XXX another gem from the Broadcom driver :( */
3642                         ap->state = ANEG_STATE_LINK_OK;
3643                 }
3644                 break;
3645
3646         case ANEG_STATE_LINK_OK:
3647                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3648                 ret = ANEG_DONE;
3649                 break;
3650
3651         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3652                 /* ??? unimplemented */
3653                 break;
3654
3655         case ANEG_STATE_NEXT_PAGE_WAIT:
3656                 /* ??? unimplemented */
3657                 break;
3658
3659         default:
3660                 ret = ANEG_FAILED;
3661                 break;
3662         }
3663
3664         return ret;
3665 }
3666
3667 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3668 {
3669         int res = 0;
3670         struct tg3_fiber_aneginfo aninfo;
3671         int status = ANEG_FAILED;
3672         unsigned int tick;
3673         u32 tmp;
3674
3675         tw32_f(MAC_TX_AUTO_NEG, 0);
3676
3677         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3678         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3679         udelay(40);
3680
3681         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3682         udelay(40);
3683
3684         memset(&aninfo, 0, sizeof(aninfo));
3685         aninfo.flags |= MR_AN_ENABLE;
3686         aninfo.state = ANEG_STATE_UNKNOWN;
3687         aninfo.cur_time = 0;
3688         tick = 0;
3689         while (++tick < 195000) {
3690                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3691                 if (status == ANEG_DONE || status == ANEG_FAILED)
3692                         break;
3693
3694                 udelay(1);
3695         }
3696
3697         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3698         tw32_f(MAC_MODE, tp->mac_mode);
3699         udelay(40);
3700
3701         *txflags = aninfo.txconfig;
3702         *rxflags = aninfo.flags;
3703
3704         if (status == ANEG_DONE &&
3705             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3706                              MR_LP_ADV_FULL_DUPLEX)))
3707                 res = 1;
3708
3709         return res;
3710 }
3711
3712 static void tg3_init_bcm8002(struct tg3 *tp)
3713 {
3714         u32 mac_status = tr32(MAC_STATUS);
3715         int i;
3716
3717         /* Reset when initting first time or we have a link. */
3718         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3719             !(mac_status & MAC_STATUS_PCS_SYNCED))
3720                 return;
3721
3722         /* Set PLL lock range. */
3723         tg3_writephy(tp, 0x16, 0x8007);
3724
3725         /* SW reset */
3726         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3727
3728         /* Wait for reset to complete. */
3729         /* XXX schedule_timeout() ... */
3730         for (i = 0; i < 500; i++)
3731                 udelay(10);
3732
3733         /* Config mode; select PMA/Ch 1 regs. */
3734         tg3_writephy(tp, 0x10, 0x8411);
3735
3736         /* Enable auto-lock and comdet, select txclk for tx. */
3737         tg3_writephy(tp, 0x11, 0x0a10);
3738
3739         tg3_writephy(tp, 0x18, 0x00a0);
3740         tg3_writephy(tp, 0x16, 0x41ff);
3741
3742         /* Assert and deassert POR. */
3743         tg3_writephy(tp, 0x13, 0x0400);
3744         udelay(40);
3745         tg3_writephy(tp, 0x13, 0x0000);
3746
3747         tg3_writephy(tp, 0x11, 0x0a50);
3748         udelay(40);
3749         tg3_writephy(tp, 0x11, 0x0a10);
3750
3751         /* Wait for signal to stabilize */
3752         /* XXX schedule_timeout() ... */
3753         for (i = 0; i < 15000; i++)
3754                 udelay(10);
3755
3756         /* Deselect the channel register so we can read the PHYID
3757          * later.
3758          */
3759         tg3_writephy(tp, 0x10, 0x8011);
3760 }
3761
3762 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3763 {
3764         u16 flowctrl;
3765         u32 sg_dig_ctrl, sg_dig_status;
3766         u32 serdes_cfg, expected_sg_dig_ctrl;
3767         int workaround, port_a;
3768         int current_link_up;
3769
3770         serdes_cfg = 0;
3771         expected_sg_dig_ctrl = 0;
3772         workaround = 0;
3773         port_a = 1;
3774         current_link_up = 0;
3775
3776         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3777             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3778                 workaround = 1;
3779                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3780                         port_a = 0;
3781
3782                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3783                 /* preserve bits 20-23 for voltage regulator */
3784                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3785         }
3786
3787         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3788
3789         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3790                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3791                         if (workaround) {
3792                                 u32 val = serdes_cfg;
3793
3794                                 if (port_a)
3795                                         val |= 0xc010000;
3796                                 else
3797                                         val |= 0x4010000;
3798                                 tw32_f(MAC_SERDES_CFG, val);
3799                         }
3800
3801                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3802                 }
3803                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3804                         tg3_setup_flow_control(tp, 0, 0);
3805                         current_link_up = 1;
3806                 }
3807                 goto out;
3808         }
3809
3810         /* Want auto-negotiation.  */
3811         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3812
3813         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3814         if (flowctrl & ADVERTISE_1000XPAUSE)
3815                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3816         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3817                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3818
3819         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3820                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3821                     tp->serdes_counter &&
3822                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3823                                     MAC_STATUS_RCVD_CFG)) ==
3824                      MAC_STATUS_PCS_SYNCED)) {
3825                         tp->serdes_counter--;
3826                         current_link_up = 1;
3827                         goto out;
3828                 }
3829 restart_autoneg:
3830                 if (workaround)
3831                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3832                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3833                 udelay(5);
3834                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3835
3836                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3837                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3838         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3839                                  MAC_STATUS_SIGNAL_DET)) {
3840                 sg_dig_status = tr32(SG_DIG_STATUS);
3841                 mac_status = tr32(MAC_STATUS);
3842
3843                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3844                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3845                         u32 local_adv = 0, remote_adv = 0;
3846
3847                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3848                                 local_adv |= ADVERTISE_1000XPAUSE;
3849                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3850                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3851
3852                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3853                                 remote_adv |= LPA_1000XPAUSE;
3854                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3855                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3856
3857                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3858                         current_link_up = 1;
3859                         tp->serdes_counter = 0;
3860                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3861                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3862                         if (tp->serdes_counter)
3863                                 tp->serdes_counter--;
3864                         else {
3865                                 if (workaround) {
3866                                         u32 val = serdes_cfg;
3867
3868                                         if (port_a)
3869                                                 val |= 0xc010000;
3870                                         else
3871                                                 val |= 0x4010000;
3872
3873                                         tw32_f(MAC_SERDES_CFG, val);
3874                                 }
3875
3876                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3877                                 udelay(40);
3878
3879                                 /* Link parallel detection - link is up */
3880                                 /* only if we have PCS_SYNC and not */
3881                                 /* receiving config code words */
3882                                 mac_status = tr32(MAC_STATUS);
3883                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3884                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3885                                         tg3_setup_flow_control(tp, 0, 0);
3886                                         current_link_up = 1;
3887                                         tp->tg3_flags2 |=
3888                                                 TG3_FLG2_PARALLEL_DETECT;
3889                                         tp->serdes_counter =
3890                                                 SERDES_PARALLEL_DET_TIMEOUT;
3891                                 } else
3892                                         goto restart_autoneg;
3893                         }
3894                 }
3895         } else {
3896                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3897                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3898         }
3899
3900 out:
3901         return current_link_up;
3902 }
3903
3904 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3905 {
3906         int current_link_up = 0;
3907
3908         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3909                 goto out;
3910
3911         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3912                 u32 txflags, rxflags;
3913                 int i;
3914
3915                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3916                         u32 local_adv = 0, remote_adv = 0;
3917
3918                         if (txflags & ANEG_CFG_PS1)
3919                                 local_adv |= ADVERTISE_1000XPAUSE;
3920                         if (txflags & ANEG_CFG_PS2)
3921                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3922
3923                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3924                                 remote_adv |= LPA_1000XPAUSE;
3925                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3926                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3927
3928                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3929
3930                         current_link_up = 1;
3931                 }
3932                 for (i = 0; i < 30; i++) {
3933                         udelay(20);
3934                         tw32_f(MAC_STATUS,
3935                                (MAC_STATUS_SYNC_CHANGED |
3936                                 MAC_STATUS_CFG_CHANGED));
3937                         udelay(40);
3938                         if ((tr32(MAC_STATUS) &
3939                              (MAC_STATUS_SYNC_CHANGED |
3940                               MAC_STATUS_CFG_CHANGED)) == 0)
3941                                 break;
3942                 }
3943
3944                 mac_status = tr32(MAC_STATUS);
3945                 if (current_link_up == 0 &&
3946                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3947                     !(mac_status & MAC_STATUS_RCVD_CFG))
3948                         current_link_up = 1;
3949         } else {
3950                 tg3_setup_flow_control(tp, 0, 0);
3951
3952                 /* Forcing 1000FD link up. */
3953                 current_link_up = 1;
3954
3955                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3956                 udelay(40);
3957
3958                 tw32_f(MAC_MODE, tp->mac_mode);
3959                 udelay(40);
3960         }
3961
3962 out:
3963         return current_link_up;
3964 }
3965
3966 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3967 {
3968         u32 orig_pause_cfg;
3969         u16 orig_active_speed;
3970         u8 orig_active_duplex;
3971         u32 mac_status;
3972         int current_link_up;
3973         int i;
3974
3975         orig_pause_cfg = tp->link_config.active_flowctrl;
3976         orig_active_speed = tp->link_config.active_speed;
3977         orig_active_duplex = tp->link_config.active_duplex;
3978
3979         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3980             netif_carrier_ok(tp->dev) &&
3981             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3982                 mac_status = tr32(MAC_STATUS);
3983                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3984                                MAC_STATUS_SIGNAL_DET |
3985                                MAC_STATUS_CFG_CHANGED |
3986                                MAC_STATUS_RCVD_CFG);
3987                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3988                                    MAC_STATUS_SIGNAL_DET)) {
3989                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3990                                             MAC_STATUS_CFG_CHANGED));
3991                         return 0;
3992                 }
3993         }
3994
3995         tw32_f(MAC_TX_AUTO_NEG, 0);
3996
3997         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3998         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3999         tw32_f(MAC_MODE, tp->mac_mode);
4000         udelay(40);
4001
4002         if (tp->phy_id == TG3_PHY_ID_BCM8002)
4003                 tg3_init_bcm8002(tp);
4004
4005         /* Enable link change event even when serdes polling.  */
4006         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4007         udelay(40);
4008
4009         current_link_up = 0;
4010         mac_status = tr32(MAC_STATUS);
4011
4012         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
4013                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4014         else
4015                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4016
4017         tp->napi[0].hw_status->status =
4018                 (SD_STATUS_UPDATED |
4019                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4020
4021         for (i = 0; i < 100; i++) {
4022                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4023                                     MAC_STATUS_CFG_CHANGED));
4024                 udelay(5);
4025                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4026                                          MAC_STATUS_CFG_CHANGED |
4027                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4028                         break;
4029         }
4030
4031         mac_status = tr32(MAC_STATUS);
4032         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4033                 current_link_up = 0;
4034                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4035                     tp->serdes_counter == 0) {
4036                         tw32_f(MAC_MODE, (tp->mac_mode |
4037                                           MAC_MODE_SEND_CONFIGS));
4038                         udelay(1);
4039                         tw32_f(MAC_MODE, tp->mac_mode);
4040                 }
4041         }
4042
4043         if (current_link_up == 1) {
4044                 tp->link_config.active_speed = SPEED_1000;
4045                 tp->link_config.active_duplex = DUPLEX_FULL;
4046                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4047                                     LED_CTRL_LNKLED_OVERRIDE |
4048                                     LED_CTRL_1000MBPS_ON));
4049         } else {
4050                 tp->link_config.active_speed = SPEED_INVALID;
4051                 tp->link_config.active_duplex = DUPLEX_INVALID;
4052                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4053                                     LED_CTRL_LNKLED_OVERRIDE |
4054                                     LED_CTRL_TRAFFIC_OVERRIDE));
4055         }
4056
4057         if (current_link_up != netif_carrier_ok(tp->dev)) {
4058                 if (current_link_up)
4059                         netif_carrier_on(tp->dev);
4060                 else
4061                         netif_carrier_off(tp->dev);
4062                 tg3_link_report(tp);
4063         } else {
4064                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4065                 if (orig_pause_cfg != now_pause_cfg ||
4066                     orig_active_speed != tp->link_config.active_speed ||
4067                     orig_active_duplex != tp->link_config.active_duplex)
4068                         tg3_link_report(tp);
4069         }
4070
4071         return 0;
4072 }
4073
4074 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4075 {
4076         int current_link_up, err = 0;
4077         u32 bmsr, bmcr;
4078         u16 current_speed;
4079         u8 current_duplex;
4080         u32 local_adv, remote_adv;
4081
4082         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4083         tw32_f(MAC_MODE, tp->mac_mode);
4084         udelay(40);
4085
4086         tw32(MAC_EVENT, 0);
4087
4088         tw32_f(MAC_STATUS,
4089              (MAC_STATUS_SYNC_CHANGED |
4090               MAC_STATUS_CFG_CHANGED |
4091               MAC_STATUS_MI_COMPLETION |
4092               MAC_STATUS_LNKSTATE_CHANGED));
4093         udelay(40);
4094
4095         if (force_reset)
4096                 tg3_phy_reset(tp);
4097
4098         current_link_up = 0;
4099         current_speed = SPEED_INVALID;
4100         current_duplex = DUPLEX_INVALID;
4101
4102         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4103         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4104         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4105                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4106                         bmsr |= BMSR_LSTATUS;
4107                 else
4108                         bmsr &= ~BMSR_LSTATUS;
4109         }
4110
4111         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4112
4113         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4114             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4115                 /* do nothing, just check for link up at the end */
4116         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4117                 u32 adv, new_adv;
4118
4119                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4120                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4121                                   ADVERTISE_1000XPAUSE |
4122                                   ADVERTISE_1000XPSE_ASYM |
4123                                   ADVERTISE_SLCT);
4124
4125                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4126
4127                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4128                         new_adv |= ADVERTISE_1000XHALF;
4129                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4130                         new_adv |= ADVERTISE_1000XFULL;
4131
4132                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4133                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4134                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4135                         tg3_writephy(tp, MII_BMCR, bmcr);
4136
4137                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4138                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4139                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4140
4141                         return err;
4142                 }
4143         } else {
4144                 u32 new_bmcr;
4145
4146                 bmcr &= ~BMCR_SPEED1000;
4147                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4148
4149                 if (tp->link_config.duplex == DUPLEX_FULL)
4150                         new_bmcr |= BMCR_FULLDPLX;
4151
4152                 if (new_bmcr != bmcr) {
4153                         /* BMCR_SPEED1000 is a reserved bit that needs
4154                          * to be set on write.
4155                          */
4156                         new_bmcr |= BMCR_SPEED1000;
4157
4158                         /* Force a linkdown */
4159                         if (netif_carrier_ok(tp->dev)) {
4160                                 u32 adv;
4161
4162                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4163                                 adv &= ~(ADVERTISE_1000XFULL |
4164                                          ADVERTISE_1000XHALF |
4165                                          ADVERTISE_SLCT);
4166                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4167                                 tg3_writephy(tp, MII_BMCR, bmcr |
4168                                                            BMCR_ANRESTART |
4169                                                            BMCR_ANENABLE);
4170                                 udelay(10);
4171                                 netif_carrier_off(tp->dev);
4172                         }
4173                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4174                         bmcr = new_bmcr;
4175                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4176                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4177                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4178                             ASIC_REV_5714) {
4179                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4180                                         bmsr |= BMSR_LSTATUS;
4181                                 else
4182                                         bmsr &= ~BMSR_LSTATUS;
4183                         }
4184                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4185                 }
4186         }
4187
4188         if (bmsr & BMSR_LSTATUS) {
4189                 current_speed = SPEED_1000;
4190                 current_link_up = 1;
4191                 if (bmcr & BMCR_FULLDPLX)
4192                         current_duplex = DUPLEX_FULL;
4193                 else
4194                         current_duplex = DUPLEX_HALF;
4195
4196                 local_adv = 0;
4197                 remote_adv = 0;
4198
4199                 if (bmcr & BMCR_ANENABLE) {
4200                         u32 common;
4201
4202                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4203                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4204                         common = local_adv & remote_adv;
4205                         if (common & (ADVERTISE_1000XHALF |
4206                                       ADVERTISE_1000XFULL)) {
4207                                 if (common & ADVERTISE_1000XFULL)
4208                                         current_duplex = DUPLEX_FULL;
4209                                 else
4210                                         current_duplex = DUPLEX_HALF;
4211                         } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4212                                 /* Link is up via parallel detect */
4213                         } else {
4214                                 current_link_up = 0;
4215                         }
4216                 }
4217         }
4218
4219         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4220                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4221
4222         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4223         if (tp->link_config.active_duplex == DUPLEX_HALF)
4224                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4225
4226         tw32_f(MAC_MODE, tp->mac_mode);
4227         udelay(40);
4228
4229         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4230
4231         tp->link_config.active_speed = current_speed;
4232         tp->link_config.active_duplex = current_duplex;
4233
4234         if (current_link_up != netif_carrier_ok(tp->dev)) {
4235                 if (current_link_up)
4236                         netif_carrier_on(tp->dev);
4237                 else {
4238                         netif_carrier_off(tp->dev);
4239                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4240                 }
4241                 tg3_link_report(tp);
4242         }
4243         return err;
4244 }
4245
4246 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4247 {
4248         if (tp->serdes_counter) {
4249                 /* Give autoneg time to complete. */
4250                 tp->serdes_counter--;
4251                 return;
4252         }
4253
4254         if (!netif_carrier_ok(tp->dev) &&
4255             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4256                 u32 bmcr;
4257
4258                 tg3_readphy(tp, MII_BMCR, &bmcr);
4259                 if (bmcr & BMCR_ANENABLE) {
4260                         u32 phy1, phy2;
4261
4262                         /* Select shadow register 0x1f */
4263                         tg3_writephy(tp, 0x1c, 0x7c00);
4264                         tg3_readphy(tp, 0x1c, &phy1);
4265
4266                         /* Select expansion interrupt status register */
4267                         tg3_writephy(tp, 0x17, 0x0f01);
4268                         tg3_readphy(tp, 0x15, &phy2);
4269                         tg3_readphy(tp, 0x15, &phy2);
4270
4271                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4272                                 /* We have signal detect and not receiving
4273                                  * config code words, link is up by parallel
4274                                  * detection.
4275                                  */
4276
4277                                 bmcr &= ~BMCR_ANENABLE;
4278                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4279                                 tg3_writephy(tp, MII_BMCR, bmcr);
4280                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4281                         }
4282                 }
4283         } else if (netif_carrier_ok(tp->dev) &&
4284                    (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4285                    (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4286                 u32 phy2;
4287
4288                 /* Select expansion interrupt status register */
4289                 tg3_writephy(tp, 0x17, 0x0f01);
4290                 tg3_readphy(tp, 0x15, &phy2);
4291                 if (phy2 & 0x20) {
4292                         u32 bmcr;
4293
4294                         /* Config code words received, turn on autoneg. */
4295                         tg3_readphy(tp, MII_BMCR, &bmcr);
4296                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4297
4298                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4299
4300                 }
4301         }
4302 }
4303
4304 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4305 {
4306         int err;
4307
4308         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
4309                 err = tg3_setup_fiber_phy(tp, force_reset);
4310         else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
4311                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4312         else
4313                 err = tg3_setup_copper_phy(tp, force_reset);
4314
4315         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4316                 u32 val, scale;
4317
4318                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4319                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4320                         scale = 65;
4321                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4322                         scale = 6;
4323                 else
4324                         scale = 12;
4325
4326                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4327                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4328                 tw32(GRC_MISC_CFG, val);
4329         }
4330
4331         if (tp->link_config.active_speed == SPEED_1000 &&
4332             tp->link_config.active_duplex == DUPLEX_HALF)
4333                 tw32(MAC_TX_LENGTHS,
4334                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4335                       (6 << TX_LENGTHS_IPG_SHIFT) |
4336                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4337         else
4338                 tw32(MAC_TX_LENGTHS,
4339                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4340                       (6 << TX_LENGTHS_IPG_SHIFT) |
4341                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4342
4343         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4344                 if (netif_carrier_ok(tp->dev)) {
4345                         tw32(HOSTCC_STAT_COAL_TICKS,
4346                              tp->coal.stats_block_coalesce_usecs);
4347                 } else {
4348                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4349                 }
4350         }
4351
4352         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4353                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4354                 if (!netif_carrier_ok(tp->dev))
4355                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4356                               tp->pwrmgmt_thresh;
4357                 else
4358                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4359                 tw32(PCIE_PWR_MGMT_THRESH, val);
4360         }
4361
4362         return err;
4363 }
4364
4365 /* This is called whenever we suspect that the system chipset is re-
4366  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4367  * is bogus tx completions. We try to recover by setting the
4368  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4369  * in the workqueue.
4370  */
4371 static void tg3_tx_recover(struct tg3 *tp)
4372 {
4373         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4374                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4375
4376         netdev_warn(tp->dev,
4377                     "The system may be re-ordering memory-mapped I/O "
4378                     "cycles to the network device, attempting to recover. "
4379                     "Please report the problem to the driver maintainer "
4380                     "and include system chipset information.\n");
4381
4382         spin_lock(&tp->lock);
4383         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4384         spin_unlock(&tp->lock);
4385 }
4386
4387 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4388 {
4389         smp_mb();
4390         return tnapi->tx_pending -
4391                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4392 }
4393
4394 /* Tigon3 never reports partial packet sends.  So we do not
4395  * need special logic to handle SKBs that have not had all
4396  * of their frags sent yet, like SunGEM does.
4397  */
4398 static void tg3_tx(struct tg3_napi *tnapi)
4399 {
4400         struct tg3 *tp = tnapi->tp;
4401         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4402         u32 sw_idx = tnapi->tx_cons;
4403         struct netdev_queue *txq;
4404         int index = tnapi - tp->napi;
4405
4406         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4407                 index--;
4408
4409         txq = netdev_get_tx_queue(tp->dev, index);
4410
4411         while (sw_idx != hw_idx) {
4412                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4413                 struct sk_buff *skb = ri->skb;
4414                 int i, tx_bug = 0;
4415
4416                 if (unlikely(skb == NULL)) {
4417                         tg3_tx_recover(tp);
4418                         return;
4419                 }
4420
4421                 pci_unmap_single(tp->pdev,
4422                                  dma_unmap_addr(ri, mapping),
4423                                  skb_headlen(skb),
4424                                  PCI_DMA_TODEVICE);
4425
4426                 ri->skb = NULL;
4427
4428                 sw_idx = NEXT_TX(sw_idx);
4429
4430                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4431                         ri = &tnapi->tx_buffers[sw_idx];
4432                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4433                                 tx_bug = 1;
4434
4435                         pci_unmap_page(tp->pdev,
4436                                        dma_unmap_addr(ri, mapping),
4437                                        skb_shinfo(skb)->frags[i].size,
4438                                        PCI_DMA_TODEVICE);
4439                         sw_idx = NEXT_TX(sw_idx);
4440                 }
4441
4442                 dev_kfree_skb(skb);
4443
4444                 if (unlikely(tx_bug)) {
4445                         tg3_tx_recover(tp);
4446                         return;
4447                 }
4448         }
4449
4450         tnapi->tx_cons = sw_idx;
4451
4452         /* Need to make the tx_cons update visible to tg3_start_xmit()
4453          * before checking for netif_queue_stopped().  Without the
4454          * memory barrier, there is a small possibility that tg3_start_xmit()
4455          * will miss it and cause the queue to be stopped forever.
4456          */
4457         smp_mb();
4458
4459         if (unlikely(netif_tx_queue_stopped(txq) &&
4460                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4461                 __netif_tx_lock(txq, smp_processor_id());
4462                 if (netif_tx_queue_stopped(txq) &&
4463                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4464                         netif_tx_wake_queue(txq);
4465                 __netif_tx_unlock(txq);
4466         }
4467 }
4468
4469 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4470 {
4471         if (!ri->skb)
4472                 return;
4473
4474         pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4475                          map_sz, PCI_DMA_FROMDEVICE);
4476         dev_kfree_skb_any(ri->skb);
4477         ri->skb = NULL;
4478 }
4479
4480 /* Returns size of skb allocated or < 0 on error.
4481  *
4482  * We only need to fill in the address because the other members
4483  * of the RX descriptor are invariant, see tg3_init_rings.
4484  *
4485  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4486  * posting buffers we only dirty the first cache line of the RX
4487  * descriptor (containing the address).  Whereas for the RX status
4488  * buffers the cpu only reads the last cacheline of the RX descriptor
4489  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4490  */
4491 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4492                             u32 opaque_key, u32 dest_idx_unmasked)
4493 {
4494         struct tg3_rx_buffer_desc *desc;
4495         struct ring_info *map, *src_map;
4496         struct sk_buff *skb;
4497         dma_addr_t mapping;
4498         int skb_size, dest_idx;
4499
4500         src_map = NULL;
4501         switch (opaque_key) {
4502         case RXD_OPAQUE_RING_STD:
4503                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4504                 desc = &tpr->rx_std[dest_idx];
4505                 map = &tpr->rx_std_buffers[dest_idx];
4506                 skb_size = tp->rx_pkt_map_sz;
4507                 break;
4508
4509         case RXD_OPAQUE_RING_JUMBO:
4510                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4511                 desc = &tpr->rx_jmb[dest_idx].std;
4512                 map = &tpr->rx_jmb_buffers[dest_idx];
4513                 skb_size = TG3_RX_JMB_MAP_SZ;
4514                 break;
4515
4516         default:
4517                 return -EINVAL;
4518         }
4519
4520         /* Do not overwrite any of the map or rp information
4521          * until we are sure we can commit to a new buffer.
4522          *
4523          * Callers depend upon this behavior and assume that
4524          * we leave everything unchanged if we fail.
4525          */
4526         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4527         if (skb == NULL)
4528                 return -ENOMEM;
4529
4530         skb_reserve(skb, tp->rx_offset);
4531
4532         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4533                                  PCI_DMA_FROMDEVICE);
4534         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4535                 dev_kfree_skb(skb);
4536                 return -EIO;
4537         }
4538
4539         map->skb = skb;
4540         dma_unmap_addr_set(map, mapping, mapping);
4541
4542         desc->addr_hi = ((u64)mapping >> 32);
4543         desc->addr_lo = ((u64)mapping & 0xffffffff);
4544
4545         return skb_size;
4546 }
4547
4548 /* We only need to move over in the address because the other
4549  * members of the RX descriptor are invariant.  See notes above
4550  * tg3_alloc_rx_skb for full details.
4551  */
4552 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4553                            struct tg3_rx_prodring_set *dpr,
4554                            u32 opaque_key, int src_idx,
4555                            u32 dest_idx_unmasked)
4556 {
4557         struct tg3 *tp = tnapi->tp;
4558         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4559         struct ring_info *src_map, *dest_map;
4560         struct tg3_rx_prodring_set *spr = &tp->prodring[0];
4561         int dest_idx;
4562
4563         switch (opaque_key) {
4564         case RXD_OPAQUE_RING_STD:
4565                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4566                 dest_desc = &dpr->rx_std[dest_idx];
4567                 dest_map = &dpr->rx_std_buffers[dest_idx];
4568                 src_desc = &spr->rx_std[src_idx];
4569                 src_map = &spr->rx_std_buffers[src_idx];
4570                 break;
4571
4572         case RXD_OPAQUE_RING_JUMBO:
4573                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4574                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4575                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4576                 src_desc = &spr->rx_jmb[src_idx].std;
4577                 src_map = &spr->rx_jmb_buffers[src_idx];
4578                 break;
4579
4580         default:
4581                 return;
4582         }
4583
4584         dest_map->skb = src_map->skb;
4585         dma_unmap_addr_set(dest_map, mapping,
4586                            dma_unmap_addr(src_map, mapping));
4587         dest_desc->addr_hi = src_desc->addr_hi;
4588         dest_desc->addr_lo = src_desc->addr_lo;
4589
4590         /* Ensure that the update to the skb happens after the physical
4591          * addresses have been transferred to the new BD location.
4592          */
4593         smp_wmb();
4594
4595         src_map->skb = NULL;
4596 }
4597
4598 /* The RX ring scheme is composed of multiple rings which post fresh
4599  * buffers to the chip, and one special ring the chip uses to report
4600  * status back to the host.
4601  *
4602  * The special ring reports the status of received packets to the
4603  * host.  The chip does not write into the original descriptor the
4604  * RX buffer was obtained from.  The chip simply takes the original
4605  * descriptor as provided by the host, updates the status and length
4606  * field, then writes this into the next status ring entry.
4607  *
4608  * Each ring the host uses to post buffers to the chip is described
4609  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4610  * it is first placed into the on-chip ram.  When the packet's length
4611  * is known, it walks down the TG3_BDINFO entries to select the ring.
4612  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4613  * which is within the range of the new packet's length is chosen.
4614  *
4615  * The "separate ring for rx status" scheme may sound queer, but it makes
4616  * sense from a cache coherency perspective.  If only the host writes
4617  * to the buffer post rings, and only the chip writes to the rx status
4618  * rings, then cache lines never move beyond shared-modified state.
4619  * If both the host and chip were to write into the same ring, cache line
4620  * eviction could occur since both entities want it in an exclusive state.
4621  */
4622 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4623 {
4624         struct tg3 *tp = tnapi->tp;
4625         u32 work_mask, rx_std_posted = 0;
4626         u32 std_prod_idx, jmb_prod_idx;
4627         u32 sw_idx = tnapi->rx_rcb_ptr;
4628         u16 hw_idx;
4629         int received;
4630         struct tg3_rx_prodring_set *tpr = tnapi->prodring;
4631
4632         hw_idx = *(tnapi->rx_rcb_prod_idx);
4633         /*
4634          * We need to order the read of hw_idx and the read of
4635          * the opaque cookie.
4636          */
4637         rmb();
4638         work_mask = 0;
4639         received = 0;
4640         std_prod_idx = tpr->rx_std_prod_idx;
4641         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4642         while (sw_idx != hw_idx && budget > 0) {
4643                 struct ring_info *ri;
4644                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4645                 unsigned int len;
4646                 struct sk_buff *skb;
4647                 dma_addr_t dma_addr;
4648                 u32 opaque_key, desc_idx, *post_ptr;
4649                 bool hw_vlan __maybe_unused = false;
4650                 u16 vtag __maybe_unused = 0;
4651
4652                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4653                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4654                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4655                         ri = &tp->prodring[0].rx_std_buffers[desc_idx];
4656                         dma_addr = dma_unmap_addr(ri, mapping);
4657                         skb = ri->skb;
4658                         post_ptr = &std_prod_idx;
4659                         rx_std_posted++;
4660                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4661                         ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
4662                         dma_addr = dma_unmap_addr(ri, mapping);
4663                         skb = ri->skb;
4664                         post_ptr = &jmb_prod_idx;
4665                 } else
4666                         goto next_pkt_nopost;
4667
4668                 work_mask |= opaque_key;
4669
4670                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4671                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4672                 drop_it:
4673                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4674                                        desc_idx, *post_ptr);
4675                 drop_it_no_recycle:
4676                         /* Other statistics kept track of by card. */
4677                         tp->net_stats.rx_dropped++;
4678                         goto next_pkt;
4679                 }
4680
4681                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4682                       ETH_FCS_LEN;
4683
4684                 if (len > TG3_RX_COPY_THRESH(tp)) {
4685                         int skb_size;
4686
4687                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4688                                                     *post_ptr);
4689                         if (skb_size < 0)
4690                                 goto drop_it;
4691
4692                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4693                                          PCI_DMA_FROMDEVICE);
4694
4695                         /* Ensure that the update to the skb happens
4696                          * after the usage of the old DMA mapping.
4697                          */
4698                         smp_wmb();
4699
4700                         ri->skb = NULL;
4701
4702                         skb_put(skb, len);
4703                 } else {
4704                         struct sk_buff *copy_skb;
4705
4706                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4707                                        desc_idx, *post_ptr);
4708
4709                         copy_skb = netdev_alloc_skb(tp->dev, len + VLAN_HLEN +
4710                                                     TG3_RAW_IP_ALIGN);
4711                         if (copy_skb == NULL)
4712                                 goto drop_it_no_recycle;
4713
4714                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN + VLAN_HLEN);
4715                         skb_put(copy_skb, len);
4716                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4717                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4718                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4719
4720                         /* We'll reuse the original ring buffer. */
4721                         skb = copy_skb;
4722                 }
4723
4724                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4725                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4726                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4727                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4728                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4729                 else
4730                         skb->ip_summed = CHECKSUM_NONE;
4731
4732                 skb->protocol = eth_type_trans(skb, tp->dev);
4733
4734                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4735                     skb->protocol != htons(ETH_P_8021Q)) {
4736                         dev_kfree_skb(skb);
4737                         goto next_pkt;
4738                 }
4739
4740                 if (desc->type_flags & RXD_FLAG_VLAN &&
4741                     !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) {
4742                         vtag = desc->err_vlan & RXD_VLAN_MASK;
4743 #if TG3_VLAN_TAG_USED
4744                         if (tp->vlgrp)
4745                                 hw_vlan = true;
4746                         else
4747 #endif
4748                         {
4749                                 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
4750                                                     __skb_push(skb, VLAN_HLEN);
4751
4752                                 memmove(ve, skb->data + VLAN_HLEN,
4753                                         ETH_ALEN * 2);
4754                                 ve->h_vlan_proto = htons(ETH_P_8021Q);
4755                                 ve->h_vlan_TCI = htons(vtag);
4756                         }
4757                 }
4758
4759 #if TG3_VLAN_TAG_USED
4760                 if (hw_vlan)
4761                         vlan_gro_receive(&tnapi->napi, tp->vlgrp, vtag, skb);
4762                 else
4763 #endif
4764                         napi_gro_receive(&tnapi->napi, skb);
4765
4766                 received++;
4767                 budget--;
4768
4769 next_pkt:
4770                 (*post_ptr)++;
4771
4772                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4773                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4774                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4775                                      tpr->rx_std_prod_idx);
4776                         work_mask &= ~RXD_OPAQUE_RING_STD;
4777                         rx_std_posted = 0;
4778                 }
4779 next_pkt_nopost:
4780                 sw_idx++;
4781                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4782
4783                 /* Refresh hw_idx to see if there is new work */
4784                 if (sw_idx == hw_idx) {
4785                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4786                         rmb();
4787                 }
4788         }
4789
4790         /* ACK the status ring. */
4791         tnapi->rx_rcb_ptr = sw_idx;
4792         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4793
4794         /* Refill RX ring(s). */
4795         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4796                 if (work_mask & RXD_OPAQUE_RING_STD) {
4797                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4798                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4799                                      tpr->rx_std_prod_idx);
4800                 }
4801                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4802                         tpr->rx_jmb_prod_idx = jmb_prod_idx %
4803                                                TG3_RX_JUMBO_RING_SIZE;
4804                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4805                                      tpr->rx_jmb_prod_idx);
4806                 }
4807                 mmiowb();
4808         } else if (work_mask) {
4809                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4810                  * updated before the producer indices can be updated.
4811                  */
4812                 smp_wmb();
4813
4814                 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4815                 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
4816
4817                 if (tnapi != &tp->napi[1])
4818                         napi_schedule(&tp->napi[1].napi);
4819         }
4820
4821         return received;
4822 }
4823
4824 static void tg3_poll_link(struct tg3 *tp)
4825 {
4826         /* handle link change and other phy events */
4827         if (!(tp->tg3_flags &
4828               (TG3_FLAG_USE_LINKCHG_REG |
4829                TG3_FLAG_POLL_SERDES))) {
4830                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4831
4832                 if (sblk->status & SD_STATUS_LINK_CHG) {
4833                         sblk->status = SD_STATUS_UPDATED |
4834                                        (sblk->status & ~SD_STATUS_LINK_CHG);
4835                         spin_lock(&tp->lock);
4836                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4837                                 tw32_f(MAC_STATUS,
4838                                      (MAC_STATUS_SYNC_CHANGED |
4839                                       MAC_STATUS_CFG_CHANGED |
4840                                       MAC_STATUS_MI_COMPLETION |
4841                                       MAC_STATUS_LNKSTATE_CHANGED));
4842                                 udelay(40);
4843                         } else
4844                                 tg3_setup_phy(tp, 0);
4845                         spin_unlock(&tp->lock);
4846                 }
4847         }
4848 }
4849
4850 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4851                                 struct tg3_rx_prodring_set *dpr,
4852                                 struct tg3_rx_prodring_set *spr)
4853 {
4854         u32 si, di, cpycnt, src_prod_idx;
4855         int i, err = 0;
4856
4857         while (1) {
4858                 src_prod_idx = spr->rx_std_prod_idx;
4859
4860                 /* Make sure updates to the rx_std_buffers[] entries and the
4861                  * standard producer index are seen in the correct order.
4862                  */
4863                 smp_rmb();
4864
4865                 if (spr->rx_std_cons_idx == src_prod_idx)
4866                         break;
4867
4868                 if (spr->rx_std_cons_idx < src_prod_idx)
4869                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4870                 else
4871                         cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4872
4873                 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4874
4875                 si = spr->rx_std_cons_idx;
4876                 di = dpr->rx_std_prod_idx;
4877
4878                 for (i = di; i < di + cpycnt; i++) {
4879                         if (dpr->rx_std_buffers[i].skb) {
4880                                 cpycnt = i - di;
4881                                 err = -ENOSPC;
4882                                 break;
4883                         }
4884                 }
4885
4886                 if (!cpycnt)
4887                         break;
4888
4889                 /* Ensure that updates to the rx_std_buffers ring and the
4890                  * shadowed hardware producer ring from tg3_recycle_skb() are
4891                  * ordered correctly WRT the skb check above.
4892                  */
4893                 smp_rmb();
4894
4895                 memcpy(&dpr->rx_std_buffers[di],
4896                        &spr->rx_std_buffers[si],
4897                        cpycnt * sizeof(struct ring_info));
4898
4899                 for (i = 0; i < cpycnt; i++, di++, si++) {
4900                         struct tg3_rx_buffer_desc *sbd, *dbd;
4901                         sbd = &spr->rx_std[si];
4902                         dbd = &dpr->rx_std[di];
4903                         dbd->addr_hi = sbd->addr_hi;
4904                         dbd->addr_lo = sbd->addr_lo;
4905                 }
4906
4907                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4908                                        TG3_RX_RING_SIZE;
4909                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4910                                        TG3_RX_RING_SIZE;
4911         }
4912
4913         while (1) {
4914                 src_prod_idx = spr->rx_jmb_prod_idx;
4915
4916                 /* Make sure updates to the rx_jmb_buffers[] entries and
4917                  * the jumbo producer index are seen in the correct order.
4918                  */
4919                 smp_rmb();
4920
4921                 if (spr->rx_jmb_cons_idx == src_prod_idx)
4922                         break;
4923
4924                 if (spr->rx_jmb_cons_idx < src_prod_idx)
4925                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4926                 else
4927                         cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4928
4929                 cpycnt = min(cpycnt,
4930                              TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4931
4932                 si = spr->rx_jmb_cons_idx;
4933                 di = dpr->rx_jmb_prod_idx;
4934
4935                 for (i = di; i < di + cpycnt; i++) {
4936                         if (dpr->rx_jmb_buffers[i].skb) {
4937                                 cpycnt = i - di;
4938                                 err = -ENOSPC;
4939                                 break;
4940                         }
4941                 }
4942
4943                 if (!cpycnt)
4944                         break;
4945
4946                 /* Ensure that updates to the rx_jmb_buffers ring and the
4947                  * shadowed hardware producer ring from tg3_recycle_skb() are
4948                  * ordered correctly WRT the skb check above.
4949                  */
4950                 smp_rmb();
4951
4952                 memcpy(&dpr->rx_jmb_buffers[di],
4953                        &spr->rx_jmb_buffers[si],
4954                        cpycnt * sizeof(struct ring_info));
4955
4956                 for (i = 0; i < cpycnt; i++, di++, si++) {
4957                         struct tg3_rx_buffer_desc *sbd, *dbd;
4958                         sbd = &spr->rx_jmb[si].std;
4959                         dbd = &dpr->rx_jmb[di].std;
4960                         dbd->addr_hi = sbd->addr_hi;
4961                         dbd->addr_lo = sbd->addr_lo;
4962                 }
4963
4964                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4965                                        TG3_RX_JUMBO_RING_SIZE;
4966                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4967                                        TG3_RX_JUMBO_RING_SIZE;
4968         }
4969
4970         return err;
4971 }
4972
4973 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4974 {
4975         struct tg3 *tp = tnapi->tp;
4976
4977         /* run TX completion thread */
4978         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4979                 tg3_tx(tnapi);
4980                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4981                         return work_done;
4982         }
4983
4984         /* run RX thread, within the bounds set by NAPI.
4985          * All RX "locking" is done by ensuring outside
4986          * code synchronizes with tg3->napi.poll()
4987          */
4988         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4989                 work_done += tg3_rx(tnapi, budget - work_done);
4990
4991         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4992                 struct tg3_rx_prodring_set *dpr = &tp->prodring[0];
4993                 int i, err = 0;
4994                 u32 std_prod_idx = dpr->rx_std_prod_idx;
4995                 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
4996
4997                 for (i = 1; i < tp->irq_cnt; i++)
4998                         err |= tg3_rx_prodring_xfer(tp, dpr,
4999                                                     tp->napi[i].prodring);
5000
5001                 wmb();
5002
5003                 if (std_prod_idx != dpr->rx_std_prod_idx)
5004                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5005                                      dpr->rx_std_prod_idx);
5006
5007                 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5008                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5009                                      dpr->rx_jmb_prod_idx);
5010
5011                 mmiowb();
5012
5013                 if (err)
5014                         tw32_f(HOSTCC_MODE, tp->coal_now);
5015         }
5016
5017         return work_done;
5018 }
5019
5020 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5021 {
5022         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5023         struct tg3 *tp = tnapi->tp;
5024         int work_done = 0;
5025         struct tg3_hw_status *sblk = tnapi->hw_status;
5026
5027         while (1) {
5028                 work_done = tg3_poll_work(tnapi, work_done, budget);
5029
5030                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5031                         goto tx_recovery;
5032
5033                 if (unlikely(work_done >= budget))
5034                         break;
5035
5036                 /* tp->last_tag is used in tg3_int_reenable() below
5037                  * to tell the hw how much work has been processed,
5038                  * so we must read it before checking for more work.
5039                  */
5040                 tnapi->last_tag = sblk->status_tag;
5041                 tnapi->last_irq_tag = tnapi->last_tag;
5042                 rmb();
5043
5044                 /* check for RX/TX work to do */
5045                 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5046                            *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5047                         napi_complete(napi);
5048                         /* Reenable interrupts. */
5049                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5050                         mmiowb();
5051                         break;
5052                 }
5053         }
5054
5055         return work_done;
5056
5057 tx_recovery:
5058         /* work_done is guaranteed to be less than budget. */
5059         napi_complete(napi);
5060         schedule_work(&tp->reset_task);
5061         return work_done;
5062 }
5063
5064 static int tg3_poll(struct napi_struct *napi, int budget)
5065 {
5066         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5067         struct tg3 *tp = tnapi->tp;
5068         int work_done = 0;
5069         struct tg3_hw_status *sblk = tnapi->hw_status;
5070
5071         while (1) {
5072                 tg3_poll_link(tp);
5073
5074                 work_done = tg3_poll_work(tnapi, work_done, budget);
5075
5076                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5077                         goto tx_recovery;
5078
5079                 if (unlikely(work_done >= budget))
5080                         break;
5081
5082                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5083                         /* tp->last_tag is used in tg3_int_reenable() below
5084                          * to tell the hw how much work has been processed,
5085                          * so we must read it before checking for more work.
5086                          */
5087                         tnapi->last_tag = sblk->status_tag;
5088                         tnapi->last_irq_tag = tnapi->last_tag;
5089                         rmb();
5090                 } else
5091                         sblk->status &= ~SD_STATUS_UPDATED;
5092
5093                 if (likely(!tg3_has_work(tnapi))) {
5094                         napi_complete(napi);
5095                         tg3_int_reenable(tnapi);
5096                         break;
5097                 }
5098         }
5099
5100         return work_done;
5101
5102 tx_recovery:
5103         /* work_done is guaranteed to be less than budget. */
5104         napi_complete(napi);
5105         schedule_work(&tp->reset_task);
5106         return work_done;
5107 }
5108
5109 static void tg3_irq_quiesce(struct tg3 *tp)
5110 {
5111         int i;
5112
5113         BUG_ON(tp->irq_sync);
5114
5115         tp->irq_sync = 1;
5116         smp_mb();
5117
5118         for (i = 0; i < tp->irq_cnt; i++)
5119                 synchronize_irq(tp->napi[i].irq_vec);
5120 }
5121
5122 static inline int tg3_irq_sync(struct tg3 *tp)
5123 {
5124         return tp->irq_sync;
5125 }
5126
5127 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5128  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5129  * with as well.  Most of the time, this is not necessary except when
5130  * shutting down the device.
5131  */
5132 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5133 {
5134         spin_lock_bh(&tp->lock);
5135         if (irq_sync)
5136                 tg3_irq_quiesce(tp);
5137 }
5138
5139 static inline void tg3_full_unlock(struct tg3 *tp)
5140 {
5141         spin_unlock_bh(&tp->lock);
5142 }
5143
5144 /* One-shot MSI handler - Chip automatically disables interrupt
5145  * after sending MSI so driver doesn't have to do it.
5146  */
5147 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5148 {
5149         struct tg3_napi *tnapi = dev_id;
5150         struct tg3 *tp = tnapi->tp;
5151
5152         prefetch(tnapi->hw_status);
5153         if (tnapi->rx_rcb)
5154                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5155
5156         if (likely(!tg3_irq_sync(tp)))
5157                 napi_schedule(&tnapi->napi);
5158
5159         return IRQ_HANDLED;
5160 }
5161
5162 /* MSI ISR - No need to check for interrupt sharing and no need to
5163  * flush status block and interrupt mailbox. PCI ordering rules
5164  * guarantee that MSI will arrive after the status block.
5165  */
5166 static irqreturn_t tg3_msi(int irq, void *dev_id)
5167 {
5168         struct tg3_napi *tnapi = dev_id;
5169         struct tg3 *tp = tnapi->tp;
5170
5171         prefetch(tnapi->hw_status);
5172         if (tnapi->rx_rcb)
5173                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5174         /*
5175          * Writing any value to intr-mbox-0 clears PCI INTA# and
5176          * chip-internal interrupt pending events.
5177          * Writing non-zero to intr-mbox-0 additional tells the
5178          * NIC to stop sending us irqs, engaging "in-intr-handler"
5179          * event coalescing.
5180          */
5181         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5182         if (likely(!tg3_irq_sync(tp)))
5183                 napi_schedule(&tnapi->napi);
5184
5185         return IRQ_RETVAL(1);
5186 }
5187
5188 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5189 {
5190         struct tg3_napi *tnapi = dev_id;
5191         struct tg3 *tp = tnapi->tp;
5192         struct tg3_hw_status *sblk = tnapi->hw_status;
5193         unsigned int handled = 1;
5194
5195         /* In INTx mode, it is possible for the interrupt to arrive at
5196          * the CPU before the status block posted prior to the interrupt.
5197          * Reading the PCI State register will confirm whether the
5198          * interrupt is ours and will flush the status block.
5199          */
5200         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5201                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5202                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5203                         handled = 0;
5204                         goto out;
5205                 }
5206         }
5207
5208         /*
5209          * Writing any value to intr-mbox-0 clears PCI INTA# and
5210          * chip-internal interrupt pending events.
5211          * Writing non-zero to intr-mbox-0 additional tells the
5212          * NIC to stop sending us irqs, engaging "in-intr-handler"
5213          * event coalescing.
5214          *
5215          * Flush the mailbox to de-assert the IRQ immediately to prevent
5216          * spurious interrupts.  The flush impacts performance but
5217          * excessive spurious interrupts can be worse in some cases.
5218          */
5219         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5220         if (tg3_irq_sync(tp))
5221                 goto out;
5222         sblk->status &= ~SD_STATUS_UPDATED;
5223         if (likely(tg3_has_work(tnapi))) {
5224                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5225                 napi_schedule(&tnapi->napi);
5226         } else {
5227                 /* No work, shared interrupt perhaps?  re-enable
5228                  * interrupts, and flush that PCI write
5229                  */
5230                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5231                                0x00000000);
5232         }
5233 out:
5234         return IRQ_RETVAL(handled);
5235 }
5236
5237 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5238 {
5239         struct tg3_napi *tnapi = dev_id;
5240         struct tg3 *tp = tnapi->tp;
5241         struct tg3_hw_status *sblk = tnapi->hw_status;
5242         unsigned int handled = 1;
5243
5244         /* In INTx mode, it is possible for the interrupt to arrive at
5245          * the CPU before the status block posted prior to the interrupt.
5246          * Reading the PCI State register will confirm whether the
5247          * interrupt is ours and will flush the status block.
5248          */
5249         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5250                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5251                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5252                         handled = 0;
5253                         goto out;
5254                 }
5255         }
5256
5257         /*
5258          * writing any value to intr-mbox-0 clears PCI INTA# and
5259          * chip-internal interrupt pending events.
5260          * writing non-zero to intr-mbox-0 additional tells the
5261          * NIC to stop sending us irqs, engaging "in-intr-handler"
5262          * event coalescing.
5263          *
5264          * Flush the mailbox to de-assert the IRQ immediately to prevent
5265          * spurious interrupts.  The flush impacts performance but
5266          * excessive spurious interrupts can be worse in some cases.
5267          */
5268         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5269
5270         /*
5271          * In a shared interrupt configuration, sometimes other devices'
5272          * interrupts will scream.  We record the current status tag here
5273          * so that the above check can report that the screaming interrupts
5274          * are unhandled.  Eventually they will be silenced.
5275          */
5276         tnapi->last_irq_tag = sblk->status_tag;
5277
5278         if (tg3_irq_sync(tp))
5279                 goto out;
5280
5281         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5282
5283         napi_schedule(&tnapi->napi);
5284
5285 out:
5286         return IRQ_RETVAL(handled);
5287 }
5288
5289 /* ISR for interrupt test */
5290 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5291 {
5292         struct tg3_napi *tnapi = dev_id;
5293         struct tg3 *tp = tnapi->tp;
5294         struct tg3_hw_status *sblk = tnapi->hw_status;
5295
5296         if ((sblk->status & SD_STATUS_UPDATED) ||
5297             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5298                 tg3_disable_ints(tp);
5299                 return IRQ_RETVAL(1);
5300         }
5301         return IRQ_RETVAL(0);
5302 }
5303
5304 static int tg3_init_hw(struct tg3 *, int);
5305 static int tg3_halt(struct tg3 *, int, int);
5306
5307 /* Restart hardware after configuration changes, self-test, etc.
5308  * Invoked with tp->lock held.
5309  */
5310 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5311         __releases(tp->lock)
5312         __acquires(tp->lock)
5313 {
5314         int err;
5315
5316         err = tg3_init_hw(tp, reset_phy);
5317         if (err) {
5318                 netdev_err(tp->dev,
5319                            "Failed to re-initialize device, aborting\n");
5320                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5321                 tg3_full_unlock(tp);
5322                 del_timer_sync(&tp->timer);
5323                 tp->irq_sync = 0;
5324                 tg3_napi_enable(tp);
5325                 dev_close(tp->dev);
5326                 tg3_full_lock(tp, 0);
5327         }
5328         return err;
5329 }
5330
5331 #ifdef CONFIG_NET_POLL_CONTROLLER
5332 static void tg3_poll_controller(struct net_device *dev)
5333 {
5334         int i;
5335         struct tg3 *tp = netdev_priv(dev);
5336
5337         for (i = 0; i < tp->irq_cnt; i++)
5338                 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5339 }
5340 #endif
5341
5342 static void tg3_reset_task(struct work_struct *work)
5343 {
5344         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5345         int err;
5346         unsigned int restart_timer;
5347
5348         tg3_full_lock(tp, 0);
5349
5350         if (!netif_running(tp->dev)) {
5351                 tg3_full_unlock(tp);
5352                 return;
5353         }
5354
5355         tg3_full_unlock(tp);
5356
5357         tg3_phy_stop(tp);
5358
5359         tg3_netif_stop(tp);
5360
5361         tg3_full_lock(tp, 1);
5362
5363         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5364         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5365
5366         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5367                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5368                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5369                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5370                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5371         }
5372
5373         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5374         err = tg3_init_hw(tp, 1);
5375         if (err)
5376                 goto out;
5377
5378         tg3_netif_start(tp);
5379
5380         if (restart_timer)
5381                 mod_timer(&tp->timer, jiffies + 1);
5382
5383 out:
5384         tg3_full_unlock(tp);
5385
5386         if (!err)
5387                 tg3_phy_start(tp);
5388 }
5389
5390 static void tg3_dump_short_state(struct tg3 *tp)
5391 {
5392         netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5393                    tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5394         netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5395                    tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5396 }
5397
5398 static void tg3_tx_timeout(struct net_device *dev)
5399 {
5400         struct tg3 *tp = netdev_priv(dev);
5401
5402         if (netif_msg_tx_err(tp)) {
5403                 netdev_err(dev, "transmit timed out, resetting\n");
5404                 tg3_dump_short_state(tp);
5405         }
5406
5407         schedule_work(&tp->reset_task);
5408 }
5409
5410 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5411 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5412 {
5413         u32 base = (u32) mapping & 0xffffffff;
5414
5415         return ((base > 0xffffdcc0) &&
5416                 (base + len + 8 < base));
5417 }
5418
5419 /* Test for DMA addresses > 40-bit */
5420 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5421                                           int len)
5422 {
5423 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5424         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5425                 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5426         return 0;
5427 #else
5428         return 0;
5429 #endif
5430 }
5431
5432 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5433
5434 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5435 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5436                                        struct sk_buff *skb, u32 last_plus_one,
5437                                        u32 *start, u32 base_flags, u32 mss)
5438 {
5439         struct tg3 *tp = tnapi->tp;
5440         struct sk_buff *new_skb;
5441         dma_addr_t new_addr = 0;
5442         u32 entry = *start;
5443         int i, ret = 0;
5444
5445         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5446                 new_skb = skb_copy(skb, GFP_ATOMIC);
5447         else {
5448                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5449
5450                 new_skb = skb_copy_expand(skb,
5451                                           skb_headroom(skb) + more_headroom,
5452                                           skb_tailroom(skb), GFP_ATOMIC);
5453         }
5454
5455         if (!new_skb) {
5456                 ret = -1;
5457         } else {
5458                 /* New SKB is guaranteed to be linear. */
5459                 entry = *start;
5460                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5461                                           PCI_DMA_TODEVICE);
5462                 /* Make sure the mapping succeeded */
5463                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5464                         ret = -1;
5465                         dev_kfree_skb(new_skb);
5466                         new_skb = NULL;
5467
5468                 /* Make sure new skb does not cross any 4G boundaries.
5469                  * Drop the packet if it does.
5470                  */
5471                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5472                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5473                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5474                                          PCI_DMA_TODEVICE);
5475                         ret = -1;
5476                         dev_kfree_skb(new_skb);
5477                         new_skb = NULL;
5478                 } else {
5479                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5480                                     base_flags, 1 | (mss << 1));
5481                         *start = NEXT_TX(entry);
5482                 }
5483         }
5484
5485         /* Now clean up the sw ring entries. */
5486         i = 0;
5487         while (entry != last_plus_one) {
5488                 int len;
5489
5490                 if (i == 0)
5491                         len = skb_headlen(skb);
5492                 else
5493                         len = skb_shinfo(skb)->frags[i-1].size;
5494
5495                 pci_unmap_single(tp->pdev,
5496                                  dma_unmap_addr(&tnapi->tx_buffers[entry],
5497                                                 mapping),
5498                                  len, PCI_DMA_TODEVICE);
5499                 if (i == 0) {
5500                         tnapi->tx_buffers[entry].skb = new_skb;
5501                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5502                                            new_addr);
5503                 } else {
5504                         tnapi->tx_buffers[entry].skb = NULL;
5505                 }
5506                 entry = NEXT_TX(entry);
5507                 i++;
5508         }
5509
5510         dev_kfree_skb(skb);
5511
5512         return ret;
5513 }
5514
5515 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5516                         dma_addr_t mapping, int len, u32 flags,
5517                         u32 mss_and_is_end)
5518 {
5519         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5520         int is_end = (mss_and_is_end & 0x1);
5521         u32 mss = (mss_and_is_end >> 1);
5522         u32 vlan_tag = 0;
5523
5524         if (is_end)
5525                 flags |= TXD_FLAG_END;
5526         if (flags & TXD_FLAG_VLAN) {
5527                 vlan_tag = flags >> 16;
5528                 flags &= 0xffff;
5529         }
5530         vlan_tag |= (mss << TXD_MSS_SHIFT);
5531
5532         txd->addr_hi = ((u64) mapping >> 32);
5533         txd->addr_lo = ((u64) mapping & 0xffffffff);
5534         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5535         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5536 }
5537
5538 /* hard_start_xmit for devices that don't have any bugs and
5539  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5540  */
5541 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5542                                   struct net_device *dev)
5543 {
5544         struct tg3 *tp = netdev_priv(dev);
5545         u32 len, entry, base_flags, mss;
5546         dma_addr_t mapping;
5547         struct tg3_napi *tnapi;
5548         struct netdev_queue *txq;
5549         unsigned int i, last;
5550
5551         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5552         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5553         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5554                 tnapi++;
5555
5556         /* We are running in BH disabled context with netif_tx_lock
5557          * and TX reclaim runs via tp->napi.poll inside of a software
5558          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5559          * no IRQ context deadlocks to worry about either.  Rejoice!
5560          */
5561         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5562                 if (!netif_tx_queue_stopped(txq)) {
5563                         netif_tx_stop_queue(txq);
5564
5565                         /* This is a hard error, log it. */
5566                         netdev_err(dev,
5567                                    "BUG! Tx Ring full when queue awake!\n");
5568                 }
5569                 return NETDEV_TX_BUSY;
5570         }
5571
5572         entry = tnapi->tx_prod;
5573         base_flags = 0;
5574         mss = skb_shinfo(skb)->gso_size;
5575         if (mss) {
5576                 int tcp_opt_len, ip_tcp_len;
5577                 u32 hdrlen;
5578
5579                 if (skb_header_cloned(skb) &&
5580                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5581                         dev_kfree_skb(skb);
5582                         goto out_unlock;
5583                 }
5584
5585                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5586                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5587                 else {
5588                         struct iphdr *iph = ip_hdr(skb);
5589
5590                         tcp_opt_len = tcp_optlen(skb);
5591                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5592
5593                         iph->check = 0;
5594                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5595                         hdrlen = ip_tcp_len + tcp_opt_len;
5596                 }
5597
5598                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5599                         mss |= (hdrlen & 0xc) << 12;
5600                         if (hdrlen & 0x10)
5601                                 base_flags |= 0x00000010;
5602                         base_flags |= (hdrlen & 0x3e0) << 5;
5603                 } else
5604                         mss |= hdrlen << 9;
5605
5606                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5607                                TXD_FLAG_CPU_POST_DMA);
5608
5609                 tcp_hdr(skb)->check = 0;
5610
5611         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5612                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5613         }
5614
5615 #if TG3_VLAN_TAG_USED
5616         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5617                 base_flags |= (TXD_FLAG_VLAN |
5618                                (vlan_tx_tag_get(skb) << 16));
5619 #endif
5620
5621         len = skb_headlen(skb);
5622
5623         /* Queue skb data, a.k.a. the main skb fragment. */
5624         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5625         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5626                 dev_kfree_skb(skb);
5627                 goto out_unlock;
5628         }
5629
5630         tnapi->tx_buffers[entry].skb = skb;
5631         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5632
5633         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5634             !mss && skb->len > ETH_DATA_LEN)
5635                 base_flags |= TXD_FLAG_JMB_PKT;
5636
5637         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5638                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5639
5640         entry = NEXT_TX(entry);
5641
5642         /* Now loop through additional data fragments, and queue them. */
5643         if (skb_shinfo(skb)->nr_frags > 0) {
5644                 last = skb_shinfo(skb)->nr_frags - 1;
5645                 for (i = 0; i <= last; i++) {
5646                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5647
5648                         len = frag->size;
5649                         mapping = pci_map_page(tp->pdev,
5650                                                frag->page,
5651                                                frag->page_offset,
5652                                                len, PCI_DMA_TODEVICE);
5653                         if (pci_dma_mapping_error(tp->pdev, mapping))
5654                                 goto dma_error;
5655
5656                         tnapi->tx_buffers[entry].skb = NULL;
5657                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5658                                            mapping);
5659
5660                         tg3_set_txd(tnapi, entry, mapping, len,
5661                                     base_flags, (i == last) | (mss << 1));
5662
5663                         entry = NEXT_TX(entry);
5664                 }
5665         }
5666
5667         /* Packets are ready, update Tx producer idx local and on card. */
5668         tw32_tx_mbox(tnapi->prodmbox, entry);
5669
5670         tnapi->tx_prod = entry;
5671         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5672                 netif_tx_stop_queue(txq);
5673                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5674                         netif_tx_wake_queue(txq);
5675         }
5676
5677 out_unlock:
5678         mmiowb();
5679
5680         return NETDEV_TX_OK;
5681
5682 dma_error:
5683         last = i;
5684         entry = tnapi->tx_prod;
5685         tnapi->tx_buffers[entry].skb = NULL;
5686         pci_unmap_single(tp->pdev,
5687                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5688                          skb_headlen(skb),
5689                          PCI_DMA_TODEVICE);
5690         for (i = 0; i <= last; i++) {
5691                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5692                 entry = NEXT_TX(entry);
5693
5694                 pci_unmap_page(tp->pdev,
5695                                dma_unmap_addr(&tnapi->tx_buffers[entry],
5696                                               mapping),
5697                                frag->size, PCI_DMA_TODEVICE);
5698         }
5699
5700         dev_kfree_skb(skb);
5701         return NETDEV_TX_OK;
5702 }
5703
5704 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5705                                           struct net_device *);
5706
5707 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5708  * TSO header is greater than 80 bytes.
5709  */
5710 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5711 {
5712         struct sk_buff *segs, *nskb;
5713         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5714
5715         /* Estimate the number of fragments in the worst case */
5716         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5717                 netif_stop_queue(tp->dev);
5718                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5719                         return NETDEV_TX_BUSY;
5720
5721                 netif_wake_queue(tp->dev);
5722         }
5723
5724         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5725         if (IS_ERR(segs))
5726                 goto tg3_tso_bug_end;
5727
5728         do {
5729                 nskb = segs;
5730                 segs = segs->next;
5731                 nskb->next = NULL;
5732                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5733         } while (segs);
5734
5735 tg3_tso_bug_end:
5736         dev_kfree_skb(skb);
5737
5738         return NETDEV_TX_OK;
5739 }
5740
5741 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5742  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5743  */
5744 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5745                                           struct net_device *dev)
5746 {
5747         struct tg3 *tp = netdev_priv(dev);
5748         u32 len, entry, base_flags, mss;
5749         int would_hit_hwbug;
5750         dma_addr_t mapping;
5751         struct tg3_napi *tnapi;
5752         struct netdev_queue *txq;
5753         unsigned int i, last;
5754
5755         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5756         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5757         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5758                 tnapi++;
5759
5760         /* We are running in BH disabled context with netif_tx_lock
5761          * and TX reclaim runs via tp->napi.poll inside of a software
5762          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5763          * no IRQ context deadlocks to worry about either.  Rejoice!
5764          */
5765         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5766                 if (!netif_tx_queue_stopped(txq)) {
5767                         netif_tx_stop_queue(txq);
5768
5769                         /* This is a hard error, log it. */
5770                         netdev_err(dev,
5771                                    "BUG! Tx Ring full when queue awake!\n");
5772                 }
5773                 return NETDEV_TX_BUSY;
5774         }
5775
5776         entry = tnapi->tx_prod;
5777         base_flags = 0;
5778         if (skb->ip_summed == CHECKSUM_PARTIAL)
5779                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5780
5781         mss = skb_shinfo(skb)->gso_size;
5782         if (mss) {
5783                 struct iphdr *iph;
5784                 u32 tcp_opt_len, hdr_len;
5785
5786                 if (skb_header_cloned(skb) &&
5787                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5788                         dev_kfree_skb(skb);
5789                         goto out_unlock;
5790                 }
5791
5792                 iph = ip_hdr(skb);
5793                 tcp_opt_len = tcp_optlen(skb);
5794
5795                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
5796                         hdr_len = skb_headlen(skb) - ETH_HLEN;
5797                 } else {
5798                         u32 ip_tcp_len;
5799
5800                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5801                         hdr_len = ip_tcp_len + tcp_opt_len;
5802
5803                         iph->check = 0;
5804                         iph->tot_len = htons(mss + hdr_len);
5805                 }
5806
5807                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5808                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5809                         return tg3_tso_bug(tp, skb);
5810
5811                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5812                                TXD_FLAG_CPU_POST_DMA);
5813
5814                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5815                         tcp_hdr(skb)->check = 0;
5816                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5817                 } else
5818                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5819                                                                  iph->daddr, 0,
5820                                                                  IPPROTO_TCP,
5821                                                                  0);
5822
5823                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5824                         mss |= (hdr_len & 0xc) << 12;
5825                         if (hdr_len & 0x10)
5826                                 base_flags |= 0x00000010;
5827                         base_flags |= (hdr_len & 0x3e0) << 5;
5828                 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5829                         mss |= hdr_len << 9;
5830                 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5831                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5832                         if (tcp_opt_len || iph->ihl > 5) {
5833                                 int tsflags;
5834
5835                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5836                                 mss |= (tsflags << 11);
5837                         }
5838                 } else {
5839                         if (tcp_opt_len || iph->ihl > 5) {
5840                                 int tsflags;
5841
5842                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5843                                 base_flags |= tsflags << 12;
5844                         }
5845                 }
5846         }
5847 #if TG3_VLAN_TAG_USED
5848         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5849                 base_flags |= (TXD_FLAG_VLAN |
5850                                (vlan_tx_tag_get(skb) << 16));
5851 #endif
5852
5853         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5854             !mss && skb->len > ETH_DATA_LEN)
5855                 base_flags |= TXD_FLAG_JMB_PKT;
5856
5857         len = skb_headlen(skb);
5858
5859         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5860         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5861                 dev_kfree_skb(skb);
5862                 goto out_unlock;
5863         }
5864
5865         tnapi->tx_buffers[entry].skb = skb;
5866         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5867
5868         would_hit_hwbug = 0;
5869
5870         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5871                 would_hit_hwbug = 1;
5872
5873         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5874             tg3_4g_overflow_test(mapping, len))
5875                 would_hit_hwbug = 1;
5876
5877         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5878             tg3_40bit_overflow_test(tp, mapping, len))
5879                 would_hit_hwbug = 1;
5880
5881         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5882                 would_hit_hwbug = 1;
5883
5884         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5885                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5886
5887         entry = NEXT_TX(entry);
5888
5889         /* Now loop through additional data fragments, and queue them. */
5890         if (skb_shinfo(skb)->nr_frags > 0) {
5891                 last = skb_shinfo(skb)->nr_frags - 1;
5892                 for (i = 0; i <= last; i++) {
5893                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5894
5895                         len = frag->size;
5896                         mapping = pci_map_page(tp->pdev,
5897                                                frag->page,
5898                                                frag->page_offset,
5899                                                len, PCI_DMA_TODEVICE);
5900
5901                         tnapi->tx_buffers[entry].skb = NULL;
5902                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5903                                            mapping);
5904                         if (pci_dma_mapping_error(tp->pdev, mapping))
5905                                 goto dma_error;
5906
5907                         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5908                             len <= 8)
5909                                 would_hit_hwbug = 1;
5910
5911                         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5912                             tg3_4g_overflow_test(mapping, len))
5913                                 would_hit_hwbug = 1;
5914
5915                         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5916                             tg3_40bit_overflow_test(tp, mapping, len))
5917                                 would_hit_hwbug = 1;
5918
5919                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5920                                 tg3_set_txd(tnapi, entry, mapping, len,
5921                                             base_flags, (i == last)|(mss << 1));
5922                         else
5923                                 tg3_set_txd(tnapi, entry, mapping, len,
5924                                             base_flags, (i == last));
5925
5926                         entry = NEXT_TX(entry);
5927                 }
5928         }
5929
5930         if (would_hit_hwbug) {
5931                 u32 last_plus_one = entry;
5932                 u32 start;
5933
5934                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5935                 start &= (TG3_TX_RING_SIZE - 1);
5936
5937                 /* If the workaround fails due to memory/mapping
5938                  * failure, silently drop this packet.
5939                  */
5940                 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
5941                                                 &start, base_flags, mss))
5942                         goto out_unlock;
5943
5944                 entry = start;
5945         }
5946
5947         /* Packets are ready, update Tx producer idx local and on card. */
5948         tw32_tx_mbox(tnapi->prodmbox, entry);
5949
5950         tnapi->tx_prod = entry;
5951         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5952                 netif_tx_stop_queue(txq);
5953                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5954                         netif_tx_wake_queue(txq);
5955         }
5956
5957 out_unlock:
5958         mmiowb();
5959
5960         return NETDEV_TX_OK;
5961
5962 dma_error:
5963         last = i;
5964         entry = tnapi->tx_prod;
5965         tnapi->tx_buffers[entry].skb = NULL;
5966         pci_unmap_single(tp->pdev,
5967                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5968                          skb_headlen(skb),
5969                          PCI_DMA_TODEVICE);
5970         for (i = 0; i <= last; i++) {
5971                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5972                 entry = NEXT_TX(entry);
5973
5974                 pci_unmap_page(tp->pdev,
5975                                dma_unmap_addr(&tnapi->tx_buffers[entry],
5976                                               mapping),
5977                                frag->size, PCI_DMA_TODEVICE);
5978         }
5979
5980         dev_kfree_skb(skb);
5981         return NETDEV_TX_OK;
5982 }
5983
5984 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5985                                int new_mtu)
5986 {
5987         dev->mtu = new_mtu;
5988
5989         if (new_mtu > ETH_DATA_LEN) {
5990                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5991                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5992                         ethtool_op_set_tso(dev, 0);
5993                 } else {
5994                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5995                 }
5996         } else {
5997                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5998                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5999                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
6000         }
6001 }
6002
6003 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
6004 {
6005         struct tg3 *tp = netdev_priv(dev);
6006         int err;
6007
6008         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
6009                 return -EINVAL;
6010
6011         if (!netif_running(dev)) {
6012                 /* We'll just catch it later when the
6013                  * device is up'd.
6014                  */
6015                 tg3_set_mtu(dev, tp, new_mtu);
6016                 return 0;
6017         }
6018
6019         tg3_phy_stop(tp);
6020
6021         tg3_netif_stop(tp);
6022
6023         tg3_full_lock(tp, 1);
6024
6025         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6026
6027         tg3_set_mtu(dev, tp, new_mtu);
6028
6029         err = tg3_restart_hw(tp, 0);
6030
6031         if (!err)
6032                 tg3_netif_start(tp);
6033
6034         tg3_full_unlock(tp);
6035
6036         if (!err)
6037                 tg3_phy_start(tp);
6038
6039         return err;
6040 }
6041
6042 static void tg3_rx_prodring_free(struct tg3 *tp,
6043                                  struct tg3_rx_prodring_set *tpr)
6044 {
6045         int i;
6046
6047         if (tpr != &tp->prodring[0]) {
6048                 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
6049                      i = (i + 1) % TG3_RX_RING_SIZE)
6050                         tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6051                                         tp->rx_pkt_map_sz);
6052
6053                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6054                         for (i = tpr->rx_jmb_cons_idx;
6055                              i != tpr->rx_jmb_prod_idx;
6056                              i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
6057                                 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6058                                                 TG3_RX_JMB_MAP_SZ);
6059                         }
6060                 }
6061
6062                 return;
6063         }
6064
6065         for (i = 0; i < TG3_RX_RING_SIZE; i++)
6066                 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6067                                 tp->rx_pkt_map_sz);
6068
6069         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6070                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
6071                         tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6072                                         TG3_RX_JMB_MAP_SZ);
6073         }
6074 }
6075
6076 /* Initialize rx rings for packet processing.
6077  *
6078  * The chip has been shut down and the driver detached from
6079  * the networking, so no interrupts or new tx packets will
6080  * end up in the driver.  tp->{tx,}lock are held and thus
6081  * we may not sleep.
6082  */
6083 static int tg3_rx_prodring_alloc(struct tg3 *tp,
6084                                  struct tg3_rx_prodring_set *tpr)
6085 {
6086         u32 i, rx_pkt_dma_sz;
6087
6088         tpr->rx_std_cons_idx = 0;
6089         tpr->rx_std_prod_idx = 0;
6090         tpr->rx_jmb_cons_idx = 0;
6091         tpr->rx_jmb_prod_idx = 0;
6092
6093         if (tpr != &tp->prodring[0]) {
6094                 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
6095                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
6096                         memset(&tpr->rx_jmb_buffers[0], 0,
6097                                TG3_RX_JMB_BUFF_RING_SIZE);
6098                 goto done;
6099         }
6100
6101         /* Zero out all descriptors. */
6102         memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
6103
6104         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6105         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
6106             tp->dev->mtu > ETH_DATA_LEN)
6107                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6108         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6109
6110         /* Initialize invariants of the rings, we only set this
6111          * stuff once.  This works because the card does not
6112          * write into the rx buffer posting rings.
6113          */
6114         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
6115                 struct tg3_rx_buffer_desc *rxd;
6116
6117                 rxd = &tpr->rx_std[i];
6118                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6119                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6120                 rxd->opaque = (RXD_OPAQUE_RING_STD |
6121                                (i << RXD_OPAQUE_INDEX_SHIFT));
6122         }
6123
6124         /* Now allocate fresh SKBs for each rx ring. */
6125         for (i = 0; i < tp->rx_pending; i++) {
6126                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6127                         netdev_warn(tp->dev,
6128                                     "Using a smaller RX standard ring. Only "
6129                                     "%d out of %d buffers were allocated "
6130                                     "successfully\n", i, tp->rx_pending);
6131                         if (i == 0)
6132                                 goto initfail;
6133                         tp->rx_pending = i;
6134                         break;
6135                 }
6136         }
6137
6138         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6139                 goto done;
6140
6141         memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
6142
6143         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
6144                 goto done;
6145
6146         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
6147                 struct tg3_rx_buffer_desc *rxd;
6148
6149                 rxd = &tpr->rx_jmb[i].std;
6150                 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6151                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6152                                   RXD_FLAG_JUMBO;
6153                 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6154                        (i << RXD_OPAQUE_INDEX_SHIFT));
6155         }
6156
6157         for (i = 0; i < tp->rx_jumbo_pending; i++) {
6158                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
6159                         netdev_warn(tp->dev,
6160                                     "Using a smaller RX jumbo ring. Only %d "
6161                                     "out of %d buffers were allocated "
6162                                     "successfully\n", i, tp->rx_jumbo_pending);
6163                         if (i == 0)
6164                                 goto initfail;
6165                         tp->rx_jumbo_pending = i;
6166                         break;
6167                 }
6168         }
6169
6170 done:
6171         return 0;
6172
6173 initfail:
6174         tg3_rx_prodring_free(tp, tpr);
6175         return -ENOMEM;
6176 }
6177
6178 static void tg3_rx_prodring_fini(struct tg3 *tp,
6179                                  struct tg3_rx_prodring_set *tpr)
6180 {
6181         kfree(tpr->rx_std_buffers);
6182         tpr->rx_std_buffers = NULL;
6183         kfree(tpr->rx_jmb_buffers);
6184         tpr->rx_jmb_buffers = NULL;
6185         if (tpr->rx_std) {
6186                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
6187                                     tpr->rx_std, tpr->rx_std_mapping);
6188                 tpr->rx_std = NULL;
6189         }
6190         if (tpr->rx_jmb) {
6191                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
6192                                     tpr->rx_jmb, tpr->rx_jmb_mapping);
6193                 tpr->rx_jmb = NULL;
6194         }
6195 }
6196
6197 static int tg3_rx_prodring_init(struct tg3 *tp,
6198                                 struct tg3_rx_prodring_set *tpr)
6199 {
6200         tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
6201         if (!tpr->rx_std_buffers)
6202                 return -ENOMEM;
6203
6204         tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6205                                            &tpr->rx_std_mapping);
6206         if (!tpr->rx_std)
6207                 goto err_out;
6208
6209         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6210                 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
6211                                               GFP_KERNEL);
6212                 if (!tpr->rx_jmb_buffers)
6213                         goto err_out;
6214
6215                 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6216                                                    TG3_RX_JUMBO_RING_BYTES,
6217                                                    &tpr->rx_jmb_mapping);
6218                 if (!tpr->rx_jmb)
6219                         goto err_out;
6220         }
6221
6222         return 0;
6223
6224 err_out:
6225         tg3_rx_prodring_fini(tp, tpr);
6226         return -ENOMEM;
6227 }
6228
6229 /* Free up pending packets in all rx/tx rings.
6230  *
6231  * The chip has been shut down and the driver detached from
6232  * the networking, so no interrupts or new tx packets will
6233  * end up in the driver.  tp->{tx,}lock is not held and we are not
6234  * in an interrupt context and thus may sleep.
6235  */
6236 static void tg3_free_rings(struct tg3 *tp)
6237 {
6238         int i, j;
6239
6240         for (j = 0; j < tp->irq_cnt; j++) {
6241                 struct tg3_napi *tnapi = &tp->napi[j];
6242
6243                 tg3_rx_prodring_free(tp, &tp->prodring[j]);
6244
6245                 if (!tnapi->tx_buffers)
6246                         continue;
6247
6248                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6249                         struct ring_info *txp;
6250                         struct sk_buff *skb;
6251                         unsigned int k;
6252
6253                         txp = &tnapi->tx_buffers[i];
6254                         skb = txp->skb;
6255
6256                         if (skb == NULL) {
6257                                 i++;
6258                                 continue;
6259                         }
6260
6261                         pci_unmap_single(tp->pdev,
6262                                          dma_unmap_addr(txp, mapping),
6263                                          skb_headlen(skb),
6264                                          PCI_DMA_TODEVICE);
6265                         txp->skb = NULL;
6266
6267                         i++;
6268
6269                         for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6270                                 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6271                                 pci_unmap_page(tp->pdev,
6272                                                dma_unmap_addr(txp, mapping),
6273                                                skb_shinfo(skb)->frags[k].size,
6274                                                PCI_DMA_TODEVICE);
6275                                 i++;
6276                         }
6277
6278                         dev_kfree_skb_any(skb);
6279                 }
6280         }
6281 }
6282
6283 /* Initialize tx/rx rings for packet processing.
6284  *
6285  * The chip has been shut down and the driver detached from
6286  * the networking, so no interrupts or new tx packets will
6287  * end up in the driver.  tp->{tx,}lock are held and thus
6288  * we may not sleep.
6289  */
6290 static int tg3_init_rings(struct tg3 *tp)
6291 {
6292         int i;
6293
6294         /* Free up all the SKBs. */
6295         tg3_free_rings(tp);
6296
6297         for (i = 0; i < tp->irq_cnt; i++) {
6298                 struct tg3_napi *tnapi = &tp->napi[i];
6299
6300                 tnapi->last_tag = 0;
6301                 tnapi->last_irq_tag = 0;
6302                 tnapi->hw_status->status = 0;
6303                 tnapi->hw_status->status_tag = 0;
6304                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6305
6306                 tnapi->tx_prod = 0;
6307                 tnapi->tx_cons = 0;
6308                 if (tnapi->tx_ring)
6309                         memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6310
6311                 tnapi->rx_rcb_ptr = 0;
6312                 if (tnapi->rx_rcb)
6313                         memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6314
6315                 if (tg3_rx_prodring_alloc(tp, &tp->prodring[i])) {
6316                         tg3_free_rings(tp);
6317                         return -ENOMEM;
6318                 }
6319         }
6320
6321         return 0;
6322 }
6323
6324 /*
6325  * Must not be invoked with interrupt sources disabled and
6326  * the hardware shutdown down.
6327  */
6328 static void tg3_free_consistent(struct tg3 *tp)
6329 {
6330         int i;
6331
6332         for (i = 0; i < tp->irq_cnt; i++) {
6333                 struct tg3_napi *tnapi = &tp->napi[i];
6334
6335                 if (tnapi->tx_ring) {
6336                         pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6337                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
6338                         tnapi->tx_ring = NULL;
6339                 }
6340
6341                 kfree(tnapi->tx_buffers);
6342                 tnapi->tx_buffers = NULL;
6343
6344                 if (tnapi->rx_rcb) {
6345                         pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6346                                             tnapi->rx_rcb,
6347                                             tnapi->rx_rcb_mapping);
6348                         tnapi->rx_rcb = NULL;
6349                 }
6350
6351                 if (tnapi->hw_status) {
6352                         pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6353                                             tnapi->hw_status,
6354                                             tnapi->status_mapping);
6355                         tnapi->hw_status = NULL;
6356                 }
6357         }
6358
6359         if (tp->hw_stats) {
6360                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6361                                     tp->hw_stats, tp->stats_mapping);
6362                 tp->hw_stats = NULL;
6363         }
6364
6365         for (i = 0; i < tp->irq_cnt; i++)
6366                 tg3_rx_prodring_fini(tp, &tp->prodring[i]);
6367 }
6368
6369 /*
6370  * Must not be invoked with interrupt sources disabled and
6371  * the hardware shutdown down.  Can sleep.
6372  */
6373 static int tg3_alloc_consistent(struct tg3 *tp)
6374 {
6375         int i;
6376
6377         for (i = 0; i < tp->irq_cnt; i++) {
6378                 if (tg3_rx_prodring_init(tp, &tp->prodring[i]))
6379                         goto err_out;
6380         }
6381
6382         tp->hw_stats = pci_alloc_consistent(tp->pdev,
6383                                             sizeof(struct tg3_hw_stats),
6384                                             &tp->stats_mapping);
6385         if (!tp->hw_stats)
6386                 goto err_out;
6387
6388         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6389
6390         for (i = 0; i < tp->irq_cnt; i++) {
6391                 struct tg3_napi *tnapi = &tp->napi[i];
6392                 struct tg3_hw_status *sblk;
6393
6394                 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6395                                                         TG3_HW_STATUS_SIZE,
6396                                                         &tnapi->status_mapping);
6397                 if (!tnapi->hw_status)
6398                         goto err_out;
6399
6400                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6401                 sblk = tnapi->hw_status;
6402
6403                 /* If multivector TSS is enabled, vector 0 does not handle
6404                  * tx interrupts.  Don't allocate any resources for it.
6405                  */
6406                 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6407                     (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6408                         tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6409                                                     TG3_TX_RING_SIZE,
6410                                                     GFP_KERNEL);
6411                         if (!tnapi->tx_buffers)
6412                                 goto err_out;
6413
6414                         tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6415                                                               TG3_TX_RING_BYTES,
6416                                                        &tnapi->tx_desc_mapping);
6417                         if (!tnapi->tx_ring)
6418                                 goto err_out;
6419                 }
6420
6421                 /*
6422                  * When RSS is enabled, the status block format changes
6423                  * slightly.  The "rx_jumbo_consumer", "reserved",
6424                  * and "rx_mini_consumer" members get mapped to the
6425                  * other three rx return ring producer indexes.
6426                  */
6427                 switch (i) {
6428                 default:
6429                         tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6430                         break;
6431                 case 2:
6432                         tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6433                         break;
6434                 case 3:
6435                         tnapi->rx_rcb_prod_idx = &sblk->reserved;
6436                         break;
6437                 case 4:
6438                         tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6439                         break;
6440                 }
6441
6442                 tnapi->prodring = &tp->prodring[i];
6443
6444                 /*
6445                  * If multivector RSS is enabled, vector 0 does not handle
6446                  * rx or tx interrupts.  Don't allocate any resources for it.
6447                  */
6448                 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6449                         continue;
6450
6451                 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6452                                                      TG3_RX_RCB_RING_BYTES(tp),
6453                                                      &tnapi->rx_rcb_mapping);
6454                 if (!tnapi->rx_rcb)
6455                         goto err_out;
6456
6457                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6458         }
6459
6460         return 0;
6461
6462 err_out:
6463         tg3_free_consistent(tp);
6464         return -ENOMEM;
6465 }
6466
6467 #define MAX_WAIT_CNT 1000
6468
6469 /* To stop a block, clear the enable bit and poll till it
6470  * clears.  tp->lock is held.
6471  */
6472 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6473 {
6474         unsigned int i;
6475         u32 val;
6476
6477         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6478                 switch (ofs) {
6479                 case RCVLSC_MODE:
6480                 case DMAC_MODE:
6481                 case MBFREE_MODE:
6482                 case BUFMGR_MODE:
6483                 case MEMARB_MODE:
6484                         /* We can't enable/disable these bits of the
6485                          * 5705/5750, just say success.
6486                          */
6487                         return 0;
6488
6489                 default:
6490                         break;
6491                 }
6492         }
6493
6494         val = tr32(ofs);
6495         val &= ~enable_bit;
6496         tw32_f(ofs, val);
6497
6498         for (i = 0; i < MAX_WAIT_CNT; i++) {
6499                 udelay(100);
6500                 val = tr32(ofs);
6501                 if ((val & enable_bit) == 0)
6502                         break;
6503         }
6504
6505         if (i == MAX_WAIT_CNT && !silent) {
6506                 dev_err(&tp->pdev->dev,
6507                         "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6508                         ofs, enable_bit);
6509                 return -ENODEV;
6510         }
6511
6512         return 0;
6513 }
6514
6515 /* tp->lock is held. */
6516 static int tg3_abort_hw(struct tg3 *tp, int silent)
6517 {
6518         int i, err;
6519
6520         tg3_disable_ints(tp);
6521
6522         tp->rx_mode &= ~RX_MODE_ENABLE;
6523         tw32_f(MAC_RX_MODE, tp->rx_mode);
6524         udelay(10);
6525
6526         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6527         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6528         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6529         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6530         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6531         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6532
6533         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6534         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6535         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6536         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6537         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6538         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6539         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6540
6541         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6542         tw32_f(MAC_MODE, tp->mac_mode);
6543         udelay(40);
6544
6545         tp->tx_mode &= ~TX_MODE_ENABLE;
6546         tw32_f(MAC_TX_MODE, tp->tx_mode);
6547
6548         for (i = 0; i < MAX_WAIT_CNT; i++) {
6549                 udelay(100);
6550                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6551                         break;
6552         }
6553         if (i >= MAX_WAIT_CNT) {
6554                 dev_err(&tp->pdev->dev,
6555                         "%s timed out, TX_MODE_ENABLE will not clear "
6556                         "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
6557                 err |= -ENODEV;
6558         }
6559
6560         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6561         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6562         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6563
6564         tw32(FTQ_RESET, 0xffffffff);
6565         tw32(FTQ_RESET, 0x00000000);
6566
6567         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6568         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6569
6570         for (i = 0; i < tp->irq_cnt; i++) {
6571                 struct tg3_napi *tnapi = &tp->napi[i];
6572                 if (tnapi->hw_status)
6573                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6574         }
6575         if (tp->hw_stats)
6576                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6577
6578         return err;
6579 }
6580
6581 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6582 {
6583         int i;
6584         u32 apedata;
6585
6586         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6587         if (apedata != APE_SEG_SIG_MAGIC)
6588                 return;
6589
6590         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6591         if (!(apedata & APE_FW_STATUS_READY))
6592                 return;
6593
6594         /* Wait for up to 1 millisecond for APE to service previous event. */
6595         for (i = 0; i < 10; i++) {
6596                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6597                         return;
6598
6599                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6600
6601                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6602                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6603                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6604
6605                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6606
6607                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6608                         break;
6609
6610                 udelay(100);
6611         }
6612
6613         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6614                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6615 }
6616
6617 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6618 {
6619         u32 event;
6620         u32 apedata;
6621
6622         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6623                 return;
6624
6625         switch (kind) {
6626         case RESET_KIND_INIT:
6627                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6628                                 APE_HOST_SEG_SIG_MAGIC);
6629                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6630                                 APE_HOST_SEG_LEN_MAGIC);
6631                 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6632                 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6633                 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6634                         APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
6635                 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6636                                 APE_HOST_BEHAV_NO_PHYLOCK);
6637
6638                 event = APE_EVENT_STATUS_STATE_START;
6639                 break;
6640         case RESET_KIND_SHUTDOWN:
6641                 /* With the interface we are currently using,
6642                  * APE does not track driver state.  Wiping
6643                  * out the HOST SEGMENT SIGNATURE forces
6644                  * the APE to assume OS absent status.
6645                  */
6646                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6647
6648                 event = APE_EVENT_STATUS_STATE_UNLOAD;
6649                 break;
6650         case RESET_KIND_SUSPEND:
6651                 event = APE_EVENT_STATUS_STATE_SUSPEND;
6652                 break;
6653         default:
6654                 return;
6655         }
6656
6657         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6658
6659         tg3_ape_send_event(tp, event);
6660 }
6661
6662 /* tp->lock is held. */
6663 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6664 {
6665         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6666                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6667
6668         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6669                 switch (kind) {
6670                 case RESET_KIND_INIT:
6671                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6672                                       DRV_STATE_START);
6673                         break;
6674
6675                 case RESET_KIND_SHUTDOWN:
6676                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6677                                       DRV_STATE_UNLOAD);
6678                         break;
6679
6680                 case RESET_KIND_SUSPEND:
6681                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6682                                       DRV_STATE_SUSPEND);
6683                         break;
6684
6685                 default:
6686                         break;
6687                 }
6688         }
6689
6690         if (kind == RESET_KIND_INIT ||
6691             kind == RESET_KIND_SUSPEND)
6692                 tg3_ape_driver_state_change(tp, kind);
6693 }
6694
6695 /* tp->lock is held. */
6696 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6697 {
6698         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6699                 switch (kind) {
6700                 case RESET_KIND_INIT:
6701                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6702                                       DRV_STATE_START_DONE);
6703                         break;
6704
6705                 case RESET_KIND_SHUTDOWN:
6706                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6707                                       DRV_STATE_UNLOAD_DONE);
6708                         break;
6709
6710                 default:
6711                         break;
6712                 }
6713         }
6714
6715         if (kind == RESET_KIND_SHUTDOWN)
6716                 tg3_ape_driver_state_change(tp, kind);
6717 }
6718
6719 /* tp->lock is held. */
6720 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6721 {
6722         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6723                 switch (kind) {
6724                 case RESET_KIND_INIT:
6725                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6726                                       DRV_STATE_START);
6727                         break;
6728
6729                 case RESET_KIND_SHUTDOWN:
6730                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6731                                       DRV_STATE_UNLOAD);
6732                         break;
6733
6734                 case RESET_KIND_SUSPEND:
6735                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6736                                       DRV_STATE_SUSPEND);
6737                         break;
6738
6739                 default:
6740                         break;
6741                 }
6742         }
6743 }
6744
6745 static int tg3_poll_fw(struct tg3 *tp)
6746 {
6747         int i;
6748         u32 val;
6749
6750         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6751                 /* Wait up to 20ms for init done. */
6752                 for (i = 0; i < 200; i++) {
6753                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6754                                 return 0;
6755                         udelay(100);
6756                 }
6757                 return -ENODEV;
6758         }
6759
6760         /* Wait for firmware initialization to complete. */
6761         for (i = 0; i < 100000; i++) {
6762                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6763                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6764                         break;
6765                 udelay(10);
6766         }
6767
6768         /* Chip might not be fitted with firmware.  Some Sun onboard
6769          * parts are configured like that.  So don't signal the timeout
6770          * of the above loop as an error, but do report the lack of
6771          * running firmware once.
6772          */
6773         if (i >= 100000 &&
6774             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6775                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6776
6777                 netdev_info(tp->dev, "No firmware running\n");
6778         }
6779
6780         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6781                 /* The 57765 A0 needs a little more
6782                  * time to do some important work.
6783                  */
6784                 mdelay(10);
6785         }
6786
6787         return 0;
6788 }
6789
6790 /* Save PCI command register before chip reset */
6791 static void tg3_save_pci_state(struct tg3 *tp)
6792 {
6793         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6794 }
6795
6796 /* Restore PCI state after chip reset */
6797 static void tg3_restore_pci_state(struct tg3 *tp)
6798 {
6799         u32 val;
6800
6801         /* Re-enable indirect register accesses. */
6802         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6803                                tp->misc_host_ctrl);
6804
6805         /* Set MAX PCI retry to zero. */
6806         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6807         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6808             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6809                 val |= PCISTATE_RETRY_SAME_DMA;
6810         /* Allow reads and writes to the APE register and memory space. */
6811         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6812                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6813                        PCISTATE_ALLOW_APE_SHMEM_WR |
6814                        PCISTATE_ALLOW_APE_PSPACE_WR;
6815         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6816
6817         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6818
6819         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6820                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6821                         pcie_set_readrq(tp->pdev, 4096);
6822                 else {
6823                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6824                                               tp->pci_cacheline_sz);
6825                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6826                                               tp->pci_lat_timer);
6827                 }
6828         }
6829
6830         /* Make sure PCI-X relaxed ordering bit is clear. */
6831         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6832                 u16 pcix_cmd;
6833
6834                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6835                                      &pcix_cmd);
6836                 pcix_cmd &= ~PCI_X_CMD_ERO;
6837                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6838                                       pcix_cmd);
6839         }
6840
6841         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6842
6843                 /* Chip reset on 5780 will reset MSI enable bit,
6844                  * so need to restore it.
6845                  */
6846                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6847                         u16 ctrl;
6848
6849                         pci_read_config_word(tp->pdev,
6850                                              tp->msi_cap + PCI_MSI_FLAGS,
6851                                              &ctrl);
6852                         pci_write_config_word(tp->pdev,
6853                                               tp->msi_cap + PCI_MSI_FLAGS,
6854                                               ctrl | PCI_MSI_FLAGS_ENABLE);
6855                         val = tr32(MSGINT_MODE);
6856                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6857                 }
6858         }
6859 }
6860
6861 static void tg3_stop_fw(struct tg3 *);
6862
6863 /* tp->lock is held. */
6864 static int tg3_chip_reset(struct tg3 *tp)
6865 {
6866         u32 val;
6867         void (*write_op)(struct tg3 *, u32, u32);
6868         int i, err;
6869
6870         tg3_nvram_lock(tp);
6871
6872         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6873
6874         /* No matching tg3_nvram_unlock() after this because
6875          * chip reset below will undo the nvram lock.
6876          */
6877         tp->nvram_lock_cnt = 0;
6878
6879         /* GRC_MISC_CFG core clock reset will clear the memory
6880          * enable bit in PCI register 4 and the MSI enable bit
6881          * on some chips, so we save relevant registers here.
6882          */
6883         tg3_save_pci_state(tp);
6884
6885         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6886             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6887                 tw32(GRC_FASTBOOT_PC, 0);
6888
6889         /*
6890          * We must avoid the readl() that normally takes place.
6891          * It locks machines, causes machine checks, and other
6892          * fun things.  So, temporarily disable the 5701
6893          * hardware workaround, while we do the reset.
6894          */
6895         write_op = tp->write32;
6896         if (write_op == tg3_write_flush_reg32)
6897                 tp->write32 = tg3_write32;
6898
6899         /* Prevent the irq handler from reading or writing PCI registers
6900          * during chip reset when the memory enable bit in the PCI command
6901          * register may be cleared.  The chip does not generate interrupt
6902          * at this time, but the irq handler may still be called due to irq
6903          * sharing or irqpoll.
6904          */
6905         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6906         for (i = 0; i < tp->irq_cnt; i++) {
6907                 struct tg3_napi *tnapi = &tp->napi[i];
6908                 if (tnapi->hw_status) {
6909                         tnapi->hw_status->status = 0;
6910                         tnapi->hw_status->status_tag = 0;
6911                 }
6912                 tnapi->last_tag = 0;
6913                 tnapi->last_irq_tag = 0;
6914         }
6915         smp_mb();
6916
6917         for (i = 0; i < tp->irq_cnt; i++)
6918                 synchronize_irq(tp->napi[i].irq_vec);
6919
6920         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6921                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6922                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6923         }
6924
6925         /* do the reset */
6926         val = GRC_MISC_CFG_CORECLK_RESET;
6927
6928         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6929                 /* Force PCIe 1.0a mode */
6930                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
6931                     !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
6932                     tr32(TG3_PCIE_PHY_TSTCTL) ==
6933                     (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
6934                         tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
6935
6936                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6937                         tw32(GRC_MISC_CFG, (1 << 29));
6938                         val |= (1 << 29);
6939                 }
6940         }
6941
6942         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6943                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6944                 tw32(GRC_VCPU_EXT_CTRL,
6945                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6946         }
6947
6948         /* Manage gphy power for all CPMU absent PCIe devices. */
6949         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6950             !(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
6951                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6952
6953         tw32(GRC_MISC_CFG, val);
6954
6955         /* restore 5701 hardware bug workaround write method */
6956         tp->write32 = write_op;
6957
6958         /* Unfortunately, we have to delay before the PCI read back.
6959          * Some 575X chips even will not respond to a PCI cfg access
6960          * when the reset command is given to the chip.
6961          *
6962          * How do these hardware designers expect things to work
6963          * properly if the PCI write is posted for a long period
6964          * of time?  It is always necessary to have some method by
6965          * which a register read back can occur to push the write
6966          * out which does the reset.
6967          *
6968          * For most tg3 variants the trick below was working.
6969          * Ho hum...
6970          */
6971         udelay(120);
6972
6973         /* Flush PCI posted writes.  The normal MMIO registers
6974          * are inaccessible at this time so this is the only
6975          * way to make this reliably (actually, this is no longer
6976          * the case, see above).  I tried to use indirect
6977          * register read/write but this upset some 5701 variants.
6978          */
6979         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6980
6981         udelay(120);
6982
6983         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6984                 u16 val16;
6985
6986                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6987                         int i;
6988                         u32 cfg_val;
6989
6990                         /* Wait for link training to complete.  */
6991                         for (i = 0; i < 5000; i++)
6992                                 udelay(100);
6993
6994                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6995                         pci_write_config_dword(tp->pdev, 0xc4,
6996                                                cfg_val | (1 << 15));
6997                 }
6998
6999                 /* Clear the "no snoop" and "relaxed ordering" bits. */
7000                 pci_read_config_word(tp->pdev,
7001                                      tp->pcie_cap + PCI_EXP_DEVCTL,
7002                                      &val16);
7003                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
7004                            PCI_EXP_DEVCTL_NOSNOOP_EN);
7005                 /*
7006                  * Older PCIe devices only support the 128 byte
7007                  * MPS setting.  Enforce the restriction.
7008                  */
7009                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7010                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
7011                 pci_write_config_word(tp->pdev,
7012                                       tp->pcie_cap + PCI_EXP_DEVCTL,
7013                                       val16);
7014
7015                 pcie_set_readrq(tp->pdev, 4096);
7016
7017                 /* Clear error status */
7018                 pci_write_config_word(tp->pdev,
7019                                       tp->pcie_cap + PCI_EXP_DEVSTA,
7020                                       PCI_EXP_DEVSTA_CED |
7021                                       PCI_EXP_DEVSTA_NFED |
7022                                       PCI_EXP_DEVSTA_FED |
7023                                       PCI_EXP_DEVSTA_URD);
7024         }
7025
7026         tg3_restore_pci_state(tp);
7027
7028         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
7029
7030         val = 0;
7031         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
7032                 val = tr32(MEMARB_MODE);
7033         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7034
7035         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7036                 tg3_stop_fw(tp);
7037                 tw32(0x5000, 0x400);
7038         }
7039
7040         tw32(GRC_MODE, tp->grc_mode);
7041
7042         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
7043                 val = tr32(0xc4);
7044
7045                 tw32(0xc4, val | (1 << 15));
7046         }
7047
7048         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7049             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7050                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7051                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7052                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7053                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7054         }
7055
7056         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7057                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
7058                 tw32_f(MAC_MODE, tp->mac_mode);
7059         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7060                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
7061                 tw32_f(MAC_MODE, tp->mac_mode);
7062         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7063                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
7064                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
7065                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
7066                 tw32_f(MAC_MODE, tp->mac_mode);
7067         } else
7068                 tw32_f(MAC_MODE, 0);
7069         udelay(40);
7070
7071         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7072
7073         err = tg3_poll_fw(tp);
7074         if (err)
7075                 return err;
7076
7077         tg3_mdio_start(tp);
7078
7079         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
7080             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7081             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7082             !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
7083                 val = tr32(0x7c00);
7084
7085                 tw32(0x7c00, val | (1 << 25));
7086         }
7087
7088         /* Reprobe ASF enable state.  */
7089         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7090         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7091         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7092         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7093                 u32 nic_cfg;
7094
7095                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7096                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7097                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7098                         tp->last_event_jiffies = jiffies;
7099                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7100                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7101                 }
7102         }
7103
7104         return 0;
7105 }
7106
7107 /* tp->lock is held. */
7108 static void tg3_stop_fw(struct tg3 *tp)
7109 {
7110         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7111            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7112                 /* Wait for RX cpu to ACK the previous event. */
7113                 tg3_wait_for_event_ack(tp);
7114
7115                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7116
7117                 tg3_generate_fw_event(tp);
7118
7119                 /* Wait for RX cpu to ACK this event. */
7120                 tg3_wait_for_event_ack(tp);
7121         }
7122 }
7123
7124 /* tp->lock is held. */
7125 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7126 {
7127         int err;
7128
7129         tg3_stop_fw(tp);
7130
7131         tg3_write_sig_pre_reset(tp, kind);
7132
7133         tg3_abort_hw(tp, silent);
7134         err = tg3_chip_reset(tp);
7135
7136         __tg3_set_mac_addr(tp, 0);
7137
7138         tg3_write_sig_legacy(tp, kind);
7139         tg3_write_sig_post_reset(tp, kind);
7140
7141         if (err)
7142                 return err;
7143
7144         return 0;
7145 }
7146
7147 #define RX_CPU_SCRATCH_BASE     0x30000
7148 #define RX_CPU_SCRATCH_SIZE     0x04000
7149 #define TX_CPU_SCRATCH_BASE     0x34000
7150 #define TX_CPU_SCRATCH_SIZE     0x04000
7151
7152 /* tp->lock is held. */
7153 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7154 {
7155         int i;
7156
7157         BUG_ON(offset == TX_CPU_BASE &&
7158             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7159
7160         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7161                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7162
7163                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7164                 return 0;
7165         }
7166         if (offset == RX_CPU_BASE) {
7167                 for (i = 0; i < 10000; i++) {
7168                         tw32(offset + CPU_STATE, 0xffffffff);
7169                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7170                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7171                                 break;
7172                 }
7173
7174                 tw32(offset + CPU_STATE, 0xffffffff);
7175                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
7176                 udelay(10);
7177         } else {
7178                 for (i = 0; i < 10000; i++) {
7179                         tw32(offset + CPU_STATE, 0xffffffff);
7180                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7181                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7182                                 break;
7183                 }
7184         }
7185
7186         if (i >= 10000) {
7187                 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7188                            __func__, offset == RX_CPU_BASE ? "RX" : "TX");
7189                 return -ENODEV;
7190         }
7191
7192         /* Clear firmware's nvram arbitration. */
7193         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7194                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7195         return 0;
7196 }
7197
7198 struct fw_info {
7199         unsigned int fw_base;
7200         unsigned int fw_len;
7201         const __be32 *fw_data;
7202 };
7203
7204 /* tp->lock is held. */
7205 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7206                                  int cpu_scratch_size, struct fw_info *info)
7207 {
7208         int err, lock_err, i;
7209         void (*write_op)(struct tg3 *, u32, u32);
7210
7211         if (cpu_base == TX_CPU_BASE &&
7212             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7213                 netdev_err(tp->dev,
7214                            "%s: Trying to load TX cpu firmware which is 5705\n",
7215                            __func__);
7216                 return -EINVAL;
7217         }
7218
7219         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7220                 write_op = tg3_write_mem;
7221         else
7222                 write_op = tg3_write_indirect_reg32;
7223
7224         /* It is possible that bootcode is still loading at this point.
7225          * Get the nvram lock first before halting the cpu.
7226          */
7227         lock_err = tg3_nvram_lock(tp);
7228         err = tg3_halt_cpu(tp, cpu_base);
7229         if (!lock_err)
7230                 tg3_nvram_unlock(tp);
7231         if (err)
7232                 goto out;
7233
7234         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7235                 write_op(tp, cpu_scratch_base + i, 0);
7236         tw32(cpu_base + CPU_STATE, 0xffffffff);
7237         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7238         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7239                 write_op(tp, (cpu_scratch_base +
7240                               (info->fw_base & 0xffff) +
7241                               (i * sizeof(u32))),
7242                               be32_to_cpu(info->fw_data[i]));
7243
7244         err = 0;
7245
7246 out:
7247         return err;
7248 }
7249
7250 /* tp->lock is held. */
7251 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7252 {
7253         struct fw_info info;
7254         const __be32 *fw_data;
7255         int err, i;
7256
7257         fw_data = (void *)tp->fw->data;
7258
7259         /* Firmware blob starts with version numbers, followed by
7260            start address and length. We are setting complete length.
7261            length = end_address_of_bss - start_address_of_text.
7262            Remainder is the blob to be loaded contiguously
7263            from start address. */
7264
7265         info.fw_base = be32_to_cpu(fw_data[1]);
7266         info.fw_len = tp->fw->size - 12;
7267         info.fw_data = &fw_data[3];
7268
7269         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7270                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7271                                     &info);
7272         if (err)
7273                 return err;
7274
7275         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7276                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7277                                     &info);
7278         if (err)
7279                 return err;
7280
7281         /* Now startup only the RX cpu. */
7282         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7283         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7284
7285         for (i = 0; i < 5; i++) {
7286                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7287                         break;
7288                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7289                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
7290                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7291                 udelay(1000);
7292         }
7293         if (i >= 5) {
7294                 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7295                            "should be %08x\n", __func__,
7296                            tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
7297                 return -ENODEV;
7298         }
7299         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7300         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
7301
7302         return 0;
7303 }
7304
7305 /* 5705 needs a special version of the TSO firmware.  */
7306
7307 /* tp->lock is held. */
7308 static int tg3_load_tso_firmware(struct tg3 *tp)
7309 {
7310         struct fw_info info;
7311         const __be32 *fw_data;
7312         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7313         int err, i;
7314
7315         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7316                 return 0;
7317
7318         fw_data = (void *)tp->fw->data;
7319
7320         /* Firmware blob starts with version numbers, followed by
7321            start address and length. We are setting complete length.
7322            length = end_address_of_bss - start_address_of_text.
7323            Remainder is the blob to be loaded contiguously
7324            from start address. */
7325
7326         info.fw_base = be32_to_cpu(fw_data[1]);
7327         cpu_scratch_size = tp->fw_len;
7328         info.fw_len = tp->fw->size - 12;
7329         info.fw_data = &fw_data[3];
7330
7331         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7332                 cpu_base = RX_CPU_BASE;
7333                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7334         } else {
7335                 cpu_base = TX_CPU_BASE;
7336                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7337                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7338         }
7339
7340         err = tg3_load_firmware_cpu(tp, cpu_base,
7341                                     cpu_scratch_base, cpu_scratch_size,
7342                                     &info);
7343         if (err)
7344                 return err;
7345
7346         /* Now startup the cpu. */
7347         tw32(cpu_base + CPU_STATE, 0xffffffff);
7348         tw32_f(cpu_base + CPU_PC, info.fw_base);
7349
7350         for (i = 0; i < 5; i++) {
7351                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7352                         break;
7353                 tw32(cpu_base + CPU_STATE, 0xffffffff);
7354                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
7355                 tw32_f(cpu_base + CPU_PC, info.fw_base);
7356                 udelay(1000);
7357         }
7358         if (i >= 5) {
7359                 netdev_err(tp->dev,
7360                            "%s fails to set CPU PC, is %08x should be %08x\n",
7361                            __func__, tr32(cpu_base + CPU_PC), info.fw_base);
7362                 return -ENODEV;
7363         }
7364         tw32(cpu_base + CPU_STATE, 0xffffffff);
7365         tw32_f(cpu_base + CPU_MODE,  0x00000000);
7366         return 0;
7367 }
7368
7369
7370 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7371 {
7372         struct tg3 *tp = netdev_priv(dev);
7373         struct sockaddr *addr = p;
7374         int err = 0, skip_mac_1 = 0;
7375
7376         if (!is_valid_ether_addr(addr->sa_data))
7377                 return -EINVAL;
7378
7379         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7380
7381         if (!netif_running(dev))
7382                 return 0;
7383
7384         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7385                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7386
7387                 addr0_high = tr32(MAC_ADDR_0_HIGH);
7388                 addr0_low = tr32(MAC_ADDR_0_LOW);
7389                 addr1_high = tr32(MAC_ADDR_1_HIGH);
7390                 addr1_low = tr32(MAC_ADDR_1_LOW);
7391
7392                 /* Skip MAC addr 1 if ASF is using it. */
7393                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7394                     !(addr1_high == 0 && addr1_low == 0))
7395                         skip_mac_1 = 1;
7396         }
7397         spin_lock_bh(&tp->lock);
7398         __tg3_set_mac_addr(tp, skip_mac_1);
7399         spin_unlock_bh(&tp->lock);
7400
7401         return err;
7402 }
7403
7404 /* tp->lock is held. */
7405 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7406                            dma_addr_t mapping, u32 maxlen_flags,
7407                            u32 nic_addr)
7408 {
7409         tg3_write_mem(tp,
7410                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7411                       ((u64) mapping >> 32));
7412         tg3_write_mem(tp,
7413                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7414                       ((u64) mapping & 0xffffffff));
7415         tg3_write_mem(tp,
7416                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7417                        maxlen_flags);
7418
7419         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7420                 tg3_write_mem(tp,
7421                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7422                               nic_addr);
7423 }
7424
7425 static void __tg3_set_rx_mode(struct net_device *);
7426 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7427 {
7428         int i;
7429
7430         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7431                 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7432                 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7433                 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7434         } else {
7435                 tw32(HOSTCC_TXCOL_TICKS, 0);
7436                 tw32(HOSTCC_TXMAX_FRAMES, 0);
7437                 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7438         }
7439
7440         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
7441                 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7442                 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7443                 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7444         } else {
7445                 tw32(HOSTCC_RXCOL_TICKS, 0);
7446                 tw32(HOSTCC_RXMAX_FRAMES, 0);
7447                 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7448         }
7449
7450         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7451                 u32 val = ec->stats_block_coalesce_usecs;
7452
7453                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7454                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7455
7456                 if (!netif_carrier_ok(tp->dev))
7457                         val = 0;
7458
7459                 tw32(HOSTCC_STAT_COAL_TICKS, val);
7460         }
7461
7462         for (i = 0; i < tp->irq_cnt - 1; i++) {
7463                 u32 reg;
7464
7465                 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7466                 tw32(reg, ec->rx_coalesce_usecs);
7467                 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7468                 tw32(reg, ec->rx_max_coalesced_frames);
7469                 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7470                 tw32(reg, ec->rx_max_coalesced_frames_irq);
7471
7472                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7473                         reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7474                         tw32(reg, ec->tx_coalesce_usecs);
7475                         reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7476                         tw32(reg, ec->tx_max_coalesced_frames);
7477                         reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7478                         tw32(reg, ec->tx_max_coalesced_frames_irq);
7479                 }
7480         }
7481
7482         for (; i < tp->irq_max - 1; i++) {
7483                 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7484                 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7485                 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7486
7487                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7488                         tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7489                         tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7490                         tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7491                 }
7492         }
7493 }
7494
7495 /* tp->lock is held. */
7496 static void tg3_rings_reset(struct tg3 *tp)
7497 {
7498         int i;
7499         u32 stblk, txrcb, rxrcb, limit;
7500         struct tg3_napi *tnapi = &tp->napi[0];
7501
7502         /* Disable all transmit rings but the first. */
7503         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7504                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7505         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7506                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7507         else
7508                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7509
7510         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7511              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7512                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7513                               BDINFO_FLAGS_DISABLED);
7514
7515
7516         /* Disable all receive return rings but the first. */
7517         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7518             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7519                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7520         else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7521                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7522         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7523                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7524                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7525         else
7526                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7527
7528         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7529              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7530                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7531                               BDINFO_FLAGS_DISABLED);
7532
7533         /* Disable interrupts */
7534         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7535
7536         /* Zero mailbox registers. */
7537         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7538                 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7539                         tp->napi[i].tx_prod = 0;
7540                         tp->napi[i].tx_cons = 0;
7541                         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7542                                 tw32_mailbox(tp->napi[i].prodmbox, 0);
7543                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
7544                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7545                 }
7546                 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7547                         tw32_mailbox(tp->napi[0].prodmbox, 0);
7548         } else {
7549                 tp->napi[0].tx_prod = 0;
7550                 tp->napi[0].tx_cons = 0;
7551                 tw32_mailbox(tp->napi[0].prodmbox, 0);
7552                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7553         }
7554
7555         /* Make sure the NIC-based send BD rings are disabled. */
7556         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7557                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7558                 for (i = 0; i < 16; i++)
7559                         tw32_tx_mbox(mbox + i * 8, 0);
7560         }
7561
7562         txrcb = NIC_SRAM_SEND_RCB;
7563         rxrcb = NIC_SRAM_RCV_RET_RCB;
7564
7565         /* Clear status block in ram. */
7566         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7567
7568         /* Set status block DMA address */
7569         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7570              ((u64) tnapi->status_mapping >> 32));
7571         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7572              ((u64) tnapi->status_mapping & 0xffffffff));
7573
7574         if (tnapi->tx_ring) {
7575                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7576                                (TG3_TX_RING_SIZE <<
7577                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7578                                NIC_SRAM_TX_BUFFER_DESC);
7579                 txrcb += TG3_BDINFO_SIZE;
7580         }
7581
7582         if (tnapi->rx_rcb) {
7583                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7584                                (TG3_RX_RCB_RING_SIZE(tp) <<
7585                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7586                 rxrcb += TG3_BDINFO_SIZE;
7587         }
7588
7589         stblk = HOSTCC_STATBLCK_RING1;
7590
7591         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7592                 u64 mapping = (u64)tnapi->status_mapping;
7593                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7594                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7595
7596                 /* Clear status block in ram. */
7597                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7598
7599                 if (tnapi->tx_ring) {
7600                         tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7601                                        (TG3_TX_RING_SIZE <<
7602                                         BDINFO_FLAGS_MAXLEN_SHIFT),
7603                                        NIC_SRAM_TX_BUFFER_DESC);
7604                         txrcb += TG3_BDINFO_SIZE;
7605                 }
7606
7607                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7608                                (TG3_RX_RCB_RING_SIZE(tp) <<
7609                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7610
7611                 stblk += 8;
7612                 rxrcb += TG3_BDINFO_SIZE;
7613         }
7614 }
7615
7616 /* tp->lock is held. */
7617 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7618 {
7619         u32 val, rdmac_mode;
7620         int i, err, limit;
7621         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
7622
7623         tg3_disable_ints(tp);
7624
7625         tg3_stop_fw(tp);
7626
7627         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7628
7629         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
7630                 tg3_abort_hw(tp, 1);
7631
7632         if (reset_phy)
7633                 tg3_phy_reset(tp);
7634
7635         err = tg3_chip_reset(tp);
7636         if (err)
7637                 return err;
7638
7639         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7640
7641         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7642                 val = tr32(TG3_CPMU_CTRL);
7643                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7644                 tw32(TG3_CPMU_CTRL, val);
7645
7646                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7647                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7648                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7649                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7650
7651                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7652                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7653                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7654                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7655
7656                 val = tr32(TG3_CPMU_HST_ACC);
7657                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7658                 val |= CPMU_HST_ACC_MACCLK_6_25;
7659                 tw32(TG3_CPMU_HST_ACC, val);
7660         }
7661
7662         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7663                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7664                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7665                        PCIE_PWR_MGMT_L1_THRESH_4MS;
7666                 tw32(PCIE_PWR_MGMT_THRESH, val);
7667
7668                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7669                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7670
7671                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7672
7673                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7674                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7675         }
7676
7677         if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7678                 u32 grc_mode = tr32(GRC_MODE);
7679
7680                 /* Access the lower 1K of PL PCIE block registers. */
7681                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7682                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7683
7684                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7685                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7686                      val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7687
7688                 tw32(GRC_MODE, grc_mode);
7689         }
7690
7691         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
7692                 u32 grc_mode = tr32(GRC_MODE);
7693
7694                 /* Access the lower 1K of PL PCIE block registers. */
7695                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7696                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7697
7698                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5);
7699                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
7700                      val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
7701
7702                 tw32(GRC_MODE, grc_mode);
7703
7704                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7705                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7706                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7707                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7708         }
7709
7710         /* This works around an issue with Athlon chipsets on
7711          * B3 tigon3 silicon.  This bit has no effect on any
7712          * other revision.  But do not set this on PCI Express
7713          * chips and don't even touch the clocks if the CPMU is present.
7714          */
7715         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7716                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7717                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7718                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7719         }
7720
7721         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7722             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7723                 val = tr32(TG3PCI_PCISTATE);
7724                 val |= PCISTATE_RETRY_SAME_DMA;
7725                 tw32(TG3PCI_PCISTATE, val);
7726         }
7727
7728         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7729                 /* Allow reads and writes to the
7730                  * APE register and memory space.
7731                  */
7732                 val = tr32(TG3PCI_PCISTATE);
7733                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7734                        PCISTATE_ALLOW_APE_SHMEM_WR |
7735                        PCISTATE_ALLOW_APE_PSPACE_WR;
7736                 tw32(TG3PCI_PCISTATE, val);
7737         }
7738
7739         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7740                 /* Enable some hw fixes.  */
7741                 val = tr32(TG3PCI_MSI_DATA);
7742                 val |= (1 << 26) | (1 << 28) | (1 << 29);
7743                 tw32(TG3PCI_MSI_DATA, val);
7744         }
7745
7746         /* Descriptor ring init may make accesses to the
7747          * NIC SRAM area to setup the TX descriptors, so we
7748          * can only do this after the hardware has been
7749          * successfully reset.
7750          */
7751         err = tg3_init_rings(tp);
7752         if (err)
7753                 return err;
7754
7755         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
7756                 val = tr32(TG3PCI_DMA_RW_CTRL) &
7757                       ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7758                 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
7759                         val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
7760                 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7761         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7762                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7763                 /* This value is determined during the probe time DMA
7764                  * engine test, tg3_test_dma.
7765                  */
7766                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7767         }
7768
7769         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7770                           GRC_MODE_4X_NIC_SEND_RINGS |
7771                           GRC_MODE_NO_TX_PHDR_CSUM |
7772                           GRC_MODE_NO_RX_PHDR_CSUM);
7773         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7774
7775         /* Pseudo-header checksum is done by hardware logic and not
7776          * the offload processers, so make the chip do the pseudo-
7777          * header checksums on receive.  For transmit it is more
7778          * convenient to do the pseudo-header checksum in software
7779          * as Linux does that on transmit for us in all cases.
7780          */
7781         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7782
7783         tw32(GRC_MODE,
7784              tp->grc_mode |
7785              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7786
7787         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7788         val = tr32(GRC_MISC_CFG);
7789         val &= ~0xff;
7790         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7791         tw32(GRC_MISC_CFG, val);
7792
7793         /* Initialize MBUF/DESC pool. */
7794         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7795                 /* Do nothing.  */
7796         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7797                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7798                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7799                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7800                 else
7801                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7802                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7803                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7804         } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7805                 int fw_len;
7806
7807                 fw_len = tp->fw_len;
7808                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7809                 tw32(BUFMGR_MB_POOL_ADDR,
7810                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7811                 tw32(BUFMGR_MB_POOL_SIZE,
7812                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7813         }
7814
7815         if (tp->dev->mtu <= ETH_DATA_LEN) {
7816                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7817                      tp->bufmgr_config.mbuf_read_dma_low_water);
7818                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7819                      tp->bufmgr_config.mbuf_mac_rx_low_water);
7820                 tw32(BUFMGR_MB_HIGH_WATER,
7821                      tp->bufmgr_config.mbuf_high_water);
7822         } else {
7823                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7824                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7825                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7826                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7827                 tw32(BUFMGR_MB_HIGH_WATER,
7828                      tp->bufmgr_config.mbuf_high_water_jumbo);
7829         }
7830         tw32(BUFMGR_DMA_LOW_WATER,
7831              tp->bufmgr_config.dma_low_water);
7832         tw32(BUFMGR_DMA_HIGH_WATER,
7833              tp->bufmgr_config.dma_high_water);
7834
7835         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7836         for (i = 0; i < 2000; i++) {
7837                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7838                         break;
7839                 udelay(10);
7840         }
7841         if (i >= 2000) {
7842                 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
7843                 return -ENODEV;
7844         }
7845
7846         /* Setup replenish threshold. */
7847         val = tp->rx_pending / 8;
7848         if (val == 0)
7849                 val = 1;
7850         else if (val > tp->rx_std_max_post)
7851                 val = tp->rx_std_max_post;
7852         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7853                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7854                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7855
7856                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7857                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7858         }
7859
7860         tw32(RCVBDI_STD_THRESH, val);
7861
7862         /* Initialize TG3_BDINFO's at:
7863          *  RCVDBDI_STD_BD:     standard eth size rx ring
7864          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
7865          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
7866          *
7867          * like so:
7868          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
7869          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
7870          *                              ring attribute flags
7871          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
7872          *
7873          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7874          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7875          *
7876          * The size of each ring is fixed in the firmware, but the location is
7877          * configurable.
7878          */
7879         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7880              ((u64) tpr->rx_std_mapping >> 32));
7881         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7882              ((u64) tpr->rx_std_mapping & 0xffffffff));
7883         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
7884             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
7885                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7886                      NIC_SRAM_RX_BUFFER_DESC);
7887
7888         /* Disable the mini ring */
7889         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7890                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7891                      BDINFO_FLAGS_DISABLED);
7892
7893         /* Program the jumbo buffer descriptor ring control
7894          * blocks on those devices that have them.
7895          */
7896         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7897             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7898                 /* Setup replenish threshold. */
7899                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7900
7901                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7902                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7903                              ((u64) tpr->rx_jmb_mapping >> 32));
7904                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7905                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7906                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7907                              (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7908                              BDINFO_FLAGS_USE_EXT_RECV);
7909                         if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) ||
7910                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7911                                 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7912                                      NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7913                 } else {
7914                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7915                              BDINFO_FLAGS_DISABLED);
7916                 }
7917
7918                 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
7919                         val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7920                               (TG3_RX_STD_DMA_SZ << 2);
7921                 else
7922                         val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
7923         } else
7924                 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7925
7926         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7927
7928         tpr->rx_std_prod_idx = tp->rx_pending;
7929         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
7930
7931         tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7932                           tp->rx_jumbo_pending : 0;
7933         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
7934
7935         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
7936                 tw32(STD_REPLENISH_LWM, 32);
7937                 tw32(JMB_REPLENISH_LWM, 16);
7938         }
7939
7940         tg3_rings_reset(tp);
7941
7942         /* Initialize MAC address and backoff seed. */
7943         __tg3_set_mac_addr(tp, 0);
7944
7945         /* MTU + ethernet header + FCS + optional VLAN tag */
7946         tw32(MAC_RX_MTU_SIZE,
7947              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7948
7949         /* The slot time is changed by tg3_setup_phy if we
7950          * run at gigabit with half duplex.
7951          */
7952         tw32(MAC_TX_LENGTHS,
7953              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7954              (6 << TX_LENGTHS_IPG_SHIFT) |
7955              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7956
7957         /* Receive rules. */
7958         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7959         tw32(RCVLPC_CONFIG, 0x0181);
7960
7961         /* Calculate RDMAC_MODE setting early, we need it to determine
7962          * the RCVLPC_STATE_ENABLE mask.
7963          */
7964         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7965                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7966                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7967                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7968                       RDMAC_MODE_LNGREAD_ENAB);
7969
7970         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7971             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7972                 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
7973
7974         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7975             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7976             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7977                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7978                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7979                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7980
7981         /* If statement applies to 5705 and 5750 PCI devices only */
7982         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7983              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7984             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7985                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7986                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7987                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7988                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7989                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7990                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7991                 }
7992         }
7993
7994         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7995                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7996
7997         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7998                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7999
8000         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
8001             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8002             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8003                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
8004
8005         /* Receive/send statistics. */
8006         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
8007                 val = tr32(RCVLPC_STATS_ENABLE);
8008                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8009                 tw32(RCVLPC_STATS_ENABLE, val);
8010         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8011                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8012                 val = tr32(RCVLPC_STATS_ENABLE);
8013                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8014                 tw32(RCVLPC_STATS_ENABLE, val);
8015         } else {
8016                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8017         }
8018         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8019         tw32(SNDDATAI_STATSENAB, 0xffffff);
8020         tw32(SNDDATAI_STATSCTRL,
8021              (SNDDATAI_SCTRL_ENABLE |
8022               SNDDATAI_SCTRL_FASTUPD));
8023
8024         /* Setup host coalescing engine. */
8025         tw32(HOSTCC_MODE, 0);
8026         for (i = 0; i < 2000; i++) {
8027                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8028                         break;
8029                 udelay(10);
8030         }
8031
8032         __tg3_set_coalesce(tp, &tp->coal);
8033
8034         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8035                 /* Status/statistics block address.  See tg3_timer,
8036                  * the tg3_periodic_fetch_stats call there, and
8037                  * tg3_get_stats to see how this works for 5705/5750 chips.
8038                  */
8039                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8040                      ((u64) tp->stats_mapping >> 32));
8041                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8042                      ((u64) tp->stats_mapping & 0xffffffff));
8043                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8044
8045                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
8046
8047                 /* Clear statistics and status block memory areas */
8048                 for (i = NIC_SRAM_STATS_BLK;
8049                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8050                      i += sizeof(u32)) {
8051                         tg3_write_mem(tp, i, 0);
8052                         udelay(40);
8053                 }
8054         }
8055
8056         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8057
8058         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8059         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8060         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8061                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8062
8063         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8064                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
8065                 /* reset to prevent losing 1st rx packet intermittently */
8066                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8067                 udelay(10);
8068         }
8069
8070         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8071                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8072         else
8073                 tp->mac_mode = 0;
8074         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8075                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
8076         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8077             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8078             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8079                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8080         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8081         udelay(40);
8082
8083         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8084          * If TG3_FLG2_IS_NIC is zero, we should read the
8085          * register to preserve the GPIO settings for LOMs. The GPIOs,
8086          * whether used as inputs or outputs, are set by boot code after
8087          * reset.
8088          */
8089         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
8090                 u32 gpio_mask;
8091
8092                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8093                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8094                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8095
8096                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8097                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8098                                      GRC_LCLCTRL_GPIO_OUTPUT3;
8099
8100                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8101                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8102
8103                 tp->grc_local_ctrl &= ~gpio_mask;
8104                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8105
8106                 /* GPIO1 must be driven high for eeprom write protect */
8107                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8108                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8109                                                GRC_LCLCTRL_GPIO_OUTPUT1);
8110         }
8111         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8112         udelay(100);
8113
8114         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
8115                 val = tr32(MSGINT_MODE);
8116                 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8117                 tw32(MSGINT_MODE, val);
8118         }
8119
8120         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8121                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8122                 udelay(40);
8123         }
8124
8125         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8126                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8127                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8128                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8129                WDMAC_MODE_LNGREAD_ENAB);
8130
8131         /* If statement applies to 5705 and 5750 PCI devices only */
8132         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8133              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8134             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
8135                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8136                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8137                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8138                         /* nothing */
8139                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8140                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8141                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8142                         val |= WDMAC_MODE_RX_ACCEL;
8143                 }
8144         }
8145
8146         /* Enable host coalescing bug fix */
8147         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8148                 val |= WDMAC_MODE_STATUS_TAG_FIX;
8149
8150         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8151                 val |= WDMAC_MODE_BURST_ALL_DATA;
8152
8153         tw32_f(WDMAC_MODE, val);
8154         udelay(40);
8155
8156         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8157                 u16 pcix_cmd;
8158
8159                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8160                                      &pcix_cmd);
8161                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8162                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8163                         pcix_cmd |= PCI_X_CMD_READ_2K;
8164                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8165                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8166                         pcix_cmd |= PCI_X_CMD_READ_2K;
8167                 }
8168                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8169                                       pcix_cmd);
8170         }
8171
8172         tw32_f(RDMAC_MODE, rdmac_mode);
8173         udelay(40);
8174
8175         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8176         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8177                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8178
8179         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8180                 tw32(SNDDATAC_MODE,
8181                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8182         else
8183                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8184
8185         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8186         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8187         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8188         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8189         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8190                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8191         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8192         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8193                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8194         tw32(SNDBDI_MODE, val);
8195         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8196
8197         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8198                 err = tg3_load_5701_a0_firmware_fix(tp);
8199                 if (err)
8200                         return err;
8201         }
8202
8203         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8204                 err = tg3_load_tso_firmware(tp);
8205                 if (err)
8206                         return err;
8207         }
8208
8209         tp->tx_mode = TX_MODE_ENABLE;
8210         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
8211             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8212                 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
8213         tw32_f(MAC_TX_MODE, tp->tx_mode);
8214         udelay(100);
8215
8216         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8217                 u32 reg = MAC_RSS_INDIR_TBL_0;
8218                 u8 *ent = (u8 *)&val;
8219
8220                 /* Setup the indirection table */
8221                 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8222                         int idx = i % sizeof(val);
8223
8224                         ent[idx] = i % (tp->irq_cnt - 1);
8225                         if (idx == sizeof(val) - 1) {
8226                                 tw32(reg, val);
8227                                 reg += 4;
8228                         }
8229                 }
8230
8231                 /* Setup the "secret" hash key. */
8232                 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8233                 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8234                 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8235                 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8236                 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8237                 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8238                 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8239                 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8240                 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8241                 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8242         }
8243
8244         tp->rx_mode = RX_MODE_ENABLE;
8245         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8246                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8247
8248         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8249                 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8250                                RX_MODE_RSS_ITBL_HASH_BITS_7 |
8251                                RX_MODE_RSS_IPV6_HASH_EN |
8252                                RX_MODE_RSS_TCP_IPV6_HASH_EN |
8253                                RX_MODE_RSS_IPV4_HASH_EN |
8254                                RX_MODE_RSS_TCP_IPV4_HASH_EN;
8255
8256         tw32_f(MAC_RX_MODE, tp->rx_mode);
8257         udelay(10);
8258
8259         tw32(MAC_LED_CTRL, tp->led_ctrl);
8260
8261         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8262         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8263                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8264                 udelay(10);
8265         }
8266         tw32_f(MAC_RX_MODE, tp->rx_mode);
8267         udelay(10);
8268
8269         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8270                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8271                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
8272                         /* Set drive transmission level to 1.2V  */
8273                         /* only if the signal pre-emphasis bit is not set  */
8274                         val = tr32(MAC_SERDES_CFG);
8275                         val &= 0xfffff000;
8276                         val |= 0x880;
8277                         tw32(MAC_SERDES_CFG, val);
8278                 }
8279                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8280                         tw32(MAC_SERDES_CFG, 0x616000);
8281         }
8282
8283         /* Prevent chip from dropping frames when flow control
8284          * is enabled.
8285          */
8286         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8287                 val = 1;
8288         else
8289                 val = 2;
8290         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8291
8292         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8293             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8294                 /* Use hardware link auto-negotiation */
8295                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8296         }
8297
8298         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8299             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8300                 u32 tmp;
8301
8302                 tmp = tr32(SERDES_RX_CTRL);
8303                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8304                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8305                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8306                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8307         }
8308
8309         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8310                 if (tp->link_config.phy_is_low_power) {
8311                         tp->link_config.phy_is_low_power = 0;
8312                         tp->link_config.speed = tp->link_config.orig_speed;
8313                         tp->link_config.duplex = tp->link_config.orig_duplex;
8314                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
8315                 }
8316
8317                 err = tg3_setup_phy(tp, 0);
8318                 if (err)
8319                         return err;
8320
8321                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8322                     !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
8323                         u32 tmp;
8324
8325                         /* Clear CRC stats. */
8326                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8327                                 tg3_writephy(tp, MII_TG3_TEST1,
8328                                              tmp | MII_TG3_TEST1_CRC_EN);
8329                                 tg3_readphy(tp, 0x14, &tmp);
8330                         }
8331                 }
8332         }
8333
8334         __tg3_set_rx_mode(tp->dev);
8335
8336         /* Initialize receive rules. */
8337         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
8338         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8339         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
8340         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8341
8342         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8343             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8344                 limit = 8;
8345         else
8346                 limit = 16;
8347         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8348                 limit -= 4;
8349         switch (limit) {
8350         case 16:
8351                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
8352         case 15:
8353                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
8354         case 14:
8355                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
8356         case 13:
8357                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
8358         case 12:
8359                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
8360         case 11:
8361                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
8362         case 10:
8363                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
8364         case 9:
8365                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
8366         case 8:
8367                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
8368         case 7:
8369                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
8370         case 6:
8371                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
8372         case 5:
8373                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
8374         case 4:
8375                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
8376         case 3:
8377                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
8378         case 2:
8379         case 1:
8380
8381         default:
8382                 break;
8383         }
8384
8385         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8386                 /* Write our heartbeat update interval to APE. */
8387                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8388                                 APE_HOST_HEARTBEAT_INT_DISABLE);
8389
8390         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8391
8392         return 0;
8393 }
8394
8395 /* Called at device open time to get the chip ready for
8396  * packet processing.  Invoked with tp->lock held.
8397  */
8398 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8399 {
8400         tg3_switch_clocks(tp);
8401
8402         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8403
8404         return tg3_reset_hw(tp, reset_phy);
8405 }
8406
8407 #define TG3_STAT_ADD32(PSTAT, REG) \
8408 do {    u32 __val = tr32(REG); \
8409         (PSTAT)->low += __val; \
8410         if ((PSTAT)->low < __val) \
8411                 (PSTAT)->high += 1; \
8412 } while (0)
8413
8414 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8415 {
8416         struct tg3_hw_stats *sp = tp->hw_stats;
8417
8418         if (!netif_carrier_ok(tp->dev))
8419                 return;
8420
8421         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8422         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8423         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8424         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8425         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8426         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8427         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8428         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8429         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8430         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8431         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8432         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8433         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8434
8435         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8436         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8437         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8438         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8439         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8440         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8441         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8442         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8443         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8444         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8445         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8446         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8447         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8448         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8449
8450         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8451         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8452         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8453 }
8454
8455 static void tg3_timer(unsigned long __opaque)
8456 {
8457         struct tg3 *tp = (struct tg3 *) __opaque;
8458
8459         if (tp->irq_sync)
8460                 goto restart_timer;
8461
8462         spin_lock(&tp->lock);
8463
8464         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8465                 /* All of this garbage is because when using non-tagged
8466                  * IRQ status the mailbox/status_block protocol the chip
8467                  * uses with the cpu is race prone.
8468                  */
8469                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8470                         tw32(GRC_LOCAL_CTRL,
8471                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8472                 } else {
8473                         tw32(HOSTCC_MODE, tp->coalesce_mode |
8474                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8475                 }
8476
8477                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8478                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8479                         spin_unlock(&tp->lock);
8480                         schedule_work(&tp->reset_task);
8481                         return;
8482                 }
8483         }
8484
8485         /* This part only runs once per second. */
8486         if (!--tp->timer_counter) {
8487                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8488                         tg3_periodic_fetch_stats(tp);
8489
8490                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8491                         u32 mac_stat;
8492                         int phy_event;
8493
8494                         mac_stat = tr32(MAC_STATUS);
8495
8496                         phy_event = 0;
8497                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8498                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8499                                         phy_event = 1;
8500                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8501                                 phy_event = 1;
8502
8503                         if (phy_event)
8504                                 tg3_setup_phy(tp, 0);
8505                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8506                         u32 mac_stat = tr32(MAC_STATUS);
8507                         int need_setup = 0;
8508
8509                         if (netif_carrier_ok(tp->dev) &&
8510                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8511                                 need_setup = 1;
8512                         }
8513                         if (!netif_carrier_ok(tp->dev) &&
8514                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
8515                                          MAC_STATUS_SIGNAL_DET))) {
8516                                 need_setup = 1;
8517                         }
8518                         if (need_setup) {
8519                                 if (!tp->serdes_counter) {
8520                                         tw32_f(MAC_MODE,
8521                                              (tp->mac_mode &
8522                                               ~MAC_MODE_PORT_MODE_MASK));
8523                                         udelay(40);
8524                                         tw32_f(MAC_MODE, tp->mac_mode);
8525                                         udelay(40);
8526                                 }
8527                                 tg3_setup_phy(tp, 0);
8528                         }
8529                 } else if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8530                            (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8531                         tg3_serdes_parallel_detect(tp);
8532                 }
8533
8534                 tp->timer_counter = tp->timer_multiplier;
8535         }
8536
8537         /* Heartbeat is only sent once every 2 seconds.
8538          *
8539          * The heartbeat is to tell the ASF firmware that the host
8540          * driver is still alive.  In the event that the OS crashes,
8541          * ASF needs to reset the hardware to free up the FIFO space
8542          * that may be filled with rx packets destined for the host.
8543          * If the FIFO is full, ASF will no longer function properly.
8544          *
8545          * Unintended resets have been reported on real time kernels
8546          * where the timer doesn't run on time.  Netpoll will also have
8547          * same problem.
8548          *
8549          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8550          * to check the ring condition when the heartbeat is expiring
8551          * before doing the reset.  This will prevent most unintended
8552          * resets.
8553          */
8554         if (!--tp->asf_counter) {
8555                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8556                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8557                         tg3_wait_for_event_ack(tp);
8558
8559                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8560                                       FWCMD_NICDRV_ALIVE3);
8561                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8562                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
8563                                       TG3_FW_UPDATE_TIMEOUT_SEC);
8564
8565                         tg3_generate_fw_event(tp);
8566                 }
8567                 tp->asf_counter = tp->asf_multiplier;
8568         }
8569
8570         spin_unlock(&tp->lock);
8571
8572 restart_timer:
8573         tp->timer.expires = jiffies + tp->timer_offset;
8574         add_timer(&tp->timer);
8575 }
8576
8577 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8578 {
8579         irq_handler_t fn;
8580         unsigned long flags;
8581         char *name;
8582         struct tg3_napi *tnapi = &tp->napi[irq_num];
8583
8584         if (tp->irq_cnt == 1)
8585                 name = tp->dev->name;
8586         else {
8587                 name = &tnapi->irq_lbl[0];
8588                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8589                 name[IFNAMSIZ-1] = 0;
8590         }
8591
8592         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8593                 fn = tg3_msi;
8594                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8595                         fn = tg3_msi_1shot;
8596                 flags = IRQF_SAMPLE_RANDOM;
8597         } else {
8598                 fn = tg3_interrupt;
8599                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8600                         fn = tg3_interrupt_tagged;
8601                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8602         }
8603
8604         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8605 }
8606
8607 static int tg3_test_interrupt(struct tg3 *tp)
8608 {
8609         struct tg3_napi *tnapi = &tp->napi[0];
8610         struct net_device *dev = tp->dev;
8611         int err, i, intr_ok = 0;
8612         u32 val;
8613
8614         if (!netif_running(dev))
8615                 return -ENODEV;
8616
8617         tg3_disable_ints(tp);
8618
8619         free_irq(tnapi->irq_vec, tnapi);
8620
8621         /*
8622          * Turn off MSI one shot mode.  Otherwise this test has no
8623          * observable way to know whether the interrupt was delivered.
8624          */
8625         if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8626             (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8627                 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8628                 tw32(MSGINT_MODE, val);
8629         }
8630
8631         err = request_irq(tnapi->irq_vec, tg3_test_isr,
8632                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8633         if (err)
8634                 return err;
8635
8636         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8637         tg3_enable_ints(tp);
8638
8639         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8640                tnapi->coal_now);
8641
8642         for (i = 0; i < 5; i++) {
8643                 u32 int_mbox, misc_host_ctrl;
8644
8645                 int_mbox = tr32_mailbox(tnapi->int_mbox);
8646                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8647
8648                 if ((int_mbox != 0) ||
8649                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8650                         intr_ok = 1;
8651                         break;
8652                 }
8653
8654                 msleep(10);
8655         }
8656
8657         tg3_disable_ints(tp);
8658
8659         free_irq(tnapi->irq_vec, tnapi);
8660
8661         err = tg3_request_irq(tp, 0);
8662
8663         if (err)
8664                 return err;
8665
8666         if (intr_ok) {
8667                 /* Reenable MSI one shot mode. */
8668                 if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8669                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8670                         val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8671                         tw32(MSGINT_MODE, val);
8672                 }
8673                 return 0;
8674         }
8675
8676         return -EIO;
8677 }
8678
8679 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8680  * successfully restored
8681  */
8682 static int tg3_test_msi(struct tg3 *tp)
8683 {
8684         int err;
8685         u16 pci_cmd;
8686
8687         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8688                 return 0;
8689
8690         /* Turn off SERR reporting in case MSI terminates with Master
8691          * Abort.
8692          */
8693         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8694         pci_write_config_word(tp->pdev, PCI_COMMAND,
8695                               pci_cmd & ~PCI_COMMAND_SERR);
8696
8697         err = tg3_test_interrupt(tp);
8698
8699         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8700
8701         if (!err)
8702                 return 0;
8703
8704         /* other failures */
8705         if (err != -EIO)
8706                 return err;
8707
8708         /* MSI test failed, go back to INTx mode */
8709         netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
8710                     "to INTx mode. Please report this failure to the PCI "
8711                     "maintainer and include system chipset information\n");
8712
8713         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8714
8715         pci_disable_msi(tp->pdev);
8716
8717         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8718         tp->napi[0].irq_vec = tp->pdev->irq;
8719
8720         err = tg3_request_irq(tp, 0);
8721         if (err)
8722                 return err;
8723
8724         /* Need to reset the chip because the MSI cycle may have terminated
8725          * with Master Abort.
8726          */
8727         tg3_full_lock(tp, 1);
8728
8729         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8730         err = tg3_init_hw(tp, 1);
8731
8732         tg3_full_unlock(tp);
8733
8734         if (err)
8735                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8736
8737         return err;
8738 }
8739
8740 static int tg3_request_firmware(struct tg3 *tp)
8741 {
8742         const __be32 *fw_data;
8743
8744         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8745                 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
8746                            tp->fw_needed);
8747                 return -ENOENT;
8748         }
8749
8750         fw_data = (void *)tp->fw->data;
8751
8752         /* Firmware blob starts with version numbers, followed by
8753          * start address and _full_ length including BSS sections
8754          * (which must be longer than the actual data, of course
8755          */
8756
8757         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
8758         if (tp->fw_len < (tp->fw->size - 12)) {
8759                 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
8760                            tp->fw_len, tp->fw_needed);
8761                 release_firmware(tp->fw);
8762                 tp->fw = NULL;
8763                 return -EINVAL;
8764         }
8765
8766         /* We no longer need firmware; we have it. */
8767         tp->fw_needed = NULL;
8768         return 0;
8769 }
8770
8771 static bool tg3_enable_msix(struct tg3 *tp)
8772 {
8773         int i, rc, cpus = num_online_cpus();
8774         struct msix_entry msix_ent[tp->irq_max];
8775
8776         if (cpus == 1)
8777                 /* Just fallback to the simpler MSI mode. */
8778                 return false;
8779
8780         /*
8781          * We want as many rx rings enabled as there are cpus.
8782          * The first MSIX vector only deals with link interrupts, etc,
8783          * so we add one to the number of vectors we are requesting.
8784          */
8785         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8786
8787         for (i = 0; i < tp->irq_max; i++) {
8788                 msix_ent[i].entry  = i;
8789                 msix_ent[i].vector = 0;
8790         }
8791
8792         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8793         if (rc < 0) {
8794                 return false;
8795         } else if (rc != 0) {
8796                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8797                         return false;
8798                 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
8799                               tp->irq_cnt, rc);
8800                 tp->irq_cnt = rc;
8801         }
8802
8803         for (i = 0; i < tp->irq_max; i++)
8804                 tp->napi[i].irq_vec = msix_ent[i].vector;
8805
8806         tp->dev->real_num_tx_queues = 1;
8807         if (tp->irq_cnt > 1) {
8808                 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8809
8810                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8811                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
8812                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
8813                         tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8814                 }
8815         }
8816
8817         return true;
8818 }
8819
8820 static void tg3_ints_init(struct tg3 *tp)
8821 {
8822         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8823             !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8824                 /* All MSI supporting chips should support tagged
8825                  * status.  Assert that this is the case.
8826                  */
8827                 netdev_warn(tp->dev,
8828                             "MSI without TAGGED_STATUS? Not using MSI\n");
8829                 goto defcfg;
8830         }
8831
8832         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8833                 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8834         else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8835                  pci_enable_msi(tp->pdev) == 0)
8836                 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8837
8838         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8839                 u32 msi_mode = tr32(MSGINT_MODE);
8840                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8841                         msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8842                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8843         }
8844 defcfg:
8845         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8846                 tp->irq_cnt = 1;
8847                 tp->napi[0].irq_vec = tp->pdev->irq;
8848                 tp->dev->real_num_tx_queues = 1;
8849         }
8850 }
8851
8852 static void tg3_ints_fini(struct tg3 *tp)
8853 {
8854         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8855                 pci_disable_msix(tp->pdev);
8856         else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8857                 pci_disable_msi(tp->pdev);
8858         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8859         tp->tg3_flags3 &= ~(TG3_FLG3_ENABLE_RSS | TG3_FLG3_ENABLE_TSS);
8860 }
8861
8862 static int tg3_open(struct net_device *dev)
8863 {
8864         struct tg3 *tp = netdev_priv(dev);
8865         int i, err;
8866
8867         if (tp->fw_needed) {
8868                 err = tg3_request_firmware(tp);
8869                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8870                         if (err)
8871                                 return err;
8872                 } else if (err) {
8873                         netdev_warn(tp->dev, "TSO capability disabled\n");
8874                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8875                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8876                         netdev_notice(tp->dev, "TSO capability restored\n");
8877                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8878                 }
8879         }
8880
8881         netif_carrier_off(tp->dev);
8882
8883         err = tg3_set_power_state(tp, PCI_D0);
8884         if (err)
8885                 return err;
8886
8887         tg3_full_lock(tp, 0);
8888
8889         tg3_disable_ints(tp);
8890         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8891
8892         tg3_full_unlock(tp);
8893
8894         /*
8895          * Setup interrupts first so we know how
8896          * many NAPI resources to allocate
8897          */
8898         tg3_ints_init(tp);
8899
8900         /* The placement of this call is tied
8901          * to the setup and use of Host TX descriptors.
8902          */
8903         err = tg3_alloc_consistent(tp);
8904         if (err)
8905                 goto err_out1;
8906
8907         tg3_napi_enable(tp);
8908
8909         for (i = 0; i < tp->irq_cnt; i++) {
8910                 struct tg3_napi *tnapi = &tp->napi[i];
8911                 err = tg3_request_irq(tp, i);
8912                 if (err) {
8913                         for (i--; i >= 0; i--)
8914                                 free_irq(tnapi->irq_vec, tnapi);
8915                         break;
8916                 }
8917         }
8918
8919         if (err)
8920                 goto err_out2;
8921
8922         tg3_full_lock(tp, 0);
8923
8924         err = tg3_init_hw(tp, 1);
8925         if (err) {
8926                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8927                 tg3_free_rings(tp);
8928         } else {
8929                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8930                         tp->timer_offset = HZ;
8931                 else
8932                         tp->timer_offset = HZ / 10;
8933
8934                 BUG_ON(tp->timer_offset > HZ);
8935                 tp->timer_counter = tp->timer_multiplier =
8936                         (HZ / tp->timer_offset);
8937                 tp->asf_counter = tp->asf_multiplier =
8938                         ((HZ / tp->timer_offset) * 2);
8939
8940                 init_timer(&tp->timer);
8941                 tp->timer.expires = jiffies + tp->timer_offset;
8942                 tp->timer.data = (unsigned long) tp;
8943                 tp->timer.function = tg3_timer;
8944         }
8945
8946         tg3_full_unlock(tp);
8947
8948         if (err)
8949                 goto err_out3;
8950
8951         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8952                 err = tg3_test_msi(tp);
8953
8954                 if (err) {
8955                         tg3_full_lock(tp, 0);
8956                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8957                         tg3_free_rings(tp);
8958                         tg3_full_unlock(tp);
8959
8960                         goto err_out2;
8961                 }
8962
8963                 if (!(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8964                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8965                         u32 val = tr32(PCIE_TRANSACTION_CFG);
8966
8967                         tw32(PCIE_TRANSACTION_CFG,
8968                              val | PCIE_TRANS_CFG_1SHOT_MSI);
8969                 }
8970         }
8971
8972         tg3_phy_start(tp);
8973
8974         tg3_full_lock(tp, 0);
8975
8976         add_timer(&tp->timer);
8977         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8978         tg3_enable_ints(tp);
8979
8980         tg3_full_unlock(tp);
8981
8982         netif_tx_start_all_queues(dev);
8983
8984         return 0;
8985
8986 err_out3:
8987         for (i = tp->irq_cnt - 1; i >= 0; i--) {
8988                 struct tg3_napi *tnapi = &tp->napi[i];
8989                 free_irq(tnapi->irq_vec, tnapi);
8990         }
8991
8992 err_out2:
8993         tg3_napi_disable(tp);
8994         tg3_free_consistent(tp);
8995
8996 err_out1:
8997         tg3_ints_fini(tp);
8998         return err;
8999 }
9000
9001 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
9002                                                  struct rtnl_link_stats64 *);
9003 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9004
9005 static int tg3_close(struct net_device *dev)
9006 {
9007         int i;
9008         struct tg3 *tp = netdev_priv(dev);
9009
9010         tg3_napi_disable(tp);
9011         cancel_work_sync(&tp->reset_task);
9012
9013         netif_tx_stop_all_queues(dev);
9014
9015         del_timer_sync(&tp->timer);
9016
9017         tg3_phy_stop(tp);
9018
9019         tg3_full_lock(tp, 1);
9020
9021         tg3_disable_ints(tp);
9022
9023         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9024         tg3_free_rings(tp);
9025         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9026
9027         tg3_full_unlock(tp);
9028
9029         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9030                 struct tg3_napi *tnapi = &tp->napi[i];
9031                 free_irq(tnapi->irq_vec, tnapi);
9032         }
9033
9034         tg3_ints_fini(tp);
9035
9036         tg3_get_stats64(tp->dev, &tp->net_stats_prev);
9037
9038         memcpy(&tp->estats_prev, tg3_get_estats(tp),
9039                sizeof(tp->estats_prev));
9040
9041         tg3_free_consistent(tp);
9042
9043         tg3_set_power_state(tp, PCI_D3hot);
9044
9045         netif_carrier_off(tp->dev);
9046
9047         return 0;
9048 }
9049
9050 static inline u64 get_stat64(tg3_stat64_t *val)
9051 {
9052        return ((u64)val->high << 32) | ((u64)val->low);
9053 }
9054
9055 static u64 calc_crc_errors(struct tg3 *tp)
9056 {
9057         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9058
9059         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9060             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9061              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9062                 u32 val;
9063
9064                 spin_lock_bh(&tp->lock);
9065                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9066                         tg3_writephy(tp, MII_TG3_TEST1,
9067                                      val | MII_TG3_TEST1_CRC_EN);
9068                         tg3_readphy(tp, 0x14, &val);
9069                 } else
9070                         val = 0;
9071                 spin_unlock_bh(&tp->lock);
9072
9073                 tp->phy_crc_errors += val;
9074
9075                 return tp->phy_crc_errors;
9076         }
9077
9078         return get_stat64(&hw_stats->rx_fcs_errors);
9079 }
9080
9081 #define ESTAT_ADD(member) \
9082         estats->member =        old_estats->member + \
9083                                 get_stat64(&hw_stats->member)
9084
9085 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9086 {
9087         struct tg3_ethtool_stats *estats = &tp->estats;
9088         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9089         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9090
9091         if (!hw_stats)
9092                 return old_estats;
9093
9094         ESTAT_ADD(rx_octets);
9095         ESTAT_ADD(rx_fragments);
9096         ESTAT_ADD(rx_ucast_packets);
9097         ESTAT_ADD(rx_mcast_packets);
9098         ESTAT_ADD(rx_bcast_packets);
9099         ESTAT_ADD(rx_fcs_errors);
9100         ESTAT_ADD(rx_align_errors);
9101         ESTAT_ADD(rx_xon_pause_rcvd);
9102         ESTAT_ADD(rx_xoff_pause_rcvd);
9103         ESTAT_ADD(rx_mac_ctrl_rcvd);
9104         ESTAT_ADD(rx_xoff_entered);
9105         ESTAT_ADD(rx_frame_too_long_errors);
9106         ESTAT_ADD(rx_jabbers);
9107         ESTAT_ADD(rx_undersize_packets);
9108         ESTAT_ADD(rx_in_length_errors);
9109         ESTAT_ADD(rx_out_length_errors);
9110         ESTAT_ADD(rx_64_or_less_octet_packets);
9111         ESTAT_ADD(rx_65_to_127_octet_packets);
9112         ESTAT_ADD(rx_128_to_255_octet_packets);
9113         ESTAT_ADD(rx_256_to_511_octet_packets);
9114         ESTAT_ADD(rx_512_to_1023_octet_packets);
9115         ESTAT_ADD(rx_1024_to_1522_octet_packets);
9116         ESTAT_ADD(rx_1523_to_2047_octet_packets);
9117         ESTAT_ADD(rx_2048_to_4095_octet_packets);
9118         ESTAT_ADD(rx_4096_to_8191_octet_packets);
9119         ESTAT_ADD(rx_8192_to_9022_octet_packets);
9120
9121         ESTAT_ADD(tx_octets);
9122         ESTAT_ADD(tx_collisions);
9123         ESTAT_ADD(tx_xon_sent);
9124         ESTAT_ADD(tx_xoff_sent);
9125         ESTAT_ADD(tx_flow_control);
9126         ESTAT_ADD(tx_mac_errors);
9127         ESTAT_ADD(tx_single_collisions);
9128         ESTAT_ADD(tx_mult_collisions);
9129         ESTAT_ADD(tx_deferred);
9130         ESTAT_ADD(tx_excessive_collisions);
9131         ESTAT_ADD(tx_late_collisions);
9132         ESTAT_ADD(tx_collide_2times);
9133         ESTAT_ADD(tx_collide_3times);
9134         ESTAT_ADD(tx_collide_4times);
9135         ESTAT_ADD(tx_collide_5times);
9136         ESTAT_ADD(tx_collide_6times);
9137         ESTAT_ADD(tx_collide_7times);
9138         ESTAT_ADD(tx_collide_8times);
9139         ESTAT_ADD(tx_collide_9times);
9140         ESTAT_ADD(tx_collide_10times);
9141         ESTAT_ADD(tx_collide_11times);
9142         ESTAT_ADD(tx_collide_12times);
9143         ESTAT_ADD(tx_collide_13times);
9144         ESTAT_ADD(tx_collide_14times);
9145         ESTAT_ADD(tx_collide_15times);
9146         ESTAT_ADD(tx_ucast_packets);
9147         ESTAT_ADD(tx_mcast_packets);
9148         ESTAT_ADD(tx_bcast_packets);
9149         ESTAT_ADD(tx_carrier_sense_errors);
9150         ESTAT_ADD(tx_discards);
9151         ESTAT_ADD(tx_errors);
9152
9153         ESTAT_ADD(dma_writeq_full);
9154         ESTAT_ADD(dma_write_prioq_full);
9155         ESTAT_ADD(rxbds_empty);
9156         ESTAT_ADD(rx_discards);
9157         ESTAT_ADD(rx_errors);
9158         ESTAT_ADD(rx_threshold_hit);
9159
9160         ESTAT_ADD(dma_readq_full);
9161         ESTAT_ADD(dma_read_prioq_full);
9162         ESTAT_ADD(tx_comp_queue_full);
9163
9164         ESTAT_ADD(ring_set_send_prod_index);
9165         ESTAT_ADD(ring_status_update);
9166         ESTAT_ADD(nic_irqs);
9167         ESTAT_ADD(nic_avoided_irqs);
9168         ESTAT_ADD(nic_tx_threshold_hit);
9169
9170         return estats;
9171 }
9172
9173 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
9174                                                  struct rtnl_link_stats64 *stats)
9175 {
9176         struct tg3 *tp = netdev_priv(dev);
9177         struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
9178         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9179
9180         if (!hw_stats)
9181                 return old_stats;
9182
9183         stats->rx_packets = old_stats->rx_packets +
9184                 get_stat64(&hw_stats->rx_ucast_packets) +
9185                 get_stat64(&hw_stats->rx_mcast_packets) +
9186                 get_stat64(&hw_stats->rx_bcast_packets);
9187
9188         stats->tx_packets = old_stats->tx_packets +
9189                 get_stat64(&hw_stats->tx_ucast_packets) +
9190                 get_stat64(&hw_stats->tx_mcast_packets) +
9191                 get_stat64(&hw_stats->tx_bcast_packets);
9192
9193         stats->rx_bytes = old_stats->rx_bytes +
9194                 get_stat64(&hw_stats->rx_octets);
9195         stats->tx_bytes = old_stats->tx_bytes +
9196                 get_stat64(&hw_stats->tx_octets);
9197
9198         stats->rx_errors = old_stats->rx_errors +
9199                 get_stat64(&hw_stats->rx_errors);
9200         stats->tx_errors = old_stats->tx_errors +
9201                 get_stat64(&hw_stats->tx_errors) +
9202                 get_stat64(&hw_stats->tx_mac_errors) +
9203                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9204                 get_stat64(&hw_stats->tx_discards);
9205
9206         stats->multicast = old_stats->multicast +
9207                 get_stat64(&hw_stats->rx_mcast_packets);
9208         stats->collisions = old_stats->collisions +
9209                 get_stat64(&hw_stats->tx_collisions);
9210
9211         stats->rx_length_errors = old_stats->rx_length_errors +
9212                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9213                 get_stat64(&hw_stats->rx_undersize_packets);
9214
9215         stats->rx_over_errors = old_stats->rx_over_errors +
9216                 get_stat64(&hw_stats->rxbds_empty);
9217         stats->rx_frame_errors = old_stats->rx_frame_errors +
9218                 get_stat64(&hw_stats->rx_align_errors);
9219         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9220                 get_stat64(&hw_stats->tx_discards);
9221         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9222                 get_stat64(&hw_stats->tx_carrier_sense_errors);
9223
9224         stats->rx_crc_errors = old_stats->rx_crc_errors +
9225                 calc_crc_errors(tp);
9226
9227         stats->rx_missed_errors = old_stats->rx_missed_errors +
9228                 get_stat64(&hw_stats->rx_discards);
9229
9230         return stats;
9231 }
9232
9233 static inline u32 calc_crc(unsigned char *buf, int len)
9234 {
9235         u32 reg;
9236         u32 tmp;
9237         int j, k;
9238
9239         reg = 0xffffffff;
9240
9241         for (j = 0; j < len; j++) {
9242                 reg ^= buf[j];
9243
9244                 for (k = 0; k < 8; k++) {
9245                         tmp = reg & 0x01;
9246
9247                         reg >>= 1;
9248
9249                         if (tmp)
9250                                 reg ^= 0xedb88320;
9251                 }
9252         }
9253
9254         return ~reg;
9255 }
9256
9257 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9258 {
9259         /* accept or reject all multicast frames */
9260         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9261         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9262         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9263         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9264 }
9265
9266 static void __tg3_set_rx_mode(struct net_device *dev)
9267 {
9268         struct tg3 *tp = netdev_priv(dev);
9269         u32 rx_mode;
9270
9271         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9272                                   RX_MODE_KEEP_VLAN_TAG);
9273
9274         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9275          * flag clear.
9276          */
9277 #if TG3_VLAN_TAG_USED
9278         if (!tp->vlgrp &&
9279             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9280                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9281 #else
9282         /* By definition, VLAN is disabled always in this
9283          * case.
9284          */
9285         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9286                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9287 #endif
9288
9289         if (dev->flags & IFF_PROMISC) {
9290                 /* Promiscuous mode. */
9291                 rx_mode |= RX_MODE_PROMISC;
9292         } else if (dev->flags & IFF_ALLMULTI) {
9293                 /* Accept all multicast. */
9294                 tg3_set_multi(tp, 1);
9295         } else if (netdev_mc_empty(dev)) {
9296                 /* Reject all multicast. */
9297                 tg3_set_multi(tp, 0);
9298         } else {
9299                 /* Accept one or more multicast(s). */
9300                 struct netdev_hw_addr *ha;
9301                 u32 mc_filter[4] = { 0, };
9302                 u32 regidx;
9303                 u32 bit;
9304                 u32 crc;
9305
9306                 netdev_for_each_mc_addr(ha, dev) {
9307                         crc = calc_crc(ha->addr, ETH_ALEN);
9308                         bit = ~crc & 0x7f;
9309                         regidx = (bit & 0x60) >> 5;
9310                         bit &= 0x1f;
9311                         mc_filter[regidx] |= (1 << bit);
9312                 }
9313
9314                 tw32(MAC_HASH_REG_0, mc_filter[0]);
9315                 tw32(MAC_HASH_REG_1, mc_filter[1]);
9316                 tw32(MAC_HASH_REG_2, mc_filter[2]);
9317                 tw32(MAC_HASH_REG_3, mc_filter[3]);
9318         }
9319
9320         if (rx_mode != tp->rx_mode) {
9321                 tp->rx_mode = rx_mode;
9322                 tw32_f(MAC_RX_MODE, rx_mode);
9323                 udelay(10);
9324         }
9325 }
9326
9327 static void tg3_set_rx_mode(struct net_device *dev)
9328 {
9329         struct tg3 *tp = netdev_priv(dev);
9330
9331         if (!netif_running(dev))
9332                 return;
9333
9334         tg3_full_lock(tp, 0);
9335         __tg3_set_rx_mode(dev);
9336         tg3_full_unlock(tp);
9337 }
9338
9339 #define TG3_REGDUMP_LEN         (32 * 1024)
9340
9341 static int tg3_get_regs_len(struct net_device *dev)
9342 {
9343         return TG3_REGDUMP_LEN;
9344 }
9345
9346 static void tg3_get_regs(struct net_device *dev,
9347                 struct ethtool_regs *regs, void *_p)
9348 {
9349         u32 *p = _p;
9350         struct tg3 *tp = netdev_priv(dev);
9351         u8 *orig_p = _p;
9352         int i;
9353
9354         regs->version = 0;
9355
9356         memset(p, 0, TG3_REGDUMP_LEN);
9357
9358         if (tp->link_config.phy_is_low_power)
9359                 return;
9360
9361         tg3_full_lock(tp, 0);
9362
9363 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
9364 #define GET_REG32_LOOP(base, len)               \
9365 do {    p = (u32 *)(orig_p + (base));           \
9366         for (i = 0; i < len; i += 4)            \
9367                 __GET_REG32((base) + i);        \
9368 } while (0)
9369 #define GET_REG32_1(reg)                        \
9370 do {    p = (u32 *)(orig_p + (reg));            \
9371         __GET_REG32((reg));                     \
9372 } while (0)
9373
9374         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9375         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9376         GET_REG32_LOOP(MAC_MODE, 0x4f0);
9377         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9378         GET_REG32_1(SNDDATAC_MODE);
9379         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9380         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9381         GET_REG32_1(SNDBDC_MODE);
9382         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9383         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9384         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9385         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9386         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9387         GET_REG32_1(RCVDCC_MODE);
9388         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9389         GET_REG32_LOOP(RCVCC_MODE, 0x14);
9390         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9391         GET_REG32_1(MBFREE_MODE);
9392         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9393         GET_REG32_LOOP(MEMARB_MODE, 0x10);
9394         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9395         GET_REG32_LOOP(RDMAC_MODE, 0x08);
9396         GET_REG32_LOOP(WDMAC_MODE, 0x08);
9397         GET_REG32_1(RX_CPU_MODE);
9398         GET_REG32_1(RX_CPU_STATE);
9399         GET_REG32_1(RX_CPU_PGMCTR);
9400         GET_REG32_1(RX_CPU_HWBKPT);
9401         GET_REG32_1(TX_CPU_MODE);
9402         GET_REG32_1(TX_CPU_STATE);
9403         GET_REG32_1(TX_CPU_PGMCTR);
9404         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9405         GET_REG32_LOOP(FTQ_RESET, 0x120);
9406         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9407         GET_REG32_1(DMAC_MODE);
9408         GET_REG32_LOOP(GRC_MODE, 0x4c);
9409         if (tp->tg3_flags & TG3_FLAG_NVRAM)
9410                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9411
9412 #undef __GET_REG32
9413 #undef GET_REG32_LOOP
9414 #undef GET_REG32_1
9415
9416         tg3_full_unlock(tp);
9417 }
9418
9419 static int tg3_get_eeprom_len(struct net_device *dev)
9420 {
9421         struct tg3 *tp = netdev_priv(dev);
9422
9423         return tp->nvram_size;
9424 }
9425
9426 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9427 {
9428         struct tg3 *tp = netdev_priv(dev);
9429         int ret;
9430         u8  *pd;
9431         u32 i, offset, len, b_offset, b_count;
9432         __be32 val;
9433
9434         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9435                 return -EINVAL;
9436
9437         if (tp->link_config.phy_is_low_power)
9438                 return -EAGAIN;
9439
9440         offset = eeprom->offset;
9441         len = eeprom->len;
9442         eeprom->len = 0;
9443
9444         eeprom->magic = TG3_EEPROM_MAGIC;
9445
9446         if (offset & 3) {
9447                 /* adjustments to start on required 4 byte boundary */
9448                 b_offset = offset & 3;
9449                 b_count = 4 - b_offset;
9450                 if (b_count > len) {
9451                         /* i.e. offset=1 len=2 */
9452                         b_count = len;
9453                 }
9454                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9455                 if (ret)
9456                         return ret;
9457                 memcpy(data, ((char *)&val) + b_offset, b_count);
9458                 len -= b_count;
9459                 offset += b_count;
9460                 eeprom->len += b_count;
9461         }
9462
9463         /* read bytes upto the last 4 byte boundary */
9464         pd = &data[eeprom->len];
9465         for (i = 0; i < (len - (len & 3)); i += 4) {
9466                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9467                 if (ret) {
9468                         eeprom->len += i;
9469                         return ret;
9470                 }
9471                 memcpy(pd + i, &val, 4);
9472         }
9473         eeprom->len += i;
9474
9475         if (len & 3) {
9476                 /* read last bytes not ending on 4 byte boundary */
9477                 pd = &data[eeprom->len];
9478                 b_count = len & 3;
9479                 b_offset = offset + len - b_count;
9480                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9481                 if (ret)
9482                         return ret;
9483                 memcpy(pd, &val, b_count);
9484                 eeprom->len += b_count;
9485         }
9486         return 0;
9487 }
9488
9489 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9490
9491 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9492 {
9493         struct tg3 *tp = netdev_priv(dev);
9494         int ret;
9495         u32 offset, len, b_offset, odd_len;
9496         u8 *buf;
9497         __be32 start, end;
9498
9499         if (tp->link_config.phy_is_low_power)
9500                 return -EAGAIN;
9501
9502         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9503             eeprom->magic != TG3_EEPROM_MAGIC)
9504                 return -EINVAL;
9505
9506         offset = eeprom->offset;
9507         len = eeprom->len;
9508
9509         if ((b_offset = (offset & 3))) {
9510                 /* adjustments to start on required 4 byte boundary */
9511                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9512                 if (ret)
9513                         return ret;
9514                 len += b_offset;
9515                 offset &= ~3;
9516                 if (len < 4)
9517                         len = 4;
9518         }
9519
9520         odd_len = 0;
9521         if (len & 3) {
9522                 /* adjustments to end on required 4 byte boundary */
9523                 odd_len = 1;
9524                 len = (len + 3) & ~3;
9525                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9526                 if (ret)
9527                         return ret;
9528         }
9529
9530         buf = data;
9531         if (b_offset || odd_len) {
9532                 buf = kmalloc(len, GFP_KERNEL);
9533                 if (!buf)
9534                         return -ENOMEM;
9535                 if (b_offset)
9536                         memcpy(buf, &start, 4);
9537                 if (odd_len)
9538                         memcpy(buf+len-4, &end, 4);
9539                 memcpy(buf + b_offset, data, eeprom->len);
9540         }
9541
9542         ret = tg3_nvram_write_block(tp, offset, len, buf);
9543
9544         if (buf != data)
9545                 kfree(buf);
9546
9547         return ret;
9548 }
9549
9550 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9551 {
9552         struct tg3 *tp = netdev_priv(dev);
9553
9554         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9555                 struct phy_device *phydev;
9556                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9557                         return -EAGAIN;
9558                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9559                 return phy_ethtool_gset(phydev, cmd);
9560         }
9561
9562         cmd->supported = (SUPPORTED_Autoneg);
9563
9564         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9565                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9566                                    SUPPORTED_1000baseT_Full);
9567
9568         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
9569                 cmd->supported |= (SUPPORTED_100baseT_Half |
9570                                   SUPPORTED_100baseT_Full |
9571                                   SUPPORTED_10baseT_Half |
9572                                   SUPPORTED_10baseT_Full |
9573                                   SUPPORTED_TP);
9574                 cmd->port = PORT_TP;
9575         } else {
9576                 cmd->supported |= SUPPORTED_FIBRE;
9577                 cmd->port = PORT_FIBRE;
9578         }
9579
9580         cmd->advertising = tp->link_config.advertising;
9581         if (netif_running(dev)) {
9582                 cmd->speed = tp->link_config.active_speed;
9583                 cmd->duplex = tp->link_config.active_duplex;
9584         }
9585         cmd->phy_address = tp->phy_addr;
9586         cmd->transceiver = XCVR_INTERNAL;
9587         cmd->autoneg = tp->link_config.autoneg;
9588         cmd->maxtxpkt = 0;
9589         cmd->maxrxpkt = 0;
9590         return 0;
9591 }
9592
9593 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9594 {
9595         struct tg3 *tp = netdev_priv(dev);
9596
9597         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9598                 struct phy_device *phydev;
9599                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9600                         return -EAGAIN;
9601                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9602                 return phy_ethtool_sset(phydev, cmd);
9603         }
9604
9605         if (cmd->autoneg != AUTONEG_ENABLE &&
9606             cmd->autoneg != AUTONEG_DISABLE)
9607                 return -EINVAL;
9608
9609         if (cmd->autoneg == AUTONEG_DISABLE &&
9610             cmd->duplex != DUPLEX_FULL &&
9611             cmd->duplex != DUPLEX_HALF)
9612                 return -EINVAL;
9613
9614         if (cmd->autoneg == AUTONEG_ENABLE) {
9615                 u32 mask = ADVERTISED_Autoneg |
9616                            ADVERTISED_Pause |
9617                            ADVERTISED_Asym_Pause;
9618
9619                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9620                         mask |= ADVERTISED_1000baseT_Half |
9621                                 ADVERTISED_1000baseT_Full;
9622
9623                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9624                         mask |= ADVERTISED_100baseT_Half |
9625                                 ADVERTISED_100baseT_Full |
9626                                 ADVERTISED_10baseT_Half |
9627                                 ADVERTISED_10baseT_Full |
9628                                 ADVERTISED_TP;
9629                 else
9630                         mask |= ADVERTISED_FIBRE;
9631
9632                 if (cmd->advertising & ~mask)
9633                         return -EINVAL;
9634
9635                 mask &= (ADVERTISED_1000baseT_Half |
9636                          ADVERTISED_1000baseT_Full |
9637                          ADVERTISED_100baseT_Half |
9638                          ADVERTISED_100baseT_Full |
9639                          ADVERTISED_10baseT_Half |
9640                          ADVERTISED_10baseT_Full);
9641
9642                 cmd->advertising &= mask;
9643         } else {
9644                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9645                         if (cmd->speed != SPEED_1000)
9646                                 return -EINVAL;
9647
9648                         if (cmd->duplex != DUPLEX_FULL)
9649                                 return -EINVAL;
9650                 } else {
9651                         if (cmd->speed != SPEED_100 &&
9652                             cmd->speed != SPEED_10)
9653                                 return -EINVAL;
9654                 }
9655         }
9656
9657         tg3_full_lock(tp, 0);
9658
9659         tp->link_config.autoneg = cmd->autoneg;
9660         if (cmd->autoneg == AUTONEG_ENABLE) {
9661                 tp->link_config.advertising = (cmd->advertising |
9662                                               ADVERTISED_Autoneg);
9663                 tp->link_config.speed = SPEED_INVALID;
9664                 tp->link_config.duplex = DUPLEX_INVALID;
9665         } else {
9666                 tp->link_config.advertising = 0;
9667                 tp->link_config.speed = cmd->speed;
9668                 tp->link_config.duplex = cmd->duplex;
9669         }
9670
9671         tp->link_config.orig_speed = tp->link_config.speed;
9672         tp->link_config.orig_duplex = tp->link_config.duplex;
9673         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9674
9675         if (netif_running(dev))
9676                 tg3_setup_phy(tp, 1);
9677
9678         tg3_full_unlock(tp);
9679
9680         return 0;
9681 }
9682
9683 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9684 {
9685         struct tg3 *tp = netdev_priv(dev);
9686
9687         strcpy(info->driver, DRV_MODULE_NAME);
9688         strcpy(info->version, DRV_MODULE_VERSION);
9689         strcpy(info->fw_version, tp->fw_ver);
9690         strcpy(info->bus_info, pci_name(tp->pdev));
9691 }
9692
9693 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9694 {
9695         struct tg3 *tp = netdev_priv(dev);
9696
9697         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9698             device_can_wakeup(&tp->pdev->dev))
9699                 wol->supported = WAKE_MAGIC;
9700         else
9701                 wol->supported = 0;
9702         wol->wolopts = 0;
9703         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9704             device_can_wakeup(&tp->pdev->dev))
9705                 wol->wolopts = WAKE_MAGIC;
9706         memset(&wol->sopass, 0, sizeof(wol->sopass));
9707 }
9708
9709 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9710 {
9711         struct tg3 *tp = netdev_priv(dev);
9712         struct device *dp = &tp->pdev->dev;
9713
9714         if (wol->wolopts & ~WAKE_MAGIC)
9715                 return -EINVAL;
9716         if ((wol->wolopts & WAKE_MAGIC) &&
9717             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9718                 return -EINVAL;
9719
9720         spin_lock_bh(&tp->lock);
9721         if (wol->wolopts & WAKE_MAGIC) {
9722                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9723                 device_set_wakeup_enable(dp, true);
9724         } else {
9725                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9726                 device_set_wakeup_enable(dp, false);
9727         }
9728         spin_unlock_bh(&tp->lock);
9729
9730         return 0;
9731 }
9732
9733 static u32 tg3_get_msglevel(struct net_device *dev)
9734 {
9735         struct tg3 *tp = netdev_priv(dev);
9736         return tp->msg_enable;
9737 }
9738
9739 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9740 {
9741         struct tg3 *tp = netdev_priv(dev);
9742         tp->msg_enable = value;
9743 }
9744
9745 static int tg3_set_tso(struct net_device *dev, u32 value)
9746 {
9747         struct tg3 *tp = netdev_priv(dev);
9748
9749         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9750                 if (value)
9751                         return -EINVAL;
9752                 return 0;
9753         }
9754         if ((dev->features & NETIF_F_IPV6_CSUM) &&
9755             ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9756              (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9757                 if (value) {
9758                         dev->features |= NETIF_F_TSO6;
9759                         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9760                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9761                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9762                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9763                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9764                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9765                                 dev->features |= NETIF_F_TSO_ECN;
9766                 } else
9767                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9768         }
9769         return ethtool_op_set_tso(dev, value);
9770 }
9771
9772 static int tg3_nway_reset(struct net_device *dev)
9773 {
9774         struct tg3 *tp = netdev_priv(dev);
9775         int r;
9776
9777         if (!netif_running(dev))
9778                 return -EAGAIN;
9779
9780         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9781                 return -EINVAL;
9782
9783         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9784                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9785                         return -EAGAIN;
9786                 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9787         } else {
9788                 u32 bmcr;
9789
9790                 spin_lock_bh(&tp->lock);
9791                 r = -EINVAL;
9792                 tg3_readphy(tp, MII_BMCR, &bmcr);
9793                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9794                     ((bmcr & BMCR_ANENABLE) ||
9795                      (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9796                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9797                                                    BMCR_ANENABLE);
9798                         r = 0;
9799                 }
9800                 spin_unlock_bh(&tp->lock);
9801         }
9802
9803         return r;
9804 }
9805
9806 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9807 {
9808         struct tg3 *tp = netdev_priv(dev);
9809
9810         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9811         ering->rx_mini_max_pending = 0;
9812         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9813                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9814         else
9815                 ering->rx_jumbo_max_pending = 0;
9816
9817         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9818
9819         ering->rx_pending = tp->rx_pending;
9820         ering->rx_mini_pending = 0;
9821         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9822                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9823         else
9824                 ering->rx_jumbo_pending = 0;
9825
9826         ering->tx_pending = tp->napi[0].tx_pending;
9827 }
9828
9829 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9830 {
9831         struct tg3 *tp = netdev_priv(dev);
9832         int i, irq_sync = 0, err = 0;
9833
9834         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9835             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9836             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9837             (ering->tx_pending <= MAX_SKB_FRAGS) ||
9838             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9839              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9840                 return -EINVAL;
9841
9842         if (netif_running(dev)) {
9843                 tg3_phy_stop(tp);
9844                 tg3_netif_stop(tp);
9845                 irq_sync = 1;
9846         }
9847
9848         tg3_full_lock(tp, irq_sync);
9849
9850         tp->rx_pending = ering->rx_pending;
9851
9852         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9853             tp->rx_pending > 63)
9854                 tp->rx_pending = 63;
9855         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9856
9857         for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9858                 tp->napi[i].tx_pending = ering->tx_pending;
9859
9860         if (netif_running(dev)) {
9861                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9862                 err = tg3_restart_hw(tp, 1);
9863                 if (!err)
9864                         tg3_netif_start(tp);
9865         }
9866
9867         tg3_full_unlock(tp);
9868
9869         if (irq_sync && !err)
9870                 tg3_phy_start(tp);
9871
9872         return err;
9873 }
9874
9875 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9876 {
9877         struct tg3 *tp = netdev_priv(dev);
9878
9879         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9880
9881         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9882                 epause->rx_pause = 1;
9883         else
9884                 epause->rx_pause = 0;
9885
9886         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9887                 epause->tx_pause = 1;
9888         else
9889                 epause->tx_pause = 0;
9890 }
9891
9892 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9893 {
9894         struct tg3 *tp = netdev_priv(dev);
9895         int err = 0;
9896
9897         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9898                 u32 newadv;
9899                 struct phy_device *phydev;
9900
9901                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9902
9903                 if (!(phydev->supported & SUPPORTED_Pause) ||
9904                     (!(phydev->supported & SUPPORTED_Asym_Pause) &&
9905                      ((epause->rx_pause && !epause->tx_pause) ||
9906                       (!epause->rx_pause && epause->tx_pause))))
9907                         return -EINVAL;
9908
9909                 tp->link_config.flowctrl = 0;
9910                 if (epause->rx_pause) {
9911                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
9912
9913                         if (epause->tx_pause) {
9914                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9915                                 newadv = ADVERTISED_Pause;
9916                         } else
9917                                 newadv = ADVERTISED_Pause |
9918                                          ADVERTISED_Asym_Pause;
9919                 } else if (epause->tx_pause) {
9920                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
9921                         newadv = ADVERTISED_Asym_Pause;
9922                 } else
9923                         newadv = 0;
9924
9925                 if (epause->autoneg)
9926                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9927                 else
9928                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9929
9930                 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9931                         u32 oldadv = phydev->advertising &
9932                                      (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
9933                         if (oldadv != newadv) {
9934                                 phydev->advertising &=
9935                                         ~(ADVERTISED_Pause |
9936                                           ADVERTISED_Asym_Pause);
9937                                 phydev->advertising |= newadv;
9938                                 if (phydev->autoneg) {
9939                                         /*
9940                                          * Always renegotiate the link to
9941                                          * inform our link partner of our
9942                                          * flow control settings, even if the
9943                                          * flow control is forced.  Let
9944                                          * tg3_adjust_link() do the final
9945                                          * flow control setup.
9946                                          */
9947                                         return phy_start_aneg(phydev);
9948                                 }
9949                         }
9950
9951                         if (!epause->autoneg)
9952                                 tg3_setup_flow_control(tp, 0, 0);
9953                 } else {
9954                         tp->link_config.orig_advertising &=
9955                                         ~(ADVERTISED_Pause |
9956                                           ADVERTISED_Asym_Pause);
9957                         tp->link_config.orig_advertising |= newadv;
9958                 }
9959         } else {
9960                 int irq_sync = 0;
9961
9962                 if (netif_running(dev)) {
9963                         tg3_netif_stop(tp);
9964                         irq_sync = 1;
9965                 }
9966
9967                 tg3_full_lock(tp, irq_sync);
9968
9969                 if (epause->autoneg)
9970                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9971                 else
9972                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9973                 if (epause->rx_pause)
9974                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
9975                 else
9976                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9977                 if (epause->tx_pause)
9978                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
9979                 else
9980                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9981
9982                 if (netif_running(dev)) {
9983                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9984                         err = tg3_restart_hw(tp, 1);
9985                         if (!err)
9986                                 tg3_netif_start(tp);
9987                 }
9988
9989                 tg3_full_unlock(tp);
9990         }
9991
9992         return err;
9993 }
9994
9995 static u32 tg3_get_rx_csum(struct net_device *dev)
9996 {
9997         struct tg3 *tp = netdev_priv(dev);
9998         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9999 }
10000
10001 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10002 {
10003         struct tg3 *tp = netdev_priv(dev);
10004
10005         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10006                 if (data != 0)
10007                         return -EINVAL;
10008                 return 0;
10009         }
10010
10011         spin_lock_bh(&tp->lock);
10012         if (data)
10013                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10014         else
10015                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10016         spin_unlock_bh(&tp->lock);
10017
10018         return 0;
10019 }
10020
10021 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10022 {
10023         struct tg3 *tp = netdev_priv(dev);
10024
10025         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10026                 if (data != 0)
10027                         return -EINVAL;
10028                 return 0;
10029         }
10030
10031         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10032                 ethtool_op_set_tx_ipv6_csum(dev, data);
10033         else
10034                 ethtool_op_set_tx_csum(dev, data);
10035
10036         return 0;
10037 }
10038
10039 static int tg3_get_sset_count(struct net_device *dev, int sset)
10040 {
10041         switch (sset) {
10042         case ETH_SS_TEST:
10043                 return TG3_NUM_TEST;
10044         case ETH_SS_STATS:
10045                 return TG3_NUM_STATS;
10046         default:
10047                 return -EOPNOTSUPP;
10048         }
10049 }
10050
10051 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
10052 {
10053         switch (stringset) {
10054         case ETH_SS_STATS:
10055                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10056                 break;
10057         case ETH_SS_TEST:
10058                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10059                 break;
10060         default:
10061                 WARN_ON(1);     /* we need a WARN() */
10062                 break;
10063         }
10064 }
10065
10066 static int tg3_phys_id(struct net_device *dev, u32 data)
10067 {
10068         struct tg3 *tp = netdev_priv(dev);
10069         int i;
10070
10071         if (!netif_running(tp->dev))
10072                 return -EAGAIN;
10073
10074         if (data == 0)
10075                 data = UINT_MAX / 2;
10076
10077         for (i = 0; i < (data * 2); i++) {
10078                 if ((i % 2) == 0)
10079                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10080                                            LED_CTRL_1000MBPS_ON |
10081                                            LED_CTRL_100MBPS_ON |
10082                                            LED_CTRL_10MBPS_ON |
10083                                            LED_CTRL_TRAFFIC_OVERRIDE |
10084                                            LED_CTRL_TRAFFIC_BLINK |
10085                                            LED_CTRL_TRAFFIC_LED);
10086
10087                 else
10088                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10089                                            LED_CTRL_TRAFFIC_OVERRIDE);
10090
10091                 if (msleep_interruptible(500))
10092                         break;
10093         }
10094         tw32(MAC_LED_CTRL, tp->led_ctrl);
10095         return 0;
10096 }
10097
10098 static void tg3_get_ethtool_stats(struct net_device *dev,
10099                                    struct ethtool_stats *estats, u64 *tmp_stats)
10100 {
10101         struct tg3 *tp = netdev_priv(dev);
10102         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10103 }
10104
10105 #define NVRAM_TEST_SIZE 0x100
10106 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
10107 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
10108 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
10109 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10110 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10111
10112 static int tg3_test_nvram(struct tg3 *tp)
10113 {
10114         u32 csum, magic;
10115         __be32 *buf;
10116         int i, j, k, err = 0, size;
10117
10118         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10119                 return 0;
10120
10121         if (tg3_nvram_read(tp, 0, &magic) != 0)
10122                 return -EIO;
10123
10124         if (magic == TG3_EEPROM_MAGIC)
10125                 size = NVRAM_TEST_SIZE;
10126         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10127                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10128                     TG3_EEPROM_SB_FORMAT_1) {
10129                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10130                         case TG3_EEPROM_SB_REVISION_0:
10131                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10132                                 break;
10133                         case TG3_EEPROM_SB_REVISION_2:
10134                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10135                                 break;
10136                         case TG3_EEPROM_SB_REVISION_3:
10137                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10138                                 break;
10139                         default:
10140                                 return 0;
10141                         }
10142                 } else
10143                         return 0;
10144         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10145                 size = NVRAM_SELFBOOT_HW_SIZE;
10146         else
10147                 return -EIO;
10148
10149         buf = kmalloc(size, GFP_KERNEL);
10150         if (buf == NULL)
10151                 return -ENOMEM;
10152
10153         err = -EIO;
10154         for (i = 0, j = 0; i < size; i += 4, j++) {
10155                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10156                 if (err)
10157                         break;
10158         }
10159         if (i < size)
10160                 goto out;
10161
10162         /* Selfboot format */
10163         magic = be32_to_cpu(buf[0]);
10164         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10165             TG3_EEPROM_MAGIC_FW) {
10166                 u8 *buf8 = (u8 *) buf, csum8 = 0;
10167
10168                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10169                     TG3_EEPROM_SB_REVISION_2) {
10170                         /* For rev 2, the csum doesn't include the MBA. */
10171                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10172                                 csum8 += buf8[i];
10173                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10174                                 csum8 += buf8[i];
10175                 } else {
10176                         for (i = 0; i < size; i++)
10177                                 csum8 += buf8[i];
10178                 }
10179
10180                 if (csum8 == 0) {
10181                         err = 0;
10182                         goto out;
10183                 }
10184
10185                 err = -EIO;
10186                 goto out;
10187         }
10188
10189         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10190             TG3_EEPROM_MAGIC_HW) {
10191                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10192                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10193                 u8 *buf8 = (u8 *) buf;
10194
10195                 /* Separate the parity bits and the data bytes.  */
10196                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10197                         if ((i == 0) || (i == 8)) {
10198                                 int l;
10199                                 u8 msk;
10200
10201                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10202                                         parity[k++] = buf8[i] & msk;
10203                                 i++;
10204                         } else if (i == 16) {
10205                                 int l;
10206                                 u8 msk;
10207
10208                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10209                                         parity[k++] = buf8[i] & msk;
10210                                 i++;
10211
10212                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10213                                         parity[k++] = buf8[i] & msk;
10214                                 i++;
10215                         }
10216                         data[j++] = buf8[i];
10217                 }
10218
10219                 err = -EIO;
10220                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10221                         u8 hw8 = hweight8(data[i]);
10222
10223                         if ((hw8 & 0x1) && parity[i])
10224                                 goto out;
10225                         else if (!(hw8 & 0x1) && !parity[i])
10226                                 goto out;
10227                 }
10228                 err = 0;
10229                 goto out;
10230         }
10231
10232         /* Bootstrap checksum at offset 0x10 */
10233         csum = calc_crc((unsigned char *) buf, 0x10);
10234         if (csum != be32_to_cpu(buf[0x10/4]))
10235                 goto out;
10236
10237         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10238         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10239         if (csum != be32_to_cpu(buf[0xfc/4]))
10240                 goto out;
10241
10242         err = 0;
10243
10244 out:
10245         kfree(buf);
10246         return err;
10247 }
10248
10249 #define TG3_SERDES_TIMEOUT_SEC  2
10250 #define TG3_COPPER_TIMEOUT_SEC  6
10251
10252 static int tg3_test_link(struct tg3 *tp)
10253 {
10254         int i, max;
10255
10256         if (!netif_running(tp->dev))
10257                 return -ENODEV;
10258
10259         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10260                 max = TG3_SERDES_TIMEOUT_SEC;
10261         else
10262                 max = TG3_COPPER_TIMEOUT_SEC;
10263
10264         for (i = 0; i < max; i++) {
10265                 if (netif_carrier_ok(tp->dev))
10266                         return 0;
10267
10268                 if (msleep_interruptible(1000))
10269                         break;
10270         }
10271
10272         return -EIO;
10273 }
10274
10275 /* Only test the commonly used registers */
10276 static int tg3_test_registers(struct tg3 *tp)
10277 {
10278         int i, is_5705, is_5750;
10279         u32 offset, read_mask, write_mask, val, save_val, read_val;
10280         static struct {
10281                 u16 offset;
10282                 u16 flags;
10283 #define TG3_FL_5705     0x1
10284 #define TG3_FL_NOT_5705 0x2
10285 #define TG3_FL_NOT_5788 0x4
10286 #define TG3_FL_NOT_5750 0x8
10287                 u32 read_mask;
10288                 u32 write_mask;
10289         } reg_tbl[] = {
10290                 /* MAC Control Registers */
10291                 { MAC_MODE, TG3_FL_NOT_5705,
10292                         0x00000000, 0x00ef6f8c },
10293                 { MAC_MODE, TG3_FL_5705,
10294                         0x00000000, 0x01ef6b8c },
10295                 { MAC_STATUS, TG3_FL_NOT_5705,
10296                         0x03800107, 0x00000000 },
10297                 { MAC_STATUS, TG3_FL_5705,
10298                         0x03800100, 0x00000000 },
10299                 { MAC_ADDR_0_HIGH, 0x0000,
10300                         0x00000000, 0x0000ffff },
10301                 { MAC_ADDR_0_LOW, 0x0000,
10302                         0x00000000, 0xffffffff },
10303                 { MAC_RX_MTU_SIZE, 0x0000,
10304                         0x00000000, 0x0000ffff },
10305                 { MAC_TX_MODE, 0x0000,
10306                         0x00000000, 0x00000070 },
10307                 { MAC_TX_LENGTHS, 0x0000,
10308                         0x00000000, 0x00003fff },
10309                 { MAC_RX_MODE, TG3_FL_NOT_5705,
10310                         0x00000000, 0x000007fc },
10311                 { MAC_RX_MODE, TG3_FL_5705,
10312                         0x00000000, 0x000007dc },
10313                 { MAC_HASH_REG_0, 0x0000,
10314                         0x00000000, 0xffffffff },
10315                 { MAC_HASH_REG_1, 0x0000,
10316                         0x00000000, 0xffffffff },
10317                 { MAC_HASH_REG_2, 0x0000,
10318                         0x00000000, 0xffffffff },
10319                 { MAC_HASH_REG_3, 0x0000,
10320                         0x00000000, 0xffffffff },
10321
10322                 /* Receive Data and Receive BD Initiator Control Registers. */
10323                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10324                         0x00000000, 0xffffffff },
10325                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10326                         0x00000000, 0xffffffff },
10327                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10328                         0x00000000, 0x00000003 },
10329                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10330                         0x00000000, 0xffffffff },
10331                 { RCVDBDI_STD_BD+0, 0x0000,
10332                         0x00000000, 0xffffffff },
10333                 { RCVDBDI_STD_BD+4, 0x0000,
10334                         0x00000000, 0xffffffff },
10335                 { RCVDBDI_STD_BD+8, 0x0000,
10336                         0x00000000, 0xffff0002 },
10337                 { RCVDBDI_STD_BD+0xc, 0x0000,
10338                         0x00000000, 0xffffffff },
10339
10340                 /* Receive BD Initiator Control Registers. */
10341                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10342                         0x00000000, 0xffffffff },
10343                 { RCVBDI_STD_THRESH, TG3_FL_5705,
10344                         0x00000000, 0x000003ff },
10345                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10346                         0x00000000, 0xffffffff },
10347
10348                 /* Host Coalescing Control Registers. */
10349                 { HOSTCC_MODE, TG3_FL_NOT_5705,
10350                         0x00000000, 0x00000004 },
10351                 { HOSTCC_MODE, TG3_FL_5705,
10352                         0x00000000, 0x000000f6 },
10353                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10354                         0x00000000, 0xffffffff },
10355                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10356                         0x00000000, 0x000003ff },
10357                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10358                         0x00000000, 0xffffffff },
10359                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10360                         0x00000000, 0x000003ff },
10361                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10362                         0x00000000, 0xffffffff },
10363                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10364                         0x00000000, 0x000000ff },
10365                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10366                         0x00000000, 0xffffffff },
10367                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10368                         0x00000000, 0x000000ff },
10369                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10370                         0x00000000, 0xffffffff },
10371                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10372                         0x00000000, 0xffffffff },
10373                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10374                         0x00000000, 0xffffffff },
10375                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10376                         0x00000000, 0x000000ff },
10377                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10378                         0x00000000, 0xffffffff },
10379                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10380                         0x00000000, 0x000000ff },
10381                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10382                         0x00000000, 0xffffffff },
10383                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10384                         0x00000000, 0xffffffff },
10385                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10386                         0x00000000, 0xffffffff },
10387                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10388                         0x00000000, 0xffffffff },
10389                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10390                         0x00000000, 0xffffffff },
10391                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10392                         0xffffffff, 0x00000000 },
10393                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10394                         0xffffffff, 0x00000000 },
10395
10396                 /* Buffer Manager Control Registers. */
10397                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10398                         0x00000000, 0x007fff80 },
10399                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10400                         0x00000000, 0x007fffff },
10401                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10402                         0x00000000, 0x0000003f },
10403                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10404                         0x00000000, 0x000001ff },
10405                 { BUFMGR_MB_HIGH_WATER, 0x0000,
10406                         0x00000000, 0x000001ff },
10407                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10408                         0xffffffff, 0x00000000 },
10409                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10410                         0xffffffff, 0x00000000 },
10411
10412                 /* Mailbox Registers */
10413                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10414                         0x00000000, 0x000001ff },
10415                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10416                         0x00000000, 0x000001ff },
10417                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10418                         0x00000000, 0x000007ff },
10419                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10420                         0x00000000, 0x000001ff },
10421
10422                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10423         };
10424
10425         is_5705 = is_5750 = 0;
10426         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10427                 is_5705 = 1;
10428                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10429                         is_5750 = 1;
10430         }
10431
10432         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10433                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10434                         continue;
10435
10436                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10437                         continue;
10438
10439                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10440                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
10441                         continue;
10442
10443                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10444                         continue;
10445
10446                 offset = (u32) reg_tbl[i].offset;
10447                 read_mask = reg_tbl[i].read_mask;
10448                 write_mask = reg_tbl[i].write_mask;
10449
10450                 /* Save the original register content */
10451                 save_val = tr32(offset);
10452
10453                 /* Determine the read-only value. */
10454                 read_val = save_val & read_mask;
10455
10456                 /* Write zero to the register, then make sure the read-only bits
10457                  * are not changed and the read/write bits are all zeros.
10458                  */
10459                 tw32(offset, 0);
10460
10461                 val = tr32(offset);
10462
10463                 /* Test the read-only and read/write bits. */
10464                 if (((val & read_mask) != read_val) || (val & write_mask))
10465                         goto out;
10466
10467                 /* Write ones to all the bits defined by RdMask and WrMask, then
10468                  * make sure the read-only bits are not changed and the
10469                  * read/write bits are all ones.
10470                  */
10471                 tw32(offset, read_mask | write_mask);
10472
10473                 val = tr32(offset);
10474
10475                 /* Test the read-only bits. */
10476                 if ((val & read_mask) != read_val)
10477                         goto out;
10478
10479                 /* Test the read/write bits. */
10480                 if ((val & write_mask) != write_mask)
10481                         goto out;
10482
10483                 tw32(offset, save_val);
10484         }
10485
10486         return 0;
10487
10488 out:
10489         if (netif_msg_hw(tp))
10490                 netdev_err(tp->dev,
10491                            "Register test failed at offset %x\n", offset);
10492         tw32(offset, save_val);
10493         return -EIO;
10494 }
10495
10496 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10497 {
10498         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10499         int i;
10500         u32 j;
10501
10502         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10503                 for (j = 0; j < len; j += 4) {
10504                         u32 val;
10505
10506                         tg3_write_mem(tp, offset + j, test_pattern[i]);
10507                         tg3_read_mem(tp, offset + j, &val);
10508                         if (val != test_pattern[i])
10509                                 return -EIO;
10510                 }
10511         }
10512         return 0;
10513 }
10514
10515 static int tg3_test_memory(struct tg3 *tp)
10516 {
10517         static struct mem_entry {
10518                 u32 offset;
10519                 u32 len;
10520         } mem_tbl_570x[] = {
10521                 { 0x00000000, 0x00b50},
10522                 { 0x00002000, 0x1c000},
10523                 { 0xffffffff, 0x00000}
10524         }, mem_tbl_5705[] = {
10525                 { 0x00000100, 0x0000c},
10526                 { 0x00000200, 0x00008},
10527                 { 0x00004000, 0x00800},
10528                 { 0x00006000, 0x01000},
10529                 { 0x00008000, 0x02000},
10530                 { 0x00010000, 0x0e000},
10531                 { 0xffffffff, 0x00000}
10532         }, mem_tbl_5755[] = {
10533                 { 0x00000200, 0x00008},
10534                 { 0x00004000, 0x00800},
10535                 { 0x00006000, 0x00800},
10536                 { 0x00008000, 0x02000},
10537                 { 0x00010000, 0x0c000},
10538                 { 0xffffffff, 0x00000}
10539         }, mem_tbl_5906[] = {
10540                 { 0x00000200, 0x00008},
10541                 { 0x00004000, 0x00400},
10542                 { 0x00006000, 0x00400},
10543                 { 0x00008000, 0x01000},
10544                 { 0x00010000, 0x01000},
10545                 { 0xffffffff, 0x00000}
10546         }, mem_tbl_5717[] = {
10547                 { 0x00000200, 0x00008},
10548                 { 0x00010000, 0x0a000},
10549                 { 0x00020000, 0x13c00},
10550                 { 0xffffffff, 0x00000}
10551         }, mem_tbl_57765[] = {
10552                 { 0x00000200, 0x00008},
10553                 { 0x00004000, 0x00800},
10554                 { 0x00006000, 0x09800},
10555                 { 0x00010000, 0x0a000},
10556                 { 0xffffffff, 0x00000}
10557         };
10558         struct mem_entry *mem_tbl;
10559         int err = 0;
10560         int i;
10561
10562         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
10563             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
10564                 mem_tbl = mem_tbl_5717;
10565         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10566                 mem_tbl = mem_tbl_57765;
10567         else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10568                 mem_tbl = mem_tbl_5755;
10569         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10570                 mem_tbl = mem_tbl_5906;
10571         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10572                 mem_tbl = mem_tbl_5705;
10573         else
10574                 mem_tbl = mem_tbl_570x;
10575
10576         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10577                 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
10578                 if (err)
10579                         break;
10580         }
10581
10582         return err;
10583 }
10584
10585 #define TG3_MAC_LOOPBACK        0
10586 #define TG3_PHY_LOOPBACK        1
10587
10588 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10589 {
10590         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10591         u32 desc_idx, coal_now;
10592         struct sk_buff *skb, *rx_skb;
10593         u8 *tx_data;
10594         dma_addr_t map;
10595         int num_pkts, tx_len, rx_len, i, err;
10596         struct tg3_rx_buffer_desc *desc;
10597         struct tg3_napi *tnapi, *rnapi;
10598         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
10599
10600         tnapi = &tp->napi[0];
10601         rnapi = &tp->napi[0];
10602         if (tp->irq_cnt > 1) {
10603                 rnapi = &tp->napi[1];
10604                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
10605                         tnapi = &tp->napi[1];
10606         }
10607         coal_now = tnapi->coal_now | rnapi->coal_now;
10608
10609         if (loopback_mode == TG3_MAC_LOOPBACK) {
10610                 /* HW errata - mac loopback fails in some cases on 5780.
10611                  * Normal traffic and PHY loopback are not affected by
10612                  * errata.
10613                  */
10614                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10615                         return 0;
10616
10617                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10618                            MAC_MODE_PORT_INT_LPBACK;
10619                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10620                         mac_mode |= MAC_MODE_LINK_POLARITY;
10621                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10622                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10623                 else
10624                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10625                 tw32(MAC_MODE, mac_mode);
10626         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10627                 u32 val;
10628
10629                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10630                         tg3_phy_fet_toggle_apd(tp, false);
10631                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10632                 } else
10633                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10634
10635                 tg3_phy_toggle_automdix(tp, 0);
10636
10637                 tg3_writephy(tp, MII_BMCR, val);
10638                 udelay(40);
10639
10640                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10641                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10642                         tg3_writephy(tp, MII_TG3_FET_PTEST,
10643                                      MII_TG3_FET_PTEST_FRC_TX_LINK |
10644                                      MII_TG3_FET_PTEST_FRC_TX_LOCK);
10645                         /* The write needs to be flushed for the AC131 */
10646                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10647                                 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
10648                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10649                 } else
10650                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10651
10652                 /* reset to prevent losing 1st rx packet intermittently */
10653                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10654                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10655                         udelay(10);
10656                         tw32_f(MAC_RX_MODE, tp->rx_mode);
10657                 }
10658                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10659                         u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
10660                         if (masked_phy_id == TG3_PHY_ID_BCM5401)
10661                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10662                         else if (masked_phy_id == TG3_PHY_ID_BCM5411)
10663                                 mac_mode |= MAC_MODE_LINK_POLARITY;
10664                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
10665                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10666                 }
10667                 tw32(MAC_MODE, mac_mode);
10668         } else {
10669                 return -EINVAL;
10670         }
10671
10672         err = -EIO;
10673
10674         tx_len = 1514;
10675         skb = netdev_alloc_skb(tp->dev, tx_len);
10676         if (!skb)
10677                 return -ENOMEM;
10678
10679         tx_data = skb_put(skb, tx_len);
10680         memcpy(tx_data, tp->dev->dev_addr, 6);
10681         memset(tx_data + 6, 0x0, 8);
10682
10683         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10684
10685         for (i = 14; i < tx_len; i++)
10686                 tx_data[i] = (u8) (i & 0xff);
10687
10688         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10689         if (pci_dma_mapping_error(tp->pdev, map)) {
10690                 dev_kfree_skb(skb);
10691                 return -EIO;
10692         }
10693
10694         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10695                rnapi->coal_now);
10696
10697         udelay(10);
10698
10699         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10700
10701         num_pkts = 0;
10702
10703         tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10704
10705         tnapi->tx_prod++;
10706         num_pkts++;
10707
10708         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10709         tr32_mailbox(tnapi->prodmbox);
10710
10711         udelay(10);
10712
10713         /* 350 usec to allow enough time on some 10/100 Mbps devices.  */
10714         for (i = 0; i < 35; i++) {
10715                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10716                        coal_now);
10717
10718                 udelay(10);
10719
10720                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10721                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10722                 if ((tx_idx == tnapi->tx_prod) &&
10723                     (rx_idx == (rx_start_idx + num_pkts)))
10724                         break;
10725         }
10726
10727         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10728         dev_kfree_skb(skb);
10729
10730         if (tx_idx != tnapi->tx_prod)
10731                 goto out;
10732
10733         if (rx_idx != rx_start_idx + num_pkts)
10734                 goto out;
10735
10736         desc = &rnapi->rx_rcb[rx_start_idx];
10737         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10738         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10739         if (opaque_key != RXD_OPAQUE_RING_STD)
10740                 goto out;
10741
10742         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10743             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10744                 goto out;
10745
10746         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10747         if (rx_len != tx_len)
10748                 goto out;
10749
10750         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10751
10752         map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10753         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10754
10755         for (i = 14; i < tx_len; i++) {
10756                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10757                         goto out;
10758         }
10759         err = 0;
10760
10761         /* tg3_free_rings will unmap and free the rx_skb */
10762 out:
10763         return err;
10764 }
10765
10766 #define TG3_MAC_LOOPBACK_FAILED         1
10767 #define TG3_PHY_LOOPBACK_FAILED         2
10768 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
10769                                          TG3_PHY_LOOPBACK_FAILED)
10770
10771 static int tg3_test_loopback(struct tg3 *tp)
10772 {
10773         int err = 0;
10774         u32 cpmuctrl = 0;
10775
10776         if (!netif_running(tp->dev))
10777                 return TG3_LOOPBACK_FAILED;
10778
10779         err = tg3_reset_hw(tp, 1);
10780         if (err)
10781                 return TG3_LOOPBACK_FAILED;
10782
10783         /* Turn off gphy autopowerdown. */
10784         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10785                 tg3_phy_toggle_apd(tp, false);
10786
10787         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10788                 int i;
10789                 u32 status;
10790
10791                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10792
10793                 /* Wait for up to 40 microseconds to acquire lock. */
10794                 for (i = 0; i < 4; i++) {
10795                         status = tr32(TG3_CPMU_MUTEX_GNT);
10796                         if (status == CPMU_MUTEX_GNT_DRIVER)
10797                                 break;
10798                         udelay(10);
10799                 }
10800
10801                 if (status != CPMU_MUTEX_GNT_DRIVER)
10802                         return TG3_LOOPBACK_FAILED;
10803
10804                 /* Turn off link-based power management. */
10805                 cpmuctrl = tr32(TG3_CPMU_CTRL);
10806                 tw32(TG3_CPMU_CTRL,
10807                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10808                                   CPMU_CTRL_LINK_AWARE_MODE));
10809         }
10810
10811         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10812                 err |= TG3_MAC_LOOPBACK_FAILED;
10813
10814         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10815                 tw32(TG3_CPMU_CTRL, cpmuctrl);
10816
10817                 /* Release the mutex */
10818                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10819         }
10820
10821         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10822             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10823                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10824                         err |= TG3_PHY_LOOPBACK_FAILED;
10825         }
10826
10827         /* Re-enable gphy autopowerdown. */
10828         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10829                 tg3_phy_toggle_apd(tp, true);
10830
10831         return err;
10832 }
10833
10834 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10835                           u64 *data)
10836 {
10837         struct tg3 *tp = netdev_priv(dev);
10838
10839         if (tp->link_config.phy_is_low_power)
10840                 tg3_set_power_state(tp, PCI_D0);
10841
10842         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10843
10844         if (tg3_test_nvram(tp) != 0) {
10845                 etest->flags |= ETH_TEST_FL_FAILED;
10846                 data[0] = 1;
10847         }
10848         if (tg3_test_link(tp) != 0) {
10849                 etest->flags |= ETH_TEST_FL_FAILED;
10850                 data[1] = 1;
10851         }
10852         if (etest->flags & ETH_TEST_FL_OFFLINE) {
10853                 int err, err2 = 0, irq_sync = 0;
10854
10855                 if (netif_running(dev)) {
10856                         tg3_phy_stop(tp);
10857                         tg3_netif_stop(tp);
10858                         irq_sync = 1;
10859                 }
10860
10861                 tg3_full_lock(tp, irq_sync);
10862
10863                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10864                 err = tg3_nvram_lock(tp);
10865                 tg3_halt_cpu(tp, RX_CPU_BASE);
10866                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10867                         tg3_halt_cpu(tp, TX_CPU_BASE);
10868                 if (!err)
10869                         tg3_nvram_unlock(tp);
10870
10871                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10872                         tg3_phy_reset(tp);
10873
10874                 if (tg3_test_registers(tp) != 0) {
10875                         etest->flags |= ETH_TEST_FL_FAILED;
10876                         data[2] = 1;
10877                 }
10878                 if (tg3_test_memory(tp) != 0) {
10879                         etest->flags |= ETH_TEST_FL_FAILED;
10880                         data[3] = 1;
10881                 }
10882                 if ((data[4] = tg3_test_loopback(tp)) != 0)
10883                         etest->flags |= ETH_TEST_FL_FAILED;
10884
10885                 tg3_full_unlock(tp);
10886
10887                 if (tg3_test_interrupt(tp) != 0) {
10888                         etest->flags |= ETH_TEST_FL_FAILED;
10889                         data[5] = 1;
10890                 }
10891
10892                 tg3_full_lock(tp, 0);
10893
10894                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10895                 if (netif_running(dev)) {
10896                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10897                         err2 = tg3_restart_hw(tp, 1);
10898                         if (!err2)
10899                                 tg3_netif_start(tp);
10900                 }
10901
10902                 tg3_full_unlock(tp);
10903
10904                 if (irq_sync && !err2)
10905                         tg3_phy_start(tp);
10906         }
10907         if (tp->link_config.phy_is_low_power)
10908                 tg3_set_power_state(tp, PCI_D3hot);
10909
10910 }
10911
10912 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10913 {
10914         struct mii_ioctl_data *data = if_mii(ifr);
10915         struct tg3 *tp = netdev_priv(dev);
10916         int err;
10917
10918         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10919                 struct phy_device *phydev;
10920                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10921                         return -EAGAIN;
10922                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10923                 return phy_mii_ioctl(phydev, ifr, cmd);
10924         }
10925
10926         switch (cmd) {
10927         case SIOCGMIIPHY:
10928                 data->phy_id = tp->phy_addr;
10929
10930                 /* fallthru */
10931         case SIOCGMIIREG: {
10932                 u32 mii_regval;
10933
10934                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10935                         break;                  /* We have no PHY */
10936
10937                 if (tp->link_config.phy_is_low_power)
10938                         return -EAGAIN;
10939
10940                 spin_lock_bh(&tp->lock);
10941                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10942                 spin_unlock_bh(&tp->lock);
10943
10944                 data->val_out = mii_regval;
10945
10946                 return err;
10947         }
10948
10949         case SIOCSMIIREG:
10950                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10951                         break;                  /* We have no PHY */
10952
10953                 if (tp->link_config.phy_is_low_power)
10954                         return -EAGAIN;
10955
10956                 spin_lock_bh(&tp->lock);
10957                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10958                 spin_unlock_bh(&tp->lock);
10959
10960                 return err;
10961
10962         default:
10963                 /* do nothing */
10964                 break;
10965         }
10966         return -EOPNOTSUPP;
10967 }
10968
10969 #if TG3_VLAN_TAG_USED
10970 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10971 {
10972         struct tg3 *tp = netdev_priv(dev);
10973
10974         if (!netif_running(dev)) {
10975                 tp->vlgrp = grp;
10976                 return;
10977         }
10978
10979         tg3_netif_stop(tp);
10980
10981         tg3_full_lock(tp, 0);
10982
10983         tp->vlgrp = grp;
10984
10985         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10986         __tg3_set_rx_mode(dev);
10987
10988         tg3_netif_start(tp);
10989
10990         tg3_full_unlock(tp);
10991 }
10992 #endif
10993
10994 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10995 {
10996         struct tg3 *tp = netdev_priv(dev);
10997
10998         memcpy(ec, &tp->coal, sizeof(*ec));
10999         return 0;
11000 }
11001
11002 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11003 {
11004         struct tg3 *tp = netdev_priv(dev);
11005         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11006         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11007
11008         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11009                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11010                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11011                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11012                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11013         }
11014
11015         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11016             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11017             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11018             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11019             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11020             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11021             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11022             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11023             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11024             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11025                 return -EINVAL;
11026
11027         /* No rx interrupts will be generated if both are zero */
11028         if ((ec->rx_coalesce_usecs == 0) &&
11029             (ec->rx_max_coalesced_frames == 0))
11030                 return -EINVAL;
11031
11032         /* No tx interrupts will be generated if both are zero */
11033         if ((ec->tx_coalesce_usecs == 0) &&
11034             (ec->tx_max_coalesced_frames == 0))
11035                 return -EINVAL;
11036
11037         /* Only copy relevant parameters, ignore all others. */
11038         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11039         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11040         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11041         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11042         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11043         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11044         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11045         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11046         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11047
11048         if (netif_running(dev)) {
11049                 tg3_full_lock(tp, 0);
11050                 __tg3_set_coalesce(tp, &tp->coal);
11051                 tg3_full_unlock(tp);
11052         }
11053         return 0;
11054 }
11055
11056 static const struct ethtool_ops tg3_ethtool_ops = {
11057         .get_settings           = tg3_get_settings,
11058         .set_settings           = tg3_set_settings,
11059         .get_drvinfo            = tg3_get_drvinfo,
11060         .get_regs_len           = tg3_get_regs_len,
11061         .get_regs               = tg3_get_regs,
11062         .get_wol                = tg3_get_wol,
11063         .set_wol                = tg3_set_wol,
11064         .get_msglevel           = tg3_get_msglevel,
11065         .set_msglevel           = tg3_set_msglevel,
11066         .nway_reset             = tg3_nway_reset,
11067         .get_link               = ethtool_op_get_link,
11068         .get_eeprom_len         = tg3_get_eeprom_len,
11069         .get_eeprom             = tg3_get_eeprom,
11070         .set_eeprom             = tg3_set_eeprom,
11071         .get_ringparam          = tg3_get_ringparam,
11072         .set_ringparam          = tg3_set_ringparam,
11073         .get_pauseparam         = tg3_get_pauseparam,
11074         .set_pauseparam         = tg3_set_pauseparam,
11075         .get_rx_csum            = tg3_get_rx_csum,
11076         .set_rx_csum            = tg3_set_rx_csum,
11077         .set_tx_csum            = tg3_set_tx_csum,
11078         .set_sg                 = ethtool_op_set_sg,
11079         .set_tso                = tg3_set_tso,
11080         .self_test              = tg3_self_test,
11081         .get_strings            = tg3_get_strings,
11082         .phys_id                = tg3_phys_id,
11083         .get_ethtool_stats      = tg3_get_ethtool_stats,
11084         .get_coalesce           = tg3_get_coalesce,
11085         .set_coalesce           = tg3_set_coalesce,
11086         .get_sset_count         = tg3_get_sset_count,
11087 };
11088
11089 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11090 {
11091         u32 cursize, val, magic;
11092
11093         tp->nvram_size = EEPROM_CHIP_SIZE;
11094
11095         if (tg3_nvram_read(tp, 0, &magic) != 0)
11096                 return;
11097
11098         if ((magic != TG3_EEPROM_MAGIC) &&
11099             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11100             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11101                 return;
11102
11103         /*
11104          * Size the chip by reading offsets at increasing powers of two.
11105          * When we encounter our validation signature, we know the addressing
11106          * has wrapped around, and thus have our chip size.
11107          */
11108         cursize = 0x10;
11109
11110         while (cursize < tp->nvram_size) {
11111                 if (tg3_nvram_read(tp, cursize, &val) != 0)
11112                         return;
11113
11114                 if (val == magic)
11115                         break;
11116
11117                 cursize <<= 1;
11118         }
11119
11120         tp->nvram_size = cursize;
11121 }
11122
11123 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11124 {
11125         u32 val;
11126
11127         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11128             tg3_nvram_read(tp, 0, &val) != 0)
11129                 return;
11130
11131         /* Selfboot format */
11132         if (val != TG3_EEPROM_MAGIC) {
11133                 tg3_get_eeprom_size(tp);
11134                 return;
11135         }
11136
11137         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11138                 if (val != 0) {
11139                         /* This is confusing.  We want to operate on the
11140                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
11141                          * call will read from NVRAM and byteswap the data
11142                          * according to the byteswapping settings for all
11143                          * other register accesses.  This ensures the data we
11144                          * want will always reside in the lower 16-bits.
11145                          * However, the data in NVRAM is in LE format, which
11146                          * means the data from the NVRAM read will always be
11147                          * opposite the endianness of the CPU.  The 16-bit
11148                          * byteswap then brings the data to CPU endianness.
11149                          */
11150                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11151                         return;
11152                 }
11153         }
11154         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11155 }
11156
11157 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11158 {
11159         u32 nvcfg1;
11160
11161         nvcfg1 = tr32(NVRAM_CFG1);
11162         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11163                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11164         } else {
11165                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11166                 tw32(NVRAM_CFG1, nvcfg1);
11167         }
11168
11169         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11170             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11171                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11172                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11173                         tp->nvram_jedecnum = JEDEC_ATMEL;
11174                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11175                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11176                         break;
11177                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11178                         tp->nvram_jedecnum = JEDEC_ATMEL;
11179                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11180                         break;
11181                 case FLASH_VENDOR_ATMEL_EEPROM:
11182                         tp->nvram_jedecnum = JEDEC_ATMEL;
11183                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11184                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11185                         break;
11186                 case FLASH_VENDOR_ST:
11187                         tp->nvram_jedecnum = JEDEC_ST;
11188                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11189                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11190                         break;
11191                 case FLASH_VENDOR_SAIFUN:
11192                         tp->nvram_jedecnum = JEDEC_SAIFUN;
11193                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11194                         break;
11195                 case FLASH_VENDOR_SST_SMALL:
11196                 case FLASH_VENDOR_SST_LARGE:
11197                         tp->nvram_jedecnum = JEDEC_SST;
11198                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11199                         break;
11200                 }
11201         } else {
11202                 tp->nvram_jedecnum = JEDEC_ATMEL;
11203                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11204                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11205         }
11206 }
11207
11208 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11209 {
11210         switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11211         case FLASH_5752PAGE_SIZE_256:
11212                 tp->nvram_pagesize = 256;
11213                 break;
11214         case FLASH_5752PAGE_SIZE_512:
11215                 tp->nvram_pagesize = 512;
11216                 break;
11217         case FLASH_5752PAGE_SIZE_1K:
11218                 tp->nvram_pagesize = 1024;
11219                 break;
11220         case FLASH_5752PAGE_SIZE_2K:
11221                 tp->nvram_pagesize = 2048;
11222                 break;
11223         case FLASH_5752PAGE_SIZE_4K:
11224                 tp->nvram_pagesize = 4096;
11225                 break;
11226         case FLASH_5752PAGE_SIZE_264:
11227                 tp->nvram_pagesize = 264;
11228                 break;
11229         case FLASH_5752PAGE_SIZE_528:
11230                 tp->nvram_pagesize = 528;
11231                 break;
11232         }
11233 }
11234
11235 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11236 {
11237         u32 nvcfg1;
11238
11239         nvcfg1 = tr32(NVRAM_CFG1);
11240
11241         /* NVRAM protection for TPM */
11242         if (nvcfg1 & (1 << 27))
11243                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11244
11245         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11246         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11247         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11248                 tp->nvram_jedecnum = JEDEC_ATMEL;
11249                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11250                 break;
11251         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11252                 tp->nvram_jedecnum = JEDEC_ATMEL;
11253                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11254                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11255                 break;
11256         case FLASH_5752VENDOR_ST_M45PE10:
11257         case FLASH_5752VENDOR_ST_M45PE20:
11258         case FLASH_5752VENDOR_ST_M45PE40:
11259                 tp->nvram_jedecnum = JEDEC_ST;
11260                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11261                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11262                 break;
11263         }
11264
11265         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11266                 tg3_nvram_get_pagesize(tp, nvcfg1);
11267         } else {
11268                 /* For eeprom, set pagesize to maximum eeprom size */
11269                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11270
11271                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11272                 tw32(NVRAM_CFG1, nvcfg1);
11273         }
11274 }
11275
11276 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11277 {
11278         u32 nvcfg1, protect = 0;
11279
11280         nvcfg1 = tr32(NVRAM_CFG1);
11281
11282         /* NVRAM protection for TPM */
11283         if (nvcfg1 & (1 << 27)) {
11284                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11285                 protect = 1;
11286         }
11287
11288         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11289         switch (nvcfg1) {
11290         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11291         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11292         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11293         case FLASH_5755VENDOR_ATMEL_FLASH_5:
11294                 tp->nvram_jedecnum = JEDEC_ATMEL;
11295                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11296                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11297                 tp->nvram_pagesize = 264;
11298                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11299                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11300                         tp->nvram_size = (protect ? 0x3e200 :
11301                                           TG3_NVRAM_SIZE_512KB);
11302                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11303                         tp->nvram_size = (protect ? 0x1f200 :
11304                                           TG3_NVRAM_SIZE_256KB);
11305                 else
11306                         tp->nvram_size = (protect ? 0x1f200 :
11307                                           TG3_NVRAM_SIZE_128KB);
11308                 break;
11309         case FLASH_5752VENDOR_ST_M45PE10:
11310         case FLASH_5752VENDOR_ST_M45PE20:
11311         case FLASH_5752VENDOR_ST_M45PE40:
11312                 tp->nvram_jedecnum = JEDEC_ST;
11313                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11314                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11315                 tp->nvram_pagesize = 256;
11316                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11317                         tp->nvram_size = (protect ?
11318                                           TG3_NVRAM_SIZE_64KB :
11319                                           TG3_NVRAM_SIZE_128KB);
11320                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11321                         tp->nvram_size = (protect ?
11322                                           TG3_NVRAM_SIZE_64KB :
11323                                           TG3_NVRAM_SIZE_256KB);
11324                 else
11325                         tp->nvram_size = (protect ?
11326                                           TG3_NVRAM_SIZE_128KB :
11327                                           TG3_NVRAM_SIZE_512KB);
11328                 break;
11329         }
11330 }
11331
11332 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11333 {
11334         u32 nvcfg1;
11335
11336         nvcfg1 = tr32(NVRAM_CFG1);
11337
11338         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11339         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11340         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11341         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11342         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11343                 tp->nvram_jedecnum = JEDEC_ATMEL;
11344                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11345                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11346
11347                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11348                 tw32(NVRAM_CFG1, nvcfg1);
11349                 break;
11350         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11351         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11352         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11353         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11354                 tp->nvram_jedecnum = JEDEC_ATMEL;
11355                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11356                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11357                 tp->nvram_pagesize = 264;
11358                 break;
11359         case FLASH_5752VENDOR_ST_M45PE10:
11360         case FLASH_5752VENDOR_ST_M45PE20:
11361         case FLASH_5752VENDOR_ST_M45PE40:
11362                 tp->nvram_jedecnum = JEDEC_ST;
11363                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11364                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11365                 tp->nvram_pagesize = 256;
11366                 break;
11367         }
11368 }
11369
11370 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11371 {
11372         u32 nvcfg1, protect = 0;
11373
11374         nvcfg1 = tr32(NVRAM_CFG1);
11375
11376         /* NVRAM protection for TPM */
11377         if (nvcfg1 & (1 << 27)) {
11378                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11379                 protect = 1;
11380         }
11381
11382         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11383         switch (nvcfg1) {
11384         case FLASH_5761VENDOR_ATMEL_ADB021D:
11385         case FLASH_5761VENDOR_ATMEL_ADB041D:
11386         case FLASH_5761VENDOR_ATMEL_ADB081D:
11387         case FLASH_5761VENDOR_ATMEL_ADB161D:
11388         case FLASH_5761VENDOR_ATMEL_MDB021D:
11389         case FLASH_5761VENDOR_ATMEL_MDB041D:
11390         case FLASH_5761VENDOR_ATMEL_MDB081D:
11391         case FLASH_5761VENDOR_ATMEL_MDB161D:
11392                 tp->nvram_jedecnum = JEDEC_ATMEL;
11393                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11394                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11395                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11396                 tp->nvram_pagesize = 256;
11397                 break;
11398         case FLASH_5761VENDOR_ST_A_M45PE20:
11399         case FLASH_5761VENDOR_ST_A_M45PE40:
11400         case FLASH_5761VENDOR_ST_A_M45PE80:
11401         case FLASH_5761VENDOR_ST_A_M45PE16:
11402         case FLASH_5761VENDOR_ST_M_M45PE20:
11403         case FLASH_5761VENDOR_ST_M_M45PE40:
11404         case FLASH_5761VENDOR_ST_M_M45PE80:
11405         case FLASH_5761VENDOR_ST_M_M45PE16:
11406                 tp->nvram_jedecnum = JEDEC_ST;
11407                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11408                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11409                 tp->nvram_pagesize = 256;
11410                 break;
11411         }
11412
11413         if (protect) {
11414                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11415         } else {
11416                 switch (nvcfg1) {
11417                 case FLASH_5761VENDOR_ATMEL_ADB161D:
11418                 case FLASH_5761VENDOR_ATMEL_MDB161D:
11419                 case FLASH_5761VENDOR_ST_A_M45PE16:
11420                 case FLASH_5761VENDOR_ST_M_M45PE16:
11421                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11422                         break;
11423                 case FLASH_5761VENDOR_ATMEL_ADB081D:
11424                 case FLASH_5761VENDOR_ATMEL_MDB081D:
11425                 case FLASH_5761VENDOR_ST_A_M45PE80:
11426                 case FLASH_5761VENDOR_ST_M_M45PE80:
11427                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11428                         break;
11429                 case FLASH_5761VENDOR_ATMEL_ADB041D:
11430                 case FLASH_5761VENDOR_ATMEL_MDB041D:
11431                 case FLASH_5761VENDOR_ST_A_M45PE40:
11432                 case FLASH_5761VENDOR_ST_M_M45PE40:
11433                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11434                         break;
11435                 case FLASH_5761VENDOR_ATMEL_ADB021D:
11436                 case FLASH_5761VENDOR_ATMEL_MDB021D:
11437                 case FLASH_5761VENDOR_ST_A_M45PE20:
11438                 case FLASH_5761VENDOR_ST_M_M45PE20:
11439                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11440                         break;
11441                 }
11442         }
11443 }
11444
11445 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11446 {
11447         tp->nvram_jedecnum = JEDEC_ATMEL;
11448         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11449         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11450 }
11451
11452 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11453 {
11454         u32 nvcfg1;
11455
11456         nvcfg1 = tr32(NVRAM_CFG1);
11457
11458         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11459         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11460         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11461                 tp->nvram_jedecnum = JEDEC_ATMEL;
11462                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11463                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11464
11465                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11466                 tw32(NVRAM_CFG1, nvcfg1);
11467                 return;
11468         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11469         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11470         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11471         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11472         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11473         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11474         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11475                 tp->nvram_jedecnum = JEDEC_ATMEL;
11476                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11477                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11478
11479                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11480                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11481                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11482                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11483                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11484                         break;
11485                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11486                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11487                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11488                         break;
11489                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11490                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11491                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11492                         break;
11493                 }
11494                 break;
11495         case FLASH_5752VENDOR_ST_M45PE10:
11496         case FLASH_5752VENDOR_ST_M45PE20:
11497         case FLASH_5752VENDOR_ST_M45PE40:
11498                 tp->nvram_jedecnum = JEDEC_ST;
11499                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11500                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11501
11502                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11503                 case FLASH_5752VENDOR_ST_M45PE10:
11504                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11505                         break;
11506                 case FLASH_5752VENDOR_ST_M45PE20:
11507                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11508                         break;
11509                 case FLASH_5752VENDOR_ST_M45PE40:
11510                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11511                         break;
11512                 }
11513                 break;
11514         default:
11515                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11516                 return;
11517         }
11518
11519         tg3_nvram_get_pagesize(tp, nvcfg1);
11520         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11521                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11522 }
11523
11524
11525 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11526 {
11527         u32 nvcfg1;
11528
11529         nvcfg1 = tr32(NVRAM_CFG1);
11530
11531         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11532         case FLASH_5717VENDOR_ATMEL_EEPROM:
11533         case FLASH_5717VENDOR_MICRO_EEPROM:
11534                 tp->nvram_jedecnum = JEDEC_ATMEL;
11535                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11536                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11537
11538                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11539                 tw32(NVRAM_CFG1, nvcfg1);
11540                 return;
11541         case FLASH_5717VENDOR_ATMEL_MDB011D:
11542         case FLASH_5717VENDOR_ATMEL_ADB011B:
11543         case FLASH_5717VENDOR_ATMEL_ADB011D:
11544         case FLASH_5717VENDOR_ATMEL_MDB021D:
11545         case FLASH_5717VENDOR_ATMEL_ADB021B:
11546         case FLASH_5717VENDOR_ATMEL_ADB021D:
11547         case FLASH_5717VENDOR_ATMEL_45USPT:
11548                 tp->nvram_jedecnum = JEDEC_ATMEL;
11549                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11550                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11551
11552                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11553                 case FLASH_5717VENDOR_ATMEL_MDB021D:
11554                 case FLASH_5717VENDOR_ATMEL_ADB021B:
11555                 case FLASH_5717VENDOR_ATMEL_ADB021D:
11556                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11557                         break;
11558                 default:
11559                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11560                         break;
11561                 }
11562                 break;
11563         case FLASH_5717VENDOR_ST_M_M25PE10:
11564         case FLASH_5717VENDOR_ST_A_M25PE10:
11565         case FLASH_5717VENDOR_ST_M_M45PE10:
11566         case FLASH_5717VENDOR_ST_A_M45PE10:
11567         case FLASH_5717VENDOR_ST_M_M25PE20:
11568         case FLASH_5717VENDOR_ST_A_M25PE20:
11569         case FLASH_5717VENDOR_ST_M_M45PE20:
11570         case FLASH_5717VENDOR_ST_A_M45PE20:
11571         case FLASH_5717VENDOR_ST_25USPT:
11572         case FLASH_5717VENDOR_ST_45USPT:
11573                 tp->nvram_jedecnum = JEDEC_ST;
11574                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11575                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11576
11577                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11578                 case FLASH_5717VENDOR_ST_M_M25PE20:
11579                 case FLASH_5717VENDOR_ST_A_M25PE20:
11580                 case FLASH_5717VENDOR_ST_M_M45PE20:
11581                 case FLASH_5717VENDOR_ST_A_M45PE20:
11582                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11583                         break;
11584                 default:
11585                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11586                         break;
11587                 }
11588                 break;
11589         default:
11590                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11591                 return;
11592         }
11593
11594         tg3_nvram_get_pagesize(tp, nvcfg1);
11595         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11596                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11597 }
11598
11599 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11600 static void __devinit tg3_nvram_init(struct tg3 *tp)
11601 {
11602         tw32_f(GRC_EEPROM_ADDR,
11603              (EEPROM_ADDR_FSM_RESET |
11604               (EEPROM_DEFAULT_CLOCK_PERIOD <<
11605                EEPROM_ADDR_CLKPERD_SHIFT)));
11606
11607         msleep(1);
11608
11609         /* Enable seeprom accesses. */
11610         tw32_f(GRC_LOCAL_CTRL,
11611              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11612         udelay(100);
11613
11614         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11615             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11616                 tp->tg3_flags |= TG3_FLAG_NVRAM;
11617
11618                 if (tg3_nvram_lock(tp)) {
11619                         netdev_warn(tp->dev,
11620                                     "Cannot get nvram lock, %s failed\n",
11621                                     __func__);
11622                         return;
11623                 }
11624                 tg3_enable_nvram_access(tp);
11625
11626                 tp->nvram_size = 0;
11627
11628                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11629                         tg3_get_5752_nvram_info(tp);
11630                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11631                         tg3_get_5755_nvram_info(tp);
11632                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11633                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11634                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11635                         tg3_get_5787_nvram_info(tp);
11636                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11637                         tg3_get_5761_nvram_info(tp);
11638                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11639                         tg3_get_5906_nvram_info(tp);
11640                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11641                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11642                         tg3_get_57780_nvram_info(tp);
11643                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
11644                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
11645                         tg3_get_5717_nvram_info(tp);
11646                 else
11647                         tg3_get_nvram_info(tp);
11648
11649                 if (tp->nvram_size == 0)
11650                         tg3_get_nvram_size(tp);
11651
11652                 tg3_disable_nvram_access(tp);
11653                 tg3_nvram_unlock(tp);
11654
11655         } else {
11656                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11657
11658                 tg3_get_eeprom_size(tp);
11659         }
11660 }
11661
11662 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11663                                     u32 offset, u32 len, u8 *buf)
11664 {
11665         int i, j, rc = 0;
11666         u32 val;
11667
11668         for (i = 0; i < len; i += 4) {
11669                 u32 addr;
11670                 __be32 data;
11671
11672                 addr = offset + i;
11673
11674                 memcpy(&data, buf + i, 4);
11675
11676                 /*
11677                  * The SEEPROM interface expects the data to always be opposite
11678                  * the native endian format.  We accomplish this by reversing
11679                  * all the operations that would have been performed on the
11680                  * data from a call to tg3_nvram_read_be32().
11681                  */
11682                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11683
11684                 val = tr32(GRC_EEPROM_ADDR);
11685                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11686
11687                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11688                         EEPROM_ADDR_READ);
11689                 tw32(GRC_EEPROM_ADDR, val |
11690                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
11691                         (addr & EEPROM_ADDR_ADDR_MASK) |
11692                         EEPROM_ADDR_START |
11693                         EEPROM_ADDR_WRITE);
11694
11695                 for (j = 0; j < 1000; j++) {
11696                         val = tr32(GRC_EEPROM_ADDR);
11697
11698                         if (val & EEPROM_ADDR_COMPLETE)
11699                                 break;
11700                         msleep(1);
11701                 }
11702                 if (!(val & EEPROM_ADDR_COMPLETE)) {
11703                         rc = -EBUSY;
11704                         break;
11705                 }
11706         }
11707
11708         return rc;
11709 }
11710
11711 /* offset and length are dword aligned */
11712 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11713                 u8 *buf)
11714 {
11715         int ret = 0;
11716         u32 pagesize = tp->nvram_pagesize;
11717         u32 pagemask = pagesize - 1;
11718         u32 nvram_cmd;
11719         u8 *tmp;
11720
11721         tmp = kmalloc(pagesize, GFP_KERNEL);
11722         if (tmp == NULL)
11723                 return -ENOMEM;
11724
11725         while (len) {
11726                 int j;
11727                 u32 phy_addr, page_off, size;
11728
11729                 phy_addr = offset & ~pagemask;
11730
11731                 for (j = 0; j < pagesize; j += 4) {
11732                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
11733                                                   (__be32 *) (tmp + j));
11734                         if (ret)
11735                                 break;
11736                 }
11737                 if (ret)
11738                         break;
11739
11740                 page_off = offset & pagemask;
11741                 size = pagesize;
11742                 if (len < size)
11743                         size = len;
11744
11745                 len -= size;
11746
11747                 memcpy(tmp + page_off, buf, size);
11748
11749                 offset = offset + (pagesize - page_off);
11750
11751                 tg3_enable_nvram_access(tp);
11752
11753                 /*
11754                  * Before we can erase the flash page, we need
11755                  * to issue a special "write enable" command.
11756                  */
11757                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11758
11759                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11760                         break;
11761
11762                 /* Erase the target page */
11763                 tw32(NVRAM_ADDR, phy_addr);
11764
11765                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11766                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11767
11768                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11769                         break;
11770
11771                 /* Issue another write enable to start the write. */
11772                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11773
11774                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11775                         break;
11776
11777                 for (j = 0; j < pagesize; j += 4) {
11778                         __be32 data;
11779
11780                         data = *((__be32 *) (tmp + j));
11781
11782                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
11783
11784                         tw32(NVRAM_ADDR, phy_addr + j);
11785
11786                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11787                                 NVRAM_CMD_WR;
11788
11789                         if (j == 0)
11790                                 nvram_cmd |= NVRAM_CMD_FIRST;
11791                         else if (j == (pagesize - 4))
11792                                 nvram_cmd |= NVRAM_CMD_LAST;
11793
11794                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11795                                 break;
11796                 }
11797                 if (ret)
11798                         break;
11799         }
11800
11801         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11802         tg3_nvram_exec_cmd(tp, nvram_cmd);
11803
11804         kfree(tmp);
11805
11806         return ret;
11807 }
11808
11809 /* offset and length are dword aligned */
11810 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11811                 u8 *buf)
11812 {
11813         int i, ret = 0;
11814
11815         for (i = 0; i < len; i += 4, offset += 4) {
11816                 u32 page_off, phy_addr, nvram_cmd;
11817                 __be32 data;
11818
11819                 memcpy(&data, buf + i, 4);
11820                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11821
11822                 page_off = offset % tp->nvram_pagesize;
11823
11824                 phy_addr = tg3_nvram_phys_addr(tp, offset);
11825
11826                 tw32(NVRAM_ADDR, phy_addr);
11827
11828                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11829
11830                 if (page_off == 0 || i == 0)
11831                         nvram_cmd |= NVRAM_CMD_FIRST;
11832                 if (page_off == (tp->nvram_pagesize - 4))
11833                         nvram_cmd |= NVRAM_CMD_LAST;
11834
11835                 if (i == (len - 4))
11836                         nvram_cmd |= NVRAM_CMD_LAST;
11837
11838                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11839                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11840                     (tp->nvram_jedecnum == JEDEC_ST) &&
11841                     (nvram_cmd & NVRAM_CMD_FIRST)) {
11842
11843                         if ((ret = tg3_nvram_exec_cmd(tp,
11844                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11845                                 NVRAM_CMD_DONE)))
11846
11847                                 break;
11848                 }
11849                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11850                         /* We always do complete word writes to eeprom. */
11851                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11852                 }
11853
11854                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11855                         break;
11856         }
11857         return ret;
11858 }
11859
11860 /* offset and length are dword aligned */
11861 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11862 {
11863         int ret;
11864
11865         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11866                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11867                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
11868                 udelay(40);
11869         }
11870
11871         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11872                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11873         } else {
11874                 u32 grc_mode;
11875
11876                 ret = tg3_nvram_lock(tp);
11877                 if (ret)
11878                         return ret;
11879
11880                 tg3_enable_nvram_access(tp);
11881                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11882                     !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
11883                         tw32(NVRAM_WRITE1, 0x406);
11884
11885                 grc_mode = tr32(GRC_MODE);
11886                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11887
11888                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11889                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11890
11891                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
11892                                 buf);
11893                 } else {
11894                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11895                                 buf);
11896                 }
11897
11898                 grc_mode = tr32(GRC_MODE);
11899                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11900
11901                 tg3_disable_nvram_access(tp);
11902                 tg3_nvram_unlock(tp);
11903         }
11904
11905         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11906                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11907                 udelay(40);
11908         }
11909
11910         return ret;
11911 }
11912
11913 struct subsys_tbl_ent {
11914         u16 subsys_vendor, subsys_devid;
11915         u32 phy_id;
11916 };
11917
11918 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
11919         /* Broadcom boards. */
11920         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11921           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
11922         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11923           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
11924         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11925           TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
11926         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11927           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
11928         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11929           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
11930         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11931           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
11932         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11933           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
11934         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11935           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
11936         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11937           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
11938         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11939           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
11940         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11941           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
11942
11943         /* 3com boards. */
11944         { TG3PCI_SUBVENDOR_ID_3COM,
11945           TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
11946         { TG3PCI_SUBVENDOR_ID_3COM,
11947           TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
11948         { TG3PCI_SUBVENDOR_ID_3COM,
11949           TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
11950         { TG3PCI_SUBVENDOR_ID_3COM,
11951           TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
11952         { TG3PCI_SUBVENDOR_ID_3COM,
11953           TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
11954
11955         /* DELL boards. */
11956         { TG3PCI_SUBVENDOR_ID_DELL,
11957           TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
11958         { TG3PCI_SUBVENDOR_ID_DELL,
11959           TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
11960         { TG3PCI_SUBVENDOR_ID_DELL,
11961           TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
11962         { TG3PCI_SUBVENDOR_ID_DELL,
11963           TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
11964
11965         /* Compaq boards. */
11966         { TG3PCI_SUBVENDOR_ID_COMPAQ,
11967           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
11968         { TG3PCI_SUBVENDOR_ID_COMPAQ,
11969           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
11970         { TG3PCI_SUBVENDOR_ID_COMPAQ,
11971           TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
11972         { TG3PCI_SUBVENDOR_ID_COMPAQ,
11973           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
11974         { TG3PCI_SUBVENDOR_ID_COMPAQ,
11975           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
11976
11977         /* IBM boards. */
11978         { TG3PCI_SUBVENDOR_ID_IBM,
11979           TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
11980 };
11981
11982 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
11983 {
11984         int i;
11985
11986         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11987                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11988                      tp->pdev->subsystem_vendor) &&
11989                     (subsys_id_to_phy_id[i].subsys_devid ==
11990                      tp->pdev->subsystem_device))
11991                         return &subsys_id_to_phy_id[i];
11992         }
11993         return NULL;
11994 }
11995
11996 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
11997 {
11998         u32 val;
11999         u16 pmcsr;
12000
12001         /* On some early chips the SRAM cannot be accessed in D3hot state,
12002          * so need make sure we're in D0.
12003          */
12004         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12005         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12006         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12007         msleep(1);
12008
12009         /* Make sure register accesses (indirect or otherwise)
12010          * will function correctly.
12011          */
12012         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12013                                tp->misc_host_ctrl);
12014
12015         /* The memory arbiter has to be enabled in order for SRAM accesses
12016          * to succeed.  Normally on powerup the tg3 chip firmware will make
12017          * sure it is enabled, but other entities such as system netboot
12018          * code might disable it.
12019          */
12020         val = tr32(MEMARB_MODE);
12021         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12022
12023         tp->phy_id = TG3_PHY_ID_INVALID;
12024         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12025
12026         /* Assume an onboard device and WOL capable by default.  */
12027         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12028
12029         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12030                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12031                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12032                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12033                 }
12034                 val = tr32(VCPU_CFGSHDW);
12035                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12036                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12037                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12038                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
12039                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12040                 goto done;
12041         }
12042
12043         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12044         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12045                 u32 nic_cfg, led_cfg;
12046                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12047                 int eeprom_phy_serdes = 0;
12048
12049                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12050                 tp->nic_sram_data_cfg = nic_cfg;
12051
12052                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12053                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12054                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12055                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12056                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12057                     (ver > 0) && (ver < 0x100))
12058                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12059
12060                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12061                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12062
12063                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12064                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12065                         eeprom_phy_serdes = 1;
12066
12067                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12068                 if (nic_phy_id != 0) {
12069                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12070                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12071
12072                         eeprom_phy_id  = (id1 >> 16) << 10;
12073                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
12074                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
12075                 } else
12076                         eeprom_phy_id = 0;
12077
12078                 tp->phy_id = eeprom_phy_id;
12079                 if (eeprom_phy_serdes) {
12080                         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12081                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12082                         else
12083                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
12084                 }
12085
12086                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12087                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12088                                     SHASTA_EXT_LED_MODE_MASK);
12089                 else
12090                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12091
12092                 switch (led_cfg) {
12093                 default:
12094                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12095                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12096                         break;
12097
12098                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12099                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12100                         break;
12101
12102                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12103                         tp->led_ctrl = LED_CTRL_MODE_MAC;
12104
12105                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12106                          * read on some older 5700/5701 bootcode.
12107                          */
12108                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12109                             ASIC_REV_5700 ||
12110                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
12111                             ASIC_REV_5701)
12112                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12113
12114                         break;
12115
12116                 case SHASTA_EXT_LED_SHARED:
12117                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
12118                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12119                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12120                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12121                                                  LED_CTRL_MODE_PHY_2);
12122                         break;
12123
12124                 case SHASTA_EXT_LED_MAC:
12125                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12126                         break;
12127
12128                 case SHASTA_EXT_LED_COMBO:
12129                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
12130                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12131                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12132                                                  LED_CTRL_MODE_PHY_2);
12133                         break;
12134
12135                 }
12136
12137                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12138                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12139                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12140                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12141
12142                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12143                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12144
12145                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12146                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12147                         if ((tp->pdev->subsystem_vendor ==
12148                              PCI_VENDOR_ID_ARIMA) &&
12149                             (tp->pdev->subsystem_device == 0x205a ||
12150                              tp->pdev->subsystem_device == 0x2063))
12151                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12152                 } else {
12153                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12154                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12155                 }
12156
12157                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12158                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12159                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12160                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12161                 }
12162
12163                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12164                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12165                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12166
12167                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
12168                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12169                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12170
12171                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12172                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12173                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12174
12175                 if (cfg2 & (1 << 17))
12176                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
12177
12178                 /* serdes signal pre-emphasis in register 0x590 set by */
12179                 /* bootcode if bit 18 is set */
12180                 if (cfg2 & (1 << 18))
12181                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
12182
12183                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12184                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
12185                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12186                         tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
12187
12188                 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12189                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12190                     !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
12191                         u32 cfg3;
12192
12193                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12194                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12195                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12196                 }
12197
12198                 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12199                         tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
12200                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12201                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12202                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12203                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12204         }
12205 done:
12206         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12207         device_set_wakeup_enable(&tp->pdev->dev,
12208                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12209 }
12210
12211 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12212 {
12213         int i;
12214         u32 val;
12215
12216         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12217         tw32(OTP_CTRL, cmd);
12218
12219         /* Wait for up to 1 ms for command to execute. */
12220         for (i = 0; i < 100; i++) {
12221                 val = tr32(OTP_STATUS);
12222                 if (val & OTP_STATUS_CMD_DONE)
12223                         break;
12224                 udelay(10);
12225         }
12226
12227         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12228 }
12229
12230 /* Read the gphy configuration from the OTP region of the chip.  The gphy
12231  * configuration is a 32-bit value that straddles the alignment boundary.
12232  * We do two 32-bit reads and then shift and merge the results.
12233  */
12234 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12235 {
12236         u32 bhalf_otp, thalf_otp;
12237
12238         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12239
12240         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12241                 return 0;
12242
12243         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12244
12245         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12246                 return 0;
12247
12248         thalf_otp = tr32(OTP_READ_DATA);
12249
12250         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12251
12252         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12253                 return 0;
12254
12255         bhalf_otp = tr32(OTP_READ_DATA);
12256
12257         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12258 }
12259
12260 static int __devinit tg3_phy_probe(struct tg3 *tp)
12261 {
12262         u32 hw_phy_id_1, hw_phy_id_2;
12263         u32 hw_phy_id, hw_phy_id_masked;
12264         int err;
12265
12266         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12267                 return tg3_phy_init(tp);
12268
12269         /* Reading the PHY ID register can conflict with ASF
12270          * firmware access to the PHY hardware.
12271          */
12272         err = 0;
12273         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12274             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12275                 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
12276         } else {
12277                 /* Now read the physical PHY_ID from the chip and verify
12278                  * that it is sane.  If it doesn't look good, we fall back
12279                  * to either the hard-coded table based PHY_ID and failing
12280                  * that the value found in the eeprom area.
12281                  */
12282                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12283                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12284
12285                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
12286                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12287                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
12288
12289                 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
12290         }
12291
12292         if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
12293                 tp->phy_id = hw_phy_id;
12294                 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
12295                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12296                 else
12297                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
12298         } else {
12299                 if (tp->phy_id != TG3_PHY_ID_INVALID) {
12300                         /* Do nothing, phy ID already set up in
12301                          * tg3_get_eeprom_hw_cfg().
12302                          */
12303                 } else {
12304                         struct subsys_tbl_ent *p;
12305
12306                         /* No eeprom signature?  Try the hardcoded
12307                          * subsys device table.
12308                          */
12309                         p = tg3_lookup_by_subsys(tp);
12310                         if (!p)
12311                                 return -ENODEV;
12312
12313                         tp->phy_id = p->phy_id;
12314                         if (!tp->phy_id ||
12315                             tp->phy_id == TG3_PHY_ID_BCM8002)
12316                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12317                 }
12318         }
12319
12320         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
12321             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12322             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12323                 u32 bmsr, adv_reg, tg3_ctrl, mask;
12324
12325                 tg3_readphy(tp, MII_BMSR, &bmsr);
12326                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12327                     (bmsr & BMSR_LSTATUS))
12328                         goto skip_phy_reset;
12329
12330                 err = tg3_phy_reset(tp);
12331                 if (err)
12332                         return err;
12333
12334                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12335                            ADVERTISE_100HALF | ADVERTISE_100FULL |
12336                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12337                 tg3_ctrl = 0;
12338                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12339                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12340                                     MII_TG3_CTRL_ADV_1000_FULL);
12341                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12342                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12343                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12344                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
12345                 }
12346
12347                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12348                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12349                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12350                 if (!tg3_copper_is_advertising_all(tp, mask)) {
12351                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12352
12353                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12354                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12355
12356                         tg3_writephy(tp, MII_BMCR,
12357                                      BMCR_ANENABLE | BMCR_ANRESTART);
12358                 }
12359                 tg3_phy_set_wirespeed(tp);
12360
12361                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12362                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12363                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12364         }
12365
12366 skip_phy_reset:
12367         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
12368                 err = tg3_init_5401phy_dsp(tp);
12369                 if (err)
12370                         return err;
12371
12372                 err = tg3_init_5401phy_dsp(tp);
12373         }
12374
12375         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
12376                 tp->link_config.advertising =
12377                         (ADVERTISED_1000baseT_Half |
12378                          ADVERTISED_1000baseT_Full |
12379                          ADVERTISED_Autoneg |
12380                          ADVERTISED_FIBRE);
12381         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12382                 tp->link_config.advertising &=
12383                         ~(ADVERTISED_1000baseT_Half |
12384                           ADVERTISED_1000baseT_Full);
12385
12386         return err;
12387 }
12388
12389 static void __devinit tg3_read_vpd(struct tg3 *tp)
12390 {
12391         u8 vpd_data[TG3_NVM_VPD_LEN];
12392         unsigned int block_end, rosize, len;
12393         int j, i = 0;
12394         u32 magic;
12395
12396         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12397             tg3_nvram_read(tp, 0x0, &magic))
12398                 goto out_not_found;
12399
12400         if (magic == TG3_EEPROM_MAGIC) {
12401                 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12402                         u32 tmp;
12403
12404                         /* The data is in little-endian format in NVRAM.
12405                          * Use the big-endian read routines to preserve
12406                          * the byte order as it exists in NVRAM.
12407                          */
12408                         if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12409                                 goto out_not_found;
12410
12411                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12412                 }
12413         } else {
12414                 ssize_t cnt;
12415                 unsigned int pos = 0;
12416
12417                 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12418                         cnt = pci_read_vpd(tp->pdev, pos,
12419                                            TG3_NVM_VPD_LEN - pos,
12420                                            &vpd_data[pos]);
12421                         if (cnt == -ETIMEDOUT || -EINTR)
12422                                 cnt = 0;
12423                         else if (cnt < 0)
12424                                 goto out_not_found;
12425                 }
12426                 if (pos != TG3_NVM_VPD_LEN)
12427                         goto out_not_found;
12428         }
12429
12430         i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
12431                              PCI_VPD_LRDT_RO_DATA);
12432         if (i < 0)
12433                 goto out_not_found;
12434
12435         rosize = pci_vpd_lrdt_size(&vpd_data[i]);
12436         block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
12437         i += PCI_VPD_LRDT_TAG_SIZE;
12438
12439         if (block_end > TG3_NVM_VPD_LEN)
12440                 goto out_not_found;
12441
12442         j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12443                                       PCI_VPD_RO_KEYWORD_MFR_ID);
12444         if (j > 0) {
12445                 len = pci_vpd_info_field_size(&vpd_data[j]);
12446
12447                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12448                 if (j + len > block_end || len != 4 ||
12449                     memcmp(&vpd_data[j], "1028", 4))
12450                         goto partno;
12451
12452                 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12453                                               PCI_VPD_RO_KEYWORD_VENDOR0);
12454                 if (j < 0)
12455                         goto partno;
12456
12457                 len = pci_vpd_info_field_size(&vpd_data[j]);
12458
12459                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12460                 if (j + len > block_end)
12461                         goto partno;
12462
12463                 memcpy(tp->fw_ver, &vpd_data[j], len);
12464                 strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
12465         }
12466
12467 partno:
12468         i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12469                                       PCI_VPD_RO_KEYWORD_PARTNO);
12470         if (i < 0)
12471                 goto out_not_found;
12472
12473         len = pci_vpd_info_field_size(&vpd_data[i]);
12474
12475         i += PCI_VPD_INFO_FLD_HDR_SIZE;
12476         if (len > TG3_BPN_SIZE ||
12477             (len + i) > TG3_NVM_VPD_LEN)
12478                 goto out_not_found;
12479
12480         memcpy(tp->board_part_number, &vpd_data[i], len);
12481
12482         return;
12483
12484 out_not_found:
12485         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12486                 strcpy(tp->board_part_number, "BCM95906");
12487         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12488                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12489                 strcpy(tp->board_part_number, "BCM57780");
12490         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12491                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12492                 strcpy(tp->board_part_number, "BCM57760");
12493         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12494                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12495                 strcpy(tp->board_part_number, "BCM57790");
12496         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12497                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12498                 strcpy(tp->board_part_number, "BCM57788");
12499         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12500                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
12501                 strcpy(tp->board_part_number, "BCM57761");
12502         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12503                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
12504                 strcpy(tp->board_part_number, "BCM57765");
12505         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12506                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
12507                 strcpy(tp->board_part_number, "BCM57781");
12508         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12509                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
12510                 strcpy(tp->board_part_number, "BCM57785");
12511         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12512                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
12513                 strcpy(tp->board_part_number, "BCM57791");
12514         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12515                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12516                 strcpy(tp->board_part_number, "BCM57795");
12517         else
12518                 strcpy(tp->board_part_number, "none");
12519 }
12520
12521 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12522 {
12523         u32 val;
12524
12525         if (tg3_nvram_read(tp, offset, &val) ||
12526             (val & 0xfc000000) != 0x0c000000 ||
12527             tg3_nvram_read(tp, offset + 4, &val) ||
12528             val != 0)
12529                 return 0;
12530
12531         return 1;
12532 }
12533
12534 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12535 {
12536         u32 val, offset, start, ver_offset;
12537         int i, dst_off;
12538         bool newver = false;
12539
12540         if (tg3_nvram_read(tp, 0xc, &offset) ||
12541             tg3_nvram_read(tp, 0x4, &start))
12542                 return;
12543
12544         offset = tg3_nvram_logical_addr(tp, offset);
12545
12546         if (tg3_nvram_read(tp, offset, &val))
12547                 return;
12548
12549         if ((val & 0xfc000000) == 0x0c000000) {
12550                 if (tg3_nvram_read(tp, offset + 4, &val))
12551                         return;
12552
12553                 if (val == 0)
12554                         newver = true;
12555         }
12556
12557         dst_off = strlen(tp->fw_ver);
12558
12559         if (newver) {
12560                 if (TG3_VER_SIZE - dst_off < 16 ||
12561                     tg3_nvram_read(tp, offset + 8, &ver_offset))
12562                         return;
12563
12564                 offset = offset + ver_offset - start;
12565                 for (i = 0; i < 16; i += 4) {
12566                         __be32 v;
12567                         if (tg3_nvram_read_be32(tp, offset + i, &v))
12568                                 return;
12569
12570                         memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
12571                 }
12572         } else {
12573                 u32 major, minor;
12574
12575                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12576                         return;
12577
12578                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12579                         TG3_NVM_BCVER_MAJSFT;
12580                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12581                 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
12582                          "v%d.%02d", major, minor);
12583         }
12584 }
12585
12586 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12587 {
12588         u32 val, major, minor;
12589
12590         /* Use native endian representation */
12591         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12592                 return;
12593
12594         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12595                 TG3_NVM_HWSB_CFG1_MAJSFT;
12596         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12597                 TG3_NVM_HWSB_CFG1_MINSFT;
12598
12599         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12600 }
12601
12602 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12603 {
12604         u32 offset, major, minor, build;
12605
12606         strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
12607
12608         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12609                 return;
12610
12611         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12612         case TG3_EEPROM_SB_REVISION_0:
12613                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12614                 break;
12615         case TG3_EEPROM_SB_REVISION_2:
12616                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12617                 break;
12618         case TG3_EEPROM_SB_REVISION_3:
12619                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12620                 break;
12621         case TG3_EEPROM_SB_REVISION_4:
12622                 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
12623                 break;
12624         case TG3_EEPROM_SB_REVISION_5:
12625                 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
12626                 break;
12627         default:
12628                 return;
12629         }
12630
12631         if (tg3_nvram_read(tp, offset, &val))
12632                 return;
12633
12634         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12635                 TG3_EEPROM_SB_EDH_BLD_SHFT;
12636         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12637                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12638         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
12639
12640         if (minor > 99 || build > 26)
12641                 return;
12642
12643         offset = strlen(tp->fw_ver);
12644         snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
12645                  " v%d.%02d", major, minor);
12646
12647         if (build > 0) {
12648                 offset = strlen(tp->fw_ver);
12649                 if (offset < TG3_VER_SIZE - 1)
12650                         tp->fw_ver[offset] = 'a' + build - 1;
12651         }
12652 }
12653
12654 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12655 {
12656         u32 val, offset, start;
12657         int i, vlen;
12658
12659         for (offset = TG3_NVM_DIR_START;
12660              offset < TG3_NVM_DIR_END;
12661              offset += TG3_NVM_DIRENT_SIZE) {
12662                 if (tg3_nvram_read(tp, offset, &val))
12663                         return;
12664
12665                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12666                         break;
12667         }
12668
12669         if (offset == TG3_NVM_DIR_END)
12670                 return;
12671
12672         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12673                 start = 0x08000000;
12674         else if (tg3_nvram_read(tp, offset - 4, &start))
12675                 return;
12676
12677         if (tg3_nvram_read(tp, offset + 4, &offset) ||
12678             !tg3_fw_img_is_valid(tp, offset) ||
12679             tg3_nvram_read(tp, offset + 8, &val))
12680                 return;
12681
12682         offset += val - start;
12683
12684         vlen = strlen(tp->fw_ver);
12685
12686         tp->fw_ver[vlen++] = ',';
12687         tp->fw_ver[vlen++] = ' ';
12688
12689         for (i = 0; i < 4; i++) {
12690                 __be32 v;
12691                 if (tg3_nvram_read_be32(tp, offset, &v))
12692                         return;
12693
12694                 offset += sizeof(v);
12695
12696                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12697                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12698                         break;
12699                 }
12700
12701                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12702                 vlen += sizeof(v);
12703         }
12704 }
12705
12706 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12707 {
12708         int vlen;
12709         u32 apedata;
12710         char *fwtype;
12711
12712         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12713             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
12714                 return;
12715
12716         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12717         if (apedata != APE_SEG_SIG_MAGIC)
12718                 return;
12719
12720         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12721         if (!(apedata & APE_FW_STATUS_READY))
12722                 return;
12723
12724         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12725
12726         if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI)
12727                 fwtype = "NCSI";
12728         else
12729                 fwtype = "DASH";
12730
12731         vlen = strlen(tp->fw_ver);
12732
12733         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
12734                  fwtype,
12735                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12736                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12737                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12738                  (apedata & APE_FW_VERSION_BLDMSK));
12739 }
12740
12741 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12742 {
12743         u32 val;
12744         bool vpd_vers = false;
12745
12746         if (tp->fw_ver[0] != 0)
12747                 vpd_vers = true;
12748
12749         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12750                 strcat(tp->fw_ver, "sb");
12751                 return;
12752         }
12753
12754         if (tg3_nvram_read(tp, 0, &val))
12755                 return;
12756
12757         if (val == TG3_EEPROM_MAGIC)
12758                 tg3_read_bc_ver(tp);
12759         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12760                 tg3_read_sb_ver(tp, val);
12761         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12762                 tg3_read_hwsb_ver(tp);
12763         else
12764                 return;
12765
12766         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12767              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
12768                 goto done;
12769
12770         tg3_read_mgmtfw_ver(tp);
12771
12772 done:
12773         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12774 }
12775
12776 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12777
12778 static void inline vlan_features_add(struct net_device *dev, unsigned long flags)
12779 {
12780 #if TG3_VLAN_TAG_USED
12781         dev->vlan_features |= flags;
12782 #endif
12783 }
12784
12785 static int __devinit tg3_get_invariants(struct tg3 *tp)
12786 {
12787         static struct pci_device_id write_reorder_chipsets[] = {
12788                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12789                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12790                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12791                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12792                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12793                              PCI_DEVICE_ID_VIA_8385_0) },
12794                 { },
12795         };
12796         u32 misc_ctrl_reg;
12797         u32 pci_state_reg, grc_misc_cfg;
12798         u32 val;
12799         u16 pci_cmd;
12800         int err;
12801
12802         /* Force memory write invalidate off.  If we leave it on,
12803          * then on 5700_BX chips we have to enable a workaround.
12804          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12805          * to match the cacheline size.  The Broadcom driver have this
12806          * workaround but turns MWI off all the times so never uses
12807          * it.  This seems to suggest that the workaround is insufficient.
12808          */
12809         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12810         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12811         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12812
12813         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12814          * has the register indirect write enable bit set before
12815          * we try to access any of the MMIO registers.  It is also
12816          * critical that the PCI-X hw workaround situation is decided
12817          * before that as well.
12818          */
12819         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12820                               &misc_ctrl_reg);
12821
12822         tp->pci_chip_rev_id = (misc_ctrl_reg >>
12823                                MISC_HOST_CTRL_CHIPREV_SHIFT);
12824         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12825                 u32 prod_id_asic_rev;
12826
12827                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12828                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12829                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724 ||
12830                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719)
12831                         pci_read_config_dword(tp->pdev,
12832                                               TG3PCI_GEN2_PRODID_ASICREV,
12833                                               &prod_id_asic_rev);
12834                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
12835                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
12836                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
12837                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
12838                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
12839                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12840                         pci_read_config_dword(tp->pdev,
12841                                               TG3PCI_GEN15_PRODID_ASICREV,
12842                                               &prod_id_asic_rev);
12843                 else
12844                         pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12845                                               &prod_id_asic_rev);
12846
12847                 tp->pci_chip_rev_id = prod_id_asic_rev;
12848         }
12849
12850         /* Wrong chip ID in 5752 A0. This code can be removed later
12851          * as A0 is not in production.
12852          */
12853         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12854                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12855
12856         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12857          * we need to disable memory and use config. cycles
12858          * only to access all registers. The 5702/03 chips
12859          * can mistakenly decode the special cycles from the
12860          * ICH chipsets as memory write cycles, causing corruption
12861          * of register and memory space. Only certain ICH bridges
12862          * will drive special cycles with non-zero data during the
12863          * address phase which can fall within the 5703's address
12864          * range. This is not an ICH bug as the PCI spec allows
12865          * non-zero address during special cycles. However, only
12866          * these ICH bridges are known to drive non-zero addresses
12867          * during special cycles.
12868          *
12869          * Since special cycles do not cross PCI bridges, we only
12870          * enable this workaround if the 5703 is on the secondary
12871          * bus of these ICH bridges.
12872          */
12873         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12874             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12875                 static struct tg3_dev_id {
12876                         u32     vendor;
12877                         u32     device;
12878                         u32     rev;
12879                 } ich_chipsets[] = {
12880                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12881                           PCI_ANY_ID },
12882                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12883                           PCI_ANY_ID },
12884                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12885                           0xa },
12886                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12887                           PCI_ANY_ID },
12888                         { },
12889                 };
12890                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12891                 struct pci_dev *bridge = NULL;
12892
12893                 while (pci_id->vendor != 0) {
12894                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
12895                                                 bridge);
12896                         if (!bridge) {
12897                                 pci_id++;
12898                                 continue;
12899                         }
12900                         if (pci_id->rev != PCI_ANY_ID) {
12901                                 if (bridge->revision > pci_id->rev)
12902                                         continue;
12903                         }
12904                         if (bridge->subordinate &&
12905                             (bridge->subordinate->number ==
12906                              tp->pdev->bus->number)) {
12907
12908                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12909                                 pci_dev_put(bridge);
12910                                 break;
12911                         }
12912                 }
12913         }
12914
12915         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12916                 static struct tg3_dev_id {
12917                         u32     vendor;
12918                         u32     device;
12919                 } bridge_chipsets[] = {
12920                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12921                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12922                         { },
12923                 };
12924                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12925                 struct pci_dev *bridge = NULL;
12926
12927                 while (pci_id->vendor != 0) {
12928                         bridge = pci_get_device(pci_id->vendor,
12929                                                 pci_id->device,
12930                                                 bridge);
12931                         if (!bridge) {
12932                                 pci_id++;
12933                                 continue;
12934                         }
12935                         if (bridge->subordinate &&
12936                             (bridge->subordinate->number <=
12937                              tp->pdev->bus->number) &&
12938                             (bridge->subordinate->subordinate >=
12939                              tp->pdev->bus->number)) {
12940                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12941                                 pci_dev_put(bridge);
12942                                 break;
12943                         }
12944                 }
12945         }
12946
12947         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12948          * DMA addresses > 40-bit. This bridge may have other additional
12949          * 57xx devices behind it in some 4-port NIC designs for example.
12950          * Any tg3 device found behind the bridge will also need the 40-bit
12951          * DMA workaround.
12952          */
12953         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12954             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12955                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
12956                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12957                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
12958         } else {
12959                 struct pci_dev *bridge = NULL;
12960
12961                 do {
12962                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12963                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
12964                                                 bridge);
12965                         if (bridge && bridge->subordinate &&
12966                             (bridge->subordinate->number <=
12967                              tp->pdev->bus->number) &&
12968                             (bridge->subordinate->subordinate >=
12969                              tp->pdev->bus->number)) {
12970                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12971                                 pci_dev_put(bridge);
12972                                 break;
12973                         }
12974                 } while (bridge);
12975         }
12976
12977         /* Initialize misc host control in PCI block. */
12978         tp->misc_host_ctrl |= (misc_ctrl_reg &
12979                                MISC_HOST_CTRL_CHIPREV);
12980         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12981                                tp->misc_host_ctrl);
12982
12983         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
12984             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
12985             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12986                 tp->pdev_peer = tg3_find_peer(tp);
12987
12988         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
12989             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
12990             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
12991                 tp->tg3_flags3 |= TG3_FLG3_5717_PLUS;
12992
12993         /* Intentionally exclude ASIC_REV_5906 */
12994         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12995             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12996             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12997             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12998             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12999             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13000             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13001                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13002
13003         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13004             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13005             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13006             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13007             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13008                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13009
13010         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13011             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13012                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13013
13014         /* 5700 B0 chips do not support checksumming correctly due
13015          * to hardware bugs.
13016          */
13017         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13018                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13019         else {
13020                 unsigned long features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_GRO;
13021
13022                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13023                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13024                         features |= NETIF_F_IPV6_CSUM;
13025                 tp->dev->features |= features;
13026                 vlan_features_add(tp->dev, features);
13027         }
13028
13029         /* Determine TSO capabilities */
13030         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13031                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13032         else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13033                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13034                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13035         else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13036                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13037                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13038                     tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13039                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13040         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13041                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13042                    tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13043                 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13044                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13045                         tp->fw_needed = FIRMWARE_TG3TSO5;
13046                 else
13047                         tp->fw_needed = FIRMWARE_TG3TSO;
13048         }
13049
13050         tp->irq_max = 1;
13051
13052         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13053                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13054                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13055                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13056                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13057                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13058                      tp->pdev_peer == tp->pdev))
13059                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13060
13061                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13062                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13063                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13064                 }
13065
13066                 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
13067                         tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13068                         tp->irq_max = TG3_IRQ_MAX_VECS;
13069                 }
13070         }
13071
13072         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13073             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13074             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13075                 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13076         else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13077                 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13078                 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13079         }
13080
13081         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13082                 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13083
13084         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13085             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13086             (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13087                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13088
13089         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13090                               &pci_state_reg);
13091
13092         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13093         if (tp->pcie_cap != 0) {
13094                 u16 lnkctl;
13095
13096                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13097
13098                 pcie_set_readrq(tp->pdev, 4096);
13099
13100                 pci_read_config_word(tp->pdev,
13101                                      tp->pcie_cap + PCI_EXP_LNKCTL,
13102                                      &lnkctl);
13103                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13104                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13105                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13106                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13107                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13108                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13109                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13110                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13111                 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13112                         tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13113                 }
13114         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13115                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13116         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13117                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13118                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13119                 if (!tp->pcix_cap) {
13120                         dev_err(&tp->pdev->dev,
13121                                 "Cannot find PCI-X capability, aborting\n");
13122                         return -EIO;
13123                 }
13124
13125                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13126                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13127         }
13128
13129         /* If we have an AMD 762 or VIA K8T800 chipset, write
13130          * reordering to the mailbox registers done by the host
13131          * controller can cause major troubles.  We read back from
13132          * every mailbox register write to force the writes to be
13133          * posted to the chip in order.
13134          */
13135         if (pci_dev_present(write_reorder_chipsets) &&
13136             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13137                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13138
13139         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13140                              &tp->pci_cacheline_sz);
13141         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13142                              &tp->pci_lat_timer);
13143         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13144             tp->pci_lat_timer < 64) {
13145                 tp->pci_lat_timer = 64;
13146                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13147                                       tp->pci_lat_timer);
13148         }
13149
13150         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13151                 /* 5700 BX chips need to have their TX producer index
13152                  * mailboxes written twice to workaround a bug.
13153                  */
13154                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13155
13156                 /* If we are in PCI-X mode, enable register write workaround.
13157                  *
13158                  * The workaround is to use indirect register accesses
13159                  * for all chip writes not to mailbox registers.
13160                  */
13161                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13162                         u32 pm_reg;
13163
13164                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13165
13166                         /* The chip can have it's power management PCI config
13167                          * space registers clobbered due to this bug.
13168                          * So explicitly force the chip into D0 here.
13169                          */
13170                         pci_read_config_dword(tp->pdev,
13171                                               tp->pm_cap + PCI_PM_CTRL,
13172                                               &pm_reg);
13173                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13174                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13175                         pci_write_config_dword(tp->pdev,
13176                                                tp->pm_cap + PCI_PM_CTRL,
13177                                                pm_reg);
13178
13179                         /* Also, force SERR#/PERR# in PCI command. */
13180                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13181                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13182                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13183                 }
13184         }
13185
13186         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13187                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13188         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13189                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13190
13191         /* Chip-specific fixup from Broadcom driver */
13192         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13193             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13194                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13195                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13196         }
13197
13198         /* Default fast path register access methods */
13199         tp->read32 = tg3_read32;
13200         tp->write32 = tg3_write32;
13201         tp->read32_mbox = tg3_read32;
13202         tp->write32_mbox = tg3_write32;
13203         tp->write32_tx_mbox = tg3_write32;
13204         tp->write32_rx_mbox = tg3_write32;
13205
13206         /* Various workaround register access methods */
13207         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13208                 tp->write32 = tg3_write_indirect_reg32;
13209         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13210                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13211                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13212                 /*
13213                  * Back to back register writes can cause problems on these
13214                  * chips, the workaround is to read back all reg writes
13215                  * except those to mailbox regs.
13216                  *
13217                  * See tg3_write_indirect_reg32().
13218                  */
13219                 tp->write32 = tg3_write_flush_reg32;
13220         }
13221
13222         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13223             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13224                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13225                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13226                         tp->write32_rx_mbox = tg3_write_flush_reg32;
13227         }
13228
13229         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13230                 tp->read32 = tg3_read_indirect_reg32;
13231                 tp->write32 = tg3_write_indirect_reg32;
13232                 tp->read32_mbox = tg3_read_indirect_mbox;
13233                 tp->write32_mbox = tg3_write_indirect_mbox;
13234                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13235                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13236
13237                 iounmap(tp->regs);
13238                 tp->regs = NULL;
13239
13240                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13241                 pci_cmd &= ~PCI_COMMAND_MEMORY;
13242                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13243         }
13244         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13245                 tp->read32_mbox = tg3_read32_mbox_5906;
13246                 tp->write32_mbox = tg3_write32_mbox_5906;
13247                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13248                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13249         }
13250
13251         if (tp->write32 == tg3_write_indirect_reg32 ||
13252             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13253              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13254               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13255                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13256
13257         /* Get eeprom hw config before calling tg3_set_power_state().
13258          * In particular, the TG3_FLG2_IS_NIC flag must be
13259          * determined before calling tg3_set_power_state() so that
13260          * we know whether or not to switch out of Vaux power.
13261          * When the flag is set, it means that GPIO1 is used for eeprom
13262          * write protect and also implies that it is a LOM where GPIOs
13263          * are not used to switch power.
13264          */
13265         tg3_get_eeprom_hw_cfg(tp);
13266
13267         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13268                 /* Allow reads and writes to the
13269                  * APE register and memory space.
13270                  */
13271                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13272                                  PCISTATE_ALLOW_APE_SHMEM_WR |
13273                                  PCISTATE_ALLOW_APE_PSPACE_WR;
13274                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13275                                        pci_state_reg);
13276         }
13277
13278         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13279             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13280             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13281             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13282             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13283                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13284
13285         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13286          * GPIO1 driven high will bring 5700's external PHY out of reset.
13287          * It is also used as eeprom write protect on LOMs.
13288          */
13289         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13290         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13291             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13292                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13293                                        GRC_LCLCTRL_GPIO_OUTPUT1);
13294         /* Unused GPIO3 must be driven as output on 5752 because there
13295          * are no pull-up resistors on unused GPIO pins.
13296          */
13297         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13298                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13299
13300         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13301             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13302             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13303                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13304
13305         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13306             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13307                 /* Turn off the debug UART. */
13308                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13309                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13310                         /* Keep VMain power. */
13311                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13312                                               GRC_LCLCTRL_GPIO_OUTPUT0;
13313         }
13314
13315         /* Force the chip into D0. */
13316         err = tg3_set_power_state(tp, PCI_D0);
13317         if (err) {
13318                 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
13319                 return err;
13320         }
13321
13322         /* Derive initial jumbo mode from MTU assigned in
13323          * ether_setup() via the alloc_etherdev() call
13324          */
13325         if (tp->dev->mtu > ETH_DATA_LEN &&
13326             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13327                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13328
13329         /* Determine WakeOnLan speed to use. */
13330         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13331             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13332             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13333             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13334                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13335         } else {
13336                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13337         }
13338
13339         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13340                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
13341
13342         /* A few boards don't want Ethernet@WireSpeed phy feature */
13343         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13344             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13345              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13346              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13347             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
13348             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
13349                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
13350
13351         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13352             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13353                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
13354         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13355                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
13356
13357         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13358             !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
13359             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13360             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13361             !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
13362                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13363                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13364                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13365                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13366                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13367                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13368                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
13369                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13370                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
13371                 } else
13372                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
13373         }
13374
13375         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13376             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13377                 tp->phy_otp = tg3_read_otp_phycfg(tp);
13378                 if (tp->phy_otp == 0)
13379                         tp->phy_otp = TG3_OTP_DEFAULT;
13380         }
13381
13382         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13383                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13384         else
13385                 tp->mi_mode = MAC_MI_MODE_BASE;
13386
13387         tp->coalesce_mode = 0;
13388         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13389             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13390                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13391
13392         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13393             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13394                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13395
13396         err = tg3_mdio_init(tp);
13397         if (err)
13398                 return err;
13399
13400         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
13401             tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
13402                 return -ENOTSUPP;
13403
13404         /* Initialize data/descriptor byte/word swapping. */
13405         val = tr32(GRC_MODE);
13406         val &= GRC_MODE_HOST_STACKUP;
13407         tw32(GRC_MODE, val | tp->grc_mode);
13408
13409         tg3_switch_clocks(tp);
13410
13411         /* Clear this out for sanity. */
13412         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13413
13414         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13415                               &pci_state_reg);
13416         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13417             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13418                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13419
13420                 if (chiprevid == CHIPREV_ID_5701_A0 ||
13421                     chiprevid == CHIPREV_ID_5701_B0 ||
13422                     chiprevid == CHIPREV_ID_5701_B2 ||
13423                     chiprevid == CHIPREV_ID_5701_B5) {
13424                         void __iomem *sram_base;
13425
13426                         /* Write some dummy words into the SRAM status block
13427                          * area, see if it reads back correctly.  If the return
13428                          * value is bad, force enable the PCIX workaround.
13429                          */
13430                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13431
13432                         writel(0x00000000, sram_base);
13433                         writel(0x00000000, sram_base + 4);
13434                         writel(0xffffffff, sram_base + 4);
13435                         if (readl(sram_base) != 0x00000000)
13436                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13437                 }
13438         }
13439
13440         udelay(50);
13441         tg3_nvram_init(tp);
13442
13443         grc_misc_cfg = tr32(GRC_MISC_CFG);
13444         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13445
13446         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13447             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13448              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13449                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13450
13451         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13452             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13453                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13454         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13455                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13456                                       HOSTCC_MODE_CLRTICK_TXBD);
13457
13458                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13459                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13460                                        tp->misc_host_ctrl);
13461         }
13462
13463         /* Preserve the APE MAC_MODE bits */
13464         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13465                 tp->mac_mode = tr32(MAC_MODE) |
13466                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13467         else
13468                 tp->mac_mode = TG3_DEF_MAC_MODE;
13469
13470         /* these are limited to 10/100 only */
13471         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13472              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13473             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13474              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13475              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13476               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13477               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13478             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13479              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13480               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13481               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13482             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13483             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13484             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
13485             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
13486                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13487
13488         err = tg3_phy_probe(tp);
13489         if (err) {
13490                 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
13491                 /* ... but do not return immediately ... */
13492                 tg3_mdio_fini(tp);
13493         }
13494
13495         tg3_read_vpd(tp);
13496         tg3_read_fw_ver(tp);
13497
13498         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13499                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13500         } else {
13501                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13502                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13503                 else
13504                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13505         }
13506
13507         /* 5700 {AX,BX} chips have a broken status block link
13508          * change bit implementation, so we must use the
13509          * status register in those cases.
13510          */
13511         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13512                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13513         else
13514                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13515
13516         /* The led_ctrl is set during tg3_phy_probe, here we might
13517          * have to force the link status polling mechanism based
13518          * upon subsystem IDs.
13519          */
13520         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13521             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13522             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13523                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13524                                   TG3_FLAG_USE_LINKCHG_REG);
13525         }
13526
13527         /* For all SERDES we poll the MAC status register. */
13528         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13529                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13530         else
13531                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13532
13533         tp->rx_offset = NET_IP_ALIGN + TG3_RX_HEADROOM;
13534         tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
13535         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13536             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
13537                 tp->rx_offset -= NET_IP_ALIGN;
13538 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
13539                 tp->rx_copy_thresh = ~(u16)0;
13540 #endif
13541         }
13542
13543         tp->rx_std_max_post = TG3_RX_RING_SIZE;
13544
13545         /* Increment the rx prod index on the rx std ring by at most
13546          * 8 for these chips to workaround hw errata.
13547          */
13548         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13549             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13550             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13551                 tp->rx_std_max_post = 8;
13552
13553         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13554                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13555                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
13556
13557         return err;
13558 }
13559
13560 #ifdef CONFIG_SPARC
13561 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13562 {
13563         struct net_device *dev = tp->dev;
13564         struct pci_dev *pdev = tp->pdev;
13565         struct device_node *dp = pci_device_to_OF_node(pdev);
13566         const unsigned char *addr;
13567         int len;
13568
13569         addr = of_get_property(dp, "local-mac-address", &len);
13570         if (addr && len == 6) {
13571                 memcpy(dev->dev_addr, addr, 6);
13572                 memcpy(dev->perm_addr, dev->dev_addr, 6);
13573                 return 0;
13574         }
13575         return -ENODEV;
13576 }
13577
13578 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13579 {
13580         struct net_device *dev = tp->dev;
13581
13582         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13583         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13584         return 0;
13585 }
13586 #endif
13587
13588 static int __devinit tg3_get_device_address(struct tg3 *tp)
13589 {
13590         struct net_device *dev = tp->dev;
13591         u32 hi, lo, mac_offset;
13592         int addr_ok = 0;
13593
13594 #ifdef CONFIG_SPARC
13595         if (!tg3_get_macaddr_sparc(tp))
13596                 return 0;
13597 #endif
13598
13599         mac_offset = 0x7c;
13600         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13601             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13602                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13603                         mac_offset = 0xcc;
13604                 if (tg3_nvram_lock(tp))
13605                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13606                 else
13607                         tg3_nvram_unlock(tp);
13608         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13609                    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
13610                 if (PCI_FUNC(tp->pdev->devfn) & 1)
13611                         mac_offset = 0xcc;
13612                 if (PCI_FUNC(tp->pdev->devfn) > 1)
13613                         mac_offset += 0x18c;
13614         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13615                 mac_offset = 0x10;
13616
13617         /* First try to get it from MAC address mailbox. */
13618         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13619         if ((hi >> 16) == 0x484b) {
13620                 dev->dev_addr[0] = (hi >>  8) & 0xff;
13621                 dev->dev_addr[1] = (hi >>  0) & 0xff;
13622
13623                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13624                 dev->dev_addr[2] = (lo >> 24) & 0xff;
13625                 dev->dev_addr[3] = (lo >> 16) & 0xff;
13626                 dev->dev_addr[4] = (lo >>  8) & 0xff;
13627                 dev->dev_addr[5] = (lo >>  0) & 0xff;
13628
13629                 /* Some old bootcode may report a 0 MAC address in SRAM */
13630                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13631         }
13632         if (!addr_ok) {
13633                 /* Next, try NVRAM. */
13634                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13635                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13636                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13637                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13638                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13639                 }
13640                 /* Finally just fetch it out of the MAC control regs. */
13641                 else {
13642                         hi = tr32(MAC_ADDR_0_HIGH);
13643                         lo = tr32(MAC_ADDR_0_LOW);
13644
13645                         dev->dev_addr[5] = lo & 0xff;
13646                         dev->dev_addr[4] = (lo >> 8) & 0xff;
13647                         dev->dev_addr[3] = (lo >> 16) & 0xff;
13648                         dev->dev_addr[2] = (lo >> 24) & 0xff;
13649                         dev->dev_addr[1] = hi & 0xff;
13650                         dev->dev_addr[0] = (hi >> 8) & 0xff;
13651                 }
13652         }
13653
13654         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13655 #ifdef CONFIG_SPARC
13656                 if (!tg3_get_default_macaddr_sparc(tp))
13657                         return 0;
13658 #endif
13659                 return -EINVAL;
13660         }
13661         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13662         return 0;
13663 }
13664
13665 #define BOUNDARY_SINGLE_CACHELINE       1
13666 #define BOUNDARY_MULTI_CACHELINE        2
13667
13668 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13669 {
13670         int cacheline_size;
13671         u8 byte;
13672         int goal;
13673
13674         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13675         if (byte == 0)
13676                 cacheline_size = 1024;
13677         else
13678                 cacheline_size = (int) byte * 4;
13679
13680         /* On 5703 and later chips, the boundary bits have no
13681          * effect.
13682          */
13683         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13684             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13685             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13686                 goto out;
13687
13688 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13689         goal = BOUNDARY_MULTI_CACHELINE;
13690 #else
13691 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13692         goal = BOUNDARY_SINGLE_CACHELINE;
13693 #else
13694         goal = 0;
13695 #endif
13696 #endif
13697
13698         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
13699                 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13700                 goto out;
13701         }
13702
13703         if (!goal)
13704                 goto out;
13705
13706         /* PCI controllers on most RISC systems tend to disconnect
13707          * when a device tries to burst across a cache-line boundary.
13708          * Therefore, letting tg3 do so just wastes PCI bandwidth.
13709          *
13710          * Unfortunately, for PCI-E there are only limited
13711          * write-side controls for this, and thus for reads
13712          * we will still get the disconnects.  We'll also waste
13713          * these PCI cycles for both read and write for chips
13714          * other than 5700 and 5701 which do not implement the
13715          * boundary bits.
13716          */
13717         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13718             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13719                 switch (cacheline_size) {
13720                 case 16:
13721                 case 32:
13722                 case 64:
13723                 case 128:
13724                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13725                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13726                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13727                         } else {
13728                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13729                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13730                         }
13731                         break;
13732
13733                 case 256:
13734                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13735                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13736                         break;
13737
13738                 default:
13739                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13740                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13741                         break;
13742                 }
13743         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13744                 switch (cacheline_size) {
13745                 case 16:
13746                 case 32:
13747                 case 64:
13748                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13749                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13750                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13751                                 break;
13752                         }
13753                         /* fallthrough */
13754                 case 128:
13755                 default:
13756                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13757                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13758                         break;
13759                 }
13760         } else {
13761                 switch (cacheline_size) {
13762                 case 16:
13763                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13764                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13765                                         DMA_RWCTRL_WRITE_BNDRY_16);
13766                                 break;
13767                         }
13768                         /* fallthrough */
13769                 case 32:
13770                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13771                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13772                                         DMA_RWCTRL_WRITE_BNDRY_32);
13773                                 break;
13774                         }
13775                         /* fallthrough */
13776                 case 64:
13777                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13778                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13779                                         DMA_RWCTRL_WRITE_BNDRY_64);
13780                                 break;
13781                         }
13782                         /* fallthrough */
13783                 case 128:
13784                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13785                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13786                                         DMA_RWCTRL_WRITE_BNDRY_128);
13787                                 break;
13788                         }
13789                         /* fallthrough */
13790                 case 256:
13791                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
13792                                 DMA_RWCTRL_WRITE_BNDRY_256);
13793                         break;
13794                 case 512:
13795                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
13796                                 DMA_RWCTRL_WRITE_BNDRY_512);
13797                         break;
13798                 case 1024:
13799                 default:
13800                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13801                                 DMA_RWCTRL_WRITE_BNDRY_1024);
13802                         break;
13803                 }
13804         }
13805
13806 out:
13807         return val;
13808 }
13809
13810 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13811 {
13812         struct tg3_internal_buffer_desc test_desc;
13813         u32 sram_dma_descs;
13814         int i, ret;
13815
13816         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13817
13818         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13819         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13820         tw32(RDMAC_STATUS, 0);
13821         tw32(WDMAC_STATUS, 0);
13822
13823         tw32(BUFMGR_MODE, 0);
13824         tw32(FTQ_RESET, 0);
13825
13826         test_desc.addr_hi = ((u64) buf_dma) >> 32;
13827         test_desc.addr_lo = buf_dma & 0xffffffff;
13828         test_desc.nic_mbuf = 0x00002100;
13829         test_desc.len = size;
13830
13831         /*
13832          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13833          * the *second* time the tg3 driver was getting loaded after an
13834          * initial scan.
13835          *
13836          * Broadcom tells me:
13837          *   ...the DMA engine is connected to the GRC block and a DMA
13838          *   reset may affect the GRC block in some unpredictable way...
13839          *   The behavior of resets to individual blocks has not been tested.
13840          *
13841          * Broadcom noted the GRC reset will also reset all sub-components.
13842          */
13843         if (to_device) {
13844                 test_desc.cqid_sqid = (13 << 8) | 2;
13845
13846                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13847                 udelay(40);
13848         } else {
13849                 test_desc.cqid_sqid = (16 << 8) | 7;
13850
13851                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13852                 udelay(40);
13853         }
13854         test_desc.flags = 0x00000005;
13855
13856         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13857                 u32 val;
13858
13859                 val = *(((u32 *)&test_desc) + i);
13860                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13861                                        sram_dma_descs + (i * sizeof(u32)));
13862                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13863         }
13864         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13865
13866         if (to_device)
13867                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13868         else
13869                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13870
13871         ret = -ENODEV;
13872         for (i = 0; i < 40; i++) {
13873                 u32 val;
13874
13875                 if (to_device)
13876                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13877                 else
13878                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13879                 if ((val & 0xffff) == sram_dma_descs) {
13880                         ret = 0;
13881                         break;
13882                 }
13883
13884                 udelay(100);
13885         }
13886
13887         return ret;
13888 }
13889
13890 #define TEST_BUFFER_SIZE        0x2000
13891
13892 static int __devinit tg3_test_dma(struct tg3 *tp)
13893 {
13894         dma_addr_t buf_dma;
13895         u32 *buf, saved_dma_rwctrl;
13896         int ret = 0;
13897
13898         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13899         if (!buf) {
13900                 ret = -ENOMEM;
13901                 goto out_nofree;
13902         }
13903
13904         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13905                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13906
13907         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13908
13909         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13910                 goto out;
13911
13912         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13913                 /* DMA read watermark not used on PCIE */
13914                 tp->dma_rwctrl |= 0x00180000;
13915         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
13916                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13917                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
13918                         tp->dma_rwctrl |= 0x003f0000;
13919                 else
13920                         tp->dma_rwctrl |= 0x003f000f;
13921         } else {
13922                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13923                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13924                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
13925                         u32 read_water = 0x7;
13926
13927                         /* If the 5704 is behind the EPB bridge, we can
13928                          * do the less restrictive ONE_DMA workaround for
13929                          * better performance.
13930                          */
13931                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13932                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13933                                 tp->dma_rwctrl |= 0x8000;
13934                         else if (ccval == 0x6 || ccval == 0x7)
13935                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13936
13937                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13938                                 read_water = 4;
13939                         /* Set bit 23 to enable PCIX hw bug fix */
13940                         tp->dma_rwctrl |=
13941                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13942                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13943                                 (1 << 23);
13944                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13945                         /* 5780 always in PCIX mode */
13946                         tp->dma_rwctrl |= 0x00144000;
13947                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13948                         /* 5714 always in PCIX mode */
13949                         tp->dma_rwctrl |= 0x00148000;
13950                 } else {
13951                         tp->dma_rwctrl |= 0x001b000f;
13952                 }
13953         }
13954
13955         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13956             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13957                 tp->dma_rwctrl &= 0xfffffff0;
13958
13959         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13960             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13961                 /* Remove this if it causes problems for some boards. */
13962                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13963
13964                 /* On 5700/5701 chips, we need to set this bit.
13965                  * Otherwise the chip will issue cacheline transactions
13966                  * to streamable DMA memory with not all the byte
13967                  * enables turned on.  This is an error on several
13968                  * RISC PCI controllers, in particular sparc64.
13969                  *
13970                  * On 5703/5704 chips, this bit has been reassigned
13971                  * a different meaning.  In particular, it is used
13972                  * on those chips to enable a PCI-X workaround.
13973                  */
13974                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13975         }
13976
13977         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13978
13979 #if 0
13980         /* Unneeded, already done by tg3_get_invariants.  */
13981         tg3_switch_clocks(tp);
13982 #endif
13983
13984         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13985             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13986                 goto out;
13987
13988         /* It is best to perform DMA test with maximum write burst size
13989          * to expose the 5700/5701 write DMA bug.
13990          */
13991         saved_dma_rwctrl = tp->dma_rwctrl;
13992         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13993         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13994
13995         while (1) {
13996                 u32 *p = buf, i;
13997
13998                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13999                         p[i] = i;
14000
14001                 /* Send the buffer to the chip. */
14002                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14003                 if (ret) {
14004                         dev_err(&tp->pdev->dev,
14005                                 "%s: Buffer write failed. err = %d\n",
14006                                 __func__, ret);
14007                         break;
14008                 }
14009
14010 #if 0
14011                 /* validate data reached card RAM correctly. */
14012                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14013                         u32 val;
14014                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
14015                         if (le32_to_cpu(val) != p[i]) {
14016                                 dev_err(&tp->pdev->dev,
14017                                         "%s: Buffer corrupted on device! "
14018                                         "(%d != %d)\n", __func__, val, i);
14019                                 /* ret = -ENODEV here? */
14020                         }
14021                         p[i] = 0;
14022                 }
14023 #endif
14024                 /* Now read it back. */
14025                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14026                 if (ret) {
14027                         dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
14028                                 "err = %d\n", __func__, ret);
14029                         break;
14030                 }
14031
14032                 /* Verify it. */
14033                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14034                         if (p[i] == i)
14035                                 continue;
14036
14037                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14038                             DMA_RWCTRL_WRITE_BNDRY_16) {
14039                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14040                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14041                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14042                                 break;
14043                         } else {
14044                                 dev_err(&tp->pdev->dev,
14045                                         "%s: Buffer corrupted on read back! "
14046                                         "(%d != %d)\n", __func__, p[i], i);
14047                                 ret = -ENODEV;
14048                                 goto out;
14049                         }
14050                 }
14051
14052                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14053                         /* Success. */
14054                         ret = 0;
14055                         break;
14056                 }
14057         }
14058         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14059             DMA_RWCTRL_WRITE_BNDRY_16) {
14060                 static struct pci_device_id dma_wait_state_chipsets[] = {
14061                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14062                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14063                         { },
14064                 };
14065
14066                 /* DMA test passed without adjusting DMA boundary,
14067                  * now look for chipsets that are known to expose the
14068                  * DMA bug without failing the test.
14069                  */
14070                 if (pci_dev_present(dma_wait_state_chipsets)) {
14071                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14072                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14073                 } else {
14074                         /* Safe to use the calculated DMA boundary. */
14075                         tp->dma_rwctrl = saved_dma_rwctrl;
14076                 }
14077
14078                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14079         }
14080
14081 out:
14082         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14083 out_nofree:
14084         return ret;
14085 }
14086
14087 static void __devinit tg3_init_link_config(struct tg3 *tp)
14088 {
14089         tp->link_config.advertising =
14090                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14091                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14092                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14093                  ADVERTISED_Autoneg | ADVERTISED_MII);
14094         tp->link_config.speed = SPEED_INVALID;
14095         tp->link_config.duplex = DUPLEX_INVALID;
14096         tp->link_config.autoneg = AUTONEG_ENABLE;
14097         tp->link_config.active_speed = SPEED_INVALID;
14098         tp->link_config.active_duplex = DUPLEX_INVALID;
14099         tp->link_config.phy_is_low_power = 0;
14100         tp->link_config.orig_speed = SPEED_INVALID;
14101         tp->link_config.orig_duplex = DUPLEX_INVALID;
14102         tp->link_config.orig_autoneg = AUTONEG_INVALID;
14103 }
14104
14105 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14106 {
14107         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
14108                 tp->bufmgr_config.mbuf_read_dma_low_water =
14109                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14110                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14111                         DEFAULT_MB_MACRX_LOW_WATER_57765;
14112                 tp->bufmgr_config.mbuf_high_water =
14113                         DEFAULT_MB_HIGH_WATER_57765;
14114
14115                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14116                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14117                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14118                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14119                 tp->bufmgr_config.mbuf_high_water_jumbo =
14120                         DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14121         } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14122                 tp->bufmgr_config.mbuf_read_dma_low_water =
14123                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14124                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14125                         DEFAULT_MB_MACRX_LOW_WATER_5705;
14126                 tp->bufmgr_config.mbuf_high_water =
14127                         DEFAULT_MB_HIGH_WATER_5705;
14128                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14129                         tp->bufmgr_config.mbuf_mac_rx_low_water =
14130                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
14131                         tp->bufmgr_config.mbuf_high_water =
14132                                 DEFAULT_MB_HIGH_WATER_5906;
14133                 }
14134
14135                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14136                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14137                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14138                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14139                 tp->bufmgr_config.mbuf_high_water_jumbo =
14140                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14141         } else {
14142                 tp->bufmgr_config.mbuf_read_dma_low_water =
14143                         DEFAULT_MB_RDMA_LOW_WATER;
14144                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14145                         DEFAULT_MB_MACRX_LOW_WATER;
14146                 tp->bufmgr_config.mbuf_high_water =
14147                         DEFAULT_MB_HIGH_WATER;
14148
14149                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14150                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14151                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14152                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14153                 tp->bufmgr_config.mbuf_high_water_jumbo =
14154                         DEFAULT_MB_HIGH_WATER_JUMBO;
14155         }
14156
14157         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14158         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14159 }
14160
14161 static char * __devinit tg3_phy_string(struct tg3 *tp)
14162 {
14163         switch (tp->phy_id & TG3_PHY_ID_MASK) {
14164         case TG3_PHY_ID_BCM5400:        return "5400";
14165         case TG3_PHY_ID_BCM5401:        return "5401";
14166         case TG3_PHY_ID_BCM5411:        return "5411";
14167         case TG3_PHY_ID_BCM5701:        return "5701";
14168         case TG3_PHY_ID_BCM5703:        return "5703";
14169         case TG3_PHY_ID_BCM5704:        return "5704";
14170         case TG3_PHY_ID_BCM5705:        return "5705";
14171         case TG3_PHY_ID_BCM5750:        return "5750";
14172         case TG3_PHY_ID_BCM5752:        return "5752";
14173         case TG3_PHY_ID_BCM5714:        return "5714";
14174         case TG3_PHY_ID_BCM5780:        return "5780";
14175         case TG3_PHY_ID_BCM5755:        return "5755";
14176         case TG3_PHY_ID_BCM5787:        return "5787";
14177         case TG3_PHY_ID_BCM5784:        return "5784";
14178         case TG3_PHY_ID_BCM5756:        return "5722/5756";
14179         case TG3_PHY_ID_BCM5906:        return "5906";
14180         case TG3_PHY_ID_BCM5761:        return "5761";
14181         case TG3_PHY_ID_BCM5718C:       return "5718C";
14182         case TG3_PHY_ID_BCM5718S:       return "5718S";
14183         case TG3_PHY_ID_BCM57765:       return "57765";
14184         case TG3_PHY_ID_BCM5719C:       return "5719C";
14185         case TG3_PHY_ID_BCM8002:        return "8002/serdes";
14186         case 0:                 return "serdes";
14187         default:                return "unknown";
14188         }
14189 }
14190
14191 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14192 {
14193         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14194                 strcpy(str, "PCI Express");
14195                 return str;
14196         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14197                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14198
14199                 strcpy(str, "PCIX:");
14200
14201                 if ((clock_ctrl == 7) ||
14202                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14203                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14204                         strcat(str, "133MHz");
14205                 else if (clock_ctrl == 0)
14206                         strcat(str, "33MHz");
14207                 else if (clock_ctrl == 2)
14208                         strcat(str, "50MHz");
14209                 else if (clock_ctrl == 4)
14210                         strcat(str, "66MHz");
14211                 else if (clock_ctrl == 6)
14212                         strcat(str, "100MHz");
14213         } else {
14214                 strcpy(str, "PCI:");
14215                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14216                         strcat(str, "66MHz");
14217                 else
14218                         strcat(str, "33MHz");
14219         }
14220         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14221                 strcat(str, ":32-bit");
14222         else
14223                 strcat(str, ":64-bit");
14224         return str;
14225 }
14226
14227 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14228 {
14229         struct pci_dev *peer;
14230         unsigned int func, devnr = tp->pdev->devfn & ~7;
14231
14232         for (func = 0; func < 8; func++) {
14233                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14234                 if (peer && peer != tp->pdev)
14235                         break;
14236                 pci_dev_put(peer);
14237         }
14238         /* 5704 can be configured in single-port mode, set peer to
14239          * tp->pdev in that case.
14240          */
14241         if (!peer) {
14242                 peer = tp->pdev;
14243                 return peer;
14244         }
14245
14246         /*
14247          * We don't need to keep the refcount elevated; there's no way
14248          * to remove one half of this device without removing the other
14249          */
14250         pci_dev_put(peer);
14251
14252         return peer;
14253 }
14254
14255 static void __devinit tg3_init_coal(struct tg3 *tp)
14256 {
14257         struct ethtool_coalesce *ec = &tp->coal;
14258
14259         memset(ec, 0, sizeof(*ec));
14260         ec->cmd = ETHTOOL_GCOALESCE;
14261         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14262         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14263         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14264         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14265         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14266         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14267         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14268         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14269         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14270
14271         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14272                                  HOSTCC_MODE_CLRTICK_TXBD)) {
14273                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14274                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14275                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14276                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14277         }
14278
14279         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14280                 ec->rx_coalesce_usecs_irq = 0;
14281                 ec->tx_coalesce_usecs_irq = 0;
14282                 ec->stats_block_coalesce_usecs = 0;
14283         }
14284 }
14285
14286 static const struct net_device_ops tg3_netdev_ops = {
14287         .ndo_open               = tg3_open,
14288         .ndo_stop               = tg3_close,
14289         .ndo_start_xmit         = tg3_start_xmit,
14290         .ndo_get_stats64        = tg3_get_stats64,
14291         .ndo_validate_addr      = eth_validate_addr,
14292         .ndo_set_multicast_list = tg3_set_rx_mode,
14293         .ndo_set_mac_address    = tg3_set_mac_addr,
14294         .ndo_do_ioctl           = tg3_ioctl,
14295         .ndo_tx_timeout         = tg3_tx_timeout,
14296         .ndo_change_mtu         = tg3_change_mtu,
14297 #if TG3_VLAN_TAG_USED
14298         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14299 #endif
14300 #ifdef CONFIG_NET_POLL_CONTROLLER
14301         .ndo_poll_controller    = tg3_poll_controller,
14302 #endif
14303 };
14304
14305 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14306         .ndo_open               = tg3_open,
14307         .ndo_stop               = tg3_close,
14308         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
14309         .ndo_get_stats64        = tg3_get_stats64,
14310         .ndo_validate_addr      = eth_validate_addr,
14311         .ndo_set_multicast_list = tg3_set_rx_mode,
14312         .ndo_set_mac_address    = tg3_set_mac_addr,
14313         .ndo_do_ioctl           = tg3_ioctl,
14314         .ndo_tx_timeout         = tg3_tx_timeout,
14315         .ndo_change_mtu         = tg3_change_mtu,
14316 #if TG3_VLAN_TAG_USED
14317         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14318 #endif
14319 #ifdef CONFIG_NET_POLL_CONTROLLER
14320         .ndo_poll_controller    = tg3_poll_controller,
14321 #endif
14322 };
14323
14324 static int __devinit tg3_init_one(struct pci_dev *pdev,
14325                                   const struct pci_device_id *ent)
14326 {
14327         struct net_device *dev;
14328         struct tg3 *tp;
14329         int i, err, pm_cap;
14330         u32 sndmbx, rcvmbx, intmbx;
14331         char str[40];
14332         u64 dma_mask, persist_dma_mask;
14333
14334         printk_once(KERN_INFO "%s\n", version);
14335
14336         err = pci_enable_device(pdev);
14337         if (err) {
14338                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
14339                 return err;
14340         }
14341
14342         err = pci_request_regions(pdev, DRV_MODULE_NAME);
14343         if (err) {
14344                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
14345                 goto err_out_disable_pdev;
14346         }
14347
14348         pci_set_master(pdev);
14349
14350         /* Find power-management capability. */
14351         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14352         if (pm_cap == 0) {
14353                 dev_err(&pdev->dev,
14354                         "Cannot find Power Management capability, aborting\n");
14355                 err = -EIO;
14356                 goto err_out_free_res;
14357         }
14358
14359         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14360         if (!dev) {
14361                 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
14362                 err = -ENOMEM;
14363                 goto err_out_free_res;
14364         }
14365
14366         SET_NETDEV_DEV(dev, &pdev->dev);
14367
14368 #if TG3_VLAN_TAG_USED
14369         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14370 #endif
14371
14372         tp = netdev_priv(dev);
14373         tp->pdev = pdev;
14374         tp->dev = dev;
14375         tp->pm_cap = pm_cap;
14376         tp->rx_mode = TG3_DEF_RX_MODE;
14377         tp->tx_mode = TG3_DEF_TX_MODE;
14378
14379         if (tg3_debug > 0)
14380                 tp->msg_enable = tg3_debug;
14381         else
14382                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14383
14384         /* The word/byte swap controls here control register access byte
14385          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
14386          * setting below.
14387          */
14388         tp->misc_host_ctrl =
14389                 MISC_HOST_CTRL_MASK_PCI_INT |
14390                 MISC_HOST_CTRL_WORD_SWAP |
14391                 MISC_HOST_CTRL_INDIR_ACCESS |
14392                 MISC_HOST_CTRL_PCISTATE_RW;
14393
14394         /* The NONFRM (non-frame) byte/word swap controls take effect
14395          * on descriptor entries, anything which isn't packet data.
14396          *
14397          * The StrongARM chips on the board (one for tx, one for rx)
14398          * are running in big-endian mode.
14399          */
14400         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14401                         GRC_MODE_WSWAP_NONFRM_DATA);
14402 #ifdef __BIG_ENDIAN
14403         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14404 #endif
14405         spin_lock_init(&tp->lock);
14406         spin_lock_init(&tp->indirect_lock);
14407         INIT_WORK(&tp->reset_task, tg3_reset_task);
14408
14409         tp->regs = pci_ioremap_bar(pdev, BAR_0);
14410         if (!tp->regs) {
14411                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
14412                 err = -ENOMEM;
14413                 goto err_out_free_dev;
14414         }
14415
14416         tg3_init_link_config(tp);
14417
14418         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14419         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14420
14421         dev->ethtool_ops = &tg3_ethtool_ops;
14422         dev->watchdog_timeo = TG3_TX_TIMEOUT;
14423         dev->irq = pdev->irq;
14424
14425         err = tg3_get_invariants(tp);
14426         if (err) {
14427                 dev_err(&pdev->dev,
14428                         "Problem fetching invariants of chip, aborting\n");
14429                 goto err_out_iounmap;
14430         }
14431
14432         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14433             tp->pci_chip_rev_id != CHIPREV_ID_5717_A0 &&
14434             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
14435                 dev->netdev_ops = &tg3_netdev_ops;
14436         else
14437                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14438
14439
14440         /* The EPB bridge inside 5714, 5715, and 5780 and any
14441          * device behind the EPB cannot support DMA addresses > 40-bit.
14442          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14443          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14444          * do DMA address check in tg3_start_xmit().
14445          */
14446         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14447                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14448         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14449                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14450 #ifdef CONFIG_HIGHMEM
14451                 dma_mask = DMA_BIT_MASK(64);
14452 #endif
14453         } else
14454                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14455
14456         /* Configure DMA attributes. */
14457         if (dma_mask > DMA_BIT_MASK(32)) {
14458                 err = pci_set_dma_mask(pdev, dma_mask);
14459                 if (!err) {
14460                         dev->features |= NETIF_F_HIGHDMA;
14461                         err = pci_set_consistent_dma_mask(pdev,
14462                                                           persist_dma_mask);
14463                         if (err < 0) {
14464                                 dev_err(&pdev->dev, "Unable to obtain 64 bit "
14465                                         "DMA for consistent allocations\n");
14466                                 goto err_out_iounmap;
14467                         }
14468                 }
14469         }
14470         if (err || dma_mask == DMA_BIT_MASK(32)) {
14471                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14472                 if (err) {
14473                         dev_err(&pdev->dev,
14474                                 "No usable DMA configuration, aborting\n");
14475                         goto err_out_iounmap;
14476                 }
14477         }
14478
14479         tg3_init_bufmgr_config(tp);
14480
14481         /* Selectively allow TSO based on operating conditions */
14482         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14483             (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14484                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14485         else {
14486                 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14487                 tp->fw_needed = NULL;
14488         }
14489
14490         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14491                 tp->fw_needed = FIRMWARE_TG3;
14492
14493         /* TSO is on by default on chips that support hardware TSO.
14494          * Firmware TSO on older chips gives lower performance, so it
14495          * is off by default, but can be enabled using ethtool.
14496          */
14497         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14498             (dev->features & NETIF_F_IP_CSUM)) {
14499                 dev->features |= NETIF_F_TSO;
14500                 vlan_features_add(dev, NETIF_F_TSO);
14501         }
14502         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14503             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14504                 if (dev->features & NETIF_F_IPV6_CSUM) {
14505                         dev->features |= NETIF_F_TSO6;
14506                         vlan_features_add(dev, NETIF_F_TSO6);
14507                 }
14508                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14509                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14510                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14511                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14512                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14513                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
14514                         dev->features |= NETIF_F_TSO_ECN;
14515                         vlan_features_add(dev, NETIF_F_TSO_ECN);
14516                 }
14517         }
14518
14519         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14520             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14521             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14522                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14523                 tp->rx_pending = 63;
14524         }
14525
14526         err = tg3_get_device_address(tp);
14527         if (err) {
14528                 dev_err(&pdev->dev,
14529                         "Could not obtain valid ethernet address, aborting\n");
14530                 goto err_out_iounmap;
14531         }
14532
14533         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14534                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14535                 if (!tp->aperegs) {
14536                         dev_err(&pdev->dev,
14537                                 "Cannot map APE registers, aborting\n");
14538                         err = -ENOMEM;
14539                         goto err_out_iounmap;
14540                 }
14541
14542                 tg3_ape_lock_init(tp);
14543
14544                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14545                         tg3_read_dash_ver(tp);
14546         }
14547
14548         /*
14549          * Reset chip in case UNDI or EFI driver did not shutdown
14550          * DMA self test will enable WDMAC and we'll see (spurious)
14551          * pending DMA on the PCI bus at that point.
14552          */
14553         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14554             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14555                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14556                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14557         }
14558
14559         err = tg3_test_dma(tp);
14560         if (err) {
14561                 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
14562                 goto err_out_apeunmap;
14563         }
14564
14565         /* flow control autonegotiation is default behavior */
14566         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14567         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14568
14569         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14570         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14571         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14572         for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14573                 struct tg3_napi *tnapi = &tp->napi[i];
14574
14575                 tnapi->tp = tp;
14576                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14577
14578                 tnapi->int_mbox = intmbx;
14579                 if (i < 4)
14580                         intmbx += 0x8;
14581                 else
14582                         intmbx += 0x4;
14583
14584                 tnapi->consmbox = rcvmbx;
14585                 tnapi->prodmbox = sndmbx;
14586
14587                 if (i) {
14588                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14589                         netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14590                 } else {
14591                         tnapi->coal_now = HOSTCC_MODE_NOW;
14592                         netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14593                 }
14594
14595                 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14596                         break;
14597
14598                 /*
14599                  * If we support MSIX, we'll be using RSS.  If we're using
14600                  * RSS, the first vector only handles link interrupts and the
14601                  * remaining vectors handle rx and tx interrupts.  Reuse the
14602                  * mailbox values for the next iteration.  The values we setup
14603                  * above are still useful for the single vectored mode.
14604                  */
14605                 if (!i)
14606                         continue;
14607
14608                 rcvmbx += 0x8;
14609
14610                 if (sndmbx & 0x4)
14611                         sndmbx -= 0x4;
14612                 else
14613                         sndmbx += 0xc;
14614         }
14615
14616         tg3_init_coal(tp);
14617
14618         pci_set_drvdata(pdev, dev);
14619
14620         err = register_netdev(dev);
14621         if (err) {
14622                 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
14623                 goto err_out_apeunmap;
14624         }
14625
14626         netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14627                     tp->board_part_number,
14628                     tp->pci_chip_rev_id,
14629                     tg3_bus_string(tp, str),
14630                     dev->dev_addr);
14631
14632         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14633                 struct phy_device *phydev;
14634                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14635                 netdev_info(dev,
14636                             "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14637                             phydev->drv->name, dev_name(&phydev->dev));
14638         } else
14639                 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
14640                             "(WireSpeed[%d])\n", tg3_phy_string(tp),
14641                             ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14642                              ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14643                               "10/100/1000Base-T")),
14644                             (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14645
14646         netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14647                     (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14648                     (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14649                     (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14650                     (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14651                     (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14652         netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14653                     tp->dma_rwctrl,
14654                     pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
14655                     ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
14656
14657         return 0;
14658
14659 err_out_apeunmap:
14660         if (tp->aperegs) {
14661                 iounmap(tp->aperegs);
14662                 tp->aperegs = NULL;
14663         }
14664
14665 err_out_iounmap:
14666         if (tp->regs) {
14667                 iounmap(tp->regs);
14668                 tp->regs = NULL;
14669         }
14670
14671 err_out_free_dev:
14672         free_netdev(dev);
14673
14674 err_out_free_res:
14675         pci_release_regions(pdev);
14676
14677 err_out_disable_pdev:
14678         pci_disable_device(pdev);
14679         pci_set_drvdata(pdev, NULL);
14680         return err;
14681 }
14682
14683 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14684 {
14685         struct net_device *dev = pci_get_drvdata(pdev);
14686
14687         if (dev) {
14688                 struct tg3 *tp = netdev_priv(dev);
14689
14690                 if (tp->fw)
14691                         release_firmware(tp->fw);
14692
14693                 flush_scheduled_work();
14694
14695                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14696                         tg3_phy_fini(tp);
14697                         tg3_mdio_fini(tp);
14698                 }
14699
14700                 unregister_netdev(dev);
14701                 if (tp->aperegs) {
14702                         iounmap(tp->aperegs);
14703                         tp->aperegs = NULL;
14704                 }
14705                 if (tp->regs) {
14706                         iounmap(tp->regs);
14707                         tp->regs = NULL;
14708                 }
14709                 free_netdev(dev);
14710                 pci_release_regions(pdev);
14711                 pci_disable_device(pdev);
14712                 pci_set_drvdata(pdev, NULL);
14713         }
14714 }
14715
14716 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14717 {
14718         struct net_device *dev = pci_get_drvdata(pdev);
14719         struct tg3 *tp = netdev_priv(dev);
14720         pci_power_t target_state;
14721         int err;
14722
14723         /* PCI register 4 needs to be saved whether netif_running() or not.
14724          * MSI address and data need to be saved if using MSI and
14725          * netif_running().
14726          */
14727         pci_save_state(pdev);
14728
14729         if (!netif_running(dev))
14730                 return 0;
14731
14732         flush_scheduled_work();
14733         tg3_phy_stop(tp);
14734         tg3_netif_stop(tp);
14735
14736         del_timer_sync(&tp->timer);
14737
14738         tg3_full_lock(tp, 1);
14739         tg3_disable_ints(tp);
14740         tg3_full_unlock(tp);
14741
14742         netif_device_detach(dev);
14743
14744         tg3_full_lock(tp, 0);
14745         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14746         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14747         tg3_full_unlock(tp);
14748
14749         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14750
14751         err = tg3_set_power_state(tp, target_state);
14752         if (err) {
14753                 int err2;
14754
14755                 tg3_full_lock(tp, 0);
14756
14757                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14758                 err2 = tg3_restart_hw(tp, 1);
14759                 if (err2)
14760                         goto out;
14761
14762                 tp->timer.expires = jiffies + tp->timer_offset;
14763                 add_timer(&tp->timer);
14764
14765                 netif_device_attach(dev);
14766                 tg3_netif_start(tp);
14767
14768 out:
14769                 tg3_full_unlock(tp);
14770
14771                 if (!err2)
14772                         tg3_phy_start(tp);
14773         }
14774
14775         return err;
14776 }
14777
14778 static int tg3_resume(struct pci_dev *pdev)
14779 {
14780         struct net_device *dev = pci_get_drvdata(pdev);
14781         struct tg3 *tp = netdev_priv(dev);
14782         int err;
14783
14784         pci_restore_state(tp->pdev);
14785
14786         if (!netif_running(dev))
14787                 return 0;
14788
14789         err = tg3_set_power_state(tp, PCI_D0);
14790         if (err)
14791                 return err;
14792
14793         netif_device_attach(dev);
14794
14795         tg3_full_lock(tp, 0);
14796
14797         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14798         err = tg3_restart_hw(tp, 1);
14799         if (err)
14800                 goto out;
14801
14802         tp->timer.expires = jiffies + tp->timer_offset;
14803         add_timer(&tp->timer);
14804
14805         tg3_netif_start(tp);
14806
14807 out:
14808         tg3_full_unlock(tp);
14809
14810         if (!err)
14811                 tg3_phy_start(tp);
14812
14813         return err;
14814 }
14815
14816 static struct pci_driver tg3_driver = {
14817         .name           = DRV_MODULE_NAME,
14818         .id_table       = tg3_pci_tbl,
14819         .probe          = tg3_init_one,
14820         .remove         = __devexit_p(tg3_remove_one),
14821         .suspend        = tg3_suspend,
14822         .resume         = tg3_resume
14823 };
14824
14825 static int __init tg3_init(void)
14826 {
14827         return pci_register_driver(&tg3_driver);
14828 }
14829
14830 static void __exit tg3_cleanup(void)
14831 {
14832         pci_unregister_driver(&tg3_driver);
14833 }
14834
14835 module_init(tg3_init);
14836 module_exit(tg3_cleanup);